OpenCores
URL https://opencores.org/ocsvn/spacewiresystemc/spacewiresystemc/trunk

Subversion Repositories spacewiresystemc

[/] [spacewiresystemc/] [trunk/] [altera_work/] [spw_fifo_ulight/] [simulation/] [modelsim/] [spw_fifo_ulight.vo] - Rev 40

Compare with Previous | Blame | View Log

// Copyright (C) 2017  Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Intel Program License 
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel MegaCore Function License Agreement, or other 
// applicable license agreement, including, without limitation, 
// that your use is for the sole purpose of programming logic 
// devices manufactured by Intel and sold by Intel or its 
// authorized distributors.  Please refer to the applicable 
// agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus Prime"
// VERSION "Version 17.0.2 Build 602 07/19/2017 SJ Lite Edition"

// DATE "11/10/2017 11:13:11"

// 
// Device: Altera 5CSEMA4U23C6 Package UFBGA672
// 

// 
// This Verilog file should be used for ModelSim-Altera (Verilog) only
// 

`timescale 1 ps/ 1 ps

module SPW_ULIGHT_FIFO (
        \sout_a(n) ,
        \dout_a(n) ,
        \din_a(n) ,
        \sin_a(n) ,
        FPGA_CLK1_50,
        KEY,
        din_a,
        sin_a,
        dout_a,
        sout_a,
        LED);
output  \sout_a(n) ;
output  \dout_a(n) ;
input   \din_a(n) ;
input   \sin_a(n) ;
input   FPGA_CLK1_50;
input   [1:0] KEY;
input   din_a;
input   sin_a;
output  dout_a;
output  sout_a;
output  [7:0] LED;

// Design Ports Information
// sout_a       =>  Location: PIN_AF20,  I/O Standard: LVDS,     Current Strength: Default
// LED[5]       =>  Location: PIN_AE26,  I/O Standard: 3.3-V LVTTL,      Current Strength: 16mA
// LED[7]       =>  Location: PIN_AA23,  I/O Standard: 3.3-V LVTTL,      Current Strength: 16mA
// dout_a       =>  Location: PIN_AG28,  I/O Standard: LVDS,     Current Strength: Default
// LED[0]       =>  Location: PIN_W15,   I/O Standard: 3.3-V LVTTL,      Current Strength: 16mA
// LED[1]       =>  Location: PIN_AA24,  I/O Standard: 3.3-V LVTTL,      Current Strength: 16mA
// LED[2]       =>  Location: PIN_V16,   I/O Standard: 3.3-V LVTTL,      Current Strength: 16mA
// LED[3]       =>  Location: PIN_V15,   I/O Standard: 3.3-V LVTTL,      Current Strength: 16mA
// LED[4]       =>  Location: PIN_AF26,  I/O Standard: 3.3-V LVTTL,      Current Strength: 16mA
// KEY[0]       =>  Location: PIN_AH17,  I/O Standard: 3.3-V LVTTL,      Current Strength: Default
// LED[6]       =>  Location: PIN_Y16,   I/O Standard: 3.3-V LVTTL,      Current Strength: 16mA
// FPGA_CLK1_50 =>  Location: PIN_Y13,   I/O Standard: 3.3-V LVTTL,      Current Strength: Default
// KEY[1]       =>  Location: PIN_AH16,  I/O Standard: 3.3-V LVTTL,      Current Strength: Default
// din_a        =>  Location: PIN_Y15,   I/O Standard: LVDS,     Current Strength: Default
// sin_a        =>  Location: PIN_AE20,  I/O Standard: LVDS,     Current Strength: Default
// sout_a(n)    =>  Location: PIN_AG20,  I/O Standard: LVDS,     Current Strength: Default
// dout_a(n)    =>  Location: PIN_AH27,  I/O Standard: LVDS,     Current Strength: Default
// din_a(n)     =>  Location: PIN_AA15,  I/O Standard: LVDS,     Current Strength: Default
// sin_a(n)     =>  Location: PIN_AD20,  I/O Standard: LVDS,     Current Strength: Default


wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
assign unknown = 1'bx;

tri1 devclrn;
tri1 devpor;
tri1 devoe;
wire \u0|hps_0|fpga_interfaces|fpga2hps~arready ;
wire \u0|hps_0|fpga_interfaces|f2sdram~O_BONDING_OUT_10 ;
wire \u0|hps_0|fpga_interfaces|f2sdram~O_BONDING_OUT_11 ;
wire \u0|hps_0|fpga_interfaces|f2sdram~O_BONDING_OUT_12 ;
wire \u0|hps_0|fpga_interfaces|f2sdram~O_BONDING_OUT_13 ;
wire \u0|hps_0|fpga_interfaces|tpiu~trace_data ;
wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA1 ;
wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA2 ;
wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA3 ;
wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA4 ;
wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA5 ;
wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA6 ;
wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA7 ;
wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA8 ;
wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA9 ;
wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA10 ;
wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA11 ;
wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA12 ;
wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA13 ;
wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA14 ;
wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA15 ;
wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA16 ;
wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA17 ;
wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA18 ;
wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA19 ;
wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA20 ;
wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA21 ;
wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA22 ;
wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA23 ;
wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA24 ;
wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA25 ;
wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA26 ;
wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA27 ;
wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA28 ;
wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA29 ;
wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA30 ;
wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA31 ;
wire \u0|hps_0|fpga_interfaces|boot_from_fpga~fake_dout ;
wire \u0|hps_0|fpga_interfaces|debug_apb~O_P_ADDR_31 ;
wire \u0|hps_0|fpga_interfaces|clocks_resets~h2f_cold_rst_n ;
wire \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|clk0bad ;
wire \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|blockselect ;
wire \KEY[0]~input_o ;
wire \~QUARTUS_CREATED_GND~I_combout ;
wire \FPGA_CLK1_50~input_o ;
wire \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|refclk_select_extswitchbuf_wire ;
wire \FPGA_CLK1_50~inputCLKENA0_outclk ;
wire \KEY[1]~input_o ;
wire \db_system_spwulight_b|Add0~61_sumout ;
wire \db_system_spwulight_b|counter~15_combout ;
wire \db_system_spwulight_b|Add0~62 ;
wire \db_system_spwulight_b|Add0~57_sumout ;
wire \db_system_spwulight_b|counter~14_combout ;
wire \db_system_spwulight_b|Add0~58 ;
wire \db_system_spwulight_b|Add0~53_sumout ;
wire \db_system_spwulight_b|counter~13_combout ;
wire \db_system_spwulight_b|Add0~54 ;
wire \db_system_spwulight_b|Add0~49_sumout ;
wire \db_system_spwulight_b|counter~12_combout ;
wire \db_system_spwulight_b|Add0~50 ;
wire \db_system_spwulight_b|Add0~38 ;
wire \db_system_spwulight_b|Add0~41_sumout ;
wire \db_system_spwulight_b|counter~10_combout ;
wire \db_system_spwulight_b|Add0~42 ;
wire \db_system_spwulight_b|Add0~45_sumout ;
wire \db_system_spwulight_b|counter~11_combout ;
wire \db_system_spwulight_b|Add0~46 ;
wire \db_system_spwulight_b|Add0~29_sumout ;
wire \db_system_spwulight_b|counter~7_combout ;
wire \db_system_spwulight_b|Add0~30 ;
wire \db_system_spwulight_b|Add0~33_sumout ;
wire \db_system_spwulight_b|counter~8_combout ;
wire \db_system_spwulight_b|Add0~34 ;
wire \db_system_spwulight_b|Add0~9_sumout ;
wire \db_system_spwulight_b|counter~2_combout ;
wire \db_system_spwulight_b|Add0~10 ;
wire \db_system_spwulight_b|Add0~13_sumout ;
wire \db_system_spwulight_b|counter~3_combout ;
wire \db_system_spwulight_b|Add0~14 ;
wire \db_system_spwulight_b|Add0~17_sumout ;
wire \db_system_spwulight_b|counter~4_combout ;
wire \db_system_spwulight_b|Add0~18 ;
wire \db_system_spwulight_b|Add0~21_sumout ;
wire \db_system_spwulight_b|counter~5_combout ;
wire \db_system_spwulight_b|Add0~22 ;
wire \db_system_spwulight_b|Add0~25_sumout ;
wire \db_system_spwulight_b|counter~6_combout ;
wire \db_system_spwulight_b|Add0~26 ;
wire \db_system_spwulight_b|Add0~1_sumout ;
wire \db_system_spwulight_b|counter~0_combout ;
wire \db_system_spwulight_b|LessThan0~0_combout ;
wire \db_system_spwulight_b|LessThan0~2_combout ;
wire \db_system_spwulight_b|Add0~37_sumout ;
wire \db_system_spwulight_b|counter~9_combout ;
wire \db_system_spwulight_b|LessThan0~1_combout ;
wire \db_system_spwulight_b|Add0~2 ;
wire \db_system_spwulight_b|Add0~5_sumout ;
wire \db_system_spwulight_b|counter~1_combout ;
wire \db_system_spwulight_b|aux_pb~0_combout ;
wire \db_system_spwulight_b|aux_pb~q ;
wire \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|refclk_select_clkout_wire ;
wire \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|pll_reconfig_up_wire ;
wire \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|pll_reconfig_shiftenm_wire ;
wire \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|shift ;
wire \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|cntnen ;
wire \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|tclk ;
wire \u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ;
wire \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock ;
wire \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter~2_combout ;
wire \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder_combout ;
wire \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ;
wire \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ;
wire \u0|mm_interconnect_0|write_en_tx_s1_translator|waitrequest_reset_override~feeder_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_translator|waitrequest_reset_override~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override~feeder_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override~feeder_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override~q ;
wire \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~2_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override~feeder_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override~q ;
wire \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg~1_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][110]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][69]~q ;
wire \u0|mm_interconnect_0|cmd_mux|packet_in_progress~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux|packet_in_progress~q ;
wire \u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~feeder_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~4_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg~1_combout ;
wire \u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add1~6 ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add1~29_sumout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter_100~8_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add1~30 ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add1~33_sumout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter_100~9_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add1~34 ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add1~37_sumout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter_100~10_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add1~38 ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add1~41_sumout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter_100~11_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|LessThan16~0_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add1~42 ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add1~13_sumout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter_100~4_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add1~14 ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add1~17_sumout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter_100~5_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add1~18 ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add1~21_sumout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter_100~6_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add1~22 ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add1~25_sumout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter_100~7_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|LessThan16~1_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add1~9_sumout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter_100~3_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter_100~0_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add1~10 ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add1~1_sumout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter_100~1_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add1~2 ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add1~5_sumout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter_100~2_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~0_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ;
wire \A_SPW_TOP|tx_data|counter_writer[0]~0_combout ;
wire \A_SPW_TOP|tx_data|Add1~1_combout ;
wire \A_SPW_TOP|tx_data|Add1~2_combout ;
wire \A_SPW_TOP|tx_data|Add1~3_combout ;
wire \A_SPW_TOP|tx_data|counter_reader[0]~0_combout ;
wire \sin_a~input_o ;
wire \din_a~input_o ;
wire \A_SPW_TOP|SPW|RX|always3~0_combout ;
wire \A_SPW_TOP|SPW|RX|counter_neg[0]~feeder_combout ;
wire \A_SPW_TOP|SPW|RX|always2~0_combout ;
wire \A_SPW_TOP|SPW|RX|ready_data_p~combout ;
wire \A_SPW_TOP|SPW|RX|ready_data~combout ;
wire \A_SPW_TOP|SPW|RX|bit_d_1~feeder_combout ;
wire \A_SPW_TOP|SPW|RX|bit_d_1~q ;
wire \A_SPW_TOP|SPW|RX|bit_d_3~feeder_combout ;
wire \A_SPW_TOP|SPW|RX|bit_d_3~q ;
wire \A_SPW_TOP|SPW|RX|bit_d_5~q ;
wire \A_SPW_TOP|SPW|RX|bit_d_7~q ;
wire \A_SPW_TOP|SPW|RX|bit_d_9~feeder_combout ;
wire \A_SPW_TOP|SPW|RX|bit_d_9~q ;
wire \A_SPW_TOP|SPW|RX|parity_rec_d~feeder_combout ;
wire \A_SPW_TOP|SPW|RX|parity_rec_d~q ;
wire \A_SPW_TOP|SPW|RX|bit_d_0~q ;
wire \A_SPW_TOP|SPW|RX|bit_d_2~q ;
wire \A_SPW_TOP|SPW|RX|bit_d_4~q ;
wire \A_SPW_TOP|SPW|RX|bit_d_6~feeder_combout ;
wire \A_SPW_TOP|SPW|RX|bit_d_6~q ;
wire \A_SPW_TOP|SPW|RX|bit_d_8~feeder_combout ;
wire \A_SPW_TOP|SPW|RX|bit_d_8~q ;
wire \A_SPW_TOP|SPW|RX|dta_timec[8]~feeder_combout ;
wire \A_SPW_TOP|SPW|RX|always15~0_combout ;
wire \A_SPW_TOP|SPW|RX|control_bit_found~q ;
wire \A_SPW_TOP|SPW|RX|Selector0~1_combout ;
wire \A_SPW_TOP|SPW|RX|Selector0~3_combout ;
wire \A_SPW_TOP|SPW|RX|is_control~q ;
wire \A_SPW_TOP|SPW|RX|ready_data_p_r~0_combout ;
wire \A_SPW_TOP|SPW|RX|ready_data_p_r~q ;
wire \A_SPW_TOP|SPW|RX|last_is_control~0_combout ;
wire \A_SPW_TOP|SPW|RX|next_state_data_process.01~0_combout ;
wire \A_SPW_TOP|SPW|RX|state_data_process.01~feeder_combout ;
wire \A_SPW_TOP|SPW|RX|state_data_process.01~q ;
wire \A_SPW_TOP|SPW|RX|last_is_control~q ;
wire \A_SPW_TOP|SPW|RX|rx_error_c~0_combout ;
wire \A_SPW_TOP|SPW|RX|bit_c_1~q ;
wire \A_SPW_TOP|SPW|RX|control_r[1]~feeder_combout ;
wire \A_SPW_TOP|SPW|RX|control~1_combout ;
wire \A_SPW_TOP|SPW|RX|bit_c_0~q ;
wire \A_SPW_TOP|SPW|RX|control~2_combout ;
wire \A_SPW_TOP|SPW|RX|rx_error_d~0_combout ;
wire \A_SPW_TOP|SPW|RX|dta_timec[3]~feeder_combout ;
wire \A_SPW_TOP|SPW|RX|bit_c_2~q ;
wire \A_SPW_TOP|SPW|RX|control~0_combout ;
wire \A_SPW_TOP|SPW|RX|control[2]~feeder_combout ;
wire \A_SPW_TOP|SPW|RX|data~0_combout ;
wire \A_SPW_TOP|SPW|RX|data~5_combout ;
wire \A_SPW_TOP|SPW|RX|dta_timec[6]~feeder_combout ;
wire \A_SPW_TOP|SPW|RX|dta_timec_p[6]~feeder_combout ;
wire \A_SPW_TOP|SPW|RX|data~2_combout ;
wire \A_SPW_TOP|SPW|RX|dta_timec[2]~feeder_combout ;
wire \A_SPW_TOP|SPW|RX|data~6_combout ;
wire \A_SPW_TOP|SPW|RX|dta_timec[7]~feeder_combout ;
wire \A_SPW_TOP|SPW|RX|data~1_combout ;
wire \A_SPW_TOP|SPW|RX|dta_timec[4]~feeder_combout ;
wire \A_SPW_TOP|SPW|RX|data~4_combout ;
wire \A_SPW_TOP|SPW|RX|dta_timec[5]~feeder_combout ;
wire \A_SPW_TOP|SPW|RX|dta_timec_p[5]~feeder_combout ;
wire \A_SPW_TOP|SPW|RX|data~3_combout ;
wire \A_SPW_TOP|SPW|RX|always16~0_combout ;
wire \A_SPW_TOP|SPW|RX|dta_timec[0]~feeder_combout ;
wire \A_SPW_TOP|SPW|RX|dta_timec_p[0]~feeder_combout ;
wire \A_SPW_TOP|SPW|RX|data~8_combout ;
wire \A_SPW_TOP|SPW|RX|dta_timec[1]~feeder_combout ;
wire \A_SPW_TOP|SPW|RX|dta_timec_p[1]~feeder_combout ;
wire \A_SPW_TOP|SPW|RX|data~7_combout ;
wire \A_SPW_TOP|SPW|RX|always16~1_combout ;
wire \A_SPW_TOP|SPW|RX|rx_error_d~1_combout ;
wire \A_SPW_TOP|SPW|RX|rx_error_d~q ;
wire \A_SPW_TOP|SPW|RX|bit_c_3~q ;
wire \A_SPW_TOP|SPW|RX|parity_rec_c~q ;
wire \A_SPW_TOP|SPW|RX|always16~2_combout ;
wire \A_SPW_TOP|SPW|RX|rx_error_c~1_combout ;
wire \A_SPW_TOP|SPW|RX|rx_error_c~2_combout ;
wire \A_SPW_TOP|SPW|RX|rx_error_c~q ;
wire \A_SPW_TOP|SPW|RX|last_is_timec~0_combout ;
wire \A_SPW_TOP|SPW|RX|last_is_timec~q ;
wire \A_SPW_TOP|SPW|RX|rx_got_null~0_combout ;
wire \A_SPW_TOP|SPW|RX|rx_got_null~q ;
wire \u0|mm_interconnect_0|router|Equal20~0_combout ;
wire \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder_combout ;
wire \u0|hps_0|fpga_interfaces|h2f_rst_n[0]~CLKENA0_outclk ;
wire \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][5]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter~2_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~4_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~1_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][6]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][129]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_busy~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][75]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~6_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][74]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~5_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][76]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~7_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][76]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][78]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~9_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][78]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][77]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~8_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][77]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~2_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~1_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~1_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~1_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~2_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|comb~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][66]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~3_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][66]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][129]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|read~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|read~1_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used[0]~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][9]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout ;
wire \A_SPW_TOP|SPW|FSM|enable_tx~0_combout ;
wire \A_SPW_TOP|SPW|FSM|enable_tx~q ;
wire \A_SPW_TOP|tx_data|Add2~0_combout ;
wire \A_SPW_TOP|tx_data|Add2~1_combout ;
wire \A_SPW_TOP|tx_data|Add3~2 ;
wire \A_SPW_TOP|tx_data|Add3~3 ;
wire \A_SPW_TOP|tx_data|Add3~6 ;
wire \A_SPW_TOP|tx_data|Add3~7 ;
wire \A_SPW_TOP|tx_data|Add3~9_sumout ;
wire \A_SPW_TOP|tx_data|Add3~1_sumout ;
wire \A_SPW_TOP|tx_data|Add3~10 ;
wire \A_SPW_TOP|tx_data|Add3~11 ;
wire \A_SPW_TOP|tx_data|Add3~13_sumout ;
wire \A_SPW_TOP|tx_data|Add1~4_combout ;
wire \A_SPW_TOP|tx_data|Add2~4_combout ;
wire \A_SPW_TOP|tx_data|Add3~14 ;
wire \A_SPW_TOP|tx_data|Add3~15 ;
wire \A_SPW_TOP|tx_data|Add3~18 ;
wire \A_SPW_TOP|tx_data|Add3~19 ;
wire \A_SPW_TOP|tx_data|Add3~21_sumout ;
wire \A_SPW_TOP|tx_data|LessThan0~0_combout ;
wire \A_SPW_TOP|tx_data|f_empty~q ;
wire \A_SPW_TOP|tx_data|state_data_read~10_combout ;
wire \A_SPW_TOP|tx_data|state_data_read.01~q ;
wire \A_SPW_TOP|tx_data|state_data_read.00~0_combout ;
wire \A_SPW_TOP|tx_data|state_data_read~11_combout ;
wire \A_SPW_TOP|tx_data|state_data_read.00~feeder_combout ;
wire \A_SPW_TOP|tx_data|state_data_read.00~q ;
wire \A_SPW_TOP|tx_data|write_tx~q ;
wire \A_SPW_TOP|SPW|TX|LessThan3~0_combout ;
wire \m_x|control_bit_found~q ;
wire \m_x|counter_neg[0]~feeder_combout ;
wire \m_x|Selector2~0_combout ;
wire \m_x|Selector2~1_combout ;
wire \m_x|WideOr7~0_combout ;
wire \m_x|Selector3~0_combout ;
wire \m_x|Selector3~1_combout ;
wire \m_x|Selector1~0_combout ;
wire \m_x|Selector1~1_combout ;
wire \m_x|Selector5~0_combout ;
wire \m_x|Selector0~1_combout ;
wire \m_x|Selector5~1_combout ;
wire \m_x|Selector0~0_combout ;
wire \m_x|Selector4~0_combout ;
wire \m_x|Selector0~2_combout ;
wire \m_x|Selector0~3_combout ;
wire \m_x|is_control~q ;
wire \m_x|always1~0_combout ;
wire \m_x|always2~0_combout ;
wire \m_x|ready_control_p_r~0_combout ;
wire \m_x|ready_control_p_r~q ;
wire \m_x|bit_c_1~feeder_combout ;
wire \m_x|bit_c_1~q ;
wire \m_x|control_p_r[1]~feeder_combout ;
wire \m_x|control~1_combout ;
wire \m_x|ready_data~combout ;
wire \m_x|ready_data_p~combout ;
wire \m_x|ready_data_p_r~0_combout ;
wire \m_x|ready_data_p_r~q ;
wire \m_x|next_state_data_process.01~0_combout ;
wire \m_x|state_data_process.01~q ;
wire \m_x|control_l_r~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~13_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;
wire \u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override~feeder_combout ;
wire \u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|write~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_busy~q ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][75]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~6_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][75]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][78]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~3_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][78]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][76]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~5_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][76]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][77]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~4_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][77]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][74]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~7_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][74]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~1_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~2_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~1_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~1_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~2_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][66]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~2_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][66]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[0]~1_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][129]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~1_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][129]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent|comb~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[1]~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~1_combout ;
wire \m_x|bit_c_0~q ;
wire \m_x|bit_c_2~q ;
wire \m_x|control_r[2]~feeder_combout ;
wire \m_x|control~2_combout ;
wire \m_x|control_l_r~2_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|read~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[1]~1_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][12]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~12_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][12]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~32_combout ;
wire \m_x|bit_c_3~q ;
wire \m_x|control_r[3]~feeder_combout ;
wire \m_x|control~3_combout ;
wire \m_x|control_l_r~3_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][13]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~13_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][13]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~33_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_busy~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override~feeder_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;
wire \u0|mm_interconnect_0|router_001|Equal2~2_combout ;
wire \u0|mm_interconnect_0|router_001|Equal2~1_combout ;
wire \u0|mm_interconnect_0|router_001|Equal1~3_combout ;
wire \u0|mm_interconnect_0|router_001|src_data[102]~0_combout ;
wire \u0|mm_interconnect_0|router_001|src_data[100]~1_combout ;
wire \u0|mm_interconnect_0|router_001|src_data[101]~2_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~0_combout ;
wire \u0|mm_interconnect_0|router_001|src_data[103]~3_combout ;
wire \u0|mm_interconnect_0|router_001|src_data[104]~4_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~1_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_016|last_cycle~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;
wire \u0|mm_interconnect_0|router_001|Equal9~0_combout ;
wire \u0|mm_interconnect_0|router_001|Equal9~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override~feeder_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][129]~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ;
wire \u0|mm_interconnect_0|router_001|Equal1~4_combout ;
wire \u0|mm_interconnect_0|router_001|Equal15~0_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|src9_valid~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_009|src_valid~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_009|packet_in_progress~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_009|packet_in_progress~q ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~2_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override~feeder_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;
wire \u0|mm_interconnect_0|cmd_mux_009|src_valid~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent|local_write~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~4_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent|m0_read~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|write~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][69]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~1_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][78]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~9_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][78]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][77]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~8_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][77]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][74]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~5_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][74]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][76]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~7_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][76]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][75]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~6_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][75]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_busy~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg~1_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][129]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][129]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|read~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|read~1_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[1]~1_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[0]~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent|comb~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~2_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~2_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~1_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~1_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~1_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][66]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~3_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][66]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[0]~1_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][69]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][68]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~2_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][68]~q ;
wire \u0|mm_interconnect_0|rsp_demux_009|src0_valid~0_combout ;
wire \u0|mm_interconnect_0|rsp_demux_009|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[1]~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent|m0_write~combout ;
wire \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~1_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~1_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_011|src_valid~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_011|packet_in_progress~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_011|packet_in_progress~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;
wire \u0|mm_interconnect_0|router_001|Equal17~0_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|src11_valid~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_011|src_valid~1_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][110]~q ;
wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~5_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~14_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][110]~feeder_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][110]~q ;
wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~5_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][110]~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~14_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][110]~q ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;
wire \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~2_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent|m0_read~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent|m0_write~combout ;
wire \u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~feeder_combout ;
wire \u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~q ;
wire \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~1_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;
wire \u0|mm_interconnect_0|router_001|Equal19~0_combout ;
wire \u0|mm_interconnect_0|router_001|Equal19~1_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[13]~feeder_combout ;
wire \u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;
wire \u0|mm_interconnect_0|cmd_mux_015|src_valid~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;
wire \u0|mm_interconnect_0|router_001|Equal12~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_021|last_cycle~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4]~feeder_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~1_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5]~feeder_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~2_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~3_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent|rp_valid~combout ;
wire \u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][116]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~21_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_busy~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][74]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~5_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][74]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][78]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~9_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][78]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][75]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~6_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][75]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][77]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~8_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][77]~feeder_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][77]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][76]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~7_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][76]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~2_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~1_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~1_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~1_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~2_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][116]~q ;
wire \u0|mm_interconnect_0|router_001|Equal20~0_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|src14_valid~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;
wire \u0|mm_interconnect_0|cmd_demux_001|src14_valid~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_014|src_valid~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~feeder_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_write~combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~3_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_read~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|write~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][129]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][66]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~3_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66]~feeder_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][68]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][68]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][69]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][69]~feeder_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][69]~q ;
wire \u0|mm_interconnect_0|rsp_demux_014|src0_valid~0_combout ;
wire \u0|mm_interconnect_0|rsp_demux_014|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[0]~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][129]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|comb~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][74]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~5_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][76]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~7_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][76]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][75]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~6_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][75]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][78]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~9_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][78]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][77]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~8_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][77]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_busy~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[1]~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add6~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~2_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~1_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~5_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~6_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Equal0~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_014|packet_in_progress~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_014|packet_in_progress~q ;
wire \u0|mm_interconnect_0|cmd_mux_014|update_grant~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~2_combout ;
wire \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_014|arb|grant[1]~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_014|saved_grant[1]~feeder_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][116]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~21_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][116]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|rp_valid~combout ;
wire \u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~201_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][116]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~21_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][116]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][116]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~21_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][116]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~200_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override~feeder_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][129]~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~1_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][77]~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~4_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][77]~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][74]~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~7_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][75]~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~6_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][78]~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~3_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][78]~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][76]~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~5_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][76]~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~2_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~1_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][66]~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~2_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][66]~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][129]~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|read~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[1]~1_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[0]~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|comb~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[0]~1_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override~feeder_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~1_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~2_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~3_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|write~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][129]~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~1_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][129]~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|comb~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][76]~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~5_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][76]~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][75]~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~6_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][77]~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~4_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][77]~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][74]~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~7_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][78]~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~3_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][78]~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~2_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~1_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~1_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][66]~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~2_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][66]~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[1]~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[0]~1_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][116]~q ;
wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~11_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~20_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][116]~feeder_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][116]~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][116]~q ;
wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~11_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~20_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][116]~q ;
wire \u0|mm_interconnect_0|router_001|Equal14~0_combout ;
wire \u0|mm_interconnect_0|router_001|Equal14~1_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|src8_valid~0_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|src8_valid~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_008|arb|grant[1]~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;
wire \u0|mm_interconnect_0|router|Equal14~1_combout ;
wire \u0|mm_interconnect_0|cmd_demux|src8_valid~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_008|src_valid~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~2_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~3_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_008|packet_in_progress~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_008|packet_in_progress~q ;
wire \u0|mm_interconnect_0|cmd_mux_008|update_grant~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][66]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~3_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66]~feeder_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent|m0_read~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][129]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][129]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent|comb~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][74]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~5_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_busy~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~2_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][77]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~8_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][75]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~6_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][76]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~7_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][78]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~9_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][78]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~1_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~2_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~1_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~1_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[0]~1_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][68]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~2_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][68]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][69]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~1_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][69]~q ;
wire \u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ;
wire \u0|mm_interconnect_0|router_001|Equal7~0_combout ;
wire \u0|mm_interconnect_0|router_001|Equal8~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override~feeder_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~1_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~2_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|write~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][75]~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~6_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~feeder_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][129]~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~1_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][129]~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|read~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[1]~1_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[0]~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent|comb~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[0]~1_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][78]~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~3_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][78]~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][77]~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~4_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][77]~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][74]~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~7_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][76]~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~5_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76]~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_busy~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~2_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~2_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~1_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~1_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~1_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][66]~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~2_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][66]~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[1]~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~2_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Equal0~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ;
wire \u0|mm_interconnect_0|cmd_mux_019|packet_in_progress~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_019|packet_in_progress~q ;
wire \u0|mm_interconnect_0|cmd_mux_019|update_grant~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~11_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][116]~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~20_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][116]~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~198_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~199_combout ;
wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~11_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][116]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~20_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][116]~q ;
wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~11_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][116]~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~20_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][116]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][66]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~3_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~4_combout ;
wire \u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg~1_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~1_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[1]~1_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[0]~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent|comb~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][66]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][69]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~1_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][69]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][68]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~2_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][68]~q ;
wire \u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~11_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][116]~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override~feeder_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][74]~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~7_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|write~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][129]~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][129]~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|read~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[1]~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[0]~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|comb~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[0]~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][75]~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~6_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][77]~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~4_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][77]~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][76]~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~5_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][76]~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][78]~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~3_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][78]~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~2_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][66]~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~2_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][66]~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[1]~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~20_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][116]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][116]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~21_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][116]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~196_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~197_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][116]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ;
wire \u0|mm_interconnect_0|cmd_mux_018|src_valid~1_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~2_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~3_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent|local_write~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~1_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][75]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~6_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][75]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][76]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~7_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][76]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][74]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~5_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][74]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][78]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~9_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][78]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][77]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~8_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][77]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~1_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~2_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~1_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~1_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_busy~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][66]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~3_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][66]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|write~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used[1]~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~21_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][116]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][116]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~21_combout ;
wire \u0|mm_interconnect_0|rsp_demux_015|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~4_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][129]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_read~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][129]~feeder_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][129]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|read~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|read~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[1]~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[0]~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|comb~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|always0~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|write~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used[0]~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][116]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|rp_valid~combout ;
wire \u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~202_combout ;
wire \u0|mm_interconnect_0|router_001|Equal18~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~2_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override~feeder_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|write~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[0]~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][129]~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][129]~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|read~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[1]~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[0]~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|comb~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][76]~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~5_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][76]~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][75]~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~6_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][74]~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~7_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][77]~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~4_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][77]~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~2_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][78]~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~3_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][78]~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][66]~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~2_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][66]~feeder_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][66]~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[1]~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ;
wire \u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~q ;
wire \u0|mm_interconnect_0|cmd_mux_012|update_grant~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~11_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][116]~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~20_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][116]~feeder_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][116]~q ;
wire \u0|mm_interconnect_0|router_001|Equal1~5_combout ;
wire \u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override~feeder_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~1_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~2_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ;
wire \u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~q ;
wire \u0|mm_interconnect_0|cmd_mux_001|update_grant~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][129]~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~1_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][129]~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|read~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[1]~1_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[0]~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent|comb~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_busy~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][77]~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~5_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][77]~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][76]~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~6_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][76]~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][74]~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~8_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74]~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][75]~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~7_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75]~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~1_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][78]~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~4_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][78]~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~1_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~3_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~2_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~1_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][66]~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~3_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][66]~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[1]~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|write~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[0]~1_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][116]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;
wire \u0|mm_interconnect_0|cmd_mux|src_valid~0_combout ;
wire \u0|mm_interconnect_0|router|src_data[103]~0_combout ;
wire \u0|mm_interconnect_0|router|Equal6~7_combout ;
wire \u0|mm_interconnect_0|cmd_demux|src0_valid~0_combout ;
wire \u0|mm_interconnect_0|cmd_demux|src0_valid~1_combout ;
wire \u0|mm_interconnect_0|cmd_demux|src0_valid~2_combout ;
wire \u0|mm_interconnect_0|cmd_demux|src0_valid~3_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~21_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter~2_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_translator|waitrequest_reset_override~feeder_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_translator|waitrequest_reset_override~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent|m0_read~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent|local_write~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent|m0_write~combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter~1_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~4_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|write~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][77]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~8_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][77]~feeder_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][77]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][75]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~6_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][75]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][76]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~7_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][76]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_busy~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][78]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~9_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][78]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][74]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~5_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][74]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add1~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~2_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add1~1_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~2_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~1_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~1_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][66]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~3_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][66]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg~1_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][129]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][129]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|read~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|read~1_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used[1]~1_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used[0]~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent|comb~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used[0]~1_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][116]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ;
wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~11_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][116]~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~20_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][116]~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|waitrequest_reset_override~feeder_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|waitrequest_reset_override~q ;
wire \u0|mm_interconnect_0|router_001|Equal3~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_002|last_cycle~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~1_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~2_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][129]~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~1_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][78]~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~3_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][78]~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][75]~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~6_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][75]~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][77]~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~4_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][77]~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][74]~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~7_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74]~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][76]~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~5_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][76]~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~1_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_busy~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~2_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~2_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~1_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~1_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][66]~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~2_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][66]~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|comb~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|write~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[0]~1_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[1]~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ;
wire \u0|mm_interconnect_0|cmd_mux_002|packet_in_progress~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_002|packet_in_progress~q ;
wire \u0|mm_interconnect_0|cmd_mux_002|update_grant~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|read~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[1]~1_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[0]~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~11_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][116]~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~20_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][116]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~56_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~203_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][129]~q ;
wire \u0|mm_interconnect_0|cmd_mux_003|last_cycle~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_translator|waitrequest_reset_override~feeder_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_translator|waitrequest_reset_override~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~1_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~2_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ;
wire \u0|mm_interconnect_0|cmd_mux_003|packet_in_progress~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_003|packet_in_progress~q ;
wire \u0|mm_interconnect_0|cmd_mux_003|update_grant~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~1_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|write~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][66]~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~2_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][66]~feeder_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][66]~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][77]~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~4_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][77]~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][78]~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~3_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][78]~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_busy~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][75]~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~6_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][75]~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][74]~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~7_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][74]~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][76]~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~5_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][76]~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add1~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~2_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~2_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add1~1_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~1_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~1_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used[0]~1_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][129]~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|read~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used[1]~1_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used[0]~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|comb~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|always0~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used[1]~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout ;
wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~11_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][116]~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~20_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][116]~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|waitrequest_reset_override~feeder_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|waitrequest_reset_override~q ;
wire \u0|mm_interconnect_0|router_001|Equal11~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~2_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][74]~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~7_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|write~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][129]~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|read~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[1]~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[0]~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|comb~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[0]~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][75]~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~6_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][75]~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][76]~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~5_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][76]~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][78]~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~3_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][78]~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][77]~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~4_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][77]~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~2_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_busy~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][66]~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~2_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][66]~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[1]~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ;
wire \u0|mm_interconnect_0|cmd_mux_006|packet_in_progress~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_006|packet_in_progress~q ;
wire \u0|mm_interconnect_0|cmd_mux_006|update_grant~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~11_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][116]~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~20_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][116]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~57_combout ;
wire \u0|mm_interconnect_0|router_001|Equal7~1_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|src4_valid~0_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|src4_valid~1_combout ;
wire \u0|mm_interconnect_0|router|Equal7~2_combout ;
wire \u0|mm_interconnect_0|router|Equal7~3_combout ;
wire \u0|mm_interconnect_0|cmd_demux|src4_valid~0_combout ;
wire \u0|mm_interconnect_0|cmd_demux|src4_valid~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_004|src_valid~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_004|arb|grant[1]~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_004|src_valid~1_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_read~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][129]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][129]~feeder_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~feeder_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter~2_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~4_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|write~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][75]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~6_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][75]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][74]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~5_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][74]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][78]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~9_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][78]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_busy~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~2_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][76]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~7_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][76]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][77]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~8_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][77]~feeder_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][77]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add1~1_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~2_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~1_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add1~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~1_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][66]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~3_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][66]~feeder_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][66]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used[0]~1_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][129]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg~1_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg[0]~feeder_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~1_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[1]~1_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[0]~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|comb~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|always0~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used[1]~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_write~combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter~1_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~2_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~3_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~1_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_004|packet_in_progress~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_004|packet_in_progress~q ;
wire \u0|mm_interconnect_0|cmd_mux_004|update_grant~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_004|arb|grant[0]~1_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][68]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~2_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][68]~feeder_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][68]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][69]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~1_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][69]~feeder_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][69]~q ;
wire \u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][116]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~21_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][116]~q ;
wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~11_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][116]~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~20_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][116]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~204_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~205_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][115]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~20_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][115]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][115]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~20_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][115]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~190_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][115]~q ;
wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~10_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~19_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][115]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][115]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~20_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][115]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~188_combout ;
wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~10_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][115]~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~19_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][115]~feeder_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][115]~q ;
wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~10_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][115]~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~19_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][115]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~189_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][115]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~20_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][115]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][115]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~20_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][115]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~192_combout ;
wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~10_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][115]~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~19_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][115]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~54_combout ;
wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~10_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][115]~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~19_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][115]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][115]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~20_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][115]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~193_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][115]~q ;
wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~10_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~19_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][115]~q ;
wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~10_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][115]~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~19_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][115]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][115]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~20_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][115]~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][115]~q ;
wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~10_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~19_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][115]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~55_combout ;
wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~10_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][115]~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~19_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][115]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~194_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~195_combout ;
wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~10_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][115]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~19_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][115]~feeder_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][115]~q ;
wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~10_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][115]~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~19_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][115]~q ;
wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~10_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][115]~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~19_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][115]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][115]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~20_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][115]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~186_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~187_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][115]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~20_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][115]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][115]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~20_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][115]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~191_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][114]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~19_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][114]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][114]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~19_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][114]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~180_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][114]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~19_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][114]~q ;
wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~9_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][114]~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~18_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][114]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~176_combout ;
wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~9_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][114]~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~18_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][114]~q ;
wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~9_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][114]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~18_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][114]~feeder_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][114]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~177_combout ;
wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~9_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][114]~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~18_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][114]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~53_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][114]~q ;
wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~9_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~18_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][114]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][114]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~19_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][114]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~184_combout ;
wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~9_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][114]~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~18_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][114]~feeder_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][114]~q ;
wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~9_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][114]~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~18_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][114]~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][114]~q ;
wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~9_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~18_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][114]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~52_combout ;
wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~9_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][114]~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~18_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][114]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][114]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~19_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][114]~feeder_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][114]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~183_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~185_combout ;
wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~9_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][114]~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~18_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][114]~q ;
wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~9_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][114]~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~18_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][114]~q ;
wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~9_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][114]~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~18_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][114]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][114]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~19_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][114]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~178_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~179_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][114]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~19_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][114]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][114]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~19_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][114]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~181_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][114]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~19_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][114]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][114]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~19_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][114]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~182_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ;
wire \u0|mm_interconnect_0|cmd_mux_021|packet_in_progress~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_021|packet_in_progress~q ;
wire \u0|mm_interconnect_0|cmd_mux_021|update_grant~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|write~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[1]~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][113]~q ;
wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~8_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~17_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][113]~feeder_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][113]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][113]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~18_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][113]~q ;
wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~8_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][113]~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~17_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][113]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~168_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][113]~q ;
wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~8_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~17_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][113]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~169_combout ;
wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~8_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][113]~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~17_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][113]~feeder_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][113]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][113]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~18_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][113]~q ;
wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~8_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][113]~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~17_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][113]~q ;
wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~8_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][113]~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~17_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][113]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~50_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~173_combout ;
wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~8_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][113]~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~17_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][113]~q ;
wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~8_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][113]~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~17_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][113]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~51_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][113]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~18_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][113]~q ;
wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~8_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][113]~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~17_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][113]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~174_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~175_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][113]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~18_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][113]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][113]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~18_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][113]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~170_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][113]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~18_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][113]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~172_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][113]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~18_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][113]~q ;
wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~8_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][113]~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~17_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][113]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~166_combout ;
wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~8_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][113]~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~17_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][113]~q ;
wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~8_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][113]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~17_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][113]~feeder_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][113]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~167_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][113]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~18_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][113]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][113]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~18_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][113]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~171_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~3_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][77]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~8_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][77]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][78]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~9_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][78]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][75]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~6_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][75]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_busy~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][76]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~7_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][76]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][74]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~5_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][74]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add1~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add1~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used[1]~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][112]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~17_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][112]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][112]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~17_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][112]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~162_combout ;
wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~7_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][112]~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~16_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][112]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][112]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~17_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][112]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~158_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][112]~q ;
wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~7_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~16_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][112]~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][112]~q ;
wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~7_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~16_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][112]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~159_combout ;
wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~7_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][112]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~16_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][112]~feeder_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][112]~q ;
wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~7_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][112]~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~16_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][112]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][112]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~17_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][112]~q ;
wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~7_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][112]~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~16_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][112]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~156_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~157_combout ;
wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~7_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][112]~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~16_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][112]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~49_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][112]~q ;
wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~7_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~16_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][112]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][112]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~17_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][112]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~164_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][112]~q ;
wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~7_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~16_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][112]~q ;
wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~7_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][112]~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~16_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][112]~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][112]~q ;
wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~7_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~16_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][112]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~48_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~163_combout ;
wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~7_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][112]~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~16_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][112]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~165_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][112]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~17_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][112]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][112]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~17_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][112]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~160_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][112]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~17_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][112]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][112]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~17_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][112]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~161_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ;
wire \u0|mm_interconnect_0|cmd_mux_013|packet_in_progress~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_013|packet_in_progress~q ;
wire \u0|mm_interconnect_0|cmd_mux_013|update_grant~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~2_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~3_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout ;
wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~6_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][111]~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~15_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][111]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][111]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~16_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][111]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~146_combout ;
wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~6_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][111]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~15_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][111]~feeder_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][111]~q ;
wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~6_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][111]~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~15_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][111]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~147_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][111]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~16_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][111]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~150_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][111]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~16_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][111]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][111]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~16_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][111]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~151_combout ;
wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~6_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][111]~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~15_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][111]~feeder_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][111]~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][111]~q ;
wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~6_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~15_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][111]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~46_combout ;
wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~6_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][111]~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~15_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][111]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][111]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~16_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][111]~feeder_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][111]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~153_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][111]~q ;
wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~6_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~15_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][111]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~47_combout ;
wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~6_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][111]~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~15_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][111]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][111]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~16_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][111]~feeder_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][111]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~154_combout ;
wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~6_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][111]~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~15_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][111]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~155_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][111]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~16_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][111]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][111]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~16_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][111]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~152_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][111]~q ;
wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~6_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~15_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][111]~q ;
wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~6_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][111]~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~15_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][111]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][111]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~16_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][111]~feeder_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][111]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~148_combout ;
wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~6_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][111]~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~15_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][111]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~149_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~3_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;
wire \u0|mm_interconnect_0|router_001|Equal13~0_combout ;
wire \u0|mm_interconnect_0|router_001|Equal13~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_007|src_valid~1_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~2_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~3_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[4]~5_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~1_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|LessThan14~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~1_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~4_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector28~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~5_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|LessThan12~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~6_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~7_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~21_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~77_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|LessThan10~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector29~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~78 ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~73_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~1_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~22 ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~17_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector28~1_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~74 ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~69_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~18 ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~13_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector27~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~70 ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~65_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~14 ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~9_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector26~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~10 ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~5_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~66 ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~9_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector25~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~10 ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~6 ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~17_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector23~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~18 ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~13_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector22~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~14 ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~25_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector21~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~26 ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~21_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector20~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~22 ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~41_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector19~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~42 ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~37_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector18~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~38 ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~33_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector17~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~34 ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~49_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector16~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~50 ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~29_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector15~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~30 ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~46 ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~61_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector13~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~62 ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~1_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector12~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~2 ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~58 ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~53_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector10~0_combout ;
wire \u0|mm_interconnect_0|router|Equal6~5_combout ;
wire \u0|mm_interconnect_0|cmd_mux_007|src_valid~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~2_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~3_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent|local_write~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][129]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][129]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][110]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~15_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][110]~feeder_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][110]~q ;
wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~5_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][110]~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~14_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][110]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~136_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~137_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][110]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~15_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][110]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~140_combout ;
wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~5_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][110]~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~14_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][110]~feeder_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][110]~q ;
wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~5_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][110]~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~14_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][110]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][110]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~15_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][110]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~138_combout ;
wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~5_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][110]~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~14_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][110]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~139_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][110]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~15_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][110]~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][110]~q ;
wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~5_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~14_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][110]~q ;
wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~5_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][110]~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~14_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][110]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~44_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~143_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][110]~q ;
wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~5_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~14_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][110]~q ;
wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~5_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][110]~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~14_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][110]~q ;
wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~5_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][110]~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~14_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][110]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~45_combout ;
wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~5_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][110]~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~14_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][110]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][110]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~15_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][110]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~144_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~145_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][110]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~15_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][110]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][110]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~15_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][110]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~141_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][110]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~15_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][110]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][110]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~15_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][110]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~142_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~4_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~2_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~3_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~1_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_011|update_grant~0_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|src11_valid~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg~2_combout ;
wire \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_011|arb|grant[1]~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent|m0_read~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg~1_combout ;
wire \u0|mm_interconnect_0|rsp_demux_011|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][129]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][129]~feeder_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][129]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|read~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|read~1_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used[1]~1_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used[0]~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent|comb~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|always0~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used[0]~1_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent|rp_valid~combout ;
wire \u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][109]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~14_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][109]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][109]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~14_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][109]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~131_combout ;
wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~4_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][109]~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~13_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][109]~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][109]~q ;
wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~4_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~13_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][109]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][109]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~14_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][109]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~128_combout ;
wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~4_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][109]~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~13_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][109]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~129_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][109]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~14_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][109]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][109]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~14_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][109]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~132_combout ;
wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~4_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][109]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~13_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][109]~feeder_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][109]~q ;
wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~4_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][109]~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~13_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][109]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~126_combout ;
wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~4_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][109]~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~13_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][109]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~127_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][109]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~14_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][109]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][109]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~14_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][109]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~130_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][109]~q ;
wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~4_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~13_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][109]~feeder_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][109]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][109]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~14_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][109]~q ;
wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~4_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][109]~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~13_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][109]~q ;
wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~4_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][109]~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~13_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][109]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~43_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~134_combout ;
wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~4_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][109]~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~13_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][109]~q ;
wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~4_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][109]~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~13_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][109]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~42_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][109]~q ;
wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~4_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~13_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][109]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][109]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~14_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][109]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~133_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~135_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~2_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~3_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_009|update_grant~0_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|src9_valid~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg~2_combout ;
wire \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_009|arb|grant[1]~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][108]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~13_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][108]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~120_combout ;
wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~3_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][108]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~12_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][108]~feeder_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][108]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][108]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~13_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][108]~q ;
wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~3_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][108]~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~12_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][108]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~116_combout ;
wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~3_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][108]~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~12_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][108]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~117_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][108]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~13_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][108]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][108]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~13_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][108]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~122_combout ;
wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~3_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][108]~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~12_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][108]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][108]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~13_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][108]~q ;
wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~3_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][108]~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~12_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][108]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~118_combout ;
wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~3_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][108]~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~12_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][108]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~119_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][108]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~13_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][108]~q ;
wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~3_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][108]~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~12_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][108]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~40_combout ;
wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~3_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][108]~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~12_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][108]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~123_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][108]~q ;
wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~3_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~12_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][108]~feeder_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][108]~q ;
wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~3_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][108]~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~12_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][108]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~41_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][108]~q ;
wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~3_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~12_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][108]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][108]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~13_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][108]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~124_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][108]~q ;
wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~3_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~12_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][108]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~125_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][108]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~13_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][108]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][108]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~13_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][108]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~121_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~2_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][74]~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~7_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][76]~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~5_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][76]~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][77]~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~4_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][77]~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][75]~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~6_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][75]~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][78]~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~3_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][78]~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~2_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_busy~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][66]~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~2_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][66]~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|read~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[1]~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[0]~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|comb~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[1]~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ;
wire \u0|mm_interconnect_0|cmd_mux_005|packet_in_progress~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_005|packet_in_progress~q ;
wire \u0|mm_interconnect_0|cmd_mux_005|update_grant~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|write~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[0]~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout ;
wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~2_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][107]~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~11_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][107]~q ;
wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~2_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][107]~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~11_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][107]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~39_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][107]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~12_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][107]~feeder_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][107]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~114_combout ;
wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~2_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][107]~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~11_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][107]~feeder_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][107]~q ;
wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~2_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][107]~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~11_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][107]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~38_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][107]~q ;
wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~2_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~11_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][107]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][107]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~12_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][107]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~113_combout ;
wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~2_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][107]~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~11_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][107]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~115_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][107]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~12_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][107]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][107]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~12_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][107]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~112_combout ;
wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~2_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][107]~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~11_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][107]~feeder_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][107]~q ;
wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~2_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][107]~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~11_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][107]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][107]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~12_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][107]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~108_combout ;
wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~2_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][107]~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~11_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][107]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~109_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][107]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~12_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][107]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][107]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~12_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][107]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~111_combout ;
wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~2_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][107]~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~11_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][107]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][107]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~12_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][107]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~106_combout ;
wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~2_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][107]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~11_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][107]~q ;
wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][107]~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~11_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][107]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~107_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][107]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~12_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][107]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][107]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~12_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][107]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~110_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~3_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ;
wire \u0|mm_interconnect_0|cmd_mux_016|packet_in_progress~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_016|packet_in_progress~q ;
wire \u0|mm_interconnect_0|cmd_mux_016|update_grant~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][75]~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~6_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][75]~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][74]~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~7_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74]~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][78]~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~3_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][78]~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][77]~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~4_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][77]~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][76]~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~5_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][76]~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][66]~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][66]~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|write~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used[1]~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][129]~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][129]~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|read~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used[1]~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used[0]~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|comb~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used[0]~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout ;
wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][106]~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~10_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][106]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][106]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~11_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][106]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~96_combout ;
wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][106]~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~10_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][106]~q ;
wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~1_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][106]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~10_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][106]~feeder_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][106]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~97_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][106]~q ;
wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~10_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][106]~q ;
wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~1_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][106]~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~10_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][106]~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][106]~q ;
wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~1_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~10_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][106]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~36_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~103_combout ;
wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][106]~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~10_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][106]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~37_combout ;
wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][106]~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~10_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][106]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][106]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~11_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][106]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~104_combout ;
wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~1_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][106]~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~10_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][106]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~105_combout ;
wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~1_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][106]~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~10_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][106]~feeder_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][106]~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][106]~q ;
wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~1_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~10_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][106]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][106]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~11_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][106]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~98_combout ;
wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~1_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][106]~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~10_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][106]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~99_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][106]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~11_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][106]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][106]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~11_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][106]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~100_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][106]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~11_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][106]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][106]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~11_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][106]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~101_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][106]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~11_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][106]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][106]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~11_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][106]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~102_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][105]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~10_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][105]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][105]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~10_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][105]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~90_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][105]~q ;
wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~9_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][105]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~88_combout ;
wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][105]~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~9_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][105]~q ;
wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][105]~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~9_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][105]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~89_combout ;
wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][105]~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~9_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][105]~q ;
wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][105]~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~9_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][105]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~35_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][105]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~10_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][105]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~94_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][105]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~10_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][105]~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][105]~q ;
wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~9_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][105]~q ;
wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][105]~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~9_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][105]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~34_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~93_combout ;
wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][105]~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~9_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][105]~feeder_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][105]~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][105]~q ;
wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~9_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][105]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~95_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][105]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~10_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][105]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][105]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~10_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][105]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~91_combout ;
wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][105]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~9_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][105]~feeder_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][105]~q ;
wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][105]~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~9_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][105]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][105]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~10_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][105]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~86_combout ;
wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][105]~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~9_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][105]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~87_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][105]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~10_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][105]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][105]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~10_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][105]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~92_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~2_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;
wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~14_combout ;
wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~16_combout ;
wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~15_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~2_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~2_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~3_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~14 ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~9_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~17_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~1_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~13_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~2_combout ;
wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~18_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][11]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~11_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][11]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~31_combout ;
wire \u0|mm_interconnect_0|cmd_mux_004|src_payload~0_combout ;
wire \u0|data_read_en_rx|data_out~feeder_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~14 ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~10 ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~5_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~13_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~9_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~6 ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~1_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;
wire \u0|data_read_en_rx|always0~0_combout ;
wire \u0|data_read_en_rx|data_out~q ;
wire \A_SPW_TOP|rx_data|Add9~1_sumout ;
wire \A_SPW_TOP|rx_data|counter_writer[0]~0_combout ;
wire \A_SPW_TOP|SPW|RX|rx_buffer_write~1_combout ;
wire \A_SPW_TOP|SPW|RX|rx_buffer_write~0_combout ;
wire \A_SPW_TOP|SPW|RX|rx_buffer_write~q ;
wire \A_SPW_TOP|rx_data|counter_reader[0]~0_combout ;
wire \A_SPW_TOP|rx_data|state_data_read~9_combout ;
wire \A_SPW_TOP|rx_data|state_data_read.10~feeder_combout ;
wire \A_SPW_TOP|rx_data|state_data_read.10~q ;
wire \A_SPW_TOP|rx_data|state_data_read~8_combout ;
wire \A_SPW_TOP|rx_data|state_data_read.01~feeder_combout ;
wire \A_SPW_TOP|rx_data|state_data_read.01~q ;
wire \A_SPW_TOP|rx_data|always5~0_combout ;
wire \A_SPW_TOP|rx_data|Add8~1_sumout ;
wire \A_SPW_TOP|rx_data|Add7~0_combout ;
wire \A_SPW_TOP|rx_data|Add6~0_combout ;
wire \A_SPW_TOP|rx_data|Add8~2 ;
wire \A_SPW_TOP|rx_data|Add8~3 ;
wire \A_SPW_TOP|rx_data|Add8~5_sumout ;
wire \A_SPW_TOP|rx_data|Add7~1_combout ;
wire \A_SPW_TOP|rx_data|Add7~2_combout ;
wire \A_SPW_TOP|rx_data|Add7~3_combout ;
wire \A_SPW_TOP|rx_data|Add7~4_combout ;
wire \A_SPW_TOP|rx_data|Add6~1_combout ;
wire \A_SPW_TOP|rx_data|Add6~3_combout ;
wire \A_SPW_TOP|rx_data|Add6~4_combout ;
wire \A_SPW_TOP|rx_data|Add8~6 ;
wire \A_SPW_TOP|rx_data|Add8~7 ;
wire \A_SPW_TOP|rx_data|Add8~10 ;
wire \A_SPW_TOP|rx_data|Add8~11 ;
wire \A_SPW_TOP|rx_data|Add8~14 ;
wire \A_SPW_TOP|rx_data|Add8~15 ;
wire \A_SPW_TOP|rx_data|Add8~18 ;
wire \A_SPW_TOP|rx_data|Add8~19 ;
wire \A_SPW_TOP|rx_data|Add8~21_sumout ;
wire \A_SPW_TOP|rx_data|Add8~17_sumout ;
wire \A_SPW_TOP|rx_data|Add8~9_sumout ;
wire \A_SPW_TOP|rx_data|Equal9~0_combout ;
wire \A_SPW_TOP|rx_data|f_full~q ;
wire \A_SPW_TOP|rx_data|state_data_write~8_combout ;
wire \A_SPW_TOP|rx_data|state_data_write.01~q ;
wire \A_SPW_TOP|rx_data|state_data_write~7_combout ;
wire \A_SPW_TOP|rx_data|state_data_write.00~q ;
wire \A_SPW_TOP|rx_data|state_data_write~9_combout ;
wire \A_SPW_TOP|rx_data|state_data_write.10~q ;
wire \A_SPW_TOP|rx_data|Add6~2_combout ;
wire \A_SPW_TOP|rx_data|Add8~13_sumout ;
wire \A_SPW_TOP|rx_data|Equal10~0_combout ;
wire \A_SPW_TOP|rx_data|f_empty~q ;
wire \A_SPW_TOP|rx_data|state_data_read~7_combout ;
wire \A_SPW_TOP|rx_data|state_data_read.00~feeder_combout ;
wire \A_SPW_TOP|rx_data|state_data_read.00~q ;
wire \A_SPW_TOP|rx_data|Add9~2 ;
wire \A_SPW_TOP|rx_data|Add9~13_sumout ;
wire \A_SPW_TOP|rx_data|Add9~14 ;
wire \A_SPW_TOP|rx_data|Add9~9_sumout ;
wire \A_SPW_TOP|rx_data|always3~0_combout ;
wire \A_SPW_TOP|rx_data|state_open_slot~8_combout ;
wire \A_SPW_TOP|rx_data|state_open_slot.00~q ;
wire \A_SPW_TOP|rx_data|Selector8~1_combout ;
wire \A_SPW_TOP|rx_data|Selector1~0_combout ;
wire \A_SPW_TOP|rx_data|Add0~30 ;
wire \A_SPW_TOP|rx_data|Add0~25_sumout ;
wire \A_SPW_TOP|rx_data|Selector14~0_combout ;
wire \A_SPW_TOP|rx_data|Add0~26 ;
wire \A_SPW_TOP|rx_data|Add0~21_sumout ;
wire \A_SPW_TOP|rx_data|Selector13~0_combout ;
wire \A_SPW_TOP|rx_data|Add0~22 ;
wire \A_SPW_TOP|rx_data|Add0~17_sumout ;
wire \A_SPW_TOP|rx_data|Selector12~0_combout ;
wire \A_SPW_TOP|rx_data|Add0~18 ;
wire \A_SPW_TOP|rx_data|Add0~13_sumout ;
wire \A_SPW_TOP|rx_data|Selector11~0_combout ;
wire \A_SPW_TOP|rx_data|Add0~14 ;
wire \A_SPW_TOP|rx_data|Add0~9_sumout ;
wire \A_SPW_TOP|rx_data|Selector10~0_combout ;
wire \A_SPW_TOP|rx_data|Add0~10 ;
wire \A_SPW_TOP|rx_data|Add0~5_sumout ;
wire \A_SPW_TOP|rx_data|Selector9~0_combout ;
wire \A_SPW_TOP|rx_data|Add0~6 ;
wire \A_SPW_TOP|rx_data|Add0~1_sumout ;
wire \A_SPW_TOP|rx_data|Selector8~2_combout ;
wire \A_SPW_TOP|rx_data|Equal0~0_combout ;
wire \A_SPW_TOP|rx_data|Add0~41_sumout ;
wire \A_SPW_TOP|rx_data|Selector18~0_combout ;
wire \A_SPW_TOP|rx_data|Selector18~1_combout ;
wire \A_SPW_TOP|rx_data|Add0~42 ;
wire \A_SPW_TOP|rx_data|Add0~37_sumout ;
wire \A_SPW_TOP|rx_data|Selector17~0_combout ;
wire \A_SPW_TOP|rx_data|Add0~38 ;
wire \A_SPW_TOP|rx_data|Add0~33_sumout ;
wire \A_SPW_TOP|rx_data|Selector16~0_combout ;
wire \A_SPW_TOP|rx_data|Add0~34 ;
wire \A_SPW_TOP|rx_data|Add0~29_sumout ;
wire \A_SPW_TOP|rx_data|Selector15~0_combout ;
wire \A_SPW_TOP|rx_data|Equal0~1_combout ;
wire \A_SPW_TOP|rx_data|state_open_slot~9_combout ;
wire \A_SPW_TOP|rx_data|state_open_slot.10~q ;
wire \A_SPW_TOP|rx_data|state_open_slot~7_combout ;
wire \A_SPW_TOP|rx_data|state_open_slot.01~q ;
wire \A_SPW_TOP|rx_data|Selector8~0_combout ;
wire \A_SPW_TOP|rx_data|open_slot_fct~q ;
wire \A_SPW_TOP|SPW|TX|fct_flag~2_combout ;
wire \A_SPW_TOP|SPW|TX|state_fct_send.001~q ;
wire \A_SPW_TOP|SPW|TX|fct_flag~0_combout ;
wire \A_SPW_TOP|SPW|RX|rx_got_fct_fsm~feeder_combout ;
wire \A_SPW_TOP|SPW|RX|control_l_r~0_combout ;
wire \A_SPW_TOP|SPW|RX|control_l_r~2_combout ;
wire \A_SPW_TOP|SPW|RX|control_l_r~1_combout ;
wire \A_SPW_TOP|SPW|RX|always8~0_combout ;
wire \A_SPW_TOP|SPW|RX|always10~0_combout ;
wire \A_SPW_TOP|SPW|RX|rx_got_fct_fsm~q ;
wire \A_SPW_TOP|SPW|RX|rx_got_time_code~0_combout ;
wire \A_SPW_TOP|SPW|RX|rx_got_time_code~q ;
wire \A_SPW_TOP|SPW|FSM|state_fsm~21_combout ;
wire \A_SPW_TOP|SPW|FSM|always0~1_combout ;
wire \A_SPW_TOP|SPW|FSM|always0~0_combout ;
wire \A_SPW_TOP|SPW|FSM|state_fsm~18_combout ;
wire \A_SPW_TOP|SPW|FSM|state_fsm.connecting~q ;
wire \A_SPW_TOP|SPW|FSM|send_fct_tx~0_combout ;
wire \A_SPW_TOP|SPW|FSM|send_fct_tx~q ;
wire \u0|mm_interconnect_0|cmd_mux_015|src_payload~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_write~combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;
wire \u0|timecode_tx_enable|always0~0_combout ;
wire \u0|timecode_tx_enable|data_out~q ;
wire \A_SPW_TOP|SPW|TX|Equal0~5_combout ;
wire \A_SPW_TOP|SPW|TX|Equal0~6_combout ;
wire \A_SPW_TOP|SPW|TX|Selector42~1_combout ;
wire \A_SPW_TOP|SPW|TX|tx_tcode_in~0_combout ;
wire \A_SPW_TOP|tx_data|rd_ptr~5_combout ;
wire \A_SPW_TOP|tx_data|rd_ptr~1_combout ;
wire \A_SPW_TOP|tx_data|rd_ptr~3_combout ;
wire \A_SPW_TOP|tx_data|rd_ptr~2_combout ;
wire \A_SPW_TOP|tx_data|Add4~0_combout ;
wire \A_SPW_TOP|tx_data|rd_ptr~4_combout ;
wire \A_SPW_TOP|tx_data|rd_ptr~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_010|src_payload~8_combout ;
wire \u0|write_data_fifo_tx|always0~0_combout ;
wire \A_SPW_TOP|tx_data|wr_ptr[0]~0_combout ;
wire \A_SPW_TOP|tx_data|Add0~4_combout ;
wire \A_SPW_TOP|tx_data|Add0~1_combout ;
wire \A_SPW_TOP|tx_data|Add0~2_combout ;
wire \A_SPW_TOP|tx_data|Add0~3_combout ;
wire \A_SPW_TOP|tx_data|wr_ptr[4]~feeder_combout ;
wire \A_SPW_TOP|tx_data|Add0~0_combout ;
wire \A_SPW_TOP|tx_data|wr_ptr[5]~feeder_combout ;
wire \A_SPW_TOP|tx_data|Decoder0~13_combout ;
wire \A_SPW_TOP|tx_data|Selector401~0_combout ;
wire \A_SPW_TOP|tx_data|Decoder0~20_combout ;
wire \A_SPW_TOP|tx_data|Selector437~0_combout ;
wire \A_SPW_TOP|tx_data|Selector437~1_combout ;
wire \A_SPW_TOP|tx_data|mem[48][8]~q ;
wire \A_SPW_TOP|tx_data|Decoder0~18_combout ;
wire \A_SPW_TOP|tx_data|Selector185~0_combout ;
wire \A_SPW_TOP|tx_data|Selector185~1_combout ;
wire \A_SPW_TOP|tx_data|mem[20][8]~q ;
wire \A_SPW_TOP|tx_data|Decoder0~16_combout ;
wire \A_SPW_TOP|tx_data|Selector149~0_combout ;
wire \A_SPW_TOP|tx_data|Selector149~1_combout ;
wire \A_SPW_TOP|tx_data|mem[16][8]~q ;
wire \A_SPW_TOP|tx_data|Decoder0~22_combout ;
wire \A_SPW_TOP|tx_data|Selector473~0_combout ;
wire \A_SPW_TOP|tx_data|Selector473~1_combout ;
wire \A_SPW_TOP|tx_data|mem[52][8]~q ;
wire \A_SPW_TOP|tx_data|Mux0~2_combout ;
wire \A_SPW_TOP|tx_data|Decoder0~17_combout ;
wire \A_SPW_TOP|tx_data|Selector221~0_combout ;
wire \A_SPW_TOP|tx_data|Selector221~1_combout ;
wire \A_SPW_TOP|tx_data|mem[24][8]~q ;
wire \A_SPW_TOP|tx_data|Decoder0~21_combout ;
wire \A_SPW_TOP|tx_data|Selector509~0_combout ;
wire \A_SPW_TOP|tx_data|Selector509~1_combout ;
wire \A_SPW_TOP|tx_data|mem[56][8]~q ;
wire \A_SPW_TOP|tx_data|Decoder0~23_combout ;
wire \A_SPW_TOP|tx_data|Selector545~0_combout ;
wire \A_SPW_TOP|tx_data|Selector545~1_combout ;
wire \A_SPW_TOP|tx_data|mem[60][8]~q ;
wire \A_SPW_TOP|tx_data|Decoder0~19_combout ;
wire \A_SPW_TOP|tx_data|Selector257~0_combout ;
wire \A_SPW_TOP|tx_data|Selector257~1_combout ;
wire \A_SPW_TOP|tx_data|mem[28][8]~q ;
wire \A_SPW_TOP|tx_data|Mux0~3_combout ;
wire \A_SPW_TOP|tx_data|Decoder0~4_combout ;
wire \A_SPW_TOP|tx_data|Selector77~0_combout ;
wire \A_SPW_TOP|tx_data|Selector77~1_combout ;
wire \A_SPW_TOP|tx_data|mem[8][8]~q ;
wire \A_SPW_TOP|tx_data|Decoder0~12_combout ;
wire \A_SPW_TOP|tx_data|Selector113~0_combout ;
wire \A_SPW_TOP|tx_data|Selector113~1_combout ;
wire \A_SPW_TOP|tx_data|mem[12][8]~q ;
wire \A_SPW_TOP|tx_data|Decoder0~5_combout ;
wire \A_SPW_TOP|tx_data|Selector365~0_combout ;
wire \A_SPW_TOP|tx_data|Selector365~1_combout ;
wire \A_SPW_TOP|tx_data|mem[40][8]~q ;
wire \A_SPW_TOP|tx_data|Mux0~1_combout ;
wire \A_SPW_TOP|tx_data|Decoder0~1_combout ;
wire \A_SPW_TOP|tx_data|Selector293~0_combout ;
wire \A_SPW_TOP|tx_data|Selector293~1_combout ;
wire \A_SPW_TOP|tx_data|mem[32][8]~q ;
wire \A_SPW_TOP|tx_data|Decoder0~0_combout ;
wire \A_SPW_TOP|tx_data|Selector5~0_combout ;
wire \A_SPW_TOP|tx_data|Selector5~1_combout ;
wire \A_SPW_TOP|tx_data|mem[0][8]~feeder_combout ;
wire \A_SPW_TOP|tx_data|mem[0][8]~q ;
wire \A_SPW_TOP|tx_data|Decoder0~9_combout ;
wire \A_SPW_TOP|tx_data|Selector329~0_combout ;
wire \A_SPW_TOP|tx_data|Selector329~1_combout ;
wire \A_SPW_TOP|tx_data|mem[36][8]~q ;
wire \A_SPW_TOP|tx_data|Decoder0~8_combout ;
wire \A_SPW_TOP|tx_data|Selector41~0_combout ;
wire \A_SPW_TOP|tx_data|Selector41~1_combout ;
wire \A_SPW_TOP|tx_data|mem[4][8]~q ;
wire \A_SPW_TOP|tx_data|Mux0~0_combout ;
wire \A_SPW_TOP|tx_data|Mux0~4_combout ;
wire \A_SPW_TOP|tx_data|Decoder0~58_combout ;
wire \A_SPW_TOP|tx_data|Selector212~0_combout ;
wire \A_SPW_TOP|tx_data|Selector212~1_combout ;
wire \A_SPW_TOP|tx_data|mem[23][8]~q ;
wire \A_SPW_TOP|tx_data|Decoder0~42_combout ;
wire \A_SPW_TOP|tx_data|Selector68~0_combout ;
wire \A_SPW_TOP|tx_data|Selector68~1_combout ;
wire \A_SPW_TOP|tx_data|mem[7][8]~q ;
wire \A_SPW_TOP|tx_data|Decoder0~59_combout ;
wire \A_SPW_TOP|tx_data|Selector284~0_combout ;
wire \A_SPW_TOP|tx_data|Selector284~1_combout ;
wire \A_SPW_TOP|tx_data|mem[31][8]~q ;
wire \A_SPW_TOP|tx_data|Decoder0~46_combout ;
wire \A_SPW_TOP|tx_data|Selector140~0_combout ;
wire \A_SPW_TOP|tx_data|Selector140~1_combout ;
wire \A_SPW_TOP|tx_data|mem[15][8]~q ;
wire \A_SPW_TOP|tx_data|Mux0~17_combout ;
wire \A_SPW_TOP|tx_data|Decoder0~47_combout ;
wire \A_SPW_TOP|tx_data|Selector428~0_combout ;
wire \A_SPW_TOP|tx_data|Selector428~1_combout ;
wire \A_SPW_TOP|tx_data|mem[47][8]~q ;
wire \A_SPW_TOP|tx_data|Decoder0~62_combout ;
wire \A_SPW_TOP|tx_data|Selector500~0_combout ;
wire \A_SPW_TOP|tx_data|Selector500~1_combout ;
wire \A_SPW_TOP|tx_data|mem[55][8]~q ;
wire \A_SPW_TOP|tx_data|Decoder0~63_combout ;
wire \A_SPW_TOP|tx_data|Selector572~0_combout ;
wire \A_SPW_TOP|tx_data|Selector572~1_combout ;
wire \A_SPW_TOP|tx_data|mem[63][8]~q ;
wire \A_SPW_TOP|tx_data|Decoder0~43_combout ;
wire \A_SPW_TOP|tx_data|Selector356~0_combout ;
wire \A_SPW_TOP|tx_data|Selector356~1_combout ;
wire \A_SPW_TOP|tx_data|mem[39][8]~q ;
wire \A_SPW_TOP|tx_data|Mux0~18_combout ;
wire \A_SPW_TOP|tx_data|Decoder0~34_combout ;
wire \A_SPW_TOP|tx_data|Selector32~0_combout ;
wire \A_SPW_TOP|tx_data|Selector32~1_combout ;
wire \A_SPW_TOP|tx_data|mem[3][8]~q ;
wire \A_SPW_TOP|tx_data|Decoder0~38_combout ;
wire \A_SPW_TOP|tx_data|Selector104~0_combout ;
wire \A_SPW_TOP|tx_data|Selector104~1_combout ;
wire \A_SPW_TOP|tx_data|mem[11][8]~q ;
wire \A_SPW_TOP|tx_data|Decoder0~56_combout ;
wire \A_SPW_TOP|tx_data|Selector176~0_combout ;
wire \A_SPW_TOP|tx_data|Selector176~1_combout ;
wire \A_SPW_TOP|tx_data|mem[19][8]~q ;
wire \A_SPW_TOP|tx_data|Decoder0~57_combout ;
wire \A_SPW_TOP|tx_data|Selector248~0_combout ;
wire \A_SPW_TOP|tx_data|Selector248~1_combout ;
wire \A_SPW_TOP|tx_data|mem[27][8]~q ;
wire \A_SPW_TOP|tx_data|Mux0~15_combout ;
wire \A_SPW_TOP|tx_data|Decoder0~39_combout ;
wire \A_SPW_TOP|tx_data|Selector392~0_combout ;
wire \A_SPW_TOP|tx_data|Selector392~1_combout ;
wire \A_SPW_TOP|tx_data|mem[43][8]~q ;
wire \A_SPW_TOP|tx_data|Decoder0~35_combout ;
wire \A_SPW_TOP|tx_data|Selector320~0_combout ;
wire \A_SPW_TOP|tx_data|Selector320~1_combout ;
wire \A_SPW_TOP|tx_data|mem[35][8]~q ;
wire \A_SPW_TOP|tx_data|Decoder0~60_combout ;
wire \A_SPW_TOP|tx_data|Selector464~0_combout ;
wire \A_SPW_TOP|tx_data|Selector464~1_combout ;
wire \A_SPW_TOP|tx_data|mem[51][8]~q ;
wire \A_SPW_TOP|tx_data|Decoder0~61_combout ;
wire \A_SPW_TOP|tx_data|Selector536~0_combout ;
wire \A_SPW_TOP|tx_data|Selector536~1_combout ;
wire \A_SPW_TOP|tx_data|mem[59][8]~q ;
wire \A_SPW_TOP|tx_data|Mux0~16_combout ;
wire \A_SPW_TOP|tx_data|Mux0~19_combout ;
wire \A_SPW_TOP|tx_data|Decoder0~27_combout ;
wire \A_SPW_TOP|tx_data|Selector275~0_combout ;
wire \A_SPW_TOP|tx_data|Selector275~1_combout ;
wire \A_SPW_TOP|tx_data|mem[30][8]~q ;
wire \A_SPW_TOP|tx_data|Decoder0~26_combout ;
wire \A_SPW_TOP|tx_data|Selector203~0_combout ;
wire \A_SPW_TOP|tx_data|Selector203~1_combout ;
wire \A_SPW_TOP|tx_data|mem[22][8]~q ;
wire \A_SPW_TOP|tx_data|Decoder0~14_combout ;
wire \A_SPW_TOP|tx_data|Selector131~0_combout ;
wire \A_SPW_TOP|tx_data|Selector131~1_combout ;
wire \A_SPW_TOP|tx_data|mem[14][8]~q ;
wire \A_SPW_TOP|tx_data|Decoder0~10_combout ;
wire \A_SPW_TOP|tx_data|Selector59~0_combout ;
wire \A_SPW_TOP|tx_data|Selector59~1_combout ;
wire \A_SPW_TOP|tx_data|mem[6][8]~q ;
wire \A_SPW_TOP|tx_data|Mux0~7_combout ;
wire \A_SPW_TOP|tx_data|Decoder0~24_combout ;
wire \A_SPW_TOP|tx_data|Selector167~0_combout ;
wire \A_SPW_TOP|tx_data|Selector167~1_combout ;
wire \A_SPW_TOP|tx_data|mem[18][8]~q ;
wire \A_SPW_TOP|tx_data|Decoder0~2_combout ;
wire \A_SPW_TOP|tx_data|Selector23~0_combout ;
wire \A_SPW_TOP|tx_data|Selector23~1_combout ;
wire \A_SPW_TOP|tx_data|mem[2][8]~q ;
wire \A_SPW_TOP|tx_data|Decoder0~25_combout ;
wire \A_SPW_TOP|tx_data|Selector239~0_combout ;
wire \A_SPW_TOP|tx_data|Selector239~1_combout ;
wire \A_SPW_TOP|tx_data|mem[26][8]~q ;
wire \A_SPW_TOP|tx_data|Decoder0~6_combout ;
wire \A_SPW_TOP|tx_data|Selector95~0_combout ;
wire \A_SPW_TOP|tx_data|Selector95~1_combout ;
wire \A_SPW_TOP|tx_data|mem[10][8]~q ;
wire \A_SPW_TOP|tx_data|Mux0~5_combout ;
wire \A_SPW_TOP|tx_data|Decoder0~7_combout ;
wire \A_SPW_TOP|tx_data|Selector383~0_combout ;
wire \A_SPW_TOP|tx_data|Selector383~1_combout ;
wire \A_SPW_TOP|tx_data|mem[42][8]~feeder_combout ;
wire \A_SPW_TOP|tx_data|mem[42][8]~q ;
wire \A_SPW_TOP|tx_data|Decoder0~28_combout ;
wire \A_SPW_TOP|tx_data|Selector455~0_combout ;
wire \A_SPW_TOP|tx_data|Selector455~1_combout ;
wire \A_SPW_TOP|tx_data|mem[50][8]~q ;
wire \A_SPW_TOP|tx_data|Decoder0~29_combout ;
wire \A_SPW_TOP|tx_data|Selector527~0_combout ;
wire \A_SPW_TOP|tx_data|Selector527~1_combout ;
wire \A_SPW_TOP|tx_data|mem[58][8]~q ;
wire \A_SPW_TOP|tx_data|Decoder0~3_combout ;
wire \A_SPW_TOP|tx_data|Selector311~0_combout ;
wire \A_SPW_TOP|tx_data|Selector311~1_combout ;
wire \A_SPW_TOP|tx_data|mem[34][8]~q ;
wire \A_SPW_TOP|tx_data|Mux0~6_combout ;
wire \A_SPW_TOP|tx_data|Decoder0~15_combout ;
wire \A_SPW_TOP|tx_data|Selector419~0_combout ;
wire \A_SPW_TOP|tx_data|Selector419~1_combout ;
wire \A_SPW_TOP|tx_data|mem[46][8]~q ;
wire \A_SPW_TOP|tx_data|Decoder0~30_combout ;
wire \A_SPW_TOP|tx_data|Selector491~0_combout ;
wire \A_SPW_TOP|tx_data|Selector491~1_combout ;
wire \A_SPW_TOP|tx_data|mem[54][8]~q ;
wire \A_SPW_TOP|tx_data|Decoder0~11_combout ;
wire \A_SPW_TOP|tx_data|Selector347~0_combout ;
wire \A_SPW_TOP|tx_data|Selector347~1_combout ;
wire \A_SPW_TOP|tx_data|mem[38][8]~q ;
wire \A_SPW_TOP|tx_data|Decoder0~31_combout ;
wire \A_SPW_TOP|tx_data|Selector563~0_combout ;
wire \A_SPW_TOP|tx_data|Selector563~1_combout ;
wire \A_SPW_TOP|tx_data|mem[62][8]~q ;
wire \A_SPW_TOP|tx_data|Mux0~8_combout ;
wire \A_SPW_TOP|tx_data|Mux0~9_combout ;
wire \A_SPW_TOP|tx_data|Decoder0~37_combout ;
wire \A_SPW_TOP|tx_data|Selector374~0_combout ;
wire \A_SPW_TOP|tx_data|Selector374~1_combout ;
wire \A_SPW_TOP|tx_data|mem[41][8]~q ;
wire \A_SPW_TOP|tx_data|Decoder0~45_combout ;
wire \A_SPW_TOP|tx_data|Selector410~0_combout ;
wire \A_SPW_TOP|tx_data|Selector410~1_combout ;
wire \A_SPW_TOP|tx_data|mem[45][8]~q ;
wire \A_SPW_TOP|tx_data|Decoder0~36_combout ;
wire \A_SPW_TOP|tx_data|Selector86~0_combout ;
wire \A_SPW_TOP|tx_data|Selector86~1_combout ;
wire \A_SPW_TOP|tx_data|mem[9][8]~q ;
wire \A_SPW_TOP|tx_data|Decoder0~44_combout ;
wire \A_SPW_TOP|tx_data|Selector122~0_combout ;
wire \A_SPW_TOP|tx_data|Selector122~1_combout ;
wire \A_SPW_TOP|tx_data|mem[13][8]~q ;
wire \A_SPW_TOP|tx_data|Mux0~11_combout ;
wire \A_SPW_TOP|tx_data|Decoder0~32_combout ;
wire \A_SPW_TOP|tx_data|Selector14~0_combout ;
wire \A_SPW_TOP|tx_data|Selector14~1_combout ;
wire \A_SPW_TOP|tx_data|mem[1][8]~q ;
wire \A_SPW_TOP|tx_data|Decoder0~40_combout ;
wire \A_SPW_TOP|tx_data|Selector50~0_combout ;
wire \A_SPW_TOP|tx_data|Selector50~1_combout ;
wire \A_SPW_TOP|tx_data|mem[5][8]~q ;
wire \A_SPW_TOP|tx_data|Decoder0~33_combout ;
wire \A_SPW_TOP|tx_data|Selector302~0_combout ;
wire \A_SPW_TOP|tx_data|Selector302~1_combout ;
wire \A_SPW_TOP|tx_data|mem[33][8]~q ;
wire \A_SPW_TOP|tx_data|Decoder0~41_combout ;
wire \A_SPW_TOP|tx_data|Selector338~0_combout ;
wire \A_SPW_TOP|tx_data|Selector338~1_combout ;
wire \A_SPW_TOP|tx_data|mem[37][8]~q ;
wire \A_SPW_TOP|tx_data|Mux0~10_combout ;
wire \A_SPW_TOP|tx_data|Decoder0~55_combout ;
wire \A_SPW_TOP|tx_data|Selector554~0_combout ;
wire \A_SPW_TOP|tx_data|Selector554~1_combout ;
wire \A_SPW_TOP|tx_data|mem[61][8]~q ;
wire \A_SPW_TOP|tx_data|Decoder0~49_combout ;
wire \A_SPW_TOP|tx_data|Selector230~0_combout ;
wire \A_SPW_TOP|tx_data|Selector230~1_combout ;
wire \A_SPW_TOP|tx_data|mem[25][8]~q ;
wire \A_SPW_TOP|tx_data|Decoder0~53_combout ;
wire \A_SPW_TOP|tx_data|Selector518~0_combout ;
wire \A_SPW_TOP|tx_data|Selector518~1_combout ;
wire \A_SPW_TOP|tx_data|mem[57][8]~q ;
wire \A_SPW_TOP|tx_data|Decoder0~51_combout ;
wire \A_SPW_TOP|tx_data|Selector266~0_combout ;
wire \A_SPW_TOP|tx_data|Selector266~1_combout ;
wire \A_SPW_TOP|tx_data|mem[29][8]~q ;
wire \A_SPW_TOP|tx_data|Mux0~13_combout ;
wire \A_SPW_TOP|tx_data|Decoder0~48_combout ;
wire \A_SPW_TOP|tx_data|Selector158~0_combout ;
wire \A_SPW_TOP|tx_data|Selector158~1_combout ;
wire \A_SPW_TOP|tx_data|mem[17][8]~q ;
wire \A_SPW_TOP|tx_data|Decoder0~52_combout ;
wire \A_SPW_TOP|tx_data|Selector446~0_combout ;
wire \A_SPW_TOP|tx_data|Selector446~1_combout ;
wire \A_SPW_TOP|tx_data|mem[49][8]~q ;
wire \A_SPW_TOP|tx_data|Decoder0~54_combout ;
wire \A_SPW_TOP|tx_data|Selector482~0_combout ;
wire \A_SPW_TOP|tx_data|Selector482~1_combout ;
wire \A_SPW_TOP|tx_data|mem[53][8]~q ;
wire \A_SPW_TOP|tx_data|Decoder0~50_combout ;
wire \A_SPW_TOP|tx_data|Selector194~0_combout ;
wire \A_SPW_TOP|tx_data|Selector194~1_combout ;
wire \A_SPW_TOP|tx_data|mem[21][8]~q ;
wire \A_SPW_TOP|tx_data|Mux0~12_combout ;
wire \A_SPW_TOP|tx_data|Mux0~14_combout ;
wire \A_SPW_TOP|tx_data|Mux0~20_combout ;
wire \A_SPW_TOP|tx_data|Selector401~1_combout ;
wire \A_SPW_TOP|tx_data|mem[44][8]~q ;
wire \A_SPW_TOP|tx_data|Mux9~3_combout ;
wire \A_SPW_TOP|tx_data|Mux9~2_combout ;
wire \A_SPW_TOP|tx_data|Mux9~0_combout ;
wire \A_SPW_TOP|tx_data|Mux9~1_combout ;
wire \A_SPW_TOP|tx_data|Mux9~4_combout ;
wire \A_SPW_TOP|tx_data|Mux9~17_combout ;
wire \A_SPW_TOP|tx_data|Mux9~18_combout ;
wire \A_SPW_TOP|tx_data|Mux9~16_combout ;
wire \A_SPW_TOP|tx_data|Mux9~15_combout ;
wire \A_SPW_TOP|tx_data|Mux9~19_combout ;
wire \A_SPW_TOP|tx_data|Mux9~10_combout ;
wire \A_SPW_TOP|tx_data|Mux9~11_combout ;
wire \A_SPW_TOP|tx_data|Mux9~12_combout ;
wire \A_SPW_TOP|tx_data|Mux9~13_combout ;
wire \A_SPW_TOP|tx_data|Mux9~14_combout ;
wire \A_SPW_TOP|tx_data|Mux9~8_combout ;
wire \A_SPW_TOP|tx_data|Mux9~7_combout ;
wire \A_SPW_TOP|tx_data|Mux9~6_combout ;
wire \A_SPW_TOP|tx_data|Mux9~5_combout ;
wire \A_SPW_TOP|tx_data|Mux9~9_combout ;
wire \A_SPW_TOP|tx_data|Mux9~20_combout ;
wire \A_SPW_TOP|SPW|TX|tcode_rdy_trnsp~0_combout ;
wire \A_SPW_TOP|SPW|TX|Selector32~0_combout ;
wire \A_SPW_TOP|SPW|TX|next_state_tx~1_combout ;
wire \A_SPW_TOP|SPW|TX|state_tx~15_combout ;
wire \A_SPW_TOP|SPW|TX|next_state_tx~0_combout ;
wire \A_SPW_TOP|SPW|TX|state_tx~13_combout ;
wire \A_SPW_TOP|SPW|TX|state_tx~14_combout ;
wire \A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q ;
wire \A_SPW_TOP|SPW|TX|state_tx~30_combout ;
wire \A_SPW_TOP|SPW|TX|state_tx~29_combout ;
wire \A_SPW_TOP|SPW|TX|state_tx~31_combout ;
wire \A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c~q ;
wire \A_SPW_TOP|SPW|TX|Selector39~0_combout ;
wire \A_SPW_TOP|SPW|TX|Selector40~0_combout ;
wire \A_SPW_TOP|SPW|TX|Selector32~1_combout ;
wire \A_SPW_TOP|SPW|TX|Selector42~0_combout ;
wire \A_SPW_TOP|SPW|TX|state_fct_p~16_combout ;
wire \A_SPW_TOP|SPW|TX|state_fct_p.100~q ;
wire \A_SPW_TOP|SPW|RX|always8~1_combout ;
wire \A_SPW_TOP|SPW|RX|rx_got_fct~q ;
wire \A_SPW_TOP|SPW|TX|state_fct_receive.000~0_combout ;
wire \A_SPW_TOP|SPW|TX|state_fct_receive~13_combout ;
wire \A_SPW_TOP|SPW|TX|state_fct_receive.000~q ;
wire \A_SPW_TOP|SPW|TX|state_fct_receive~14_combout ;
wire \A_SPW_TOP|SPW|TX|state_fct_receive.010~q ;
wire \A_SPW_TOP|SPW|TX|state_fct_receive~11_combout ;
wire \A_SPW_TOP|SPW|TX|state_fct_receive.001~q ;
wire \A_SPW_TOP|SPW|TX|Selector11~0_combout ;
wire \A_SPW_TOP|SPW|TX|state_fct_p~12_combout ;
wire \A_SPW_TOP|SPW|TX|state_fct_p.001~q ;
wire \A_SPW_TOP|SPW|TX|clear_reg~q ;
wire \A_SPW_TOP|SPW|TX|state_fct_receive~15_combout ;
wire \A_SPW_TOP|SPW|TX|state_fct_receive.011~q ;
wire \A_SPW_TOP|SPW|TX|state_fct_receive~12_combout ;
wire \A_SPW_TOP|SPW|TX|state_fct_receive.100~q ;
wire \A_SPW_TOP|SPW|TX|Selector12~0_combout ;
wire \A_SPW_TOP|SPW|TX|Selector10~0_combout ;
wire \A_SPW_TOP|SPW|TX|state_fct_p~14_combout ;
wire \A_SPW_TOP|SPW|TX|state_fct_p~15_combout ;
wire \A_SPW_TOP|SPW|TX|state_fct_p.000~q ;
wire \A_SPW_TOP|SPW|TX|state_fct_p~13_combout ;
wire \A_SPW_TOP|SPW|TX|state_fct_p.010~q ;
wire \A_SPW_TOP|SPW|TX|state_fct_p.000~0_combout ;
wire \A_SPW_TOP|SPW|TX|state_fct_p~11_combout ;
wire \A_SPW_TOP|SPW|TX|state_fct_p.011~q ;
wire \A_SPW_TOP|SPW|TX|Selector17~0_combout ;
wire \A_SPW_TOP|SPW|TX|Selector17~2_combout ;
wire \A_SPW_TOP|SPW|TX|Selector21~0_combout ;
wire \A_SPW_TOP|SPW|TX|Selector22~0_combout ;
wire \A_SPW_TOP|SPW|TX|Selector21~1_combout ;
wire \A_SPW_TOP|SPW|TX|Selector20~0_combout ;
wire \A_SPW_TOP|SPW|TX|LessThan2~1_combout ;
wire \A_SPW_TOP|SPW|TX|Selector19~0_combout ;
wire \A_SPW_TOP|SPW|TX|LessThan2~2_combout ;
wire \A_SPW_TOP|SPW|TX|Selector18~0_combout ;
wire \A_SPW_TOP|SPW|TX|Selector17~1_combout ;
wire \A_SPW_TOP|SPW|TX|LessThan2~0_combout ;
wire \A_SPW_TOP|SPW|TX|Selector42~2_combout ;
wire \A_SPW_TOP|SPW|TX|Selector40~2_combout ;
wire \A_SPW_TOP|SPW|TX|Selector42~3_combout ;
wire \A_SPW_TOP|SPW|TX|process_data_0~q ;
wire \A_SPW_TOP|SPW|TX|state_tx~21_combout ;
wire \A_SPW_TOP|SPW|TX|state_tx~22_combout ;
wire \A_SPW_TOP|SPW|TX|Selector23~0_combout ;
wire \A_SPW_TOP|SPW|TX|state_tx~23_combout ;
wire \A_SPW_TOP|SPW|TX|state_tx~19_combout ;
wire \A_SPW_TOP|SPW|TX|state_tx~20_combout ;
wire \A_SPW_TOP|SPW|TX|state_tx~24_combout ;
wire \A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_c~q ;
wire \A_SPW_TOP|SPW|TX|Selector51~1_combout ;
wire \A_SPW_TOP|SPW|TX|Selector51~0_combout ;
wire \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~5_combout ;
wire \A_SPW_TOP|SPW|TX|Selector50~1_combout ;
wire \A_SPW_TOP|SPW|TX|Selector51~2_combout ;
wire \A_SPW_TOP|SPW|TX|tcode_rdy_trnsp~q ;
wire \A_SPW_TOP|SPW|TX|state_tx~27_combout ;
wire \A_SPW_TOP|SPW|TX|state_tx~28_combout ;
wire \A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct~q ;
wire \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~1_combout ;
wire \A_SPW_TOP|SPW|TX|LessThan6~1_combout ;
wire \A_SPW_TOP|SPW|TX|Selector72~0_combout ;
wire \A_SPW_TOP|SPW|TX|Equal0~0_combout ;
wire \A_SPW_TOP|SPW|TX|Selector72~1_combout ;
wire \A_SPW_TOP|SPW|TX|fct_sent~q ;
wire \A_SPW_TOP|SPW|TX|state_fct_send_p~12_combout ;
wire \A_SPW_TOP|SPW|TX|state_fct_send_p.001~q ;
wire \A_SPW_TOP|SPW|TX|state_fct_send_p.001~0_combout ;
wire \A_SPW_TOP|SPW|TX|state_fct_send_p~11_combout ;
wire \A_SPW_TOP|SPW|TX|state_fct_send_p.010~q ;
wire \A_SPW_TOP|SPW|TX|state_fct_send_p~9_combout ;
wire \A_SPW_TOP|SPW|TX|state_fct_send_p~10_combout ;
wire \A_SPW_TOP|SPW|TX|state_fct_send_p.000~q ;
wire \A_SPW_TOP|SPW|TX|Selector2~1_combout ;
wire \A_SPW_TOP|SPW|TX|clear_reg_fct_flag~q ;
wire \A_SPW_TOP|SPW|TX|fct_flag~1_combout ;
wire \A_SPW_TOP|SPW|TX|Selector2~0_combout ;
wire \A_SPW_TOP|SPW|TX|Selector6~0_combout ;
wire \A_SPW_TOP|SPW|TX|Selector6~1_combout ;
wire \A_SPW_TOP|SPW|TX|Selector5~0_combout ;
wire \A_SPW_TOP|SPW|TX|Selector5~1_combout ;
wire \A_SPW_TOP|SPW|TX|Selector4~0_combout ;
wire \A_SPW_TOP|SPW|TX|Selector4~1_combout ;
wire \A_SPW_TOP|SPW|TX|state_fct_send_p~8_combout ;
wire \A_SPW_TOP|SPW|TX|state_tx~32_combout ;
wire \A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct_c~q ;
wire \A_SPW_TOP|SPW|TX|Selector30~0_combout ;
wire \A_SPW_TOP|SPW|TX|Selector30~1_combout ;
wire \A_SPW_TOP|SPW|TX|Selector30~2_combout ;
wire \A_SPW_TOP|SPW|TX|Selector23~1_combout ;
wire \A_SPW_TOP|SPW|TX|Selector63~0_combout ;
wire \A_SPW_TOP|SPW|TX|WideOr12~combout ;
wire \A_SPW_TOP|SPW|TX|Selector73~0_combout ;
wire \A_SPW_TOP|SPW|TX|Selector73~2_combout ;
wire \A_SPW_TOP|SPW|TX|char_sent~q ;
wire \A_SPW_TOP|SPW|TX|Selector41~0_combout ;
wire \A_SPW_TOP|SPW|TX|Selector41~1_combout ;
wire \A_SPW_TOP|SPW|TX|Selector41~3_combout ;
wire \A_SPW_TOP|SPW|TX|Selector30~4_combout ;
wire \A_SPW_TOP|SPW|TX|Selector41~2_combout ;
wire \A_SPW_TOP|SPW|TX|Selector41~4_combout ;
wire \A_SPW_TOP|SPW|TX|process_data~q ;
wire \A_SPW_TOP|SPW|TX|state_tx~17_combout ;
wire \A_SPW_TOP|SPW|TX|state_tx~16_combout ;
wire \A_SPW_TOP|SPW|TX|state_tx~18_combout ;
wire \A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q ;
wire \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~2_combout ;
wire \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~3_combout ;
wire \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~4_combout ;
wire \A_SPW_TOP|SPW|TX|state_tx~12_combout ;
wire \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~q ;
wire \A_SPW_TOP|SPW|TX|Selector65~0_combout ;
wire \A_SPW_TOP|SPW|TX|Equal0~1_combout ;
wire \A_SPW_TOP|SPW|TX|state_tx~25_combout ;
wire \A_SPW_TOP|SPW|TX|state_tx~26_combout ;
wire \A_SPW_TOP|SPW|TX|state_tx.tx_spw_null~q ;
wire \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~0_combout ;
wire \A_SPW_TOP|SPW|TX|Add4~1_combout ;
wire \A_SPW_TOP|SPW|TX|Selector62~1_combout ;
wire \A_SPW_TOP|SPW|TX|Selector62~2_combout ;
wire \A_SPW_TOP|SPW|TX|Equal0~3_combout ;
wire \A_SPW_TOP|SPW|TX|Selector62~0_combout ;
wire \A_SPW_TOP|SPW|TX|Add4~0_combout ;
wire \A_SPW_TOP|SPW|TX|Selector63~1_combout ;
wire \A_SPW_TOP|SPW|TX|Selector63~2_combout ;
wire \u0|mm_interconnect_0|cmd_mux_010|src_payload~1_combout ;
wire \A_SPW_TOP|tx_data|Selector300~0_combout ;
wire \A_SPW_TOP|tx_data|mem[32][1]~q ;
wire \A_SPW_TOP|tx_data|Selector309~0_combout ;
wire \A_SPW_TOP|tx_data|mem[33][1]~q ;
wire \A_SPW_TOP|tx_data|Selector327~0_combout ;
wire \A_SPW_TOP|tx_data|mem[35][1]~q ;
wire \A_SPW_TOP|tx_data|Selector318~0_combout ;
wire \A_SPW_TOP|tx_data|mem[34][1]~q ;
wire \A_SPW_TOP|tx_data|Mux7~2_combout ;
wire \A_SPW_TOP|tx_data|Selector21~0_combout ;
wire \A_SPW_TOP|tx_data|mem[1][1]~q ;
wire \A_SPW_TOP|tx_data|Selector30~0_combout ;
wire \A_SPW_TOP|tx_data|mem[2][1]~q ;
wire \A_SPW_TOP|tx_data|Selector12~0_combout ;
wire \A_SPW_TOP|tx_data|mem[0][1]~q ;
wire \A_SPW_TOP|tx_data|Selector39~0_combout ;
wire \A_SPW_TOP|tx_data|mem[3][1]~q ;
wire \A_SPW_TOP|tx_data|Mux7~0_combout ;
wire \A_SPW_TOP|tx_data|Selector102~0_combout ;
wire \A_SPW_TOP|tx_data|mem[10][1]~q ;
wire \A_SPW_TOP|tx_data|Selector111~0_combout ;
wire \A_SPW_TOP|tx_data|mem[11][1]~q ;
wire \A_SPW_TOP|tx_data|Selector84~0_combout ;
wire \A_SPW_TOP|tx_data|mem[8][1]~q ;
wire \A_SPW_TOP|tx_data|Selector93~0_combout ;
wire \A_SPW_TOP|tx_data|mem[9][1]~feeder_combout ;
wire \A_SPW_TOP|tx_data|mem[9][1]~q ;
wire \A_SPW_TOP|tx_data|Mux7~1_combout ;
wire \A_SPW_TOP|tx_data|Selector399~0_combout ;
wire \A_SPW_TOP|tx_data|mem[43][1]~q ;
wire \A_SPW_TOP|tx_data|Selector381~0_combout ;
wire \A_SPW_TOP|tx_data|mem[41][1]~q ;
wire \A_SPW_TOP|tx_data|Selector372~0_combout ;
wire \A_SPW_TOP|tx_data|mem[40][1]~q ;
wire \A_SPW_TOP|tx_data|Selector390~0_combout ;
wire \A_SPW_TOP|tx_data|mem[42][1]~q ;
wire \A_SPW_TOP|tx_data|Mux7~3_combout ;
wire \A_SPW_TOP|tx_data|Mux7~4_combout ;
wire \A_SPW_TOP|tx_data|Selector210~0_combout ;
wire \A_SPW_TOP|tx_data|mem[22][1]~q ;
wire \A_SPW_TOP|tx_data|Selector507~0_combout ;
wire \A_SPW_TOP|tx_data|mem[55][1]~q ;
wire \A_SPW_TOP|tx_data|Selector498~0_combout ;
wire \A_SPW_TOP|tx_data|mem[54][1]~q ;
wire \A_SPW_TOP|tx_data|Selector219~0_combout ;
wire \A_SPW_TOP|tx_data|mem[23][1]~q ;
wire \A_SPW_TOP|tx_data|Mux7~17_combout ;
wire \A_SPW_TOP|tx_data|Selector291~0_combout ;
wire \A_SPW_TOP|tx_data|mem[31][1]~q ;
wire \A_SPW_TOP|tx_data|Selector282~0_combout ;
wire \A_SPW_TOP|tx_data|mem[30][1]~q ;
wire \A_SPW_TOP|tx_data|Selector579~0_combout ;
wire \A_SPW_TOP|tx_data|mem[63][1]~q ;
wire \A_SPW_TOP|tx_data|Selector570~0_combout ;
wire \A_SPW_TOP|tx_data|mem[62][1]~q ;
wire \A_SPW_TOP|tx_data|Mux7~18_combout ;
wire \A_SPW_TOP|tx_data|Selector552~0_combout ;
wire \A_SPW_TOP|tx_data|mem[60][1]~q ;
wire \A_SPW_TOP|tx_data|Selector264~0_combout ;
wire \A_SPW_TOP|tx_data|mem[28][1]~feeder_combout ;
wire \A_SPW_TOP|tx_data|mem[28][1]~q ;
wire \A_SPW_TOP|tx_data|Selector273~0_combout ;
wire \A_SPW_TOP|tx_data|mem[29][1]~q ;
wire \A_SPW_TOP|tx_data|Selector561~0_combout ;
wire \A_SPW_TOP|tx_data|mem[61][1]~q ;
wire \A_SPW_TOP|tx_data|Mux7~16_combout ;
wire \A_SPW_TOP|tx_data|Selector201~0_combout ;
wire \A_SPW_TOP|tx_data|mem[21][1]~q ;
wire \A_SPW_TOP|tx_data|Selector192~0_combout ;
wire \A_SPW_TOP|tx_data|mem[20][1]~q ;
wire \A_SPW_TOP|tx_data|Selector480~0_combout ;
wire \A_SPW_TOP|tx_data|mem[52][1]~q ;
wire \A_SPW_TOP|tx_data|Selector489~0_combout ;
wire \A_SPW_TOP|tx_data|mem[53][1]~q ;
wire \A_SPW_TOP|tx_data|Mux7~15_combout ;
wire \A_SPW_TOP|tx_data|Mux7~19_combout ;
wire \A_SPW_TOP|tx_data|Selector471~0_combout ;
wire \A_SPW_TOP|tx_data|mem[51][1]~q ;
wire \A_SPW_TOP|tx_data|Selector462~0_combout ;
wire \A_SPW_TOP|tx_data|mem[50][1]~q ;
wire \A_SPW_TOP|tx_data|Selector453~0_combout ;
wire \A_SPW_TOP|tx_data|mem[49][1]~q ;
wire \A_SPW_TOP|tx_data|Selector444~0_combout ;
wire \A_SPW_TOP|tx_data|mem[48][1]~q ;
wire \A_SPW_TOP|tx_data|Mux7~7_combout ;
wire \A_SPW_TOP|tx_data|Selector246~0_combout ;
wire \A_SPW_TOP|tx_data|mem[26][1]~q ;
wire \A_SPW_TOP|tx_data|Selector237~0_combout ;
wire \A_SPW_TOP|tx_data|mem[25][1]~feeder_combout ;
wire \A_SPW_TOP|tx_data|mem[25][1]~q ;
wire \A_SPW_TOP|tx_data|Selector228~0_combout ;
wire \A_SPW_TOP|tx_data|mem[24][1]~q ;
wire \A_SPW_TOP|tx_data|Selector255~0_combout ;
wire \A_SPW_TOP|tx_data|mem[27][1]~feeder_combout ;
wire \A_SPW_TOP|tx_data|mem[27][1]~q ;
wire \A_SPW_TOP|tx_data|Mux7~6_combout ;
wire \A_SPW_TOP|tx_data|Selector165~0_combout ;
wire \A_SPW_TOP|tx_data|mem[17][1]~q ;
wire \A_SPW_TOP|tx_data|Selector174~0_combout ;
wire \A_SPW_TOP|tx_data|mem[18][1]~q ;
wire \A_SPW_TOP|tx_data|Selector183~0_combout ;
wire \A_SPW_TOP|tx_data|mem[19][1]~q ;
wire \A_SPW_TOP|tx_data|Selector156~0_combout ;
wire \A_SPW_TOP|tx_data|mem[16][1]~q ;
wire \A_SPW_TOP|tx_data|Mux7~5_combout ;
wire \A_SPW_TOP|tx_data|Selector543~0_combout ;
wire \A_SPW_TOP|tx_data|mem[59][1]~q ;
wire \A_SPW_TOP|tx_data|Selector525~0_combout ;
wire \A_SPW_TOP|tx_data|mem[57][1]~q ;
wire \A_SPW_TOP|tx_data|Selector516~0_combout ;
wire \A_SPW_TOP|tx_data|mem[56][1]~q ;
wire \A_SPW_TOP|tx_data|Selector534~0_combout ;
wire \A_SPW_TOP|tx_data|mem[58][1]~q ;
wire \A_SPW_TOP|tx_data|Mux7~8_combout ;
wire \A_SPW_TOP|tx_data|Mux7~9_combout ;
wire \A_SPW_TOP|tx_data|Selector426~0_combout ;
wire \A_SPW_TOP|tx_data|mem[46][1]~q ;
wire \A_SPW_TOP|tx_data|Selector435~0_combout ;
wire \A_SPW_TOP|tx_data|mem[47][1]~q ;
wire \A_SPW_TOP|tx_data|Selector417~0_combout ;
wire \A_SPW_TOP|tx_data|mem[45][1]~q ;
wire \A_SPW_TOP|tx_data|Selector408~0_combout ;
wire \A_SPW_TOP|tx_data|mem[44][1]~q ;
wire \A_SPW_TOP|tx_data|Mux7~13_combout ;
wire \A_SPW_TOP|tx_data|Selector66~0_combout ;
wire \A_SPW_TOP|tx_data|mem[6][1]~q ;
wire \A_SPW_TOP|tx_data|Selector57~0_combout ;
wire \A_SPW_TOP|tx_data|mem[5][1]~q ;
wire \A_SPW_TOP|tx_data|Selector48~0_combout ;
wire \A_SPW_TOP|tx_data|mem[4][1]~q ;
wire \A_SPW_TOP|tx_data|Selector75~0_combout ;
wire \A_SPW_TOP|tx_data|mem[7][1]~q ;
wire \A_SPW_TOP|tx_data|Mux7~10_combout ;
wire \A_SPW_TOP|tx_data|Selector363~0_combout ;
wire \A_SPW_TOP|tx_data|mem[39][1]~q ;
wire \A_SPW_TOP|tx_data|Selector354~0_combout ;
wire \A_SPW_TOP|tx_data|mem[38][1]~q ;
wire \A_SPW_TOP|tx_data|Selector345~0_combout ;
wire \A_SPW_TOP|tx_data|mem[37][1]~q ;
wire \A_SPW_TOP|tx_data|Selector336~0_combout ;
wire \A_SPW_TOP|tx_data|mem[36][1]~q ;
wire \A_SPW_TOP|tx_data|Mux7~12_combout ;
wire \A_SPW_TOP|tx_data|Selector138~0_combout ;
wire \A_SPW_TOP|tx_data|mem[14][1]~q ;
wire \A_SPW_TOP|tx_data|Selector147~0_combout ;
wire \A_SPW_TOP|tx_data|mem[15][1]~q ;
wire \A_SPW_TOP|tx_data|Selector120~0_combout ;
wire \A_SPW_TOP|tx_data|mem[12][1]~q ;
wire \A_SPW_TOP|tx_data|Mux7~11_combout ;
wire \A_SPW_TOP|tx_data|Mux7~14_combout ;
wire \A_SPW_TOP|tx_data|Mux7~20_combout ;
wire \A_SPW_TOP|tx_data|Selector129~0_combout ;
wire \A_SPW_TOP|tx_data|mem[13][1]~q ;
wire \A_SPW_TOP|tx_data|Mux16~12_combout ;
wire \A_SPW_TOP|tx_data|Mux16~13_combout ;
wire \A_SPW_TOP|tx_data|Mux16~10_combout ;
wire \A_SPW_TOP|tx_data|Mux16~11_combout ;
wire \A_SPW_TOP|tx_data|Mux16~14_combout ;
wire \A_SPW_TOP|tx_data|Mux16~7_combout ;
wire \A_SPW_TOP|tx_data|Mux16~6_combout ;
wire \A_SPW_TOP|tx_data|Mux16~8_combout ;
wire \A_SPW_TOP|tx_data|Mux16~5_combout ;
wire \A_SPW_TOP|tx_data|Mux16~9_combout ;
wire \A_SPW_TOP|tx_data|Mux16~1_combout ;
wire \A_SPW_TOP|tx_data|Mux16~0_combout ;
wire \A_SPW_TOP|tx_data|Mux16~2_combout ;
wire \A_SPW_TOP|tx_data|Mux16~3_combout ;
wire \A_SPW_TOP|tx_data|Mux16~4_combout ;
wire \A_SPW_TOP|tx_data|Mux16~18_combout ;
wire \A_SPW_TOP|tx_data|Mux16~17_combout ;
wire \A_SPW_TOP|tx_data|Mux16~16_combout ;
wire \A_SPW_TOP|tx_data|Mux16~15_combout ;
wire \A_SPW_TOP|tx_data|Mux16~19_combout ;
wire \A_SPW_TOP|tx_data|Mux16~20_combout ;
wire \A_SPW_TOP|SPW|TX|Selector30~3_combout ;
wire \A_SPW_TOP|SPW|TX|last_type~11_combout ;
wire \A_SPW_TOP|SPW|TX|Selector67~0_combout ;
wire \A_SPW_TOP|SPW|TX|Selector39~1_combout ;
wire \A_SPW_TOP|SPW|TX|last_type~10_combout ;
wire \A_SPW_TOP|SPW|TX|Selector67~1_combout ;
wire \A_SPW_TOP|SPW|TX|LessThan5~0_combout ;
wire \A_SPW_TOP|SPW|TX|Selector67~3_combout ;
wire \A_SPW_TOP|SPW|TX|Selector67~2_combout ;
wire \A_SPW_TOP|SPW|TX|Selector71~0_combout ;
wire \A_SPW_TOP|SPW|TX|last_type~15_combout ;
wire \A_SPW_TOP|SPW|TX|Selector68~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_010|src_payload~0_combout ;
wire \u0|write_data_fifo_tx|data_out[0]~feeder_combout ;
wire \A_SPW_TOP|tx_data|Selector481~0_combout ;
wire \A_SPW_TOP|tx_data|mem[52][0]~q ;
wire \A_SPW_TOP|tx_data|Selector301~0_combout ;
wire \A_SPW_TOP|tx_data|mem[32][0]~q ;
wire \A_SPW_TOP|tx_data|Selector445~0_combout ;
wire \A_SPW_TOP|tx_data|mem[48][0]~q ;
wire \A_SPW_TOP|tx_data|Selector337~0_combout ;
wire \A_SPW_TOP|tx_data|mem[36][0]~q ;
wire \A_SPW_TOP|tx_data|Mux8~10_combout ;
wire \A_SPW_TOP|tx_data|Selector490~0_combout ;
wire \A_SPW_TOP|tx_data|mem[53][0]~q ;
wire \A_SPW_TOP|tx_data|Selector346~0_combout ;
wire \A_SPW_TOP|tx_data|mem[37][0]~q ;
wire \A_SPW_TOP|tx_data|Selector454~0_combout ;
wire \A_SPW_TOP|tx_data|mem[49][0]~q ;
wire \A_SPW_TOP|tx_data|Selector310~0_combout ;
wire \A_SPW_TOP|tx_data|mem[33][0]~q ;
wire \A_SPW_TOP|tx_data|Mux8~11_combout ;
wire \A_SPW_TOP|tx_data|Selector499~0_combout ;
wire \A_SPW_TOP|tx_data|mem[54][0]~q ;
wire \A_SPW_TOP|tx_data|Selector319~0_combout ;
wire \A_SPW_TOP|tx_data|mem[34][0]~q ;
wire \A_SPW_TOP|tx_data|Selector355~0_combout ;
wire \A_SPW_TOP|tx_data|mem[38][0]~q ;
wire \A_SPW_TOP|tx_data|Selector463~0_combout ;
wire \A_SPW_TOP|tx_data|mem[50][0]~q ;
wire \A_SPW_TOP|tx_data|Mux8~12_combout ;
wire \A_SPW_TOP|tx_data|Selector508~0_combout ;
wire \A_SPW_TOP|tx_data|mem[55][0]~q ;
wire \A_SPW_TOP|tx_data|Selector328~0_combout ;
wire \A_SPW_TOP|tx_data|mem[35][0]~q ;
wire \A_SPW_TOP|tx_data|Selector472~0_combout ;
wire \A_SPW_TOP|tx_data|mem[51][0]~q ;
wire \A_SPW_TOP|tx_data|Selector364~0_combout ;
wire \A_SPW_TOP|tx_data|mem[39][0]~q ;
wire \A_SPW_TOP|tx_data|Mux8~13_combout ;
wire \A_SPW_TOP|tx_data|Mux8~14_combout ;
wire \A_SPW_TOP|tx_data|Selector139~0_combout ;
wire \A_SPW_TOP|tx_data|mem[14][0]~q ;
wire \A_SPW_TOP|tx_data|Selector283~0_combout ;
wire \A_SPW_TOP|tx_data|mem[30][0]~q ;
wire \A_SPW_TOP|tx_data|Selector103~0_combout ;
wire \A_SPW_TOP|tx_data|mem[10][0]~q ;
wire \A_SPW_TOP|tx_data|Selector247~0_combout ;
wire \A_SPW_TOP|tx_data|mem[26][0]~q ;
wire \A_SPW_TOP|tx_data|Mux8~7_combout ;
wire \A_SPW_TOP|tx_data|Selector256~0_combout ;
wire \A_SPW_TOP|tx_data|mem[27][0]~q ;
wire \A_SPW_TOP|tx_data|Selector292~0_combout ;
wire \A_SPW_TOP|tx_data|mem[31][0]~q ;
wire \A_SPW_TOP|tx_data|Selector112~0_combout ;
wire \A_SPW_TOP|tx_data|mem[11][0]~q ;
wire \A_SPW_TOP|tx_data|Selector148~0_combout ;
wire \A_SPW_TOP|tx_data|mem[15][0]~feeder_combout ;
wire \A_SPW_TOP|tx_data|mem[15][0]~q ;
wire \A_SPW_TOP|tx_data|Mux8~8_combout ;
wire \A_SPW_TOP|tx_data|Selector229~0_combout ;
wire \A_SPW_TOP|tx_data|mem[24][0]~q ;
wire \A_SPW_TOP|tx_data|Selector265~0_combout ;
wire \A_SPW_TOP|tx_data|mem[28][0]~q ;
wire \A_SPW_TOP|tx_data|Selector85~0_combout ;
wire \A_SPW_TOP|tx_data|mem[8][0]~q ;
wire \A_SPW_TOP|tx_data|Selector121~0_combout ;
wire \A_SPW_TOP|tx_data|mem[12][0]~q ;
wire \A_SPW_TOP|tx_data|Mux8~5_combout ;
wire \A_SPW_TOP|tx_data|Selector94~0_combout ;
wire \A_SPW_TOP|tx_data|mem[9][0]~q ;
wire \A_SPW_TOP|tx_data|Selector274~0_combout ;
wire \A_SPW_TOP|tx_data|mem[29][0]~q ;
wire \A_SPW_TOP|tx_data|Selector238~0_combout ;
wire \A_SPW_TOP|tx_data|mem[25][0]~q ;
wire \A_SPW_TOP|tx_data|Selector130~0_combout ;
wire \A_SPW_TOP|tx_data|mem[13][0]~q ;
wire \A_SPW_TOP|tx_data|Mux8~6_combout ;
wire \A_SPW_TOP|tx_data|Mux8~9_combout ;
wire \A_SPW_TOP|tx_data|Selector418~0_combout ;
wire \A_SPW_TOP|tx_data|mem[45][0]~q ;
wire \A_SPW_TOP|tx_data|Selector436~0_combout ;
wire \A_SPW_TOP|tx_data|mem[47][0]~q ;
wire \A_SPW_TOP|tx_data|Selector562~0_combout ;
wire \A_SPW_TOP|tx_data|mem[61][0]~q ;
wire \A_SPW_TOP|tx_data|Selector580~0_combout ;
wire \A_SPW_TOP|tx_data|mem[63][0]~q ;
wire \A_SPW_TOP|tx_data|Mux8~18_combout ;
wire \A_SPW_TOP|tx_data|Selector373~0_combout ;
wire \A_SPW_TOP|tx_data|mem[40][0]~q ;
wire \A_SPW_TOP|tx_data|Selector391~0_combout ;
wire \A_SPW_TOP|tx_data|mem[42][0]~q ;
wire \A_SPW_TOP|tx_data|Selector535~0_combout ;
wire \A_SPW_TOP|tx_data|mem[58][0]~q ;
wire \A_SPW_TOP|tx_data|Selector517~0_combout ;
wire \A_SPW_TOP|tx_data|mem[56][0]~q ;
wire \A_SPW_TOP|tx_data|Mux8~15_combout ;
wire \A_SPW_TOP|tx_data|Selector526~0_combout ;
wire \A_SPW_TOP|tx_data|mem[57][0]~q ;
wire \A_SPW_TOP|tx_data|Selector544~0_combout ;
wire \A_SPW_TOP|tx_data|mem[59][0]~q ;
wire \A_SPW_TOP|tx_data|Selector382~0_combout ;
wire \A_SPW_TOP|tx_data|mem[41][0]~q ;
wire \A_SPW_TOP|tx_data|Selector400~0_combout ;
wire \A_SPW_TOP|tx_data|mem[43][0]~q ;
wire \A_SPW_TOP|tx_data|Mux8~16_combout ;
wire \A_SPW_TOP|tx_data|Selector553~0_combout ;
wire \A_SPW_TOP|tx_data|mem[60][0]~q ;
wire \A_SPW_TOP|tx_data|Selector427~0_combout ;
wire \A_SPW_TOP|tx_data|mem[46][0]~q ;
wire \A_SPW_TOP|tx_data|Selector409~0_combout ;
wire \A_SPW_TOP|tx_data|mem[44][0]~q ;
wire \A_SPW_TOP|tx_data|Selector571~0_combout ;
wire \A_SPW_TOP|tx_data|mem[62][0]~q ;
wire \A_SPW_TOP|tx_data|Mux8~17_combout ;
wire \A_SPW_TOP|tx_data|Mux8~19_combout ;
wire \A_SPW_TOP|tx_data|Selector166~0_combout ;
wire \A_SPW_TOP|tx_data|mem[17][0]~q ;
wire \A_SPW_TOP|tx_data|Selector22~0_combout ;
wire \A_SPW_TOP|tx_data|mem[1][0]~q ;
wire \A_SPW_TOP|tx_data|Selector202~0_combout ;
wire \A_SPW_TOP|tx_data|mem[21][0]~q ;
wire \A_SPW_TOP|tx_data|Selector58~0_combout ;
wire \A_SPW_TOP|tx_data|mem[5][0]~q ;
wire \A_SPW_TOP|tx_data|Mux8~1_combout ;
wire \A_SPW_TOP|tx_data|Selector49~0_combout ;
wire \A_SPW_TOP|tx_data|mem[4][0]~q ;
wire \A_SPW_TOP|tx_data|Selector157~0_combout ;
wire \A_SPW_TOP|tx_data|mem[16][0]~q ;
wire \A_SPW_TOP|tx_data|Selector193~0_combout ;
wire \A_SPW_TOP|tx_data|mem[20][0]~q ;
wire \A_SPW_TOP|tx_data|Selector13~0_combout ;
wire \A_SPW_TOP|tx_data|mem[0][0]~q ;
wire \A_SPW_TOP|tx_data|Mux8~0_combout ;
wire \A_SPW_TOP|tx_data|Selector40~0_combout ;
wire \A_SPW_TOP|tx_data|mem[3][0]~q ;
wire \A_SPW_TOP|tx_data|Selector76~0_combout ;
wire \A_SPW_TOP|tx_data|mem[7][0]~q ;
wire \A_SPW_TOP|tx_data|Selector184~0_combout ;
wire \A_SPW_TOP|tx_data|mem[19][0]~q ;
wire \A_SPW_TOP|tx_data|Selector220~0_combout ;
wire \A_SPW_TOP|tx_data|mem[23][0]~q ;
wire \A_SPW_TOP|tx_data|Mux8~3_combout ;
wire \A_SPW_TOP|tx_data|Selector31~0_combout ;
wire \A_SPW_TOP|tx_data|mem[2][0]~q ;
wire \A_SPW_TOP|tx_data|Selector175~0_combout ;
wire \A_SPW_TOP|tx_data|mem[18][0]~q ;
wire \A_SPW_TOP|tx_data|Selector67~0_combout ;
wire \A_SPW_TOP|tx_data|mem[6][0]~q ;
wire \A_SPW_TOP|tx_data|Mux8~2_combout ;
wire \A_SPW_TOP|tx_data|Mux8~4_combout ;
wire \A_SPW_TOP|tx_data|Mux8~20_combout ;
wire \A_SPW_TOP|tx_data|Selector211~0_combout ;
wire \A_SPW_TOP|tx_data|mem[22][0]~q ;
wire \A_SPW_TOP|tx_data|Mux17~2_combout ;
wire \A_SPW_TOP|tx_data|Mux17~1_combout ;
wire \A_SPW_TOP|tx_data|Mux17~3_combout ;
wire \A_SPW_TOP|tx_data|Mux17~0_combout ;
wire \A_SPW_TOP|tx_data|Mux17~4_combout ;
wire \A_SPW_TOP|tx_data|Mux17~12_combout ;
wire \A_SPW_TOP|tx_data|Mux17~13_combout ;
wire \A_SPW_TOP|tx_data|Mux17~10_combout ;
wire \A_SPW_TOP|tx_data|Mux17~11_combout ;
wire \A_SPW_TOP|tx_data|Mux17~14_combout ;
wire \A_SPW_TOP|tx_data|Mux17~17_combout ;
wire \A_SPW_TOP|tx_data|Mux17~16_combout ;
wire \A_SPW_TOP|tx_data|Mux17~15_combout ;
wire \A_SPW_TOP|tx_data|Mux17~18_combout ;
wire \A_SPW_TOP|tx_data|Mux17~19_combout ;
wire \A_SPW_TOP|tx_data|Mux17~6_combout ;
wire \A_SPW_TOP|tx_data|Mux17~5_combout ;
wire \A_SPW_TOP|tx_data|Mux17~8_combout ;
wire \A_SPW_TOP|tx_data|Mux17~7_combout ;
wire \A_SPW_TOP|tx_data|Mux17~9_combout ;
wire \A_SPW_TOP|tx_data|Mux17~20_combout ;
wire \A_SPW_TOP|SPW|TX|Selector31~0_combout ;
wire \A_SPW_TOP|SPW|TX|last_type~12_combout ;
wire \A_SPW_TOP|SPW|TX|Selector68~1_combout ;
wire \A_SPW_TOP|SPW|TX|Selector40~1_combout ;
wire \A_SPW_TOP|SPW|TX|last_type~13_combout ;
wire \A_SPW_TOP|SPW|TX|Selector68~2_combout ;
wire \A_SPW_TOP|SPW|TX|last_type~17_combout ;
wire \A_SPW_TOP|SPW|TX|last_type.EOP~q ;
wire \A_SPW_TOP|SPW|TX|Selector70~1_combout ;
wire \A_SPW_TOP|SPW|TX|Selector70~0_combout ;
wire \A_SPW_TOP|SPW|TX|last_type~14_combout ;
wire \A_SPW_TOP|SPW|TX|Selector70~2_combout ;
wire \A_SPW_TOP|SPW|TX|Selector70~3_combout ;
wire \A_SPW_TOP|SPW|TX|last_type~16_combout ;
wire \A_SPW_TOP|SPW|TX|last_type.DATA~q ;
wire \A_SPW_TOP|SPW|TX|Selector69~2_combout ;
wire \A_SPW_TOP|SPW|TX|Selector69~0_combout ;
wire \A_SPW_TOP|SPW|TX|Selector69~1_combout ;
wire \A_SPW_TOP|SPW|TX|last_type~18_combout ;
wire \A_SPW_TOP|SPW|TX|last_type.EEP~q ;
wire \A_SPW_TOP|SPW|TX|last_type~24_combout ;
wire \A_SPW_TOP|SPW|TX|last_type.TIMEC~q ;
wire \A_SPW_TOP|SPW|TX|last_type~19_combout ;
wire \A_SPW_TOP|SPW|TX|last_type~21_combout ;
wire \A_SPW_TOP|SPW|TX|last_type~20_combout ;
wire \A_SPW_TOP|SPW|TX|last_type~22_combout ;
wire \A_SPW_TOP|SPW|TX|last_type.NULL~q ;
wire \A_SPW_TOP|SPW|TX|last_type.NULL~0_combout ;
wire \A_SPW_TOP|SPW|TX|last_type~23_combout ;
wire \A_SPW_TOP|SPW|TX|last_type.FCT~q ;
wire \A_SPW_TOP|SPW|TX|always0~11_combout ;
wire \A_SPW_TOP|SPW|TX|always0~10_combout ;
wire \A_SPW_TOP|SPW|TX|always0~7_combout ;
wire \A_SPW_TOP|SPW|TX|always0~6_combout ;
wire \A_SPW_TOP|SPW|TX|always0~8_combout ;
wire \A_SPW_TOP|SPW|TX|always0~9_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout~23_combout ;
wire \A_SPW_TOP|SPW|TX|Equal0~2_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout~21_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout~16_combout ;
wire \u0|mm_interconnect_0|cmd_mux_010|src_payload~2_combout ;
wire \A_SPW_TOP|tx_data|Selector479~0_combout ;
wire \A_SPW_TOP|tx_data|mem[52][2]~q ;
wire \A_SPW_TOP|tx_data|Selector263~0_combout ;
wire \A_SPW_TOP|tx_data|mem[28][2]~q ;
wire \A_SPW_TOP|tx_data|Selector551~0_combout ;
wire \A_SPW_TOP|tx_data|mem[60][2]~q ;
wire \A_SPW_TOP|tx_data|Selector191~0_combout ;
wire \A_SPW_TOP|tx_data|mem[20][2]~q ;
wire \A_SPW_TOP|tx_data|Mux6~3_combout ;
wire \A_SPW_TOP|tx_data|Selector83~0_combout ;
wire \A_SPW_TOP|tx_data|mem[8][2]~q ;
wire \A_SPW_TOP|tx_data|Selector299~0_combout ;
wire \A_SPW_TOP|tx_data|mem[32][2]~q ;
wire \A_SPW_TOP|tx_data|Selector11~0_combout ;
wire \A_SPW_TOP|tx_data|mem[0][2]~q ;
wire \A_SPW_TOP|tx_data|Selector371~0_combout ;
wire \A_SPW_TOP|tx_data|mem[40][2]~q ;
wire \A_SPW_TOP|tx_data|Mux6~0_combout ;
wire \A_SPW_TOP|tx_data|Selector119~0_combout ;
wire \A_SPW_TOP|tx_data|mem[12][2]~q ;
wire \A_SPW_TOP|tx_data|Selector335~0_combout ;
wire \A_SPW_TOP|tx_data|mem[36][2]~q ;
wire \A_SPW_TOP|tx_data|Selector407~0_combout ;
wire \A_SPW_TOP|tx_data|mem[44][2]~q ;
wire \A_SPW_TOP|tx_data|Selector47~0_combout ;
wire \A_SPW_TOP|tx_data|mem[4][2]~q ;
wire \A_SPW_TOP|tx_data|Mux6~1_combout ;
wire \A_SPW_TOP|tx_data|Selector515~0_combout ;
wire \A_SPW_TOP|tx_data|mem[56][2]~q ;
wire \A_SPW_TOP|tx_data|Selector155~0_combout ;
wire \A_SPW_TOP|tx_data|mem[16][2]~q ;
wire \A_SPW_TOP|tx_data|Selector443~0_combout ;
wire \A_SPW_TOP|tx_data|mem[48][2]~q ;
wire \A_SPW_TOP|tx_data|Selector227~0_combout ;
wire \A_SPW_TOP|tx_data|mem[24][2]~q ;
wire \A_SPW_TOP|tx_data|Mux6~2_combout ;
wire \A_SPW_TOP|tx_data|Mux6~4_combout ;
wire \A_SPW_TOP|tx_data|Selector128~0_combout ;
wire \A_SPW_TOP|tx_data|mem[13][2]~q ;
wire \A_SPW_TOP|tx_data|Selector56~0_combout ;
wire \A_SPW_TOP|tx_data|mem[5][2]~q ;
wire \A_SPW_TOP|tx_data|Selector344~0_combout ;
wire \A_SPW_TOP|tx_data|mem[37][2]~q ;
wire \A_SPW_TOP|tx_data|Selector416~0_combout ;
wire \A_SPW_TOP|tx_data|mem[45][2]~q ;
wire \A_SPW_TOP|tx_data|Mux6~6_combout ;
wire \A_SPW_TOP|tx_data|Selector308~0_combout ;
wire \A_SPW_TOP|tx_data|mem[33][2]~q ;
wire \A_SPW_TOP|tx_data|Selector380~0_combout ;
wire \A_SPW_TOP|tx_data|mem[41][2]~q ;
wire \A_SPW_TOP|tx_data|Selector92~0_combout ;
wire \A_SPW_TOP|tx_data|mem[9][2]~q ;
wire \A_SPW_TOP|tx_data|Mux6~5_combout ;
wire \A_SPW_TOP|tx_data|Selector272~0_combout ;
wire \A_SPW_TOP|tx_data|mem[29][2]~q ;
wire \A_SPW_TOP|tx_data|Selector560~0_combout ;
wire \A_SPW_TOP|tx_data|mem[61][2]~q ;
wire \A_SPW_TOP|tx_data|Selector200~0_combout ;
wire \A_SPW_TOP|tx_data|mem[21][2]~q ;
wire \A_SPW_TOP|tx_data|Selector488~0_combout ;
wire \A_SPW_TOP|tx_data|mem[53][2]~q ;
wire \A_SPW_TOP|tx_data|Mux6~8_combout ;
wire \A_SPW_TOP|tx_data|Selector236~0_combout ;
wire \A_SPW_TOP|tx_data|mem[25][2]~q ;
wire \A_SPW_TOP|tx_data|Selector524~0_combout ;
wire \A_SPW_TOP|tx_data|mem[57][2]~q ;
wire \A_SPW_TOP|tx_data|Selector452~0_combout ;
wire \A_SPW_TOP|tx_data|mem[49][2]~q ;
wire \A_SPW_TOP|tx_data|Selector164~0_combout ;
wire \A_SPW_TOP|tx_data|mem[17][2]~q ;
wire \A_SPW_TOP|tx_data|Mux6~7_combout ;
wire \A_SPW_TOP|tx_data|Mux6~9_combout ;
wire \A_SPW_TOP|tx_data|Selector434~0_combout ;
wire \A_SPW_TOP|tx_data|mem[47][2]~q ;
wire \A_SPW_TOP|tx_data|Selector362~0_combout ;
wire \A_SPW_TOP|tx_data|mem[39][2]~q ;
wire \A_SPW_TOP|tx_data|Selector326~0_combout ;
wire \A_SPW_TOP|tx_data|mem[35][2]~q ;
wire \A_SPW_TOP|tx_data|Selector398~0_combout ;
wire \A_SPW_TOP|tx_data|mem[43][2]~q ;
wire \A_SPW_TOP|tx_data|Mux6~16_combout ;
wire \A_SPW_TOP|tx_data|Selector290~0_combout ;
wire \A_SPW_TOP|tx_data|mem[31][2]~q ;
wire \A_SPW_TOP|tx_data|Selector254~0_combout ;
wire \A_SPW_TOP|tx_data|mem[27][2]~q ;
wire \A_SPW_TOP|tx_data|Selector218~0_combout ;
wire \A_SPW_TOP|tx_data|mem[23][2]~q ;
wire \A_SPW_TOP|tx_data|Selector182~0_combout ;
wire \A_SPW_TOP|tx_data|mem[19][2]~q ;
wire \A_SPW_TOP|tx_data|Mux6~17_combout ;
wire \A_SPW_TOP|tx_data|Selector542~0_combout ;
wire \A_SPW_TOP|tx_data|mem[59][2]~q ;
wire \A_SPW_TOP|tx_data|Selector506~0_combout ;
wire \A_SPW_TOP|tx_data|mem[55][2]~q ;
wire \A_SPW_TOP|tx_data|Selector578~0_combout ;
wire \A_SPW_TOP|tx_data|mem[63][2]~q ;
wire \A_SPW_TOP|tx_data|Selector470~0_combout ;
wire \A_SPW_TOP|tx_data|mem[51][2]~q ;
wire \A_SPW_TOP|tx_data|Mux6~18_combout ;
wire \A_SPW_TOP|tx_data|Selector74~0_combout ;
wire \A_SPW_TOP|tx_data|mem[7][2]~q ;
wire \A_SPW_TOP|tx_data|Selector146~0_combout ;
wire \A_SPW_TOP|tx_data|mem[15][2]~q ;
wire \A_SPW_TOP|tx_data|Selector38~0_combout ;
wire \A_SPW_TOP|tx_data|mem[3][2]~q ;
wire \A_SPW_TOP|tx_data|Selector110~0_combout ;
wire \A_SPW_TOP|tx_data|mem[11][2]~q ;
wire \A_SPW_TOP|tx_data|Mux6~15_combout ;
wire \A_SPW_TOP|tx_data|Mux6~19_combout ;
wire \A_SPW_TOP|tx_data|Selector353~0_combout ;
wire \A_SPW_TOP|tx_data|mem[38][2]~q ;
wire \A_SPW_TOP|tx_data|Selector425~0_combout ;
wire \A_SPW_TOP|tx_data|mem[46][2]~q ;
wire \A_SPW_TOP|tx_data|Selector65~0_combout ;
wire \A_SPW_TOP|tx_data|mem[6][2]~q ;
wire \A_SPW_TOP|tx_data|Selector137~0_combout ;
wire \A_SPW_TOP|tx_data|mem[14][2]~q ;
wire \A_SPW_TOP|tx_data|Mux6~11_combout ;
wire \A_SPW_TOP|tx_data|Selector389~0_combout ;
wire \A_SPW_TOP|tx_data|mem[42][2]~q ;
wire \A_SPW_TOP|tx_data|Selector29~0_combout ;
wire \A_SPW_TOP|tx_data|mem[2][2]~feeder_combout ;
wire \A_SPW_TOP|tx_data|mem[2][2]~q ;
wire \A_SPW_TOP|tx_data|Selector101~0_combout ;
wire \A_SPW_TOP|tx_data|mem[10][2]~q ;
wire \A_SPW_TOP|tx_data|Selector317~0_combout ;
wire \A_SPW_TOP|tx_data|mem[34][2]~q ;
wire \A_SPW_TOP|tx_data|Mux6~10_combout ;
wire \A_SPW_TOP|tx_data|Selector461~0_combout ;
wire \A_SPW_TOP|tx_data|mem[50][2]~q ;
wire \A_SPW_TOP|tx_data|Selector173~0_combout ;
wire \A_SPW_TOP|tx_data|mem[18][2]~q ;
wire \A_SPW_TOP|tx_data|Selector533~0_combout ;
wire \A_SPW_TOP|tx_data|mem[58][2]~q ;
wire \A_SPW_TOP|tx_data|Selector245~0_combout ;
wire \A_SPW_TOP|tx_data|mem[26][2]~q ;
wire \A_SPW_TOP|tx_data|Mux6~12_combout ;
wire \A_SPW_TOP|tx_data|Selector497~0_combout ;
wire \A_SPW_TOP|tx_data|mem[54][2]~q ;
wire \A_SPW_TOP|tx_data|Selector281~0_combout ;
wire \A_SPW_TOP|tx_data|mem[30][2]~q ;
wire \A_SPW_TOP|tx_data|Selector569~0_combout ;
wire \A_SPW_TOP|tx_data|mem[62][2]~q ;
wire \A_SPW_TOP|tx_data|Selector209~0_combout ;
wire \A_SPW_TOP|tx_data|mem[22][2]~q ;
wire \A_SPW_TOP|tx_data|Mux6~13_combout ;
wire \A_SPW_TOP|tx_data|Mux6~14_combout ;
wire \A_SPW_TOP|tx_data|Mux6~20_combout ;
wire \A_SPW_TOP|tx_data|Selector20~0_combout ;
wire \A_SPW_TOP|tx_data|mem[1][2]~q ;
wire \A_SPW_TOP|tx_data|Mux15~10_combout ;
wire \A_SPW_TOP|tx_data|Mux15~13_combout ;
wire \A_SPW_TOP|tx_data|Mux15~12_combout ;
wire \A_SPW_TOP|tx_data|Mux15~11_combout ;
wire \A_SPW_TOP|tx_data|Mux15~14_combout ;
wire \A_SPW_TOP|tx_data|Mux15~16_combout ;
wire \A_SPW_TOP|tx_data|Mux15~15_combout ;
wire \A_SPW_TOP|tx_data|Mux15~18_combout ;
wire \A_SPW_TOP|tx_data|Mux15~17_combout ;
wire \A_SPW_TOP|tx_data|Mux15~19_combout ;
wire \A_SPW_TOP|tx_data|Mux15~3_combout ;
wire \A_SPW_TOP|tx_data|Mux15~1_combout ;
wire \A_SPW_TOP|tx_data|Mux15~0_combout ;
wire \A_SPW_TOP|tx_data|Mux15~2_combout ;
wire \A_SPW_TOP|tx_data|Mux15~4_combout ;
wire \A_SPW_TOP|tx_data|Mux15~8_combout ;
wire \A_SPW_TOP|tx_data|Mux15~5_combout ;
wire \A_SPW_TOP|tx_data|Mux15~7_combout ;
wire \A_SPW_TOP|tx_data|Mux15~6_combout ;
wire \A_SPW_TOP|tx_data|Mux15~9_combout ;
wire \A_SPW_TOP|tx_data|Mux15~20_combout ;
wire \A_SPW_TOP|SPW|TX|Selector38~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_010|src_payload~3_combout ;
wire \u0|write_data_fifo_tx|data_out[3]~feeder_combout ;
wire \A_SPW_TOP|tx_data|Selector451~0_combout ;
wire \A_SPW_TOP|tx_data|mem[49][3]~q ;
wire \A_SPW_TOP|tx_data|Selector487~0_combout ;
wire \A_SPW_TOP|tx_data|mem[53][3]~q ;
wire \A_SPW_TOP|tx_data|Selector307~0_combout ;
wire \A_SPW_TOP|tx_data|mem[33][3]~q ;
wire \A_SPW_TOP|tx_data|Selector343~0_combout ;
wire \A_SPW_TOP|tx_data|mem[37][3]~q ;
wire \A_SPW_TOP|tx_data|Mux5~11_combout ;
wire \A_SPW_TOP|tx_data|Selector316~0_combout ;
wire \A_SPW_TOP|tx_data|mem[34][3]~q ;
wire \A_SPW_TOP|tx_data|Selector460~0_combout ;
wire \A_SPW_TOP|tx_data|mem[50][3]~q ;
wire \A_SPW_TOP|tx_data|Selector496~0_combout ;
wire \A_SPW_TOP|tx_data|mem[54][3]~q ;
wire \A_SPW_TOP|tx_data|Selector352~0_combout ;
wire \A_SPW_TOP|tx_data|mem[38][3]~q ;
wire \A_SPW_TOP|tx_data|Mux5~12_combout ;
wire \A_SPW_TOP|tx_data|Selector334~0_combout ;
wire \A_SPW_TOP|tx_data|mem[36][3]~q ;
wire \A_SPW_TOP|tx_data|Selector478~0_combout ;
wire \A_SPW_TOP|tx_data|mem[52][3]~q ;
wire \A_SPW_TOP|tx_data|Selector442~0_combout ;
wire \A_SPW_TOP|tx_data|mem[48][3]~q ;
wire \A_SPW_TOP|tx_data|Selector298~0_combout ;
wire \A_SPW_TOP|tx_data|mem[32][3]~q ;
wire \A_SPW_TOP|tx_data|Mux5~10_combout ;
wire \A_SPW_TOP|tx_data|Selector361~0_combout ;
wire \A_SPW_TOP|tx_data|mem[39][3]~q ;
wire \A_SPW_TOP|tx_data|Selector469~0_combout ;
wire \A_SPW_TOP|tx_data|mem[51][3]~q ;
wire \A_SPW_TOP|tx_data|Selector505~0_combout ;
wire \A_SPW_TOP|tx_data|mem[55][3]~q ;
wire \A_SPW_TOP|tx_data|Selector325~0_combout ;
wire \A_SPW_TOP|tx_data|mem[35][3]~q ;
wire \A_SPW_TOP|tx_data|Mux5~13_combout ;
wire \A_SPW_TOP|tx_data|Mux5~14_combout ;
wire \A_SPW_TOP|tx_data|Selector190~0_combout ;
wire \A_SPW_TOP|tx_data|mem[20][3]~q ;
wire \A_SPW_TOP|tx_data|Selector154~0_combout ;
wire \A_SPW_TOP|tx_data|mem[16][3]~q ;
wire \A_SPW_TOP|tx_data|Selector46~0_combout ;
wire \A_SPW_TOP|tx_data|mem[4][3]~q ;
wire \A_SPW_TOP|tx_data|Selector10~0_combout ;
wire \A_SPW_TOP|tx_data|mem[0][3]~q ;
wire \A_SPW_TOP|tx_data|Mux5~0_combout ;
wire \A_SPW_TOP|tx_data|Selector64~0_combout ;
wire \A_SPW_TOP|tx_data|mem[6][3]~q ;
wire \A_SPW_TOP|tx_data|Selector28~0_combout ;
wire \A_SPW_TOP|tx_data|mem[2][3]~q ;
wire \A_SPW_TOP|tx_data|Selector208~0_combout ;
wire \A_SPW_TOP|tx_data|mem[22][3]~q ;
wire \A_SPW_TOP|tx_data|Selector172~0_combout ;
wire \A_SPW_TOP|tx_data|mem[18][3]~q ;
wire \A_SPW_TOP|tx_data|Mux5~2_combout ;
wire \A_SPW_TOP|tx_data|Selector19~0_combout ;
wire \A_SPW_TOP|tx_data|mem[1][3]~q ;
wire \A_SPW_TOP|tx_data|Selector55~0_combout ;
wire \A_SPW_TOP|tx_data|mem[5][3]~q ;
wire \A_SPW_TOP|tx_data|Selector163~0_combout ;
wire \A_SPW_TOP|tx_data|mem[17][3]~q ;
wire \A_SPW_TOP|tx_data|Selector199~0_combout ;
wire \A_SPW_TOP|tx_data|mem[21][3]~q ;
wire \A_SPW_TOP|tx_data|Mux5~1_combout ;
wire \A_SPW_TOP|tx_data|Selector181~0_combout ;
wire \A_SPW_TOP|tx_data|mem[19][3]~q ;
wire \A_SPW_TOP|tx_data|Selector73~0_combout ;
wire \A_SPW_TOP|tx_data|mem[7][3]~q ;
wire \A_SPW_TOP|tx_data|Selector217~0_combout ;
wire \A_SPW_TOP|tx_data|mem[23][3]~q ;
wire \A_SPW_TOP|tx_data|Selector37~0_combout ;
wire \A_SPW_TOP|tx_data|mem[3][3]~q ;
wire \A_SPW_TOP|tx_data|Mux5~3_combout ;
wire \A_SPW_TOP|tx_data|Mux5~4_combout ;
wire \A_SPW_TOP|tx_data|Selector271~0_combout ;
wire \A_SPW_TOP|tx_data|mem[29][3]~q ;
wire \A_SPW_TOP|tx_data|Selector235~0_combout ;
wire \A_SPW_TOP|tx_data|mem[25][3]~q ;
wire \A_SPW_TOP|tx_data|Selector127~0_combout ;
wire \A_SPW_TOP|tx_data|mem[13][3]~q ;
wire \A_SPW_TOP|tx_data|Selector91~0_combout ;
wire \A_SPW_TOP|tx_data|mem[9][3]~q ;
wire \A_SPW_TOP|tx_data|Mux5~6_combout ;
wire \A_SPW_TOP|tx_data|Selector253~0_combout ;
wire \A_SPW_TOP|tx_data|mem[27][3]~q ;
wire \A_SPW_TOP|tx_data|Selector109~0_combout ;
wire \A_SPW_TOP|tx_data|mem[11][3]~q ;
wire \A_SPW_TOP|tx_data|Selector145~0_combout ;
wire \A_SPW_TOP|tx_data|mem[15][3]~q ;
wire \A_SPW_TOP|tx_data|Mux5~8_combout ;
wire \A_SPW_TOP|tx_data|Selector118~0_combout ;
wire \A_SPW_TOP|tx_data|mem[12][3]~q ;
wire \A_SPW_TOP|tx_data|Selector226~0_combout ;
wire \A_SPW_TOP|tx_data|mem[24][3]~q ;
wire \A_SPW_TOP|tx_data|Selector82~0_combout ;
wire \A_SPW_TOP|tx_data|mem[8][3]~q ;
wire \A_SPW_TOP|tx_data|Selector262~0_combout ;
wire \A_SPW_TOP|tx_data|mem[28][3]~q ;
wire \A_SPW_TOP|tx_data|Mux5~5_combout ;
wire \A_SPW_TOP|tx_data|Selector280~0_combout ;
wire \A_SPW_TOP|tx_data|mem[30][3]~q ;
wire \A_SPW_TOP|tx_data|Selector100~0_combout ;
wire \A_SPW_TOP|tx_data|mem[10][3]~q ;
wire \A_SPW_TOP|tx_data|Selector136~0_combout ;
wire \A_SPW_TOP|tx_data|mem[14][3]~q ;
wire \A_SPW_TOP|tx_data|Selector244~0_combout ;
wire \A_SPW_TOP|tx_data|mem[26][3]~q ;
wire \A_SPW_TOP|tx_data|Mux5~7_combout ;
wire \A_SPW_TOP|tx_data|Mux5~9_combout ;
wire \A_SPW_TOP|tx_data|Selector388~0_combout ;
wire \A_SPW_TOP|tx_data|mem[42][3]~q ;
wire \A_SPW_TOP|tx_data|Selector370~0_combout ;
wire \A_SPW_TOP|tx_data|mem[40][3]~q ;
wire \A_SPW_TOP|tx_data|Selector532~0_combout ;
wire \A_SPW_TOP|tx_data|mem[58][3]~q ;
wire \A_SPW_TOP|tx_data|Selector514~0_combout ;
wire \A_SPW_TOP|tx_data|mem[56][3]~q ;
wire \A_SPW_TOP|tx_data|Mux5~15_combout ;
wire \A_SPW_TOP|tx_data|Selector415~0_combout ;
wire \A_SPW_TOP|tx_data|mem[45][3]~q ;
wire \A_SPW_TOP|tx_data|Selector577~0_combout ;
wire \A_SPW_TOP|tx_data|mem[63][3]~q ;
wire \A_SPW_TOP|tx_data|Selector559~0_combout ;
wire \A_SPW_TOP|tx_data|mem[61][3]~q ;
wire \A_SPW_TOP|tx_data|Selector433~0_combout ;
wire \A_SPW_TOP|tx_data|mem[47][3]~q ;
wire \A_SPW_TOP|tx_data|Mux5~18_combout ;
wire \A_SPW_TOP|tx_data|Selector406~0_combout ;
wire \A_SPW_TOP|tx_data|mem[44][3]~q ;
wire \A_SPW_TOP|tx_data|Selector550~0_combout ;
wire \A_SPW_TOP|tx_data|mem[60][3]~q ;
wire \A_SPW_TOP|tx_data|Selector568~0_combout ;
wire \A_SPW_TOP|tx_data|mem[62][3]~q ;
wire \A_SPW_TOP|tx_data|Selector424~0_combout ;
wire \A_SPW_TOP|tx_data|mem[46][3]~q ;
wire \A_SPW_TOP|tx_data|Mux5~17_combout ;
wire \A_SPW_TOP|tx_data|Selector523~0_combout ;
wire \A_SPW_TOP|tx_data|mem[57][3]~q ;
wire \A_SPW_TOP|tx_data|Selector397~0_combout ;
wire \A_SPW_TOP|tx_data|mem[43][3]~q ;
wire \A_SPW_TOP|tx_data|Selector541~0_combout ;
wire \A_SPW_TOP|tx_data|mem[59][3]~q ;
wire \A_SPW_TOP|tx_data|Selector379~0_combout ;
wire \A_SPW_TOP|tx_data|mem[41][3]~q ;
wire \A_SPW_TOP|tx_data|Mux5~16_combout ;
wire \A_SPW_TOP|tx_data|Mux5~19_combout ;
wire \A_SPW_TOP|tx_data|Mux5~20_combout ;
wire \A_SPW_TOP|tx_data|Selector289~0_combout ;
wire \A_SPW_TOP|tx_data|mem[31][3]~q ;
wire \A_SPW_TOP|tx_data|Mux14~8_combout ;
wire \A_SPW_TOP|tx_data|Mux14~7_combout ;
wire \A_SPW_TOP|tx_data|Mux14~6_combout ;
wire \A_SPW_TOP|tx_data|Mux14~5_combout ;
wire \A_SPW_TOP|tx_data|Mux14~9_combout ;
wire \A_SPW_TOP|tx_data|Mux14~15_combout ;
wire \A_SPW_TOP|tx_data|Mux14~16_combout ;
wire \A_SPW_TOP|tx_data|Mux14~17_combout ;
wire \A_SPW_TOP|tx_data|Mux14~18_combout ;
wire \A_SPW_TOP|tx_data|Mux14~19_combout ;
wire \A_SPW_TOP|tx_data|Mux14~2_combout ;
wire \A_SPW_TOP|tx_data|Mux14~1_combout ;
wire \A_SPW_TOP|tx_data|Mux14~3_combout ;
wire \A_SPW_TOP|tx_data|Mux14~0_combout ;
wire \A_SPW_TOP|tx_data|Mux14~4_combout ;
wire \A_SPW_TOP|tx_data|Mux14~12_combout ;
wire \A_SPW_TOP|tx_data|Mux14~13_combout ;
wire \A_SPW_TOP|tx_data|Mux14~10_combout ;
wire \A_SPW_TOP|tx_data|Mux14~11_combout ;
wire \A_SPW_TOP|tx_data|Mux14~14_combout ;
wire \A_SPW_TOP|tx_data|Mux14~20_combout ;
wire \A_SPW_TOP|SPW|TX|Selector37~0_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout~39_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout~19_combout ;
wire \A_SPW_TOP|SPW|TX|LessThan6~0_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout~15_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout~18_combout ;
wire \u0|mm_interconnect_0|cmd_mux_010|src_payload~7_combout ;
wire \A_SPW_TOP|tx_data|Selector231~0_combout ;
wire \A_SPW_TOP|tx_data|mem[25][7]~q ;
wire \A_SPW_TOP|tx_data|Selector240~0_combout ;
wire \A_SPW_TOP|tx_data|mem[26][7]~q ;
wire \A_SPW_TOP|tx_data|Selector222~0_combout ;
wire \A_SPW_TOP|tx_data|mem[24][7]~q ;
wire \A_SPW_TOP|tx_data|Selector249~0_combout ;
wire \A_SPW_TOP|tx_data|mem[27][7]~q ;
wire \A_SPW_TOP|tx_data|Mux1~6_combout ;
wire \A_SPW_TOP|tx_data|Selector456~0_combout ;
wire \A_SPW_TOP|tx_data|mem[50][7]~q ;
wire \A_SPW_TOP|tx_data|Selector438~0_combout ;
wire \A_SPW_TOP|tx_data|mem[48][7]~q ;
wire \A_SPW_TOP|tx_data|Selector465~0_combout ;
wire \A_SPW_TOP|tx_data|mem[51][7]~q ;
wire \A_SPW_TOP|tx_data|Selector447~0_combout ;
wire \A_SPW_TOP|tx_data|mem[49][7]~q ;
wire \A_SPW_TOP|tx_data|Mux1~7_combout ;
wire \A_SPW_TOP|tx_data|Selector168~0_combout ;
wire \A_SPW_TOP|tx_data|mem[18][7]~q ;
wire \A_SPW_TOP|tx_data|Selector159~0_combout ;
wire \A_SPW_TOP|tx_data|mem[17][7]~q ;
wire \A_SPW_TOP|tx_data|Selector177~0_combout ;
wire \A_SPW_TOP|tx_data|mem[19][7]~q ;
wire \A_SPW_TOP|tx_data|Selector150~0_combout ;
wire \A_SPW_TOP|tx_data|mem[16][7]~q ;
wire \A_SPW_TOP|tx_data|Mux1~5_combout ;
wire \A_SPW_TOP|tx_data|Selector537~0_combout ;
wire \A_SPW_TOP|tx_data|mem[59][7]~q ;
wire \A_SPW_TOP|tx_data|Selector528~0_combout ;
wire \A_SPW_TOP|tx_data|mem[58][7]~q ;
wire \A_SPW_TOP|tx_data|Selector519~0_combout ;
wire \A_SPW_TOP|tx_data|mem[57][7]~q ;
wire \A_SPW_TOP|tx_data|Selector510~0_combout ;
wire \A_SPW_TOP|tx_data|mem[56][7]~q ;
wire \A_SPW_TOP|tx_data|Mux1~8_combout ;
wire \A_SPW_TOP|tx_data|Mux1~9_combout ;
wire \A_SPW_TOP|tx_data|Selector195~0_combout ;
wire \A_SPW_TOP|tx_data|mem[21][7]~q ;
wire \A_SPW_TOP|tx_data|Selector213~0_combout ;
wire \A_SPW_TOP|tx_data|mem[23][7]~q ;
wire \A_SPW_TOP|tx_data|Selector501~0_combout ;
wire \A_SPW_TOP|tx_data|mem[55][7]~q ;
wire \A_SPW_TOP|tx_data|Selector483~0_combout ;
wire \A_SPW_TOP|tx_data|mem[53][7]~q ;
wire \A_SPW_TOP|tx_data|Mux1~17_combout ;
wire \A_SPW_TOP|tx_data|Selector186~0_combout ;
wire \A_SPW_TOP|tx_data|mem[20][7]~q ;
wire \A_SPW_TOP|tx_data|Selector204~0_combout ;
wire \A_SPW_TOP|tx_data|mem[22][7]~q ;
wire \A_SPW_TOP|tx_data|Selector492~0_combout ;
wire \A_SPW_TOP|tx_data|mem[54][7]~q ;
wire \A_SPW_TOP|tx_data|Selector474~0_combout ;
wire \A_SPW_TOP|tx_data|mem[52][7]~q ;
wire \A_SPW_TOP|tx_data|Mux1~15_combout ;
wire \A_SPW_TOP|tx_data|Selector258~0_combout ;
wire \A_SPW_TOP|tx_data|mem[28][7]~q ;
wire \A_SPW_TOP|tx_data|Selector564~0_combout ;
wire \A_SPW_TOP|tx_data|mem[62][7]~q ;
wire \A_SPW_TOP|tx_data|Selector276~0_combout ;
wire \A_SPW_TOP|tx_data|mem[30][7]~q ;
wire \A_SPW_TOP|tx_data|Selector546~0_combout ;
wire \A_SPW_TOP|tx_data|mem[60][7]~q ;
wire \A_SPW_TOP|tx_data|Mux1~16_combout ;
wire \A_SPW_TOP|tx_data|Selector285~0_combout ;
wire \A_SPW_TOP|tx_data|mem[31][7]~q ;
wire \A_SPW_TOP|tx_data|Selector555~0_combout ;
wire \A_SPW_TOP|tx_data|mem[61][7]~q ;
wire \A_SPW_TOP|tx_data|Selector573~0_combout ;
wire \A_SPW_TOP|tx_data|mem[63][7]~q ;
wire \A_SPW_TOP|tx_data|Selector267~0_combout ;
wire \A_SPW_TOP|tx_data|mem[29][7]~q ;
wire \A_SPW_TOP|tx_data|Mux1~18_combout ;
wire \A_SPW_TOP|tx_data|Mux1~19_combout ;
wire \A_SPW_TOP|tx_data|Selector114~0_combout ;
wire \A_SPW_TOP|tx_data|mem[12][7]~q ;
wire \A_SPW_TOP|tx_data|Selector132~0_combout ;
wire \A_SPW_TOP|tx_data|mem[14][7]~q ;
wire \A_SPW_TOP|tx_data|Selector123~0_combout ;
wire \A_SPW_TOP|tx_data|mem[13][7]~q ;
wire \A_SPW_TOP|tx_data|Selector141~0_combout ;
wire \A_SPW_TOP|tx_data|mem[15][7]~q ;
wire \A_SPW_TOP|tx_data|Mux1~11_combout ;
wire \A_SPW_TOP|tx_data|Selector69~0_combout ;
wire \A_SPW_TOP|tx_data|mem[7][7]~q ;
wire \A_SPW_TOP|tx_data|Selector60~0_combout ;
wire \A_SPW_TOP|tx_data|mem[6][7]~q ;
wire \A_SPW_TOP|tx_data|Selector51~0_combout ;
wire \A_SPW_TOP|tx_data|mem[5][7]~q ;
wire \A_SPW_TOP|tx_data|Selector42~0_combout ;
wire \A_SPW_TOP|tx_data|mem[4][7]~q ;
wire \A_SPW_TOP|tx_data|Mux1~10_combout ;
wire \A_SPW_TOP|tx_data|Selector348~0_combout ;
wire \A_SPW_TOP|tx_data|mem[38][7]~q ;
wire \A_SPW_TOP|tx_data|Selector330~0_combout ;
wire \A_SPW_TOP|tx_data|mem[36][7]~q ;
wire \A_SPW_TOP|tx_data|Selector357~0_combout ;
wire \A_SPW_TOP|tx_data|mem[39][7]~q ;
wire \A_SPW_TOP|tx_data|Selector339~0_combout ;
wire \A_SPW_TOP|tx_data|mem[37][7]~q ;
wire \A_SPW_TOP|tx_data|Mux1~12_combout ;
wire \A_SPW_TOP|tx_data|Selector402~0_combout ;
wire \A_SPW_TOP|tx_data|mem[44][7]~q ;
wire \A_SPW_TOP|tx_data|Selector420~0_combout ;
wire \A_SPW_TOP|tx_data|mem[46][7]~q ;
wire \A_SPW_TOP|tx_data|Selector429~0_combout ;
wire \A_SPW_TOP|tx_data|mem[47][7]~q ;
wire \A_SPW_TOP|tx_data|Selector411~0_combout ;
wire \A_SPW_TOP|tx_data|mem[45][7]~q ;
wire \A_SPW_TOP|tx_data|Mux1~13_combout ;
wire \A_SPW_TOP|tx_data|Mux1~14_combout ;
wire \A_SPW_TOP|tx_data|Selector24~0_combout ;
wire \A_SPW_TOP|tx_data|mem[2][7]~q ;
wire \A_SPW_TOP|tx_data|Selector33~0_combout ;
wire \A_SPW_TOP|tx_data|mem[3][7]~q ;
wire \A_SPW_TOP|tx_data|Selector15~0_combout ;
wire \A_SPW_TOP|tx_data|mem[1][7]~q ;
wire \A_SPW_TOP|tx_data|Mux1~0_combout ;
wire \A_SPW_TOP|tx_data|Selector384~0_combout ;
wire \A_SPW_TOP|tx_data|mem[42][7]~q ;
wire \A_SPW_TOP|tx_data|Selector366~0_combout ;
wire \A_SPW_TOP|tx_data|mem[40][7]~q ;
wire \A_SPW_TOP|tx_data|Selector375~0_combout ;
wire \A_SPW_TOP|tx_data|mem[41][7]~feeder_combout ;
wire \A_SPW_TOP|tx_data|mem[41][7]~q ;
wire \A_SPW_TOP|tx_data|Selector393~0_combout ;
wire \A_SPW_TOP|tx_data|mem[43][7]~q ;
wire \A_SPW_TOP|tx_data|Mux1~3_combout ;
wire \A_SPW_TOP|tx_data|Selector78~0_combout ;
wire \A_SPW_TOP|tx_data|mem[8][7]~q ;
wire \A_SPW_TOP|tx_data|Selector105~0_combout ;
wire \A_SPW_TOP|tx_data|mem[11][7]~q ;
wire \A_SPW_TOP|tx_data|Selector87~0_combout ;
wire \A_SPW_TOP|tx_data|mem[9][7]~q ;
wire \A_SPW_TOP|tx_data|Selector96~0_combout ;
wire \A_SPW_TOP|tx_data|mem[10][7]~q ;
wire \A_SPW_TOP|tx_data|Mux1~1_combout ;
wire \A_SPW_TOP|tx_data|Selector294~0_combout ;
wire \A_SPW_TOP|tx_data|mem[32][7]~q ;
wire \A_SPW_TOP|tx_data|Selector303~0_combout ;
wire \A_SPW_TOP|tx_data|mem[33][7]~q ;
wire \A_SPW_TOP|tx_data|Selector321~0_combout ;
wire \A_SPW_TOP|tx_data|mem[35][7]~q ;
wire \A_SPW_TOP|tx_data|Selector312~0_combout ;
wire \A_SPW_TOP|tx_data|mem[34][7]~q ;
wire \A_SPW_TOP|tx_data|Mux1~2_combout ;
wire \A_SPW_TOP|tx_data|Mux1~4_combout ;
wire \A_SPW_TOP|tx_data|Mux1~20_combout ;
wire \A_SPW_TOP|tx_data|Selector6~0_combout ;
wire \A_SPW_TOP|tx_data|mem[0][7]~q ;
wire \A_SPW_TOP|tx_data|Mux10~0_combout ;
wire \A_SPW_TOP|tx_data|Mux10~3_combout ;
wire \A_SPW_TOP|tx_data|Mux10~2_combout ;
wire \A_SPW_TOP|tx_data|Mux10~1_combout ;
wire \A_SPW_TOP|tx_data|Mux10~4_combout ;
wire \A_SPW_TOP|tx_data|Mux10~18_combout ;
wire \A_SPW_TOP|tx_data|Mux10~17_combout ;
wire \A_SPW_TOP|tx_data|Mux10~15_combout ;
wire \A_SPW_TOP|tx_data|Mux10~16_combout ;
wire \A_SPW_TOP|tx_data|Mux10~19_combout ;
wire \A_SPW_TOP|tx_data|Mux10~6_combout ;
wire \A_SPW_TOP|tx_data|Mux10~8_combout ;
wire \A_SPW_TOP|tx_data|Mux10~5_combout ;
wire \A_SPW_TOP|tx_data|Mux10~7_combout ;
wire \A_SPW_TOP|tx_data|Mux10~9_combout ;
wire \A_SPW_TOP|tx_data|Mux10~13_combout ;
wire \A_SPW_TOP|tx_data|Mux10~12_combout ;
wire \A_SPW_TOP|tx_data|Mux10~10_combout ;
wire \A_SPW_TOP|tx_data|Mux10~11_combout ;
wire \A_SPW_TOP|tx_data|Mux10~14_combout ;
wire \A_SPW_TOP|tx_data|Mux10~20_combout ;
wire \A_SPW_TOP|SPW|TX|Selector33~0_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout~38_combout ;
wire \A_SPW_TOP|tx_data|Selector520~0_combout ;
wire \A_SPW_TOP|tx_data|mem[57][6]~q ;
wire \A_SPW_TOP|tx_data|Selector376~0_combout ;
wire \A_SPW_TOP|tx_data|mem[41][6]~q ;
wire \A_SPW_TOP|tx_data|Selector394~0_combout ;
wire \A_SPW_TOP|tx_data|mem[43][6]~q ;
wire \A_SPW_TOP|tx_data|Selector538~0_combout ;
wire \A_SPW_TOP|tx_data|mem[59][6]~q ;
wire \A_SPW_TOP|tx_data|Mux2~16_combout ;
wire \A_SPW_TOP|tx_data|Selector547~0_combout ;
wire \A_SPW_TOP|tx_data|mem[60][6]~feeder_combout ;
wire \A_SPW_TOP|tx_data|mem[60][6]~q ;
wire \A_SPW_TOP|tx_data|Selector403~0_combout ;
wire \A_SPW_TOP|tx_data|mem[44][6]~q ;
wire \A_SPW_TOP|tx_data|Selector421~0_combout ;
wire \A_SPW_TOP|tx_data|mem[46][6]~feeder_combout ;
wire \A_SPW_TOP|tx_data|mem[46][6]~q ;
wire \A_SPW_TOP|tx_data|Selector565~0_combout ;
wire \A_SPW_TOP|tx_data|mem[62][6]~q ;
wire \A_SPW_TOP|tx_data|Mux2~17_combout ;
wire \A_SPW_TOP|tx_data|Selector385~0_combout ;
wire \A_SPW_TOP|tx_data|mem[42][6]~q ;
wire \A_SPW_TOP|tx_data|Selector367~0_combout ;
wire \A_SPW_TOP|tx_data|mem[40][6]~q ;
wire \A_SPW_TOP|tx_data|Selector529~0_combout ;
wire \A_SPW_TOP|tx_data|mem[58][6]~q ;
wire \A_SPW_TOP|tx_data|Selector511~0_combout ;
wire \A_SPW_TOP|tx_data|mem[56][6]~q ;
wire \A_SPW_TOP|tx_data|Mux2~15_combout ;
wire \A_SPW_TOP|tx_data|Selector430~0_combout ;
wire \A_SPW_TOP|tx_data|mem[47][6]~q ;
wire \A_SPW_TOP|tx_data|Selector556~0_combout ;
wire \A_SPW_TOP|tx_data|mem[61][6]~q ;
wire \A_SPW_TOP|tx_data|Selector412~0_combout ;
wire \A_SPW_TOP|tx_data|mem[45][6]~q ;
wire \A_SPW_TOP|tx_data|Selector574~0_combout ;
wire \A_SPW_TOP|tx_data|mem[63][6]~q ;
wire \A_SPW_TOP|tx_data|Mux2~18_combout ;
wire \A_SPW_TOP|tx_data|Mux2~19_combout ;
wire \A_SPW_TOP|tx_data|Selector448~0_combout ;
wire \A_SPW_TOP|tx_data|mem[49][6]~q ;
wire \A_SPW_TOP|tx_data|Selector304~0_combout ;
wire \A_SPW_TOP|tx_data|mem[33][6]~q ;
wire \A_SPW_TOP|tx_data|Selector340~0_combout ;
wire \A_SPW_TOP|tx_data|mem[37][6]~q ;
wire \A_SPW_TOP|tx_data|Selector484~0_combout ;
wire \A_SPW_TOP|tx_data|mem[53][6]~q ;
wire \A_SPW_TOP|tx_data|Mux2~11_combout ;
wire \A_SPW_TOP|tx_data|Selector322~0_combout ;
wire \A_SPW_TOP|tx_data|mem[35][6]~q ;
wire \A_SPW_TOP|tx_data|Selector358~0_combout ;
wire \A_SPW_TOP|tx_data|mem[39][6]~q ;
wire \A_SPW_TOP|tx_data|Selector466~0_combout ;
wire \A_SPW_TOP|tx_data|mem[51][6]~q ;
wire \A_SPW_TOP|tx_data|Selector502~0_combout ;
wire \A_SPW_TOP|tx_data|mem[55][6]~q ;
wire \A_SPW_TOP|tx_data|Mux2~13_combout ;
wire \A_SPW_TOP|tx_data|Selector457~0_combout ;
wire \A_SPW_TOP|tx_data|mem[50][6]~q ;
wire \A_SPW_TOP|tx_data|Selector313~0_combout ;
wire \A_SPW_TOP|tx_data|mem[34][6]~q ;
wire \A_SPW_TOP|tx_data|Selector349~0_combout ;
wire \A_SPW_TOP|tx_data|mem[38][6]~q ;
wire \A_SPW_TOP|tx_data|Selector493~0_combout ;
wire \A_SPW_TOP|tx_data|mem[54][6]~q ;
wire \A_SPW_TOP|tx_data|Mux2~12_combout ;
wire \A_SPW_TOP|tx_data|Selector295~0_combout ;
wire \A_SPW_TOP|tx_data|mem[32][6]~q ;
wire \A_SPW_TOP|tx_data|Selector439~0_combout ;
wire \A_SPW_TOP|tx_data|mem[48][6]~q ;
wire \A_SPW_TOP|tx_data|Selector331~0_combout ;
wire \A_SPW_TOP|tx_data|mem[36][6]~q ;
wire \A_SPW_TOP|tx_data|Selector475~0_combout ;
wire \A_SPW_TOP|tx_data|mem[52][6]~q ;
wire \A_SPW_TOP|tx_data|Mux2~10_combout ;
wire \A_SPW_TOP|tx_data|Mux2~14_combout ;
wire \A_SPW_TOP|tx_data|Selector196~0_combout ;
wire \A_SPW_TOP|tx_data|mem[21][6]~q ;
wire \A_SPW_TOP|tx_data|Selector52~0_combout ;
wire \A_SPW_TOP|tx_data|mem[5][6]~q ;
wire \A_SPW_TOP|tx_data|Selector160~0_combout ;
wire \A_SPW_TOP|tx_data|mem[17][6]~q ;
wire \A_SPW_TOP|tx_data|Selector16~0_combout ;
wire \A_SPW_TOP|tx_data|mem[1][6]~q ;
wire \A_SPW_TOP|tx_data|Mux2~1_combout ;
wire \A_SPW_TOP|tx_data|Selector205~0_combout ;
wire \A_SPW_TOP|tx_data|mem[22][6]~q ;
wire \A_SPW_TOP|tx_data|Selector25~0_combout ;
wire \A_SPW_TOP|tx_data|mem[2][6]~q ;
wire \A_SPW_TOP|tx_data|Selector169~0_combout ;
wire \A_SPW_TOP|tx_data|mem[18][6]~q ;
wire \A_SPW_TOP|tx_data|Mux2~2_combout ;
wire \A_SPW_TOP|tx_data|Selector34~0_combout ;
wire \A_SPW_TOP|tx_data|mem[3][6]~q ;
wire \A_SPW_TOP|tx_data|Selector70~0_combout ;
wire \A_SPW_TOP|tx_data|mem[7][6]~q ;
wire \A_SPW_TOP|tx_data|Selector214~0_combout ;
wire \A_SPW_TOP|tx_data|mem[23][6]~q ;
wire \A_SPW_TOP|tx_data|Selector178~0_combout ;
wire \A_SPW_TOP|tx_data|mem[19][6]~q ;
wire \A_SPW_TOP|tx_data|Mux2~3_combout ;
wire \A_SPW_TOP|tx_data|Selector43~0_combout ;
wire \A_SPW_TOP|tx_data|mem[4][6]~q ;
wire \A_SPW_TOP|tx_data|Selector187~0_combout ;
wire \A_SPW_TOP|tx_data|mem[20][6]~q ;
wire \A_SPW_TOP|tx_data|Selector151~0_combout ;
wire \A_SPW_TOP|tx_data|mem[16][6]~q ;
wire \A_SPW_TOP|tx_data|Selector7~0_combout ;
wire \A_SPW_TOP|tx_data|mem[0][6]~q ;
wire \A_SPW_TOP|tx_data|Mux2~0_combout ;
wire \A_SPW_TOP|tx_data|Mux2~4_combout ;
wire \A_SPW_TOP|tx_data|Selector106~0_combout ;
wire \A_SPW_TOP|tx_data|mem[11][6]~q ;
wire \A_SPW_TOP|tx_data|Selector97~0_combout ;
wire \A_SPW_TOP|tx_data|mem[10][6]~q ;
wire \A_SPW_TOP|tx_data|Selector142~0_combout ;
wire \A_SPW_TOP|tx_data|mem[15][6]~q ;
wire \A_SPW_TOP|tx_data|Selector133~0_combout ;
wire \A_SPW_TOP|tx_data|mem[14][6]~q ;
wire \A_SPW_TOP|tx_data|Mux2~7_combout ;
wire \A_SPW_TOP|tx_data|Selector88~0_combout ;
wire \A_SPW_TOP|tx_data|mem[9][6]~q ;
wire \A_SPW_TOP|tx_data|Selector115~0_combout ;
wire \A_SPW_TOP|tx_data|mem[12][6]~q ;
wire \A_SPW_TOP|tx_data|Selector79~0_combout ;
wire \A_SPW_TOP|tx_data|mem[8][6]~q ;
wire \A_SPW_TOP|tx_data|Selector124~0_combout ;
wire \A_SPW_TOP|tx_data|mem[13][6]~q ;
wire \A_SPW_TOP|tx_data|Mux2~5_combout ;
wire \A_SPW_TOP|tx_data|Selector277~0_combout ;
wire \A_SPW_TOP|tx_data|mem[30][6]~q ;
wire \A_SPW_TOP|tx_data|Selector250~0_combout ;
wire \A_SPW_TOP|tx_data|mem[27][6]~q ;
wire \A_SPW_TOP|tx_data|Selector286~0_combout ;
wire \A_SPW_TOP|tx_data|mem[31][6]~q ;
wire \A_SPW_TOP|tx_data|Selector241~0_combout ;
wire \A_SPW_TOP|tx_data|mem[26][6]~q ;
wire \A_SPW_TOP|tx_data|Mux2~8_combout ;
wire \A_SPW_TOP|tx_data|Selector232~0_combout ;
wire \A_SPW_TOP|tx_data|mem[25][6]~q ;
wire \A_SPW_TOP|tx_data|Selector259~0_combout ;
wire \A_SPW_TOP|tx_data|mem[28][6]~q ;
wire \A_SPW_TOP|tx_data|Selector268~0_combout ;
wire \A_SPW_TOP|tx_data|mem[29][6]~q ;
wire \A_SPW_TOP|tx_data|Selector223~0_combout ;
wire \A_SPW_TOP|tx_data|mem[24][6]~q ;
wire \A_SPW_TOP|tx_data|Mux2~6_combout ;
wire \A_SPW_TOP|tx_data|Mux2~9_combout ;
wire \A_SPW_TOP|tx_data|Mux2~20_combout ;
wire \A_SPW_TOP|tx_data|Selector61~0_combout ;
wire \A_SPW_TOP|tx_data|mem[6][6]~q ;
wire \A_SPW_TOP|tx_data|Mux11~0_combout ;
wire \A_SPW_TOP|tx_data|Mux11~1_combout ;
wire \A_SPW_TOP|tx_data|Mux11~3_combout ;
wire \A_SPW_TOP|tx_data|Mux11~2_combout ;
wire \A_SPW_TOP|tx_data|Mux11~4_combout ;
wire \A_SPW_TOP|tx_data|Mux11~6_combout ;
wire \A_SPW_TOP|tx_data|Mux11~8_combout ;
wire \A_SPW_TOP|tx_data|Mux11~7_combout ;
wire \A_SPW_TOP|tx_data|Mux11~5_combout ;
wire \A_SPW_TOP|tx_data|Mux11~9_combout ;
wire \A_SPW_TOP|tx_data|Mux11~11_combout ;
wire \A_SPW_TOP|tx_data|Mux11~13_combout ;
wire \A_SPW_TOP|tx_data|Mux11~12_combout ;
wire \A_SPW_TOP|tx_data|Mux11~10_combout ;
wire \A_SPW_TOP|tx_data|Mux11~14_combout ;
wire \A_SPW_TOP|tx_data|Mux11~17_combout ;
wire \A_SPW_TOP|tx_data|Mux11~18_combout ;
wire \A_SPW_TOP|tx_data|Mux11~15_combout ;
wire \A_SPW_TOP|tx_data|Mux11~16_combout ;
wire \A_SPW_TOP|tx_data|Mux11~19_combout ;
wire \A_SPW_TOP|tx_data|Mux11~20_combout ;
wire \A_SPW_TOP|SPW|TX|Selector34~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_010|src_payload~5_combout ;
wire \A_SPW_TOP|tx_data|Selector242~0_combout ;
wire \A_SPW_TOP|tx_data|mem[26][5]~q ;
wire \A_SPW_TOP|tx_data|Selector170~0_combout ;
wire \A_SPW_TOP|tx_data|mem[18][5]~feeder_combout ;
wire \A_SPW_TOP|tx_data|mem[18][5]~q ;
wire \A_SPW_TOP|tx_data|Selector458~0_combout ;
wire \A_SPW_TOP|tx_data|mem[50][5]~q ;
wire \A_SPW_TOP|tx_data|Selector530~0_combout ;
wire \A_SPW_TOP|tx_data|mem[58][5]~q ;
wire \A_SPW_TOP|tx_data|Mux3~12_combout ;
wire \A_SPW_TOP|tx_data|Selector26~0_combout ;
wire \A_SPW_TOP|tx_data|mem[2][5]~q ;
wire \A_SPW_TOP|tx_data|Selector314~0_combout ;
wire \A_SPW_TOP|tx_data|mem[34][5]~q ;
wire \A_SPW_TOP|tx_data|Selector386~0_combout ;
wire \A_SPW_TOP|tx_data|mem[42][5]~q ;
wire \A_SPW_TOP|tx_data|Selector98~0_combout ;
wire \A_SPW_TOP|tx_data|mem[10][5]~q ;
wire \A_SPW_TOP|tx_data|Mux3~10_combout ;
wire \A_SPW_TOP|tx_data|Selector278~0_combout ;
wire \A_SPW_TOP|tx_data|mem[30][5]~q ;
wire \A_SPW_TOP|tx_data|Selector566~0_combout ;
wire \A_SPW_TOP|tx_data|mem[62][5]~q ;
wire \A_SPW_TOP|tx_data|Selector494~0_combout ;
wire \A_SPW_TOP|tx_data|mem[54][5]~q ;
wire \A_SPW_TOP|tx_data|Selector206~0_combout ;
wire \A_SPW_TOP|tx_data|mem[22][5]~q ;
wire \A_SPW_TOP|tx_data|Mux3~13_combout ;
wire \A_SPW_TOP|tx_data|Selector350~0_combout ;
wire \A_SPW_TOP|tx_data|mem[38][5]~q ;
wire \A_SPW_TOP|tx_data|Selector62~0_combout ;
wire \A_SPW_TOP|tx_data|mem[6][5]~q ;
wire \A_SPW_TOP|tx_data|Selector422~0_combout ;
wire \A_SPW_TOP|tx_data|mem[46][5]~q ;
wire \A_SPW_TOP|tx_data|Selector134~0_combout ;
wire \A_SPW_TOP|tx_data|mem[14][5]~q ;
wire \A_SPW_TOP|tx_data|Mux3~11_combout ;
wire \A_SPW_TOP|tx_data|Mux3~14_combout ;
wire \A_SPW_TOP|tx_data|Selector8~0_combout ;
wire \A_SPW_TOP|tx_data|mem[0][5]~q ;
wire \A_SPW_TOP|tx_data|Selector296~0_combout ;
wire \A_SPW_TOP|tx_data|mem[32][5]~q ;
wire \A_SPW_TOP|tx_data|Selector80~0_combout ;
wire \A_SPW_TOP|tx_data|mem[8][5]~q ;
wire \A_SPW_TOP|tx_data|Selector368~0_combout ;
wire \A_SPW_TOP|tx_data|mem[40][5]~q ;
wire \A_SPW_TOP|tx_data|Mux3~0_combout ;
wire \A_SPW_TOP|tx_data|Selector116~0_combout ;
wire \A_SPW_TOP|tx_data|mem[12][5]~q ;
wire \A_SPW_TOP|tx_data|Selector404~0_combout ;
wire \A_SPW_TOP|tx_data|mem[44][5]~q ;
wire \A_SPW_TOP|tx_data|Selector44~0_combout ;
wire \A_SPW_TOP|tx_data|mem[4][5]~q ;
wire \A_SPW_TOP|tx_data|Selector332~0_combout ;
wire \A_SPW_TOP|tx_data|mem[36][5]~q ;
wire \A_SPW_TOP|tx_data|Mux3~1_combout ;
wire \A_SPW_TOP|tx_data|Selector440~0_combout ;
wire \A_SPW_TOP|tx_data|mem[48][5]~q ;
wire \A_SPW_TOP|tx_data|Selector224~0_combout ;
wire \A_SPW_TOP|tx_data|mem[24][5]~q ;
wire \A_SPW_TOP|tx_data|Selector152~0_combout ;
wire \A_SPW_TOP|tx_data|mem[16][5]~q ;
wire \A_SPW_TOP|tx_data|Selector512~0_combout ;
wire \A_SPW_TOP|tx_data|mem[56][5]~q ;
wire \A_SPW_TOP|tx_data|Mux3~2_combout ;
wire \A_SPW_TOP|tx_data|Selector476~0_combout ;
wire \A_SPW_TOP|tx_data|mem[52][5]~q ;
wire \A_SPW_TOP|tx_data|Selector260~0_combout ;
wire \A_SPW_TOP|tx_data|mem[28][5]~q ;
wire \A_SPW_TOP|tx_data|Selector188~0_combout ;
wire \A_SPW_TOP|tx_data|mem[20][5]~q ;
wire \A_SPW_TOP|tx_data|Mux3~3_combout ;
wire \A_SPW_TOP|tx_data|Mux3~4_combout ;
wire \A_SPW_TOP|tx_data|Selector449~0_combout ;
wire \A_SPW_TOP|tx_data|mem[49][5]~feeder_combout ;
wire \A_SPW_TOP|tx_data|mem[49][5]~q ;
wire \A_SPW_TOP|tx_data|Selector521~0_combout ;
wire \A_SPW_TOP|tx_data|mem[57][5]~q ;
wire \A_SPW_TOP|tx_data|Selector161~0_combout ;
wire \A_SPW_TOP|tx_data|mem[17][5]~q ;
wire \A_SPW_TOP|tx_data|Selector233~0_combout ;
wire \A_SPW_TOP|tx_data|mem[25][5]~q ;
wire \A_SPW_TOP|tx_data|Mux3~7_combout ;
wire \A_SPW_TOP|tx_data|Selector53~0_combout ;
wire \A_SPW_TOP|tx_data|mem[5][5]~q ;
wire \A_SPW_TOP|tx_data|Selector125~0_combout ;
wire \A_SPW_TOP|tx_data|mem[13][5]~q ;
wire \A_SPW_TOP|tx_data|Selector413~0_combout ;
wire \A_SPW_TOP|tx_data|mem[45][5]~q ;
wire \A_SPW_TOP|tx_data|Selector341~0_combout ;
wire \A_SPW_TOP|tx_data|mem[37][5]~q ;
wire \A_SPW_TOP|tx_data|Mux3~6_combout ;
wire \A_SPW_TOP|tx_data|Selector305~0_combout ;
wire \A_SPW_TOP|tx_data|mem[33][5]~q ;
wire \A_SPW_TOP|tx_data|Selector89~0_combout ;
wire \A_SPW_TOP|tx_data|mem[9][5]~q ;
wire \A_SPW_TOP|tx_data|Selector377~0_combout ;
wire \A_SPW_TOP|tx_data|mem[41][5]~q ;
wire \A_SPW_TOP|tx_data|Selector17~0_combout ;
wire \A_SPW_TOP|tx_data|mem[1][5]~q ;
wire \A_SPW_TOP|tx_data|Mux3~5_combout ;
wire \A_SPW_TOP|tx_data|Selector197~0_combout ;
wire \A_SPW_TOP|tx_data|mem[21][5]~q ;
wire \A_SPW_TOP|tx_data|Selector269~0_combout ;
wire \A_SPW_TOP|tx_data|mem[29][5]~q ;
wire \A_SPW_TOP|tx_data|Selector485~0_combout ;
wire \A_SPW_TOP|tx_data|mem[53][5]~q ;
wire \A_SPW_TOP|tx_data|Selector557~0_combout ;
wire \A_SPW_TOP|tx_data|mem[61][5]~q ;
wire \A_SPW_TOP|tx_data|Mux3~8_combout ;
wire \A_SPW_TOP|tx_data|Mux3~9_combout ;
wire \A_SPW_TOP|tx_data|Selector575~0_combout ;
wire \A_SPW_TOP|tx_data|mem[63][5]~q ;
wire \A_SPW_TOP|tx_data|Selector539~0_combout ;
wire \A_SPW_TOP|tx_data|mem[59][5]~q ;
wire \A_SPW_TOP|tx_data|Selector467~0_combout ;
wire \A_SPW_TOP|tx_data|mem[51][5]~feeder_combout ;
wire \A_SPW_TOP|tx_data|mem[51][5]~q ;
wire \A_SPW_TOP|tx_data|Selector503~0_combout ;
wire \A_SPW_TOP|tx_data|mem[55][5]~q ;
wire \A_SPW_TOP|tx_data|Mux3~18_combout ;
wire \A_SPW_TOP|tx_data|Selector431~0_combout ;
wire \A_SPW_TOP|tx_data|mem[47][5]~q ;
wire \A_SPW_TOP|tx_data|Selector359~0_combout ;
wire \A_SPW_TOP|tx_data|mem[39][5]~q ;
wire \A_SPW_TOP|tx_data|Selector323~0_combout ;
wire \A_SPW_TOP|tx_data|mem[35][5]~q ;
wire \A_SPW_TOP|tx_data|Selector395~0_combout ;
wire \A_SPW_TOP|tx_data|mem[43][5]~q ;
wire \A_SPW_TOP|tx_data|Mux3~16_combout ;
wire \A_SPW_TOP|tx_data|Selector35~0_combout ;
wire \A_SPW_TOP|tx_data|mem[3][5]~q ;
wire \A_SPW_TOP|tx_data|Selector107~0_combout ;
wire \A_SPW_TOP|tx_data|mem[11][5]~q ;
wire \A_SPW_TOP|tx_data|Selector143~0_combout ;
wire \A_SPW_TOP|tx_data|mem[15][5]~q ;
wire \A_SPW_TOP|tx_data|Selector71~0_combout ;
wire \A_SPW_TOP|tx_data|mem[7][5]~q ;
wire \A_SPW_TOP|tx_data|Mux3~15_combout ;
wire \A_SPW_TOP|tx_data|Selector215~0_combout ;
wire \A_SPW_TOP|tx_data|mem[23][5]~q ;
wire \A_SPW_TOP|tx_data|Selector251~0_combout ;
wire \A_SPW_TOP|tx_data|mem[27][5]~q ;
wire \A_SPW_TOP|tx_data|Selector287~0_combout ;
wire \A_SPW_TOP|tx_data|mem[31][5]~q ;
wire \A_SPW_TOP|tx_data|Selector179~0_combout ;
wire \A_SPW_TOP|tx_data|mem[19][5]~q ;
wire \A_SPW_TOP|tx_data|Mux3~17_combout ;
wire \A_SPW_TOP|tx_data|Mux3~19_combout ;
wire \A_SPW_TOP|tx_data|Mux3~20_combout ;
wire \A_SPW_TOP|tx_data|Selector548~0_combout ;
wire \A_SPW_TOP|tx_data|mem[60][5]~q ;
wire \A_SPW_TOP|tx_data|Mux12~6_combout ;
wire \A_SPW_TOP|tx_data|Mux12~7_combout ;
wire \A_SPW_TOP|tx_data|Mux12~5_combout ;
wire \A_SPW_TOP|tx_data|Mux12~8_combout ;
wire \A_SPW_TOP|tx_data|Mux12~9_combout ;
wire \A_SPW_TOP|tx_data|Mux12~17_combout ;
wire \A_SPW_TOP|tx_data|Mux12~16_combout ;
wire \A_SPW_TOP|tx_data|Mux12~18_combout ;
wire \A_SPW_TOP|tx_data|Mux12~15_combout ;
wire \A_SPW_TOP|tx_data|Mux12~19_combout ;
wire \A_SPW_TOP|tx_data|Mux12~13_combout ;
wire \A_SPW_TOP|tx_data|Mux12~11_combout ;
wire \A_SPW_TOP|tx_data|Mux12~12_combout ;
wire \A_SPW_TOP|tx_data|Mux12~10_combout ;
wire \A_SPW_TOP|tx_data|Mux12~14_combout ;
wire \A_SPW_TOP|tx_data|Mux12~2_combout ;
wire \A_SPW_TOP|tx_data|Mux12~3_combout ;
wire \A_SPW_TOP|tx_data|Mux12~1_combout ;
wire \A_SPW_TOP|tx_data|Mux12~0_combout ;
wire \A_SPW_TOP|tx_data|Mux12~4_combout ;
wire \A_SPW_TOP|tx_data|Mux12~20_combout ;
wire \A_SPW_TOP|SPW|TX|Selector35~0_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout~17_combout ;
wire \u0|mm_interconnect_0|cmd_mux_010|src_payload~4_combout ;
wire \u0|write_data_fifo_tx|data_out[4]~feeder_combout ;
wire \A_SPW_TOP|tx_data|Selector306~0_combout ;
wire \A_SPW_TOP|tx_data|mem[33][4]~q ;
wire \A_SPW_TOP|tx_data|Selector315~0_combout ;
wire \A_SPW_TOP|tx_data|mem[34][4]~q ;
wire \A_SPW_TOP|tx_data|Selector324~0_combout ;
wire \A_SPW_TOP|tx_data|mem[35][4]~q ;
wire \A_SPW_TOP|tx_data|Selector297~0_combout ;
wire \A_SPW_TOP|tx_data|mem[32][4]~q ;
wire \A_SPW_TOP|tx_data|Mux4~2_combout ;
wire \A_SPW_TOP|tx_data|Selector90~0_combout ;
wire \A_SPW_TOP|tx_data|mem[9][4]~q ;
wire \A_SPW_TOP|tx_data|Selector81~0_combout ;
wire \A_SPW_TOP|tx_data|mem[8][4]~q ;
wire \A_SPW_TOP|tx_data|Selector108~0_combout ;
wire \A_SPW_TOP|tx_data|mem[11][4]~q ;
wire \A_SPW_TOP|tx_data|Selector99~0_combout ;
wire \A_SPW_TOP|tx_data|mem[10][4]~q ;
wire \A_SPW_TOP|tx_data|Mux4~1_combout ;
wire \A_SPW_TOP|tx_data|Selector27~0_combout ;
wire \A_SPW_TOP|tx_data|mem[2][4]~q ;
wire \A_SPW_TOP|tx_data|Selector18~0_combout ;
wire \A_SPW_TOP|tx_data|mem[1][4]~feeder_combout ;
wire \A_SPW_TOP|tx_data|mem[1][4]~q ;
wire \A_SPW_TOP|tx_data|Selector36~0_combout ;
wire \A_SPW_TOP|tx_data|mem[3][4]~q ;
wire \A_SPW_TOP|tx_data|Mux4~0_combout ;
wire \A_SPW_TOP|tx_data|Selector387~0_combout ;
wire \A_SPW_TOP|tx_data|mem[42][4]~q ;
wire \A_SPW_TOP|tx_data|Selector369~0_combout ;
wire \A_SPW_TOP|tx_data|mem[40][4]~q ;
wire \A_SPW_TOP|tx_data|Selector378~0_combout ;
wire \A_SPW_TOP|tx_data|mem[41][4]~q ;
wire \A_SPW_TOP|tx_data|Selector396~0_combout ;
wire \A_SPW_TOP|tx_data|mem[43][4]~q ;
wire \A_SPW_TOP|tx_data|Mux4~3_combout ;
wire \A_SPW_TOP|tx_data|Mux4~4_combout ;
wire \A_SPW_TOP|tx_data|Selector360~0_combout ;
wire \A_SPW_TOP|tx_data|mem[39][4]~q ;
wire \A_SPW_TOP|tx_data|Selector351~0_combout ;
wire \A_SPW_TOP|tx_data|mem[38][4]~q ;
wire \A_SPW_TOP|tx_data|Selector333~0_combout ;
wire \A_SPW_TOP|tx_data|mem[36][4]~q ;
wire \A_SPW_TOP|tx_data|Selector342~0_combout ;
wire \A_SPW_TOP|tx_data|mem[37][4]~q ;
wire \A_SPW_TOP|tx_data|Mux4~12_combout ;
wire \A_SPW_TOP|tx_data|Selector63~0_combout ;
wire \A_SPW_TOP|tx_data|mem[6][4]~q ;
wire \A_SPW_TOP|tx_data|Selector45~0_combout ;
wire \A_SPW_TOP|tx_data|mem[4][4]~q ;
wire \A_SPW_TOP|tx_data|Selector72~0_combout ;
wire \A_SPW_TOP|tx_data|mem[7][4]~q ;
wire \A_SPW_TOP|tx_data|Selector54~0_combout ;
wire \A_SPW_TOP|tx_data|mem[5][4]~q ;
wire \A_SPW_TOP|tx_data|Mux4~10_combout ;
wire \A_SPW_TOP|tx_data|Selector405~0_combout ;
wire \A_SPW_TOP|tx_data|mem[44][4]~q ;
wire \A_SPW_TOP|tx_data|Selector414~0_combout ;
wire \A_SPW_TOP|tx_data|mem[45][4]~q ;
wire \A_SPW_TOP|tx_data|Selector432~0_combout ;
wire \A_SPW_TOP|tx_data|mem[47][4]~q ;
wire \A_SPW_TOP|tx_data|Selector423~0_combout ;
wire \A_SPW_TOP|tx_data|mem[46][4]~q ;
wire \A_SPW_TOP|tx_data|Mux4~13_combout ;
wire \A_SPW_TOP|tx_data|Selector144~0_combout ;
wire \A_SPW_TOP|tx_data|mem[15][4]~q ;
wire \A_SPW_TOP|tx_data|Selector117~0_combout ;
wire \A_SPW_TOP|tx_data|mem[12][4]~q ;
wire \A_SPW_TOP|tx_data|Selector135~0_combout ;
wire \A_SPW_TOP|tx_data|mem[14][4]~q ;
wire \A_SPW_TOP|tx_data|Selector126~0_combout ;
wire \A_SPW_TOP|tx_data|mem[13][4]~q ;
wire \A_SPW_TOP|tx_data|Mux4~11_combout ;
wire \A_SPW_TOP|tx_data|Mux4~14_combout ;
wire \A_SPW_TOP|tx_data|Selector171~0_combout ;
wire \A_SPW_TOP|tx_data|mem[18][4]~q ;
wire \A_SPW_TOP|tx_data|Selector162~0_combout ;
wire \A_SPW_TOP|tx_data|mem[17][4]~q ;
wire \A_SPW_TOP|tx_data|Selector180~0_combout ;
wire \A_SPW_TOP|tx_data|mem[19][4]~feeder_combout ;
wire \A_SPW_TOP|tx_data|mem[19][4]~q ;
wire \A_SPW_TOP|tx_data|Selector153~0_combout ;
wire \A_SPW_TOP|tx_data|mem[16][4]~q ;
wire \A_SPW_TOP|tx_data|Mux4~5_combout ;
wire \A_SPW_TOP|tx_data|Selector234~0_combout ;
wire \A_SPW_TOP|tx_data|mem[25][4]~q ;
wire \A_SPW_TOP|tx_data|Selector252~0_combout ;
wire \A_SPW_TOP|tx_data|mem[27][4]~q ;
wire \A_SPW_TOP|tx_data|Selector243~0_combout ;
wire \A_SPW_TOP|tx_data|mem[26][4]~q ;
wire \A_SPW_TOP|tx_data|Selector225~0_combout ;
wire \A_SPW_TOP|tx_data|mem[24][4]~q ;
wire \A_SPW_TOP|tx_data|Mux4~6_combout ;
wire \A_SPW_TOP|tx_data|Selector459~0_combout ;
wire \A_SPW_TOP|tx_data|mem[50][4]~q ;
wire \A_SPW_TOP|tx_data|Selector468~0_combout ;
wire \A_SPW_TOP|tx_data|mem[51][4]~q ;
wire \A_SPW_TOP|tx_data|Selector441~0_combout ;
wire \A_SPW_TOP|tx_data|mem[48][4]~q ;
wire \A_SPW_TOP|tx_data|Selector450~0_combout ;
wire \A_SPW_TOP|tx_data|mem[49][4]~q ;
wire \A_SPW_TOP|tx_data|Mux4~7_combout ;
wire \A_SPW_TOP|tx_data|Selector531~0_combout ;
wire \A_SPW_TOP|tx_data|mem[58][4]~q ;
wire \A_SPW_TOP|tx_data|Selector522~0_combout ;
wire \A_SPW_TOP|tx_data|mem[57][4]~q ;
wire \A_SPW_TOP|tx_data|Selector540~0_combout ;
wire \A_SPW_TOP|tx_data|mem[59][4]~q ;
wire \A_SPW_TOP|tx_data|Selector513~0_combout ;
wire \A_SPW_TOP|tx_data|mem[56][4]~q ;
wire \A_SPW_TOP|tx_data|Mux4~8_combout ;
wire \A_SPW_TOP|tx_data|Mux4~9_combout ;
wire \A_SPW_TOP|tx_data|Selector189~0_combout ;
wire \A_SPW_TOP|tx_data|mem[20][4]~q ;
wire \A_SPW_TOP|tx_data|Selector486~0_combout ;
wire \A_SPW_TOP|tx_data|mem[53][4]~feeder_combout ;
wire \A_SPW_TOP|tx_data|mem[53][4]~q ;
wire \A_SPW_TOP|tx_data|Selector477~0_combout ;
wire \A_SPW_TOP|tx_data|mem[52][4]~q ;
wire \A_SPW_TOP|tx_data|Selector198~0_combout ;
wire \A_SPW_TOP|tx_data|mem[21][4]~q ;
wire \A_SPW_TOP|tx_data|Mux4~15_combout ;
wire \A_SPW_TOP|tx_data|Selector216~0_combout ;
wire \A_SPW_TOP|tx_data|mem[23][4]~q ;
wire \A_SPW_TOP|tx_data|Selector495~0_combout ;
wire \A_SPW_TOP|tx_data|mem[54][4]~q ;
wire \A_SPW_TOP|tx_data|Selector504~0_combout ;
wire \A_SPW_TOP|tx_data|mem[55][4]~q ;
wire \A_SPW_TOP|tx_data|Selector207~0_combout ;
wire \A_SPW_TOP|tx_data|mem[22][4]~q ;
wire \A_SPW_TOP|tx_data|Mux4~17_combout ;
wire \A_SPW_TOP|tx_data|Selector558~0_combout ;
wire \A_SPW_TOP|tx_data|mem[61][4]~q ;
wire \A_SPW_TOP|tx_data|Selector549~0_combout ;
wire \A_SPW_TOP|tx_data|mem[60][4]~q ;
wire \A_SPW_TOP|tx_data|Selector270~0_combout ;
wire \A_SPW_TOP|tx_data|mem[29][4]~q ;
wire \A_SPW_TOP|tx_data|Selector261~0_combout ;
wire \A_SPW_TOP|tx_data|mem[28][4]~q ;
wire \A_SPW_TOP|tx_data|Mux4~16_combout ;
wire \A_SPW_TOP|tx_data|Selector576~0_combout ;
wire \A_SPW_TOP|tx_data|mem[63][4]~q ;
wire \A_SPW_TOP|tx_data|Selector288~0_combout ;
wire \A_SPW_TOP|tx_data|mem[31][4]~q ;
wire \A_SPW_TOP|tx_data|Selector279~0_combout ;
wire \A_SPW_TOP|tx_data|mem[30][4]~q ;
wire \A_SPW_TOP|tx_data|Selector567~0_combout ;
wire \A_SPW_TOP|tx_data|mem[62][4]~q ;
wire \A_SPW_TOP|tx_data|Mux4~18_combout ;
wire \A_SPW_TOP|tx_data|Mux4~19_combout ;
wire \A_SPW_TOP|tx_data|Mux4~20_combout ;
wire \A_SPW_TOP|tx_data|Selector9~0_combout ;
wire \A_SPW_TOP|tx_data|mem[0][4]~q ;
wire \A_SPW_TOP|tx_data|Mux13~0_combout ;
wire \A_SPW_TOP|tx_data|Mux13~3_combout ;
wire \A_SPW_TOP|tx_data|Mux13~2_combout ;
wire \A_SPW_TOP|tx_data|Mux13~1_combout ;
wire \A_SPW_TOP|tx_data|Mux13~4_combout ;
wire \A_SPW_TOP|tx_data|Mux13~10_combout ;
wire \A_SPW_TOP|tx_data|Mux13~13_combout ;
wire \A_SPW_TOP|tx_data|Mux13~12_combout ;
wire \A_SPW_TOP|tx_data|Mux13~11_combout ;
wire \A_SPW_TOP|tx_data|Mux13~14_combout ;
wire \A_SPW_TOP|tx_data|Mux13~18_combout ;
wire \A_SPW_TOP|tx_data|Mux13~17_combout ;
wire \A_SPW_TOP|tx_data|Mux13~15_combout ;
wire \A_SPW_TOP|tx_data|Mux13~16_combout ;
wire \A_SPW_TOP|tx_data|Mux13~19_combout ;
wire \A_SPW_TOP|tx_data|Mux13~5_combout ;
wire \A_SPW_TOP|tx_data|Mux13~7_combout ;
wire \A_SPW_TOP|tx_data|Mux13~8_combout ;
wire \A_SPW_TOP|tx_data|Mux13~6_combout ;
wire \A_SPW_TOP|tx_data|Mux13~9_combout ;
wire \A_SPW_TOP|tx_data|Mux13~20_combout ;
wire \A_SPW_TOP|SPW|TX|Selector36~0_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout~14_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout~20_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout~6_combout ;
wire \A_SPW_TOP|SPW|TX|Selector74~0_combout ;
wire \A_SPW_TOP|SPW|TX|Selector25~0_combout ;
wire \A_SPW_TOP|SPW|TX|Selector75~0_combout ;
wire \A_SPW_TOP|SPW|TX|Selector26~0_combout ;
wire \A_SPW_TOP|SPW|TX|Selector76~0_combout ;
wire \A_SPW_TOP|SPW|TX|Selector27~0_combout ;
wire \A_SPW_TOP|SPW|TX|Selector77~0_combout ;
wire \A_SPW_TOP|SPW|TX|Selector24~0_combout ;
wire \A_SPW_TOP|SPW|TX|Selector74~1_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout~4_combout ;
wire \A_SPW_TOP|SPW|TX|Selector28~0_combout ;
wire \A_SPW_TOP|SPW|TX|Selector78~0_combout ;
wire \A_SPW_TOP|SPW|TX|Selector29~0_combout ;
wire \A_SPW_TOP|SPW|TX|Selector79~0_combout ;
wire \A_SPW_TOP|SPW|TX|Selector81~0_combout ;
wire \A_SPW_TOP|SPW|TX|Selector80~0_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout~5_combout ;
wire \A_SPW_TOP|SPW|TX|Selector50~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_014|src_payload~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;
wire \u0|timecode_tx_data|always0~0_combout ;
wire \A_SPW_TOP|SPW|TX|Selector49~0_combout ;
wire \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~2_combout ;
wire \u0|mm_interconnect_0|cmd_mux_014|src_payload~3_combout ;
wire \A_SPW_TOP|SPW|TX|Selector47~0_combout ;
wire \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_014|src_payload~2_combout ;
wire \A_SPW_TOP|SPW|TX|Selector48~0_combout ;
wire \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_014|src_payload~0_combout ;
wire \A_SPW_TOP|SPW|TX|Selector50~2_combout ;
wire \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~3_combout ;
wire \u0|mm_interconnect_0|cmd_mux_014|src_payload~7_combout ;
wire \A_SPW_TOP|SPW|TX|Selector43~0_combout ;
wire \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~4_combout ;
wire \u0|mm_interconnect_0|cmd_mux_014|src_payload~6_combout ;
wire \A_SPW_TOP|SPW|TX|Selector44~0_combout ;
wire \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~5_combout ;
wire \u0|mm_interconnect_0|cmd_mux_014|src_payload~5_combout ;
wire \A_SPW_TOP|SPW|TX|Selector45~0_combout ;
wire \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~6_combout ;
wire \u0|mm_interconnect_0|cmd_mux_014|src_payload~4_combout ;
wire \A_SPW_TOP|SPW|TX|Selector46~0_combout ;
wire \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~7_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout~7_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout~8_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout~22_combout ;
wire \A_SPW_TOP|SPW|TX|Selector0~2_combout ;
wire \A_SPW_TOP|SPW|TX|Selector0~3_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout~24_combout ;
wire \A_SPW_TOP|SPW|TX|Selector0~4_combout ;
wire \A_SPW_TOP|SPW|TX|Selector0~1_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout~25_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout~26_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout~27_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout~28_combout ;
wire \A_SPW_TOP|SPW|TX|Selector0~5_combout ;
wire \A_SPW_TOP|SPW|TX|timecode_s~2_combout ;
wire \A_SPW_TOP|SPW|TX|timecode_s~1_combout ;
wire \A_SPW_TOP|SPW|TX|timecode_s~0_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout~10_combout ;
wire \A_SPW_TOP|SPW|TX|timecode_s~8_combout ;
wire \A_SPW_TOP|SPW|TX|timecode_s~7_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout~12_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout~9_combout ;
wire \A_SPW_TOP|SPW|TX|timecode_s~5_combout ;
wire \A_SPW_TOP|SPW|TX|timecode_s~3_combout ;
wire \A_SPW_TOP|SPW|TX|timecode_s~6_combout ;
wire \A_SPW_TOP|SPW|TX|timecode_s~4_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout~11_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout~13_combout ;
wire \A_SPW_TOP|SPW|TX|Selector0~0_combout ;
wire \A_SPW_TOP|SPW|TX|always0~12_combout ;
wire \A_SPW_TOP|SPW|TX|always0~13_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout~36_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout~35_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout~32_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout~41_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout~42_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout~30_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout~29_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout~33_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout~40_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout~31_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout~34_combout ;
wire \A_SPW_TOP|SPW|TX|Selector0~9_combout ;
wire \A_SPW_TOP|SPW|TX|Selector0~11_combout ;
wire \A_SPW_TOP|SPW|TX|Selector0~10_combout ;
wire \A_SPW_TOP|SPW|TX|Selector0~12_combout ;
wire \A_SPW_TOP|SPW|TX|Selector0~7_combout ;
wire \A_SPW_TOP|SPW|TX|Selector0~8_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout~37_combout ;
wire \A_SPW_TOP|SPW|TX|Selector0~13_combout ;
wire \A_SPW_TOP|SPW|TX|Selector0~6_combout ;
wire \A_SPW_TOP|SPW|TX|Selector0~14_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout~q ;
wire \A_SPW_TOP|SPW|TX|tx_dout_e~q ;
wire \m_x|always3~0_combout ;
wire \m_x|control_r[0]~feeder_combout ;
wire \m_x|control~0_combout ;
wire \m_x|control_l_r~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][10]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~10_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][10]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~30_combout ;
wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~12_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~9_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][9]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~29_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~1_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~10 ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~6 ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~1_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3]~feeder_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][8]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~8_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][8]~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][8]~q ;
wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~15_combout ;
wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~16_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~14_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;
wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~17_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~18_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;
wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~13_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~12_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;
wire \A_SPW_TOP|SPW|RX|dta_timec_p[8]~feeder_combout ;
wire \A_SPW_TOP|SPW|RX|rx_data_flag~8_combout ;
wire \A_SPW_TOP|rx_data|wr_ptr[0]~0_combout ;
wire \A_SPW_TOP|rx_data|Add1~2_combout ;
wire \A_SPW_TOP|rx_data|Add1~1_combout ;
wire \A_SPW_TOP|rx_data|Add1~3_combout ;
wire \A_SPW_TOP|rx_data|Add1~0_combout ;
wire \A_SPW_TOP|rx_data|Add1~4_combout ;
wire \A_SPW_TOP|rx_data|Decoder0~52_combout ;
wire \A_SPW_TOP|rx_data|Selector244~0_combout ;
wire \A_SPW_TOP|rx_data|Decoder0~44_combout ;
wire \A_SPW_TOP|rx_data|Selector145~0_combout ;
wire \A_SPW_TOP|rx_data|Selector145~1_combout ;
wire \A_SPW_TOP|rx_data|mem[14][8]~q ;
wire \A_SPW_TOP|rx_data|Decoder0~51_combout ;
wire \A_SPW_TOP|rx_data|Selector289~0_combout ;
wire \A_SPW_TOP|rx_data|Selector289~1_combout ;
wire \A_SPW_TOP|rx_data|mem[30][8]~q ;
wire \A_SPW_TOP|rx_data|Decoder0~28_combout ;
wire \A_SPW_TOP|rx_data|Selector217~0_combout ;
wire \A_SPW_TOP|rx_data|Selector217~1_combout ;
wire \A_SPW_TOP|rx_data|mem[22][8]~q ;
wire \A_SPW_TOP|rx_data|Decoder0~12_combout ;
wire \A_SPW_TOP|rx_data|Selector73~0_combout ;
wire \A_SPW_TOP|rx_data|Selector73~1_combout ;
wire \A_SPW_TOP|rx_data|mem[6][8]~q ;
wire \A_SPW_TOP|rx_data|Mux0~7_combout ;
wire \A_SPW_TOP|rx_data|Decoder0~49_combout ;
wire \A_SPW_TOP|rx_data|Selector253~0_combout ;
wire \A_SPW_TOP|rx_data|Selector253~1_combout ;
wire \A_SPW_TOP|rx_data|mem[26][8]~q ;
wire \A_SPW_TOP|rx_data|Decoder0~24_combout ;
wire \A_SPW_TOP|rx_data|Selector181~0_combout ;
wire \A_SPW_TOP|rx_data|Selector181~1_combout ;
wire \A_SPW_TOP|rx_data|mem[18][8]~q ;
wire \A_SPW_TOP|rx_data|Decoder0~40_combout ;
wire \A_SPW_TOP|rx_data|Selector109~0_combout ;
wire \A_SPW_TOP|rx_data|Selector109~1_combout ;
wire \A_SPW_TOP|rx_data|mem[10][8]~q ;
wire \A_SPW_TOP|rx_data|Decoder0~8_combout ;
wire \A_SPW_TOP|rx_data|Selector37~0_combout ;
wire \A_SPW_TOP|rx_data|Selector37~1_combout ;
wire \A_SPW_TOP|rx_data|mem[2][8]~q ;
wire \A_SPW_TOP|rx_data|Mux0~5_combout ;
wire \A_SPW_TOP|rx_data|Decoder0~10_combout ;
wire \A_SPW_TOP|rx_data|Selector325~0_combout ;
wire \A_SPW_TOP|rx_data|Selector325~1_combout ;
wire \A_SPW_TOP|rx_data|mem[34][8]~q ;
wire \A_SPW_TOP|rx_data|Decoder0~42_combout ;
wire \A_SPW_TOP|rx_data|Selector397~0_combout ;
wire \A_SPW_TOP|rx_data|Selector397~1_combout ;
wire \A_SPW_TOP|rx_data|mem[42][8]~q ;
wire \A_SPW_TOP|rx_data|Decoder0~26_combout ;
wire \A_SPW_TOP|rx_data|Selector469~0_combout ;
wire \A_SPW_TOP|rx_data|Selector469~1_combout ;
wire \A_SPW_TOP|rx_data|mem[50][8]~q ;
wire \A_SPW_TOP|rx_data|Decoder0~57_combout ;
wire \A_SPW_TOP|rx_data|Selector541~0_combout ;
wire \A_SPW_TOP|rx_data|Selector541~1_combout ;
wire \A_SPW_TOP|rx_data|mem[58][8]~q ;
wire \A_SPW_TOP|rx_data|Mux0~6_combout ;
wire \A_SPW_TOP|rx_data|Decoder0~46_combout ;
wire \A_SPW_TOP|rx_data|Selector433~0_combout ;
wire \A_SPW_TOP|rx_data|Selector433~1_combout ;
wire \A_SPW_TOP|rx_data|mem[46][8]~q ;
wire \A_SPW_TOP|rx_data|Decoder0~14_combout ;
wire \A_SPW_TOP|rx_data|Selector361~0_combout ;
wire \A_SPW_TOP|rx_data|Selector361~1_combout ;
wire \A_SPW_TOP|rx_data|mem[38][8]~q ;
wire \A_SPW_TOP|rx_data|Decoder0~30_combout ;
wire \A_SPW_TOP|rx_data|Selector505~0_combout ;
wire \A_SPW_TOP|rx_data|Selector505~1_combout ;
wire \A_SPW_TOP|rx_data|mem[54][8]~q ;
wire \A_SPW_TOP|rx_data|Decoder0~59_combout ;
wire \A_SPW_TOP|rx_data|Selector577~0_combout ;
wire \A_SPW_TOP|rx_data|Selector577~1_combout ;
wire \A_SPW_TOP|rx_data|mem[62][8]~q ;
wire \A_SPW_TOP|rx_data|Mux0~8_combout ;
wire \A_SPW_TOP|rx_data|Mux0~9_combout ;
wire \A_SPW_TOP|rx_data|Decoder0~19_combout ;
wire \A_SPW_TOP|rx_data|Selector460~0_combout ;
wire \A_SPW_TOP|rx_data|Selector460~1_combout ;
wire \A_SPW_TOP|rx_data|mem[49][8]~q ;
wire \A_SPW_TOP|rx_data|Decoder0~21_combout ;
wire \A_SPW_TOP|rx_data|Selector208~0_combout ;
wire \A_SPW_TOP|rx_data|Selector208~1_combout ;
wire \A_SPW_TOP|rx_data|mem[21][8]~q ;
wire \A_SPW_TOP|rx_data|Decoder0~23_combout ;
wire \A_SPW_TOP|rx_data|Selector496~0_combout ;
wire \A_SPW_TOP|rx_data|Selector496~1_combout ;
wire \A_SPW_TOP|rx_data|mem[53][8]~q ;
wire \A_SPW_TOP|rx_data|Decoder0~17_combout ;
wire \A_SPW_TOP|rx_data|Selector172~0_combout ;
wire \A_SPW_TOP|rx_data|Selector172~1_combout ;
wire \A_SPW_TOP|rx_data|mem[17][8]~q ;
wire \A_SPW_TOP|rx_data|Mux0~12_combout ;
wire \A_SPW_TOP|rx_data|Decoder0~60_combout ;
wire \A_SPW_TOP|rx_data|Selector532~0_combout ;
wire \A_SPW_TOP|rx_data|Selector532~1_combout ;
wire \A_SPW_TOP|rx_data|mem[57][8]~q ;
wire \A_SPW_TOP|rx_data|Decoder0~62_combout ;
wire \A_SPW_TOP|rx_data|Selector568~0_combout ;
wire \A_SPW_TOP|rx_data|Selector568~1_combout ;
wire \A_SPW_TOP|rx_data|mem[61][8]~q ;
wire \A_SPW_TOP|rx_data|Decoder0~54_combout ;
wire \A_SPW_TOP|rx_data|Selector280~0_combout ;
wire \A_SPW_TOP|rx_data|Selector280~1_combout ;
wire \A_SPW_TOP|rx_data|mem[29][8]~q ;
wire \A_SPW_TOP|rx_data|Mux0~13_combout ;
wire \A_SPW_TOP|rx_data|Decoder0~37_combout ;
wire \A_SPW_TOP|rx_data|Selector136~0_combout ;
wire \A_SPW_TOP|rx_data|Selector136~1_combout ;
wire \A_SPW_TOP|rx_data|mem[13][8]~q ;
wire \A_SPW_TOP|rx_data|Decoder0~39_combout ;
wire \A_SPW_TOP|rx_data|Selector424~0_combout ;
wire \A_SPW_TOP|rx_data|Selector424~1_combout ;
wire \A_SPW_TOP|rx_data|mem[45][8]~q ;
wire \A_SPW_TOP|rx_data|Decoder0~33_combout ;
wire \A_SPW_TOP|rx_data|Selector100~0_combout ;
wire \A_SPW_TOP|rx_data|Selector100~1_combout ;
wire \A_SPW_TOP|rx_data|mem[9][8]~q ;
wire \A_SPW_TOP|rx_data|Decoder0~35_combout ;
wire \A_SPW_TOP|rx_data|Selector388~0_combout ;
wire \A_SPW_TOP|rx_data|Selector388~1_combout ;
wire \A_SPW_TOP|rx_data|mem[41][8]~q ;
wire \A_SPW_TOP|rx_data|Mux0~11_combout ;
wire \A_SPW_TOP|rx_data|Decoder0~1_combout ;
wire \A_SPW_TOP|rx_data|Selector28~0_combout ;
wire \A_SPW_TOP|rx_data|Selector28~1_combout ;
wire \A_SPW_TOP|rx_data|mem[1][8]~q ;
wire \A_SPW_TOP|rx_data|Decoder0~3_combout ;
wire \A_SPW_TOP|rx_data|Selector316~0_combout ;
wire \A_SPW_TOP|rx_data|Selector316~1_combout ;
wire \A_SPW_TOP|rx_data|mem[33][8]~q ;
wire \A_SPW_TOP|rx_data|Decoder0~7_combout ;
wire \A_SPW_TOP|rx_data|Selector352~0_combout ;
wire \A_SPW_TOP|rx_data|Selector352~1_combout ;
wire \A_SPW_TOP|rx_data|mem[37][8]~q ;
wire \A_SPW_TOP|rx_data|Decoder0~5_combout ;
wire \A_SPW_TOP|rx_data|Selector64~0_combout ;
wire \A_SPW_TOP|rx_data|Selector64~1_combout ;
wire \A_SPW_TOP|rx_data|mem[5][8]~q ;
wire \A_SPW_TOP|rx_data|Mux0~10_combout ;
wire \A_SPW_TOP|rx_data|Mux0~14_combout ;
wire \A_SPW_TOP|rx_data|Decoder0~56_combout ;
wire \A_SPW_TOP|rx_data|Selector523~0_combout ;
wire \A_SPW_TOP|rx_data|Selector523~1_combout ;
wire \A_SPW_TOP|rx_data|mem[56][8]~q ;
wire \A_SPW_TOP|rx_data|Decoder0~50_combout ;
wire \A_SPW_TOP|rx_data|Selector271~0_combout ;
wire \A_SPW_TOP|rx_data|Selector271~1_combout ;
wire \A_SPW_TOP|rx_data|mem[28][8]~q ;
wire \A_SPW_TOP|rx_data|Decoder0~48_combout ;
wire \A_SPW_TOP|rx_data|Selector235~0_combout ;
wire \A_SPW_TOP|rx_data|Selector235~1_combout ;
wire \A_SPW_TOP|rx_data|mem[24][8]~feeder_combout ;
wire \A_SPW_TOP|rx_data|mem[24][8]~q ;
wire \A_SPW_TOP|rx_data|Decoder0~58_combout ;
wire \A_SPW_TOP|rx_data|Selector559~0_combout ;
wire \A_SPW_TOP|rx_data|Selector559~1_combout ;
wire \A_SPW_TOP|rx_data|mem[60][8]~q ;
wire \A_SPW_TOP|rx_data|Mux0~3_combout ;
wire \A_SPW_TOP|rx_data|Decoder0~20_combout ;
wire \A_SPW_TOP|rx_data|Selector199~0_combout ;
wire \A_SPW_TOP|rx_data|Selector199~1_combout ;
wire \A_SPW_TOP|rx_data|mem[20][8]~q ;
wire \A_SPW_TOP|rx_data|Decoder0~18_combout ;
wire \A_SPW_TOP|rx_data|Selector451~0_combout ;
wire \A_SPW_TOP|rx_data|Selector451~1_combout ;
wire \A_SPW_TOP|rx_data|mem[48][8]~q ;
wire \A_SPW_TOP|rx_data|Decoder0~16_combout ;
wire \A_SPW_TOP|rx_data|Selector163~0_combout ;
wire \A_SPW_TOP|rx_data|Selector163~1_combout ;
wire \A_SPW_TOP|rx_data|mem[16][8]~q ;
wire \A_SPW_TOP|rx_data|Decoder0~22_combout ;
wire \A_SPW_TOP|rx_data|Selector487~0_combout ;
wire \A_SPW_TOP|rx_data|Selector487~1_combout ;
wire \A_SPW_TOP|rx_data|mem[52][8]~q ;
wire \A_SPW_TOP|rx_data|Mux0~2_combout ;
wire \A_SPW_TOP|rx_data|Decoder0~0_combout ;
wire \A_SPW_TOP|rx_data|Selector19~0_combout ;
wire \A_SPW_TOP|rx_data|Selector19~1_combout ;
wire \A_SPW_TOP|rx_data|mem[0][8]~q ;
wire \A_SPW_TOP|rx_data|Decoder0~6_combout ;
wire \A_SPW_TOP|rx_data|Selector343~0_combout ;
wire \A_SPW_TOP|rx_data|Selector343~1_combout ;
wire \A_SPW_TOP|rx_data|mem[36][8]~q ;
wire \A_SPW_TOP|rx_data|Decoder0~4_combout ;
wire \A_SPW_TOP|rx_data|Selector55~0_combout ;
wire \A_SPW_TOP|rx_data|Selector55~1_combout ;
wire \A_SPW_TOP|rx_data|mem[4][8]~q ;
wire \A_SPW_TOP|rx_data|Decoder0~2_combout ;
wire \A_SPW_TOP|rx_data|Selector307~0_combout ;
wire \A_SPW_TOP|rx_data|Selector307~1_combout ;
wire \A_SPW_TOP|rx_data|mem[32][8]~q ;
wire \A_SPW_TOP|rx_data|Mux0~0_combout ;
wire \A_SPW_TOP|rx_data|Decoder0~32_combout ;
wire \A_SPW_TOP|rx_data|Selector91~0_combout ;
wire \A_SPW_TOP|rx_data|Selector91~1_combout ;
wire \A_SPW_TOP|rx_data|mem[8][8]~q ;
wire \A_SPW_TOP|rx_data|Decoder0~34_combout ;
wire \A_SPW_TOP|rx_data|Selector379~0_combout ;
wire \A_SPW_TOP|rx_data|Selector379~1_combout ;
wire \A_SPW_TOP|rx_data|mem[40][8]~q ;
wire \A_SPW_TOP|rx_data|Decoder0~36_combout ;
wire \A_SPW_TOP|rx_data|Selector127~0_combout ;
wire \A_SPW_TOP|rx_data|Selector127~1_combout ;
wire \A_SPW_TOP|rx_data|mem[12][8]~q ;
wire \A_SPW_TOP|rx_data|Decoder0~38_combout ;
wire \A_SPW_TOP|rx_data|Selector415~0_combout ;
wire \A_SPW_TOP|rx_data|Selector415~1_combout ;
wire \A_SPW_TOP|rx_data|mem[44][8]~q ;
wire \A_SPW_TOP|rx_data|Mux0~1_combout ;
wire \A_SPW_TOP|rx_data|Mux0~4_combout ;
wire \A_SPW_TOP|rx_data|Decoder0~47_combout ;
wire \A_SPW_TOP|rx_data|Selector442~0_combout ;
wire \A_SPW_TOP|rx_data|Selector442~1_combout ;
wire \A_SPW_TOP|rx_data|mem[47][8]~feeder_combout ;
wire \A_SPW_TOP|rx_data|mem[47][8]~q ;
wire \A_SPW_TOP|rx_data|Decoder0~63_combout ;
wire \A_SPW_TOP|rx_data|Selector586~0_combout ;
wire \A_SPW_TOP|rx_data|Selector586~1_combout ;
wire \A_SPW_TOP|rx_data|mem[63][8]~q ;
wire \A_SPW_TOP|rx_data|Decoder0~31_combout ;
wire \A_SPW_TOP|rx_data|Selector514~0_combout ;
wire \A_SPW_TOP|rx_data|Selector514~1_combout ;
wire \A_SPW_TOP|rx_data|mem[55][8]~q ;
wire \A_SPW_TOP|rx_data|Decoder0~15_combout ;
wire \A_SPW_TOP|rx_data|Selector370~0_combout ;
wire \A_SPW_TOP|rx_data|Selector370~1_combout ;
wire \A_SPW_TOP|rx_data|mem[39][8]~q ;
wire \A_SPW_TOP|rx_data|Mux0~18_combout ;
wire \A_SPW_TOP|rx_data|Decoder0~29_combout ;
wire \A_SPW_TOP|rx_data|Selector226~0_combout ;
wire \A_SPW_TOP|rx_data|Selector226~1_combout ;
wire \A_SPW_TOP|rx_data|mem[23][8]~q ;
wire \A_SPW_TOP|rx_data|Decoder0~55_combout ;
wire \A_SPW_TOP|rx_data|Selector298~0_combout ;
wire \A_SPW_TOP|rx_data|Selector298~1_combout ;
wire \A_SPW_TOP|rx_data|mem[31][8]~q ;
wire \A_SPW_TOP|rx_data|Decoder0~45_combout ;
wire \A_SPW_TOP|rx_data|Selector154~0_combout ;
wire \A_SPW_TOP|rx_data|Selector154~1_combout ;
wire \A_SPW_TOP|rx_data|mem[15][8]~q ;
wire \A_SPW_TOP|rx_data|Decoder0~13_combout ;
wire \A_SPW_TOP|rx_data|Selector82~0_combout ;
wire \A_SPW_TOP|rx_data|Selector82~1_combout ;
wire \A_SPW_TOP|rx_data|mem[7][8]~q ;
wire \A_SPW_TOP|rx_data|Mux0~17_combout ;
wire \A_SPW_TOP|rx_data|Decoder0~9_combout ;
wire \A_SPW_TOP|rx_data|Selector46~0_combout ;
wire \A_SPW_TOP|rx_data|Selector46~1_combout ;
wire \A_SPW_TOP|rx_data|mem[3][8]~q ;
wire \A_SPW_TOP|rx_data|Decoder0~41_combout ;
wire \A_SPW_TOP|rx_data|Selector118~0_combout ;
wire \A_SPW_TOP|rx_data|Selector118~1_combout ;
wire \A_SPW_TOP|rx_data|mem[11][8]~q ;
wire \A_SPW_TOP|rx_data|Decoder0~53_combout ;
wire \A_SPW_TOP|rx_data|Selector262~0_combout ;
wire \A_SPW_TOP|rx_data|Selector262~1_combout ;
wire \A_SPW_TOP|rx_data|mem[27][8]~q ;
wire \A_SPW_TOP|rx_data|Decoder0~25_combout ;
wire \A_SPW_TOP|rx_data|Selector190~0_combout ;
wire \A_SPW_TOP|rx_data|Selector190~1_combout ;
wire \A_SPW_TOP|rx_data|mem[19][8]~q ;
wire \A_SPW_TOP|rx_data|Mux0~15_combout ;
wire \A_SPW_TOP|rx_data|Decoder0~27_combout ;
wire \A_SPW_TOP|rx_data|Selector478~0_combout ;
wire \A_SPW_TOP|rx_data|Selector478~1_combout ;
wire \A_SPW_TOP|rx_data|mem[51][8]~q ;
wire \A_SPW_TOP|rx_data|Decoder0~61_combout ;
wire \A_SPW_TOP|rx_data|Selector550~0_combout ;
wire \A_SPW_TOP|rx_data|Selector550~1_combout ;
wire \A_SPW_TOP|rx_data|mem[59][8]~q ;
wire \A_SPW_TOP|rx_data|Decoder0~43_combout ;
wire \A_SPW_TOP|rx_data|Selector406~0_combout ;
wire \A_SPW_TOP|rx_data|Selector406~1_combout ;
wire \A_SPW_TOP|rx_data|mem[43][8]~q ;
wire \A_SPW_TOP|rx_data|Decoder0~11_combout ;
wire \A_SPW_TOP|rx_data|Selector334~0_combout ;
wire \A_SPW_TOP|rx_data|Selector334~1_combout ;
wire \A_SPW_TOP|rx_data|mem[35][8]~q ;
wire \A_SPW_TOP|rx_data|Mux0~16_combout ;
wire \A_SPW_TOP|rx_data|Mux0~19_combout ;
wire \A_SPW_TOP|rx_data|Mux0~20_combout ;
wire \A_SPW_TOP|rx_data|Selector244~1_combout ;
wire \A_SPW_TOP|rx_data|mem[25][8]~q ;
wire \A_SPW_TOP|rx_data|Add9~10 ;
wire \A_SPW_TOP|rx_data|Add9~21_sumout ;
wire \A_SPW_TOP|rx_data|rd_ptr[3]~feeder_combout ;
wire \A_SPW_TOP|rx_data|Add9~22 ;
wire \A_SPW_TOP|rx_data|Add9~17_sumout ;
wire \A_SPW_TOP|rx_data|Mux9~1_combout ;
wire \A_SPW_TOP|rx_data|Mux9~3_combout ;
wire \A_SPW_TOP|rx_data|Mux9~0_combout ;
wire \A_SPW_TOP|rx_data|Add9~18 ;
wire \A_SPW_TOP|rx_data|Add9~5_sumout ;
wire \A_SPW_TOP|rx_data|rd_ptr[5]~feeder_combout ;
wire \A_SPW_TOP|rx_data|Mux9~2_combout ;
wire \A_SPW_TOP|rx_data|Mux9~4_combout ;
wire \A_SPW_TOP|rx_data|Mux9~16_combout ;
wire \A_SPW_TOP|rx_data|Mux9~17_combout ;
wire \A_SPW_TOP|rx_data|Mux9~15_combout ;
wire \A_SPW_TOP|rx_data|Mux9~18_combout ;
wire \A_SPW_TOP|rx_data|Mux9~19_combout ;
wire \A_SPW_TOP|rx_data|Mux9~11_combout ;
wire \A_SPW_TOP|rx_data|Mux9~12_combout ;
wire \A_SPW_TOP|rx_data|Mux9~13_combout ;
wire \A_SPW_TOP|rx_data|Mux9~10_combout ;
wire \A_SPW_TOP|rx_data|Mux9~14_combout ;
wire \A_SPW_TOP|rx_data|Mux9~7_combout ;
wire \A_SPW_TOP|rx_data|Mux9~5_combout ;
wire \A_SPW_TOP|rx_data|Mux9~6_combout ;
wire \A_SPW_TOP|rx_data|Mux9~8_combout ;
wire \A_SPW_TOP|rx_data|Mux9~9_combout ;
wire \A_SPW_TOP|rx_data|Mux9~20_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~8_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][8]~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][8]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~8_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][8]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[8]~83_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[8]~84_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[8]~85_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|LessThan18~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~5_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2]~feeder_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][7]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~7_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][7]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~79_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|read~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|read~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[1]~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][7]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~7_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][7]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~80_combout ;
wire \A_SPW_TOP|SPW|RX|rx_data_flag~0_combout ;
wire \A_SPW_TOP|SPW|RX|rx_data_flag~7_combout ;
wire \A_SPW_TOP|rx_data|Selector371~0_combout ;
wire \A_SPW_TOP|rx_data|mem[39][7]~q ;
wire \A_SPW_TOP|rx_data|Selector344~0_combout ;
wire \A_SPW_TOP|rx_data|mem[36][7]~q ;
wire \A_SPW_TOP|rx_data|Selector362~0_combout ;
wire \A_SPW_TOP|rx_data|mem[38][7]~q ;
wire \A_SPW_TOP|rx_data|Selector353~0_combout ;
wire \A_SPW_TOP|rx_data|mem[37][7]~q ;
wire \A_SPW_TOP|rx_data|Mux1~12_combout ;
wire \A_SPW_TOP|rx_data|Selector65~0_combout ;
wire \A_SPW_TOP|rx_data|mem[5][7]~q ;
wire \A_SPW_TOP|rx_data|Selector56~0_combout ;
wire \A_SPW_TOP|rx_data|mem[4][7]~q ;
wire \A_SPW_TOP|rx_data|Selector83~0_combout ;
wire \A_SPW_TOP|rx_data|mem[7][7]~q ;
wire \A_SPW_TOP|rx_data|Selector74~0_combout ;
wire \A_SPW_TOP|rx_data|mem[6][7]~q ;
wire \A_SPW_TOP|rx_data|Mux1~10_combout ;
wire \A_SPW_TOP|rx_data|Selector416~0_combout ;
wire \A_SPW_TOP|rx_data|mem[44][7]~q ;
wire \A_SPW_TOP|rx_data|Selector425~0_combout ;
wire \A_SPW_TOP|rx_data|mem[45][7]~q ;
wire \A_SPW_TOP|rx_data|Selector434~0_combout ;
wire \A_SPW_TOP|rx_data|mem[46][7]~q ;
wire \A_SPW_TOP|rx_data|Selector443~0_combout ;
wire \A_SPW_TOP|rx_data|mem[47][7]~q ;
wire \A_SPW_TOP|rx_data|Mux1~13_combout ;
wire \A_SPW_TOP|rx_data|Selector146~0_combout ;
wire \A_SPW_TOP|rx_data|mem[14][7]~q ;
wire \A_SPW_TOP|rx_data|Selector137~0_combout ;
wire \A_SPW_TOP|rx_data|mem[13][7]~q ;
wire \A_SPW_TOP|rx_data|Selector128~0_combout ;
wire \A_SPW_TOP|rx_data|mem[12][7]~q ;
wire \A_SPW_TOP|rx_data|Selector155~0_combout ;
wire \A_SPW_TOP|rx_data|mem[15][7]~q ;
wire \A_SPW_TOP|rx_data|Mux1~11_combout ;
wire \A_SPW_TOP|rx_data|Mux1~14_combout ;
wire \A_SPW_TOP|rx_data|Selector533~0_combout ;
wire \A_SPW_TOP|rx_data|mem[57][7]~q ;
wire \A_SPW_TOP|rx_data|Selector551~0_combout ;
wire \A_SPW_TOP|rx_data|mem[59][7]~q ;
wire \A_SPW_TOP|rx_data|Selector542~0_combout ;
wire \A_SPW_TOP|rx_data|mem[58][7]~q ;
wire \A_SPW_TOP|rx_data|Selector524~0_combout ;
wire \A_SPW_TOP|rx_data|mem[56][7]~q ;
wire \A_SPW_TOP|rx_data|Mux1~8_combout ;
wire \A_SPW_TOP|rx_data|Selector236~0_combout ;
wire \A_SPW_TOP|rx_data|mem[24][7]~q ;
wire \A_SPW_TOP|rx_data|Selector254~0_combout ;
wire \A_SPW_TOP|rx_data|mem[26][7]~q ;
wire \A_SPW_TOP|rx_data|Selector245~0_combout ;
wire \A_SPW_TOP|rx_data|mem[25][7]~feeder_combout ;
wire \A_SPW_TOP|rx_data|mem[25][7]~q ;
wire \A_SPW_TOP|rx_data|Selector263~0_combout ;
wire \A_SPW_TOP|rx_data|mem[27][7]~q ;
wire \A_SPW_TOP|rx_data|Mux1~6_combout ;
wire \A_SPW_TOP|rx_data|Selector164~0_combout ;
wire \A_SPW_TOP|rx_data|mem[16][7]~q ;
wire \A_SPW_TOP|rx_data|Selector182~0_combout ;
wire \A_SPW_TOP|rx_data|mem[18][7]~q ;
wire \A_SPW_TOP|rx_data|Selector173~0_combout ;
wire \A_SPW_TOP|rx_data|mem[17][7]~feeder_combout ;
wire \A_SPW_TOP|rx_data|mem[17][7]~q ;
wire \A_SPW_TOP|rx_data|Selector191~0_combout ;
wire \A_SPW_TOP|rx_data|mem[19][7]~q ;
wire \A_SPW_TOP|rx_data|Mux1~5_combout ;
wire \A_SPW_TOP|rx_data|Selector461~0_combout ;
wire \A_SPW_TOP|rx_data|mem[49][7]~q ;
wire \A_SPW_TOP|rx_data|Selector470~0_combout ;
wire \A_SPW_TOP|rx_data|mem[50][7]~q ;
wire \A_SPW_TOP|rx_data|Selector452~0_combout ;
wire \A_SPW_TOP|rx_data|mem[48][7]~q ;
wire \A_SPW_TOP|rx_data|Selector479~0_combout ;
wire \A_SPW_TOP|rx_data|mem[51][7]~q ;
wire \A_SPW_TOP|rx_data|Mux1~7_combout ;
wire \A_SPW_TOP|rx_data|Mux1~9_combout ;
wire \A_SPW_TOP|rx_data|Selector281~0_combout ;
wire \A_SPW_TOP|rx_data|mem[29][7]~q ;
wire \A_SPW_TOP|rx_data|Selector569~0_combout ;
wire \A_SPW_TOP|rx_data|mem[61][7]~q ;
wire \A_SPW_TOP|rx_data|Selector299~0_combout ;
wire \A_SPW_TOP|rx_data|mem[31][7]~q ;
wire \A_SPW_TOP|rx_data|Selector587~0_combout ;
wire \A_SPW_TOP|rx_data|mem[63][7]~q ;
wire \A_SPW_TOP|rx_data|Mux1~18_combout ;
wire \A_SPW_TOP|rx_data|Selector209~0_combout ;
wire \A_SPW_TOP|rx_data|mem[21][7]~q ;
wire \A_SPW_TOP|rx_data|Selector227~0_combout ;
wire \A_SPW_TOP|rx_data|mem[23][7]~q ;
wire \A_SPW_TOP|rx_data|Selector497~0_combout ;
wire \A_SPW_TOP|rx_data|mem[53][7]~q ;
wire \A_SPW_TOP|rx_data|Mux1~17_combout ;
wire \A_SPW_TOP|rx_data|Selector488~0_combout ;
wire \A_SPW_TOP|rx_data|mem[52][7]~q ;
wire \A_SPW_TOP|rx_data|Selector506~0_combout ;
wire \A_SPW_TOP|rx_data|mem[54][7]~q ;
wire \A_SPW_TOP|rx_data|Selector200~0_combout ;
wire \A_SPW_TOP|rx_data|mem[20][7]~q ;
wire \A_SPW_TOP|rx_data|Selector218~0_combout ;
wire \A_SPW_TOP|rx_data|mem[22][7]~q ;
wire \A_SPW_TOP|rx_data|Mux1~15_combout ;
wire \A_SPW_TOP|rx_data|Selector578~0_combout ;
wire \A_SPW_TOP|rx_data|mem[62][7]~q ;
wire \A_SPW_TOP|rx_data|Selector272~0_combout ;
wire \A_SPW_TOP|rx_data|mem[28][7]~q ;
wire \A_SPW_TOP|rx_data|Selector290~0_combout ;
wire \A_SPW_TOP|rx_data|mem[30][7]~q ;
wire \A_SPW_TOP|rx_data|Selector560~0_combout ;
wire \A_SPW_TOP|rx_data|mem[60][7]~q ;
wire \A_SPW_TOP|rx_data|Mux1~16_combout ;
wire \A_SPW_TOP|rx_data|Mux1~19_combout ;
wire \A_SPW_TOP|rx_data|Selector398~0_combout ;
wire \A_SPW_TOP|rx_data|mem[42][7]~q ;
wire \A_SPW_TOP|rx_data|Selector380~0_combout ;
wire \A_SPW_TOP|rx_data|mem[40][7]~q ;
wire \A_SPW_TOP|rx_data|Selector407~0_combout ;
wire \A_SPW_TOP|rx_data|mem[43][7]~q ;
wire \A_SPW_TOP|rx_data|Selector389~0_combout ;
wire \A_SPW_TOP|rx_data|mem[41][7]~q ;
wire \A_SPW_TOP|rx_data|Mux1~3_combout ;
wire \A_SPW_TOP|rx_data|Selector110~0_combout ;
wire \A_SPW_TOP|rx_data|mem[10][7]~q ;
wire \A_SPW_TOP|rx_data|Selector92~0_combout ;
wire \A_SPW_TOP|rx_data|mem[8][7]~q ;
wire \A_SPW_TOP|rx_data|Selector119~0_combout ;
wire \A_SPW_TOP|rx_data|mem[11][7]~q ;
wire \A_SPW_TOP|rx_data|Selector101~0_combout ;
wire \A_SPW_TOP|rx_data|mem[9][7]~q ;
wire \A_SPW_TOP|rx_data|Mux1~1_combout ;
wire \A_SPW_TOP|rx_data|Selector47~0_combout ;
wire \A_SPW_TOP|rx_data|mem[3][7]~q ;
wire \A_SPW_TOP|rx_data|Selector38~0_combout ;
wire \A_SPW_TOP|rx_data|mem[2][7]~q ;
wire \A_SPW_TOP|rx_data|Selector20~0_combout ;
wire \A_SPW_TOP|rx_data|mem[0][7]~q ;
wire \A_SPW_TOP|rx_data|Selector29~0_combout ;
wire \A_SPW_TOP|rx_data|mem[1][7]~q ;
wire \A_SPW_TOP|rx_data|Mux1~0_combout ;
wire \A_SPW_TOP|rx_data|Selector335~0_combout ;
wire \A_SPW_TOP|rx_data|mem[35][7]~q ;
wire \A_SPW_TOP|rx_data|Selector308~0_combout ;
wire \A_SPW_TOP|rx_data|mem[32][7]~q ;
wire \A_SPW_TOP|rx_data|Selector326~0_combout ;
wire \A_SPW_TOP|rx_data|mem[34][7]~q ;
wire \A_SPW_TOP|rx_data|Selector317~0_combout ;
wire \A_SPW_TOP|rx_data|mem[33][7]~q ;
wire \A_SPW_TOP|rx_data|Mux1~2_combout ;
wire \A_SPW_TOP|rx_data|Mux1~4_combout ;
wire \A_SPW_TOP|rx_data|Mux1~20_combout ;
wire \A_SPW_TOP|rx_data|Selector515~0_combout ;
wire \A_SPW_TOP|rx_data|mem[55][7]~q ;
wire \A_SPW_TOP|rx_data|Mux10~16_combout ;
wire \A_SPW_TOP|rx_data|Mux10~15_combout ;
wire \A_SPW_TOP|rx_data|Mux10~17_combout ;
wire \A_SPW_TOP|rx_data|Mux10~18_combout ;
wire \A_SPW_TOP|rx_data|Mux10~19_combout ;
wire \A_SPW_TOP|rx_data|Mux10~3_combout ;
wire \A_SPW_TOP|rx_data|Mux10~2_combout ;
wire \A_SPW_TOP|rx_data|Mux10~0_combout ;
wire \A_SPW_TOP|rx_data|Mux10~1_combout ;
wire \A_SPW_TOP|rx_data|Mux10~4_combout ;
wire \A_SPW_TOP|rx_data|Mux10~8_combout ;
wire \A_SPW_TOP|rx_data|Mux10~5_combout ;
wire \A_SPW_TOP|rx_data|Mux10~7_combout ;
wire \A_SPW_TOP|rx_data|Mux10~6_combout ;
wire \A_SPW_TOP|rx_data|Mux10~9_combout ;
wire \A_SPW_TOP|rx_data|Mux10~11_combout ;
wire \A_SPW_TOP|rx_data|Mux10~12_combout ;
wire \A_SPW_TOP|rx_data|Mux10~10_combout ;
wire \A_SPW_TOP|rx_data|Mux10~13_combout ;
wire \A_SPW_TOP|rx_data|Mux10~14_combout ;
wire \A_SPW_TOP|rx_data|Mux10~20_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][7]~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~7_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][7]~q ;
wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~12_combout ;
wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~14_combout ;
wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~15_combout ;
wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~16_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;
wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~13_combout ;
wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~17_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~18_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;
wire \A_SPW_TOP|SPW|RX|timecode~0_combout ;
wire \A_SPW_TOP|SPW|RX|timecode~8_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][7]~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~7_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][7]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~81_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~82_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][7]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~7_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][7]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~206_combout ;
wire \u0|mm_interconnect_0|cmd_mux_010|src_payload~6_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~6_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][6]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~75_combout ;
wire \A_SPW_TOP|SPW|RX|rx_data_flag~6_combout ;
wire \A_SPW_TOP|rx_data|Selector507~0_combout ;
wire \A_SPW_TOP|rx_data|mem[54][6]~q ;
wire \A_SPW_TOP|rx_data|Selector363~0_combout ;
wire \A_SPW_TOP|rx_data|mem[38][6]~q ;
wire \A_SPW_TOP|rx_data|Selector471~0_combout ;
wire \A_SPW_TOP|rx_data|mem[50][6]~q ;
wire \A_SPW_TOP|rx_data|Selector327~0_combout ;
wire \A_SPW_TOP|rx_data|mem[34][6]~q ;
wire \A_SPW_TOP|rx_data|Mux2~12_combout ;
wire \A_SPW_TOP|rx_data|Selector309~0_combout ;
wire \A_SPW_TOP|rx_data|mem[32][6]~q ;
wire \A_SPW_TOP|rx_data|Selector345~0_combout ;
wire \A_SPW_TOP|rx_data|mem[36][6]~q ;
wire \A_SPW_TOP|rx_data|Selector489~0_combout ;
wire \A_SPW_TOP|rx_data|mem[52][6]~q ;
wire \A_SPW_TOP|rx_data|Selector453~0_combout ;
wire \A_SPW_TOP|rx_data|mem[48][6]~q ;
wire \A_SPW_TOP|rx_data|Mux2~10_combout ;
wire \A_SPW_TOP|rx_data|Selector462~0_combout ;
wire \A_SPW_TOP|rx_data|mem[49][6]~q ;
wire \A_SPW_TOP|rx_data|Selector318~0_combout ;
wire \A_SPW_TOP|rx_data|mem[33][6]~q ;
wire \A_SPW_TOP|rx_data|Selector498~0_combout ;
wire \A_SPW_TOP|rx_data|mem[53][6]~q ;
wire \A_SPW_TOP|rx_data|Selector354~0_combout ;
wire \A_SPW_TOP|rx_data|mem[37][6]~q ;
wire \A_SPW_TOP|rx_data|Mux2~11_combout ;
wire \A_SPW_TOP|rx_data|Selector336~0_combout ;
wire \A_SPW_TOP|rx_data|mem[35][6]~q ;
wire \A_SPW_TOP|rx_data|Selector480~0_combout ;
wire \A_SPW_TOP|rx_data|mem[51][6]~q ;
wire \A_SPW_TOP|rx_data|Selector372~0_combout ;
wire \A_SPW_TOP|rx_data|mem[39][6]~feeder_combout ;
wire \A_SPW_TOP|rx_data|mem[39][6]~q ;
wire \A_SPW_TOP|rx_data|Selector516~0_combout ;
wire \A_SPW_TOP|rx_data|mem[55][6]~q ;
wire \A_SPW_TOP|rx_data|Mux2~13_combout ;
wire \A_SPW_TOP|rx_data|Mux2~14_combout ;
wire \A_SPW_TOP|rx_data|Selector111~0_combout ;
wire \A_SPW_TOP|rx_data|mem[10][6]~q ;
wire \A_SPW_TOP|rx_data|Selector156~0_combout ;
wire \A_SPW_TOP|rx_data|mem[15][6]~q ;
wire \A_SPW_TOP|rx_data|Selector120~0_combout ;
wire \A_SPW_TOP|rx_data|mem[11][6]~q ;
wire \A_SPW_TOP|rx_data|Selector147~0_combout ;
wire \A_SPW_TOP|rx_data|mem[14][6]~q ;
wire \A_SPW_TOP|rx_data|Mux2~7_combout ;
wire \A_SPW_TOP|rx_data|Selector300~0_combout ;
wire \A_SPW_TOP|rx_data|mem[31][6]~q ;
wire \A_SPW_TOP|rx_data|Selector264~0_combout ;
wire \A_SPW_TOP|rx_data|mem[27][6]~q ;
wire \A_SPW_TOP|rx_data|Selector255~0_combout ;
wire \A_SPW_TOP|rx_data|mem[26][6]~q ;
wire \A_SPW_TOP|rx_data|Selector291~0_combout ;
wire \A_SPW_TOP|rx_data|mem[30][6]~q ;
wire \A_SPW_TOP|rx_data|Mux2~8_combout ;
wire \A_SPW_TOP|rx_data|Selector273~0_combout ;
wire \A_SPW_TOP|rx_data|mem[28][6]~q ;
wire \A_SPW_TOP|rx_data|Selector237~0_combout ;
wire \A_SPW_TOP|rx_data|mem[24][6]~q ;
wire \A_SPW_TOP|rx_data|Selector246~0_combout ;
wire \A_SPW_TOP|rx_data|mem[25][6]~q ;
wire \A_SPW_TOP|rx_data|Mux2~6_combout ;
wire \A_SPW_TOP|rx_data|Selector138~0_combout ;
wire \A_SPW_TOP|rx_data|mem[13][6]~q ;
wire \A_SPW_TOP|rx_data|Selector129~0_combout ;
wire \A_SPW_TOP|rx_data|mem[12][6]~q ;
wire \A_SPW_TOP|rx_data|Selector93~0_combout ;
wire \A_SPW_TOP|rx_data|mem[8][6]~q ;
wire \A_SPW_TOP|rx_data|Selector102~0_combout ;
wire \A_SPW_TOP|rx_data|mem[9][6]~q ;
wire \A_SPW_TOP|rx_data|Mux2~5_combout ;
wire \A_SPW_TOP|rx_data|Mux2~9_combout ;
wire \A_SPW_TOP|rx_data|Selector48~0_combout ;
wire \A_SPW_TOP|rx_data|mem[3][6]~q ;
wire \A_SPW_TOP|rx_data|Selector228~0_combout ;
wire \A_SPW_TOP|rx_data|mem[23][6]~q ;
wire \A_SPW_TOP|rx_data|Selector192~0_combout ;
wire \A_SPW_TOP|rx_data|mem[19][6]~q ;
wire \A_SPW_TOP|rx_data|Selector84~0_combout ;
wire \A_SPW_TOP|rx_data|mem[7][6]~q ;
wire \A_SPW_TOP|rx_data|Mux2~3_combout ;
wire \A_SPW_TOP|rx_data|Selector66~0_combout ;
wire \A_SPW_TOP|rx_data|mem[5][6]~q ;
wire \A_SPW_TOP|rx_data|Selector30~0_combout ;
wire \A_SPW_TOP|rx_data|mem[1][6]~q ;
wire \A_SPW_TOP|rx_data|Selector210~0_combout ;
wire \A_SPW_TOP|rx_data|mem[21][6]~q ;
wire \A_SPW_TOP|rx_data|Selector174~0_combout ;
wire \A_SPW_TOP|rx_data|mem[17][6]~q ;
wire \A_SPW_TOP|rx_data|Mux2~1_combout ;
wire \A_SPW_TOP|rx_data|Selector21~0_combout ;
wire \A_SPW_TOP|rx_data|mem[0][6]~q ;
wire \A_SPW_TOP|rx_data|Selector201~0_combout ;
wire \A_SPW_TOP|rx_data|mem[20][6]~q ;
wire \A_SPW_TOP|rx_data|Selector57~0_combout ;
wire \A_SPW_TOP|rx_data|mem[4][6]~q ;
wire \A_SPW_TOP|rx_data|Selector165~0_combout ;
wire \A_SPW_TOP|rx_data|mem[16][6]~q ;
wire \A_SPW_TOP|rx_data|Mux2~0_combout ;
wire \A_SPW_TOP|rx_data|Selector75~0_combout ;
wire \A_SPW_TOP|rx_data|mem[6][6]~q ;
wire \A_SPW_TOP|rx_data|Selector219~0_combout ;
wire \A_SPW_TOP|rx_data|mem[22][6]~q ;
wire \A_SPW_TOP|rx_data|Selector39~0_combout ;
wire \A_SPW_TOP|rx_data|mem[2][6]~q ;
wire \A_SPW_TOP|rx_data|Selector183~0_combout ;
wire \A_SPW_TOP|rx_data|mem[18][6]~q ;
wire \A_SPW_TOP|rx_data|Mux2~2_combout ;
wire \A_SPW_TOP|rx_data|Mux2~4_combout ;
wire \A_SPW_TOP|rx_data|Selector525~0_combout ;
wire \A_SPW_TOP|rx_data|mem[56][6]~q ;
wire \A_SPW_TOP|rx_data|Selector381~0_combout ;
wire \A_SPW_TOP|rx_data|mem[40][6]~q ;
wire \A_SPW_TOP|rx_data|Selector399~0_combout ;
wire \A_SPW_TOP|rx_data|mem[42][6]~q ;
wire \A_SPW_TOP|rx_data|Selector543~0_combout ;
wire \A_SPW_TOP|rx_data|mem[58][6]~q ;
wire \A_SPW_TOP|rx_data|Mux2~15_combout ;
wire \A_SPW_TOP|rx_data|Selector570~0_combout ;
wire \A_SPW_TOP|rx_data|mem[61][6]~q ;
wire \A_SPW_TOP|rx_data|Selector426~0_combout ;
wire \A_SPW_TOP|rx_data|mem[45][6]~q ;
wire \A_SPW_TOP|rx_data|Selector444~0_combout ;
wire \A_SPW_TOP|rx_data|mem[47][6]~q ;
wire \A_SPW_TOP|rx_data|Selector588~0_combout ;
wire \A_SPW_TOP|rx_data|mem[63][6]~q ;
wire \A_SPW_TOP|rx_data|Mux2~18_combout ;
wire \A_SPW_TOP|rx_data|Selector390~0_combout ;
wire \A_SPW_TOP|rx_data|mem[41][6]~q ;
wire \A_SPW_TOP|rx_data|Selector408~0_combout ;
wire \A_SPW_TOP|rx_data|mem[43][6]~q ;
wire \A_SPW_TOP|rx_data|Selector534~0_combout ;
wire \A_SPW_TOP|rx_data|mem[57][6]~q ;
wire \A_SPW_TOP|rx_data|Selector552~0_combout ;
wire \A_SPW_TOP|rx_data|mem[59][6]~q ;
wire \A_SPW_TOP|rx_data|Mux2~16_combout ;
wire \A_SPW_TOP|rx_data|Selector561~0_combout ;
wire \A_SPW_TOP|rx_data|mem[60][6]~q ;
wire \A_SPW_TOP|rx_data|Selector435~0_combout ;
wire \A_SPW_TOP|rx_data|mem[46][6]~q ;
wire \A_SPW_TOP|rx_data|Selector579~0_combout ;
wire \A_SPW_TOP|rx_data|mem[62][6]~q ;
wire \A_SPW_TOP|rx_data|Selector417~0_combout ;
wire \A_SPW_TOP|rx_data|mem[44][6]~q ;
wire \A_SPW_TOP|rx_data|Mux2~17_combout ;
wire \A_SPW_TOP|rx_data|Mux2~19_combout ;
wire \A_SPW_TOP|rx_data|Mux2~20_combout ;
wire \A_SPW_TOP|rx_data|Selector282~0_combout ;
wire \A_SPW_TOP|rx_data|mem[29][6]~q ;
wire \A_SPW_TOP|rx_data|Mux11~15_combout ;
wire \A_SPW_TOP|rx_data|Mux11~17_combout ;
wire \A_SPW_TOP|rx_data|Mux11~16_combout ;
wire \A_SPW_TOP|rx_data|Mux11~18_combout ;
wire \A_SPW_TOP|rx_data|Mux11~19_combout ;
wire \A_SPW_TOP|rx_data|Mux11~2_combout ;
wire \A_SPW_TOP|rx_data|Mux11~3_combout ;
wire \A_SPW_TOP|rx_data|Mux11~1_combout ;
wire \A_SPW_TOP|rx_data|Mux11~0_combout ;
wire \A_SPW_TOP|rx_data|Mux11~4_combout ;
wire \A_SPW_TOP|rx_data|Mux11~10_combout ;
wire \A_SPW_TOP|rx_data|Mux11~12_combout ;
wire \A_SPW_TOP|rx_data|Mux11~11_combout ;
wire \A_SPW_TOP|rx_data|Mux11~13_combout ;
wire \A_SPW_TOP|rx_data|Mux11~14_combout ;
wire \A_SPW_TOP|rx_data|Mux11~8_combout ;
wire \A_SPW_TOP|rx_data|Mux11~6_combout ;
wire \A_SPW_TOP|rx_data|Mux11~7_combout ;
wire \A_SPW_TOP|rx_data|Mux11~5_combout ;
wire \A_SPW_TOP|rx_data|Mux11~9_combout ;
wire \A_SPW_TOP|rx_data|Mux11~20_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][6]~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~6_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][6]~q ;
wire \A_SPW_TOP|SPW|RX|timecode~7_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[6]~feeder_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][6]~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~6_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][6]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~77_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~78_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][6]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~6_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][6]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~76_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][6]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~6_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][6]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~210_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~2_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~3_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_010|src_valid~0_combout ;
wire \u0|mm_interconnect_0|router_001|Equal16~0_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|src10_valid~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_010|src_valid~1_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_read~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg~1_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used[1]~1_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~5_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][5]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~66_combout ;
wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~12_combout ;
wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~14_combout ;
wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~15_combout ;
wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~16_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;
wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~13_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~17_combout ;
wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~18_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;
wire \u0|counter_rx_fifo|read_mux_out[5]~5_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][5]~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~5_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][5]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~68_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][5]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~5_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][5]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~67_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][5]~q ;
wire \A_SPW_TOP|SPW|RX|timecode~6_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~5_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][5]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~69_combout ;
wire \A_SPW_TOP|SPW|RX|rx_data_flag~5_combout ;
wire \A_SPW_TOP|rx_data|Selector481~0_combout ;
wire \A_SPW_TOP|rx_data|mem[51][5]~q ;
wire \A_SPW_TOP|rx_data|Selector517~0_combout ;
wire \A_SPW_TOP|rx_data|mem[55][5]~q ;
wire \A_SPW_TOP|rx_data|Selector553~0_combout ;
wire \A_SPW_TOP|rx_data|mem[59][5]~q ;
wire \A_SPW_TOP|rx_data|Selector589~0_combout ;
wire \A_SPW_TOP|rx_data|mem[63][5]~q ;
wire \A_SPW_TOP|rx_data|Mux3~18_combout ;
wire \A_SPW_TOP|rx_data|Selector337~0_combout ;
wire \A_SPW_TOP|rx_data|mem[35][5]~q ;
wire \A_SPW_TOP|rx_data|Selector445~0_combout ;
wire \A_SPW_TOP|rx_data|mem[47][5]~q ;
wire \A_SPW_TOP|rx_data|Selector409~0_combout ;
wire \A_SPW_TOP|rx_data|mem[43][5]~q ;
wire \A_SPW_TOP|rx_data|Selector373~0_combout ;
wire \A_SPW_TOP|rx_data|mem[39][5]~q ;
wire \A_SPW_TOP|rx_data|Mux3~16_combout ;
wire \A_SPW_TOP|rx_data|Selector265~0_combout ;
wire \A_SPW_TOP|rx_data|mem[27][5]~q ;
wire \A_SPW_TOP|rx_data|Selector193~0_combout ;
wire \A_SPW_TOP|rx_data|mem[19][5]~q ;
wire \A_SPW_TOP|rx_data|Selector301~0_combout ;
wire \A_SPW_TOP|rx_data|mem[31][5]~q ;
wire \A_SPW_TOP|rx_data|Selector229~0_combout ;
wire \A_SPW_TOP|rx_data|mem[23][5]~q ;
wire \A_SPW_TOP|rx_data|Mux3~17_combout ;
wire \A_SPW_TOP|rx_data|Selector121~0_combout ;
wire \A_SPW_TOP|rx_data|mem[11][5]~q ;
wire \A_SPW_TOP|rx_data|Selector85~0_combout ;
wire \A_SPW_TOP|rx_data|mem[7][5]~q ;
wire \A_SPW_TOP|rx_data|Selector157~0_combout ;
wire \A_SPW_TOP|rx_data|mem[15][5]~q ;
wire \A_SPW_TOP|rx_data|Selector49~0_combout ;
wire \A_SPW_TOP|rx_data|mem[3][5]~q ;
wire \A_SPW_TOP|rx_data|Mux3~15_combout ;
wire \A_SPW_TOP|rx_data|Mux3~19_combout ;
wire \A_SPW_TOP|rx_data|Selector58~0_combout ;
wire \A_SPW_TOP|rx_data|mem[4][5]~q ;
wire \A_SPW_TOP|rx_data|Selector346~0_combout ;
wire \A_SPW_TOP|rx_data|mem[36][5]~q ;
wire \A_SPW_TOP|rx_data|Selector130~0_combout ;
wire \A_SPW_TOP|rx_data|mem[12][5]~q ;
wire \A_SPW_TOP|rx_data|Selector418~0_combout ;
wire \A_SPW_TOP|rx_data|mem[44][5]~q ;
wire \A_SPW_TOP|rx_data|Mux3~1_combout ;
wire \A_SPW_TOP|rx_data|Selector274~0_combout ;
wire \A_SPW_TOP|rx_data|mem[28][5]~q ;
wire \A_SPW_TOP|rx_data|Selector202~0_combout ;
wire \A_SPW_TOP|rx_data|mem[20][5]~q ;
wire \A_SPW_TOP|rx_data|Selector562~0_combout ;
wire \A_SPW_TOP|rx_data|mem[60][5]~feeder_combout ;
wire \A_SPW_TOP|rx_data|mem[60][5]~q ;
wire \A_SPW_TOP|rx_data|Selector490~0_combout ;
wire \A_SPW_TOP|rx_data|mem[52][5]~q ;
wire \A_SPW_TOP|rx_data|Mux3~3_combout ;
wire \A_SPW_TOP|rx_data|Selector454~0_combout ;
wire \A_SPW_TOP|rx_data|mem[48][5]~q ;
wire \A_SPW_TOP|rx_data|Selector526~0_combout ;
wire \A_SPW_TOP|rx_data|mem[56][5]~q ;
wire \A_SPW_TOP|rx_data|Selector238~0_combout ;
wire \A_SPW_TOP|rx_data|mem[24][5]~q ;
wire \A_SPW_TOP|rx_data|Selector166~0_combout ;
wire \A_SPW_TOP|rx_data|mem[16][5]~q ;
wire \A_SPW_TOP|rx_data|Mux3~2_combout ;
wire \A_SPW_TOP|rx_data|Selector310~0_combout ;
wire \A_SPW_TOP|rx_data|mem[32][5]~q ;
wire \A_SPW_TOP|rx_data|Selector382~0_combout ;
wire \A_SPW_TOP|rx_data|mem[40][5]~q ;
wire \A_SPW_TOP|rx_data|Selector94~0_combout ;
wire \A_SPW_TOP|rx_data|mem[8][5]~q ;
wire \A_SPW_TOP|rx_data|Selector22~0_combout ;
wire \A_SPW_TOP|rx_data|mem[0][5]~feeder_combout ;
wire \A_SPW_TOP|rx_data|mem[0][5]~q ;
wire \A_SPW_TOP|rx_data|Mux3~0_combout ;
wire \A_SPW_TOP|rx_data|Mux3~4_combout ;
wire \A_SPW_TOP|rx_data|Selector436~0_combout ;
wire \A_SPW_TOP|rx_data|mem[46][5]~q ;
wire \A_SPW_TOP|rx_data|Selector76~0_combout ;
wire \A_SPW_TOP|rx_data|mem[6][5]~q ;
wire \A_SPW_TOP|rx_data|Selector148~0_combout ;
wire \A_SPW_TOP|rx_data|mem[14][5]~q ;
wire \A_SPW_TOP|rx_data|Selector364~0_combout ;
wire \A_SPW_TOP|rx_data|mem[38][5]~q ;
wire \A_SPW_TOP|rx_data|Mux3~11_combout ;
wire \A_SPW_TOP|rx_data|Selector184~0_combout ;
wire \A_SPW_TOP|rx_data|mem[18][5]~q ;
wire \A_SPW_TOP|rx_data|Selector256~0_combout ;
wire \A_SPW_TOP|rx_data|mem[26][5]~q ;
wire \A_SPW_TOP|rx_data|Selector472~0_combout ;
wire \A_SPW_TOP|rx_data|mem[50][5]~q ;
wire \A_SPW_TOP|rx_data|Selector544~0_combout ;
wire \A_SPW_TOP|rx_data|mem[58][5]~q ;
wire \A_SPW_TOP|rx_data|Mux3~12_combout ;
wire \A_SPW_TOP|rx_data|Selector220~0_combout ;
wire \A_SPW_TOP|rx_data|mem[22][5]~q ;
wire \A_SPW_TOP|rx_data|Selector292~0_combout ;
wire \A_SPW_TOP|rx_data|mem[30][5]~q ;
wire \A_SPW_TOP|rx_data|Selector508~0_combout ;
wire \A_SPW_TOP|rx_data|mem[54][5]~q ;
wire \A_SPW_TOP|rx_data|Selector580~0_combout ;
wire \A_SPW_TOP|rx_data|mem[62][5]~q ;
wire \A_SPW_TOP|rx_data|Mux3~13_combout ;
wire \A_SPW_TOP|rx_data|Selector40~0_combout ;
wire \A_SPW_TOP|rx_data|mem[2][5]~q ;
wire \A_SPW_TOP|rx_data|Selector328~0_combout ;
wire \A_SPW_TOP|rx_data|mem[34][5]~q ;
wire \A_SPW_TOP|rx_data|Selector400~0_combout ;
wire \A_SPW_TOP|rx_data|mem[42][5]~q ;
wire \A_SPW_TOP|rx_data|Selector112~0_combout ;
wire \A_SPW_TOP|rx_data|mem[10][5]~q ;
wire \A_SPW_TOP|rx_data|Mux3~10_combout ;
wire \A_SPW_TOP|rx_data|Mux3~14_combout ;
wire \A_SPW_TOP|rx_data|Selector319~0_combout ;
wire \A_SPW_TOP|rx_data|mem[33][5]~q ;
wire \A_SPW_TOP|rx_data|Selector31~0_combout ;
wire \A_SPW_TOP|rx_data|mem[1][5]~q ;
wire \A_SPW_TOP|rx_data|Selector391~0_combout ;
wire \A_SPW_TOP|rx_data|mem[41][5]~q ;
wire \A_SPW_TOP|rx_data|Mux3~5_combout ;
wire \A_SPW_TOP|rx_data|Selector283~0_combout ;
wire \A_SPW_TOP|rx_data|mem[29][5]~q ;
wire \A_SPW_TOP|rx_data|Selector571~0_combout ;
wire \A_SPW_TOP|rx_data|mem[61][5]~q ;
wire \A_SPW_TOP|rx_data|Selector499~0_combout ;
wire \A_SPW_TOP|rx_data|mem[53][5]~q ;
wire \A_SPW_TOP|rx_data|Selector211~0_combout ;
wire \A_SPW_TOP|rx_data|mem[21][5]~q ;
wire \A_SPW_TOP|rx_data|Mux3~8_combout ;
wire \A_SPW_TOP|rx_data|Selector67~0_combout ;
wire \A_SPW_TOP|rx_data|mem[5][5]~q ;
wire \A_SPW_TOP|rx_data|Selector139~0_combout ;
wire \A_SPW_TOP|rx_data|mem[13][5]~q ;
wire \A_SPW_TOP|rx_data|Selector355~0_combout ;
wire \A_SPW_TOP|rx_data|mem[37][5]~q ;
wire \A_SPW_TOP|rx_data|Selector427~0_combout ;
wire \A_SPW_TOP|rx_data|mem[45][5]~q ;
wire \A_SPW_TOP|rx_data|Mux3~6_combout ;
wire \A_SPW_TOP|rx_data|Selector175~0_combout ;
wire \A_SPW_TOP|rx_data|mem[17][5]~q ;
wire \A_SPW_TOP|rx_data|Selector247~0_combout ;
wire \A_SPW_TOP|rx_data|mem[25][5]~q ;
wire \A_SPW_TOP|rx_data|Selector463~0_combout ;
wire \A_SPW_TOP|rx_data|mem[49][5]~q ;
wire \A_SPW_TOP|rx_data|Selector535~0_combout ;
wire \A_SPW_TOP|rx_data|mem[57][5]~q ;
wire \A_SPW_TOP|rx_data|Mux3~7_combout ;
wire \A_SPW_TOP|rx_data|Mux3~9_combout ;
wire \A_SPW_TOP|rx_data|Mux3~20_combout ;
wire \A_SPW_TOP|rx_data|Selector103~0_combout ;
wire \A_SPW_TOP|rx_data|mem[9][5]~q ;
wire \A_SPW_TOP|rx_data|Mux12~1_combout ;
wire \A_SPW_TOP|rx_data|Mux12~3_combout ;
wire \A_SPW_TOP|rx_data|Mux12~2_combout ;
wire \A_SPW_TOP|rx_data|Mux12~0_combout ;
wire \A_SPW_TOP|rx_data|Mux12~4_combout ;
wire \A_SPW_TOP|rx_data|Mux12~17_combout ;
wire \A_SPW_TOP|rx_data|Mux12~18_combout ;
wire \A_SPW_TOP|rx_data|Mux12~16_combout ;
wire \A_SPW_TOP|rx_data|Mux12~15_combout ;
wire \A_SPW_TOP|rx_data|Mux12~19_combout ;
wire \A_SPW_TOP|rx_data|Mux12~11_combout ;
wire \A_SPW_TOP|rx_data|Mux12~10_combout ;
wire \A_SPW_TOP|rx_data|Mux12~12_combout ;
wire \A_SPW_TOP|rx_data|Mux12~13_combout ;
wire \A_SPW_TOP|rx_data|Mux12~14_combout ;
wire \A_SPW_TOP|rx_data|Mux12~8_combout ;
wire \A_SPW_TOP|rx_data|Mux12~6_combout ;
wire \A_SPW_TOP|rx_data|Mux12~5_combout ;
wire \A_SPW_TOP|rx_data|Mux12~7_combout ;
wire \A_SPW_TOP|rx_data|Mux12~9_combout ;
wire \A_SPW_TOP|rx_data|Mux12~20_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][5]~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~5_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][5]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~70_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|read~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[1]~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~13_combout ;
wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~14_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0]~feeder_combout ;
wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~15_combout ;
wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~16_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;
wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~18_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;
wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~17_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~12_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;
wire \u0|counter_tx_fifo|read_mux_out[5]~5_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][5]~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~5_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][5]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~72_combout ;
wire \m_x|bit_d_0~q ;
wire \m_x|bit_d_2~q ;
wire \m_x|bit_d_4~q ;
wire \m_x|bit_d_6~q ;
wire \m_x|bit_d_8~q ;
wire \m_x|bit_d_1~feeder_combout ;
wire \m_x|bit_d_1~q ;
wire \m_x|bit_d_3~feeder_combout ;
wire \m_x|bit_d_3~q ;
wire \m_x|bit_d_5~feeder_combout ;
wire \m_x|bit_d_5~q ;
wire \m_x|bit_d_7~feeder_combout ;
wire \m_x|bit_d_7~q ;
wire \m_x|bit_d_9~feeder_combout ;
wire \m_x|bit_d_9~q ;
wire \m_x|parity_rec_d~q ;
wire \m_x|always16~0_combout ;
wire \m_x|rx_got_time_code~0_combout ;
wire \m_x|last_is_data~0_combout ;
wire \m_x|last_is_data~q ;
wire \m_x|last_is_control~0_combout ;
wire \m_x|last_is_control~q ;
wire \m_x|rx_error_d~1_combout ;
wire \m_x|dta_timec[0]~feeder_combout ;
wire \m_x|dta_timec_p[0]~feeder_combout ;
wire \m_x|data~0_combout ;
wire \m_x|data~8_combout ;
wire \m_x|data[0]~feeder_combout ;
wire \m_x|data~7_combout ;
wire \m_x|always17~1_combout ;
wire \m_x|rx_error_d~0_combout ;
wire \m_x|data~1_combout ;
wire \m_x|dta_timec[4]~feeder_combout ;
wire \m_x|data~4_combout ;
wire \m_x|dta_timec_p[5]~feeder_combout ;
wire \m_x|data~3_combout ;
wire \m_x|dta_timec[3]~feeder_combout ;
wire \m_x|dta_timec_p[3]~feeder_combout ;
wire \m_x|data~5_combout ;
wire \m_x|dta_timec[2]~feeder_combout ;
wire \m_x|dta_timec_p[2]~feeder_combout ;
wire \m_x|data~6_combout ;
wire \m_x|dta_timec[6]~feeder_combout ;
wire \m_x|data~2_combout ;
wire \m_x|always17~0_combout ;
wire \m_x|rx_error_d~2_combout ;
wire \m_x|rx_error_d~feeder_combout ;
wire \m_x|rx_error_d~q ;
wire \m_x|parity_rec_c~q ;
wire \m_x|always17~2_combout ;
wire \m_x|rx_error_c~0_combout ;
wire \m_x|rx_error_c~1_combout ;
wire \m_x|rx_error_c~feeder_combout ;
wire \m_x|rx_error_c~q ;
wire \m_x|rx_error~combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][5]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~5_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][5]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~71_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~73_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~74_combout ;
wire \u0|mm_interconnect_0|router_001|Equal2~0_combout ;
wire \u0|mm_interconnect_0|router_001|Equal10~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_020|packet_in_progress~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_020|packet_in_progress~q ;
wire \u0|mm_interconnect_0|cmd_mux_020|update_grant~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[0]~0_combout ;
wire \u0|counter_tx_fifo|read_mux_out[4]~4_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][4]~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~4_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][4]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~64_combout ;
wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~12_combout ;
wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~14_combout ;
wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~16_combout ;
wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~15_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~13_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;
wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~17_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;
wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~18_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3]~feeder_combout ;
wire \u0|fsm_info|read_mux_out[4]~4_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][4]~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~4_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][4]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~63_combout ;
wire \u0|counter_rx_fifo|read_mux_out[4]~4_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][4]~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~4_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][4]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~65_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][4]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~4_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][4]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~218_combout ;
wire \m_x|always0~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][4]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~4_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][4]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~58_combout ;
wire \u0|mm_interconnect_0|rsp_demux|src1_valid~combout ;
wire \A_SPW_TOP|SPW|RX|timecode~5_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][4]~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~4_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][4]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~60_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~2_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~3_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ;
wire \u0|mm_interconnect_0|cmd_mux|src_payload~4_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;
wire \u0|led_pio_test|always0~0_combout ;
wire \u0|led_pio_test|data_out[4]~_Duplicate_1_q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][4]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~4_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][4]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~59_combout ;
wire \A_SPW_TOP|SPW|RX|rx_data_flag~4_combout ;
wire \A_SPW_TOP|rx_data|Selector230~0_combout ;
wire \A_SPW_TOP|rx_data|mem[23][4]~q ;
wire \A_SPW_TOP|rx_data|Selector509~0_combout ;
wire \A_SPW_TOP|rx_data|mem[54][4]~q ;
wire \A_SPW_TOP|rx_data|Selector221~0_combout ;
wire \A_SPW_TOP|rx_data|mem[22][4]~q ;
wire \A_SPW_TOP|rx_data|Selector518~0_combout ;
wire \A_SPW_TOP|rx_data|mem[55][4]~q ;
wire \A_SPW_TOP|rx_data|Mux4~17_combout ;
wire \A_SPW_TOP|rx_data|Selector581~0_combout ;
wire \A_SPW_TOP|rx_data|mem[62][4]~q ;
wire \A_SPW_TOP|rx_data|Selector302~0_combout ;
wire \A_SPW_TOP|rx_data|mem[31][4]~q ;
wire \A_SPW_TOP|rx_data|Selector293~0_combout ;
wire \A_SPW_TOP|rx_data|mem[30][4]~q ;
wire \A_SPW_TOP|rx_data|Selector590~0_combout ;
wire \A_SPW_TOP|rx_data|mem[63][4]~q ;
wire \A_SPW_TOP|rx_data|Mux4~18_combout ;
wire \A_SPW_TOP|rx_data|Selector212~0_combout ;
wire \A_SPW_TOP|rx_data|mem[21][4]~q ;
wire \A_SPW_TOP|rx_data|Selector500~0_combout ;
wire \A_SPW_TOP|rx_data|mem[53][4]~q ;
wire \A_SPW_TOP|rx_data|Selector203~0_combout ;
wire \A_SPW_TOP|rx_data|mem[20][4]~q ;
wire \A_SPW_TOP|rx_data|Selector491~0_combout ;
wire \A_SPW_TOP|rx_data|mem[52][4]~q ;
wire \A_SPW_TOP|rx_data|Mux4~15_combout ;
wire \A_SPW_TOP|rx_data|Selector275~0_combout ;
wire \A_SPW_TOP|rx_data|mem[28][4]~q ;
wire \A_SPW_TOP|rx_data|Selector563~0_combout ;
wire \A_SPW_TOP|rx_data|mem[60][4]~q ;
wire \A_SPW_TOP|rx_data|Selector284~0_combout ;
wire \A_SPW_TOP|rx_data|mem[29][4]~q ;
wire \A_SPW_TOP|rx_data|Mux4~16_combout ;
wire \A_SPW_TOP|rx_data|Mux4~19_combout ;
wire \A_SPW_TOP|rx_data|Selector455~0_combout ;
wire \A_SPW_TOP|rx_data|mem[48][4]~q ;
wire \A_SPW_TOP|rx_data|Selector482~0_combout ;
wire \A_SPW_TOP|rx_data|mem[51][4]~q ;
wire \A_SPW_TOP|rx_data|Selector464~0_combout ;
wire \A_SPW_TOP|rx_data|mem[49][4]~q ;
wire \A_SPW_TOP|rx_data|Selector473~0_combout ;
wire \A_SPW_TOP|rx_data|mem[50][4]~q ;
wire \A_SPW_TOP|rx_data|Mux4~7_combout ;
wire \A_SPW_TOP|rx_data|Selector545~0_combout ;
wire \A_SPW_TOP|rx_data|mem[58][4]~feeder_combout ;
wire \A_SPW_TOP|rx_data|mem[58][4]~q ;
wire \A_SPW_TOP|rx_data|Selector527~0_combout ;
wire \A_SPW_TOP|rx_data|mem[56][4]~q ;
wire \A_SPW_TOP|rx_data|Selector536~0_combout ;
wire \A_SPW_TOP|rx_data|mem[57][4]~q ;
wire \A_SPW_TOP|rx_data|Selector554~0_combout ;
wire \A_SPW_TOP|rx_data|mem[59][4]~q ;
wire \A_SPW_TOP|rx_data|Mux4~8_combout ;
wire \A_SPW_TOP|rx_data|Selector176~0_combout ;
wire \A_SPW_TOP|rx_data|mem[17][4]~q ;
wire \A_SPW_TOP|rx_data|Selector167~0_combout ;
wire \A_SPW_TOP|rx_data|mem[16][4]~q ;
wire \A_SPW_TOP|rx_data|Selector185~0_combout ;
wire \A_SPW_TOP|rx_data|mem[18][4]~q ;
wire \A_SPW_TOP|rx_data|Selector194~0_combout ;
wire \A_SPW_TOP|rx_data|mem[19][4]~q ;
wire \A_SPW_TOP|rx_data|Mux4~5_combout ;
wire \A_SPW_TOP|rx_data|Selector248~0_combout ;
wire \A_SPW_TOP|rx_data|mem[25][4]~q ;
wire \A_SPW_TOP|rx_data|Selector239~0_combout ;
wire \A_SPW_TOP|rx_data|mem[24][4]~q ;
wire \A_SPW_TOP|rx_data|Selector257~0_combout ;
wire \A_SPW_TOP|rx_data|mem[26][4]~q ;
wire \A_SPW_TOP|rx_data|Selector266~0_combout ;
wire \A_SPW_TOP|rx_data|mem[27][4]~q ;
wire \A_SPW_TOP|rx_data|Mux4~6_combout ;
wire \A_SPW_TOP|rx_data|Mux4~9_combout ;
wire \A_SPW_TOP|rx_data|Selector113~0_combout ;
wire \A_SPW_TOP|rx_data|mem[10][4]~q ;
wire \A_SPW_TOP|rx_data|Selector104~0_combout ;
wire \A_SPW_TOP|rx_data|mem[9][4]~q ;
wire \A_SPW_TOP|rx_data|Selector122~0_combout ;
wire \A_SPW_TOP|rx_data|mem[11][4]~q ;
wire \A_SPW_TOP|rx_data|Selector95~0_combout ;
wire \A_SPW_TOP|rx_data|mem[8][4]~q ;
wire \A_SPW_TOP|rx_data|Mux4~1_combout ;
wire \A_SPW_TOP|rx_data|Selector338~0_combout ;
wire \A_SPW_TOP|rx_data|mem[35][4]~q ;
wire \A_SPW_TOP|rx_data|Selector311~0_combout ;
wire \A_SPW_TOP|rx_data|mem[32][4]~q ;
wire \A_SPW_TOP|rx_data|Selector320~0_combout ;
wire \A_SPW_TOP|rx_data|mem[33][4]~q ;
wire \A_SPW_TOP|rx_data|Selector329~0_combout ;
wire \A_SPW_TOP|rx_data|mem[34][4]~q ;
wire \A_SPW_TOP|rx_data|Mux4~2_combout ;
wire \A_SPW_TOP|rx_data|Selector50~0_combout ;
wire \A_SPW_TOP|rx_data|mem[3][4]~q ;
wire \A_SPW_TOP|rx_data|Selector23~0_combout ;
wire \A_SPW_TOP|rx_data|mem[0][4]~q ;
wire \A_SPW_TOP|rx_data|Selector32~0_combout ;
wire \A_SPW_TOP|rx_data|mem[1][4]~q ;
wire \A_SPW_TOP|rx_data|Selector41~0_combout ;
wire \A_SPW_TOP|rx_data|mem[2][4]~q ;
wire \A_SPW_TOP|rx_data|Mux4~0_combout ;
wire \A_SPW_TOP|rx_data|Selector392~0_combout ;
wire \A_SPW_TOP|rx_data|mem[41][4]~q ;
wire \A_SPW_TOP|rx_data|Selector401~0_combout ;
wire \A_SPW_TOP|rx_data|mem[42][4]~q ;
wire \A_SPW_TOP|rx_data|Selector410~0_combout ;
wire \A_SPW_TOP|rx_data|mem[43][4]~q ;
wire \A_SPW_TOP|rx_data|Selector383~0_combout ;
wire \A_SPW_TOP|rx_data|mem[40][4]~q ;
wire \A_SPW_TOP|rx_data|Mux4~3_combout ;
wire \A_SPW_TOP|rx_data|Mux4~4_combout ;
wire \A_SPW_TOP|rx_data|Selector356~0_combout ;
wire \A_SPW_TOP|rx_data|mem[37][4]~q ;
wire \A_SPW_TOP|rx_data|Selector347~0_combout ;
wire \A_SPW_TOP|rx_data|mem[36][4]~q ;
wire \A_SPW_TOP|rx_data|Selector374~0_combout ;
wire \A_SPW_TOP|rx_data|mem[39][4]~q ;
wire \A_SPW_TOP|rx_data|Selector365~0_combout ;
wire \A_SPW_TOP|rx_data|mem[38][4]~q ;
wire \A_SPW_TOP|rx_data|Mux4~12_combout ;
wire \A_SPW_TOP|rx_data|Selector437~0_combout ;
wire \A_SPW_TOP|rx_data|mem[46][4]~q ;
wire \A_SPW_TOP|rx_data|Selector419~0_combout ;
wire \A_SPW_TOP|rx_data|mem[44][4]~q ;
wire \A_SPW_TOP|rx_data|Selector428~0_combout ;
wire \A_SPW_TOP|rx_data|mem[45][4]~q ;
wire \A_SPW_TOP|rx_data|Selector446~0_combout ;
wire \A_SPW_TOP|rx_data|mem[47][4]~q ;
wire \A_SPW_TOP|rx_data|Mux4~13_combout ;
wire \A_SPW_TOP|rx_data|Selector140~0_combout ;
wire \A_SPW_TOP|rx_data|mem[13][4]~q ;
wire \A_SPW_TOP|rx_data|Selector149~0_combout ;
wire \A_SPW_TOP|rx_data|mem[14][4]~q ;
wire \A_SPW_TOP|rx_data|Selector158~0_combout ;
wire \A_SPW_TOP|rx_data|mem[15][4]~q ;
wire \A_SPW_TOP|rx_data|Selector131~0_combout ;
wire \A_SPW_TOP|rx_data|mem[12][4]~q ;
wire \A_SPW_TOP|rx_data|Mux4~11_combout ;
wire \A_SPW_TOP|rx_data|Selector86~0_combout ;
wire \A_SPW_TOP|rx_data|mem[7][4]~q ;
wire \A_SPW_TOP|rx_data|Selector77~0_combout ;
wire \A_SPW_TOP|rx_data|mem[6][4]~q ;
wire \A_SPW_TOP|rx_data|Selector59~0_combout ;
wire \A_SPW_TOP|rx_data|mem[4][4]~q ;
wire \A_SPW_TOP|rx_data|Selector68~0_combout ;
wire \A_SPW_TOP|rx_data|mem[5][4]~q ;
wire \A_SPW_TOP|rx_data|Mux4~10_combout ;
wire \A_SPW_TOP|rx_data|Mux4~14_combout ;
wire \A_SPW_TOP|rx_data|Mux4~20_combout ;
wire \A_SPW_TOP|rx_data|Selector572~0_combout ;
wire \A_SPW_TOP|rx_data|mem[61][4]~q ;
wire \A_SPW_TOP|rx_data|Mux13~17_combout ;
wire \A_SPW_TOP|rx_data|Mux13~15_combout ;
wire \A_SPW_TOP|rx_data|Mux13~18_combout ;
wire \A_SPW_TOP|rx_data|Mux13~16_combout ;
wire \A_SPW_TOP|rx_data|Mux13~19_combout ;
wire \A_SPW_TOP|rx_data|Mux13~13_combout ;
wire \A_SPW_TOP|rx_data|Mux13~11_combout ;
wire \A_SPW_TOP|rx_data|Mux13~12_combout ;
wire \A_SPW_TOP|rx_data|Mux13~10_combout ;
wire \A_SPW_TOP|rx_data|Mux13~14_combout ;
wire \A_SPW_TOP|rx_data|Mux13~3_combout ;
wire \A_SPW_TOP|rx_data|Mux13~1_combout ;
wire \A_SPW_TOP|rx_data|Mux13~2_combout ;
wire \A_SPW_TOP|rx_data|Mux13~0_combout ;
wire \A_SPW_TOP|rx_data|Mux13~4_combout ;
wire \A_SPW_TOP|rx_data|Mux13~6_combout ;
wire \A_SPW_TOP|rx_data|Mux13~7_combout ;
wire \A_SPW_TOP|rx_data|Mux13~8_combout ;
wire \A_SPW_TOP|rx_data|Mux13~5_combout ;
wire \A_SPW_TOP|rx_data|Mux13~9_combout ;
wire \A_SPW_TOP|rx_data|Mux13~20_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][4]~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~4_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][4]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~61_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~62_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][4]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~4_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][4]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~214_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout ;
wire \u0|mm_interconnect_0|cmd_demux|src14_valid~0_combout ;
wire \u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_014|arb|grant[0]~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68]~feeder_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~4_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[0]~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][3]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~3_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][3]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~50_combout ;
wire \A_SPW_TOP|SPW|RX|rx_data_flag~3_combout ;
wire \A_SPW_TOP|rx_data|Selector429~0_combout ;
wire \A_SPW_TOP|rx_data|mem[45][3]~q ;
wire \A_SPW_TOP|rx_data|Selector591~0_combout ;
wire \A_SPW_TOP|rx_data|mem[63][3]~q ;
wire \A_SPW_TOP|rx_data|Selector447~0_combout ;
wire \A_SPW_TOP|rx_data|mem[47][3]~q ;
wire \A_SPW_TOP|rx_data|Selector573~0_combout ;
wire \A_SPW_TOP|rx_data|mem[61][3]~q ;
wire \A_SPW_TOP|rx_data|Mux5~18_combout ;
wire \A_SPW_TOP|rx_data|Selector582~0_combout ;
wire \A_SPW_TOP|rx_data|mem[62][3]~q ;
wire \A_SPW_TOP|rx_data|Selector564~0_combout ;
wire \A_SPW_TOP|rx_data|mem[60][3]~q ;
wire \A_SPW_TOP|rx_data|Selector420~0_combout ;
wire \A_SPW_TOP|rx_data|mem[44][3]~q ;
wire \A_SPW_TOP|rx_data|Mux5~17_combout ;
wire \A_SPW_TOP|rx_data|Selector411~0_combout ;
wire \A_SPW_TOP|rx_data|mem[43][3]~q ;
wire \A_SPW_TOP|rx_data|Selector393~0_combout ;
wire \A_SPW_TOP|rx_data|mem[41][3]~q ;
wire \A_SPW_TOP|rx_data|Selector555~0_combout ;
wire \A_SPW_TOP|rx_data|mem[59][3]~q ;
wire \A_SPW_TOP|rx_data|Selector537~0_combout ;
wire \A_SPW_TOP|rx_data|mem[57][3]~q ;
wire \A_SPW_TOP|rx_data|Mux5~16_combout ;
wire \A_SPW_TOP|rx_data|Selector384~0_combout ;
wire \A_SPW_TOP|rx_data|mem[40][3]~q ;
wire \A_SPW_TOP|rx_data|Selector546~0_combout ;
wire \A_SPW_TOP|rx_data|mem[58][3]~q ;
wire \A_SPW_TOP|rx_data|Selector528~0_combout ;
wire \A_SPW_TOP|rx_data|mem[56][3]~q ;
wire \A_SPW_TOP|rx_data|Selector402~0_combout ;
wire \A_SPW_TOP|rx_data|mem[42][3]~q ;
wire \A_SPW_TOP|rx_data|Mux5~15_combout ;
wire \A_SPW_TOP|rx_data|Mux5~19_combout ;
wire \A_SPW_TOP|rx_data|Selector303~0_combout ;
wire \A_SPW_TOP|rx_data|mem[31][3]~q ;
wire \A_SPW_TOP|rx_data|Selector123~0_combout ;
wire \A_SPW_TOP|rx_data|mem[11][3]~q ;
wire \A_SPW_TOP|rx_data|Selector159~0_combout ;
wire \A_SPW_TOP|rx_data|mem[15][3]~q ;
wire \A_SPW_TOP|rx_data|Selector267~0_combout ;
wire \A_SPW_TOP|rx_data|mem[27][3]~q ;
wire \A_SPW_TOP|rx_data|Mux5~8_combout ;
wire \A_SPW_TOP|rx_data|Selector141~0_combout ;
wire \A_SPW_TOP|rx_data|mem[13][3]~q ;
wire \A_SPW_TOP|rx_data|Selector105~0_combout ;
wire \A_SPW_TOP|rx_data|mem[9][3]~q ;
wire \A_SPW_TOP|rx_data|Selector285~0_combout ;
wire \A_SPW_TOP|rx_data|mem[29][3]~q ;
wire \A_SPW_TOP|rx_data|Selector249~0_combout ;
wire \A_SPW_TOP|rx_data|mem[25][3]~q ;
wire \A_SPW_TOP|rx_data|Mux5~6_combout ;
wire \A_SPW_TOP|rx_data|Selector258~0_combout ;
wire \A_SPW_TOP|rx_data|mem[26][3]~q ;
wire \A_SPW_TOP|rx_data|Selector114~0_combout ;
wire \A_SPW_TOP|rx_data|mem[10][3]~q ;
wire \A_SPW_TOP|rx_data|Selector294~0_combout ;
wire \A_SPW_TOP|rx_data|mem[30][3]~q ;
wire \A_SPW_TOP|rx_data|Selector150~0_combout ;
wire \A_SPW_TOP|rx_data|mem[14][3]~q ;
wire \A_SPW_TOP|rx_data|Mux5~7_combout ;
wire \A_SPW_TOP|rx_data|Selector276~0_combout ;
wire \A_SPW_TOP|rx_data|mem[28][3]~q ;
wire \A_SPW_TOP|rx_data|Selector240~0_combout ;
wire \A_SPW_TOP|rx_data|mem[24][3]~q ;
wire \A_SPW_TOP|rx_data|Selector96~0_combout ;
wire \A_SPW_TOP|rx_data|mem[8][3]~q ;
wire \A_SPW_TOP|rx_data|Selector132~0_combout ;
wire \A_SPW_TOP|rx_data|mem[12][3]~q ;
wire \A_SPW_TOP|rx_data|Mux5~5_combout ;
wire \A_SPW_TOP|rx_data|Mux5~9_combout ;
wire \A_SPW_TOP|rx_data|Selector69~0_combout ;
wire \A_SPW_TOP|rx_data|mem[5][3]~q ;
wire \A_SPW_TOP|rx_data|Selector177~0_combout ;
wire \A_SPW_TOP|rx_data|mem[17][3]~q ;
wire \A_SPW_TOP|rx_data|Selector213~0_combout ;
wire \A_SPW_TOP|rx_data|mem[21][3]~q ;
wire \A_SPW_TOP|rx_data|Selector33~0_combout ;
wire \A_SPW_TOP|rx_data|mem[1][3]~feeder_combout ;
wire \A_SPW_TOP|rx_data|mem[1][3]~q ;
wire \A_SPW_TOP|rx_data|Mux5~1_combout ;
wire \A_SPW_TOP|rx_data|Selector78~0_combout ;
wire \A_SPW_TOP|rx_data|mem[6][3]~feeder_combout ;
wire \A_SPW_TOP|rx_data|mem[6][3]~q ;
wire \A_SPW_TOP|rx_data|Selector186~0_combout ;
wire \A_SPW_TOP|rx_data|mem[18][3]~q ;
wire \A_SPW_TOP|rx_data|Selector222~0_combout ;
wire \A_SPW_TOP|rx_data|mem[22][3]~q ;
wire \A_SPW_TOP|rx_data|Selector42~0_combout ;
wire \A_SPW_TOP|rx_data|mem[2][3]~q ;
wire \A_SPW_TOP|rx_data|Mux5~2_combout ;
wire \A_SPW_TOP|rx_data|Selector204~0_combout ;
wire \A_SPW_TOP|rx_data|mem[20][3]~q ;
wire \A_SPW_TOP|rx_data|Selector60~0_combout ;
wire \A_SPW_TOP|rx_data|mem[4][3]~q ;
wire \A_SPW_TOP|rx_data|Selector168~0_combout ;
wire \A_SPW_TOP|rx_data|mem[16][3]~feeder_combout ;
wire \A_SPW_TOP|rx_data|mem[16][3]~q ;
wire \A_SPW_TOP|rx_data|Selector24~0_combout ;
wire \A_SPW_TOP|rx_data|mem[0][3]~q ;
wire \A_SPW_TOP|rx_data|Mux5~0_combout ;
wire \A_SPW_TOP|rx_data|Selector87~0_combout ;
wire \A_SPW_TOP|rx_data|mem[7][3]~q ;
wire \A_SPW_TOP|rx_data|Selector195~0_combout ;
wire \A_SPW_TOP|rx_data|mem[19][3]~q ;
wire \A_SPW_TOP|rx_data|Selector231~0_combout ;
wire \A_SPW_TOP|rx_data|mem[23][3]~q ;
wire \A_SPW_TOP|rx_data|Selector51~0_combout ;
wire \A_SPW_TOP|rx_data|mem[3][3]~q ;
wire \A_SPW_TOP|rx_data|Mux5~3_combout ;
wire \A_SPW_TOP|rx_data|Mux5~4_combout ;
wire \A_SPW_TOP|rx_data|Selector321~0_combout ;
wire \A_SPW_TOP|rx_data|mem[33][3]~q ;
wire \A_SPW_TOP|rx_data|Selector357~0_combout ;
wire \A_SPW_TOP|rx_data|mem[37][3]~q ;
wire \A_SPW_TOP|rx_data|Selector501~0_combout ;
wire \A_SPW_TOP|rx_data|mem[53][3]~q ;
wire \A_SPW_TOP|rx_data|Selector465~0_combout ;
wire \A_SPW_TOP|rx_data|mem[49][3]~q ;
wire \A_SPW_TOP|rx_data|Mux5~11_combout ;
wire \A_SPW_TOP|rx_data|Selector474~0_combout ;
wire \A_SPW_TOP|rx_data|mem[50][3]~q ;
wire \A_SPW_TOP|rx_data|Selector366~0_combout ;
wire \A_SPW_TOP|rx_data|mem[38][3]~q ;
wire \A_SPW_TOP|rx_data|Selector330~0_combout ;
wire \A_SPW_TOP|rx_data|mem[34][3]~q ;
wire \A_SPW_TOP|rx_data|Selector510~0_combout ;
wire \A_SPW_TOP|rx_data|mem[54][3]~q ;
wire \A_SPW_TOP|rx_data|Mux5~12_combout ;
wire \A_SPW_TOP|rx_data|Selector492~0_combout ;
wire \A_SPW_TOP|rx_data|mem[52][3]~q ;
wire \A_SPW_TOP|rx_data|Selector312~0_combout ;
wire \A_SPW_TOP|rx_data|mem[32][3]~q ;
wire \A_SPW_TOP|rx_data|Selector456~0_combout ;
wire \A_SPW_TOP|rx_data|mem[48][3]~feeder_combout ;
wire \A_SPW_TOP|rx_data|mem[48][3]~q ;
wire \A_SPW_TOP|rx_data|Selector348~0_combout ;
wire \A_SPW_TOP|rx_data|mem[36][3]~q ;
wire \A_SPW_TOP|rx_data|Mux5~10_combout ;
wire \A_SPW_TOP|rx_data|Selector519~0_combout ;
wire \A_SPW_TOP|rx_data|mem[55][3]~q ;
wire \A_SPW_TOP|rx_data|Selector339~0_combout ;
wire \A_SPW_TOP|rx_data|mem[35][3]~q ;
wire \A_SPW_TOP|rx_data|Selector483~0_combout ;
wire \A_SPW_TOP|rx_data|mem[51][3]~q ;
wire \A_SPW_TOP|rx_data|Selector375~0_combout ;
wire \A_SPW_TOP|rx_data|mem[39][3]~q ;
wire \A_SPW_TOP|rx_data|Mux5~13_combout ;
wire \A_SPW_TOP|rx_data|Mux5~14_combout ;
wire \A_SPW_TOP|rx_data|Mux5~20_combout ;
wire \A_SPW_TOP|rx_data|Selector438~0_combout ;
wire \A_SPW_TOP|rx_data|mem[46][3]~q ;
wire \A_SPW_TOP|rx_data|Mux14~13_combout ;
wire \A_SPW_TOP|rx_data|Mux14~12_combout ;
wire \A_SPW_TOP|rx_data|Mux14~11_combout ;
wire \A_SPW_TOP|rx_data|Mux14~10_combout ;
wire \A_SPW_TOP|rx_data|Mux14~14_combout ;
wire \A_SPW_TOP|rx_data|Mux14~1_combout ;
wire \A_SPW_TOP|rx_data|Mux14~0_combout ;
wire \A_SPW_TOP|rx_data|Mux14~2_combout ;
wire \A_SPW_TOP|rx_data|Mux14~3_combout ;
wire \A_SPW_TOP|rx_data|Mux14~4_combout ;
wire \A_SPW_TOP|rx_data|Mux14~17_combout ;
wire \A_SPW_TOP|rx_data|Mux14~16_combout ;
wire \A_SPW_TOP|rx_data|Mux14~15_combout ;
wire \A_SPW_TOP|rx_data|Mux14~18_combout ;
wire \A_SPW_TOP|rx_data|Mux14~19_combout ;
wire \A_SPW_TOP|rx_data|Mux14~8_combout ;
wire \A_SPW_TOP|rx_data|Mux14~5_combout ;
wire \A_SPW_TOP|rx_data|Mux14~6_combout ;
wire \A_SPW_TOP|rx_data|Mux14~7_combout ;
wire \A_SPW_TOP|rx_data|Mux14~9_combout ;
wire \A_SPW_TOP|rx_data|Mux14~20_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][3]~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~3_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][3]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~53_combout ;
wire \u0|mm_interconnect_0|cmd_mux|src_payload~3_combout ;
wire \u0|led_pio_test|data_out[3]~_Duplicate_1_q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][3]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~3_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][3]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~51_combout ;
wire \A_SPW_TOP|SPW|RX|timecode~4_combout ;
wire \A_SPW_TOP|SPW|RX|timecode[3]~feeder_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][3]~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~3_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][3]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~52_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~54_combout ;
wire \m_x|always10~0_combout ;
wire \m_x|always10~1_combout ;
wire \m_x|rx_got_null~0_combout ;
wire \m_x|rx_got_null~q ;
wire \u0|fsm_info|read_mux_out[3]~3_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][3]~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~3_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][3]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~55_combout ;
wire \u0|counter_tx_fifo|read_mux_out[3]~3_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][3]~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~3_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][3]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~56_combout ;
wire \u0|counter_rx_fifo|read_mux_out[3]~3_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][3]~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~3_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][3]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~57_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][3]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~3_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][3]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~226_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][3]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~3_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][3]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~222_combout ;
wire \u0|mm_interconnect_0|router_001|Equal1~1_combout ;
wire \u0|mm_interconnect_0|router_001|Equal4~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_017|last_cycle~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_017|packet_in_progress~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_017|packet_in_progress~q ;
wire \u0|mm_interconnect_0|cmd_mux_017|update_grant~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[0]~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][2]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][2]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~47_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][69]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~1_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][69]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][68]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~2_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][68]~q ;
wire \u0|mm_interconnect_0|rsp_demux_018|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][129]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][129]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|read~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used[1]~1_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used[0]~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_018|src_payload~2_combout ;
wire \u0|clock_sel|data_out[2]~feeder_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent|m0_write~combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;
wire \u0|clock_sel|always0~0_combout ;
wire \u0|clock_sel|readdata[2]~2_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[1][2]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem~2_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[0][2]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~48_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~49_combout ;
wire \m_x|rx_got_nchar~0_combout ;
wire \m_x|rx_got_nchar~q ;
wire \u0|counter_rx_fifo|read_mux_out[2]~2_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][2]~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~2_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][2]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~46_combout ;
wire \u0|counter_tx_fifo|read_mux_out[2]~2_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][2]~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~2_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][2]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~45_combout ;
wire \u0|fsm_info|read_mux_out[2]~2_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][2]~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~2_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][2]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~44_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][2]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~2_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][2]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~234_combout ;
wire \A_SPW_TOP|SPW|RX|timecode~3_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[2]~feeder_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][2]~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~2_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][2]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~41_combout ;
wire \A_SPW_TOP|SPW|RX|rx_data_flag~2_combout ;
wire \A_SPW_TOP|rx_data|Selector250~0_combout ;
wire \A_SPW_TOP|rx_data|mem[25][2]~q ;
wire \A_SPW_TOP|rx_data|Selector178~0_combout ;
wire \A_SPW_TOP|rx_data|mem[17][2]~q ;
wire \A_SPW_TOP|rx_data|Selector538~0_combout ;
wire \A_SPW_TOP|rx_data|mem[57][2]~q ;
wire \A_SPW_TOP|rx_data|Selector466~0_combout ;
wire \A_SPW_TOP|rx_data|mem[49][2]~q ;
wire \A_SPW_TOP|rx_data|Mux6~7_combout ;
wire \A_SPW_TOP|rx_data|Selector574~0_combout ;
wire \A_SPW_TOP|rx_data|mem[61][2]~q ;
wire \A_SPW_TOP|rx_data|Selector502~0_combout ;
wire \A_SPW_TOP|rx_data|mem[53][2]~q ;
wire \A_SPW_TOP|rx_data|Selector286~0_combout ;
wire \A_SPW_TOP|rx_data|mem[29][2]~q ;
wire \A_SPW_TOP|rx_data|Selector214~0_combout ;
wire \A_SPW_TOP|rx_data|mem[21][2]~feeder_combout ;
wire \A_SPW_TOP|rx_data|mem[21][2]~q ;
wire \A_SPW_TOP|rx_data|Mux6~8_combout ;
wire \A_SPW_TOP|rx_data|Selector358~0_combout ;
wire \A_SPW_TOP|rx_data|mem[37][2]~q ;
wire \A_SPW_TOP|rx_data|Selector70~0_combout ;
wire \A_SPW_TOP|rx_data|mem[5][2]~q ;
wire \A_SPW_TOP|rx_data|Selector142~0_combout ;
wire \A_SPW_TOP|rx_data|mem[13][2]~q ;
wire \A_SPW_TOP|rx_data|Selector430~0_combout ;
wire \A_SPW_TOP|rx_data|mem[45][2]~q ;
wire \A_SPW_TOP|rx_data|Mux6~6_combout ;
wire \A_SPW_TOP|rx_data|Selector34~0_combout ;
wire \A_SPW_TOP|rx_data|mem[1][2]~q ;
wire \A_SPW_TOP|rx_data|Selector394~0_combout ;
wire \A_SPW_TOP|rx_data|mem[41][2]~q ;
wire \A_SPW_TOP|rx_data|Selector106~0_combout ;
wire \A_SPW_TOP|rx_data|mem[9][2]~q ;
wire \A_SPW_TOP|rx_data|Selector322~0_combout ;
wire \A_SPW_TOP|rx_data|mem[33][2]~q ;
wire \A_SPW_TOP|rx_data|Mux6~5_combout ;
wire \A_SPW_TOP|rx_data|Mux6~9_combout ;
wire \A_SPW_TOP|rx_data|Selector493~0_combout ;
wire \A_SPW_TOP|rx_data|mem[52][2]~q ;
wire \A_SPW_TOP|rx_data|Selector277~0_combout ;
wire \A_SPW_TOP|rx_data|mem[28][2]~q ;
wire \A_SPW_TOP|rx_data|Selector205~0_combout ;
wire \A_SPW_TOP|rx_data|mem[20][2]~q ;
wire \A_SPW_TOP|rx_data|Selector565~0_combout ;
wire \A_SPW_TOP|rx_data|mem[60][2]~q ;
wire \A_SPW_TOP|rx_data|Mux6~3_combout ;
wire \A_SPW_TOP|rx_data|Selector61~0_combout ;
wire \A_SPW_TOP|rx_data|mem[4][2]~q ;
wire \A_SPW_TOP|rx_data|Selector421~0_combout ;
wire \A_SPW_TOP|rx_data|mem[44][2]~q ;
wire \A_SPW_TOP|rx_data|Selector133~0_combout ;
wire \A_SPW_TOP|rx_data|mem[12][2]~q ;
wire \A_SPW_TOP|rx_data|Selector349~0_combout ;
wire \A_SPW_TOP|rx_data|mem[36][2]~q ;
wire \A_SPW_TOP|rx_data|Mux6~1_combout ;
wire \A_SPW_TOP|rx_data|Selector97~0_combout ;
wire \A_SPW_TOP|rx_data|mem[8][2]~q ;
wire \A_SPW_TOP|rx_data|Selector313~0_combout ;
wire \A_SPW_TOP|rx_data|mem[32][2]~q ;
wire \A_SPW_TOP|rx_data|Selector385~0_combout ;
wire \A_SPW_TOP|rx_data|mem[40][2]~q ;
wire \A_SPW_TOP|rx_data|Selector25~0_combout ;
wire \A_SPW_TOP|rx_data|mem[0][2]~q ;
wire \A_SPW_TOP|rx_data|Mux6~0_combout ;
wire \A_SPW_TOP|rx_data|Selector457~0_combout ;
wire \A_SPW_TOP|rx_data|mem[48][2]~q ;
wire \A_SPW_TOP|rx_data|Selector241~0_combout ;
wire \A_SPW_TOP|rx_data|mem[24][2]~q ;
wire \A_SPW_TOP|rx_data|Selector529~0_combout ;
wire \A_SPW_TOP|rx_data|mem[56][2]~q ;
wire \A_SPW_TOP|rx_data|Selector169~0_combout ;
wire \A_SPW_TOP|rx_data|mem[16][2]~q ;
wire \A_SPW_TOP|rx_data|Mux6~2_combout ;
wire \A_SPW_TOP|rx_data|Mux6~4_combout ;
wire \A_SPW_TOP|rx_data|Selector187~0_combout ;
wire \A_SPW_TOP|rx_data|mem[18][2]~q ;
wire \A_SPW_TOP|rx_data|Selector475~0_combout ;
wire \A_SPW_TOP|rx_data|mem[50][2]~q ;
wire \A_SPW_TOP|rx_data|Selector547~0_combout ;
wire \A_SPW_TOP|rx_data|mem[58][2]~q ;
wire \A_SPW_TOP|rx_data|Selector259~0_combout ;
wire \A_SPW_TOP|rx_data|mem[26][2]~q ;
wire \A_SPW_TOP|rx_data|Mux6~12_combout ;
wire \A_SPW_TOP|rx_data|Selector511~0_combout ;
wire \A_SPW_TOP|rx_data|mem[54][2]~q ;
wire \A_SPW_TOP|rx_data|Selector223~0_combout ;
wire \A_SPW_TOP|rx_data|mem[22][2]~q ;
wire \A_SPW_TOP|rx_data|Selector295~0_combout ;
wire \A_SPW_TOP|rx_data|mem[30][2]~feeder_combout ;
wire \A_SPW_TOP|rx_data|mem[30][2]~q ;
wire \A_SPW_TOP|rx_data|Selector583~0_combout ;
wire \A_SPW_TOP|rx_data|mem[62][2]~q ;
wire \A_SPW_TOP|rx_data|Mux6~13_combout ;
wire \A_SPW_TOP|rx_data|Selector79~0_combout ;
wire \A_SPW_TOP|rx_data|mem[6][2]~q ;
wire \A_SPW_TOP|rx_data|Selector439~0_combout ;
wire \A_SPW_TOP|rx_data|mem[46][2]~q ;
wire \A_SPW_TOP|rx_data|Selector367~0_combout ;
wire \A_SPW_TOP|rx_data|mem[38][2]~q ;
wire \A_SPW_TOP|rx_data|Selector151~0_combout ;
wire \A_SPW_TOP|rx_data|mem[14][2]~q ;
wire \A_SPW_TOP|rx_data|Mux6~11_combout ;
wire \A_SPW_TOP|rx_data|Selector115~0_combout ;
wire \A_SPW_TOP|rx_data|mem[10][2]~q ;
wire \A_SPW_TOP|rx_data|Selector331~0_combout ;
wire \A_SPW_TOP|rx_data|mem[34][2]~q ;
wire \A_SPW_TOP|rx_data|Selector403~0_combout ;
wire \A_SPW_TOP|rx_data|mem[42][2]~q ;
wire \A_SPW_TOP|rx_data|Selector43~0_combout ;
wire \A_SPW_TOP|rx_data|mem[2][2]~q ;
wire \A_SPW_TOP|rx_data|Mux6~10_combout ;
wire \A_SPW_TOP|rx_data|Mux6~14_combout ;
wire \A_SPW_TOP|rx_data|Selector52~0_combout ;
wire \A_SPW_TOP|rx_data|mem[3][2]~q ;
wire \A_SPW_TOP|rx_data|Selector160~0_combout ;
wire \A_SPW_TOP|rx_data|mem[15][2]~q ;
wire \A_SPW_TOP|rx_data|Selector124~0_combout ;
wire \A_SPW_TOP|rx_data|mem[11][2]~q ;
wire \A_SPW_TOP|rx_data|Selector88~0_combout ;
wire \A_SPW_TOP|rx_data|mem[7][2]~q ;
wire \A_SPW_TOP|rx_data|Mux6~15_combout ;
wire \A_SPW_TOP|rx_data|Selector304~0_combout ;
wire \A_SPW_TOP|rx_data|mem[31][2]~q ;
wire \A_SPW_TOP|rx_data|Selector232~0_combout ;
wire \A_SPW_TOP|rx_data|mem[23][2]~q ;
wire \A_SPW_TOP|rx_data|Selector268~0_combout ;
wire \A_SPW_TOP|rx_data|mem[27][2]~q ;
wire \A_SPW_TOP|rx_data|Mux6~17_combout ;
wire \A_SPW_TOP|rx_data|Selector520~0_combout ;
wire \A_SPW_TOP|rx_data|mem[55][2]~q ;
wire \A_SPW_TOP|rx_data|Selector484~0_combout ;
wire \A_SPW_TOP|rx_data|mem[51][2]~q ;
wire \A_SPW_TOP|rx_data|Selector592~0_combout ;
wire \A_SPW_TOP|rx_data|mem[63][2]~q ;
wire \A_SPW_TOP|rx_data|Selector556~0_combout ;
wire \A_SPW_TOP|rx_data|mem[59][2]~q ;
wire \A_SPW_TOP|rx_data|Mux6~18_combout ;
wire \A_SPW_TOP|rx_data|Selector340~0_combout ;
wire \A_SPW_TOP|rx_data|mem[35][2]~q ;
wire \A_SPW_TOP|rx_data|Selector412~0_combout ;
wire \A_SPW_TOP|rx_data|mem[43][2]~q ;
wire \A_SPW_TOP|rx_data|Selector448~0_combout ;
wire \A_SPW_TOP|rx_data|mem[47][2]~q ;
wire \A_SPW_TOP|rx_data|Selector376~0_combout ;
wire \A_SPW_TOP|rx_data|mem[39][2]~q ;
wire \A_SPW_TOP|rx_data|Mux6~16_combout ;
wire \A_SPW_TOP|rx_data|Mux6~19_combout ;
wire \A_SPW_TOP|rx_data|Mux6~20_combout ;
wire \A_SPW_TOP|rx_data|Selector196~0_combout ;
wire \A_SPW_TOP|rx_data|mem[19][2]~q ;
wire \A_SPW_TOP|rx_data|Mux15~11_combout ;
wire \A_SPW_TOP|rx_data|Mux15~10_combout ;
wire \A_SPW_TOP|rx_data|Mux15~13_combout ;
wire \A_SPW_TOP|rx_data|Mux15~12_combout ;
wire \A_SPW_TOP|rx_data|Mux15~14_combout ;
wire \A_SPW_TOP|rx_data|Mux15~6_combout ;
wire \A_SPW_TOP|rx_data|Mux15~5_combout ;
wire \A_SPW_TOP|rx_data|Mux15~7_combout ;
wire \A_SPW_TOP|rx_data|Mux15~8_combout ;
wire \A_SPW_TOP|rx_data|Mux15~9_combout ;
wire \A_SPW_TOP|rx_data|Mux15~16_combout ;
wire \A_SPW_TOP|rx_data|Mux15~18_combout ;
wire \A_SPW_TOP|rx_data|Mux15~15_combout ;
wire \A_SPW_TOP|rx_data|Mux15~17_combout ;
wire \A_SPW_TOP|rx_data|Mux15~19_combout ;
wire \A_SPW_TOP|rx_data|Mux15~1_combout ;
wire \A_SPW_TOP|rx_data|Mux15~3_combout ;
wire \A_SPW_TOP|rx_data|Mux15~2_combout ;
wire \A_SPW_TOP|rx_data|Mux15~0_combout ;
wire \A_SPW_TOP|rx_data|Mux15~4_combout ;
wire \A_SPW_TOP|rx_data|Mux15~20_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][2]~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~2_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][2]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~42_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][2]~q ;
wire \u0|mm_interconnect_0|cmd_mux|src_payload~2_combout ;
wire \u0|led_pio_test|data_out[2]~_Duplicate_1feeder_combout ;
wire \u0|led_pio_test|data_out[2]~_Duplicate_1_q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~2_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][2]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~40_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~43_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][2]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~2_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][2]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~230_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout ;
wire \u0|mm_interconnect_0|router|Equal15~0_combout ;
wire \u0|mm_interconnect_0|cmd_demux|src9_valid~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_009|arb|grant[0]~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_009|src_payload~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;
wire \u0|link_disable|always0~0_combout ;
wire \u0|link_disable|data_out~q ;
wire \u0|mm_interconnect_0|cmd_mux_007|src_payload~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;
wire \u0|link_start|always0~0_combout ;
wire \u0|link_start|data_out~q ;
wire \u0|mm_interconnect_0|cmd_mux_008|src_payload~0_combout ;
wire \u0|auto_start|data_out~feeder_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent|m0_write~combout ;
wire \u0|auto_start|always0~0_combout ;
wire \u0|auto_start|data_out~q ;
wire \A_SPW_TOP|SPW|FSM|state_fsm~26_combout ;
wire \A_SPW_TOP|SPW|FSM|state_fsm~20_combout ;
wire \A_SPW_TOP|SPW|FSM|state_fsm~16_combout ;
wire \A_SPW_TOP|SPW|FSM|state_fsm.ready~q ;
wire \A_SPW_TOP|SPW|FSM|state_fsm~27_combout ;
wire \A_SPW_TOP|SPW|FSM|state_fsm~28_combout ;
wire \A_SPW_TOP|SPW|FSM|state_fsm~17_combout ;
wire \A_SPW_TOP|SPW|FSM|state_fsm.started~q ;
wire \A_SPW_TOP|SPW|FSM|after128us~0_combout ;
wire \A_SPW_TOP|SPW|FSM|Add0~1_sumout ;
wire \A_SPW_TOP|SPW|FSM|after128us~1_combout ;
wire \A_SPW_TOP|SPW|FSM|Add0~2 ;
wire \A_SPW_TOP|SPW|FSM|Add0~5_sumout ;
wire \A_SPW_TOP|SPW|FSM|after128us~2_combout ;
wire \A_SPW_TOP|SPW|FSM|Add0~6 ;
wire \A_SPW_TOP|SPW|FSM|Add0~9_sumout ;
wire \A_SPW_TOP|SPW|FSM|after128us~3_combout ;
wire \A_SPW_TOP|SPW|FSM|Add0~10 ;
wire \A_SPW_TOP|SPW|FSM|Add0~13_sumout ;
wire \A_SPW_TOP|SPW|FSM|after128us~4_combout ;
wire \A_SPW_TOP|SPW|FSM|Add0~14 ;
wire \A_SPW_TOP|SPW|FSM|Add0~17_sumout ;
wire \A_SPW_TOP|SPW|FSM|after128us~5_combout ;
wire \A_SPW_TOP|SPW|FSM|Add0~18 ;
wire \A_SPW_TOP|SPW|FSM|Add0~21_sumout ;
wire \A_SPW_TOP|SPW|FSM|after128us~6_combout ;
wire \A_SPW_TOP|SPW|FSM|Add0~22 ;
wire \A_SPW_TOP|SPW|FSM|Add0~26 ;
wire \A_SPW_TOP|SPW|FSM|Add0~29_sumout ;
wire \A_SPW_TOP|SPW|FSM|after128us~8_combout ;
wire \A_SPW_TOP|SPW|FSM|Add0~30 ;
wire \A_SPW_TOP|SPW|FSM|Add0~37_sumout ;
wire \A_SPW_TOP|SPW|FSM|after128us~10_combout ;
wire \A_SPW_TOP|SPW|FSM|Add0~38 ;
wire \A_SPW_TOP|SPW|FSM|Add0~41_sumout ;
wire \A_SPW_TOP|SPW|FSM|after128us~11_combout ;
wire \A_SPW_TOP|SPW|FSM|Add0~42 ;
wire \A_SPW_TOP|SPW|FSM|Add0~33_sumout ;
wire \A_SPW_TOP|SPW|FSM|after128us~9_combout ;
wire \A_SPW_TOP|SPW|FSM|Equal0~0_combout ;
wire \A_SPW_TOP|SPW|FSM|LessThan0~0_combout ;
wire \A_SPW_TOP|SPW|FSM|Add0~25_sumout ;
wire \A_SPW_TOP|SPW|FSM|after128us~7_combout ;
wire \A_SPW_TOP|SPW|FSM|Equal0~1_combout ;
wire \A_SPW_TOP|SPW|FSM|Selector4~0_combout ;
wire \A_SPW_TOP|SPW|FSM|Add0~34 ;
wire \A_SPW_TOP|SPW|FSM|Add0~45_sumout ;
wire \A_SPW_TOP|SPW|FSM|after128us~12_combout ;
wire \A_SPW_TOP|SPW|FSM|Equal0~2_combout ;
wire \A_SPW_TOP|SPW|FSM|Equal0~3_combout ;
wire \A_SPW_TOP|SPW|FSM|Selector0~1_combout ;
wire \A_SPW_TOP|SPW|FSM|Selector0~2_combout ;
wire \A_SPW_TOP|SPW|FSM|got_bit_internal~0_combout ;
wire \A_SPW_TOP|SPW|FSM|got_bit_internal~q ;
wire \A_SPW_TOP|SPW|FSM|Add2~29_sumout ;
wire \A_SPW_TOP|SPW|FSM|after850ns~7_combout ;
wire \A_SPW_TOP|SPW|FSM|Add2~30 ;
wire \A_SPW_TOP|SPW|FSM|Add2~25_sumout ;
wire \A_SPW_TOP|SPW|FSM|after850ns~6_combout ;
wire \A_SPW_TOP|SPW|FSM|Add2~26 ;
wire \A_SPW_TOP|SPW|FSM|Add2~22 ;
wire \A_SPW_TOP|SPW|FSM|Add2~9_sumout ;
wire \A_SPW_TOP|SPW|FSM|after850ns~2_combout ;
wire \A_SPW_TOP|SPW|FSM|Add2~10 ;
wire \A_SPW_TOP|SPW|FSM|Add2~17_sumout ;
wire \A_SPW_TOP|SPW|FSM|after850ns~4_combout ;
wire \A_SPW_TOP|SPW|FSM|Add2~18 ;
wire \A_SPW_TOP|SPW|FSM|Add2~5_sumout ;
wire \A_SPW_TOP|SPW|FSM|after850ns~1_combout ;
wire \A_SPW_TOP|SPW|FSM|Add2~6 ;
wire \A_SPW_TOP|SPW|FSM|Add2~13_sumout ;
wire \A_SPW_TOP|SPW|FSM|after850ns~3_combout ;
wire \A_SPW_TOP|SPW|FSM|LessThan2~1_combout ;
wire \A_SPW_TOP|SPW|FSM|Add2~14 ;
wire \A_SPW_TOP|SPW|FSM|Add2~33_sumout ;
wire \A_SPW_TOP|SPW|FSM|after850ns~8_combout ;
wire \A_SPW_TOP|SPW|FSM|Add2~34 ;
wire \A_SPW_TOP|SPW|FSM|Add2~37_sumout ;
wire \A_SPW_TOP|SPW|FSM|after850ns~9_combout ;
wire \A_SPW_TOP|SPW|FSM|Add2~38 ;
wire \A_SPW_TOP|SPW|FSM|Add2~41_sumout ;
wire \A_SPW_TOP|SPW|FSM|after850ns~10_combout ;
wire \A_SPW_TOP|SPW|FSM|Add2~42 ;
wire \A_SPW_TOP|SPW|FSM|Add2~45_sumout ;
wire \A_SPW_TOP|SPW|FSM|after850ns~11_combout ;
wire \A_SPW_TOP|SPW|FSM|Equal1~1_combout ;
wire \A_SPW_TOP|SPW|FSM|always5~1_combout ;
wire \A_SPW_TOP|SPW|FSM|Add2~21_sumout ;
wire \A_SPW_TOP|SPW|FSM|after850ns~5_combout ;
wire \A_SPW_TOP|SPW|FSM|LessThan2~0_combout ;
wire \A_SPW_TOP|SPW|FSM|always5~0_combout ;
wire \A_SPW_TOP|SPW|FSM|Add2~46 ;
wire \A_SPW_TOP|SPW|FSM|Add2~1_sumout ;
wire \A_SPW_TOP|SPW|FSM|after850ns~0_combout ;
wire \A_SPW_TOP|SPW|FSM|Equal1~0_combout ;
wire \A_SPW_TOP|SPW|FSM|Equal1~2_combout ;
wire \A_SPW_TOP|rx_data|credit_counter_write[0]~0_combout ;
wire \A_SPW_TOP|rx_data|Add2~2_combout ;
wire \A_SPW_TOP|rx_data|Add2~1_combout ;
wire \A_SPW_TOP|rx_data|credit_counter_reader~4_combout ;
wire \A_SPW_TOP|rx_data|credit_counter_reader~3_combout ;
wire \A_SPW_TOP|rx_data|credit_counter_reader~0_combout ;
wire \A_SPW_TOP|rx_data|credit_counter_reader~1_combout ;
wire \A_SPW_TOP|rx_data|Add2~0_combout ;
wire \A_SPW_TOP|rx_data|Add5~14 ;
wire \A_SPW_TOP|rx_data|Add5~15 ;
wire \A_SPW_TOP|rx_data|Add5~10 ;
wire \A_SPW_TOP|rx_data|Add5~11 ;
wire \A_SPW_TOP|rx_data|Add5~6 ;
wire \A_SPW_TOP|rx_data|Add5~7 ;
wire \A_SPW_TOP|rx_data|Add5~1_sumout ;
wire \A_SPW_TOP|rx_data|Add5~9_sumout ;
wire \A_SPW_TOP|rx_data|Add5~13_sumout ;
wire \A_SPW_TOP|rx_data|credit_counter_reader~6_combout ;
wire \A_SPW_TOP|rx_data|credit_counter_reader~5_combout ;
wire \A_SPW_TOP|rx_data|Add2~4_combout ;
wire \A_SPW_TOP|rx_data|Add2~3_combout ;
wire \A_SPW_TOP|rx_data|Add5~2 ;
wire \A_SPW_TOP|rx_data|Add5~3 ;
wire \A_SPW_TOP|rx_data|Add5~22 ;
wire \A_SPW_TOP|rx_data|Add5~23 ;
wire \A_SPW_TOP|rx_data|Add5~17_sumout ;
wire \A_SPW_TOP|rx_data|Add5~21_sumout ;
wire \A_SPW_TOP|rx_data|LessThan0~0_combout ;
wire \A_SPW_TOP|rx_data|credit_counter_reader~2_combout ;
wire \A_SPW_TOP|rx_data|Add5~5_sumout ;
wire \A_SPW_TOP|rx_data|LessThan1~0_combout ;
wire \A_SPW_TOP|rx_data|overflow_credit_error~q ;
wire \A_SPW_TOP|SPW|FSM|Selector0~0_combout ;
wire \A_SPW_TOP|SPW|FSM|state_fsm~13_combout ;
wire \A_SPW_TOP|SPW|FSM|state_fsm~14_combout ;
wire \A_SPW_TOP|SPW|FSM|state_fsm~15_combout ;
wire \A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q ;
wire \A_SPW_TOP|SPW|FSM|Equal2~3_combout ;
wire \A_SPW_TOP|SPW|FSM|Add1~5_sumout ;
wire \A_SPW_TOP|SPW|FSM|after64us~2_combout ;
wire \A_SPW_TOP|SPW|FSM|Add1~6 ;
wire \A_SPW_TOP|SPW|FSM|Add1~10 ;
wire \A_SPW_TOP|SPW|FSM|Add1~13_sumout ;
wire \A_SPW_TOP|SPW|FSM|after64us~4_combout ;
wire \A_SPW_TOP|SPW|FSM|Add1~14 ;
wire \A_SPW_TOP|SPW|FSM|Add1~17_sumout ;
wire \A_SPW_TOP|SPW|FSM|after64us~5_combout ;
wire \A_SPW_TOP|SPW|FSM|Add1~18 ;
wire \A_SPW_TOP|SPW|FSM|Add1~21_sumout ;
wire \A_SPW_TOP|SPW|FSM|after64us~6_combout ;
wire \A_SPW_TOP|SPW|FSM|Add1~22 ;
wire \A_SPW_TOP|SPW|FSM|Add1~25_sumout ;
wire \A_SPW_TOP|SPW|FSM|after64us~7_combout ;
wire \A_SPW_TOP|SPW|FSM|Add1~26 ;
wire \A_SPW_TOP|SPW|FSM|Add1~2 ;
wire \A_SPW_TOP|SPW|FSM|Add1~34 ;
wire \A_SPW_TOP|SPW|FSM|Add1~38 ;
wire \A_SPW_TOP|SPW|FSM|Add1~30 ;
wire \A_SPW_TOP|SPW|FSM|Add1~41_sumout ;
wire \A_SPW_TOP|SPW|FSM|after64us~11_combout ;
wire \A_SPW_TOP|SPW|FSM|Add1~42 ;
wire \A_SPW_TOP|SPW|FSM|Add1~45_sumout ;
wire \A_SPW_TOP|SPW|FSM|after64us~12_combout ;
wire \A_SPW_TOP|SPW|FSM|after64us~0_combout ;
wire \A_SPW_TOP|SPW|FSM|Add1~9_sumout ;
wire \A_SPW_TOP|SPW|FSM|after64us~3_combout ;
wire \A_SPW_TOP|SPW|FSM|Equal2~0_combout ;
wire \A_SPW_TOP|SPW|FSM|Add1~29_sumout ;
wire \A_SPW_TOP|SPW|FSM|after64us~8_combout ;
wire \A_SPW_TOP|SPW|FSM|Add1~37_sumout ;
wire \A_SPW_TOP|SPW|FSM|after64us~10_combout ;
wire \A_SPW_TOP|SPW|FSM|Equal2~2_combout ;
wire \A_SPW_TOP|SPW|FSM|Add1~1_sumout ;
wire \A_SPW_TOP|SPW|FSM|after64us~1_combout ;
wire \A_SPW_TOP|SPW|FSM|Add1~33_sumout ;
wire \A_SPW_TOP|SPW|FSM|after64us~9_combout ;
wire \A_SPW_TOP|SPW|FSM|Equal2~1_combout ;
wire \A_SPW_TOP|SPW|FSM|rx_resetn~0_combout ;
wire \A_SPW_TOP|SPW|FSM|rx_resetn~q ;
wire \A_SPW_TOP|SPW|RX|WideOr7~0_combout ;
wire \A_SPW_TOP|SPW|RX|Selector2~0_combout ;
wire \A_SPW_TOP|SPW|RX|Selector3~0_combout ;
wire \A_SPW_TOP|SPW|RX|Selector3~1_combout ;
wire \A_SPW_TOP|SPW|RX|Selector2~1_combout ;
wire \A_SPW_TOP|SPW|RX|Selector0~0_combout ;
wire \A_SPW_TOP|SPW|RX|Selector4~0_combout ;
wire \A_SPW_TOP|SPW|RX|Selector1~0_combout ;
wire \A_SPW_TOP|SPW|RX|Selector1~1_combout ;
wire \A_SPW_TOP|SPW|RX|Selector0~2_combout ;
wire \A_SPW_TOP|SPW|RX|Selector5~0_combout ;
wire \A_SPW_TOP|SPW|RX|Selector5~1_combout ;
wire \A_SPW_TOP|SPW|RX|always1~0_combout ;
wire \A_SPW_TOP|SPW|RX|ready_control_p_r~0_combout ;
wire \A_SPW_TOP|SPW|RX|ready_control_p_r~q ;
wire \A_SPW_TOP|SPW|RX|last_is_data~0_combout ;
wire \A_SPW_TOP|SPW|RX|last_is_data~q ;
wire \A_SPW_TOP|SPW|RX|rx_got_nchar~0_combout ;
wire \A_SPW_TOP|SPW|RX|rx_got_nchar~feeder_combout ;
wire \A_SPW_TOP|SPW|RX|rx_got_nchar~q ;
wire \A_SPW_TOP|SPW|FSM|state_fsm~24_combout ;
wire \A_SPW_TOP|SPW|FSM|state_fsm~22_combout ;
wire \A_SPW_TOP|SPW|FSM|state_fsm~23_combout ;
wire \A_SPW_TOP|SPW|FSM|state_fsm~25_combout ;
wire \A_SPW_TOP|SPW|FSM|state_fsm~19_combout ;
wire \A_SPW_TOP|SPW|FSM|state_fsm.run~q ;
wire \A_SPW_TOP|SPW|FSM|state_fsm.error_reset~0_combout ;
wire \A_SPW_TOP|SPW|FSM|state_fsm~11_combout ;
wire \A_SPW_TOP|SPW|FSM|state_fsm~12_combout ;
wire \A_SPW_TOP|SPW|FSM|state_fsm.error_wait~q ;
wire \A_SPW_TOP|SPW|FSM|WideOr0~combout ;
wire \A_SPW_TOP|SPW|FSM|send_null_tx~q ;
wire \A_SPW_TOP|SPW|TX|Selector63~3_combout ;
wire \A_SPW_TOP|SPW|TX|Selector64~0_combout ;
wire \A_SPW_TOP|SPW|TX|Equal0~4_combout ;
wire \A_SPW_TOP|SPW|TX|Selector73~1_combout ;
wire \A_SPW_TOP|SPW|TX|Selector60~0_combout ;
wire \A_SPW_TOP|SPW|TX|ready_tx_data~q ;
wire \A_SPW_TOP|tx_data|state_data_read~13_combout ;
wire \A_SPW_TOP|tx_data|state_data_read.11~q ;
wire \A_SPW_TOP|tx_data|state_data_read~12_combout ;
wire \A_SPW_TOP|tx_data|state_data_read.10~q ;
wire \A_SPW_TOP|tx_data|always3~0_combout ;
wire \A_SPW_TOP|tx_data|Add2~2_combout ;
wire \A_SPW_TOP|tx_data|Add2~3_combout ;
wire \A_SPW_TOP|tx_data|Add3~17_sumout ;
wire \A_SPW_TOP|tx_data|Equal0~0_combout ;
wire \A_SPW_TOP|tx_data|f_full~q ;
wire \u0|mm_interconnect_0|cmd_mux_011|src_payload~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;
wire \u0|write_en_tx|always0~0_combout ;
wire \u0|write_en_tx|data_out~q ;
wire \A_SPW_TOP|tx_data|state_data_write~7_combout ;
wire \A_SPW_TOP|tx_data|state_data_write.00~q ;
wire \A_SPW_TOP|tx_data|state_data_write~8_combout ;
wire \A_SPW_TOP|tx_data|state_data_write.01~q ;
wire \A_SPW_TOP|tx_data|state_data_write~9_combout ;
wire \A_SPW_TOP|tx_data|state_data_write.10~q ;
wire \A_SPW_TOP|tx_data|Add1~0_combout ;
wire \A_SPW_TOP|tx_data|Add3~5_sumout ;
wire \u0|counter_tx_fifo|read_mux_out[1]~1_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][1]~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~1_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][1]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~35_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][1]~q ;
wire \u0|fsm_info|read_mux_out[1]~1_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~1_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][1]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~34_combout ;
wire \u0|counter_rx_fifo|read_mux_out[1]~1_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][1]~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~1_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][1]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~36_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][1]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~1_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][1]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~242_combout ;
wire \m_x|rx_got_time_code~1_combout ;
wire \m_x|rx_got_time_code~q ;
wire \u0|mm_interconnect_0|cmd_mux|src_payload~1_combout ;
wire \u0|led_pio_test|data_out[1]~_Duplicate_1feeder_combout ;
wire \u0|led_pio_test|data_out[1]~_Duplicate_1_q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][1]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~1_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][1]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~30_combout ;
wire \A_SPW_TOP|SPW|RX|timecode~2_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][1]~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~1_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][1]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~31_combout ;
wire \A_SPW_TOP|SPW|RX|rx_data_flag~1_combout ;
wire \A_SPW_TOP|rx_data|Selector494~0_combout ;
wire \A_SPW_TOP|rx_data|mem[52][1]~q ;
wire \A_SPW_TOP|rx_data|Selector215~0_combout ;
wire \A_SPW_TOP|rx_data|mem[21][1]~q ;
wire \A_SPW_TOP|rx_data|Selector503~0_combout ;
wire \A_SPW_TOP|rx_data|mem[53][1]~q ;
wire \A_SPW_TOP|rx_data|Selector206~0_combout ;
wire \A_SPW_TOP|rx_data|mem[20][1]~q ;
wire \A_SPW_TOP|rx_data|Mux7~15_combout ;
wire \A_SPW_TOP|rx_data|Selector566~0_combout ;
wire \A_SPW_TOP|rx_data|mem[60][1]~q ;
wire \A_SPW_TOP|rx_data|Selector278~0_combout ;
wire \A_SPW_TOP|rx_data|mem[28][1]~q ;
wire \A_SPW_TOP|rx_data|Selector287~0_combout ;
wire \A_SPW_TOP|rx_data|mem[29][1]~q ;
wire \A_SPW_TOP|rx_data|Selector575~0_combout ;
wire \A_SPW_TOP|rx_data|mem[61][1]~q ;
wire \A_SPW_TOP|rx_data|Mux7~16_combout ;
wire \A_SPW_TOP|rx_data|Selector512~0_combout ;
wire \A_SPW_TOP|rx_data|mem[54][1]~q ;
wire \A_SPW_TOP|rx_data|Selector224~0_combout ;
wire \A_SPW_TOP|rx_data|mem[22][1]~q ;
wire \A_SPW_TOP|rx_data|Selector521~0_combout ;
wire \A_SPW_TOP|rx_data|mem[55][1]~q ;
wire \A_SPW_TOP|rx_data|Selector233~0_combout ;
wire \A_SPW_TOP|rx_data|mem[23][1]~q ;
wire \A_SPW_TOP|rx_data|Mux7~17_combout ;
wire \A_SPW_TOP|rx_data|Selector584~0_combout ;
wire \A_SPW_TOP|rx_data|mem[62][1]~q ;
wire \A_SPW_TOP|rx_data|Selector593~0_combout ;
wire \A_SPW_TOP|rx_data|mem[63][1]~q ;
wire \A_SPW_TOP|rx_data|Selector305~0_combout ;
wire \A_SPW_TOP|rx_data|mem[31][1]~q ;
wire \A_SPW_TOP|rx_data|Selector296~0_combout ;
wire \A_SPW_TOP|rx_data|mem[30][1]~q ;
wire \A_SPW_TOP|rx_data|Mux7~18_combout ;
wire \A_SPW_TOP|rx_data|Mux7~19_combout ;
wire \A_SPW_TOP|rx_data|Selector152~0_combout ;
wire \A_SPW_TOP|rx_data|mem[14][1]~q ;
wire \A_SPW_TOP|rx_data|Selector134~0_combout ;
wire \A_SPW_TOP|rx_data|mem[12][1]~q ;
wire \A_SPW_TOP|rx_data|Selector161~0_combout ;
wire \A_SPW_TOP|rx_data|mem[15][1]~q ;
wire \A_SPW_TOP|rx_data|Selector143~0_combout ;
wire \A_SPW_TOP|rx_data|mem[13][1]~q ;
wire \A_SPW_TOP|rx_data|Mux7~11_combout ;
wire \A_SPW_TOP|rx_data|Selector431~0_combout ;
wire \A_SPW_TOP|rx_data|mem[45][1]~q ;
wire \A_SPW_TOP|rx_data|Selector422~0_combout ;
wire \A_SPW_TOP|rx_data|mem[44][1]~q ;
wire \A_SPW_TOP|rx_data|Selector449~0_combout ;
wire \A_SPW_TOP|rx_data|mem[47][1]~q ;
wire \A_SPW_TOP|rx_data|Selector440~0_combout ;
wire \A_SPW_TOP|rx_data|mem[46][1]~q ;
wire \A_SPW_TOP|rx_data|Mux7~13_combout ;
wire \A_SPW_TOP|rx_data|Selector359~0_combout ;
wire \A_SPW_TOP|rx_data|mem[37][1]~q ;
wire \A_SPW_TOP|rx_data|Selector368~0_combout ;
wire \A_SPW_TOP|rx_data|mem[38][1]~q ;
wire \A_SPW_TOP|rx_data|Selector350~0_combout ;
wire \A_SPW_TOP|rx_data|mem[36][1]~q ;
wire \A_SPW_TOP|rx_data|Selector377~0_combout ;
wire \A_SPW_TOP|rx_data|mem[39][1]~q ;
wire \A_SPW_TOP|rx_data|Mux7~12_combout ;
wire \A_SPW_TOP|rx_data|Selector80~0_combout ;
wire \A_SPW_TOP|rx_data|mem[6][1]~q ;
wire \A_SPW_TOP|rx_data|Selector62~0_combout ;
wire \A_SPW_TOP|rx_data|mem[4][1]~q ;
wire \A_SPW_TOP|rx_data|Selector89~0_combout ;
wire \A_SPW_TOP|rx_data|mem[7][1]~q ;
wire \A_SPW_TOP|rx_data|Selector71~0_combout ;
wire \A_SPW_TOP|rx_data|mem[5][1]~q ;
wire \A_SPW_TOP|rx_data|Mux7~10_combout ;
wire \A_SPW_TOP|rx_data|Mux7~14_combout ;
wire \A_SPW_TOP|rx_data|Selector539~0_combout ;
wire \A_SPW_TOP|rx_data|mem[57][1]~q ;
wire \A_SPW_TOP|rx_data|Selector530~0_combout ;
wire \A_SPW_TOP|rx_data|mem[56][1]~q ;
wire \A_SPW_TOP|rx_data|Selector548~0_combout ;
wire \A_SPW_TOP|rx_data|mem[58][1]~q ;
wire \A_SPW_TOP|rx_data|Selector557~0_combout ;
wire \A_SPW_TOP|rx_data|mem[59][1]~q ;
wire \A_SPW_TOP|rx_data|Mux7~8_combout ;
wire \A_SPW_TOP|rx_data|Selector269~0_combout ;
wire \A_SPW_TOP|rx_data|mem[27][1]~q ;
wire \A_SPW_TOP|rx_data|Selector242~0_combout ;
wire \A_SPW_TOP|rx_data|mem[24][1]~q ;
wire \A_SPW_TOP|rx_data|Selector251~0_combout ;
wire \A_SPW_TOP|rx_data|mem[25][1]~q ;
wire \A_SPW_TOP|rx_data|Selector260~0_combout ;
wire \A_SPW_TOP|rx_data|mem[26][1]~q ;
wire \A_SPW_TOP|rx_data|Mux7~6_combout ;
wire \A_SPW_TOP|rx_data|Selector170~0_combout ;
wire \A_SPW_TOP|rx_data|mem[16][1]~q ;
wire \A_SPW_TOP|rx_data|Selector188~0_combout ;
wire \A_SPW_TOP|rx_data|mem[18][1]~q ;
wire \A_SPW_TOP|rx_data|Selector197~0_combout ;
wire \A_SPW_TOP|rx_data|mem[19][1]~q ;
wire \A_SPW_TOP|rx_data|Selector179~0_combout ;
wire \A_SPW_TOP|rx_data|mem[17][1]~q ;
wire \A_SPW_TOP|rx_data|Mux7~5_combout ;
wire \A_SPW_TOP|rx_data|Selector467~0_combout ;
wire \A_SPW_TOP|rx_data|mem[49][1]~q ;
wire \A_SPW_TOP|rx_data|Selector485~0_combout ;
wire \A_SPW_TOP|rx_data|mem[51][1]~q ;
wire \A_SPW_TOP|rx_data|Selector458~0_combout ;
wire \A_SPW_TOP|rx_data|mem[48][1]~q ;
wire \A_SPW_TOP|rx_data|Selector476~0_combout ;
wire \A_SPW_TOP|rx_data|mem[50][1]~q ;
wire \A_SPW_TOP|rx_data|Mux7~7_combout ;
wire \A_SPW_TOP|rx_data|Mux7~9_combout ;
wire \A_SPW_TOP|rx_data|Selector116~0_combout ;
wire \A_SPW_TOP|rx_data|mem[10][1]~q ;
wire \A_SPW_TOP|rx_data|Selector125~0_combout ;
wire \A_SPW_TOP|rx_data|mem[11][1]~q ;
wire \A_SPW_TOP|rx_data|Selector98~0_combout ;
wire \A_SPW_TOP|rx_data|mem[8][1]~q ;
wire \A_SPW_TOP|rx_data|Mux7~1_combout ;
wire \A_SPW_TOP|rx_data|Selector395~0_combout ;
wire \A_SPW_TOP|rx_data|mem[41][1]~q ;
wire \A_SPW_TOP|rx_data|Selector404~0_combout ;
wire \A_SPW_TOP|rx_data|mem[42][1]~q ;
wire \A_SPW_TOP|rx_data|Selector386~0_combout ;
wire \A_SPW_TOP|rx_data|mem[40][1]~q ;
wire \A_SPW_TOP|rx_data|Selector413~0_combout ;
wire \A_SPW_TOP|rx_data|mem[43][1]~q ;
wire \A_SPW_TOP|rx_data|Mux7~3_combout ;
wire \A_SPW_TOP|rx_data|Selector44~0_combout ;
wire \A_SPW_TOP|rx_data|mem[2][1]~q ;
wire \A_SPW_TOP|rx_data|Selector35~0_combout ;
wire \A_SPW_TOP|rx_data|mem[1][1]~q ;
wire \A_SPW_TOP|rx_data|Selector53~0_combout ;
wire \A_SPW_TOP|rx_data|mem[3][1]~q ;
wire \A_SPW_TOP|rx_data|Selector26~0_combout ;
wire \A_SPW_TOP|rx_data|mem[0][1]~q ;
wire \A_SPW_TOP|rx_data|Mux7~0_combout ;
wire \A_SPW_TOP|rx_data|Selector332~0_combout ;
wire \A_SPW_TOP|rx_data|mem[34][1]~q ;
wire \A_SPW_TOP|rx_data|Selector314~0_combout ;
wire \A_SPW_TOP|rx_data|mem[32][1]~q ;
wire \A_SPW_TOP|rx_data|Selector341~0_combout ;
wire \A_SPW_TOP|rx_data|mem[35][1]~q ;
wire \A_SPW_TOP|rx_data|Selector323~0_combout ;
wire \A_SPW_TOP|rx_data|mem[33][1]~q ;
wire \A_SPW_TOP|rx_data|Mux7~2_combout ;
wire \A_SPW_TOP|rx_data|Mux7~4_combout ;
wire \A_SPW_TOP|rx_data|Mux7~20_combout ;
wire \A_SPW_TOP|rx_data|Selector107~0_combout ;
wire \A_SPW_TOP|rx_data|mem[9][1]~q ;
wire \A_SPW_TOP|rx_data|Mux16~7_combout ;
wire \A_SPW_TOP|rx_data|Mux16~5_combout ;
wire \A_SPW_TOP|rx_data|Mux16~6_combout ;
wire \A_SPW_TOP|rx_data|Mux16~8_combout ;
wire \A_SPW_TOP|rx_data|Mux16~9_combout ;
wire \A_SPW_TOP|rx_data|Mux16~13_combout ;
wire \A_SPW_TOP|rx_data|Mux16~10_combout ;
wire \A_SPW_TOP|rx_data|Mux16~11_combout ;
wire \A_SPW_TOP|rx_data|Mux16~12_combout ;
wire \A_SPW_TOP|rx_data|Mux16~14_combout ;
wire \A_SPW_TOP|rx_data|Mux16~16_combout ;
wire \A_SPW_TOP|rx_data|Mux16~18_combout ;
wire \A_SPW_TOP|rx_data|Mux16~15_combout ;
wire \A_SPW_TOP|rx_data|Mux16~17_combout ;
wire \A_SPW_TOP|rx_data|Mux16~19_combout ;
wire \A_SPW_TOP|rx_data|Mux16~3_combout ;
wire \A_SPW_TOP|rx_data|Mux16~2_combout ;
wire \A_SPW_TOP|rx_data|Mux16~0_combout ;
wire \A_SPW_TOP|rx_data|Mux16~1_combout ;
wire \A_SPW_TOP|rx_data|Mux16~4_combout ;
wire \A_SPW_TOP|rx_data|Mux16~20_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][1]~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~1_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][1]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~32_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~33_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][1]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][1]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~37_combout ;
wire \u0|mm_interconnect_0|cmd_mux_018|src_payload~1_combout ;
wire \u0|clock_sel|readdata[1]~1_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[1][1]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem~1_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[0][1]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~38_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~39_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][1]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~1_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][1]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~238_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|read~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|read~1_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used[1]~1_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used[0]~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem[1][0]~q ;
wire \u0|auto_start|readdata[0]~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem[0][0]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~0_combout ;
wire \u0|counter_rx_fifo|read_mux_out[0]~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][0]~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][0]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~3_combout ;
wire \u0|mm_interconnect_0|rsp_demux_008|src1_valid~combout ;
wire \u0|counter_tx_fifo|read_mux_out[0]~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][0]~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][0]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~2_combout ;
wire \u0|fsm_info|read_mux_out[0]~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][0]~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][0]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~1_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~4_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][0]~q ;
wire \A_SPW_TOP|SPW|RX|rx_data_flag~12_combout ;
wire \A_SPW_TOP|rx_data|Selector486~0_combout ;
wire \A_SPW_TOP|rx_data|mem[51][0]~q ;
wire \A_SPW_TOP|rx_data|Selector522~0_combout ;
wire \A_SPW_TOP|rx_data|mem[55][0]~feeder_combout ;
wire \A_SPW_TOP|rx_data|mem[55][0]~q ;
wire \A_SPW_TOP|rx_data|Selector342~0_combout ;
wire \A_SPW_TOP|rx_data|mem[35][0]~q ;
wire \A_SPW_TOP|rx_data|Mux8~13_combout ;
wire \A_SPW_TOP|rx_data|Selector477~0_combout ;
wire \A_SPW_TOP|rx_data|mem[50][0]~q ;
wire \A_SPW_TOP|rx_data|Selector369~0_combout ;
wire \A_SPW_TOP|rx_data|mem[38][0]~q ;
wire \A_SPW_TOP|rx_data|Selector513~0_combout ;
wire \A_SPW_TOP|rx_data|mem[54][0]~q ;
wire \A_SPW_TOP|rx_data|Selector333~0_combout ;
wire \A_SPW_TOP|rx_data|mem[34][0]~q ;
wire \A_SPW_TOP|rx_data|Mux8~12_combout ;
wire \A_SPW_TOP|rx_data|Selector459~0_combout ;
wire \A_SPW_TOP|rx_data|mem[48][0]~q ;
wire \A_SPW_TOP|rx_data|Selector495~0_combout ;
wire \A_SPW_TOP|rx_data|mem[52][0]~q ;
wire \A_SPW_TOP|rx_data|Selector351~0_combout ;
wire \A_SPW_TOP|rx_data|mem[36][0]~q ;
wire \A_SPW_TOP|rx_data|Selector315~0_combout ;
wire \A_SPW_TOP|rx_data|mem[32][0]~q ;
wire \A_SPW_TOP|rx_data|Mux8~10_combout ;
wire \A_SPW_TOP|rx_data|Selector324~0_combout ;
wire \A_SPW_TOP|rx_data|mem[33][0]~q ;
wire \A_SPW_TOP|rx_data|Selector504~0_combout ;
wire \A_SPW_TOP|rx_data|mem[53][0]~q ;
wire \A_SPW_TOP|rx_data|Selector468~0_combout ;
wire \A_SPW_TOP|rx_data|mem[49][0]~q ;
wire \A_SPW_TOP|rx_data|Selector360~0_combout ;
wire \A_SPW_TOP|rx_data|mem[37][0]~q ;
wire \A_SPW_TOP|rx_data|Mux8~11_combout ;
wire \A_SPW_TOP|rx_data|Mux8~14_combout ;
wire \A_SPW_TOP|rx_data|Selector423~0_combout ;
wire \A_SPW_TOP|rx_data|mem[44][0]~q ;
wire \A_SPW_TOP|rx_data|Selector567~0_combout ;
wire \A_SPW_TOP|rx_data|mem[60][0]~q ;
wire \A_SPW_TOP|rx_data|Selector441~0_combout ;
wire \A_SPW_TOP|rx_data|mem[46][0]~q ;
wire \A_SPW_TOP|rx_data|Selector585~0_combout ;
wire \A_SPW_TOP|rx_data|mem[62][0]~q ;
wire \A_SPW_TOP|rx_data|Mux8~17_combout ;
wire \A_SPW_TOP|rx_data|Selector387~0_combout ;
wire \A_SPW_TOP|rx_data|mem[40][0]~feeder_combout ;
wire \A_SPW_TOP|rx_data|mem[40][0]~q ;
wire \A_SPW_TOP|rx_data|Selector549~0_combout ;
wire \A_SPW_TOP|rx_data|mem[58][0]~q ;
wire \A_SPW_TOP|rx_data|Selector405~0_combout ;
wire \A_SPW_TOP|rx_data|mem[42][0]~q ;
wire \A_SPW_TOP|rx_data|Selector531~0_combout ;
wire \A_SPW_TOP|rx_data|mem[56][0]~q ;
wire \A_SPW_TOP|rx_data|Mux8~15_combout ;
wire \A_SPW_TOP|rx_data|Selector396~0_combout ;
wire \A_SPW_TOP|rx_data|mem[41][0]~q ;
wire \A_SPW_TOP|rx_data|Selector414~0_combout ;
wire \A_SPW_TOP|rx_data|mem[43][0]~q ;
wire \A_SPW_TOP|rx_data|Selector558~0_combout ;
wire \A_SPW_TOP|rx_data|mem[59][0]~q ;
wire \A_SPW_TOP|rx_data|Selector540~0_combout ;
wire \A_SPW_TOP|rx_data|mem[57][0]~q ;
wire \A_SPW_TOP|rx_data|Mux8~16_combout ;
wire \A_SPW_TOP|rx_data|Selector450~0_combout ;
wire \A_SPW_TOP|rx_data|mem[47][0]~q ;
wire \A_SPW_TOP|rx_data|Selector594~0_combout ;
wire \A_SPW_TOP|rx_data|mem[63][0]~q ;
wire \A_SPW_TOP|rx_data|Selector432~0_combout ;
wire \A_SPW_TOP|rx_data|mem[45][0]~q ;
wire \A_SPW_TOP|rx_data|Selector576~0_combout ;
wire \A_SPW_TOP|rx_data|mem[61][0]~q ;
wire \A_SPW_TOP|rx_data|Mux8~18_combout ;
wire \A_SPW_TOP|rx_data|Mux8~19_combout ;
wire \A_SPW_TOP|rx_data|Selector144~0_combout ;
wire \A_SPW_TOP|rx_data|mem[13][0]~q ;
wire \A_SPW_TOP|rx_data|Selector108~0_combout ;
wire \A_SPW_TOP|rx_data|mem[9][0]~q ;
wire \A_SPW_TOP|rx_data|Selector252~0_combout ;
wire \A_SPW_TOP|rx_data|mem[25][0]~q ;
wire \A_SPW_TOP|rx_data|Selector288~0_combout ;
wire \A_SPW_TOP|rx_data|mem[29][0]~q ;
wire \A_SPW_TOP|rx_data|Mux8~6_combout ;
wire \A_SPW_TOP|rx_data|Selector261~0_combout ;
wire \A_SPW_TOP|rx_data|mem[26][0]~q ;
wire \A_SPW_TOP|rx_data|Selector117~0_combout ;
wire \A_SPW_TOP|rx_data|mem[10][0]~q ;
wire \A_SPW_TOP|rx_data|Selector153~0_combout ;
wire \A_SPW_TOP|rx_data|mem[14][0]~q ;
wire \A_SPW_TOP|rx_data|Selector297~0_combout ;
wire \A_SPW_TOP|rx_data|mem[30][0]~q ;
wire \A_SPW_TOP|rx_data|Mux8~7_combout ;
wire \A_SPW_TOP|rx_data|Selector243~0_combout ;
wire \A_SPW_TOP|rx_data|mem[24][0]~q ;
wire \A_SPW_TOP|rx_data|Selector99~0_combout ;
wire \A_SPW_TOP|rx_data|mem[8][0]~q ;
wire \A_SPW_TOP|rx_data|Selector279~0_combout ;
wire \A_SPW_TOP|rx_data|mem[28][0]~q ;
wire \A_SPW_TOP|rx_data|Selector135~0_combout ;
wire \A_SPW_TOP|rx_data|mem[12][0]~q ;
wire \A_SPW_TOP|rx_data|Mux8~5_combout ;
wire \A_SPW_TOP|rx_data|Selector126~0_combout ;
wire \A_SPW_TOP|rx_data|mem[11][0]~q ;
wire \A_SPW_TOP|rx_data|Selector270~0_combout ;
wire \A_SPW_TOP|rx_data|mem[27][0]~feeder_combout ;
wire \A_SPW_TOP|rx_data|mem[27][0]~q ;
wire \A_SPW_TOP|rx_data|Selector306~0_combout ;
wire \A_SPW_TOP|rx_data|mem[31][0]~q ;
wire \A_SPW_TOP|rx_data|Selector162~0_combout ;
wire \A_SPW_TOP|rx_data|mem[15][0]~q ;
wire \A_SPW_TOP|rx_data|Mux8~8_combout ;
wire \A_SPW_TOP|rx_data|Mux8~9_combout ;
wire \A_SPW_TOP|rx_data|Selector207~0_combout ;
wire \A_SPW_TOP|rx_data|mem[20][0]~q ;
wire \A_SPW_TOP|rx_data|Selector63~0_combout ;
wire \A_SPW_TOP|rx_data|mem[4][0]~q ;
wire \A_SPW_TOP|rx_data|Selector171~0_combout ;
wire \A_SPW_TOP|rx_data|mem[16][0]~q ;
wire \A_SPW_TOP|rx_data|Selector27~0_combout ;
wire \A_SPW_TOP|rx_data|mem[0][0]~q ;
wire \A_SPW_TOP|rx_data|Mux8~0_combout ;
wire \A_SPW_TOP|rx_data|Selector54~0_combout ;
wire \A_SPW_TOP|rx_data|mem[3][0]~feeder_combout ;
wire \A_SPW_TOP|rx_data|mem[3][0]~q ;
wire \A_SPW_TOP|rx_data|Selector234~0_combout ;
wire \A_SPW_TOP|rx_data|mem[23][0]~q ;
wire \A_SPW_TOP|rx_data|Selector90~0_combout ;
wire \A_SPW_TOP|rx_data|mem[7][0]~q ;
wire \A_SPW_TOP|rx_data|Selector198~0_combout ;
wire \A_SPW_TOP|rx_data|mem[19][0]~q ;
wire \A_SPW_TOP|rx_data|Mux8~3_combout ;
wire \A_SPW_TOP|rx_data|Selector45~0_combout ;
wire \A_SPW_TOP|rx_data|mem[2][0]~q ;
wire \A_SPW_TOP|rx_data|Selector189~0_combout ;
wire \A_SPW_TOP|rx_data|mem[18][0]~q ;
wire \A_SPW_TOP|rx_data|Selector81~0_combout ;
wire \A_SPW_TOP|rx_data|mem[6][0]~q ;
wire \A_SPW_TOP|rx_data|Selector225~0_combout ;
wire \A_SPW_TOP|rx_data|mem[22][0]~q ;
wire \A_SPW_TOP|rx_data|Mux8~2_combout ;
wire \A_SPW_TOP|rx_data|Selector36~0_combout ;
wire \A_SPW_TOP|rx_data|mem[1][0]~feeder_combout ;
wire \A_SPW_TOP|rx_data|mem[1][0]~q ;
wire \A_SPW_TOP|rx_data|Selector180~0_combout ;
wire \A_SPW_TOP|rx_data|mem[17][0]~q ;
wire \A_SPW_TOP|rx_data|Selector216~0_combout ;
wire \A_SPW_TOP|rx_data|mem[21][0]~q ;
wire \A_SPW_TOP|rx_data|Selector72~0_combout ;
wire \A_SPW_TOP|rx_data|mem[5][0]~q ;
wire \A_SPW_TOP|rx_data|Mux8~1_combout ;
wire \A_SPW_TOP|rx_data|Mux8~4_combout ;
wire \A_SPW_TOP|rx_data|Mux8~20_combout ;
wire \A_SPW_TOP|rx_data|Selector378~0_combout ;
wire \A_SPW_TOP|rx_data|mem[39][0]~q ;
wire \A_SPW_TOP|rx_data|Mux17~3_combout ;
wire \A_SPW_TOP|rx_data|Mux17~2_combout ;
wire \A_SPW_TOP|rx_data|Mux17~0_combout ;
wire \A_SPW_TOP|rx_data|Mux17~1_combout ;
wire \A_SPW_TOP|rx_data|Mux17~4_combout ;
wire \A_SPW_TOP|rx_data|Mux17~16_combout ;
wire \A_SPW_TOP|rx_data|Mux17~18_combout ;
wire \A_SPW_TOP|rx_data|Mux17~17_combout ;
wire \A_SPW_TOP|rx_data|Mux17~15_combout ;
wire \A_SPW_TOP|rx_data|Mux17~19_combout ;
wire \A_SPW_TOP|rx_data|Mux17~13_combout ;
wire \A_SPW_TOP|rx_data|Mux17~10_combout ;
wire \A_SPW_TOP|rx_data|Mux17~12_combout ;
wire \A_SPW_TOP|rx_data|Mux17~11_combout ;
wire \A_SPW_TOP|rx_data|Mux17~14_combout ;
wire \A_SPW_TOP|rx_data|Mux17~7_combout ;
wire \A_SPW_TOP|rx_data|Mux17~8_combout ;
wire \A_SPW_TOP|rx_data|Mux17~6_combout ;
wire \A_SPW_TOP|rx_data|Mux17~5_combout ;
wire \A_SPW_TOP|rx_data|Mux17~9_combout ;
wire \A_SPW_TOP|rx_data|Mux17~20_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][0]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~13_combout ;
wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~14_combout ;
wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~15_combout ;
wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~16_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;
wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~18_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;
wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~17_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;
wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~13_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;
wire \A_SPW_TOP|SPW|RX|rx_tick_out~0_combout ;
wire \A_SPW_TOP|SPW|RX|rx_tick_out~feeder_combout ;
wire \A_SPW_TOP|SPW|RX|rx_tick_out~q ;
wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~12_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;
wire \u0|timecode_ready_rx|read_mux_out~combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem[1][0]~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem[0][0]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~17_combout ;
wire \u0|mm_interconnect_0|cmd_mux|src_payload~0_combout ;
wire \u0|led_pio_test|data_out[0]~_Duplicate_1_q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][0]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][0]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~15_combout ;
wire \A_SPW_TOP|SPW|RX|timecode~1_combout ;
wire \A_SPW_TOP|SPW|RX|timecode[0]~feeder_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][0]~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][0]~feeder_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][0]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~16_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~18_combout ;
wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~12_combout ;
wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~14_combout ;
wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~16_combout ;
wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~15_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~13_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;
wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~17_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;
wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~18_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3]~feeder_combout ;
wire \u0|fifo_full_rx_status|read_mux_out~combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][0]~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][0]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~20_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem[1][0]~q ;
wire \u0|data_read_en_rx|readdata[0]~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem[0][0]~feeder_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem[0][0]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~19_combout ;
wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~14_combout ;
wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~16_combout ;
wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~15_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;
wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~17_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;
wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~18_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;
wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~13_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;
wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~12_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;
wire \u0|fifo_full_tx_status|read_mux_out~combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][0]~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][0]~feeder_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][0]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~22_combout ;
wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~14_combout ;
wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~16_combout ;
wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~15_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~13_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;
wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~17_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;
wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~18_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;
wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~12_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;
wire \u0|fifo_empty_rx_status|read_mux_out~combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][0]~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][0]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~21_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~23_combout ;
wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~13_combout ;
wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~14_combout ;
wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~15_combout ;
wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~16_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;
wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~17_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~18_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;
wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~12_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;
wire \A_SPW_TOP|SPW|TX|Selector61~0_combout ;
wire \A_SPW_TOP|SPW|TX|Selector61~1_combout ;
wire \A_SPW_TOP|SPW|TX|ready_tx_timecode~q ;
wire \u0|timecode_tx_ready|read_mux_out~combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem[1][0]~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem[0][0]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~26_combout ;
wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~12_combout ;
wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~14_combout ;
wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~15_combout ;
wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~16_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;
wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~13_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;
wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~17_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;
wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~18_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;
wire \u0|fifo_empty_tx_status|read_mux_out~combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][0]~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][0]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~25_combout ;
wire \u0|link_start|readdata[0]~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem[1][0]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem[0][0]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~24_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~27_combout ;
wire \m_x|rx_got_fct~0_combout ;
wire \m_x|rx_got_fct~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][0]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][0]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~14_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~28_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem[1][0]~q ;
wire \u0|write_en_tx|readdata[0]~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem[0][0]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~7_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][0]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][0]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~8_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~9_combout ;
wire \u0|timecode_tx_enable|readdata[0]~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem[1][0]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem[0][0]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~10_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[1][0]~q ;
wire \u0|clock_sel|readdata[0]~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[0][0]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~11_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~12_combout ;
wire \u0|link_disable|readdata[0]~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem[1][0]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem[0][0]~feeder_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem[0][0]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~5_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][0]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][0]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~6_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~29_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][116]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~21_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][116]~feeder_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][116]~q ;
wire \u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout ;
wire \u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[116]~56_combout ;
wire \u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[116]~59_combout ;
wire \u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[116]~55_combout ;
wire \u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[116]~58_combout ;
wire \u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[116]~57_combout ;
wire \u0|mm_interconnect_0|router_001|Equal1~0_combout ;
wire \u0|mm_interconnect_0|router_001|Equal21~0_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|src15_valid~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_015|packet_in_progress~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_015|packet_in_progress~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_015|update_grant~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg~2_combout ;
wire \u0|mm_interconnect_0|cmd_mux_015|arb|grant[1]~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][66]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~3_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][66]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][69]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][69]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][68]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][68]~q ;
wire \u0|mm_interconnect_0|rsp_demux_015|src0_valid~0_combout ;
wire \u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[115]~54_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[115]~51_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[115]~50_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[115]~53_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[115]~52_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~1_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~1_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux|update_grant~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg~2_combout ;
wire \u0|mm_interconnect_0|cmd_mux|arb|grant[1]~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~1_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][69]~feeder_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][69]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][68]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~2_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][68]~q ;
wire \u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ;
wire \u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[114]~45_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[114]~47_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[114]~48_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[114]~46_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[114]~49_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][113]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~18_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][113]~q ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[113]~44_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[113]~43_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[113]~40_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[113]~42_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[113]~41_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|src0_valid~0_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|src0_valid~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux|arb|grant[0]~1_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][112]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~17_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][112]~q ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[112]~35_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[112]~36_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[112]~38_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[112]~37_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[112]~39_combout ;
wire \u0|mm_interconnect_0|router_001|Equal1~2_combout ;
wire \u0|mm_interconnect_0|router_001|Equal3~0_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|src10_valid~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_010|packet_in_progress~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_010|packet_in_progress~q ;
wire \u0|mm_interconnect_0|cmd_mux_010|update_grant~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg~2_combout ;
wire \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_010|arb|grant[1]~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][111]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~16_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][111]~q ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[111]~32_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[111]~31_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[111]~30_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[111]~34_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[111]~33_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~15_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][110]~q ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[110]~27_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[110]~29_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[110]~25_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[110]~26_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[110]~28_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~57_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector11~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~3_combout ;
wire \u0|mm_interconnect_0|router|Equal13~0_combout ;
wire \u0|mm_interconnect_0|cmd_demux|src7_valid~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_007|arb|grant[0]~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_007|packet_in_progress~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_007|packet_in_progress~q ;
wire \u0|mm_interconnect_0|cmd_mux_007|update_grant~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][109]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~14_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][109]~q ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[109]~21_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[109]~20_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[109]~24_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[109]~22_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[109]~23_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~45_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector14~0_combout ;
wire \u0|mm_interconnect_0|router|Equal7~0_combout ;
wire \u0|mm_interconnect_0|router|Equal6~4_combout ;
wire \u0|mm_interconnect_0|router|Equal6~1_combout ;
wire \u0|mm_interconnect_0|router|Equal6~2_combout ;
wire \u0|mm_interconnect_0|router|Equal6~3_combout ;
wire \u0|mm_interconnect_0|router|Equal7~1_combout ;
wire \u0|mm_interconnect_0|router|Equal16~0_combout ;
wire \u0|mm_interconnect_0|cmd_demux|src10_valid~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_010|arb|grant[0]~1_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][68]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~2_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][68]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][69]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~1_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][69]~q ;
wire \u0|mm_interconnect_0|rsp_demux_010|src0_valid~0_combout ;
wire \u0|mm_interconnect_0|rsp_demux_010|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used[1]~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][108]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~13_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][108]~q ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[108]~17_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[108]~15_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[108]~18_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[108]~19_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[108]~16_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_write~combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter~1_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|local_write~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|write~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used[0]~1_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|rp_valid~combout ;
wire \u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[107]~12_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[107]~10_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[107]~13_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[107]~14_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[107]~11_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|always0~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used[1]~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][106]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~11_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][106]~feeder_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][106]~q ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[106]~5_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[106]~6_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[106]~8_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[106]~7_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[106]~9_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout ;
wire \u0|mm_interconnect_0|cmd_demux|src8_valid~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_008|arb|grant[0]~1_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~1_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~1_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent|local_write~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|write~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[1]~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][105]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~10_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][105]~q ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[105]~1_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[105]~0_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[105]~2_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[105]~4_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[105]~3_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector24~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~6 ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~1_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~5_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[5]~4_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector24~1_combout ;
wire \u0|mm_interconnect_0|router|Equal6~0_combout ;
wire \u0|mm_interconnect_0|router|Equal6~6_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;
wire \u0|mm_interconnect_0|cmd_demux|sink_ready~0_combout ;
wire \u0|mm_interconnect_0|cmd_demux|sink_ready~7_combout ;
wire \u0|mm_interconnect_0|cmd_demux|sink_ready~3_combout ;
wire \u0|mm_interconnect_0|cmd_demux|sink_ready~4_combout ;
wire \u0|mm_interconnect_0|cmd_demux|WideOr0~1_combout ;
wire \u0|mm_interconnect_0|cmd_demux|sink_ready~5_combout ;
wire \u0|mm_interconnect_0|cmd_demux|sink_ready~6_combout ;
wire \u0|mm_interconnect_0|cmd_demux|WideOr0~2_combout ;
wire \u0|mm_interconnect_0|cmd_demux|sink_ready~9_combout ;
wire \u0|mm_interconnect_0|cmd_demux|sink_ready~8_combout ;
wire \u0|mm_interconnect_0|cmd_demux|WideOr0~3_combout ;
wire \u0|mm_interconnect_0|cmd_demux|WideOr0~4_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ;
wire \u0|mm_interconnect_0|router|Equal6~8_combout ;
wire \u0|mm_interconnect_0|cmd_demux|src18_valid~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_018|src_valid~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent|m0_read~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter~1_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter~2_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~4_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg~1_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent|comb~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|always0~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used[0]~1_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent|rp_valid~combout ;
wire \u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|WideOr1~0_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|WideOr1~1_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|WideOr1~2_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|rp_valid~combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|rp_valid~combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|WideOr1~3_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|WideOr1~4_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|WideOr1~combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|src7_valid~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg~2_combout ;
wire \u0|mm_interconnect_0|cmd_mux_007|arb|grant[1]~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][78]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~9_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][78]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_busy~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][76]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~7_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][76]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][75]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~6_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][75]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][77]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~8_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][77]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~2_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|write~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used[0]~1_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used[1]~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][74]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~5_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~1_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~2_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~1_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~1_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][130]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~4_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][130]~q ;
wire \u0|mm_interconnect_0|rsp_mux|src_payload~8_combout ;
wire \u0|mm_interconnect_0|rsp_demux_004|src1_valid~combout ;
wire \u0|mm_interconnect_0|rsp_demux_007|src1_valid~combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][130]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~4_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][130]~q ;
wire \u0|mm_interconnect_0|rsp_mux|src_payload~7_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][130]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~4_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][130]~q ;
wire \u0|mm_interconnect_0|rsp_mux|src_payload~6_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~3_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][130]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~4_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][130]~q ;
wire \u0|mm_interconnect_0|rsp_mux|src_payload~1_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][130]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~4_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][130]~q ;
wire \u0|mm_interconnect_0|rsp_mux|src_payload~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][130]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~4_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][130]~q ;
wire \u0|mm_interconnect_0|rsp_mux|src_payload~2_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~1_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][130]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~4_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][130]~q ;
wire \u0|mm_interconnect_0|rsp_mux|src_payload~3_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][130]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~4_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][130]~q ;
wire \u0|mm_interconnect_0|rsp_mux|src_payload~5_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][130]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~4_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][130]~q ;
wire \u0|mm_interconnect_0|rsp_mux|src_payload~4_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~2_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][130]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~4_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][130]~feeder_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][130]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][130]~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~8_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][130]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~8_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~9_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][130]~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~8_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][130]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~6_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~7_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][130]~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~8_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][130]~feeder_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][130]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~10_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~11_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][130]~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~8_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][130]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~4_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~5_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][130]~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~2_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][130]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~12_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][130]~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~8_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][130]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~13_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~14_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~15_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][130]~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~8_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][130]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~24_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~25_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][130]~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~8_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][130]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~26_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~27_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][130]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~8_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][130]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~22_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~23_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][130]~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~8_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][130]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~18_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~19_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][130]~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~8_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][130]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~20_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~21_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][130]~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~8_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][130]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~16_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~17_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~28_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout ;
wire \u0|mm_interconnect_0|router|Equal21~0_combout ;
wire \u0|mm_interconnect_0|cmd_demux|src15_valid~0_combout ;
wire \u0|mm_interconnect_0|cmd_demux|src15_valid~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_015|arb|grant[0]~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ;
wire \u0|mm_interconnect_0|cmd_demux|sink_ready~2_combout ;
wire \u0|mm_interconnect_0|cmd_demux|sink_ready~1_combout ;
wire \u0|mm_interconnect_0|cmd_demux|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|cmd_demux|sink_ready~10_combout ;
wire \u0|mm_interconnect_0|cmd_demux|WideOr0~combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_payload~9_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_payload~10_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_payload~12_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_payload~11_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|response_sink_accepted~combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|next_pending_response_count~1_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|always1~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|next_pending_response_count~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~1_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~2_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q ;
wire \u0|mm_interconnect_0|router|src_data[103]~1_combout ;
wire \u0|mm_interconnect_0|router|src_data~2_combout ;
wire \u0|mm_interconnect_0|router|src_data[101]~5_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~1_combout ;
wire \u0|mm_interconnect_0|router|src_data~4_combout ;
wire \u0|mm_interconnect_0|router|src_data[104]~6_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~2_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~3_combout ;
wire \u0|mm_interconnect_0|router|src_data[102]~3_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ;
wire \u0|mm_interconnect_0|router|Equal14~0_combout ;
wire \u0|mm_interconnect_0|router|Equal17~0_combout ;
wire \u0|mm_interconnect_0|cmd_demux|src11_valid~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_011|arb|grant[0]~1_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent|local_write~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent|m0_write~combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter~1_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~4_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|write~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used[1]~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][66]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~3_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][66]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][69]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~1_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][69]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][68]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~2_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][68]~q ;
wire \u0|mm_interconnect_0|rsp_demux_011|src0_valid~0_combout ;
wire \u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout ;
wire \u0|mm_interconnect_0|rsp_mux|WideOr1~1_combout ;
wire \u0|mm_interconnect_0|rsp_mux|WideOr1~0_combout ;
wire \u0|mm_interconnect_0|rsp_mux|WideOr1~combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~0_combout ;
wire \u0|mm_interconnect_0|router_001|Equal5~0_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~9_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~10_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~11_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|WideOr0~5_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~0_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~8_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|WideOr0~4_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~5_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~7_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~6_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|WideOr0~3_combout ;
wire \u0|mm_interconnect_0|router_001|Equal6~0_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~4_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~3_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|WideOr0~2_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~2_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~1_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|WideOr0~1_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|WideOr0~6_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~13_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~16_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|WideOr0~7_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~15_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~14_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~12_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~17_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|WideOr0~8_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|WideOr0~9_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|response_sink_accepted~combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|next_pending_response_count~1_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|always1~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|next_pending_response_count~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~1_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~2_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~2_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|cmd_sink_ready~0_combout ;
wire \u0|mm_interconnect_0|router_001|Equal6~1_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|src18_valid~0_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|src18_valid~1_combout ;
wire \u0|mm_interconnect_0|cmd_demux|src18_valid~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_018|arb|grant[1]~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_018|packet_in_progress~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_018|packet_in_progress~q ;
wire \u0|mm_interconnect_0|cmd_mux_018|update_grant~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_018|arb|grant[0]~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_018|src_payload~0_combout ;
wire \u0|clock_sel|data_out[0]~feeder_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add0~41_sumout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add0~34 ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add0~38 ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add0~26 ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add0~29_sumout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~41_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~44_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~42_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~88_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add0~22 ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add0~1_sumout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~13_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~16_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~14_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add0~2 ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add0~5_sumout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~18_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~20_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~17_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~64_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~61_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~62_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add0~6 ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add0~13_sumout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~26_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~28_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~25_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~69_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~72_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~70_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~71_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Mux3~4_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~27_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Mux3~0_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~4_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|always4~0_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~63_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Mux4~4_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~19_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Mux4~0_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~2_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~12_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~57_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~60_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~58_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~59_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Mux5~4_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~15_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Mux5~0_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~1_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~85_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~86_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~87_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Mux7~4_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~43_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Mux7~0_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~8_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add0~30 ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add0~21_sumout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~34_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~77_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~80_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~78_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~79_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Mux6~4_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~36_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~33_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~35_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Mux6~0_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~6_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~98_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~100_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~97_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~99_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Mux11~4_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~54_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~56_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~53_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~55_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Mux11~0_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~11_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add0~42 ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add0~33_sumout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~46_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~90_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~92_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~89_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~91_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Mux10~4_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~48_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~45_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~47_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Mux10~0_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~9_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add0~14 ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add0~17_sumout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~30_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~32_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~29_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~76_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~73_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~74_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~75_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Mux2~4_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~31_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Mux2~0_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~5_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add0~18 ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add0~9_sumout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Equal2~1_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~21_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~24_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~22_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~68_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~65_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~66_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~67_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Mux1~4_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~23_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Mux1~0_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~3_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add0~37_sumout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~96_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~94_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~93_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~95_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Mux9~4_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~52_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~49_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~50_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~51_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Mux9~0_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~10_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add0~25_sumout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~38_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~37_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~40_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~84_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~81_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~82_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~83_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Mux8~4_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~39_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Mux8~0_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~7_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~1_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~4_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~7_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~5_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|LessThan0~0_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~6_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Mux0~4_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~3_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Equal2~0_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~2_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Mux0~0_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~0_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ;
wire \A_SPW_TOP|SPW|TX|last_tx_sout~q ;
wire \A_SPW_TOP|SPW|TX|last_tx_dout~q ;
wire \A_SPW_TOP|SPW|TX|tx_sout~0_combout ;
wire \A_SPW_TOP|SPW|TX|tx_sout_e~q ;
wire \db_system_spwulight_b|PB_down~0_combout ;
wire \db_system_spwulight_b|PB_down~q ;
wire [10:0] \A_SPW_TOP|rx_data|counter_wait ;
wire [9:0] \m_x|dta_timec_p ;
wire [2:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;
wire [2:0] \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;
wire [1:0] \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|aligned_address_bits ;
wire [3:0] \m_x|control_p_r ;
wire [9:0] \m_x|data ;
wire [9:0] \m_x|dta_timec ;
wire [6:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;
wire [29:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;
wire [6:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;
wire [29:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;
wire [2:0] \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;
wire [29:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;
wire [2:0] \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;
wire [29:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;
wire [5:0] \m_x|counter_neg ;
wire [29:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;
wire [5:0] \A_SPW_TOP|SPW|RX|counter_neg ;
wire [6:0] \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;
wire [29:0] \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;
wire [29:0] \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;
wire [3:0] \A_SPW_TOP|SPW|RX|control_p_r ;
wire [2:0] \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;
wire [6:0] \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;
wire [29:0] \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;
wire [29:0] \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;
wire [6:0] \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;
wire [29:0] \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;
wire [29:0] \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;
wire [2:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;
wire [2:0] \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;
wire [2:0] \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;
wire [2:0] \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;
wire [6:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;
wire [29:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;
wire [5:0] \A_SPW_TOP|rx_data|counter_reader ;
wire [5:0] \A_SPW_TOP|rx_data|counter_writer ;
wire [6:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;
wire [29:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;
wire [29:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;
wire [5:0] \A_SPW_TOP|tx_data|counter_reader ;
wire [5:0] \A_SPW_TOP|tx_data|counter_writer ;
wire [6:0] \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;
wire [29:0] \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;
wire [6:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;
wire [3:0] \A_SPW_TOP|SPW|RX|control_r ;
wire [2:0] \A_SPW_TOP|SPW|TX|fct_flag ;
wire [3:0] \m_x|control_l_r ;
wire [3:0] \m_x|control ;
wire [29:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;
wire [29:0] \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;
wire [6:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;
wire [29:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;
wire [6:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;
wire [29:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;
wire [6:0] \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;
wire [29:0] \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;
wire [29:0] \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;
wire [3:0] \A_SPW_TOP|SPW|RX|control ;
wire [6:0] \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;
wire [29:0] \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;
wire [6:0] \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;
wire [29:0] \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;
wire [6:0] \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;
wire [29:0] \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;
wire [5:0] \A_SPW_TOP|rx_data|rd_ptr ;
wire [6:0] \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;
wire [29:0] \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;
wire [29:0] \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;
wire [6:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;
wire [29:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;
wire [6:0] \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;
wire [29:0] \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;
wire [29:0] \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;
wire [29:0] \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;
wire [29:0] \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;
wire [29:0] \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;
wire [6:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;
wire [29:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;
wire [29:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;
wire [29:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;
wire [6:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;
wire [29:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;
wire [6:0] \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;
wire [29:0] \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;
wire [6:0] \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;
wire [29:0] \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;
wire [10:0] \R_400_to_2_5_10_100_200_300MHZ|counter_100 ;
wire [11:0] \A_SPW_TOP|SPW|FSM|after850ns ;
wire [2:0] \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;
wire [11:0] \A_SPW_TOP|SPW|FSM|after128us ;
wire [8:0] \A_SPW_TOP|tx_data|data_out ;
wire [152:0] \u0|mm_interconnect_0|rsp_mux_001|src_payload ;
wire [1:0] \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used ;
wire [1:0] \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used ;
wire [0:0] \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg ;
wire [29:0] \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;
wire [8:0] \u0|write_data_fifo_tx|data_out ;
wire [6:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;
wire [0:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg ;
wire [29:0] \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;
wire [1:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used ;
wire [7:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter ;
wire [3:0] \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;
wire [3:0] \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;
wire [152:0] \u0|mm_interconnect_0|cmd_mux_009|src_payload ;
wire [1:0] \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used ;
wire [7:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter ;
wire [6:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;
wire [1:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used ;
wire [3:0] \u0|hps_0|fpga_interfaces|h2f_WSTRB ;
wire [5:0] \A_SPW_TOP|rx_data|credit_counter ;
wire [1:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used ;
wire [29:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;
wire [2:0] \u0|hps_0|fpga_interfaces|h2f_AWSIZE ;
wire [1:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used ;
wire [5:0] \A_SPW_TOP|tx_data|wr_ptr ;
wire [128:0] \u0|mm_interconnect_0|cmd_mux_009|src_data ;
wire [31:0] \u0|fifo_empty_tx_status|readdata ;
wire [29:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;
wire [0:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg ;
wire [6:0] \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;
wire [7:0] \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter ;
wire [4:0] \u0|led_pio_test|data_out ;
wire [0:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg ;
wire [1:0] \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used ;
wire [3:0] \u0|hps_0|fpga_interfaces|h2f_AWLEN ;
wire [7:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter ;
wire [3:0] \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;
wire [6:0] \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;
wire [7:0] \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter ;
wire [3:0] \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;
wire [7:0] \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter ;
wire [128:0] \u0|mm_interconnect_0|cmd_mux_010|src_data ;
wire [6:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;
wire [0:0] \u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg ;
wire [29:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;
wire [29:0] \u0|hps_0|fpga_interfaces|h2f_AWADDR ;
wire [1:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used ;
wire [3:0] \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;
wire [1:0] \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter ;
wire [6:0] \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;
wire [0:0] \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg ;
wire [1:0] \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count ;
wire [0:0] \u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg ;
wire [7:0] \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter ;
wire [1:0] \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used ;
wire [152:0] \u0|mm_interconnect_0|cmd_mux_007|src_payload ;
wire [6:0] \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;
wire [1:0] \u0|mm_interconnect_0|cmd_mux_008|saved_grant ;
wire [128:0] \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;
wire [0:0] \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg ;
wire [1:0] \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter ;
wire [1:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used ;
wire [2:0] \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;
wire [7:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter ;
wire [128:0] \u0|mm_interconnect_0|rsp_mux_001|src_data ;
wire [128:0] \u0|mm_interconnect_0|rsp_mux|src_data ;
wire [1:0] \u0|mm_interconnect_0|cmd_mux_007|saved_grant ;
wire [29:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;
wire [3:0] \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;
wire [29:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;
wire [31:0] \u0|fifo_full_tx_status|readdata ;
wire [128:0] \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;
wire [1:0] \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter ;
wire [7:0] \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter ;
wire [3:0] \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;
wire [0:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg ;
wire [2:0] \u0|hps_0|fpga_interfaces|h2f_ARSIZE ;
wire [128:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;
wire [2:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;
wire [1:0] \u0|mm_interconnect_0|cmd_mux_021|saved_grant ;
wire [1:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter ;
wire [1:0] \u0|mm_interconnect_0|cmd_mux_010|saved_grant ;
wire [1:0] \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used ;
wire [6:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;
wire [128:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;
wire [7:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter ;
wire [31:0] \u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre ;
wire [29:0] \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;
wire [29:0] \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;
wire [1:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter ;
wire [0:0] \u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg ;
wire [3:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;
wire [3:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;
wire [29:0] \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;
wire [6:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;
wire [1:0] \u0|mm_interconnect_0|cmd_mux_015|saved_grant ;
wire [11:0] \u0|hps_0|fpga_interfaces|h2f_ARID ;
wire [5:0] \A_SPW_TOP|tx_data|rd_ptr ;
wire [29:0] \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;
wire [128:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;
wire [3:0] \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;
wire [1:0] \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used ;
wire [1:0] \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used ;
wire [1:0] \u0|mm_interconnect_0|cmd_mux_002|saved_grant ;
wire [1:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used ;
wire [6:0] \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;
wire [1:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used ;
wire [1:0] \u0|mm_interconnect_0|cmd_mux_001|saved_grant ;
wire [1:0] \u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg ;
wire [6:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;
wire [29:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;
wire [1:0] \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used ;
wire [6:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;
wire [0:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg ;
wire [7:0] \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus ;
wire [0:0] \u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg ;
wire [1:0] \u0|hps_0|fpga_interfaces|h2f_ARBURST ;
wire [2:0] \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;
wire [3:0] \m_x|control_r ;
wire [1:0] \u0|mm_interconnect_0|cmd_mux_017|saved_grant ;
wire [31:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|av_readdata_pre ;
wire [6:0] \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;
wire [29:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;
wire [7:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter ;
wire [0:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg ;
wire [1:0] \u0|mm_interconnect_0|cmd_mux_004|saved_grant ;
wire [2:0] \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;
wire [1:0] \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used ;
wire [6:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;
wire [6:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;
wire [29:0] \u0|hps_0|fpga_interfaces|h2f_ARADDR ;
wire [29:0] \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;
wire [128:0] \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;
wire [1:0] \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used ;
wire [3:0] \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;
wire [6:0] \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;
wire [1:0] \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used ;
wire [0:0] \u0|hps_0|fpga_interfaces|h2f_ARVALID ;
wire [6:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;
wire [31:0] \u0|mm_interconnect_0|link_start_s1_translator|av_readdata_pre ;
wire [1:0] \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used ;
wire [31:0] \u0|led_pio_test|readdata ;
wire [7:0] \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph ;
wire [0:0] \u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg ;
wire [3:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;
wire [6:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;
wire [8:0] \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|shiften ;
wire [2:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;
wire [1:0] \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter ;
wire [6:0] \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;
wire [1:0] \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter ;
wire [3:0] \u0|hps_0|fpga_interfaces|h2f_ARLEN ;
wire [0:0] \u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg ;
wire [29:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;
wire [29:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;
wire [31:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre ;
wire [0:0] \u0|hps_0|fpga_interfaces|h2f_WLAST ;
wire [31:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|av_readdata_pre ;
wire [1:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter ;
wire [6:0] \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;
wire [0:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg ;
wire [0:0] \u0|pll_0|altera_pll_i|cyclonev_pll|divclk ;
wire [29:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;
wire [1:0] \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter ;
wire [1:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used ;
wire [6:0] \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;
wire [29:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;
wire [0:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg ;
wire [7:0] \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter ;
wire [31:0] \u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre ;
wire [0:0] \u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg ;
wire [4:0] \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id ;
wire [4:0] \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id ;
wire [2:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;
wire [1:0] \u0|mm_interconnect_0|cmd_mux_011|saved_grant ;
wire [21:0] \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel ;
wire [6:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;
wire [1:0] \u0|mm_interconnect_0|cmd_mux_012|saved_grant ;
wire [29:0] \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;
wire [1:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used ;
wire [152:0] \u0|mm_interconnect_0|cmd_mux_010|src_payload ;
wire [6:0] \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;
wire [1:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter ;
wire [1:0] \u0|hps_0|fpga_interfaces|h2f_AWBURST ;
wire [1:0] \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used ;
wire [29:0] \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;
wire [7:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter ;
wire [128:0] \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;
wire [7:0] \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter ;
wire [1:0] \u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg ;
wire [3:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;
wire [1:0] \u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter ;
wire [128:0] \u0|mm_interconnect_0|cmd_mux_011|src_data ;
wire [0:0] \u0|hps_0|fpga_interfaces|h2f_RREADY ;
wire [128:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;
wire [29:0] \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;
wire [7:0] \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter ;
wire [1:0] \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used ;
wire [1:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used ;
wire [1:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter ;
wire [7:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter ;
wire [29:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;
wire [3:0] \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;
wire [1:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used ;
wire [1:0] \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used ;
wire [6:0] \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;
wire [6:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;
wire [1:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter ;
wire [2:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;
wire [6:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;
wire [1:0] \u0|mm_interconnect_0|cmd_mux_018|saved_grant ;
wire [1:0] \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter ;
wire [5:0] \A_SPW_TOP|SPW|TX|fct_counter_receive ;
wire [6:0] \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;
wire [1:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter ;
wire [6:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;
wire [1:0] \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used ;
wire [128:0] \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;
wire [7:0] \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter ;
wire [9:0] \A_SPW_TOP|SPW|RX|dta_timec_p ;
wire [128:0] \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;
wire [1:0] \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used ;
wire [0:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg ;
wire [6:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;
wire [1:0] \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter ;
wire [10:0] \R_400_to_2_5_10_100_200_300MHZ|counter ;
wire [6:0] \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;
wire [128:0] \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;
wire [3:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;
wire [29:0] \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;
wire [6:0] \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;
wire [1:0] \u0|mm_interconnect_0|cmd_mux_013|saved_grant ;
wire [128:0] \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;
wire [1:0] \u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter ;
wire [1:0] \u0|mm_interconnect_0|cmd_mux|saved_grant ;
wire [1:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used ;
wire [1:0] \u0|mm_interconnect_0|cmd_mux_006|saved_grant ;
wire [3:0] \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;
wire [128:0] \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;
wire [6:0] \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;
wire [6:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;
wire [31:0] \u0|hps_0|fpga_interfaces|h2f_WDATA ;
wire [2:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;
wire [1:0] \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used ;
wire [6:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;
wire [0:0] \u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg ;
wire [1:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used ;
wire [1:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used ;
wire [128:0] \u0|mm_interconnect_0|cmd_mux|src_data ;
wire [0:0] \u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg ;
wire [8:0] \A_SPW_TOP|SPW|TX|tx_data_in_0 ;
wire [1:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter ;
wire [29:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;
wire [3:0] \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;
wire [7:0] \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter ;
wire [1:0] \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used ;
wire [1:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter ;
wire [11:0] \u0|hps_0|fpga_interfaces|h2f_AWID ;
wire [2:0] \A_SPW_TOP|SPW|TX|fct_flag_p ;
wire [1:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used ;
wire [128:0] \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;
wire [31:0] \u0|write_data_fifo_tx|readdata ;
wire [31:0] \u0|mm_interconnect_0|clock_sel_s1_translator|av_readdata_pre ;
wire [3:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;
wire [152:0] \u0|mm_interconnect_0|cmd_mux_018|src_payload ;
wire [31:0] \u0|timecode_rx|readdata ;
wire [1:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter ;
wire [1:0] \u0|mm_interconnect_0|cmd_mux_019|saved_grant ;
wire [1:0] \u0|mm_interconnect_0|cmd_mux_003|saved_grant ;
wire [1:0] \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter ;
wire [128:0] \u0|mm_interconnect_0|cmd_mux_014|src_data ;
wire [1:0] \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used ;
wire [1:0] \u0|mm_interconnect_0|cmd_mux_020|saved_grant ;
wire [152:0] \u0|mm_interconnect_0|cmd_mux|src_payload ;
wire [7:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter ;
wire [7:0] \A_SPW_TOP|SPW|TX|tx_tcode_in ;
wire [1:0] \u0|mm_interconnect_0|cmd_mux_014|saved_grant ;
wire [1:0] \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter ;
wire [7:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter ;
wire [128:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;
wire [3:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;
wire [1:0] \u0|mm_interconnect_0|cmd_mux_016|saved_grant ;
wire [128:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;
wire [1:0] \u0|mm_interconnect_0|cmd_mux_005|saved_grant ;
wire [31:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre ;
wire [31:0] \u0|mm_interconnect_0|link_disable_s1_translator|av_readdata_pre ;
wire [6:0] \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;
wire [29:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;
wire [31:0] \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre ;
wire [1:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used ;
wire [31:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|av_readdata_pre ;
wire [29:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;
wire [31:0] \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre ;
wire [0:0] \u0|hps_0|fpga_interfaces|h2f_WVALID ;
wire [31:0] \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre ;
wire [0:0] \u0|hps_0|fpga_interfaces|h2f_AWVALID ;
wire [31:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|av_readdata_pre ;
wire [31:0] \u0|mm_interconnect_0|data_read_en_rx_s1_translator|av_readdata_pre ;
wire [6:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;
wire [0:0] \u0|pll_0|altera_pll_i|cyclonev_pll|cascade_wire ;
wire [31:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|av_readdata_pre ;
wire [31:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|av_readdata_pre ;
wire [1:0] \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fboutclk_wire ;
wire [31:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|av_readdata_pre ;
wire [1:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used ;
wire [15:0] \db_system_spwulight_b|counter ;
wire [6:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;
wire [1:0] \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count ;
wire [21:0] \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel ;
wire [6:0] \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;
wire [6:0] \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;
wire [128:0] \u0|mm_interconnect_0|cmd_mux_004|src_data ;
wire [6:0] \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;
wire [152:0] \u0|mm_interconnect_0|cmd_mux_004|src_payload ;
wire [1:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used ;
wire [6:0] \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;
wire [29:0] \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;
wire [6:0] \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;
wire [6:0] \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;
wire [6:0] \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;
wire [6:0] \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount ;
wire [31:0] \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre ;
wire [6:0] \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;
wire [152:0] \u0|mm_interconnect_0|cmd_mux_014|src_payload ;
wire [1:0] \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg ;
wire [6:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;
wire [2:0] \u0|clock_sel|data_out ;
wire [29:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;
wire [128:0] \u0|mm_interconnect_0|cmd_mux_015|src_data ;
wire [29:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;
wire [6:0] \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;
wire [152:0] \u0|mm_interconnect_0|cmd_mux_015|src_payload ;
wire [6:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;
wire [6:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;
wire [152:0] \u0|mm_interconnect_0|cmd_mux_011|src_payload ;
wire [3:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;
wire [29:0] \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;
wire [6:0] \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;
wire [1:0] \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg ;
wire [6:0] \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;
wire [1:0] \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg ;
wire [6:0] \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;
wire [128:0] \u0|mm_interconnect_0|cmd_mux_018|src_data ;
wire [8:0] \A_SPW_TOP|SPW|TX|tx_data_in ;
wire [29:0] \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;
wire [6:0] \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;
wire [128:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;
wire [128:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;
wire [8:0] \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last ;
wire [6:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;
wire [8:0] \A_SPW_TOP|SPW|RX|rx_data_flag ;
wire [6:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;
wire [3:0] \A_SPW_TOP|SPW|RX|control_l_r ;
wire [6:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;
wire [2:0] \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;
wire [6:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;
wire [7:0] \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter ;
wire [6:0] \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;
wire [6:0] \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;
wire [128:0] \u0|mm_interconnect_0|cmd_mux_007|src_data ;
wire [6:0] \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;
wire [6:0] \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;
wire [128:0] \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;
wire [6:0] \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;
wire [5:0] \A_SPW_TOP|rx_data|wr_ptr ;
wire [128:0] \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;
wire [6:0] \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;
wire [2:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;
wire [13:0] \A_SPW_TOP|SPW|TX|timecode_s ;
wire [31:0] \u0|timecode_tx_data|readdata ;
wire [0:0] \u0|hps_0|fpga_interfaces|h2f_rst_n ;
wire [6:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;
wire [0:0] \u0|hps_0|fpga_interfaces|h2f_BREADY ;
wire [0:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg ;
wire [6:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;
wire [1:0] \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used ;
wire [128:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;
wire [6:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;
wire [6:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;
wire [2:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;
wire [6:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;
wire [6:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;
wire [2:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;
wire [6:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;
wire [6:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;
wire [6:0] \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;
wire [29:0] \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;
wire [1:0] \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg ;
wire [29:0] \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst ;
wire [1:0] \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg ;
wire [29:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;
wire [5:0] \A_SPW_TOP|rx_data|credit_counter_reader ;
wire [8:0] \u0|data_flag_rx|read_mux_out ;
wire [31:0] \u0|mm_interconnect_0|write_en_tx_s1_translator|av_readdata_pre ;
wire [6:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;
wire [5:0] \A_SPW_TOP|SPW|TX|fct_counter_p ;
wire [3:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;
wire [128:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;
wire [31:0] \u0|mm_interconnect_0|auto_start_s1_translator|av_readdata_pre ;
wire [7:0] \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter ;
wire [6:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;
wire [6:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;
wire [6:0] \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;
wire [6:0] \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;
wire [6:0] \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;
wire [29:0] \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;
wire [128:0] \u0|mm_interconnect_0|cmd_mux_008|src_data ;
wire [152:0] \u0|mm_interconnect_0|cmd_mux_008|src_payload ;
wire [6:0] \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;
wire [1:0] \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg ;
wire [29:0] \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;
wire [31:0] \u0|fsm_info|readdata ;
wire [9:0] \A_SPW_TOP|SPW|RX|data ;
wire [31:0] \u0|counter_tx_fifo|readdata ;
wire [6:0] \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;
wire [31:0] \u0|counter_rx_fifo|readdata ;
wire [29:0] \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;
wire [29:0] \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;
wire [5:0] \A_SPW_TOP|rx_data|credit_counter_write ;
wire [31:0] \u0|data_flag_rx|readdata ;
wire [1:0] \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used ;
wire [31:0] \u0|data_info|readdata ;
wire [29:0] \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;
wire [31:0] \u0|timecode_ready_rx|readdata ;
wire [29:0] \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;
wire [31:0] \u0|fifo_full_rx_status|readdata ;
wire [31:0] \u0|fifo_empty_rx_status|readdata ;
wire [29:0] \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;
wire [3:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;
wire [31:0] \u0|timecode_tx_ready|readdata ;
wire [3:0] \A_SPW_TOP|SPW|TX|global_counter_transfer ;
wire [7:0] \u0|timecode_tx_data|data_out ;
wire [7:0] \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx ;
wire [29:0] \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;
wire [1:0] \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain ;
wire [1:0] \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain ;
wire [29:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;
wire [6:0] \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;
wire [29:0] \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;
wire [1:0] \u0|mm_interconnect_0|cmd_mux_009|saved_grant ;
wire [5:0] \A_SPW_TOP|tx_data|counter ;
wire [5:0] \A_SPW_TOP|rx_data|counter ;
wire [13:0] \u0|data_info|read_mux_out ;
wire [29:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;
wire [29:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;
wire [11:0] \A_SPW_TOP|SPW|FSM|after64us ;
wire [29:0] \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;
wire [31:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre ;
wire [6:0] \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;
wire [6:0] \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;
wire [29:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;
wire [6:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;
wire [6:0] \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;
wire [1:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used ;
wire [8:0] \A_SPW_TOP|rx_data|data_out ;
wire [13:0] \m_x|info ;
wire [7:0] \u0|timecode_rx|read_mux_out ;
wire [29:0] \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;
wire [1:0] \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg ;
wire [6:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;
wire [6:0] \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;
wire [1:0] \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used ;
wire [9:0] \A_SPW_TOP|SPW|RX|timecode ;
wire [9:0] \A_SPW_TOP|SPW|RX|dta_timec ;
wire [6:0] \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;
wire [29:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;
wire [1:0] \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg ;
wire [29:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;

wire [3:0] \u0|hps_0|fpga_interfaces|f2sdram_BONDING_OUT_1_bus ;
wire [31:0] \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus ;
wire [29:0] \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus ;
wire [1:0] \u0|hps_0|fpga_interfaces|hps2fpga_ARBURST_bus ;
wire [11:0] \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus ;
wire [3:0] \u0|hps_0|fpga_interfaces|hps2fpga_ARLEN_bus ;
wire [2:0] \u0|hps_0|fpga_interfaces|hps2fpga_ARSIZE_bus ;
wire [29:0] \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus ;
wire [1:0] \u0|hps_0|fpga_interfaces|hps2fpga_AWBURST_bus ;
wire [11:0] \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus ;
wire [3:0] \u0|hps_0|fpga_interfaces|hps2fpga_AWLEN_bus ;
wire [2:0] \u0|hps_0|fpga_interfaces|hps2fpga_AWSIZE_bus ;
wire [127:0] \u0|hps_0|fpga_interfaces|hps2fpga_WDATA_bus ;
wire [15:0] \u0|hps_0|fpga_interfaces|hps2fpga_WSTRB_bus ;
wire [7:0] \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_VCOPH_bus ;
wire [7:0] \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_MHI_bus ;
wire [8:0] \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|PLL_RECONFIG_SHIFTEN_bus ;

assign \u0|hps_0|fpga_interfaces|f2sdram~O_BONDING_OUT_10  = \u0|hps_0|fpga_interfaces|f2sdram_BONDING_OUT_1_bus [0];
assign \u0|hps_0|fpga_interfaces|f2sdram~O_BONDING_OUT_11  = \u0|hps_0|fpga_interfaces|f2sdram_BONDING_OUT_1_bus [1];
assign \u0|hps_0|fpga_interfaces|f2sdram~O_BONDING_OUT_12  = \u0|hps_0|fpga_interfaces|f2sdram_BONDING_OUT_1_bus [2];
assign \u0|hps_0|fpga_interfaces|f2sdram~O_BONDING_OUT_13  = \u0|hps_0|fpga_interfaces|f2sdram_BONDING_OUT_1_bus [3];

assign \u0|hps_0|fpga_interfaces|tpiu~trace_data  = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [0];
assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA1  = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [1];
assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA2  = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [2];
assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA3  = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [3];
assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA4  = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [4];
assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA5  = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [5];
assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA6  = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [6];
assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA7  = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [7];
assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA8  = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [8];
assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA9  = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [9];
assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA10  = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [10];
assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA11  = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [11];
assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA12  = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [12];
assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA13  = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [13];
assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA14  = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [14];
assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA15  = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [15];
assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA16  = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [16];
assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA17  = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [17];
assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA18  = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [18];
assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA19  = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [19];
assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA20  = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [20];
assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA21  = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [21];
assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA22  = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [22];
assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA23  = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [23];
assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA24  = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [24];
assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA25  = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [25];
assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA26  = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [26];
assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA27  = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [27];
assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA28  = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [28];
assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA29  = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [29];
assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA30  = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [30];
assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA31  = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [31];

assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [0] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [0];
assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [1] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [1];
assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [2] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [2];
assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [3] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [3];
assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [4] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [4];
assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [5] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [5];
assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [6] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [6];
assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [7] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [7];
assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [8] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [8];
assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [9] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [9];
assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [10] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [10];
assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [11] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [11];
assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [12] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [12];
assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [13] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [13];
assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [14] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [14];
assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [15] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [15];
assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [16] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [16];
assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [17] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [17];
assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [18] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [18];
assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [19] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [19];
assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [20] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [20];
assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [21] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [21];
assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [22] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [22];
assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [23] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [23];
assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [24] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [24];
assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [25] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [25];
assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [26] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [26];
assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [27] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [27];
assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [28] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [28];
assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [29] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [29];

assign \u0|hps_0|fpga_interfaces|h2f_ARBURST [0] = \u0|hps_0|fpga_interfaces|hps2fpga_ARBURST_bus [0];
assign \u0|hps_0|fpga_interfaces|h2f_ARBURST [1] = \u0|hps_0|fpga_interfaces|hps2fpga_ARBURST_bus [1];

assign \u0|hps_0|fpga_interfaces|h2f_ARID [0] = \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus [0];
assign \u0|hps_0|fpga_interfaces|h2f_ARID [1] = \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus [1];
assign \u0|hps_0|fpga_interfaces|h2f_ARID [2] = \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus [2];
assign \u0|hps_0|fpga_interfaces|h2f_ARID [3] = \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus [3];
assign \u0|hps_0|fpga_interfaces|h2f_ARID [4] = \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus [4];
assign \u0|hps_0|fpga_interfaces|h2f_ARID [5] = \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus [5];
assign \u0|hps_0|fpga_interfaces|h2f_ARID [6] = \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus [6];
assign \u0|hps_0|fpga_interfaces|h2f_ARID [7] = \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus [7];
assign \u0|hps_0|fpga_interfaces|h2f_ARID [8] = \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus [8];
assign \u0|hps_0|fpga_interfaces|h2f_ARID [9] = \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus [9];
assign \u0|hps_0|fpga_interfaces|h2f_ARID [10] = \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus [10];
assign \u0|hps_0|fpga_interfaces|h2f_ARID [11] = \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus [11];

assign \u0|hps_0|fpga_interfaces|h2f_ARLEN [0] = \u0|hps_0|fpga_interfaces|hps2fpga_ARLEN_bus [0];
assign \u0|hps_0|fpga_interfaces|h2f_ARLEN [1] = \u0|hps_0|fpga_interfaces|hps2fpga_ARLEN_bus [1];
assign \u0|hps_0|fpga_interfaces|h2f_ARLEN [2] = \u0|hps_0|fpga_interfaces|hps2fpga_ARLEN_bus [2];
assign \u0|hps_0|fpga_interfaces|h2f_ARLEN [3] = \u0|hps_0|fpga_interfaces|hps2fpga_ARLEN_bus [3];

assign \u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] = \u0|hps_0|fpga_interfaces|hps2fpga_ARSIZE_bus [0];
assign \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] = \u0|hps_0|fpga_interfaces|hps2fpga_ARSIZE_bus [1];
assign \u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] = \u0|hps_0|fpga_interfaces|hps2fpga_ARSIZE_bus [2];

assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [0] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [0];
assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [1] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [1];
assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [2] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [2];
assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [3] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [3];
assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [4] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [4];
assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [5] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [5];
assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [6] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [6];
assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [7] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [7];
assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [8] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [8];
assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [9] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [9];
assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [10] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [10];
assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [11] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [11];
assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [12] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [12];
assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [13] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [13];
assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [14] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [14];
assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [15] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [15];
assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [16] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [16];
assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [17] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [17];
assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [18] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [18];
assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [19] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [19];

assign \u0|hps_0|fpga_interfaces|h2f_AWBURST [0] = \u0|hps_0|fpga_interfaces|hps2fpga_AWBURST_bus [0];
assign \u0|hps_0|fpga_interfaces|h2f_AWBURST [1] = \u0|hps_0|fpga_interfaces|hps2fpga_AWBURST_bus [1];

assign \u0|hps_0|fpga_interfaces|h2f_AWID [0] = \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus [0];
assign \u0|hps_0|fpga_interfaces|h2f_AWID [1] = \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus [1];
assign \u0|hps_0|fpga_interfaces|h2f_AWID [2] = \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus [2];
assign \u0|hps_0|fpga_interfaces|h2f_AWID [3] = \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus [3];
assign \u0|hps_0|fpga_interfaces|h2f_AWID [4] = \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus [4];
assign \u0|hps_0|fpga_interfaces|h2f_AWID [5] = \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus [5];
assign \u0|hps_0|fpga_interfaces|h2f_AWID [6] = \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus [6];
assign \u0|hps_0|fpga_interfaces|h2f_AWID [7] = \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus [7];
assign \u0|hps_0|fpga_interfaces|h2f_AWID [8] = \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus [8];
assign \u0|hps_0|fpga_interfaces|h2f_AWID [9] = \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus [9];
assign \u0|hps_0|fpga_interfaces|h2f_AWID [10] = \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus [10];
assign \u0|hps_0|fpga_interfaces|h2f_AWID [11] = \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus [11];

assign \u0|hps_0|fpga_interfaces|h2f_AWLEN [0] = \u0|hps_0|fpga_interfaces|hps2fpga_AWLEN_bus [0];
assign \u0|hps_0|fpga_interfaces|h2f_AWLEN [1] = \u0|hps_0|fpga_interfaces|hps2fpga_AWLEN_bus [1];
assign \u0|hps_0|fpga_interfaces|h2f_AWLEN [2] = \u0|hps_0|fpga_interfaces|hps2fpga_AWLEN_bus [2];
assign \u0|hps_0|fpga_interfaces|h2f_AWLEN [3] = \u0|hps_0|fpga_interfaces|hps2fpga_AWLEN_bus [3];

assign \u0|hps_0|fpga_interfaces|h2f_AWSIZE [0] = \u0|hps_0|fpga_interfaces|hps2fpga_AWSIZE_bus [0];
assign \u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] = \u0|hps_0|fpga_interfaces|hps2fpga_AWSIZE_bus [1];
assign \u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] = \u0|hps_0|fpga_interfaces|hps2fpga_AWSIZE_bus [2];

assign \u0|hps_0|fpga_interfaces|h2f_WDATA [0] = \u0|hps_0|fpga_interfaces|hps2fpga_WDATA_bus [0];
assign \u0|hps_0|fpga_interfaces|h2f_WDATA [1] = \u0|hps_0|fpga_interfaces|hps2fpga_WDATA_bus [1];
assign \u0|hps_0|fpga_interfaces|h2f_WDATA [2] = \u0|hps_0|fpga_interfaces|hps2fpga_WDATA_bus [2];
assign \u0|hps_0|fpga_interfaces|h2f_WDATA [3] = \u0|hps_0|fpga_interfaces|hps2fpga_WDATA_bus [3];
assign \u0|hps_0|fpga_interfaces|h2f_WDATA [4] = \u0|hps_0|fpga_interfaces|hps2fpga_WDATA_bus [4];
assign \u0|hps_0|fpga_interfaces|h2f_WDATA [5] = \u0|hps_0|fpga_interfaces|hps2fpga_WDATA_bus [5];
assign \u0|hps_0|fpga_interfaces|h2f_WDATA [6] = \u0|hps_0|fpga_interfaces|hps2fpga_WDATA_bus [6];
assign \u0|hps_0|fpga_interfaces|h2f_WDATA [7] = \u0|hps_0|fpga_interfaces|hps2fpga_WDATA_bus [7];
assign \u0|hps_0|fpga_interfaces|h2f_WDATA [8] = \u0|hps_0|fpga_interfaces|hps2fpga_WDATA_bus [8];

assign \u0|hps_0|fpga_interfaces|h2f_WSTRB [0] = \u0|hps_0|fpga_interfaces|hps2fpga_WSTRB_bus [0];
assign \u0|hps_0|fpga_interfaces|h2f_WSTRB [1] = \u0|hps_0|fpga_interfaces|hps2fpga_WSTRB_bus [1];
assign \u0|hps_0|fpga_interfaces|h2f_WSTRB [2] = \u0|hps_0|fpga_interfaces|hps2fpga_WSTRB_bus [2];
assign \u0|hps_0|fpga_interfaces|h2f_WSTRB [3] = \u0|hps_0|fpga_interfaces|hps2fpga_WSTRB_bus [3];

assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [0] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_VCOPH_bus [0];
assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [1] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_VCOPH_bus [1];
assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [2] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_VCOPH_bus [2];
assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [3] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_VCOPH_bus [3];
assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [4] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_VCOPH_bus [4];
assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [5] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_VCOPH_bus [5];
assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [6] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_VCOPH_bus [6];
assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [7] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_VCOPH_bus [7];

assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [0] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_MHI_bus [0];
assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [1] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_MHI_bus [1];
assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [2] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_MHI_bus [2];
assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [3] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_MHI_bus [3];
assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [4] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_MHI_bus [4];
assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [5] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_MHI_bus [5];
assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [6] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_MHI_bus [6];
assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [7] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_MHI_bus [7];

assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|shiften [2] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|PLL_RECONFIG_SHIFTEN_bus [2];

// Location: IOOBUF_X53_Y0_N36
cyclonev_io_obuf \sout_a~output (
        .i(\A_SPW_TOP|SPW|TX|tx_sout_e~q ),
        .oe(vcc),
        .dynamicterminationcontrol(gnd),
        .seriesterminationcontrol(16'b0000000000000000),
        .parallelterminationcontrol(16'b0000000000000000),
        .devoe(devoe),
        .o(sout_a),
        .obar(\sout_a(n) ));
// synopsys translate_off
defparam \sout_a~output .bus_hold = "false";
defparam \sout_a~output .open_drain_output = "false";
defparam \sout_a~output .shift_series_termination_control = "false";
// synopsys translate_on

// Location: IOOBUF_X68_Y10_N96
cyclonev_io_obuf \LED[5]~output (
        .i(\db_system_spwulight_b|PB_down~q ),
        .oe(vcc),
        .dynamicterminationcontrol(gnd),
        .seriesterminationcontrol(16'b0000000000000000),
        .parallelterminationcontrol(16'b0000000000000000),
        .devoe(devoe),
        .o(LED[5]),
        .obar());
// synopsys translate_off
defparam \LED[5]~output .bus_hold = "false";
defparam \LED[5]~output .open_drain_output = "false";
defparam \LED[5]~output .shift_series_termination_control = "false";
// synopsys translate_on

// Location: IOOBUF_X68_Y13_N56
cyclonev_io_obuf \LED[7]~output (
        .i(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock ),
        .oe(vcc),
        .dynamicterminationcontrol(gnd),
        .seriesterminationcontrol(16'b0000000000000000),
        .parallelterminationcontrol(16'b0000000000000000),
        .devoe(devoe),
        .o(LED[7]),
        .obar());
// synopsys translate_off
defparam \LED[7]~output .bus_hold = "false";
defparam \LED[7]~output .open_drain_output = "false";
defparam \LED[7]~output .shift_series_termination_control = "false";
// synopsys translate_on

// Location: IOOBUF_X65_Y0_N36
cyclonev_io_obuf \dout_a~output (
        .i(\A_SPW_TOP|SPW|TX|tx_dout_e~q ),
        .oe(vcc),
        .dynamicterminationcontrol(gnd),
        .seriesterminationcontrol(16'b0000000000000000),
        .parallelterminationcontrol(16'b0000000000000000),
        .devoe(devoe),
        .o(dout_a),
        .obar(\dout_a(n) ));
// synopsys translate_off
defparam \dout_a~output .bus_hold = "false";
defparam \dout_a~output .open_drain_output = "false";
defparam \dout_a~output .shift_series_termination_control = "false";
// synopsys translate_on

// Location: IOOBUF_X68_Y12_N22
cyclonev_io_obuf \LED[0]~output (
        .i(\u0|led_pio_test|data_out [0]),
        .oe(vcc),
        .dynamicterminationcontrol(gnd),
        .seriesterminationcontrol(16'b0000000000000000),
        .parallelterminationcontrol(16'b0000000000000000),
        .devoe(devoe),
        .o(LED[0]),
        .obar());
// synopsys translate_off
defparam \LED[0]~output .bus_hold = "false";
defparam \LED[0]~output .open_drain_output = "false";
defparam \LED[0]~output .shift_series_termination_control = "false";
// synopsys translate_on

// Location: IOOBUF_X68_Y13_N39
cyclonev_io_obuf \LED[1]~output (
        .i(\u0|led_pio_test|data_out [1]),
        .oe(vcc),
        .dynamicterminationcontrol(gnd),
        .seriesterminationcontrol(16'b0000000000000000),
        .parallelterminationcontrol(16'b0000000000000000),
        .devoe(devoe),
        .o(LED[1]),
        .obar());
// synopsys translate_off
defparam \LED[1]~output .bus_hold = "false";
defparam \LED[1]~output .open_drain_output = "false";
defparam \LED[1]~output .shift_series_termination_control = "false";
// synopsys translate_on

// Location: IOOBUF_X68_Y13_N5
cyclonev_io_obuf \LED[2]~output (
        .i(\u0|led_pio_test|data_out [2]),
        .oe(vcc),
        .dynamicterminationcontrol(gnd),
        .seriesterminationcontrol(16'b0000000000000000),
        .parallelterminationcontrol(16'b0000000000000000),
        .devoe(devoe),
        .o(LED[2]),
        .obar());
// synopsys translate_off
defparam \LED[2]~output .bus_hold = "false";
defparam \LED[2]~output .open_drain_output = "false";
defparam \LED[2]~output .shift_series_termination_control = "false";
// synopsys translate_on

// Location: IOOBUF_X68_Y13_N22
cyclonev_io_obuf \LED[3]~output (
        .i(\u0|led_pio_test|data_out [3]),
        .oe(vcc),
        .dynamicterminationcontrol(gnd),
        .seriesterminationcontrol(16'b0000000000000000),
        .parallelterminationcontrol(16'b0000000000000000),
        .devoe(devoe),
        .o(LED[3]),
        .obar());
// synopsys translate_off
defparam \LED[3]~output .bus_hold = "false";
defparam \LED[3]~output .open_drain_output = "false";
defparam \LED[3]~output .shift_series_termination_control = "false";
// synopsys translate_on

// Location: IOOBUF_X68_Y10_N79
cyclonev_io_obuf \LED[4]~output (
        .i(\u0|led_pio_test|data_out [4]),
        .oe(vcc),
        .dynamicterminationcontrol(gnd),
        .seriesterminationcontrol(16'b0000000000000000),
        .parallelterminationcontrol(16'b0000000000000000),
        .devoe(devoe),
        .o(LED[4]),
        .obar());
// synopsys translate_off
defparam \LED[4]~output .bus_hold = "false";
defparam \LED[4]~output .open_drain_output = "false";
defparam \LED[4]~output .shift_series_termination_control = "false";
// synopsys translate_on

// Location: IOOBUF_X68_Y12_N5
cyclonev_io_obuf \LED[6]~output (
        .i(gnd),
        .oe(vcc),
        .dynamicterminationcontrol(gnd),
        .seriesterminationcontrol(16'b0000000000000000),
        .parallelterminationcontrol(16'b0000000000000000),
        .devoe(devoe),
        .o(LED[6]),
        .obar());
// synopsys translate_off
defparam \LED[6]~output .bus_hold = "false";
defparam \LED[6]~output .open_drain_output = "false";
defparam \LED[6]~output .shift_series_termination_control = "false";
// synopsys translate_on

// Location: IOIBUF_X38_Y0_N1
cyclonev_io_ibuf \FPGA_CLK1_50~input (
        .i(FPGA_CLK1_50),
        .ibar(gnd),
        .dynamicterminationcontrol(gnd),
        .o(\FPGA_CLK1_50~input_o ));
// synopsys translate_off
defparam \FPGA_CLK1_50~input .bus_hold = "false";
defparam \FPGA_CLK1_50~input .simulate_z_as = "z";
// synopsys translate_on

// Location: PLLREFCLKSELECT_X68_Y7_N0
cyclonev_pll_refclk_select \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT (
        .adjpllin(gnd),
        .cclk(gnd),
        .coreclkin(gnd),
        .extswitch(gnd),
        .iqtxrxclkin(gnd),
        .plliqclkin(gnd),
        .rxiqclkin(gnd),
        .clkin({gnd,gnd,gnd,\FPGA_CLK1_50~input_o }),
        .refiqclk(2'b00),
        .clk0bad(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|clk0bad ),
        .clk1bad(),
        .clkout(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|refclk_select_clkout_wire ),
        .extswitchbuf(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|refclk_select_extswitchbuf_wire ),
        .pllclksel());
// synopsys translate_off
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT .pll_auto_clk_sw_en = "true";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT .pll_clk_loss_edge = "both_edges";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT .pll_clk_loss_sw_en = "true";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT .pll_clk_sw_dly = 0;
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT .pll_clkin_0_src = "clk_0";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT .pll_clkin_1_src = "clk_1";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT .pll_manu_clk_sw_en = "false";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT .pll_sw_refclk_src = "clk_0";
// synopsys translate_on

// Location: CLKCTRL_G5
cyclonev_clkena \FPGA_CLK1_50~inputCLKENA0 (
        .inclk(\FPGA_CLK1_50~input_o ),
        .ena(vcc),
        .outclk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .enaout());
// synopsys translate_off
defparam \FPGA_CLK1_50~inputCLKENA0 .clock_type = "global clock";
defparam \FPGA_CLK1_50~inputCLKENA0 .disable_mode = "low";
defparam \FPGA_CLK1_50~inputCLKENA0 .ena_register_mode = "always enabled";
defparam \FPGA_CLK1_50~inputCLKENA0 .ena_register_power_up = "high";
defparam \FPGA_CLK1_50~inputCLKENA0 .test_syn = "high";
// synopsys translate_on

// Location: IOIBUF_X46_Y0_N52
cyclonev_io_ibuf \KEY[1]~input (
        .i(KEY[1]),
        .ibar(gnd),
        .dynamicterminationcontrol(gnd),
        .o(\KEY[1]~input_o ));
// synopsys translate_off
defparam \KEY[1]~input .bus_hold = "false";
defparam \KEY[1]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: LABCELL_X46_Y1_N0
cyclonev_lcell_comb \db_system_spwulight_b|Add0~61 (
// Equation(s):
// \db_system_spwulight_b|Add0~61_sumout  = SUM(( \db_system_spwulight_b|counter [0] ) + ( VCC ) + ( !VCC ))
// \db_system_spwulight_b|Add0~62  = CARRY(( \db_system_spwulight_b|counter [0] ) + ( VCC ) + ( !VCC ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\db_system_spwulight_b|counter [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(),
        .sumout(\db_system_spwulight_b|Add0~61_sumout ),
        .cout(\db_system_spwulight_b|Add0~62 ),
        .shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|Add0~61 .extended_lut = "off";
defparam \db_system_spwulight_b|Add0~61 .lut_mask = 64'h0000000000000F0F;
defparam \db_system_spwulight_b|Add0~61 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y1_N54
cyclonev_lcell_comb \db_system_spwulight_b|counter~15 (
// Equation(s):
// \db_system_spwulight_b|counter~15_combout  = ( \db_system_spwulight_b|counter [0] & ( \db_system_spwulight_b|Add0~61_sumout  & ( !\KEY[1]~input_o  ) ) ) # ( !\db_system_spwulight_b|counter [0] & ( \db_system_spwulight_b|Add0~61_sumout  & ( 
// (\db_system_spwulight_b|LessThan0~2_combout  & (!\db_system_spwulight_b|counter [15] & (!\KEY[1]~input_o  & !\db_system_spwulight_b|LessThan0~1_combout ))) ) ) ) # ( \db_system_spwulight_b|counter [0] & ( !\db_system_spwulight_b|Add0~61_sumout  & ( 
// (!\KEY[1]~input_o  & ((!\db_system_spwulight_b|LessThan0~2_combout ) # ((\db_system_spwulight_b|LessThan0~1_combout ) # (\db_system_spwulight_b|counter [15])))) ) ) )

        .dataa(!\db_system_spwulight_b|LessThan0~2_combout ),
        .datab(!\db_system_spwulight_b|counter [15]),
        .datac(!\KEY[1]~input_o ),
        .datad(!\db_system_spwulight_b|LessThan0~1_combout ),
        .datae(!\db_system_spwulight_b|counter [0]),
        .dataf(!\db_system_spwulight_b|Add0~61_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\db_system_spwulight_b|counter~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|counter~15 .extended_lut = "off";
defparam \db_system_spwulight_b|counter~15 .lut_mask = 64'h0000B0F04000F0F0;
defparam \db_system_spwulight_b|counter~15 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y1_N56
dffeas \db_system_spwulight_b|counter[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\db_system_spwulight_b|counter~15_combout ),
        .asdata(vcc),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\db_system_spwulight_b|counter [0]),
        .prn(vcc));
// synopsys translate_off
defparam \db_system_spwulight_b|counter[0] .is_wysiwyg = "true";
defparam \db_system_spwulight_b|counter[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y1_N3
cyclonev_lcell_comb \db_system_spwulight_b|Add0~57 (
// Equation(s):
// \db_system_spwulight_b|Add0~57_sumout  = SUM(( \db_system_spwulight_b|counter [1] ) + ( GND ) + ( \db_system_spwulight_b|Add0~62  ))
// \db_system_spwulight_b|Add0~58  = CARRY(( \db_system_spwulight_b|counter [1] ) + ( GND ) + ( \db_system_spwulight_b|Add0~62  ))

        .dataa(!\db_system_spwulight_b|counter [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\db_system_spwulight_b|Add0~62 ),
        .sharein(gnd),
        .combout(),
        .sumout(\db_system_spwulight_b|Add0~57_sumout ),
        .cout(\db_system_spwulight_b|Add0~58 ),
        .shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|Add0~57 .extended_lut = "off";
defparam \db_system_spwulight_b|Add0~57 .lut_mask = 64'h0000FFFF00005555;
defparam \db_system_spwulight_b|Add0~57 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y1_N51
cyclonev_lcell_comb \db_system_spwulight_b|counter~14 (
// Equation(s):
// \db_system_spwulight_b|counter~14_combout  = ( \db_system_spwulight_b|counter [1] & ( \db_system_spwulight_b|Add0~57_sumout  & ( !\KEY[1]~input_o  ) ) ) # ( !\db_system_spwulight_b|counter [1] & ( \db_system_spwulight_b|Add0~57_sumout  & ( 
// (\db_system_spwulight_b|LessThan0~2_combout  & (!\db_system_spwulight_b|counter [15] & (!\db_system_spwulight_b|LessThan0~1_combout  & !\KEY[1]~input_o ))) ) ) ) # ( \db_system_spwulight_b|counter [1] & ( !\db_system_spwulight_b|Add0~57_sumout  & ( 
// (!\KEY[1]~input_o  & ((!\db_system_spwulight_b|LessThan0~2_combout ) # ((\db_system_spwulight_b|LessThan0~1_combout ) # (\db_system_spwulight_b|counter [15])))) ) ) )

        .dataa(!\db_system_spwulight_b|LessThan0~2_combout ),
        .datab(!\db_system_spwulight_b|counter [15]),
        .datac(!\db_system_spwulight_b|LessThan0~1_combout ),
        .datad(!\KEY[1]~input_o ),
        .datae(!\db_system_spwulight_b|counter [1]),
        .dataf(!\db_system_spwulight_b|Add0~57_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\db_system_spwulight_b|counter~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|counter~14 .extended_lut = "off";
defparam \db_system_spwulight_b|counter~14 .lut_mask = 64'h0000BF004000FF00;
defparam \db_system_spwulight_b|counter~14 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y1_N53
dffeas \db_system_spwulight_b|counter[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\db_system_spwulight_b|counter~14_combout ),
        .asdata(vcc),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\db_system_spwulight_b|counter [1]),
        .prn(vcc));
// synopsys translate_off
defparam \db_system_spwulight_b|counter[1] .is_wysiwyg = "true";
defparam \db_system_spwulight_b|counter[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y1_N6
cyclonev_lcell_comb \db_system_spwulight_b|Add0~53 (
// Equation(s):
// \db_system_spwulight_b|Add0~53_sumout  = SUM(( \db_system_spwulight_b|counter [2] ) + ( GND ) + ( \db_system_spwulight_b|Add0~58  ))
// \db_system_spwulight_b|Add0~54  = CARRY(( \db_system_spwulight_b|counter [2] ) + ( GND ) + ( \db_system_spwulight_b|Add0~58  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\db_system_spwulight_b|counter [2]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\db_system_spwulight_b|Add0~58 ),
        .sharein(gnd),
        .combout(),
        .sumout(\db_system_spwulight_b|Add0~53_sumout ),
        .cout(\db_system_spwulight_b|Add0~54 ),
        .shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|Add0~53 .extended_lut = "off";
defparam \db_system_spwulight_b|Add0~53 .lut_mask = 64'h0000FFFF00000F0F;
defparam \db_system_spwulight_b|Add0~53 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y1_N48
cyclonev_lcell_comb \db_system_spwulight_b|counter~13 (
// Equation(s):
// \db_system_spwulight_b|counter~13_combout  = ( \db_system_spwulight_b|counter [2] & ( \db_system_spwulight_b|Add0~53_sumout  & ( !\KEY[1]~input_o  ) ) ) # ( !\db_system_spwulight_b|counter [2] & ( \db_system_spwulight_b|Add0~53_sumout  & ( 
// (\db_system_spwulight_b|LessThan0~2_combout  & (!\db_system_spwulight_b|counter [15] & (!\KEY[1]~input_o  & !\db_system_spwulight_b|LessThan0~1_combout ))) ) ) ) # ( \db_system_spwulight_b|counter [2] & ( !\db_system_spwulight_b|Add0~53_sumout  & ( 
// (!\KEY[1]~input_o  & ((!\db_system_spwulight_b|LessThan0~2_combout ) # ((\db_system_spwulight_b|LessThan0~1_combout ) # (\db_system_spwulight_b|counter [15])))) ) ) )

        .dataa(!\db_system_spwulight_b|LessThan0~2_combout ),
        .datab(!\db_system_spwulight_b|counter [15]),
        .datac(!\KEY[1]~input_o ),
        .datad(!\db_system_spwulight_b|LessThan0~1_combout ),
        .datae(!\db_system_spwulight_b|counter [2]),
        .dataf(!\db_system_spwulight_b|Add0~53_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\db_system_spwulight_b|counter~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|counter~13 .extended_lut = "off";
defparam \db_system_spwulight_b|counter~13 .lut_mask = 64'h0000B0F04000F0F0;
defparam \db_system_spwulight_b|counter~13 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y1_N50
dffeas \db_system_spwulight_b|counter[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\db_system_spwulight_b|counter~13_combout ),
        .asdata(vcc),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\db_system_spwulight_b|counter [2]),
        .prn(vcc));
// synopsys translate_off
defparam \db_system_spwulight_b|counter[2] .is_wysiwyg = "true";
defparam \db_system_spwulight_b|counter[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y1_N9
cyclonev_lcell_comb \db_system_spwulight_b|Add0~49 (
// Equation(s):
// \db_system_spwulight_b|Add0~49_sumout  = SUM(( \db_system_spwulight_b|counter [3] ) + ( GND ) + ( \db_system_spwulight_b|Add0~54  ))
// \db_system_spwulight_b|Add0~50  = CARRY(( \db_system_spwulight_b|counter [3] ) + ( GND ) + ( \db_system_spwulight_b|Add0~54  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\db_system_spwulight_b|counter [3]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\db_system_spwulight_b|Add0~54 ),
        .sharein(gnd),
        .combout(),
        .sumout(\db_system_spwulight_b|Add0~49_sumout ),
        .cout(\db_system_spwulight_b|Add0~50 ),
        .shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|Add0~49 .extended_lut = "off";
defparam \db_system_spwulight_b|Add0~49 .lut_mask = 64'h0000FFFF00000F0F;
defparam \db_system_spwulight_b|Add0~49 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y1_N57
cyclonev_lcell_comb \db_system_spwulight_b|counter~12 (
// Equation(s):
// \db_system_spwulight_b|counter~12_combout  = ( \db_system_spwulight_b|counter [3] & ( \db_system_spwulight_b|Add0~49_sumout  & ( !\KEY[1]~input_o  ) ) ) # ( !\db_system_spwulight_b|counter [3] & ( \db_system_spwulight_b|Add0~49_sumout  & ( 
// (\db_system_spwulight_b|LessThan0~2_combout  & (!\db_system_spwulight_b|counter [15] & (!\db_system_spwulight_b|LessThan0~1_combout  & !\KEY[1]~input_o ))) ) ) ) # ( \db_system_spwulight_b|counter [3] & ( !\db_system_spwulight_b|Add0~49_sumout  & ( 
// (!\KEY[1]~input_o  & ((!\db_system_spwulight_b|LessThan0~2_combout ) # ((\db_system_spwulight_b|LessThan0~1_combout ) # (\db_system_spwulight_b|counter [15])))) ) ) )

        .dataa(!\db_system_spwulight_b|LessThan0~2_combout ),
        .datab(!\db_system_spwulight_b|counter [15]),
        .datac(!\db_system_spwulight_b|LessThan0~1_combout ),
        .datad(!\KEY[1]~input_o ),
        .datae(!\db_system_spwulight_b|counter [3]),
        .dataf(!\db_system_spwulight_b|Add0~49_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\db_system_spwulight_b|counter~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|counter~12 .extended_lut = "off";
defparam \db_system_spwulight_b|counter~12 .lut_mask = 64'h0000BF004000FF00;
defparam \db_system_spwulight_b|counter~12 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y1_N59
dffeas \db_system_spwulight_b|counter[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\db_system_spwulight_b|counter~12_combout ),
        .asdata(vcc),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\db_system_spwulight_b|counter [3]),
        .prn(vcc));
// synopsys translate_off
defparam \db_system_spwulight_b|counter[3] .is_wysiwyg = "true";
defparam \db_system_spwulight_b|counter[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y1_N12
cyclonev_lcell_comb \db_system_spwulight_b|Add0~37 (
// Equation(s):
// \db_system_spwulight_b|Add0~37_sumout  = SUM(( \db_system_spwulight_b|counter [4] ) + ( GND ) + ( \db_system_spwulight_b|Add0~50  ))
// \db_system_spwulight_b|Add0~38  = CARRY(( \db_system_spwulight_b|counter [4] ) + ( GND ) + ( \db_system_spwulight_b|Add0~50  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\db_system_spwulight_b|counter [4]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\db_system_spwulight_b|Add0~50 ),
        .sharein(gnd),
        .combout(),
        .sumout(\db_system_spwulight_b|Add0~37_sumout ),
        .cout(\db_system_spwulight_b|Add0~38 ),
        .shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|Add0~37 .extended_lut = "off";
defparam \db_system_spwulight_b|Add0~37 .lut_mask = 64'h0000FFFF000000FF;
defparam \db_system_spwulight_b|Add0~37 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y1_N15
cyclonev_lcell_comb \db_system_spwulight_b|Add0~41 (
// Equation(s):
// \db_system_spwulight_b|Add0~41_sumout  = SUM(( \db_system_spwulight_b|counter [5] ) + ( GND ) + ( \db_system_spwulight_b|Add0~38  ))
// \db_system_spwulight_b|Add0~42  = CARRY(( \db_system_spwulight_b|counter [5] ) + ( GND ) + ( \db_system_spwulight_b|Add0~38  ))

        .dataa(!\db_system_spwulight_b|counter [5]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\db_system_spwulight_b|Add0~38 ),
        .sharein(gnd),
        .combout(),
        .sumout(\db_system_spwulight_b|Add0~41_sumout ),
        .cout(\db_system_spwulight_b|Add0~42 ),
        .shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|Add0~41 .extended_lut = "off";
defparam \db_system_spwulight_b|Add0~41 .lut_mask = 64'h0000FFFF00005555;
defparam \db_system_spwulight_b|Add0~41 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y1_N39
cyclonev_lcell_comb \db_system_spwulight_b|counter~10 (
// Equation(s):
// \db_system_spwulight_b|counter~10_combout  = ( \db_system_spwulight_b|counter [5] & ( \db_system_spwulight_b|Add0~41_sumout  & ( !\KEY[1]~input_o  ) ) ) # ( !\db_system_spwulight_b|counter [5] & ( \db_system_spwulight_b|Add0~41_sumout  & ( 
// (!\db_system_spwulight_b|LessThan0~1_combout  & (!\KEY[1]~input_o  & (\db_system_spwulight_b|LessThan0~2_combout  & !\db_system_spwulight_b|counter [15]))) ) ) ) # ( \db_system_spwulight_b|counter [5] & ( !\db_system_spwulight_b|Add0~41_sumout  & ( 
// (!\KEY[1]~input_o  & (((!\db_system_spwulight_b|LessThan0~2_combout ) # (\db_system_spwulight_b|counter [15])) # (\db_system_spwulight_b|LessThan0~1_combout ))) ) ) )

        .dataa(!\db_system_spwulight_b|LessThan0~1_combout ),
        .datab(!\KEY[1]~input_o ),
        .datac(!\db_system_spwulight_b|LessThan0~2_combout ),
        .datad(!\db_system_spwulight_b|counter [15]),
        .datae(!\db_system_spwulight_b|counter [5]),
        .dataf(!\db_system_spwulight_b|Add0~41_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\db_system_spwulight_b|counter~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|counter~10 .extended_lut = "off";
defparam \db_system_spwulight_b|counter~10 .lut_mask = 64'h0000C4CC0800CCCC;
defparam \db_system_spwulight_b|counter~10 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y1_N41
dffeas \db_system_spwulight_b|counter[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\db_system_spwulight_b|counter~10_combout ),
        .asdata(vcc),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\db_system_spwulight_b|counter [5]),
        .prn(vcc));
// synopsys translate_off
defparam \db_system_spwulight_b|counter[5] .is_wysiwyg = "true";
defparam \db_system_spwulight_b|counter[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y1_N18
cyclonev_lcell_comb \db_system_spwulight_b|Add0~45 (
// Equation(s):
// \db_system_spwulight_b|Add0~45_sumout  = SUM(( \db_system_spwulight_b|counter [6] ) + ( GND ) + ( \db_system_spwulight_b|Add0~42  ))
// \db_system_spwulight_b|Add0~46  = CARRY(( \db_system_spwulight_b|counter [6] ) + ( GND ) + ( \db_system_spwulight_b|Add0~42  ))

        .dataa(gnd),
        .datab(!\db_system_spwulight_b|counter [6]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\db_system_spwulight_b|Add0~42 ),
        .sharein(gnd),
        .combout(),
        .sumout(\db_system_spwulight_b|Add0~45_sumout ),
        .cout(\db_system_spwulight_b|Add0~46 ),
        .shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|Add0~45 .extended_lut = "off";
defparam \db_system_spwulight_b|Add0~45 .lut_mask = 64'h0000FFFF00003333;
defparam \db_system_spwulight_b|Add0~45 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y1_N18
cyclonev_lcell_comb \db_system_spwulight_b|counter~11 (
// Equation(s):
// \db_system_spwulight_b|counter~11_combout  = ( \db_system_spwulight_b|counter [6] & ( \db_system_spwulight_b|LessThan0~2_combout  & ( (!\KEY[1]~input_o  & (((\db_system_spwulight_b|counter [15]) # (\db_system_spwulight_b|Add0~45_sumout )) # 
// (\db_system_spwulight_b|LessThan0~1_combout ))) ) ) ) # ( !\db_system_spwulight_b|counter [6] & ( \db_system_spwulight_b|LessThan0~2_combout  & ( (!\db_system_spwulight_b|LessThan0~1_combout  & (\db_system_spwulight_b|Add0~45_sumout  & 
// (!\db_system_spwulight_b|counter [15] & !\KEY[1]~input_o ))) ) ) ) # ( \db_system_spwulight_b|counter [6] & ( !\db_system_spwulight_b|LessThan0~2_combout  & ( !\KEY[1]~input_o  ) ) )

        .dataa(!\db_system_spwulight_b|LessThan0~1_combout ),
        .datab(!\db_system_spwulight_b|Add0~45_sumout ),
        .datac(!\db_system_spwulight_b|counter [15]),
        .datad(!\KEY[1]~input_o ),
        .datae(!\db_system_spwulight_b|counter [6]),
        .dataf(!\db_system_spwulight_b|LessThan0~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\db_system_spwulight_b|counter~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|counter~11 .extended_lut = "off";
defparam \db_system_spwulight_b|counter~11 .lut_mask = 64'h0000FF0020007F00;
defparam \db_system_spwulight_b|counter~11 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y1_N20
dffeas \db_system_spwulight_b|counter[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\db_system_spwulight_b|counter~11_combout ),
        .asdata(vcc),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\db_system_spwulight_b|counter [6]),
        .prn(vcc));
// synopsys translate_off
defparam \db_system_spwulight_b|counter[6] .is_wysiwyg = "true";
defparam \db_system_spwulight_b|counter[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y1_N21
cyclonev_lcell_comb \db_system_spwulight_b|Add0~29 (
// Equation(s):
// \db_system_spwulight_b|Add0~29_sumout  = SUM(( \db_system_spwulight_b|counter [7] ) + ( GND ) + ( \db_system_spwulight_b|Add0~46  ))
// \db_system_spwulight_b|Add0~30  = CARRY(( \db_system_spwulight_b|counter [7] ) + ( GND ) + ( \db_system_spwulight_b|Add0~46  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\db_system_spwulight_b|counter [7]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\db_system_spwulight_b|Add0~46 ),
        .sharein(gnd),
        .combout(),
        .sumout(\db_system_spwulight_b|Add0~29_sumout ),
        .cout(\db_system_spwulight_b|Add0~30 ),
        .shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|Add0~29 .extended_lut = "off";
defparam \db_system_spwulight_b|Add0~29 .lut_mask = 64'h0000FFFF000000FF;
defparam \db_system_spwulight_b|Add0~29 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y1_N0
cyclonev_lcell_comb \db_system_spwulight_b|counter~7 (
// Equation(s):
// \db_system_spwulight_b|counter~7_combout  = ( \db_system_spwulight_b|counter [7] & ( \db_system_spwulight_b|Add0~29_sumout  & ( !\KEY[1]~input_o  ) ) ) # ( !\db_system_spwulight_b|counter [7] & ( \db_system_spwulight_b|Add0~29_sumout  & ( 
// (!\db_system_spwulight_b|LessThan0~1_combout  & (\db_system_spwulight_b|LessThan0~2_combout  & (!\db_system_spwulight_b|counter [15] & !\KEY[1]~input_o ))) ) ) ) # ( \db_system_spwulight_b|counter [7] & ( !\db_system_spwulight_b|Add0~29_sumout  & ( 
// (!\KEY[1]~input_o  & (((!\db_system_spwulight_b|LessThan0~2_combout ) # (\db_system_spwulight_b|counter [15])) # (\db_system_spwulight_b|LessThan0~1_combout ))) ) ) )

        .dataa(!\db_system_spwulight_b|LessThan0~1_combout ),
        .datab(!\db_system_spwulight_b|LessThan0~2_combout ),
        .datac(!\db_system_spwulight_b|counter [15]),
        .datad(!\KEY[1]~input_o ),
        .datae(!\db_system_spwulight_b|counter [7]),
        .dataf(!\db_system_spwulight_b|Add0~29_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\db_system_spwulight_b|counter~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|counter~7 .extended_lut = "off";
defparam \db_system_spwulight_b|counter~7 .lut_mask = 64'h0000DF002000FF00;
defparam \db_system_spwulight_b|counter~7 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y1_N2
dffeas \db_system_spwulight_b|counter[7] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\db_system_spwulight_b|counter~7_combout ),
        .asdata(vcc),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\db_system_spwulight_b|counter [7]),
        .prn(vcc));
// synopsys translate_off
defparam \db_system_spwulight_b|counter[7] .is_wysiwyg = "true";
defparam \db_system_spwulight_b|counter[7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y1_N24
cyclonev_lcell_comb \db_system_spwulight_b|Add0~33 (
// Equation(s):
// \db_system_spwulight_b|Add0~33_sumout  = SUM(( \db_system_spwulight_b|counter [8] ) + ( GND ) + ( \db_system_spwulight_b|Add0~30  ))
// \db_system_spwulight_b|Add0~34  = CARRY(( \db_system_spwulight_b|counter [8] ) + ( GND ) + ( \db_system_spwulight_b|Add0~30  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\db_system_spwulight_b|counter [8]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\db_system_spwulight_b|Add0~30 ),
        .sharein(gnd),
        .combout(),
        .sumout(\db_system_spwulight_b|Add0~33_sumout ),
        .cout(\db_system_spwulight_b|Add0~34 ),
        .shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|Add0~33 .extended_lut = "off";
defparam \db_system_spwulight_b|Add0~33 .lut_mask = 64'h0000FFFF00000F0F;
defparam \db_system_spwulight_b|Add0~33 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y1_N3
cyclonev_lcell_comb \db_system_spwulight_b|counter~8 (
// Equation(s):
// \db_system_spwulight_b|counter~8_combout  = ( \db_system_spwulight_b|counter [8] & ( \db_system_spwulight_b|Add0~33_sumout  & ( !\KEY[1]~input_o  ) ) ) # ( !\db_system_spwulight_b|counter [8] & ( \db_system_spwulight_b|Add0~33_sumout  & ( 
// (!\db_system_spwulight_b|LessThan0~1_combout  & (\db_system_spwulight_b|LessThan0~2_combout  & (!\KEY[1]~input_o  & !\db_system_spwulight_b|counter [15]))) ) ) ) # ( \db_system_spwulight_b|counter [8] & ( !\db_system_spwulight_b|Add0~33_sumout  & ( 
// (!\KEY[1]~input_o  & (((!\db_system_spwulight_b|LessThan0~2_combout ) # (\db_system_spwulight_b|counter [15])) # (\db_system_spwulight_b|LessThan0~1_combout ))) ) ) )

        .dataa(!\db_system_spwulight_b|LessThan0~1_combout ),
        .datab(!\db_system_spwulight_b|LessThan0~2_combout ),
        .datac(!\KEY[1]~input_o ),
        .datad(!\db_system_spwulight_b|counter [15]),
        .datae(!\db_system_spwulight_b|counter [8]),
        .dataf(!\db_system_spwulight_b|Add0~33_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\db_system_spwulight_b|counter~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|counter~8 .extended_lut = "off";
defparam \db_system_spwulight_b|counter~8 .lut_mask = 64'h0000D0F02000F0F0;
defparam \db_system_spwulight_b|counter~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y1_N5
dffeas \db_system_spwulight_b|counter[8] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\db_system_spwulight_b|counter~8_combout ),
        .asdata(vcc),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\db_system_spwulight_b|counter [8]),
        .prn(vcc));
// synopsys translate_off
defparam \db_system_spwulight_b|counter[8] .is_wysiwyg = "true";
defparam \db_system_spwulight_b|counter[8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y1_N27
cyclonev_lcell_comb \db_system_spwulight_b|Add0~9 (
// Equation(s):
// \db_system_spwulight_b|Add0~9_sumout  = SUM(( \db_system_spwulight_b|counter [9] ) + ( GND ) + ( \db_system_spwulight_b|Add0~34  ))
// \db_system_spwulight_b|Add0~10  = CARRY(( \db_system_spwulight_b|counter [9] ) + ( GND ) + ( \db_system_spwulight_b|Add0~34  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\db_system_spwulight_b|counter [9]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\db_system_spwulight_b|Add0~34 ),
        .sharein(gnd),
        .combout(),
        .sumout(\db_system_spwulight_b|Add0~9_sumout ),
        .cout(\db_system_spwulight_b|Add0~10 ),
        .shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|Add0~9 .extended_lut = "off";
defparam \db_system_spwulight_b|Add0~9 .lut_mask = 64'h0000FFFF000000FF;
defparam \db_system_spwulight_b|Add0~9 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y1_N27
cyclonev_lcell_comb \db_system_spwulight_b|counter~2 (
// Equation(s):
// \db_system_spwulight_b|counter~2_combout  = ( \db_system_spwulight_b|counter [9] & ( \db_system_spwulight_b|Add0~9_sumout  & ( !\KEY[1]~input_o  ) ) ) # ( !\db_system_spwulight_b|counter [9] & ( \db_system_spwulight_b|Add0~9_sumout  & ( 
// (!\db_system_spwulight_b|LessThan0~1_combout  & (\db_system_spwulight_b|LessThan0~2_combout  & (!\KEY[1]~input_o  & !\db_system_spwulight_b|counter [15]))) ) ) ) # ( \db_system_spwulight_b|counter [9] & ( !\db_system_spwulight_b|Add0~9_sumout  & ( 
// !\KEY[1]~input_o  ) ) )

        .dataa(!\db_system_spwulight_b|LessThan0~1_combout ),
        .datab(!\db_system_spwulight_b|LessThan0~2_combout ),
        .datac(!\KEY[1]~input_o ),
        .datad(!\db_system_spwulight_b|counter [15]),
        .datae(!\db_system_spwulight_b|counter [9]),
        .dataf(!\db_system_spwulight_b|Add0~9_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\db_system_spwulight_b|counter~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|counter~2 .extended_lut = "off";
defparam \db_system_spwulight_b|counter~2 .lut_mask = 64'h0000F0F02000F0F0;
defparam \db_system_spwulight_b|counter~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y1_N29
dffeas \db_system_spwulight_b|counter[9] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\db_system_spwulight_b|counter~2_combout ),
        .asdata(vcc),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\db_system_spwulight_b|counter [9]),
        .prn(vcc));
// synopsys translate_off
defparam \db_system_spwulight_b|counter[9] .is_wysiwyg = "true";
defparam \db_system_spwulight_b|counter[9] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y1_N30
cyclonev_lcell_comb \db_system_spwulight_b|Add0~13 (
// Equation(s):
// \db_system_spwulight_b|Add0~13_sumout  = SUM(( \db_system_spwulight_b|counter [10] ) + ( GND ) + ( \db_system_spwulight_b|Add0~10  ))
// \db_system_spwulight_b|Add0~14  = CARRY(( \db_system_spwulight_b|counter [10] ) + ( GND ) + ( \db_system_spwulight_b|Add0~10  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\db_system_spwulight_b|counter [10]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\db_system_spwulight_b|Add0~10 ),
        .sharein(gnd),
        .combout(),
        .sumout(\db_system_spwulight_b|Add0~13_sumout ),
        .cout(\db_system_spwulight_b|Add0~14 ),
        .shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|Add0~13 .extended_lut = "off";
defparam \db_system_spwulight_b|Add0~13 .lut_mask = 64'h0000FFFF000000FF;
defparam \db_system_spwulight_b|Add0~13 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y1_N42
cyclonev_lcell_comb \db_system_spwulight_b|counter~3 (
// Equation(s):
// \db_system_spwulight_b|counter~3_combout  = ( \db_system_spwulight_b|counter [10] & ( \db_system_spwulight_b|Add0~13_sumout  & ( !\KEY[1]~input_o  ) ) ) # ( !\db_system_spwulight_b|counter [10] & ( \db_system_spwulight_b|Add0~13_sumout  & ( 
// (!\db_system_spwulight_b|LessThan0~1_combout  & (\db_system_spwulight_b|LessThan0~2_combout  & (!\db_system_spwulight_b|counter [15] & !\KEY[1]~input_o ))) ) ) ) # ( \db_system_spwulight_b|counter [10] & ( !\db_system_spwulight_b|Add0~13_sumout  & ( 
// !\KEY[1]~input_o  ) ) )

        .dataa(!\db_system_spwulight_b|LessThan0~1_combout ),
        .datab(!\db_system_spwulight_b|LessThan0~2_combout ),
        .datac(!\db_system_spwulight_b|counter [15]),
        .datad(!\KEY[1]~input_o ),
        .datae(!\db_system_spwulight_b|counter [10]),
        .dataf(!\db_system_spwulight_b|Add0~13_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\db_system_spwulight_b|counter~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|counter~3 .extended_lut = "off";
defparam \db_system_spwulight_b|counter~3 .lut_mask = 64'h0000FF002000FF00;
defparam \db_system_spwulight_b|counter~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y1_N44
dffeas \db_system_spwulight_b|counter[10] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\db_system_spwulight_b|counter~3_combout ),
        .asdata(vcc),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\db_system_spwulight_b|counter [10]),
        .prn(vcc));
// synopsys translate_off
defparam \db_system_spwulight_b|counter[10] .is_wysiwyg = "true";
defparam \db_system_spwulight_b|counter[10] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y1_N33
cyclonev_lcell_comb \db_system_spwulight_b|Add0~17 (
// Equation(s):
// \db_system_spwulight_b|Add0~17_sumout  = SUM(( \db_system_spwulight_b|counter [11] ) + ( GND ) + ( \db_system_spwulight_b|Add0~14  ))
// \db_system_spwulight_b|Add0~18  = CARRY(( \db_system_spwulight_b|counter [11] ) + ( GND ) + ( \db_system_spwulight_b|Add0~14  ))

        .dataa(!\db_system_spwulight_b|counter [11]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\db_system_spwulight_b|Add0~14 ),
        .sharein(gnd),
        .combout(),
        .sumout(\db_system_spwulight_b|Add0~17_sumout ),
        .cout(\db_system_spwulight_b|Add0~18 ),
        .shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|Add0~17 .extended_lut = "off";
defparam \db_system_spwulight_b|Add0~17 .lut_mask = 64'h0000FFFF00005555;
defparam \db_system_spwulight_b|Add0~17 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y1_N45
cyclonev_lcell_comb \db_system_spwulight_b|counter~4 (
// Equation(s):
// \db_system_spwulight_b|counter~4_combout  = ( \db_system_spwulight_b|counter [11] & ( \db_system_spwulight_b|Add0~17_sumout  & ( !\KEY[1]~input_o  ) ) ) # ( !\db_system_spwulight_b|counter [11] & ( \db_system_spwulight_b|Add0~17_sumout  & ( 
// (!\db_system_spwulight_b|LessThan0~1_combout  & (\db_system_spwulight_b|LessThan0~2_combout  & (!\KEY[1]~input_o  & !\db_system_spwulight_b|counter [15]))) ) ) ) # ( \db_system_spwulight_b|counter [11] & ( !\db_system_spwulight_b|Add0~17_sumout  & ( 
// !\KEY[1]~input_o  ) ) )

        .dataa(!\db_system_spwulight_b|LessThan0~1_combout ),
        .datab(!\db_system_spwulight_b|LessThan0~2_combout ),
        .datac(!\KEY[1]~input_o ),
        .datad(!\db_system_spwulight_b|counter [15]),
        .datae(!\db_system_spwulight_b|counter [11]),
        .dataf(!\db_system_spwulight_b|Add0~17_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\db_system_spwulight_b|counter~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|counter~4 .extended_lut = "off";
defparam \db_system_spwulight_b|counter~4 .lut_mask = 64'h0000F0F02000F0F0;
defparam \db_system_spwulight_b|counter~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y1_N47
dffeas \db_system_spwulight_b|counter[11] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\db_system_spwulight_b|counter~4_combout ),
        .asdata(vcc),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\db_system_spwulight_b|counter [11]),
        .prn(vcc));
// synopsys translate_off
defparam \db_system_spwulight_b|counter[11] .is_wysiwyg = "true";
defparam \db_system_spwulight_b|counter[11] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y1_N36
cyclonev_lcell_comb \db_system_spwulight_b|Add0~21 (
// Equation(s):
// \db_system_spwulight_b|Add0~21_sumout  = SUM(( \db_system_spwulight_b|counter [12] ) + ( GND ) + ( \db_system_spwulight_b|Add0~18  ))
// \db_system_spwulight_b|Add0~22  = CARRY(( \db_system_spwulight_b|counter [12] ) + ( GND ) + ( \db_system_spwulight_b|Add0~18  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\db_system_spwulight_b|counter [12]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\db_system_spwulight_b|Add0~18 ),
        .sharein(gnd),
        .combout(),
        .sumout(\db_system_spwulight_b|Add0~21_sumout ),
        .cout(\db_system_spwulight_b|Add0~22 ),
        .shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|Add0~21 .extended_lut = "off";
defparam \db_system_spwulight_b|Add0~21 .lut_mask = 64'h0000FFFF00000F0F;
defparam \db_system_spwulight_b|Add0~21 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y1_N30
cyclonev_lcell_comb \db_system_spwulight_b|counter~5 (
// Equation(s):
// \db_system_spwulight_b|counter~5_combout  = ( \db_system_spwulight_b|counter [12] & ( \db_system_spwulight_b|Add0~21_sumout  & ( !\KEY[1]~input_o  ) ) ) # ( !\db_system_spwulight_b|counter [12] & ( \db_system_spwulight_b|Add0~21_sumout  & ( 
// (!\db_system_spwulight_b|LessThan0~1_combout  & (\db_system_spwulight_b|LessThan0~2_combout  & (!\db_system_spwulight_b|counter [15] & !\KEY[1]~input_o ))) ) ) ) # ( \db_system_spwulight_b|counter [12] & ( !\db_system_spwulight_b|Add0~21_sumout  & ( 
// !\KEY[1]~input_o  ) ) )

        .dataa(!\db_system_spwulight_b|LessThan0~1_combout ),
        .datab(!\db_system_spwulight_b|LessThan0~2_combout ),
        .datac(!\db_system_spwulight_b|counter [15]),
        .datad(!\KEY[1]~input_o ),
        .datae(!\db_system_spwulight_b|counter [12]),
        .dataf(!\db_system_spwulight_b|Add0~21_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\db_system_spwulight_b|counter~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|counter~5 .extended_lut = "off";
defparam \db_system_spwulight_b|counter~5 .lut_mask = 64'h0000FF002000FF00;
defparam \db_system_spwulight_b|counter~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y1_N32
dffeas \db_system_spwulight_b|counter[12] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\db_system_spwulight_b|counter~5_combout ),
        .asdata(vcc),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\db_system_spwulight_b|counter [12]),
        .prn(vcc));
// synopsys translate_off
defparam \db_system_spwulight_b|counter[12] .is_wysiwyg = "true";
defparam \db_system_spwulight_b|counter[12] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y1_N39
cyclonev_lcell_comb \db_system_spwulight_b|Add0~25 (
// Equation(s):
// \db_system_spwulight_b|Add0~25_sumout  = SUM(( \db_system_spwulight_b|counter [13] ) + ( GND ) + ( \db_system_spwulight_b|Add0~22  ))
// \db_system_spwulight_b|Add0~26  = CARRY(( \db_system_spwulight_b|counter [13] ) + ( GND ) + ( \db_system_spwulight_b|Add0~22  ))

        .dataa(!\db_system_spwulight_b|counter [13]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\db_system_spwulight_b|Add0~22 ),
        .sharein(gnd),
        .combout(),
        .sumout(\db_system_spwulight_b|Add0~25_sumout ),
        .cout(\db_system_spwulight_b|Add0~26 ),
        .shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|Add0~25 .extended_lut = "off";
defparam \db_system_spwulight_b|Add0~25 .lut_mask = 64'h0000FFFF00005555;
defparam \db_system_spwulight_b|Add0~25 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y1_N33
cyclonev_lcell_comb \db_system_spwulight_b|counter~6 (
// Equation(s):
// \db_system_spwulight_b|counter~6_combout  = ( \db_system_spwulight_b|counter [13] & ( \db_system_spwulight_b|Add0~25_sumout  & ( !\KEY[1]~input_o  ) ) ) # ( !\db_system_spwulight_b|counter [13] & ( \db_system_spwulight_b|Add0~25_sumout  & ( 
// (!\db_system_spwulight_b|LessThan0~1_combout  & (\db_system_spwulight_b|LessThan0~2_combout  & (!\KEY[1]~input_o  & !\db_system_spwulight_b|counter [15]))) ) ) ) # ( \db_system_spwulight_b|counter [13] & ( !\db_system_spwulight_b|Add0~25_sumout  & ( 
// !\KEY[1]~input_o  ) ) )

        .dataa(!\db_system_spwulight_b|LessThan0~1_combout ),
        .datab(!\db_system_spwulight_b|LessThan0~2_combout ),
        .datac(!\KEY[1]~input_o ),
        .datad(!\db_system_spwulight_b|counter [15]),
        .datae(!\db_system_spwulight_b|counter [13]),
        .dataf(!\db_system_spwulight_b|Add0~25_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\db_system_spwulight_b|counter~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|counter~6 .extended_lut = "off";
defparam \db_system_spwulight_b|counter~6 .lut_mask = 64'h0000F0F02000F0F0;
defparam \db_system_spwulight_b|counter~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y1_N35
dffeas \db_system_spwulight_b|counter[13] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\db_system_spwulight_b|counter~6_combout ),
        .asdata(vcc),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\db_system_spwulight_b|counter [13]),
        .prn(vcc));
// synopsys translate_off
defparam \db_system_spwulight_b|counter[13] .is_wysiwyg = "true";
defparam \db_system_spwulight_b|counter[13] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y1_N42
cyclonev_lcell_comb \db_system_spwulight_b|Add0~1 (
// Equation(s):
// \db_system_spwulight_b|Add0~1_sumout  = SUM(( \db_system_spwulight_b|counter [14] ) + ( GND ) + ( \db_system_spwulight_b|Add0~26  ))
// \db_system_spwulight_b|Add0~2  = CARRY(( \db_system_spwulight_b|counter [14] ) + ( GND ) + ( \db_system_spwulight_b|Add0~26  ))

        .dataa(gnd),
        .datab(!\db_system_spwulight_b|counter [14]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\db_system_spwulight_b|Add0~26 ),
        .sharein(gnd),
        .combout(),
        .sumout(\db_system_spwulight_b|Add0~1_sumout ),
        .cout(\db_system_spwulight_b|Add0~2 ),
        .shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|Add0~1 .extended_lut = "off";
defparam \db_system_spwulight_b|Add0~1 .lut_mask = 64'h0000FFFF00003333;
defparam \db_system_spwulight_b|Add0~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y1_N24
cyclonev_lcell_comb \db_system_spwulight_b|counter~0 (
// Equation(s):
// \db_system_spwulight_b|counter~0_combout  = ( \db_system_spwulight_b|counter [14] & ( \db_system_spwulight_b|Add0~1_sumout  & ( !\KEY[1]~input_o  ) ) ) # ( !\db_system_spwulight_b|counter [14] & ( \db_system_spwulight_b|Add0~1_sumout  & ( 
// (!\db_system_spwulight_b|LessThan0~1_combout  & (\db_system_spwulight_b|LessThan0~2_combout  & (!\db_system_spwulight_b|counter [15] & !\KEY[1]~input_o ))) ) ) ) # ( \db_system_spwulight_b|counter [14] & ( !\db_system_spwulight_b|Add0~1_sumout  & ( 
// !\KEY[1]~input_o  ) ) )

        .dataa(!\db_system_spwulight_b|LessThan0~1_combout ),
        .datab(!\db_system_spwulight_b|LessThan0~2_combout ),
        .datac(!\db_system_spwulight_b|counter [15]),
        .datad(!\KEY[1]~input_o ),
        .datae(!\db_system_spwulight_b|counter [14]),
        .dataf(!\db_system_spwulight_b|Add0~1_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\db_system_spwulight_b|counter~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|counter~0 .extended_lut = "off";
defparam \db_system_spwulight_b|counter~0 .lut_mask = 64'h0000FF002000FF00;
defparam \db_system_spwulight_b|counter~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y1_N26
dffeas \db_system_spwulight_b|counter[14] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\db_system_spwulight_b|counter~0_combout ),
        .asdata(vcc),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\db_system_spwulight_b|counter [14]),
        .prn(vcc));
// synopsys translate_off
defparam \db_system_spwulight_b|counter[14] .is_wysiwyg = "true";
defparam \db_system_spwulight_b|counter[14] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y1_N12
cyclonev_lcell_comb \db_system_spwulight_b|LessThan0~0 (
// Equation(s):
// \db_system_spwulight_b|LessThan0~0_combout  = ( !\db_system_spwulight_b|counter [11] & ( !\db_system_spwulight_b|counter [10] & ( (!\db_system_spwulight_b|counter [9] & (!\db_system_spwulight_b|counter [12] & !\db_system_spwulight_b|counter [13])) ) ) )

        .dataa(!\db_system_spwulight_b|counter [9]),
        .datab(!\db_system_spwulight_b|counter [12]),
        .datac(!\db_system_spwulight_b|counter [13]),
        .datad(gnd),
        .datae(!\db_system_spwulight_b|counter [11]),
        .dataf(!\db_system_spwulight_b|counter [10]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\db_system_spwulight_b|LessThan0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|LessThan0~0 .extended_lut = "off";
defparam \db_system_spwulight_b|LessThan0~0 .lut_mask = 64'h8080000000000000;
defparam \db_system_spwulight_b|LessThan0~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y1_N57
cyclonev_lcell_comb \db_system_spwulight_b|LessThan0~2 (
// Equation(s):
// \db_system_spwulight_b|LessThan0~2_combout  = ( \db_system_spwulight_b|LessThan0~0_combout  & ( !\db_system_spwulight_b|counter [14] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\db_system_spwulight_b|counter [14]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\db_system_spwulight_b|LessThan0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\db_system_spwulight_b|LessThan0~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|LessThan0~2 .extended_lut = "off";
defparam \db_system_spwulight_b|LessThan0~2 .lut_mask = 64'h00000000F0F0F0F0;
defparam \db_system_spwulight_b|LessThan0~2 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y1_N36
cyclonev_lcell_comb \db_system_spwulight_b|counter~9 (
// Equation(s):
// \db_system_spwulight_b|counter~9_combout  = ( \db_system_spwulight_b|counter [4] & ( \db_system_spwulight_b|Add0~37_sumout  & ( !\KEY[1]~input_o  ) ) ) # ( !\db_system_spwulight_b|counter [4] & ( \db_system_spwulight_b|Add0~37_sumout  & ( 
// (!\db_system_spwulight_b|LessThan0~1_combout  & (!\KEY[1]~input_o  & (!\db_system_spwulight_b|counter [15] & \db_system_spwulight_b|LessThan0~2_combout ))) ) ) ) # ( \db_system_spwulight_b|counter [4] & ( !\db_system_spwulight_b|Add0~37_sumout  & ( 
// (!\KEY[1]~input_o  & (((!\db_system_spwulight_b|LessThan0~2_combout ) # (\db_system_spwulight_b|counter [15])) # (\db_system_spwulight_b|LessThan0~1_combout ))) ) ) )

        .dataa(!\db_system_spwulight_b|LessThan0~1_combout ),
        .datab(!\KEY[1]~input_o ),
        .datac(!\db_system_spwulight_b|counter [15]),
        .datad(!\db_system_spwulight_b|LessThan0~2_combout ),
        .datae(!\db_system_spwulight_b|counter [4]),
        .dataf(!\db_system_spwulight_b|Add0~37_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\db_system_spwulight_b|counter~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|counter~9 .extended_lut = "off";
defparam \db_system_spwulight_b|counter~9 .lut_mask = 64'h0000CC4C0080CCCC;
defparam \db_system_spwulight_b|counter~9 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y1_N38
dffeas \db_system_spwulight_b|counter[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\db_system_spwulight_b|counter~9_combout ),
        .asdata(vcc),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\db_system_spwulight_b|counter [4]),
        .prn(vcc));
// synopsys translate_off
defparam \db_system_spwulight_b|counter[4] .is_wysiwyg = "true";
defparam \db_system_spwulight_b|counter[4] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y1_N54
cyclonev_lcell_comb \db_system_spwulight_b|LessThan0~1 (
// Equation(s):
// \db_system_spwulight_b|LessThan0~1_combout  = ( \db_system_spwulight_b|counter [5] & ( (\db_system_spwulight_b|counter [8] & \db_system_spwulight_b|counter [7]) ) ) # ( !\db_system_spwulight_b|counter [5] & ( (\db_system_spwulight_b|counter [8] & 
// (\db_system_spwulight_b|counter [7] & ((\db_system_spwulight_b|counter [6]) # (\db_system_spwulight_b|counter [4])))) ) )

        .dataa(!\db_system_spwulight_b|counter [4]),
        .datab(!\db_system_spwulight_b|counter [6]),
        .datac(!\db_system_spwulight_b|counter [8]),
        .datad(!\db_system_spwulight_b|counter [7]),
        .datae(gnd),
        .dataf(!\db_system_spwulight_b|counter [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\db_system_spwulight_b|LessThan0~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|LessThan0~1 .extended_lut = "off";
defparam \db_system_spwulight_b|LessThan0~1 .lut_mask = 64'h00070007000F000F;
defparam \db_system_spwulight_b|LessThan0~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y1_N45
cyclonev_lcell_comb \db_system_spwulight_b|Add0~5 (
// Equation(s):
// \db_system_spwulight_b|Add0~5_sumout  = SUM(( \db_system_spwulight_b|counter [15] ) + ( GND ) + ( \db_system_spwulight_b|Add0~2  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\db_system_spwulight_b|counter [15]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\db_system_spwulight_b|Add0~2 ),
        .sharein(gnd),
        .combout(),
        .sumout(\db_system_spwulight_b|Add0~5_sumout ),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|Add0~5 .extended_lut = "off";
defparam \db_system_spwulight_b|Add0~5 .lut_mask = 64'h0000FFFF00000F0F;
defparam \db_system_spwulight_b|Add0~5 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y1_N48
cyclonev_lcell_comb \db_system_spwulight_b|counter~1 (
// Equation(s):
// \db_system_spwulight_b|counter~1_combout  = ( \db_system_spwulight_b|counter [15] & ( \db_system_spwulight_b|LessThan0~2_combout  & ( !\KEY[1]~input_o  ) ) ) # ( !\db_system_spwulight_b|counter [15] & ( \db_system_spwulight_b|LessThan0~2_combout  & ( 
// (!\db_system_spwulight_b|LessThan0~1_combout  & (!\KEY[1]~input_o  & \db_system_spwulight_b|Add0~5_sumout )) ) ) ) # ( \db_system_spwulight_b|counter [15] & ( !\db_system_spwulight_b|LessThan0~2_combout  & ( !\KEY[1]~input_o  ) ) )

        .dataa(!\db_system_spwulight_b|LessThan0~1_combout ),
        .datab(!\KEY[1]~input_o ),
        .datac(!\db_system_spwulight_b|Add0~5_sumout ),
        .datad(gnd),
        .datae(!\db_system_spwulight_b|counter [15]),
        .dataf(!\db_system_spwulight_b|LessThan0~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\db_system_spwulight_b|counter~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|counter~1 .extended_lut = "off";
defparam \db_system_spwulight_b|counter~1 .lut_mask = 64'h0000CCCC0808CCCC;
defparam \db_system_spwulight_b|counter~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y1_N50
dffeas \db_system_spwulight_b|counter[15] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\db_system_spwulight_b|counter~1_combout ),
        .asdata(vcc),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\db_system_spwulight_b|counter [15]),
        .prn(vcc));
// synopsys translate_off
defparam \db_system_spwulight_b|counter[15] .is_wysiwyg = "true";
defparam \db_system_spwulight_b|counter[15] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y1_N9
cyclonev_lcell_comb \db_system_spwulight_b|aux_pb~0 (
// Equation(s):
// \db_system_spwulight_b|aux_pb~0_combout  = ( \db_system_spwulight_b|LessThan0~1_combout  & ( \db_system_spwulight_b|aux_pb~q  & ( !\KEY[1]~input_o  ) ) ) # ( !\db_system_spwulight_b|LessThan0~1_combout  & ( \db_system_spwulight_b|aux_pb~q  & ( 
// !\KEY[1]~input_o  ) ) ) # ( \db_system_spwulight_b|LessThan0~1_combout  & ( !\db_system_spwulight_b|aux_pb~q  & ( !\KEY[1]~input_o  ) ) ) # ( !\db_system_spwulight_b|LessThan0~1_combout  & ( !\db_system_spwulight_b|aux_pb~q  & ( (!\KEY[1]~input_o  & 
// (((!\db_system_spwulight_b|LessThan0~0_combout ) # (\db_system_spwulight_b|counter [14])) # (\db_system_spwulight_b|counter [15]))) ) ) )

        .dataa(!\db_system_spwulight_b|counter [15]),
        .datab(!\db_system_spwulight_b|counter [14]),
        .datac(!\db_system_spwulight_b|LessThan0~0_combout ),
        .datad(!\KEY[1]~input_o ),
        .datae(!\db_system_spwulight_b|LessThan0~1_combout ),
        .dataf(!\db_system_spwulight_b|aux_pb~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\db_system_spwulight_b|aux_pb~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|aux_pb~0 .extended_lut = "off";
defparam \db_system_spwulight_b|aux_pb~0 .lut_mask = 64'hF700FF00FF00FF00;
defparam \db_system_spwulight_b|aux_pb~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y1_N17
dffeas \db_system_spwulight_b|aux_pb (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\db_system_spwulight_b|aux_pb~0_combout ),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\db_system_spwulight_b|aux_pb~q ),
        .prn(vcc));
// synopsys translate_off
defparam \db_system_spwulight_b|aux_pb .is_wysiwyg = "true";
defparam \db_system_spwulight_b|aux_pb .power_up = "low";
// synopsys translate_on

// Location: FRACTIONALPLL_X68_Y1_N0
cyclonev_fractional_pll \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll (
        .coreclkfb(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fboutclk_wire [0]),
        .ecnc1test(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|refclk_select_extswitchbuf_wire ),
        .ecnc2test(gnd),
        .fbclkfpll(gnd),
        .lvdsfbin(gnd),
        .nresync(!\db_system_spwulight_b|aux_pb~q ),
        .pfden(vcc),
        .refclkin(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|refclk_select_clkout_wire ),
        .shift(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|shift ),
        .shiftdonein(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|shift ),
        .shiften(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|pll_reconfig_shiftenm_wire ),
        .up(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|pll_reconfig_up_wire ),
        .zdb(gnd),
        .cntnen(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|cntnen ),
        .fbclk(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fboutclk_wire [0]),
        .fblvdsout(),
        .lock(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock ),
        .mcntout(),
        .plniotribuf(),
        .shiftdoneout(),
        .tclk(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|tclk ),
        .mhi(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_MHI_bus ),
        .vcoph(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_VCOPH_bus ));
// synopsys translate_off
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .dsm_accumulator_reset_value = 0;
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .forcelock = "false";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .mimic_fbclk_type = "none";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .nreset_invert = "false";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .output_clock_frequency = "400.0 mhz";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_atb = 0;
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_bwctrl = 4000;
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_cmp_buf_dly = "0 ps";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_cp_comp = "true";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_cp_current = 10;
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_ctrl_override_setting = "false";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_dsm_dither = "disable";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_dsm_out_sel = "disable";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_dsm_reset = "false";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_ecn_bypass = "false";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_ecn_test_en = "false";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_enable = "true";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_fbclk_mux_1 = "glb";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_fbclk_mux_2 = "m_cnt";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_fractional_carry_out = 32;
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_fractional_division = 1;
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_fractional_division_string = "1";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_fractional_value_ready = "true";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_lf_testen = "false";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_lock_fltr_cfg = 25;
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_lock_fltr_test = "false";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_m_cnt_bypass_en = "false";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_m_cnt_coarse_dly = "0 ps";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_m_cnt_fine_dly = "0 ps";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_m_cnt_hi_div = 4;
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_m_cnt_in_src = "ph_mux_clk";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_m_cnt_lo_div = 4;
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_m_cnt_odd_div_duty_en = "false";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_m_cnt_ph_mux_prst = 0;
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_m_cnt_prst = 1;
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_n_cnt_bypass_en = "false";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_n_cnt_coarse_dly = "0 ps";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_n_cnt_fine_dly = "0 ps";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_n_cnt_hi_div = 1;
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_n_cnt_lo_div = 1;
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_n_cnt_odd_div_duty_en = "false";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_ref_buf_dly = "0 ps";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_reg_boost = 0;
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_regulator_bypass = "false";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_ripplecap_ctrl = 0;
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_slf_rst = "false";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_tclk_mux_en = "false";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_tclk_sel = "n_src";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_test_enable = "false";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_testdn_enable = "false";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_testup_enable = "false";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_unlock_fltr_cfg = 2;
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_vco_div = 2;
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_vco_ph0_en = "true";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_vco_ph1_en = "true";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_vco_ph2_en = "true";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_vco_ph3_en = "true";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_vco_ph4_en = "true";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_vco_ph5_en = "true";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_vco_ph6_en = "true";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_vco_ph7_en = "true";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_vctrl_test_voltage = 750;
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .reference_clock_frequency = "100.0 mhz";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .vccd0g_atb = "disable";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .vccd0g_output = 0;
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .vccd1g_atb = "disable";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .vccd1g_output = 0;
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .vccm1g_tap = 2;
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .vccr_pd = "false";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .vcodiv_override = "false";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .fractional_pll_index = 0;
// synopsys translate_on

// Location: PLLRECONFIG_X68_Y5_N0
cyclonev_pll_reconfig \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|PLL_RECONFIG (
        .atpgmode(gnd),
        .clk(gnd),
        .cntnen(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|cntnen ),
        .fpllcsrtest(gnd),
        .iocsrclkin(gnd),
        .iocsrdatain(gnd),
        .iocsren(gnd),
        .iocsrrstn(gnd),
        .mdiodis(vcc),
        .phaseen(gnd),
        .read(gnd),
        .rstn(vcc),
        .scanen(gnd),
        .sershiftload(vcc),
        .shiftdonei(gnd),
        .updn(gnd),
        .write(gnd),
        .addr(6'b000000),
        .byteen(2'b00),
        .cntsel(5'b00000),
        .din(16'b0000000000000000),
        .mhi({\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [7],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [6],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [5],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [4],
\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [3],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [2],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [1],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [0]}),
        .blockselect(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|blockselect ),
        .iocsrdataout(),
        .iocsrenbuf(),
        .iocsrrstnbuf(),
        .phasedone(),
        .shift(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|shift ),
        .shiftenm(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|pll_reconfig_shiftenm_wire ),
        .up(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|pll_reconfig_up_wire ),
        .dout(),
        .dprioout(),
        .shiften(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|PLL_RECONFIG_SHIFTEN_bus ));
// synopsys translate_off
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|PLL_RECONFIG .fractional_pll_index = 0;
// synopsys translate_on

// Location: PLLOUTPUTCOUNTER_X68_Y2_N1
cyclonev_pll_output_counter \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter (
        .cascadein(gnd),
        .nen0(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|cntnen ),
        .shift0(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|shift ),
        .shiftdone0i(gnd),
        .shiften(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|shiften [2]),
        .tclk0(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|tclk ),
        .up0(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|pll_reconfig_up_wire ),
        .vco0ph({\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [7],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [6],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [5],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [4],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [3],
\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [2],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [1],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [0]}),
        .cascadeout(\u0|pll_0|altera_pll_i|cyclonev_pll|cascade_wire [0]),
        .divclk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk [0]),
        .shiftdone0o());
// synopsys translate_off
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .c_cnt_coarse_dly = "0 ps";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .c_cnt_fine_dly = "0 ps";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .c_cnt_in_src = "ph_mux_clk";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .c_cnt_ph_mux_prst = 0;
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .c_cnt_prst = 1;
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .cnt_fpll_src = "fpll_0";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .dprio0_cnt_bypass_en = "true";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .dprio0_cnt_hi_div = 256;
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .dprio0_cnt_lo_div = 256;
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .dprio0_cnt_odd_div_even_duty_en = "false";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .duty_cycle = 50;
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .output_clock_frequency = "400.0 mhz";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .phase_shift = "0 ps";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .fractional_pll_index = 0;
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .output_counter_index = 2;
// synopsys translate_on

// Location: CLKCTRL_G11
cyclonev_clkena \u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0 (
        .inclk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk [0]),
        .ena(vcc),
        .outclk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),
        .enaout());
// synopsys translate_off
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0 .clock_type = "global clock";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0 .disable_mode = "low";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0 .ena_register_mode = "always enabled";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0 .ena_register_power_up = "high";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0 .test_syn = "high";
// synopsys translate_on

// Location: LABCELL_X21_Y20_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter~2 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter~2_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter~0_combout  & ( !\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [0] $ 
// (!\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [1]) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [0]),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter~2 .lut_mask = 64'h000000000FF00FF0;
defparam \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X31_Y11_N45
cyclonev_lcell_comb \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder (
// Equation(s):
// \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder .extended_lut = "off";
defparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y11_N47
dffeas \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1] .is_wysiwyg = "true";
defparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X31_Y11_N32
dffeas \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain [1]),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0] .is_wysiwyg = "true";
defparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X31_Y11_N17
dffeas \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain [0]),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out .is_wysiwyg = "true";
defparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out .power_up = "low";
// synopsys translate_on

// Location: CLKCTRL_G3
cyclonev_clkena \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0 (
        .inclk(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .ena(vcc),
        .outclk(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .enaout());
// synopsys translate_off
defparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0 .clock_type = "global clock";
defparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0 .disable_mode = "low";
defparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0 .ena_register_mode = "always enabled";
defparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0 .ena_register_power_up = "high";
defparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0 .test_syn = "high";
// synopsys translate_on

// Location: FF_X21_Y20_N26
dffeas \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y20_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_translator|waitrequest_reset_override~feeder (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_translator|waitrequest_reset_override~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_translator|waitrequest_reset_override~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y20_N11
dffeas \u0|mm_interconnect_0|write_en_tx_s1_translator|waitrequest_reset_override (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_translator|waitrequest_reset_override~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_translator|waitrequest_reset_override~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_translator|waitrequest_reset_override .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y21_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override~feeder (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y21_N38
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y20_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override~feeder (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y20_N17
dffeas \u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y25_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~2 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~2_combout  = ( \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [1] & ( \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~0_combout  & ( 
// !\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0] ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [1] & ( \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~0_combout  & ( 
// \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0] ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0]),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [1]),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~2 .lut_mask = 64'h000000003333CCCC;
defparam \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y25_N50
dffeas \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y14_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override~feeder (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y14_N26
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y27_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg~1_combout  = ( \u0|mm_interconnect_0|cmd_mux_007|arb|grant[0]~1_combout  & ( (\u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg [1]) # 
// (\u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg~0_combout ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_007|arb|grant[0]~1_combout  & ( (!\u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg~0_combout  & 
// \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg [1]) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg~0_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_007|arb|grant[0]~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg~1 .lut_mask = 64'h00F000F00FFF0FFF;
defparam \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y27_N47
dffeas \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X22_Y24_N44
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~15_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][110]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][110] .power_up = "low";
// synopsys translate_on

// Location: FF_X27_Y17_N59
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][69] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][69]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][69] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y24_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|src_payload[0] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|src_payload [0] = ( \u0|hps_0|fpga_interfaces|h2f_WLAST [0] & ( (\u0|mm_interconnect_0|cmd_mux|saved_grant [1]) # (\u0|mm_interconnect_0|cmd_mux|saved_grant [0]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_WLAST [0] & ( 
// \u0|mm_interconnect_0|cmd_mux|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_WLAST [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux|src_payload [0]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|src_payload[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|src_payload[0] .lut_mask = 64'h00FF00FF33FF33FF;
defparam \u0|mm_interconnect_0|cmd_mux|src_payload[0] .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y24_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|packet_in_progress~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|packet_in_progress~0_combout  = ( !\u0|mm_interconnect_0|cmd_mux|update_grant~0_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux|update_grant~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux|packet_in_progress~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|packet_in_progress~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|packet_in_progress~0 .lut_mask = 64'hFFFFFFFF00000000;
defparam \u0|mm_interconnect_0|cmd_mux|packet_in_progress~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y24_N28
dffeas \u0|mm_interconnect_0|cmd_mux|packet_in_progress (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux|packet_in_progress~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux|packet_in_progress~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|packet_in_progress .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux|packet_in_progress .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y25_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~feeder (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y25_N29
dffeas \u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y25_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout  = ( !\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [1] & ( \u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~q  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0 .lut_mask = 64'h00FF00FF00000000;
defparam \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y25_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~4 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~4_combout  = ( \u0|mm_interconnect_0|auto_start_s1_agent|local_write~0_combout  & ( (\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout  & 
// (!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0] $ (((\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout ))))) ) ) # ( 
// !\u0|mm_interconnect_0|auto_start_s1_agent|local_write~0_combout  & ( (\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout  & \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0]) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout ),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0]),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout ),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|local_write~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~4 .lut_mask = 64'h1111111141114111;
defparam \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y25_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg~1_combout  = ( \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~4_combout  & ( \u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg~0_combout  ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg~0_combout ),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~4_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg~1 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y25_N41
dffeas \u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y17_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_010|src1_valid (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout  = ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|rp_valid~combout  & ( !\u0|mm_interconnect_0|rsp_demux_010|src0_valid~0_combout  ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|rsp_demux_010|src0_valid~0_combout ),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|rp_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_010|src1_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_010|src1_valid .lut_mask = 64'hCCCCCCCC00000000;
defparam \u0|mm_interconnect_0|rsp_demux_010|src1_valid .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y7_N6
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add1~5 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Add1~5_sumout  = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [2] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~2  ))
// \R_400_to_2_5_10_100_200_300MHZ|Add1~6  = CARRY(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [2] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~2  ))

        .dataa(gnd),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [2]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\R_400_to_2_5_10_100_200_300MHZ|Add1~2 ),
        .sharein(gnd),
        .combout(),
        .sumout(\R_400_to_2_5_10_100_200_300MHZ|Add1~5_sumout ),
        .cout(\R_400_to_2_5_10_100_200_300MHZ|Add1~6 ),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~5 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~5 .lut_mask = 64'h0000FFFF00003333;
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y7_N9
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add1~29 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Add1~29_sumout  = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [3] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~6  ))
// \R_400_to_2_5_10_100_200_300MHZ|Add1~30  = CARRY(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [3] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~6  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [3]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\R_400_to_2_5_10_100_200_300MHZ|Add1~6 ),
        .sharein(gnd),
        .combout(),
        .sumout(\R_400_to_2_5_10_100_200_300MHZ|Add1~29_sumout ),
        .cout(\R_400_to_2_5_10_100_200_300MHZ|Add1~30 ),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~29 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~29 .lut_mask = 64'h0000FFFF00000F0F;
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~29 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y7_N39
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter_100~8 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter_100~8_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|Add1~29_sumout  & ( \R_400_to_2_5_10_100_200_300MHZ|counter_100~0_combout  ) )

        .dataa(gnd),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter_100~0_combout ),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add1~29_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter_100~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~8 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~8 .lut_mask = 64'h0000000033333333;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X45_Y7_N41
dffeas \R_400_to_2_5_10_100_200_300MHZ|counter_100[3] (
        .clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),
        .d(\R_400_to_2_5_10_100_200_300MHZ|counter_100~8_combout ),
        .asdata(vcc),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\R_400_to_2_5_10_100_200_300MHZ|counter_100 [3]),
        .prn(vcc));
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[3] .is_wysiwyg = "true";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y7_N12
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add1~33 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Add1~33_sumout  = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [4] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~30  ))
// \R_400_to_2_5_10_100_200_300MHZ|Add1~34  = CARRY(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [4] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~30  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [4]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\R_400_to_2_5_10_100_200_300MHZ|Add1~30 ),
        .sharein(gnd),
        .combout(),
        .sumout(\R_400_to_2_5_10_100_200_300MHZ|Add1~33_sumout ),
        .cout(\R_400_to_2_5_10_100_200_300MHZ|Add1~34 ),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~33 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~33 .lut_mask = 64'h0000FFFF00000F0F;
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~33 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y7_N36
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter_100~9 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter_100~9_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|Add1~33_sumout  & ( \R_400_to_2_5_10_100_200_300MHZ|counter_100~0_combout  ) )

        .dataa(gnd),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter_100~0_combout ),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add1~33_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter_100~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~9 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~9 .lut_mask = 64'h0000000033333333;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~9 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X45_Y7_N38
dffeas \R_400_to_2_5_10_100_200_300MHZ|counter_100[4] (
        .clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),
        .d(\R_400_to_2_5_10_100_200_300MHZ|counter_100~9_combout ),
        .asdata(vcc),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\R_400_to_2_5_10_100_200_300MHZ|counter_100 [4]),
        .prn(vcc));
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[4] .is_wysiwyg = "true";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y7_N15
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add1~37 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Add1~37_sumout  = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [5] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~34  ))
// \R_400_to_2_5_10_100_200_300MHZ|Add1~38  = CARRY(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [5] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~34  ))

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [5]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\R_400_to_2_5_10_100_200_300MHZ|Add1~34 ),
        .sharein(gnd),
        .combout(),
        .sumout(\R_400_to_2_5_10_100_200_300MHZ|Add1~37_sumout ),
        .cout(\R_400_to_2_5_10_100_200_300MHZ|Add1~38 ),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~37 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~37 .lut_mask = 64'h0000FFFF00005555;
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~37 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y7_N54
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter_100~10 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter_100~10_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|Add1~37_sumout  & ( \R_400_to_2_5_10_100_200_300MHZ|counter_100~0_combout  ) )

        .dataa(gnd),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter_100~0_combout ),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add1~37_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter_100~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~10 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~10 .lut_mask = 64'h0000000033333333;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~10 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X45_Y7_N56
dffeas \R_400_to_2_5_10_100_200_300MHZ|counter_100[5] (
        .clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),
        .d(\R_400_to_2_5_10_100_200_300MHZ|counter_100~10_combout ),
        .asdata(vcc),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\R_400_to_2_5_10_100_200_300MHZ|counter_100 [5]),
        .prn(vcc));
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[5] .is_wysiwyg = "true";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y7_N18
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add1~41 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Add1~41_sumout  = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [6] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~38  ))
// \R_400_to_2_5_10_100_200_300MHZ|Add1~42  = CARRY(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [6] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~38  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [6]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\R_400_to_2_5_10_100_200_300MHZ|Add1~38 ),
        .sharein(gnd),
        .combout(),
        .sumout(\R_400_to_2_5_10_100_200_300MHZ|Add1~41_sumout ),
        .cout(\R_400_to_2_5_10_100_200_300MHZ|Add1~42 ),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~41 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~41 .lut_mask = 64'h0000FFFF00000F0F;
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~41 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y7_N51
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter_100~11 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter_100~11_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|Add1~41_sumout  & ( \R_400_to_2_5_10_100_200_300MHZ|counter_100~0_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter_100~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add1~41_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter_100~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~11 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~11 .lut_mask = 64'h000000000F0F0F0F;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~11 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X45_Y7_N53
dffeas \R_400_to_2_5_10_100_200_300MHZ|counter_100[6] (
        .clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),
        .d(\R_400_to_2_5_10_100_200_300MHZ|counter_100~11_combout ),
        .asdata(vcc),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\R_400_to_2_5_10_100_200_300MHZ|counter_100 [6]),
        .prn(vcc));
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[6] .is_wysiwyg = "true";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y7_N42
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|LessThan16~0 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|LessThan16~0_combout  = ( !\R_400_to_2_5_10_100_200_300MHZ|counter_100 [6] & ( (!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [5] & (!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [3] & 
// !\R_400_to_2_5_10_100_200_300MHZ|counter_100 [4])) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [5]),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [3]),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [4]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [6]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|LessThan16~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|LessThan16~0 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|LessThan16~0 .lut_mask = 64'h8080808000000000;
defparam \R_400_to_2_5_10_100_200_300MHZ|LessThan16~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y7_N21
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add1~13 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Add1~13_sumout  = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [7] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~42  ))
// \R_400_to_2_5_10_100_200_300MHZ|Add1~14  = CARRY(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [7] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~42  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [7]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\R_400_to_2_5_10_100_200_300MHZ|Add1~42 ),
        .sharein(gnd),
        .combout(),
        .sumout(\R_400_to_2_5_10_100_200_300MHZ|Add1~13_sumout ),
        .cout(\R_400_to_2_5_10_100_200_300MHZ|Add1~14 ),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~13 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~13 .lut_mask = 64'h0000FFFF00000F0F;
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y7_N45
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter_100~4 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter_100~4_combout  = (\R_400_to_2_5_10_100_200_300MHZ|counter_100~0_combout  & \R_400_to_2_5_10_100_200_300MHZ|Add1~13_sumout )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter_100~0_combout ),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|Add1~13_sumout ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter_100~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~4 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~4 .lut_mask = 64'h000F000F000F000F;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X45_Y7_N47
dffeas \R_400_to_2_5_10_100_200_300MHZ|counter_100[7] (
        .clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),
        .d(\R_400_to_2_5_10_100_200_300MHZ|counter_100~4_combout ),
        .asdata(vcc),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\R_400_to_2_5_10_100_200_300MHZ|counter_100 [7]),
        .prn(vcc));
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[7] .is_wysiwyg = "true";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y7_N24
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add1~17 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Add1~17_sumout  = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [8] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~14  ))
// \R_400_to_2_5_10_100_200_300MHZ|Add1~18  = CARRY(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [8] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~14  ))

        .dataa(gnd),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [8]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\R_400_to_2_5_10_100_200_300MHZ|Add1~14 ),
        .sharein(gnd),
        .combout(),
        .sumout(\R_400_to_2_5_10_100_200_300MHZ|Add1~17_sumout ),
        .cout(\R_400_to_2_5_10_100_200_300MHZ|Add1~18 ),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~17 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~17 .lut_mask = 64'h0000FFFF00003333;
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~17 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y7_N57
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter_100~5 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter_100~5_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|Add1~17_sumout  & ( \R_400_to_2_5_10_100_200_300MHZ|counter_100~0_combout  ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter_100~0_combout ),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add1~17_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter_100~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~5 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~5 .lut_mask = 64'h0000000055555555;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y7_N59
dffeas \R_400_to_2_5_10_100_200_300MHZ|counter_100[8] (
        .clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),
        .d(\R_400_to_2_5_10_100_200_300MHZ|counter_100~5_combout ),
        .asdata(vcc),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\R_400_to_2_5_10_100_200_300MHZ|counter_100 [8]),
        .prn(vcc));
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[8] .is_wysiwyg = "true";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y7_N27
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add1~21 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Add1~21_sumout  = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [9] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~18  ))
// \R_400_to_2_5_10_100_200_300MHZ|Add1~22  = CARRY(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [9] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~18  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [9]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\R_400_to_2_5_10_100_200_300MHZ|Add1~18 ),
        .sharein(gnd),
        .combout(),
        .sumout(\R_400_to_2_5_10_100_200_300MHZ|Add1~21_sumout ),
        .cout(\R_400_to_2_5_10_100_200_300MHZ|Add1~22 ),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~21 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~21 .lut_mask = 64'h0000FFFF00000F0F;
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~21 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y7_N18
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter_100~6 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter_100~6_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|Add1~21_sumout  & ( \R_400_to_2_5_10_100_200_300MHZ|counter_100~0_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\R_400_to_2_5_10_100_200_300MHZ|Add1~21_sumout ),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter_100~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter_100~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~6 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~6 .lut_mask = 64'h000000000000FFFF;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y7_N20
dffeas \R_400_to_2_5_10_100_200_300MHZ|counter_100[9] (
        .clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),
        .d(\R_400_to_2_5_10_100_200_300MHZ|counter_100~6_combout ),
        .asdata(vcc),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\R_400_to_2_5_10_100_200_300MHZ|counter_100 [9]),
        .prn(vcc));
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[9] .is_wysiwyg = "true";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[9] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y7_N30
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add1~25 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Add1~25_sumout  = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [10] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~22  ))

        .dataa(gnd),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [10]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\R_400_to_2_5_10_100_200_300MHZ|Add1~22 ),
        .sharein(gnd),
        .combout(),
        .sumout(\R_400_to_2_5_10_100_200_300MHZ|Add1~25_sumout ),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~25 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~25 .lut_mask = 64'h0000FFFF00003333;
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~25 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y7_N57
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter_100~7 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter_100~7_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|Add1~25_sumout  & ( \R_400_to_2_5_10_100_200_300MHZ|counter_100~0_combout  ) )

        .dataa(gnd),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter_100~0_combout ),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add1~25_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter_100~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~7 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~7 .lut_mask = 64'h0000000033333333;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~7 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X45_Y7_N59
dffeas \R_400_to_2_5_10_100_200_300MHZ|counter_100[10] (
        .clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),
        .d(\R_400_to_2_5_10_100_200_300MHZ|counter_100~7_combout ),
        .asdata(vcc),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\R_400_to_2_5_10_100_200_300MHZ|counter_100 [10]),
        .prn(vcc));
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[10] .is_wysiwyg = "true";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[10] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y7_N48
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|LessThan16~1 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|LessThan16~1_combout  = ( !\R_400_to_2_5_10_100_200_300MHZ|counter_100 [9] & ( (\R_400_to_2_5_10_100_200_300MHZ|LessThan16~0_combout  & (!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [10] & 
// (!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [7] & !\R_400_to_2_5_10_100_200_300MHZ|counter_100 [8]))) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|LessThan16~0_combout ),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [10]),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [7]),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [8]),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [9]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|LessThan16~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|LessThan16~1 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|LessThan16~1 .lut_mask = 64'h4000400000000000;
defparam \R_400_to_2_5_10_100_200_300MHZ|LessThan16~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y7_N0
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add1~9 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Add1~9_sumout  = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [0] ) + ( VCC ) + ( !VCC ))
// \R_400_to_2_5_10_100_200_300MHZ|Add1~10  = CARRY(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [0] ) + ( VCC ) + ( !VCC ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(),
        .sumout(\R_400_to_2_5_10_100_200_300MHZ|Add1~9_sumout ),
        .cout(\R_400_to_2_5_10_100_200_300MHZ|Add1~10 ),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~9 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~9 .lut_mask = 64'h0000000000000F0F;
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y7_N30
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter_100~3 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter_100~3_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|Add1~9_sumout  & ( \R_400_to_2_5_10_100_200_300MHZ|counter_100~0_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter_100~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add1~9_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter_100~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~3 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~3 .lut_mask = 64'h000000000F0F0F0F;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y7_N32
dffeas \R_400_to_2_5_10_100_200_300MHZ|counter_100[0] (
        .clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),
        .d(\R_400_to_2_5_10_100_200_300MHZ|counter_100~3_combout ),
        .asdata(vcc),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\R_400_to_2_5_10_100_200_300MHZ|counter_100 [0]),
        .prn(vcc));
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[0] .is_wysiwyg = "true";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y7_N48
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter_100~0 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter_100~0_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [1] & ( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [0] & ( (!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [2] & 
// (\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock  & \R_400_to_2_5_10_100_200_300MHZ|LessThan16~1_combout )) ) ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|counter_100 [1] & ( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [0] & ( 
// (!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [2] & (\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock  & \R_400_to_2_5_10_100_200_300MHZ|LessThan16~1_combout )) ) ) ) # ( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [1] & ( 
// !\R_400_to_2_5_10_100_200_300MHZ|counter_100 [0] & ( (!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [2] & (\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock  & \R_400_to_2_5_10_100_200_300MHZ|LessThan16~1_combout )) ) ) ) # ( 
// !\R_400_to_2_5_10_100_200_300MHZ|counter_100 [1] & ( !\R_400_to_2_5_10_100_200_300MHZ|counter_100 [0] & ( (\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock  & \R_400_to_2_5_10_100_200_300MHZ|LessThan16~1_combout ) ) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [2]),
        .datab(gnd),
        .datac(!\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock ),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|LessThan16~1_combout ),
        .datae(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [1]),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter_100~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~0 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~0 .lut_mask = 64'h000F000A000A000A;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y7_N3
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add1~1 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Add1~1_sumout  = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [1] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~10  ))
// \R_400_to_2_5_10_100_200_300MHZ|Add1~2  = CARRY(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [1] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~10  ))

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\R_400_to_2_5_10_100_200_300MHZ|Add1~10 ),
        .sharein(gnd),
        .combout(),
        .sumout(\R_400_to_2_5_10_100_200_300MHZ|Add1~1_sumout ),
        .cout(\R_400_to_2_5_10_100_200_300MHZ|Add1~2 ),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~1 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~1 .lut_mask = 64'h0000FFFF00005555;
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y7_N45
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter_100~1 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter_100~1_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|Add1~1_sumout  & ( \R_400_to_2_5_10_100_200_300MHZ|counter_100~0_combout  ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter_100~0_combout ),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add1~1_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter_100~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~1 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~1 .lut_mask = 64'h0000000055555555;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y7_N47
dffeas \R_400_to_2_5_10_100_200_300MHZ|counter_100[1] (
        .clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),
        .d(\R_400_to_2_5_10_100_200_300MHZ|counter_100~1_combout ),
        .asdata(vcc),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\R_400_to_2_5_10_100_200_300MHZ|counter_100 [1]),
        .prn(vcc));
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[1] .is_wysiwyg = "true";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y7_N24
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter_100~2 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter_100~2_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|Add1~5_sumout  & ( \R_400_to_2_5_10_100_200_300MHZ|counter_100~0_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\R_400_to_2_5_10_100_200_300MHZ|Add1~5_sumout ),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter_100~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter_100~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~2 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~2 .lut_mask = 64'h000000000000FFFF;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y7_N26
dffeas \R_400_to_2_5_10_100_200_300MHZ|counter_100[2] (
        .clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),
        .d(\R_400_to_2_5_10_100_200_300MHZ|counter_100~2_combout ),
        .asdata(vcc),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\R_400_to_2_5_10_100_200_300MHZ|counter_100 [2]),
        .prn(vcc));
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[2] .is_wysiwyg = "true";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y7_N3
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~0 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~0_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [1] & ( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [0] & ( (\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock  & 
// ((!\R_400_to_2_5_10_100_200_300MHZ|LessThan16~1_combout ) # (\R_400_to_2_5_10_100_200_300MHZ|counter_100 [2]))) ) ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|counter_100 [1] & ( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [0] & ( 
// \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock  ) ) ) # ( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [1] & ( !\R_400_to_2_5_10_100_200_300MHZ|counter_100 [0] & ( (\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock  & 
// ((!\R_400_to_2_5_10_100_200_300MHZ|LessThan16~1_combout ) # (\R_400_to_2_5_10_100_200_300MHZ|counter_100 [2]))) ) ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|counter_100 [1] & ( !\R_400_to_2_5_10_100_200_300MHZ|counter_100 [0] & ( 
// (\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock  & ((!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [2]) # (!\R_400_to_2_5_10_100_200_300MHZ|LessThan16~1_combout ))) ) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [2]),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|LessThan16~1_combout ),
        .datac(gnd),
        .datad(!\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock ),
        .datae(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [1]),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~0 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~0 .lut_mask = 64'h00EE00DD00FF00DD;
defparam \R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y7_N5
dffeas \R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i (
        .clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),
        .d(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~0_combout ),
        .asdata(vcc),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .prn(vcc));
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i .is_wysiwyg = "true";
defparam \R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y10_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|counter_writer[0]~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|counter_writer[0]~0_combout  = !\A_SPW_TOP|tx_data|counter_writer [0]

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|tx_data|counter_writer [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|counter_writer[0]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|counter_writer[0]~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|counter_writer[0]~0 .lut_mask = 64'hF0F0F0F0F0F0F0F0;
defparam \A_SPW_TOP|tx_data|counter_writer[0]~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y10_N45
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Add1~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Add1~1_combout  = ( \A_SPW_TOP|tx_data|counter_writer [0] & ( !\A_SPW_TOP|tx_data|counter_writer [1] $ (!\A_SPW_TOP|tx_data|counter_writer [2]) ) ) # ( !\A_SPW_TOP|tx_data|counter_writer [0] & ( \A_SPW_TOP|tx_data|counter_writer [2] ) )

        .dataa(!\A_SPW_TOP|tx_data|counter_writer [1]),
        .datab(!\A_SPW_TOP|tx_data|counter_writer [2]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|counter_writer [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Add1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Add1~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Add1~1 .lut_mask = 64'h3333333366666666;
defparam \A_SPW_TOP|tx_data|Add1~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y10_N14
dffeas \A_SPW_TOP|tx_data|counter_writer[2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Add1~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|tx_data|state_data_write.10~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|counter_writer [2]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|counter_writer[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|counter_writer[2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y10_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Add1~2 (
// Equation(s):
// \A_SPW_TOP|tx_data|Add1~2_combout  = ( \A_SPW_TOP|tx_data|counter_writer [3] & ( (!\A_SPW_TOP|tx_data|counter_writer [2]) # ((!\A_SPW_TOP|tx_data|counter_writer [1]) # (!\A_SPW_TOP|tx_data|counter_writer [0])) ) ) # ( !\A_SPW_TOP|tx_data|counter_writer 
// [3] & ( (\A_SPW_TOP|tx_data|counter_writer [2] & (\A_SPW_TOP|tx_data|counter_writer [1] & \A_SPW_TOP|tx_data|counter_writer [0])) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|tx_data|counter_writer [2]),
        .datac(!\A_SPW_TOP|tx_data|counter_writer [1]),
        .datad(!\A_SPW_TOP|tx_data|counter_writer [0]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|counter_writer [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Add1~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Add1~2 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Add1~2 .lut_mask = 64'h00030003FFFCFFFC;
defparam \A_SPW_TOP|tx_data|Add1~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y10_N17
dffeas \A_SPW_TOP|tx_data|counter_writer[3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Add1~2_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|tx_data|state_data_write.10~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|counter_writer [3]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|counter_writer[3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|counter_writer[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X36_Y10_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Add1~3 (
// Equation(s):
// \A_SPW_TOP|tx_data|Add1~3_combout  = ( \A_SPW_TOP|tx_data|counter_writer [2] & ( !\A_SPW_TOP|tx_data|counter_writer [4] $ (((!\A_SPW_TOP|tx_data|counter_writer [1]) # ((!\A_SPW_TOP|tx_data|counter_writer [0]) # (!\A_SPW_TOP|tx_data|counter_writer [3])))) 
// ) ) # ( !\A_SPW_TOP|tx_data|counter_writer [2] & ( \A_SPW_TOP|tx_data|counter_writer [4] ) )

        .dataa(!\A_SPW_TOP|tx_data|counter_writer [1]),
        .datab(!\A_SPW_TOP|tx_data|counter_writer [0]),
        .datac(!\A_SPW_TOP|tx_data|counter_writer [3]),
        .datad(!\A_SPW_TOP|tx_data|counter_writer [4]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|counter_writer [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Add1~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Add1~3 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Add1~3 .lut_mask = 64'h00FF00FF01FE01FE;
defparam \A_SPW_TOP|tx_data|Add1~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y10_N2
dffeas \A_SPW_TOP|tx_data|counter_writer[4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Add1~3_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|tx_data|state_data_write.10~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|counter_writer [4]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|counter_writer[4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|counter_writer[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X35_Y10_N33
cyclonev_lcell_comb \A_SPW_TOP|tx_data|counter_reader[0]~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|counter_reader[0]~0_combout  = ( !\A_SPW_TOP|tx_data|counter_reader [0] )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|counter_reader [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|counter_reader[0]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|counter_reader[0]~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|counter_reader[0]~0 .lut_mask = 64'hFFFFFFFF00000000;
defparam \A_SPW_TOP|tx_data|counter_reader[0]~0 .shared_arith = "off";
// synopsys translate_on

// Location: IOIBUF_X51_Y0_N1
cyclonev_io_ibuf \sin_a~input (
        .i(sin_a),
        .ibar(\sin_a(n) ),
        .dynamicterminationcontrol(gnd),
        .o(\sin_a~input_o ));
// synopsys translate_off
defparam \sin_a~input .bus_hold = "false";
defparam \sin_a~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X46_Y0_N1
cyclonev_io_ibuf \din_a~input (
        .i(din_a),
        .ibar(\din_a(n) ),
        .dynamicterminationcontrol(gnd),
        .o(\din_a~input_o ));
// synopsys translate_off
defparam \din_a~input .bus_hold = "false";
defparam \din_a~input .simulate_z_as = "z";
// synopsys translate_on

// Location: LABCELL_X48_Y2_N57
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|always3~0 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|always3~0_combout  = LCELL(( \din_a~input_o  & ( !\sin_a~input_o  ) ) # ( !\din_a~input_o  & ( \sin_a~input_o  ) ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\sin_a~input_o ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\din_a~input_o ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|always3~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|always3~0 .lut_mask = 64'h0F0F0F0FF0F0F0F0;
defparam \A_SPW_TOP|SPW|RX|always3~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y3_N42
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|counter_neg[0]~feeder (
// Equation(s):
// \A_SPW_TOP|SPW|RX|counter_neg[0]~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|counter_neg[0]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|counter_neg[0]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|counter_neg[0]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \A_SPW_TOP|SPW|RX|counter_neg[0]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y3_N12
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|always2~0 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|always2~0_combout  = LCELL(( \A_SPW_TOP|SPW|RX|counter_neg [2] & ( \A_SPW_TOP|SPW|RX|always3~0_combout  & ( (\A_SPW_TOP|SPW|RX|Selector0~0_combout  & !\A_SPW_TOP|SPW|RX|counter_neg [1]) ) ) ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|RX|Selector0~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|counter_neg [1]),
        .datae(!\A_SPW_TOP|SPW|RX|counter_neg [2]),
        .dataf(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|always2~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|always2~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|always2~0 .lut_mask = 64'h0000000000000F00;
defparam \A_SPW_TOP|SPW|RX|always2~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y3_N45
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|ready_data_p (
// Equation(s):
// \A_SPW_TOP|SPW|RX|ready_data_p~combout  = LCELL(( \A_SPW_TOP|SPW|RX|always3~0_combout  & ( (\A_SPW_TOP|SPW|RX|Selector1~0_combout  & (!\A_SPW_TOP|SPW|RX|counter_neg [4] & (!\A_SPW_TOP|SPW|RX|always2~0_combout  & \A_SPW_TOP|SPW|RX|counter_neg [5]))) ) ))

        .dataa(!\A_SPW_TOP|SPW|RX|Selector1~0_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|counter_neg [4]),
        .datac(!\A_SPW_TOP|SPW|RX|always2~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|counter_neg [5]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|ready_data_p~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|ready_data_p .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|ready_data_p .lut_mask = 64'h0000000000400040;
defparam \A_SPW_TOP|SPW|RX|ready_data_p .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y3_N18
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|ready_data (
// Equation(s):
// \A_SPW_TOP|SPW|RX|ready_data~combout  = LCELL(( !\A_SPW_TOP|SPW|RX|always3~0_combout  & ( (!\A_SPW_TOP|SPW|RX|always1~0_combout  & (!\A_SPW_TOP|SPW|RX|counter_neg [4] & (\A_SPW_TOP|SPW|RX|Selector1~0_combout  & \A_SPW_TOP|SPW|RX|counter_neg [5]))) ) ))

        .dataa(!\A_SPW_TOP|SPW|RX|always1~0_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|counter_neg [4]),
        .datac(!\A_SPW_TOP|SPW|RX|Selector1~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|counter_neg [5]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|ready_data~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|ready_data .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|ready_data .lut_mask = 64'h0008000800000000;
defparam \A_SPW_TOP|SPW|RX|ready_data .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y2_N24
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|bit_d_1~feeder (
// Equation(s):
// \A_SPW_TOP|SPW|RX|bit_d_1~feeder_combout  = ( \din_a~input_o  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\din_a~input_o ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|bit_d_1~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|bit_d_1~feeder .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|bit_d_1~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|SPW|RX|bit_d_1~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y2_N26
dffeas \A_SPW_TOP|SPW|RX|bit_d_1 (
        .clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(\A_SPW_TOP|SPW|RX|bit_d_1~feeder_combout ),
        .asdata(vcc),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|bit_d_1~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|bit_d_1 .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|bit_d_1 .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y2_N0
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|bit_d_3~feeder (
// Equation(s):
// \A_SPW_TOP|SPW|RX|bit_d_3~feeder_combout  = ( \A_SPW_TOP|SPW|RX|bit_d_1~q  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|bit_d_1~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|bit_d_3~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|bit_d_3~feeder .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|bit_d_3~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|SPW|RX|bit_d_3~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y2_N2
dffeas \A_SPW_TOP|SPW|RX|bit_d_3 (
        .clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(\A_SPW_TOP|SPW|RX|bit_d_3~feeder_combout ),
        .asdata(vcc),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|bit_d_3~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|bit_d_3 .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|bit_d_3 .power_up = "low";
// synopsys translate_on

// Location: FF_X48_Y2_N5
dffeas \A_SPW_TOP|SPW|RX|bit_d_5 (
        .clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|RX|bit_d_3~q ),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|bit_d_5~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|bit_d_5 .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|bit_d_5 .power_up = "low";
// synopsys translate_on

// Location: FF_X48_Y2_N35
dffeas \A_SPW_TOP|SPW|RX|bit_d_7 (
        .clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|RX|bit_d_5~q ),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|bit_d_7~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|bit_d_7 .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|bit_d_7 .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y2_N27
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|bit_d_9~feeder (
// Equation(s):
// \A_SPW_TOP|SPW|RX|bit_d_9~feeder_combout  = ( \A_SPW_TOP|SPW|RX|bit_d_7~q  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|bit_d_7~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|bit_d_9~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|bit_d_9~feeder .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|bit_d_9~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|SPW|RX|bit_d_9~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y2_N28
dffeas \A_SPW_TOP|SPW|RX|bit_d_9 (
        .clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(\A_SPW_TOP|SPW|RX|bit_d_9~feeder_combout ),
        .asdata(vcc),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|bit_d_9~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|bit_d_9 .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|bit_d_9 .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y2_N36
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|parity_rec_d~feeder (
// Equation(s):
// \A_SPW_TOP|SPW|RX|parity_rec_d~feeder_combout  = ( \A_SPW_TOP|SPW|RX|bit_d_9~q  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|bit_d_9~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|parity_rec_d~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|parity_rec_d~feeder .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|parity_rec_d~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|SPW|RX|parity_rec_d~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y2_N38
dffeas \A_SPW_TOP|SPW|RX|parity_rec_d (
        .clk(\A_SPW_TOP|SPW|RX|ready_data~combout ),
        .d(\A_SPW_TOP|SPW|RX|parity_rec_d~feeder_combout ),
        .asdata(vcc),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|parity_rec_d~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|parity_rec_d .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|parity_rec_d .power_up = "low";
// synopsys translate_on

// Location: FF_X48_Y2_N14
dffeas \A_SPW_TOP|SPW|RX|bit_d_0 (
        .clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(gnd),
        .asdata(\din_a~input_o ),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|bit_d_0~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|bit_d_0 .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|bit_d_0 .power_up = "low";
// synopsys translate_on

// Location: FF_X48_Y2_N50
dffeas \A_SPW_TOP|SPW|RX|bit_d_2 (
        .clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|RX|bit_d_0~q ),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|bit_d_2~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|bit_d_2 .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|bit_d_2 .power_up = "low";
// synopsys translate_on

// Location: FF_X48_Y2_N38
dffeas \A_SPW_TOP|SPW|RX|bit_d_4 (
        .clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|RX|bit_d_2~q ),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|bit_d_4~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|bit_d_4 .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|bit_d_4 .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y2_N33
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|bit_d_6~feeder (
// Equation(s):
// \A_SPW_TOP|SPW|RX|bit_d_6~feeder_combout  = ( \A_SPW_TOP|SPW|RX|bit_d_4~q  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|bit_d_4~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|bit_d_6~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|bit_d_6~feeder .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|bit_d_6~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|SPW|RX|bit_d_6~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y2_N35
dffeas \A_SPW_TOP|SPW|RX|bit_d_6 (
        .clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(\A_SPW_TOP|SPW|RX|bit_d_6~feeder_combout ),
        .asdata(vcc),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|bit_d_6~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|bit_d_6 .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|bit_d_6 .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y2_N12
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|bit_d_8~feeder (
// Equation(s):
// \A_SPW_TOP|SPW|RX|bit_d_8~feeder_combout  = ( \A_SPW_TOP|SPW|RX|bit_d_6~q  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|bit_d_6~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|bit_d_8~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|bit_d_8~feeder .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|bit_d_8~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|SPW|RX|bit_d_8~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y2_N14
dffeas \A_SPW_TOP|SPW|RX|bit_d_8 (
        .clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(\A_SPW_TOP|SPW|RX|bit_d_8~feeder_combout ),
        .asdata(vcc),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|bit_d_8~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|bit_d_8 .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|bit_d_8 .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y2_N18
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|dta_timec[8]~feeder (
// Equation(s):
// \A_SPW_TOP|SPW|RX|dta_timec[8]~feeder_combout  = ( \A_SPW_TOP|SPW|RX|bit_d_8~q  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|bit_d_8~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|dta_timec[8]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|dta_timec[8]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|dta_timec[8]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|SPW|RX|dta_timec[8]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y2_N20
dffeas \A_SPW_TOP|SPW|RX|dta_timec[8] (
        .clk(\A_SPW_TOP|SPW|RX|ready_data~combout ),
        .d(\A_SPW_TOP|SPW|RX|dta_timec[8]~feeder_combout ),
        .asdata(vcc),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|dta_timec [8]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|dta_timec[8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|dta_timec[8] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y2_N27
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|always15~0 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|always15~0_combout  = ( !\A_SPW_TOP|SPW|RX|parity_rec_d~q  & ( \A_SPW_TOP|SPW|RX|dta_timec [8] ) ) # ( \A_SPW_TOP|SPW|RX|parity_rec_d~q  & ( !\A_SPW_TOP|SPW|RX|dta_timec [8] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\A_SPW_TOP|SPW|RX|parity_rec_d~q ),
        .dataf(!\A_SPW_TOP|SPW|RX|dta_timec [8]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|always15~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|always15~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|always15~0 .lut_mask = 64'h0000FFFFFFFF0000;
defparam \A_SPW_TOP|SPW|RX|always15~0 .shared_arith = "off";
// synopsys translate_on

// Location: DDIOINCELL_X46_Y0_N14
dffeas \A_SPW_TOP|SPW|RX|control_bit_found (
        .clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(\din_a~input_o ),
        .asdata(vcc),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|control_bit_found~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|control_bit_found .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|control_bit_found .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y3_N6
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|Selector0~1 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|Selector0~1_combout  = ( !\A_SPW_TOP|SPW|RX|counter_neg [3] & ( !\A_SPW_TOP|SPW|RX|counter_neg [4] & ( (\A_SPW_TOP|SPW|RX|counter_neg [0] & ((!\A_SPW_TOP|SPW|RX|counter_neg [5] & (!\A_SPW_TOP|SPW|RX|counter_neg [2] $ 
// (!\A_SPW_TOP|SPW|RX|counter_neg [1]))) # (\A_SPW_TOP|SPW|RX|counter_neg [5] & (!\A_SPW_TOP|SPW|RX|counter_neg [2] & !\A_SPW_TOP|SPW|RX|counter_neg [1])))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|counter_neg [5]),
        .datab(!\A_SPW_TOP|SPW|RX|counter_neg [0]),
        .datac(!\A_SPW_TOP|SPW|RX|counter_neg [2]),
        .datad(!\A_SPW_TOP|SPW|RX|counter_neg [1]),
        .datae(!\A_SPW_TOP|SPW|RX|counter_neg [3]),
        .dataf(!\A_SPW_TOP|SPW|RX|counter_neg [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|Selector0~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|Selector0~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|Selector0~1 .lut_mask = 64'h1220000000000000;
defparam \A_SPW_TOP|SPW|RX|Selector0~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y3_N12
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|Selector0~3 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|Selector0~3_combout  = ( \A_SPW_TOP|SPW|RX|Selector0~1_combout  & ( (\A_SPW_TOP|SPW|RX|Selector0~2_combout  & (\A_SPW_TOP|SPW|RX|counter_neg [1] & \A_SPW_TOP|SPW|RX|control_bit_found~q )) ) ) # ( !\A_SPW_TOP|SPW|RX|Selector0~1_combout  & 
// ( \A_SPW_TOP|SPW|RX|is_control~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|Selector0~2_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|counter_neg [1]),
        .datac(!\A_SPW_TOP|SPW|RX|control_bit_found~q ),
        .datad(!\A_SPW_TOP|SPW|RX|is_control~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|Selector0~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|Selector0~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|Selector0~3 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|Selector0~3 .lut_mask = 64'h00FF00FF01010101;
defparam \A_SPW_TOP|SPW|RX|Selector0~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y3_N59
dffeas \A_SPW_TOP|SPW|RX|is_control (
        .clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|RX|Selector0~3_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|is_control~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|is_control .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|is_control .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y3_N45
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|ready_data_p_r~0 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|ready_data_p_r~0_combout  = ( !\A_SPW_TOP|SPW|RX|is_control~q  & ( \A_SPW_TOP|SPW|RX|ready_data~combout  ) ) # ( !\A_SPW_TOP|SPW|RX|is_control~q  & ( !\A_SPW_TOP|SPW|RX|ready_data~combout  & ( \A_SPW_TOP|SPW|RX|ready_data_p~combout  ) ) 
// )

        .dataa(!\A_SPW_TOP|SPW|RX|ready_data_p~combout ),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\A_SPW_TOP|SPW|RX|is_control~q ),
        .dataf(!\A_SPW_TOP|SPW|RX|ready_data~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|ready_data_p_r~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|ready_data_p_r~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|ready_data_p_r~0 .lut_mask = 64'h55550000FFFF0000;
defparam \A_SPW_TOP|SPW|RX|ready_data_p_r~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y3_N47
dffeas \A_SPW_TOP|SPW|RX|ready_data_p_r (
        .clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(\A_SPW_TOP|SPW|RX|ready_data_p_r~0_combout ),
        .asdata(vcc),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|ready_data_p_r~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|ready_data_p_r .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|ready_data_p_r .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y3_N24
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|last_is_control~0 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|last_is_control~0_combout  = ( \A_SPW_TOP|SPW|RX|last_is_control~q  & ( (!\A_SPW_TOP|SPW|RX|ready_data_p_r~q ) # (\A_SPW_TOP|SPW|RX|ready_control_p_r~q ) ) ) # ( !\A_SPW_TOP|SPW|RX|last_is_control~q  & ( 
// \A_SPW_TOP|SPW|RX|ready_control_p_r~q  ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),
        .datac(!\A_SPW_TOP|SPW|RX|ready_data_p_r~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|last_is_control~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|last_is_control~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|last_is_control~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|last_is_control~0 .lut_mask = 64'h33333333F3F3F3F3;
defparam \A_SPW_TOP|SPW|RX|last_is_control~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y3_N51
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|next_state_data_process.01~0 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|next_state_data_process.01~0_combout  = ( \A_SPW_TOP|SPW|RX|ready_control_p_r~q  & ( !\A_SPW_TOP|SPW|RX|state_data_process.01~q  ) ) # ( !\A_SPW_TOP|SPW|RX|ready_control_p_r~q  & ( (!\A_SPW_TOP|SPW|RX|state_data_process.01~q  & 
// \A_SPW_TOP|SPW|RX|ready_data_p_r~q ) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|state_data_process.01~q ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|RX|ready_data_p_r~q ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|next_state_data_process.01~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|next_state_data_process.01~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|next_state_data_process.01~0 .lut_mask = 64'h0A0AAAAA0A0AAAAA;
defparam \A_SPW_TOP|SPW|RX|next_state_data_process.01~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y3_N3
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|state_data_process.01~feeder (
// Equation(s):
// \A_SPW_TOP|SPW|RX|state_data_process.01~feeder_combout  = ( \A_SPW_TOP|SPW|RX|next_state_data_process.01~0_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|next_state_data_process.01~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|state_data_process.01~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|state_data_process.01~feeder .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|state_data_process.01~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|SPW|RX|state_data_process.01~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y3_N5
dffeas \A_SPW_TOP|SPW|RX|state_data_process.01 (
        .clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(\A_SPW_TOP|SPW|RX|state_data_process.01~feeder_combout ),
        .asdata(vcc),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|state_data_process.01~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|state_data_process.01 .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|state_data_process.01 .power_up = "low";
// synopsys translate_on

// Location: FF_X47_Y3_N11
dffeas \A_SPW_TOP|SPW|RX|last_is_control (
        .clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|RX|last_is_control~0_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(!\A_SPW_TOP|SPW|RX|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|last_is_control~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|last_is_control .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|last_is_control .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y3_N39
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|rx_error_c~0 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|rx_error_c~0_combout  = ( \A_SPW_TOP|SPW|RX|last_is_data~q  & ( !\A_SPW_TOP|SPW|RX|last_is_control~q  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\A_SPW_TOP|SPW|RX|last_is_data~q ),
        .dataf(!\A_SPW_TOP|SPW|RX|last_is_control~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|rx_error_c~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_error_c~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|rx_error_c~0 .lut_mask = 64'h0000FFFF00000000;
defparam \A_SPW_TOP|SPW|RX|rx_error_c~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y3_N41
dffeas \A_SPW_TOP|SPW|RX|bit_c_1 (
        .clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(gnd),
        .asdata(\din_a~input_o ),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|bit_c_1~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|bit_c_1 .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|bit_c_1 .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y3_N27
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|control_r[1]~feeder (
// Equation(s):
// \A_SPW_TOP|SPW|RX|control_r[1]~feeder_combout  = ( \A_SPW_TOP|SPW|RX|bit_c_1~q  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|bit_c_1~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|control_r[1]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|control_r[1]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|control_r[1]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|SPW|RX|control_r[1]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y3_N28
dffeas \A_SPW_TOP|SPW|RX|control_r[1] (
        .clk(\A_SPW_TOP|SPW|RX|always1~0_combout ),
        .d(\A_SPW_TOP|SPW|RX|control_r[1]~feeder_combout ),
        .asdata(vcc),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|control_r [1]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|control_r[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|control_r[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X50_Y3_N14
dffeas \A_SPW_TOP|SPW|RX|control_p_r[1] (
        .clk(\A_SPW_TOP|SPW|RX|always2~0_combout ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|RX|control_r [1]),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|control_p_r [1]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|control_p_r[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|control_p_r[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y3_N57
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|control~1 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|control~1_combout  = (!\A_SPW_TOP|SPW|RX|ready_control_p_r~q  & (\A_SPW_TOP|SPW|RX|control [1])) # (\A_SPW_TOP|SPW|RX|ready_control_p_r~q  & ((\A_SPW_TOP|SPW|RX|control_p_r [1])))

        .dataa(gnd),
        .datab(!\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),
        .datac(!\A_SPW_TOP|SPW|RX|control [1]),
        .datad(!\A_SPW_TOP|SPW|RX|control_p_r [1]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|control~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|control~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|control~1 .lut_mask = 64'h0C3F0C3F0C3F0C3F;
defparam \A_SPW_TOP|SPW|RX|control~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y3_N17
dffeas \A_SPW_TOP|SPW|RX|control[1] (
        .clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|RX|control~1_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(!\A_SPW_TOP|SPW|RX|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|control [1]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|control[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|control[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X49_Y3_N29
dffeas \A_SPW_TOP|SPW|RX|bit_c_0 (
        .clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(gnd),
        .asdata(\din_a~input_o ),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|bit_c_0~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|bit_c_0 .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|bit_c_0 .power_up = "low";
// synopsys translate_on

// Location: FF_X50_Y3_N49
dffeas \A_SPW_TOP|SPW|RX|control_r[0] (
        .clk(\A_SPW_TOP|SPW|RX|always1~0_combout ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|RX|bit_c_0~q ),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|control_r [0]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|control_r[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|control_r[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X50_Y3_N17
dffeas \A_SPW_TOP|SPW|RX|control_p_r[0] (
        .clk(\A_SPW_TOP|SPW|RX|always2~0_combout ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|RX|control_r [0]),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|control_p_r [0]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|control_p_r[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|control_p_r[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y3_N48
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|control~2 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|control~2_combout  = ( \A_SPW_TOP|SPW|RX|control_p_r [0] & ( (\A_SPW_TOP|SPW|RX|control [0]) # (\A_SPW_TOP|SPW|RX|ready_control_p_r~q ) ) ) # ( !\A_SPW_TOP|SPW|RX|control_p_r [0] & ( (!\A_SPW_TOP|SPW|RX|ready_control_p_r~q  & 
// \A_SPW_TOP|SPW|RX|control [0]) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),
        .datac(gnd),
        .datad(!\A_SPW_TOP|SPW|RX|control [0]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|control_p_r [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|control~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|control~2 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|control~2 .lut_mask = 64'h00CC00CC33FF33FF;
defparam \A_SPW_TOP|SPW|RX|control~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y3_N35
dffeas \A_SPW_TOP|SPW|RX|control[0] (
        .clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|RX|control~2_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(!\A_SPW_TOP|SPW|RX|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|control [0]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|control[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|control[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y3_N30
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|rx_error_d~0 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|rx_error_d~0_combout  = ( \A_SPW_TOP|SPW|RX|control [0] & ( (\A_SPW_TOP|SPW|RX|last_is_control~q  & (!\A_SPW_TOP|SPW|RX|control [1] $ (!\A_SPW_TOP|SPW|RX|parity_rec_d~q  $ (\A_SPW_TOP|SPW|RX|dta_timec [8])))) ) ) # ( 
// !\A_SPW_TOP|SPW|RX|control [0] & ( (\A_SPW_TOP|SPW|RX|last_is_control~q  & (!\A_SPW_TOP|SPW|RX|control [1] $ (!\A_SPW_TOP|SPW|RX|parity_rec_d~q  $ (!\A_SPW_TOP|SPW|RX|dta_timec [8])))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|control [1]),
        .datab(!\A_SPW_TOP|SPW|RX|parity_rec_d~q ),
        .datac(!\A_SPW_TOP|SPW|RX|dta_timec [8]),
        .datad(!\A_SPW_TOP|SPW|RX|last_is_control~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|control [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|rx_error_d~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_error_d~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|rx_error_d~0 .lut_mask = 64'h0096009600690069;
defparam \A_SPW_TOP|SPW|RX|rx_error_d~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y2_N54
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|dta_timec[3]~feeder (
// Equation(s):
// \A_SPW_TOP|SPW|RX|dta_timec[3]~feeder_combout  = ( \A_SPW_TOP|SPW|RX|bit_d_4~q  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|bit_d_4~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|dta_timec[3]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|dta_timec[3]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|dta_timec[3]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|SPW|RX|dta_timec[3]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y2_N55
dffeas \A_SPW_TOP|SPW|RX|dta_timec[3] (
        .clk(\A_SPW_TOP|SPW|RX|ready_data~combout ),
        .d(\A_SPW_TOP|SPW|RX|dta_timec[3]~feeder_combout ),
        .asdata(vcc),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|dta_timec [3]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|dta_timec[3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|dta_timec[3] .power_up = "low";
// synopsys translate_on

// Location: FF_X49_Y2_N47
dffeas \A_SPW_TOP|SPW|RX|dta_timec_p[3] (
        .clk(\A_SPW_TOP|SPW|RX|ready_data_p~combout ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|RX|dta_timec [3]),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|dta_timec_p [3]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[3] .power_up = "low";
// synopsys translate_on

// Location: FF_X49_Y3_N1
dffeas \A_SPW_TOP|SPW|RX|bit_c_2 (
        .clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|RX|bit_c_0~q ),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|bit_c_2~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|bit_c_2 .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|bit_c_2 .power_up = "low";
// synopsys translate_on

// Location: FF_X50_Y3_N53
dffeas \A_SPW_TOP|SPW|RX|control_r[2] (
        .clk(\A_SPW_TOP|SPW|RX|always1~0_combout ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|RX|bit_c_2~q ),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|control_r [2]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|control_r[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|control_r[2] .power_up = "low";
// synopsys translate_on

// Location: FF_X50_Y3_N32
dffeas \A_SPW_TOP|SPW|RX|control_p_r[2] (
        .clk(\A_SPW_TOP|SPW|RX|always2~0_combout ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|RX|control_r [2]),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|control_p_r [2]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|control_p_r[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|control_p_r[2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y3_N6
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|control~0 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|control~0_combout  = (!\A_SPW_TOP|SPW|RX|ready_control_p_r~q  & ((\A_SPW_TOP|SPW|RX|control [2]))) # (\A_SPW_TOP|SPW|RX|ready_control_p_r~q  & (\A_SPW_TOP|SPW|RX|control_p_r [2]))

        .dataa(gnd),
        .datab(!\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),
        .datac(!\A_SPW_TOP|SPW|RX|control_p_r [2]),
        .datad(!\A_SPW_TOP|SPW|RX|control [2]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|control~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|control~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|control~0 .lut_mask = 64'h03CF03CF03CF03CF;
defparam \A_SPW_TOP|SPW|RX|control~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y3_N3
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|control[2]~feeder (
// Equation(s):
// \A_SPW_TOP|SPW|RX|control[2]~feeder_combout  = ( \A_SPW_TOP|SPW|RX|control~0_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|control~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|control[2]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|control[2]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|control[2]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|SPW|RX|control[2]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y3_N5
dffeas \A_SPW_TOP|SPW|RX|control[2] (
        .clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(\A_SPW_TOP|SPW|RX|control[2]~feeder_combout ),
        .asdata(vcc),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(!\A_SPW_TOP|SPW|RX|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|control [2]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|control[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|control[2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y3_N33
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|data~0 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|data~0_combout  = ( \A_SPW_TOP|SPW|RX|ready_data_p_r~q  & ( (\A_SPW_TOP|SPW|RX|control [2] & (\A_SPW_TOP|SPW|RX|control [1] & \A_SPW_TOP|SPW|RX|control [0])) ) ) # ( !\A_SPW_TOP|SPW|RX|ready_data_p_r~q  )

        .dataa(!\A_SPW_TOP|SPW|RX|control [2]),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|RX|control [1]),
        .datad(!\A_SPW_TOP|SPW|RX|control [0]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|ready_data_p_r~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|data~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|data~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|data~0 .lut_mask = 64'hFFFFFFFF00050005;
defparam \A_SPW_TOP|SPW|RX|data~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y2_N3
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|data~5 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|data~5_combout  = ( \A_SPW_TOP|SPW|RX|data [3] & ( \A_SPW_TOP|SPW|RX|data~0_combout  ) ) # ( \A_SPW_TOP|SPW|RX|data [3] & ( !\A_SPW_TOP|SPW|RX|data~0_combout  & ( (\A_SPW_TOP|SPW|RX|ready_control_p_r~q ) # (\A_SPW_TOP|SPW|RX|dta_timec_p 
// [3]) ) ) ) # ( !\A_SPW_TOP|SPW|RX|data [3] & ( !\A_SPW_TOP|SPW|RX|data~0_combout  & ( (\A_SPW_TOP|SPW|RX|dta_timec_p [3] & !\A_SPW_TOP|SPW|RX|ready_control_p_r~q ) ) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|dta_timec_p [3]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),
        .datae(!\A_SPW_TOP|SPW|RX|data [3]),
        .dataf(!\A_SPW_TOP|SPW|RX|data~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|data~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|data~5 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|data~5 .lut_mask = 64'h550055FF0000FFFF;
defparam \A_SPW_TOP|SPW|RX|data~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y2_N2
dffeas \A_SPW_TOP|SPW|RX|data[3] (
        .clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|RX|data~5_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(!\A_SPW_TOP|SPW|RX|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|data [3]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|data[3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|data[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y2_N15
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|dta_timec[6]~feeder (
// Equation(s):
// \A_SPW_TOP|SPW|RX|dta_timec[6]~feeder_combout  = ( \A_SPW_TOP|SPW|RX|bit_d_1~q  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|bit_d_1~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|dta_timec[6]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|dta_timec[6]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|dta_timec[6]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|SPW|RX|dta_timec[6]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y2_N17
dffeas \A_SPW_TOP|SPW|RX|dta_timec[6] (
        .clk(\A_SPW_TOP|SPW|RX|ready_data~combout ),
        .d(\A_SPW_TOP|SPW|RX|dta_timec[6]~feeder_combout ),
        .asdata(vcc),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|dta_timec [6]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|dta_timec[6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|dta_timec[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y2_N51
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|dta_timec_p[6]~feeder (
// Equation(s):
// \A_SPW_TOP|SPW|RX|dta_timec_p[6]~feeder_combout  = ( \A_SPW_TOP|SPW|RX|dta_timec [6] )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|dta_timec [6]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|dta_timec_p[6]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[6]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[6]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[6]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y2_N52
dffeas \A_SPW_TOP|SPW|RX|dta_timec_p[6] (
        .clk(\A_SPW_TOP|SPW|RX|ready_data_p~combout ),
        .d(\A_SPW_TOP|SPW|RX|dta_timec_p[6]~feeder_combout ),
        .asdata(vcc),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|dta_timec_p [6]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y2_N54
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|data~2 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|data~2_combout  = ( \A_SPW_TOP|SPW|RX|data~0_combout  & ( \A_SPW_TOP|SPW|RX|data [6] ) ) # ( !\A_SPW_TOP|SPW|RX|data~0_combout  & ( \A_SPW_TOP|SPW|RX|data [6] & ( (\A_SPW_TOP|SPW|RX|dta_timec_p [6]) # 
// (\A_SPW_TOP|SPW|RX|ready_control_p_r~q ) ) ) ) # ( !\A_SPW_TOP|SPW|RX|data~0_combout  & ( !\A_SPW_TOP|SPW|RX|data [6] & ( (!\A_SPW_TOP|SPW|RX|ready_control_p_r~q  & \A_SPW_TOP|SPW|RX|dta_timec_p [6]) ) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|RX|dta_timec_p [6]),
        .datad(gnd),
        .datae(!\A_SPW_TOP|SPW|RX|data~0_combout ),
        .dataf(!\A_SPW_TOP|SPW|RX|data [6]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|data~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|data~2 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|data~2 .lut_mask = 64'h0A0A00005F5FFFFF;
defparam \A_SPW_TOP|SPW|RX|data~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y2_N8
dffeas \A_SPW_TOP|SPW|RX|data[6] (
        .clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|RX|data~2_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(!\A_SPW_TOP|SPW|RX|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|data [6]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|data[6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|data[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y2_N21
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|dta_timec[2]~feeder (
// Equation(s):
// \A_SPW_TOP|SPW|RX|dta_timec[2]~feeder_combout  = ( \A_SPW_TOP|SPW|RX|bit_d_5~q  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|bit_d_5~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|dta_timec[2]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|dta_timec[2]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|dta_timec[2]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|SPW|RX|dta_timec[2]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y2_N23
dffeas \A_SPW_TOP|SPW|RX|dta_timec[2] (
        .clk(\A_SPW_TOP|SPW|RX|ready_data~combout ),
        .d(\A_SPW_TOP|SPW|RX|dta_timec[2]~feeder_combout ),
        .asdata(vcc),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|dta_timec [2]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|dta_timec[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|dta_timec[2] .power_up = "low";
// synopsys translate_on

// Location: FF_X49_Y2_N5
dffeas \A_SPW_TOP|SPW|RX|dta_timec_p[2] (
        .clk(\A_SPW_TOP|SPW|RX|ready_data_p~combout ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|RX|dta_timec [2]),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|dta_timec_p [2]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y2_N9
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|data~6 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|data~6_combout  = ( \A_SPW_TOP|SPW|RX|dta_timec_p [2] & ( ((!\A_SPW_TOP|SPW|RX|data~0_combout  & !\A_SPW_TOP|SPW|RX|ready_control_p_r~q )) # (\A_SPW_TOP|SPW|RX|data [2]) ) ) # ( !\A_SPW_TOP|SPW|RX|dta_timec_p [2] & ( 
// (\A_SPW_TOP|SPW|RX|data [2] & ((\A_SPW_TOP|SPW|RX|ready_control_p_r~q ) # (\A_SPW_TOP|SPW|RX|data~0_combout ))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|data~0_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),
        .datac(!\A_SPW_TOP|SPW|RX|data [2]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|dta_timec_p [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|data~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|data~6 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|data~6 .lut_mask = 64'h070707078F8F8F8F;
defparam \A_SPW_TOP|SPW|RX|data~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y2_N47
dffeas \A_SPW_TOP|SPW|RX|data[2] (
        .clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|RX|data~6_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(!\A_SPW_TOP|SPW|RX|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|data [2]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|data[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|data[2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y2_N18
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|dta_timec[7]~feeder (
// Equation(s):
// \A_SPW_TOP|SPW|RX|dta_timec[7]~feeder_combout  = ( \A_SPW_TOP|SPW|RX|bit_d_0~q  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|bit_d_0~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|dta_timec[7]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|dta_timec[7]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|dta_timec[7]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|SPW|RX|dta_timec[7]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y2_N19
dffeas \A_SPW_TOP|SPW|RX|dta_timec[7] (
        .clk(\A_SPW_TOP|SPW|RX|ready_data~combout ),
        .d(\A_SPW_TOP|SPW|RX|dta_timec[7]~feeder_combout ),
        .asdata(vcc),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|dta_timec [7]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|dta_timec[7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|dta_timec[7] .power_up = "low";
// synopsys translate_on

// Location: FF_X49_Y2_N11
dffeas \A_SPW_TOP|SPW|RX|dta_timec_p[7] (
        .clk(\A_SPW_TOP|SPW|RX|ready_data_p~combout ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|RX|dta_timec [7]),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|dta_timec_p [7]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[7] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y2_N45
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|data~1 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|data~1_combout  = ( \A_SPW_TOP|SPW|RX|data [7] & ( ((\A_SPW_TOP|SPW|RX|dta_timec_p [7]) # (\A_SPW_TOP|SPW|RX|ready_control_p_r~q )) # (\A_SPW_TOP|SPW|RX|data~0_combout ) ) ) # ( !\A_SPW_TOP|SPW|RX|data [7] & ( 
// (!\A_SPW_TOP|SPW|RX|data~0_combout  & (!\A_SPW_TOP|SPW|RX|ready_control_p_r~q  & \A_SPW_TOP|SPW|RX|dta_timec_p [7])) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|data~0_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),
        .datac(!\A_SPW_TOP|SPW|RX|dta_timec_p [7]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|data [7]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|data~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|data~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|data~1 .lut_mask = 64'h080808087F7F7F7F;
defparam \A_SPW_TOP|SPW|RX|data~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y2_N44
dffeas \A_SPW_TOP|SPW|RX|data[7] (
        .clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|RX|data~1_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(!\A_SPW_TOP|SPW|RX|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|data [7]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|data[7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|data[7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y2_N27
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|dta_timec[4]~feeder (
// Equation(s):
// \A_SPW_TOP|SPW|RX|dta_timec[4]~feeder_combout  = ( \A_SPW_TOP|SPW|RX|bit_d_3~q  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|bit_d_3~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|dta_timec[4]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|dta_timec[4]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|dta_timec[4]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|SPW|RX|dta_timec[4]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y2_N29
dffeas \A_SPW_TOP|SPW|RX|dta_timec[4] (
        .clk(\A_SPW_TOP|SPW|RX|ready_data~combout ),
        .d(\A_SPW_TOP|SPW|RX|dta_timec[4]~feeder_combout ),
        .asdata(vcc),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|dta_timec [4]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|dta_timec[4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|dta_timec[4] .power_up = "low";
// synopsys translate_on

// Location: FF_X49_Y2_N41
dffeas \A_SPW_TOP|SPW|RX|dta_timec_p[4] (
        .clk(\A_SPW_TOP|SPW|RX|ready_data_p~combout ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|RX|dta_timec [4]),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|dta_timec_p [4]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y2_N36
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|data~4 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|data~4_combout  = ( \A_SPW_TOP|SPW|RX|ready_control_p_r~q  & ( \A_SPW_TOP|SPW|RX|data~0_combout  & ( \A_SPW_TOP|SPW|RX|data [4] ) ) ) # ( !\A_SPW_TOP|SPW|RX|ready_control_p_r~q  & ( \A_SPW_TOP|SPW|RX|data~0_combout  & ( 
// \A_SPW_TOP|SPW|RX|data [4] ) ) ) # ( \A_SPW_TOP|SPW|RX|ready_control_p_r~q  & ( !\A_SPW_TOP|SPW|RX|data~0_combout  & ( \A_SPW_TOP|SPW|RX|data [4] ) ) ) # ( !\A_SPW_TOP|SPW|RX|ready_control_p_r~q  & ( !\A_SPW_TOP|SPW|RX|data~0_combout  & ( 
// \A_SPW_TOP|SPW|RX|dta_timec_p [4] ) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|data [4]),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|RX|dta_timec_p [4]),
        .datad(gnd),
        .datae(!\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),
        .dataf(!\A_SPW_TOP|SPW|RX|data~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|data~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|data~4 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|data~4 .lut_mask = 64'h0F0F555555555555;
defparam \A_SPW_TOP|SPW|RX|data~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y2_N29
dffeas \A_SPW_TOP|SPW|RX|data[4] (
        .clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|RX|data~4_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(!\A_SPW_TOP|SPW|RX|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|data [4]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|data[4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|data[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y2_N12
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|dta_timec[5]~feeder (
// Equation(s):
// \A_SPW_TOP|SPW|RX|dta_timec[5]~feeder_combout  = ( \A_SPW_TOP|SPW|RX|bit_d_2~q  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|bit_d_2~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|dta_timec[5]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|dta_timec[5]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|dta_timec[5]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|SPW|RX|dta_timec[5]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y2_N14
dffeas \A_SPW_TOP|SPW|RX|dta_timec[5] (
        .clk(\A_SPW_TOP|SPW|RX|ready_data~combout ),
        .d(\A_SPW_TOP|SPW|RX|dta_timec[5]~feeder_combout ),
        .asdata(vcc),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|dta_timec [5]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|dta_timec[5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|dta_timec[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y2_N6
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|dta_timec_p[5]~feeder (
// Equation(s):
// \A_SPW_TOP|SPW|RX|dta_timec_p[5]~feeder_combout  = ( \A_SPW_TOP|SPW|RX|dta_timec [5] )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|dta_timec [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|dta_timec_p[5]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[5]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[5]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[5]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y2_N8
dffeas \A_SPW_TOP|SPW|RX|dta_timec_p[5] (
        .clk(\A_SPW_TOP|SPW|RX|ready_data_p~combout ),
        .d(\A_SPW_TOP|SPW|RX|dta_timec_p[5]~feeder_combout ),
        .asdata(vcc),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|dta_timec_p [5]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y2_N51
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|data~3 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|data~3_combout  = ( \A_SPW_TOP|SPW|RX|ready_control_p_r~q  & ( \A_SPW_TOP|SPW|RX|data [5] ) ) # ( !\A_SPW_TOP|SPW|RX|ready_control_p_r~q  & ( \A_SPW_TOP|SPW|RX|data [5] & ( (\A_SPW_TOP|SPW|RX|data~0_combout ) # 
// (\A_SPW_TOP|SPW|RX|dta_timec_p [5]) ) ) ) # ( !\A_SPW_TOP|SPW|RX|ready_control_p_r~q  & ( !\A_SPW_TOP|SPW|RX|data [5] & ( (\A_SPW_TOP|SPW|RX|dta_timec_p [5] & !\A_SPW_TOP|SPW|RX|data~0_combout ) ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|SPW|RX|dta_timec_p [5]),
        .datac(!\A_SPW_TOP|SPW|RX|data~0_combout ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),
        .dataf(!\A_SPW_TOP|SPW|RX|data [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|data~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|data~3 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|data~3 .lut_mask = 64'h303000003F3FFFFF;
defparam \A_SPW_TOP|SPW|RX|data~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y2_N50
dffeas \A_SPW_TOP|SPW|RX|data[5] (
        .clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|RX|data~3_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(!\A_SPW_TOP|SPW|RX|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|data [5]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|data[5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|data[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y2_N24
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|always16~0 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|always16~0_combout  = ( \A_SPW_TOP|SPW|RX|data [4] & ( \A_SPW_TOP|SPW|RX|data [5] & ( !\A_SPW_TOP|SPW|RX|data [3] $ (!\A_SPW_TOP|SPW|RX|data [6] $ (!\A_SPW_TOP|SPW|RX|data [2] $ (!\A_SPW_TOP|SPW|RX|data [7]))) ) ) ) # ( 
// !\A_SPW_TOP|SPW|RX|data [4] & ( \A_SPW_TOP|SPW|RX|data [5] & ( !\A_SPW_TOP|SPW|RX|data [3] $ (!\A_SPW_TOP|SPW|RX|data [6] $ (!\A_SPW_TOP|SPW|RX|data [2] $ (\A_SPW_TOP|SPW|RX|data [7]))) ) ) ) # ( \A_SPW_TOP|SPW|RX|data [4] & ( !\A_SPW_TOP|SPW|RX|data [5] 
// & ( !\A_SPW_TOP|SPW|RX|data [3] $ (!\A_SPW_TOP|SPW|RX|data [6] $ (!\A_SPW_TOP|SPW|RX|data [2] $ (\A_SPW_TOP|SPW|RX|data [7]))) ) ) ) # ( !\A_SPW_TOP|SPW|RX|data [4] & ( !\A_SPW_TOP|SPW|RX|data [5] & ( !\A_SPW_TOP|SPW|RX|data [3] $ (!\A_SPW_TOP|SPW|RX|data 
// [6] $ (!\A_SPW_TOP|SPW|RX|data [2] $ (!\A_SPW_TOP|SPW|RX|data [7]))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|data [3]),
        .datab(!\A_SPW_TOP|SPW|RX|data [6]),
        .datac(!\A_SPW_TOP|SPW|RX|data [2]),
        .datad(!\A_SPW_TOP|SPW|RX|data [7]),
        .datae(!\A_SPW_TOP|SPW|RX|data [4]),
        .dataf(!\A_SPW_TOP|SPW|RX|data [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|always16~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|always16~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|always16~0 .lut_mask = 64'h6996966996696996;
defparam \A_SPW_TOP|SPW|RX|always16~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y2_N24
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|dta_timec[0]~feeder (
// Equation(s):
// \A_SPW_TOP|SPW|RX|dta_timec[0]~feeder_combout  = ( \A_SPW_TOP|SPW|RX|bit_d_7~q  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|bit_d_7~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|dta_timec[0]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|dta_timec[0]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|dta_timec[0]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|SPW|RX|dta_timec[0]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y2_N26
dffeas \A_SPW_TOP|SPW|RX|dta_timec[0] (
        .clk(\A_SPW_TOP|SPW|RX|ready_data~combout ),
        .d(\A_SPW_TOP|SPW|RX|dta_timec[0]~feeder_combout ),
        .asdata(vcc),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|dta_timec [0]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|dta_timec[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|dta_timec[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y2_N57
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|dta_timec_p[0]~feeder (
// Equation(s):
// \A_SPW_TOP|SPW|RX|dta_timec_p[0]~feeder_combout  = ( \A_SPW_TOP|SPW|RX|dta_timec [0] )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|dta_timec [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|dta_timec_p[0]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[0]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[0]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[0]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y2_N59
dffeas \A_SPW_TOP|SPW|RX|dta_timec_p[0] (
        .clk(\A_SPW_TOP|SPW|RX|ready_data_p~combout ),
        .d(\A_SPW_TOP|SPW|RX|dta_timec_p[0]~feeder_combout ),
        .asdata(vcc),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|dta_timec_p [0]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y2_N21
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|data~8 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|data~8_combout  = ( \A_SPW_TOP|SPW|RX|data~0_combout  & ( \A_SPW_TOP|SPW|RX|data [0] ) ) # ( !\A_SPW_TOP|SPW|RX|data~0_combout  & ( \A_SPW_TOP|SPW|RX|data [0] & ( (\A_SPW_TOP|SPW|RX|ready_control_p_r~q ) # (\A_SPW_TOP|SPW|RX|dta_timec_p 
// [0]) ) ) ) # ( !\A_SPW_TOP|SPW|RX|data~0_combout  & ( !\A_SPW_TOP|SPW|RX|data [0] & ( (\A_SPW_TOP|SPW|RX|dta_timec_p [0] & !\A_SPW_TOP|SPW|RX|ready_control_p_r~q ) ) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|dta_timec_p [0]),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|SPW|RX|data~0_combout ),
        .dataf(!\A_SPW_TOP|SPW|RX|data [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|data~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|data~8 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|data~8 .lut_mask = 64'h505000005F5FFFFF;
defparam \A_SPW_TOP|SPW|RX|data~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y2_N20
dffeas \A_SPW_TOP|SPW|RX|data[0] (
        .clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|RX|data~8_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(!\A_SPW_TOP|SPW|RX|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|data [0]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|data[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|data[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y2_N45
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|dta_timec[1]~feeder (
// Equation(s):
// \A_SPW_TOP|SPW|RX|dta_timec[1]~feeder_combout  = ( \A_SPW_TOP|SPW|RX|bit_d_6~q  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|bit_d_6~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|dta_timec[1]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|dta_timec[1]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|dta_timec[1]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|SPW|RX|dta_timec[1]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y2_N47
dffeas \A_SPW_TOP|SPW|RX|dta_timec[1] (
        .clk(\A_SPW_TOP|SPW|RX|ready_data~combout ),
        .d(\A_SPW_TOP|SPW|RX|dta_timec[1]~feeder_combout ),
        .asdata(vcc),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|dta_timec [1]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|dta_timec[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|dta_timec[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y2_N33
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|dta_timec_p[1]~feeder (
// Equation(s):
// \A_SPW_TOP|SPW|RX|dta_timec_p[1]~feeder_combout  = ( \A_SPW_TOP|SPW|RX|dta_timec [1] )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|dta_timec [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|dta_timec_p[1]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[1]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[1]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[1]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y2_N35
dffeas \A_SPW_TOP|SPW|RX|dta_timec_p[1] (
        .clk(\A_SPW_TOP|SPW|RX|ready_data_p~combout ),
        .d(\A_SPW_TOP|SPW|RX|dta_timec_p[1]~feeder_combout ),
        .asdata(vcc),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|dta_timec_p [1]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y2_N36
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|data~7 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|data~7_combout  = ( \A_SPW_TOP|SPW|RX|data~0_combout  & ( \A_SPW_TOP|SPW|RX|data [1] ) ) # ( !\A_SPW_TOP|SPW|RX|data~0_combout  & ( \A_SPW_TOP|SPW|RX|data [1] & ( (\A_SPW_TOP|SPW|RX|ready_control_p_r~q ) # (\A_SPW_TOP|SPW|RX|dta_timec_p 
// [1]) ) ) ) # ( !\A_SPW_TOP|SPW|RX|data~0_combout  & ( !\A_SPW_TOP|SPW|RX|data [1] & ( (\A_SPW_TOP|SPW|RX|dta_timec_p [1] & !\A_SPW_TOP|SPW|RX|ready_control_p_r~q ) ) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|dta_timec_p [1]),
        .datab(!\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),
        .datac(gnd),
        .datad(gnd),
        .datae(!\A_SPW_TOP|SPW|RX|data~0_combout ),
        .dataf(!\A_SPW_TOP|SPW|RX|data [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|data~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|data~7 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|data~7 .lut_mask = 64'h444400007777FFFF;
defparam \A_SPW_TOP|SPW|RX|data~7 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y2_N41
dffeas \A_SPW_TOP|SPW|RX|data[1] (
        .clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|RX|data~7_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(!\A_SPW_TOP|SPW|RX|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|data [1]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|data[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|data[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y2_N48
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|always16~1 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|always16~1_combout  = ( \A_SPW_TOP|SPW|RX|data [1] & ( !\A_SPW_TOP|SPW|RX|data [0] ) ) # ( !\A_SPW_TOP|SPW|RX|data [1] & ( \A_SPW_TOP|SPW|RX|data [0] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|RX|data [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|data [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|always16~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|always16~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|always16~1 .lut_mask = 64'h0F0F0F0FF0F0F0F0;
defparam \A_SPW_TOP|SPW|RX|always16~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y2_N6
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|rx_error_d~1 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|rx_error_d~1_combout  = ( \A_SPW_TOP|SPW|RX|always16~0_combout  & ( \A_SPW_TOP|SPW|RX|always16~1_combout  & ( (((!\A_SPW_TOP|SPW|RX|always15~0_combout  & \A_SPW_TOP|SPW|RX|rx_error_c~0_combout )) # (\A_SPW_TOP|SPW|RX|rx_error_d~0_combout 
// )) # (\A_SPW_TOP|SPW|RX|rx_error_d~q ) ) ) ) # ( !\A_SPW_TOP|SPW|RX|always16~0_combout  & ( \A_SPW_TOP|SPW|RX|always16~1_combout  & ( (((\A_SPW_TOP|SPW|RX|always15~0_combout  & \A_SPW_TOP|SPW|RX|rx_error_c~0_combout )) # 
// (\A_SPW_TOP|SPW|RX|rx_error_d~0_combout )) # (\A_SPW_TOP|SPW|RX|rx_error_d~q ) ) ) ) # ( \A_SPW_TOP|SPW|RX|always16~0_combout  & ( !\A_SPW_TOP|SPW|RX|always16~1_combout  & ( (((\A_SPW_TOP|SPW|RX|always15~0_combout  & \A_SPW_TOP|SPW|RX|rx_error_c~0_combout 
// )) # (\A_SPW_TOP|SPW|RX|rx_error_d~0_combout )) # (\A_SPW_TOP|SPW|RX|rx_error_d~q ) ) ) ) # ( !\A_SPW_TOP|SPW|RX|always16~0_combout  & ( !\A_SPW_TOP|SPW|RX|always16~1_combout  & ( (((!\A_SPW_TOP|SPW|RX|always15~0_combout  & 
// \A_SPW_TOP|SPW|RX|rx_error_c~0_combout )) # (\A_SPW_TOP|SPW|RX|rx_error_d~0_combout )) # (\A_SPW_TOP|SPW|RX|rx_error_d~q ) ) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|always15~0_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_error_c~0_combout ),
        .datac(!\A_SPW_TOP|SPW|RX|rx_error_d~q ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_error_d~0_combout ),
        .datae(!\A_SPW_TOP|SPW|RX|always16~0_combout ),
        .dataf(!\A_SPW_TOP|SPW|RX|always16~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|rx_error_d~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_error_d~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|rx_error_d~1 .lut_mask = 64'h2FFF1FFF1FFF2FFF;
defparam \A_SPW_TOP|SPW|RX|rx_error_d~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y2_N50
dffeas \A_SPW_TOP|SPW|RX|rx_error_d (
        .clk(\A_SPW_TOP|SPW|RX|ready_data_p~combout ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|RX|rx_error_d~1_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|rx_error_d~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_error_d .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|rx_error_d .power_up = "low";
// synopsys translate_on

// Location: FF_X49_Y3_N34
dffeas \A_SPW_TOP|SPW|RX|bit_c_3 (
        .clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|RX|bit_c_1~q ),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|bit_c_3~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|bit_c_3 .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|bit_c_3 .power_up = "low";
// synopsys translate_on

// Location: FF_X50_Y3_N26
dffeas \A_SPW_TOP|SPW|RX|parity_rec_c (
        .clk(\A_SPW_TOP|SPW|RX|always1~0_combout ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|RX|bit_c_3~q ),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|parity_rec_c~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|parity_rec_c .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|parity_rec_c .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y3_N45
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|always16~2 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|always16~2_combout  = ( \A_SPW_TOP|SPW|RX|parity_rec_c~q  & ( !\A_SPW_TOP|SPW|RX|control_r [2] ) ) # ( !\A_SPW_TOP|SPW|RX|parity_rec_c~q  & ( \A_SPW_TOP|SPW|RX|control_r [2] ) )

        .dataa(!\A_SPW_TOP|SPW|RX|control_r [2]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|parity_rec_c~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|always16~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|always16~2 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|always16~2 .lut_mask = 64'h55555555AAAAAAAA;
defparam \A_SPW_TOP|SPW|RX|always16~2 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y3_N9
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|rx_error_c~1 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|rx_error_c~1_combout  = ( \A_SPW_TOP|SPW|RX|control [1] & ( \A_SPW_TOP|SPW|RX|parity_rec_c~q  & ( (\A_SPW_TOP|SPW|RX|last_is_control~q  & (!\A_SPW_TOP|SPW|RX|control_r [2] $ (\A_SPW_TOP|SPW|RX|control [0]))) ) ) ) # ( 
// !\A_SPW_TOP|SPW|RX|control [1] & ( \A_SPW_TOP|SPW|RX|parity_rec_c~q  & ( (\A_SPW_TOP|SPW|RX|last_is_control~q  & (!\A_SPW_TOP|SPW|RX|control_r [2] $ (!\A_SPW_TOP|SPW|RX|control [0]))) ) ) ) # ( \A_SPW_TOP|SPW|RX|control [1] & ( 
// !\A_SPW_TOP|SPW|RX|parity_rec_c~q  & ( (\A_SPW_TOP|SPW|RX|last_is_control~q  & (!\A_SPW_TOP|SPW|RX|control_r [2] $ (!\A_SPW_TOP|SPW|RX|control [0]))) ) ) ) # ( !\A_SPW_TOP|SPW|RX|control [1] & ( !\A_SPW_TOP|SPW|RX|parity_rec_c~q  & ( 
// (\A_SPW_TOP|SPW|RX|last_is_control~q  & (!\A_SPW_TOP|SPW|RX|control_r [2] $ (\A_SPW_TOP|SPW|RX|control [0]))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|control_r [2]),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|RX|last_is_control~q ),
        .datad(!\A_SPW_TOP|SPW|RX|control [0]),
        .datae(!\A_SPW_TOP|SPW|RX|control [1]),
        .dataf(!\A_SPW_TOP|SPW|RX|parity_rec_c~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|rx_error_c~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_error_c~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|rx_error_c~1 .lut_mask = 64'h0A05050A050A0A05;
defparam \A_SPW_TOP|SPW|RX|rx_error_c~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y3_N21
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|rx_error_c~2 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|rx_error_c~2_combout  = ( \A_SPW_TOP|SPW|RX|always16~1_combout  & ( \A_SPW_TOP|SPW|RX|rx_error_c~1_combout  ) ) # ( !\A_SPW_TOP|SPW|RX|always16~1_combout  & ( \A_SPW_TOP|SPW|RX|rx_error_c~1_combout  ) ) # ( 
// \A_SPW_TOP|SPW|RX|always16~1_combout  & ( !\A_SPW_TOP|SPW|RX|rx_error_c~1_combout  & ( ((\A_SPW_TOP|SPW|RX|rx_error_c~0_combout  & (!\A_SPW_TOP|SPW|RX|always16~2_combout  $ (!\A_SPW_TOP|SPW|RX|always16~0_combout )))) # (\A_SPW_TOP|SPW|RX|rx_error_c~q ) ) 
// ) ) # ( !\A_SPW_TOP|SPW|RX|always16~1_combout  & ( !\A_SPW_TOP|SPW|RX|rx_error_c~1_combout  & ( ((\A_SPW_TOP|SPW|RX|rx_error_c~0_combout  & (!\A_SPW_TOP|SPW|RX|always16~2_combout  $ (\A_SPW_TOP|SPW|RX|always16~0_combout )))) # 
// (\A_SPW_TOP|SPW|RX|rx_error_c~q ) ) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_error_c~q ),
        .datab(!\A_SPW_TOP|SPW|RX|always16~2_combout ),
        .datac(!\A_SPW_TOP|SPW|RX|rx_error_c~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|always16~0_combout ),
        .datae(!\A_SPW_TOP|SPW|RX|always16~1_combout ),
        .dataf(!\A_SPW_TOP|SPW|RX|rx_error_c~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|rx_error_c~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_error_c~2 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|rx_error_c~2 .lut_mask = 64'h5D57575DFFFFFFFF;
defparam \A_SPW_TOP|SPW|RX|rx_error_c~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y3_N2
dffeas \A_SPW_TOP|SPW|RX|rx_error_c (
        .clk(\A_SPW_TOP|SPW|RX|always2~0_combout ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|RX|rx_error_c~2_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|rx_error_c~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_error_c .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|rx_error_c .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y3_N42
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|last_is_timec~0 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|last_is_timec~0_combout  = ( \A_SPW_TOP|SPW|RX|control [2] & ( \A_SPW_TOP|SPW|RX|control [1] & ( (!\A_SPW_TOP|SPW|RX|ready_control_p_r~q  & ((!\A_SPW_TOP|SPW|RX|ready_data_p_r~q  & ((\A_SPW_TOP|SPW|RX|last_is_timec~q ))) # 
// (\A_SPW_TOP|SPW|RX|ready_data_p_r~q  & (\A_SPW_TOP|SPW|RX|control [0])))) ) ) ) # ( !\A_SPW_TOP|SPW|RX|control [2] & ( \A_SPW_TOP|SPW|RX|control [1] & ( (\A_SPW_TOP|SPW|RX|last_is_timec~q  & (!\A_SPW_TOP|SPW|RX|ready_data_p_r~q  & 
// !\A_SPW_TOP|SPW|RX|ready_control_p_r~q )) ) ) ) # ( \A_SPW_TOP|SPW|RX|control [2] & ( !\A_SPW_TOP|SPW|RX|control [1] & ( (\A_SPW_TOP|SPW|RX|last_is_timec~q  & (!\A_SPW_TOP|SPW|RX|ready_data_p_r~q  & !\A_SPW_TOP|SPW|RX|ready_control_p_r~q )) ) ) ) # ( 
// !\A_SPW_TOP|SPW|RX|control [2] & ( !\A_SPW_TOP|SPW|RX|control [1] & ( (\A_SPW_TOP|SPW|RX|last_is_timec~q  & (!\A_SPW_TOP|SPW|RX|ready_data_p_r~q  & !\A_SPW_TOP|SPW|RX|ready_control_p_r~q )) ) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|control [0]),
        .datab(!\A_SPW_TOP|SPW|RX|last_is_timec~q ),
        .datac(!\A_SPW_TOP|SPW|RX|ready_data_p_r~q ),
        .datad(!\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),
        .datae(!\A_SPW_TOP|SPW|RX|control [2]),
        .dataf(!\A_SPW_TOP|SPW|RX|control [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|last_is_timec~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|last_is_timec~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|last_is_timec~0 .lut_mask = 64'h3000300030003500;
defparam \A_SPW_TOP|SPW|RX|last_is_timec~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y3_N47
dffeas \A_SPW_TOP|SPW|RX|last_is_timec (
        .clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|RX|last_is_timec~0_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(!\A_SPW_TOP|SPW|RX|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|last_is_timec~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|last_is_timec .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|last_is_timec .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y3_N51
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|rx_got_null~0 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|rx_got_null~0_combout  = ( \A_SPW_TOP|SPW|RX|last_is_control~q  & ( (!\A_SPW_TOP|SPW|RX|last_is_timec~q ) # (\A_SPW_TOP|SPW|RX|rx_got_null~q ) ) ) # ( !\A_SPW_TOP|SPW|RX|last_is_control~q  & ( (\A_SPW_TOP|SPW|RX|rx_got_null~q  & 
// \A_SPW_TOP|SPW|RX|last_is_timec~q ) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_got_null~q ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|RX|last_is_timec~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|last_is_control~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|rx_got_null~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_got_null~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|rx_got_null~0 .lut_mask = 64'h05050505F5F5F5F5;
defparam \A_SPW_TOP|SPW|RX|rx_got_null~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y3_N56
dffeas \A_SPW_TOP|SPW|RX|rx_got_null (
        .clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|RX|rx_got_null~0_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(!\A_SPW_TOP|SPW|RX|last_is_data~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|rx_got_null~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_got_null .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|rx_got_null .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y25_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|router|Equal20~0 (
// Equation(s):
// \u0|mm_interconnect_0|router|Equal20~0_combout  = ( \u0|mm_interconnect_0|router|Equal7~1_combout  & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout  & 
// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout  & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~3_combout  & 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout ),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout ),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~3_combout ),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|router|Equal7~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router|Equal20~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router|Equal20~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router|Equal20~0 .lut_mask = 64'h0000000000040004;
defparam \u0|mm_interconnect_0|router|Equal20~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y31_N9
cyclonev_lcell_comb \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder (
// Equation(s):
// \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder .extended_lut = "off";
defparam \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: HPSINTERFACECLOCKSRESETS_X32_Y50_N111
cyclonev_hps_interface_clocks_resets \u0|hps_0|fpga_interfaces|clocks_resets (
        .f2h_cold_rst_req_n(vcc),
        .f2h_dbg_rst_req_n(vcc),
        .f2h_pending_rst_ack(vcc),
        .f2h_periph_ref_clk(gnd),
        .f2h_sdram_ref_clk(gnd),
        .f2h_warm_rst_req_n(vcc),
        .ptp_ref_clk(gnd),
        .h2f_cold_rst_n(\u0|hps_0|fpga_interfaces|clocks_resets~h2f_cold_rst_n ),
        .h2f_pending_rst_req_n(),
        .h2f_rst_n(\u0|hps_0|fpga_interfaces|h2f_rst_n [0]),
        .h2f_user0_clk(),
        .h2f_user1_clk(),
        .h2f_user2_clk());
// synopsys translate_off
defparam \u0|hps_0|fpga_interfaces|clocks_resets .h2f_user0_clk_freq = 100;
defparam \u0|hps_0|fpga_interfaces|clocks_resets .h2f_user1_clk_freq = 100;
defparam \u0|hps_0|fpga_interfaces|clocks_resets .h2f_user2_clk_freq = 100;
// synopsys translate_on

// Location: CLKCTRL_G10
cyclonev_clkena \u0|hps_0|fpga_interfaces|h2f_rst_n[0]~CLKENA0 (
        .inclk(\u0|hps_0|fpga_interfaces|h2f_rst_n [0]),
        .ena(vcc),
        .outclk(\u0|hps_0|fpga_interfaces|h2f_rst_n[0]~CLKENA0_outclk ),
        .enaout());
// synopsys translate_off
defparam \u0|hps_0|fpga_interfaces|h2f_rst_n[0]~CLKENA0 .clock_type = "global clock";
defparam \u0|hps_0|fpga_interfaces|h2f_rst_n[0]~CLKENA0 .disable_mode = "low";
defparam \u0|hps_0|fpga_interfaces|h2f_rst_n[0]~CLKENA0 .ena_register_mode = "always enabled";
defparam \u0|hps_0|fpga_interfaces|h2f_rst_n[0]~CLKENA0 .ena_register_power_up = "high";
defparam \u0|hps_0|fpga_interfaces|h2f_rst_n[0]~CLKENA0 .test_syn = "high";
// synopsys translate_on

// Location: FF_X28_Y31_N10
dffeas \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|hps_0|fpga_interfaces|h2f_rst_n[0]~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1] .is_wysiwyg = "true";
defparam \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X28_Y31_N2
dffeas \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain [1]),
        .clrn(\u0|hps_0|fpga_interfaces|h2f_rst_n[0]~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0] .is_wysiwyg = "true";
defparam \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X28_Y31_N23
dffeas \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain [0]),
        .clrn(\u0|hps_0|fpga_interfaces|h2f_rst_n[0]~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out .is_wysiwyg = "true";
defparam \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out .power_up = "low";
// synopsys translate_on

// Location: FF_X28_Y25_N32
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[14] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|router|Equal20~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [14]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[14] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[14] .power_up = "low";
// synopsys translate_on

// Location: FF_X28_Y15_N56
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~5_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y14_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter~2 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter~2_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter~0_combout  & ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [0] $ (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [1]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [0]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter~2 .lut_mask = 64'h0000000033CC33CC;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y14_N56
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y14_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~0_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override~q  & ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [1] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~0 .lut_mask = 64'h00000000FF00FF00;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y18_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~4 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~4_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [0] & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~0_combout  & ( 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|local_write~0_combout ) # ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0_combout ) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1])) ) ) ) # ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [0] & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~0_combout  & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|local_write~0_combout  & 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|local_write~0_combout ),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0_combout ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [0]),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~4 .lut_mask = 64'h000000004040BFBF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y18_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y18_N2
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y18_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~1_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~0_combout  & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & 
// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [0] $ (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|local_write~0_combout )) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0_combout ))) ) ) # ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~0_combout  & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [0]),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0_combout ),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|local_write~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~1 .lut_mask = 64'h0C0C0C0C4C8C4C8C;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y15_N20
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~6_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][6] .power_up = "low";
// synopsys translate_on

// Location: FF_X22_Y18_N2
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][129] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][129]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y18_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~0_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][129]~q  & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|local_write~0_combout  & ( 
// (((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0_combout  & \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_read~0_combout )) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1])) # 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][129]~q  & ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|local_write~0_combout  & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & (((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0_combout  & 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_read~0_combout )) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ))) ) ) ) # ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][129]~q  & ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|local_write~0_combout  & ( ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0_combout  & 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_read~0_combout )) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][129]~q  & ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|local_write~0_combout  & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0_combout  & (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_read~0_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0_combout ),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_read~0_combout ),
        .datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][129]~q ),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|local_write~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~0 .lut_mask = 64'h00300F3F50705F7F;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y17_N47
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_busy (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y18_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~1_combout  & ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y17_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y17_N47
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y17_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout  = ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) # 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) # ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  $ 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) ) )

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .lut_mask = 64'h55AA55AA44EE44EE;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y17_N44
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y17_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout  = ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) # 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) # ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] $ 
// (((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) # 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) ) )

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .lut_mask = 64'h0AF50AF50CFC0CFC;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y17_N59
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";
// synopsys translate_on

// Location: FF_X17_Y17_N26
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][75] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][75]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";
// synopsys translate_on

// Location: FF_X17_Y17_N2
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y17_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout  = ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) # 
// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ) ) # ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ) ) # ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) # 
// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) # 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))) ) ) ) # ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) # 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) )

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .lut_mask = 64'h0E04F4FE0404FEFE;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y17_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout  = ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout  & ( 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout  & 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0 .lut_mask = 64'hC0C0C0C000000000;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y18_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  = ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q )) ) ) # ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  $ 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ))) # 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q )) ) )

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .lut_mask = 64'hA05AA05A00A000A0;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y18_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout  = ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  ) ) ) # ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h0003333300000000;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y17_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  = ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4])) ) )

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h00000000A000A000;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y17_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout  = ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])) # 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))) ) ) # ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] $ 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .lut_mask = 64'h5A5A5A5A77447744;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y17_N5
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";
// synopsys translate_on

// Location: FF_X17_Y17_N50
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y17_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout  = ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) # 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) ) ) ) # ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) ) ) ) # ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg 
// [5]) ) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout 
//  & !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) ) ) )

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 .lut_mask = 64'h3030CFCF5500FFAA;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y18_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout  = ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h000000000000FF00;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y17_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout  & ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout  ) ) # ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout  & ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout  & ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout  ) ) ) # ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout  
// & ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout  ) ) # ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout  & ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout  & ( 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout  & ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ) # 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ),
        .datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h2233FFFF3333FFFF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y17_N17
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y17_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~6 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~6_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) # 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][75]~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][75]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][75]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h000F000F303F303F;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y17_N56
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~6_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";
// synopsys translate_on

// Location: FF_X17_Y17_N31
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][74] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~5_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][74]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y17_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~5 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~5_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) # 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][74]~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & 
// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][74]~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][74]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h303F303F505F505F;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y17_N53
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~5_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y17_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q  & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout  & 
// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q )) # 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))))) ) ) ) # ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q  & ( 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q )) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))))) ) ) ) # ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q  & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout  & 
// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q )) # 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))))) ) ) ) # ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q  & ( 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q )) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))))) ) ) )

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout ),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h2320202313101013;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y17_N8
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y17_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~0_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] $ (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h3C3C3C3CCCCCCCCC;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y17_N20
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][76] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~7_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][76]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y17_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~7 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~7_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4])) # 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][76]~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][76]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][76]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h0033003344774477;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y17_N59
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][76] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~7_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][76]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y17_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q  & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~0_combout  & \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout ) ) ) ) 
// # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q  & ( 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][76]~q  & \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout ) ) ) ) # ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q  & ( 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~0_combout  & \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout ) ) ) ) # ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q  & ( 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout  & (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][76]~q  $ (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~0_combout ),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout ),
        .datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h00C300AA003300AA;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y17_N44
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";
// synopsys translate_on

// Location: FF_X17_Y17_N35
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][78] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~9_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][78]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y17_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~9 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~9_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) # 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][78]~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][78]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][78]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~9 .lut_mask = 64'h005500550A5F0A5F;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~9 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y17_N35
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][78] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~9_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][78]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";
// synopsys translate_on

// Location: FF_X17_Y17_N8
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][77] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][77]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y17_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~8 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~8_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])) # 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][77]~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][77]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][77]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~8 .lut_mask = 64'h000F000F505F505F;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y17_N29
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][77] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~8_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][77]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y17_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~0_combout  = ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q  & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][76]~q  & 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q  & !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][77]~q )) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][77]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~0 .lut_mask = 64'hC000C00000000000;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y17_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~2 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~2_combout  = !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [5] $ 
// (((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]))))

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h7F807F807F807F80;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y17_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~1_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][77]~q  & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q  & 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][76]~q  & !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q )) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][77]~q  & ( 
// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q ) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][76]~q )) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][77]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h77FF77FF88008800;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y17_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~1_combout  & ( 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout  & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~2_combout )) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~1_combout  & ( 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ) # 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~2_combout ))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout ),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~2_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h3330333003000300;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y17_N38
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y17_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~1_combout  = (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [5])))

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~1 .lut_mask = 64'h8000800080008000;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y17_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~1_combout  & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout  & 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][78]~q  $ 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~0_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~1_combout  & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][78]~q  $ 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~0_combout )) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~1_combout  & ( 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][78]~q  $ (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~0_combout )) # 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~1_combout  & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout  & 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][78]~q  $ 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~0_combout )))) ) ) )

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][78]~q ),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout ),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~0_combout ),
        .datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h1020132313231020;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y17_N2
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y17_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~1_combout  = ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [5])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'hC000C00000000000;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y17_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~1_combout  & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout ) ) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~1_combout  & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][78]~q  & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~0_combout  & 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout )) ) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~1_combout  & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][78]~q  & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~0_combout  & 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][78]~q ),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~0_combout ),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout ),
        .datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h00220000002200F0;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y17_N13
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y17_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  = (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_busy~q  & 
// (((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~1_combout ) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [7])) # 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h3133313331333133;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y17_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q  & ( 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout  & 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~2_combout )) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q  & ( 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout  & !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~2_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout ),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h3300330011001100;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y17_N41
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y17_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~2 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~2_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_busy~q  & ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y17_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~0_combout  = ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_busy~q  & ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][78]~q  & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q  & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q  & 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][77]~q  & !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][76]~q ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][77]~q ),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][78]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h2000000000000000;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y17_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|comb~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|comb~0_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [0] ) ) # ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [0] & ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg [0]) # 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][129]~q ))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [0]),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|comb~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|comb~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|comb~0 .lut_mask = 64'h0333033333333333;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|comb~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y18_N44
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][66]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y18_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~3 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~3_combout  = (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66])) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & 
// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][66]~q )))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][66]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h0C3F0C3F0C3F0C3F;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y17_N8
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~3_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][66]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y17_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|comb~0_combout  & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][66]~q  & ( 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~0_combout  & ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~2_combout ) # 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~1_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|comb~0_combout  & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][66]~q  ) )

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|comb~0_combout ),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][66]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h00000000FFFFF0A0;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y17_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0_combout  & 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout ) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [0] )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0_combout ),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hFFFFFFFF30303030;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y17_N53
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][129] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][129]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y17_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|read~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|read~0_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [0] & 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][129]~q ) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg [0]) # 
// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [0] & \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][129]~q )) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [0]),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg [0]),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|read~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|read~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|read~0 .lut_mask = 64'hF0F3F0F300330033;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|read~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y17_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|read~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|read~1_combout  = (\u0|mm_interconnect_0|rsp_demux_010|WideOr0~0_combout  & !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|read~0_combout )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_010|WideOr0~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|read~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|read~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|read~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|read~1 .lut_mask = 64'h5050505050505050;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|read~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y17_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used[0]~0_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|read~1_combout  & ( ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg [0] & 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|read~1_combout  & ( 
// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1])) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [0]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg [0]),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|read~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h30FF30FF0F3F0F3F;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y17_N35
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y17_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout  = (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [0] & \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg [0])

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [0]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg [0]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0 .lut_mask = 64'h00AA00AA00AA00AA;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y16_N44
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][9] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~9_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][9]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][9] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][9] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y33_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout  = ( !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg [0] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg [0]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0 .lut_mask = 64'h3333333300000000;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y4_N39
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|enable_tx~0 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|enable_tx~0_combout  = ( \A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q  & ( !\A_SPW_TOP|SPW|FSM|state_fsm.error_wait~q  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|FSM|state_fsm.error_wait~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|enable_tx~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|enable_tx~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|enable_tx~0 .lut_mask = 64'h00000000F0F0F0F0;
defparam \A_SPW_TOP|SPW|FSM|enable_tx~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X45_Y4_N41
dffeas \A_SPW_TOP|SPW|FSM|enable_tx (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|SPW|FSM|enable_tx~0_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|enable_tx .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|enable_tx .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X36_Y10_N27
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Add2~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Add2~0_combout  = ( \A_SPW_TOP|tx_data|counter_reader [1] & ( !\A_SPW_TOP|tx_data|counter_reader [0] ) ) # ( !\A_SPW_TOP|tx_data|counter_reader [1] & ( \A_SPW_TOP|tx_data|counter_reader [0] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|tx_data|counter_reader [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|counter_reader [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Add2~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Add2~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Add2~0 .lut_mask = 64'h0F0F0F0FF0F0F0F0;
defparam \A_SPW_TOP|tx_data|Add2~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X36_Y10_N41
dffeas \A_SPW_TOP|tx_data|counter_reader[1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Add2~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|tx_data|always3~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|counter_reader [1]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|counter_reader[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|counter_reader[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X36_Y10_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Add2~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Add2~1_combout  = ( \A_SPW_TOP|tx_data|counter_reader [0] & ( \A_SPW_TOP|tx_data|counter_reader [2] & ( !\A_SPW_TOP|tx_data|counter_reader [1] ) ) ) # ( !\A_SPW_TOP|tx_data|counter_reader [0] & ( \A_SPW_TOP|tx_data|counter_reader [2] ) 
// ) # ( \A_SPW_TOP|tx_data|counter_reader [0] & ( !\A_SPW_TOP|tx_data|counter_reader [2] & ( \A_SPW_TOP|tx_data|counter_reader [1] ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|tx_data|counter_reader [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(!\A_SPW_TOP|tx_data|counter_reader [0]),
        .dataf(!\A_SPW_TOP|tx_data|counter_reader [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Add2~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Add2~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Add2~1 .lut_mask = 64'h00003333FFFFCCCC;
defparam \A_SPW_TOP|tx_data|Add2~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X36_Y10_N53
dffeas \A_SPW_TOP|tx_data|counter_reader[2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Add2~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|tx_data|always3~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|counter_reader [2]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|counter_reader[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|counter_reader[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X36_Y10_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Add3~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Add3~1_sumout  = SUM(( !\A_SPW_TOP|tx_data|counter_writer [0] $ (!\A_SPW_TOP|tx_data|counter_reader [0]) ) + ( !VCC ) + ( !VCC ))
// \A_SPW_TOP|tx_data|Add3~2  = CARRY(( !\A_SPW_TOP|tx_data|counter_writer [0] $ (!\A_SPW_TOP|tx_data|counter_reader [0]) ) + ( !VCC ) + ( !VCC ))
// \A_SPW_TOP|tx_data|Add3~3  = SHARE((!\A_SPW_TOP|tx_data|counter_reader [0]) # (\A_SPW_TOP|tx_data|counter_writer [0]))

        .dataa(gnd),
        .datab(!\A_SPW_TOP|tx_data|counter_writer [0]),
        .datac(gnd),
        .datad(!\A_SPW_TOP|tx_data|counter_reader [0]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(),
        .sumout(\A_SPW_TOP|tx_data|Add3~1_sumout ),
        .cout(\A_SPW_TOP|tx_data|Add3~2 ),
        .shareout(\A_SPW_TOP|tx_data|Add3~3 ));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Add3~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Add3~1 .lut_mask = 64'h0000FF33000033CC;
defparam \A_SPW_TOP|tx_data|Add3~1 .shared_arith = "on";
// synopsys translate_on

// Location: LABCELL_X36_Y10_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Add3~5 (
// Equation(s):
// \A_SPW_TOP|tx_data|Add3~5_sumout  = SUM(( !\A_SPW_TOP|tx_data|counter_writer [1] $ (\A_SPW_TOP|tx_data|counter_reader [1]) ) + ( \A_SPW_TOP|tx_data|Add3~3  ) + ( \A_SPW_TOP|tx_data|Add3~2  ))
// \A_SPW_TOP|tx_data|Add3~6  = CARRY(( !\A_SPW_TOP|tx_data|counter_writer [1] $ (\A_SPW_TOP|tx_data|counter_reader [1]) ) + ( \A_SPW_TOP|tx_data|Add3~3  ) + ( \A_SPW_TOP|tx_data|Add3~2  ))
// \A_SPW_TOP|tx_data|Add3~7  = SHARE((\A_SPW_TOP|tx_data|counter_writer [1] & !\A_SPW_TOP|tx_data|counter_reader [1]))

        .dataa(!\A_SPW_TOP|tx_data|counter_writer [1]),
        .datab(gnd),
        .datac(!\A_SPW_TOP|tx_data|counter_reader [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\A_SPW_TOP|tx_data|Add3~2 ),
        .sharein(\A_SPW_TOP|tx_data|Add3~3 ),
        .combout(),
        .sumout(\A_SPW_TOP|tx_data|Add3~5_sumout ),
        .cout(\A_SPW_TOP|tx_data|Add3~6 ),
        .shareout(\A_SPW_TOP|tx_data|Add3~7 ));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Add3~5 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Add3~5 .lut_mask = 64'h000050500000A5A5;
defparam \A_SPW_TOP|tx_data|Add3~5 .shared_arith = "on";
// synopsys translate_on

// Location: LABCELL_X36_Y10_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Add3~9 (
// Equation(s):
// \A_SPW_TOP|tx_data|Add3~9_sumout  = SUM(( !\A_SPW_TOP|tx_data|counter_writer [2] $ (\A_SPW_TOP|tx_data|counter_reader [2]) ) + ( \A_SPW_TOP|tx_data|Add3~7  ) + ( \A_SPW_TOP|tx_data|Add3~6  ))
// \A_SPW_TOP|tx_data|Add3~10  = CARRY(( !\A_SPW_TOP|tx_data|counter_writer [2] $ (\A_SPW_TOP|tx_data|counter_reader [2]) ) + ( \A_SPW_TOP|tx_data|Add3~7  ) + ( \A_SPW_TOP|tx_data|Add3~6  ))
// \A_SPW_TOP|tx_data|Add3~11  = SHARE((\A_SPW_TOP|tx_data|counter_writer [2] & !\A_SPW_TOP|tx_data|counter_reader [2]))

        .dataa(gnd),
        .datab(!\A_SPW_TOP|tx_data|counter_writer [2]),
        .datac(!\A_SPW_TOP|tx_data|counter_reader [2]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\A_SPW_TOP|tx_data|Add3~6 ),
        .sharein(\A_SPW_TOP|tx_data|Add3~7 ),
        .combout(),
        .sumout(\A_SPW_TOP|tx_data|Add3~9_sumout ),
        .cout(\A_SPW_TOP|tx_data|Add3~10 ),
        .shareout(\A_SPW_TOP|tx_data|Add3~11 ));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Add3~9 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Add3~9 .lut_mask = 64'h000030300000C3C3;
defparam \A_SPW_TOP|tx_data|Add3~9 .shared_arith = "on";
// synopsys translate_on

// Location: FF_X36_Y10_N8
dffeas \A_SPW_TOP|tx_data|counter[2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|tx_data|Add3~9_sumout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|counter [2]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|counter[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|counter[2] .power_up = "low";
// synopsys translate_on

// Location: FF_X36_Y10_N2
dffeas \A_SPW_TOP|tx_data|counter[0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|tx_data|Add3~1_sumout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|counter [0]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|counter[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|counter[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X36_Y10_N9
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Add3~13 (
// Equation(s):
// \A_SPW_TOP|tx_data|Add3~13_sumout  = SUM(( !\A_SPW_TOP|tx_data|counter_reader [3] $ (\A_SPW_TOP|tx_data|counter_writer [3]) ) + ( \A_SPW_TOP|tx_data|Add3~11  ) + ( \A_SPW_TOP|tx_data|Add3~10  ))
// \A_SPW_TOP|tx_data|Add3~14  = CARRY(( !\A_SPW_TOP|tx_data|counter_reader [3] $ (\A_SPW_TOP|tx_data|counter_writer [3]) ) + ( \A_SPW_TOP|tx_data|Add3~11  ) + ( \A_SPW_TOP|tx_data|Add3~10  ))
// \A_SPW_TOP|tx_data|Add3~15  = SHARE((!\A_SPW_TOP|tx_data|counter_reader [3] & \A_SPW_TOP|tx_data|counter_writer [3]))

        .dataa(!\A_SPW_TOP|tx_data|counter_reader [3]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\A_SPW_TOP|tx_data|counter_writer [3]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\A_SPW_TOP|tx_data|Add3~10 ),
        .sharein(\A_SPW_TOP|tx_data|Add3~11 ),
        .combout(),
        .sumout(\A_SPW_TOP|tx_data|Add3~13_sumout ),
        .cout(\A_SPW_TOP|tx_data|Add3~14 ),
        .shareout(\A_SPW_TOP|tx_data|Add3~15 ));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Add3~13 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Add3~13 .lut_mask = 64'h000000AA0000AA55;
defparam \A_SPW_TOP|tx_data|Add3~13 .shared_arith = "on";
// synopsys translate_on

// Location: FF_X36_Y10_N11
dffeas \A_SPW_TOP|tx_data|counter[3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|tx_data|Add3~13_sumout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|counter [3]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|counter[3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|counter[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X36_Y10_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Add1~4 (
// Equation(s):
// \A_SPW_TOP|tx_data|Add1~4_combout  = ( \A_SPW_TOP|tx_data|counter_writer [5] & ( \A_SPW_TOP|tx_data|counter_writer [1] & ( (!\A_SPW_TOP|tx_data|counter_writer [4]) # ((!\A_SPW_TOP|tx_data|counter_writer [0]) # ((!\A_SPW_TOP|tx_data|counter_writer [3]) # 
// (!\A_SPW_TOP|tx_data|counter_writer [2]))) ) ) ) # ( !\A_SPW_TOP|tx_data|counter_writer [5] & ( \A_SPW_TOP|tx_data|counter_writer [1] & ( (\A_SPW_TOP|tx_data|counter_writer [4] & (\A_SPW_TOP|tx_data|counter_writer [0] & (\A_SPW_TOP|tx_data|counter_writer 
// [3] & \A_SPW_TOP|tx_data|counter_writer [2]))) ) ) ) # ( \A_SPW_TOP|tx_data|counter_writer [5] & ( !\A_SPW_TOP|tx_data|counter_writer [1] ) )

        .dataa(!\A_SPW_TOP|tx_data|counter_writer [4]),
        .datab(!\A_SPW_TOP|tx_data|counter_writer [0]),
        .datac(!\A_SPW_TOP|tx_data|counter_writer [3]),
        .datad(!\A_SPW_TOP|tx_data|counter_writer [2]),
        .datae(!\A_SPW_TOP|tx_data|counter_writer [5]),
        .dataf(!\A_SPW_TOP|tx_data|counter_writer [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Add1~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Add1~4 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Add1~4 .lut_mask = 64'h0000FFFF0001FFFE;
defparam \A_SPW_TOP|tx_data|Add1~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y10_N5
dffeas \A_SPW_TOP|tx_data|counter_writer[5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Add1~4_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|tx_data|state_data_write.10~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|counter_writer [5]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|counter_writer[5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|counter_writer[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X36_Y10_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Add2~4 (
// Equation(s):
// \A_SPW_TOP|tx_data|Add2~4_combout  = ( \A_SPW_TOP|tx_data|counter_reader [4] & ( \A_SPW_TOP|tx_data|counter_reader [1] & ( !\A_SPW_TOP|tx_data|counter_reader [5] $ (((!\A_SPW_TOP|tx_data|counter_reader [2]) # ((!\A_SPW_TOP|tx_data|counter_reader [0]) # 
// (!\A_SPW_TOP|tx_data|counter_reader [3])))) ) ) ) # ( !\A_SPW_TOP|tx_data|counter_reader [4] & ( \A_SPW_TOP|tx_data|counter_reader [1] & ( \A_SPW_TOP|tx_data|counter_reader [5] ) ) ) # ( \A_SPW_TOP|tx_data|counter_reader [4] & ( 
// !\A_SPW_TOP|tx_data|counter_reader [1] & ( \A_SPW_TOP|tx_data|counter_reader [5] ) ) ) # ( !\A_SPW_TOP|tx_data|counter_reader [4] & ( !\A_SPW_TOP|tx_data|counter_reader [1] & ( \A_SPW_TOP|tx_data|counter_reader [5] ) ) )

        .dataa(!\A_SPW_TOP|tx_data|counter_reader [2]),
        .datab(!\A_SPW_TOP|tx_data|counter_reader [0]),
        .datac(!\A_SPW_TOP|tx_data|counter_reader [3]),
        .datad(!\A_SPW_TOP|tx_data|counter_reader [5]),
        .datae(!\A_SPW_TOP|tx_data|counter_reader [4]),
        .dataf(!\A_SPW_TOP|tx_data|counter_reader [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Add2~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Add2~4 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Add2~4 .lut_mask = 64'h00FF00FF00FF01FE;
defparam \A_SPW_TOP|tx_data|Add2~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X36_Y10_N59
dffeas \A_SPW_TOP|tx_data|counter_reader[5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Add2~4_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|tx_data|always3~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|counter_reader [5]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|counter_reader[5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|counter_reader[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X36_Y10_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Add3~17 (
// Equation(s):
// \A_SPW_TOP|tx_data|Add3~17_sumout  = SUM(( !\A_SPW_TOP|tx_data|counter_writer [4] $ (\A_SPW_TOP|tx_data|counter_reader [4]) ) + ( \A_SPW_TOP|tx_data|Add3~15  ) + ( \A_SPW_TOP|tx_data|Add3~14  ))
// \A_SPW_TOP|tx_data|Add3~18  = CARRY(( !\A_SPW_TOP|tx_data|counter_writer [4] $ (\A_SPW_TOP|tx_data|counter_reader [4]) ) + ( \A_SPW_TOP|tx_data|Add3~15  ) + ( \A_SPW_TOP|tx_data|Add3~14  ))
// \A_SPW_TOP|tx_data|Add3~19  = SHARE((\A_SPW_TOP|tx_data|counter_writer [4] & !\A_SPW_TOP|tx_data|counter_reader [4]))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|tx_data|counter_writer [4]),
        .datad(!\A_SPW_TOP|tx_data|counter_reader [4]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\A_SPW_TOP|tx_data|Add3~14 ),
        .sharein(\A_SPW_TOP|tx_data|Add3~15 ),
        .combout(),
        .sumout(\A_SPW_TOP|tx_data|Add3~17_sumout ),
        .cout(\A_SPW_TOP|tx_data|Add3~18 ),
        .shareout(\A_SPW_TOP|tx_data|Add3~19 ));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Add3~17 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Add3~17 .lut_mask = 64'h00000F000000F00F;
defparam \A_SPW_TOP|tx_data|Add3~17 .shared_arith = "on";
// synopsys translate_on

// Location: LABCELL_X36_Y10_N15
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Add3~21 (
// Equation(s):
// \A_SPW_TOP|tx_data|Add3~21_sumout  = SUM(( !\A_SPW_TOP|tx_data|counter_writer [5] $ (\A_SPW_TOP|tx_data|counter_reader [5]) ) + ( \A_SPW_TOP|tx_data|Add3~19  ) + ( \A_SPW_TOP|tx_data|Add3~18  ))

        .dataa(!\A_SPW_TOP|tx_data|counter_writer [5]),
        .datab(gnd),
        .datac(!\A_SPW_TOP|tx_data|counter_reader [5]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\A_SPW_TOP|tx_data|Add3~18 ),
        .sharein(\A_SPW_TOP|tx_data|Add3~19 ),
        .combout(),
        .sumout(\A_SPW_TOP|tx_data|Add3~21_sumout ),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Add3~21 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Add3~21 .lut_mask = 64'h000000000000A5A5;
defparam \A_SPW_TOP|tx_data|Add3~21 .shared_arith = "on";
// synopsys translate_on

// Location: FF_X36_Y10_N17
dffeas \A_SPW_TOP|tx_data|counter[5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|tx_data|Add3~21_sumout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|counter [5]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|counter[5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|counter[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X36_Y10_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|LessThan0~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|LessThan0~0_combout  = ( !\A_SPW_TOP|tx_data|counter [1] & ( !\A_SPW_TOP|tx_data|counter [5] & ( (!\A_SPW_TOP|tx_data|counter [4] & (!\A_SPW_TOP|tx_data|counter [2] & (!\A_SPW_TOP|tx_data|counter [0] & !\A_SPW_TOP|tx_data|counter [3]))) 
// ) ) )

        .dataa(!\A_SPW_TOP|tx_data|counter [4]),
        .datab(!\A_SPW_TOP|tx_data|counter [2]),
        .datac(!\A_SPW_TOP|tx_data|counter [0]),
        .datad(!\A_SPW_TOP|tx_data|counter [3]),
        .datae(!\A_SPW_TOP|tx_data|counter [1]),
        .dataf(!\A_SPW_TOP|tx_data|counter [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|LessThan0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|LessThan0~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|LessThan0~0 .lut_mask = 64'h8000000000000000;
defparam \A_SPW_TOP|tx_data|LessThan0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X36_Y10_N23
dffeas \A_SPW_TOP|tx_data|f_empty (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|LessThan0~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|f_empty~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|f_empty .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|f_empty .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X51_Y6_N57
cyclonev_lcell_comb \A_SPW_TOP|tx_data|state_data_read~10 (
// Equation(s):
// \A_SPW_TOP|tx_data|state_data_read~10_combout  = ( \A_SPW_TOP|tx_data|state_data_read.00~0_combout  & ( \A_SPW_TOP|tx_data|state_data_read.00~q  & ( (\A_SPW_TOP|tx_data|state_data_read.01~q  & ((!\A_SPW_TOP|SPW|TX|ready_tx_data~q ) # 
// (\A_SPW_TOP|tx_data|f_empty~q ))) ) ) ) # ( \A_SPW_TOP|tx_data|state_data_read.00~0_combout  & ( !\A_SPW_TOP|tx_data|state_data_read.00~q  & ( (!\A_SPW_TOP|tx_data|LessThan0~0_combout ) # ((\A_SPW_TOP|tx_data|state_data_read.01~q  & 
// ((!\A_SPW_TOP|SPW|TX|ready_tx_data~q ) # (\A_SPW_TOP|tx_data|f_empty~q )))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|f_empty~q ),
        .datab(!\A_SPW_TOP|tx_data|state_data_read.01~q ),
        .datac(!\A_SPW_TOP|tx_data|LessThan0~0_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|ready_tx_data~q ),
        .datae(!\A_SPW_TOP|tx_data|state_data_read.00~0_combout ),
        .dataf(!\A_SPW_TOP|tx_data|state_data_read.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|state_data_read~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|state_data_read~10 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|state_data_read~10 .lut_mask = 64'h0000F3F100003311;
defparam \A_SPW_TOP|tx_data|state_data_read~10 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X51_Y6_N11
dffeas \A_SPW_TOP|tx_data|state_data_read.01 (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|state_data_read~10_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|state_data_read.01~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|state_data_read.01 .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|state_data_read.01 .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X51_Y6_N45
cyclonev_lcell_comb \A_SPW_TOP|tx_data|state_data_read.00~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|state_data_read.00~0_combout  = ( \A_SPW_TOP|tx_data|state_data_read.01~q  & ( (\A_SPW_TOP|tx_data|state_data_read.00~q  & (!\A_SPW_TOP|tx_data|state_data_read.10~q  & !\A_SPW_TOP|tx_data|state_data_read.11~q )) ) ) # ( 
// !\A_SPW_TOP|tx_data|state_data_read.01~q  & ( (!\A_SPW_TOP|tx_data|state_data_read.00~q  & (!\A_SPW_TOP|tx_data|state_data_read.10~q  & !\A_SPW_TOP|tx_data|state_data_read.11~q )) # (\A_SPW_TOP|tx_data|state_data_read.00~q  & 
// (!\A_SPW_TOP|tx_data|state_data_read.10~q  $ (!\A_SPW_TOP|tx_data|state_data_read.11~q ))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_read.00~q ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|tx_data|state_data_read.10~q ),
        .datad(!\A_SPW_TOP|tx_data|state_data_read.11~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|state_data_read.01~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|state_data_read.00~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|state_data_read.00~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|state_data_read.00~0 .lut_mask = 64'hA550A55050005000;
defparam \A_SPW_TOP|tx_data|state_data_read.00~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X51_Y6_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|state_data_read~11 (
// Equation(s):
// \A_SPW_TOP|tx_data|state_data_read~11_combout  = ( \A_SPW_TOP|tx_data|LessThan0~0_combout  & ( (\A_SPW_TOP|tx_data|state_data_read.00~q  & (!\A_SPW_TOP|tx_data|state_data_read.11~q  & \A_SPW_TOP|tx_data|state_data_read.00~0_combout )) ) ) # ( 
// !\A_SPW_TOP|tx_data|LessThan0~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_read.11~q  & \A_SPW_TOP|tx_data|state_data_read.00~0_combout ) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_read.00~q ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|tx_data|state_data_read.11~q ),
        .datad(!\A_SPW_TOP|tx_data|state_data_read.00~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|LessThan0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|state_data_read~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|state_data_read~11 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|state_data_read~11 .lut_mask = 64'h00F000F000500050;
defparam \A_SPW_TOP|tx_data|state_data_read~11 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X51_Y6_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|state_data_read.00~feeder (
// Equation(s):
// \A_SPW_TOP|tx_data|state_data_read.00~feeder_combout  = ( \A_SPW_TOP|tx_data|state_data_read~11_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|state_data_read~11_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|state_data_read.00~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|state_data_read.00~feeder .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|state_data_read.00~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|tx_data|state_data_read.00~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X51_Y6_N50
dffeas \A_SPW_TOP|tx_data|state_data_read.00 (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|tx_data|state_data_read.00~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|state_data_read.00~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|state_data_read.00 .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|state_data_read.00 .power_up = "low";
// synopsys translate_on

// Location: FF_X51_Y6_N5
dffeas \A_SPW_TOP|tx_data|write_tx (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|state_data_read.00~q ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|write_tx~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|write_tx .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|write_tx .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X58_Y6_N12
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|LessThan3~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|LessThan3~0_combout  = ( \A_SPW_TOP|SPW|TX|global_counter_transfer [0] & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & !\A_SPW_TOP|SPW|TX|global_counter_transfer [3]) ) ) # ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & ( 
// (!\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & ((!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]) # (!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
        .datab(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
        .datac(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|LessThan3~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|LessThan3~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|LessThan3~0 .lut_mask = 64'hC8C8C8C888888888;
defparam \A_SPW_TOP|SPW|TX|LessThan3~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X54_Y5_N46
dffeas \m_x|control_bit_found (
        .clk(!\m_x|always3~0_combout ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|tx_dout_e~q ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|control_bit_found~q ),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|control_bit_found .is_wysiwyg = "true";
defparam \m_x|control_bit_found .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X53_Y5_N24
cyclonev_lcell_comb \m_x|counter_neg[0]~feeder (
// Equation(s):
// \m_x|counter_neg[0]~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|counter_neg[0]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|counter_neg[0]~feeder .extended_lut = "off";
defparam \m_x|counter_neg[0]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \m_x|counter_neg[0]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X54_Y5_N54
cyclonev_lcell_comb \m_x|Selector2~0 (
// Equation(s):
// \m_x|Selector2~0_combout  = (!\m_x|counter_neg [2] & (!\m_x|counter_neg [5] & (\m_x|counter_neg [0] & !\m_x|counter_neg [1])))

        .dataa(!\m_x|counter_neg [2]),
        .datab(!\m_x|counter_neg [5]),
        .datac(!\m_x|counter_neg [0]),
        .datad(!\m_x|counter_neg [1]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|Selector2~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|Selector2~0 .extended_lut = "off";
defparam \m_x|Selector2~0 .lut_mask = 64'h0800080008000800;
defparam \m_x|Selector2~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X54_Y5_N12
cyclonev_lcell_comb \m_x|Selector2~1 (
// Equation(s):
// \m_x|Selector2~1_combout  = (!\m_x|Selector2~0_combout  & (\m_x|counter_neg [4])) # (\m_x|Selector2~0_combout  & ((\m_x|counter_neg [3])))

        .dataa(!\m_x|counter_neg [4]),
        .datab(!\m_x|counter_neg [3]),
        .datac(gnd),
        .datad(!\m_x|Selector2~0_combout ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|Selector2~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|Selector2~1 .extended_lut = "off";
defparam \m_x|Selector2~1 .lut_mask = 64'h5533553355335533;
defparam \m_x|Selector2~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X54_Y5_N53
dffeas \m_x|counter_neg[4] (
        .clk(!\m_x|always3~0_combout ),
        .d(gnd),
        .asdata(\m_x|Selector2~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|counter_neg [4]),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|counter_neg[4] .is_wysiwyg = "true";
defparam \m_x|counter_neg[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X53_Y5_N33
cyclonev_lcell_comb \m_x|WideOr7~0 (
// Equation(s):
// \m_x|WideOr7~0_combout  = ( !\m_x|counter_neg [2] & ( \m_x|counter_neg [5] & ( (\m_x|counter_neg [0] & (!\m_x|counter_neg [3] & (!\m_x|counter_neg [1] & !\m_x|counter_neg [4]))) ) ) ) # ( \m_x|counter_neg [2] & ( !\m_x|counter_neg [5] & ( 
// (\m_x|counter_neg [0] & (!\m_x|counter_neg [3] & (!\m_x|counter_neg [1] & !\m_x|counter_neg [4]))) ) ) ) # ( !\m_x|counter_neg [2] & ( !\m_x|counter_neg [5] & ( (!\m_x|counter_neg [0] & (!\m_x|counter_neg [3] & (!\m_x|counter_neg [1] & !\m_x|counter_neg 
// [4]))) # (\m_x|counter_neg [0] & ((!\m_x|counter_neg [3] & (!\m_x|counter_neg [1] $ (!\m_x|counter_neg [4]))) # (\m_x|counter_neg [3] & (!\m_x|counter_neg [1] & !\m_x|counter_neg [4])))) ) ) )

        .dataa(!\m_x|counter_neg [0]),
        .datab(!\m_x|counter_neg [3]),
        .datac(!\m_x|counter_neg [1]),
        .datad(!\m_x|counter_neg [4]),
        .datae(!\m_x|counter_neg [2]),
        .dataf(!\m_x|counter_neg [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|WideOr7~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|WideOr7~0 .extended_lut = "off";
defparam \m_x|WideOr7~0 .lut_mask = 64'h9440400040000000;
defparam \m_x|WideOr7~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X53_Y5_N26
dffeas \m_x|counter_neg[0] (
        .clk(!\m_x|always3~0_combout ),
        .d(\m_x|counter_neg[0]~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\m_x|WideOr7~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|counter_neg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|counter_neg[0] .is_wysiwyg = "true";
defparam \m_x|counter_neg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X54_Y5_N21
cyclonev_lcell_comb \m_x|Selector3~0 (
// Equation(s):
// \m_x|Selector3~0_combout  = ( !\m_x|counter_neg [1] & ( (!\m_x|is_control~q  & \m_x|counter_neg [2]) ) )

        .dataa(!\m_x|is_control~q ),
        .datab(gnd),
        .datac(gnd),
        .datad(!\m_x|counter_neg [2]),
        .datae(gnd),
        .dataf(!\m_x|counter_neg [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|Selector3~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|Selector3~0 .extended_lut = "off";
defparam \m_x|Selector3~0 .lut_mask = 64'h00AA00AA00000000;
defparam \m_x|Selector3~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X54_Y5_N0
cyclonev_lcell_comb \m_x|Selector3~1 (
// Equation(s):
// \m_x|Selector3~1_combout  = ( \m_x|Selector2~0_combout  & ( \m_x|counter_neg [3] & ( ((\m_x|counter_neg [0] & (!\m_x|counter_neg [5] & \m_x|Selector3~0_combout ))) # (\m_x|counter_neg [4]) ) ) ) # ( !\m_x|Selector2~0_combout  & ( \m_x|counter_neg [3] ) ) 
// # ( \m_x|Selector2~0_combout  & ( !\m_x|counter_neg [3] & ( (\m_x|counter_neg [0] & (!\m_x|counter_neg [5] & (!\m_x|counter_neg [4] & \m_x|Selector3~0_combout ))) ) ) ) # ( !\m_x|Selector2~0_combout  & ( !\m_x|counter_neg [3] & ( (\m_x|counter_neg [0] & 
// (!\m_x|counter_neg [5] & (!\m_x|counter_neg [4] & \m_x|Selector3~0_combout ))) ) ) )

        .dataa(!\m_x|counter_neg [0]),
        .datab(!\m_x|counter_neg [5]),
        .datac(!\m_x|counter_neg [4]),
        .datad(!\m_x|Selector3~0_combout ),
        .datae(!\m_x|Selector2~0_combout ),
        .dataf(!\m_x|counter_neg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|Selector3~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|Selector3~1 .extended_lut = "off";
defparam \m_x|Selector3~1 .lut_mask = 64'h00400040FFFF0F4F;
defparam \m_x|Selector3~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X54_Y5_N44
dffeas \m_x|counter_neg[3] (
        .clk(!\m_x|always3~0_combout ),
        .d(gnd),
        .asdata(\m_x|Selector3~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|counter_neg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|counter_neg[3] .is_wysiwyg = "true";
defparam \m_x|counter_neg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X54_Y5_N36
cyclonev_lcell_comb \m_x|Selector1~0 (
// Equation(s):
// \m_x|Selector1~0_combout  = ( !\m_x|counter_neg [2] & ( \m_x|counter_neg [0] & ( (!\m_x|counter_neg [1] & !\m_x|counter_neg [3]) ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\m_x|counter_neg [1]),
        .datad(!\m_x|counter_neg [3]),
        .datae(!\m_x|counter_neg [2]),
        .dataf(!\m_x|counter_neg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|Selector1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|Selector1~0 .extended_lut = "off";
defparam \m_x|Selector1~0 .lut_mask = 64'h00000000F0000000;
defparam \m_x|Selector1~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X53_Y5_N27
cyclonev_lcell_comb \m_x|Selector1~1 (
// Equation(s):
// \m_x|Selector1~1_combout  = ( \m_x|counter_neg [4] & ( (\m_x|counter_neg [5]) # (\m_x|Selector1~0_combout ) ) ) # ( !\m_x|counter_neg [4] & ( (!\m_x|Selector1~0_combout  & \m_x|counter_neg [5]) ) )

        .dataa(gnd),
        .datab(!\m_x|Selector1~0_combout ),
        .datac(!\m_x|counter_neg [5]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\m_x|counter_neg [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|Selector1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|Selector1~1 .extended_lut = "off";
defparam \m_x|Selector1~1 .lut_mask = 64'h0C0C0C0C3F3F3F3F;
defparam \m_x|Selector1~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X53_Y5_N11
dffeas \m_x|counter_neg[5] (
        .clk(!\m_x|always3~0_combout ),
        .d(gnd),
        .asdata(\m_x|Selector1~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|counter_neg [5]),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|counter_neg[5] .is_wysiwyg = "true";
defparam \m_x|counter_neg[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X54_Y5_N57
cyclonev_lcell_comb \m_x|Selector5~0 (
// Equation(s):
// \m_x|Selector5~0_combout  = ( \m_x|counter_neg [1] & ( (\m_x|counter_neg [2] & (!\m_x|counter_neg [5] & (\m_x|counter_neg [0] & \m_x|is_control~q ))) ) ) # ( !\m_x|counter_neg [1] & ( (!\m_x|counter_neg [2] & (!\m_x|counter_neg [5] $ ((\m_x|counter_neg 
// [0])))) # (\m_x|counter_neg [2] & (!\m_x|counter_neg [5] & (\m_x|counter_neg [0] & \m_x|is_control~q ))) ) )

        .dataa(!\m_x|counter_neg [2]),
        .datab(!\m_x|counter_neg [5]),
        .datac(!\m_x|counter_neg [0]),
        .datad(!\m_x|is_control~q ),
        .datae(gnd),
        .dataf(!\m_x|counter_neg [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|Selector5~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|Selector5~0 .extended_lut = "off";
defparam \m_x|Selector5~0 .lut_mask = 64'h8286828600040004;
defparam \m_x|Selector5~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X53_Y5_N57
cyclonev_lcell_comb \m_x|Selector0~1 (
// Equation(s):
// \m_x|Selector0~1_combout  = ( !\m_x|counter_neg [2] & ( (\m_x|counter_neg [0] & (!\m_x|counter_neg [3] & (!\m_x|counter_neg [5] & !\m_x|counter_neg [4]))) ) )

        .dataa(!\m_x|counter_neg [0]),
        .datab(!\m_x|counter_neg [3]),
        .datac(!\m_x|counter_neg [5]),
        .datad(!\m_x|counter_neg [4]),
        .datae(!\m_x|counter_neg [2]),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|Selector0~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|Selector0~1 .extended_lut = "off";
defparam \m_x|Selector0~1 .lut_mask = 64'h4000000040000000;
defparam \m_x|Selector0~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X54_Y5_N42
cyclonev_lcell_comb \m_x|Selector5~1 (
// Equation(s):
// \m_x|Selector5~1_combout  = ( \m_x|counter_neg [4] & ( (\m_x|counter_neg [1] & !\m_x|Selector0~1_combout ) ) ) # ( !\m_x|counter_neg [4] & ( (!\m_x|counter_neg [1] & (\m_x|Selector5~0_combout  & ((!\m_x|counter_neg [3])))) # (\m_x|counter_neg [1] & 
// ((!\m_x|Selector0~1_combout ) # ((\m_x|Selector5~0_combout  & !\m_x|counter_neg [3])))) ) )

        .dataa(!\m_x|counter_neg [1]),
        .datab(!\m_x|Selector5~0_combout ),
        .datac(!\m_x|Selector0~1_combout ),
        .datad(!\m_x|counter_neg [3]),
        .datae(gnd),
        .dataf(!\m_x|counter_neg [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|Selector5~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|Selector5~1 .extended_lut = "off";
defparam \m_x|Selector5~1 .lut_mask = 64'h7350735050505050;
defparam \m_x|Selector5~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X54_Y5_N56
dffeas \m_x|counter_neg[1] (
        .clk(!\m_x|always3~0_combout ),
        .d(gnd),
        .asdata(\m_x|Selector5~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|counter_neg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|counter_neg[1] .is_wysiwyg = "true";
defparam \m_x|counter_neg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X54_Y5_N15
cyclonev_lcell_comb \m_x|Selector0~0 (
// Equation(s):
// \m_x|Selector0~0_combout  = ( !\m_x|counter_neg [5] & ( (!\m_x|counter_neg [4] & (!\m_x|counter_neg [3] & \m_x|counter_neg [0])) ) )

        .dataa(!\m_x|counter_neg [4]),
        .datab(gnd),
        .datac(!\m_x|counter_neg [3]),
        .datad(!\m_x|counter_neg [0]),
        .datae(gnd),
        .dataf(!\m_x|counter_neg [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|Selector0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|Selector0~0 .extended_lut = "off";
defparam \m_x|Selector0~0 .lut_mask = 64'h00A000A000000000;
defparam \m_x|Selector0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X54_Y5_N45
cyclonev_lcell_comb \m_x|Selector4~0 (
// Equation(s):
// \m_x|Selector4~0_combout  = ( \m_x|Selector0~0_combout  & ( \m_x|counter_neg [1] ) ) # ( !\m_x|Selector0~0_combout  & ( \m_x|counter_neg [2] ) )

        .dataa(!\m_x|counter_neg [1]),
        .datab(gnd),
        .datac(!\m_x|counter_neg [2]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\m_x|Selector0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|Selector4~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|Selector4~0 .extended_lut = "off";
defparam \m_x|Selector4~0 .lut_mask = 64'h0F0F0F0F55555555;
defparam \m_x|Selector4~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X54_Y5_N23
dffeas \m_x|counter_neg[2] (
        .clk(!\m_x|always3~0_combout ),
        .d(gnd),
        .asdata(\m_x|Selector4~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|counter_neg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|counter_neg[2] .is_wysiwyg = "true";
defparam \m_x|counter_neg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X54_Y5_N48
cyclonev_lcell_comb \m_x|Selector0~2 (
// Equation(s):
// \m_x|Selector0~2_combout  = ( \m_x|counter_neg [1] & ( !\m_x|counter_neg [3] & ( (!\m_x|counter_neg [2] & (\m_x|counter_neg [0] & (!\m_x|counter_neg [4] & !\m_x|counter_neg [5]))) ) ) ) # ( !\m_x|counter_neg [1] & ( !\m_x|counter_neg [3] & ( 
// (\m_x|counter_neg [0] & (!\m_x|counter_neg [4] & (!\m_x|counter_neg [2] $ (!\m_x|counter_neg [5])))) ) ) )

        .dataa(!\m_x|counter_neg [2]),
        .datab(!\m_x|counter_neg [0]),
        .datac(!\m_x|counter_neg [4]),
        .datad(!\m_x|counter_neg [5]),
        .datae(!\m_x|counter_neg [1]),
        .dataf(!\m_x|counter_neg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|Selector0~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|Selector0~2 .extended_lut = "off";
defparam \m_x|Selector0~2 .lut_mask = 64'h1020200000000000;
defparam \m_x|Selector0~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X54_Y5_N27
cyclonev_lcell_comb \m_x|Selector0~3 (
// Equation(s):
// \m_x|Selector0~3_combout  = ( \m_x|Selector0~1_combout  & ( (!\m_x|Selector0~2_combout  & (\m_x|is_control~q )) # (\m_x|Selector0~2_combout  & (((\m_x|control_bit_found~q  & \m_x|counter_neg [1])))) ) ) # ( !\m_x|Selector0~1_combout  & ( 
// (\m_x|is_control~q  & !\m_x|Selector0~2_combout ) ) )

        .dataa(!\m_x|is_control~q ),
        .datab(!\m_x|control_bit_found~q ),
        .datac(!\m_x|Selector0~2_combout ),
        .datad(!\m_x|counter_neg [1]),
        .datae(gnd),
        .dataf(!\m_x|Selector0~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|Selector0~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|Selector0~3 .extended_lut = "off";
defparam \m_x|Selector0~3 .lut_mask = 64'h5050505050535053;
defparam \m_x|Selector0~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X54_Y5_N29
dffeas \m_x|is_control (
        .clk(!\m_x|always3~0_combout ),
        .d(\m_x|Selector0~3_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|is_control~q ),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|is_control .is_wysiwyg = "true";
defparam \m_x|is_control .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X54_Y5_N6
cyclonev_lcell_comb \m_x|always1~0 (
// Equation(s):
// \m_x|always1~0_combout  = LCELL(( !\m_x|always3~0_combout  & ( (!\m_x|counter_neg [1] & (\m_x|Selector0~0_combout  & \m_x|counter_neg [2])) ) ))

        .dataa(!\m_x|counter_neg [1]),
        .datab(!\m_x|Selector0~0_combout ),
        .datac(gnd),
        .datad(!\m_x|counter_neg [2]),
        .datae(gnd),
        .dataf(!\m_x|always3~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|always1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|always1~0 .extended_lut = "off";
defparam \m_x|always1~0 .lut_mask = 64'h0022002200000000;
defparam \m_x|always1~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X54_Y5_N9
cyclonev_lcell_comb \m_x|always2~0 (
// Equation(s):
// \m_x|always2~0_combout  = LCELL(( \m_x|always3~0_combout  & ( (!\m_x|counter_neg [1] & (\m_x|Selector0~0_combout  & \m_x|counter_neg [2])) ) ))

        .dataa(!\m_x|counter_neg [1]),
        .datab(gnd),
        .datac(!\m_x|Selector0~0_combout ),
        .datad(!\m_x|counter_neg [2]),
        .datae(gnd),
        .dataf(!\m_x|always3~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|always2~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|always2~0 .extended_lut = "off";
defparam \m_x|always2~0 .lut_mask = 64'h00000000000A000A;
defparam \m_x|always2~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X54_Y5_N24
cyclonev_lcell_comb \m_x|ready_control_p_r~0 (
// Equation(s):
// \m_x|ready_control_p_r~0_combout  = ( \m_x|always2~0_combout  & ( (\m_x|ready_control_p_r~q ) # (\m_x|is_control~q ) ) ) # ( !\m_x|always2~0_combout  & ( (\m_x|always1~0_combout  & ((\m_x|ready_control_p_r~q ) # (\m_x|is_control~q ))) ) )

        .dataa(!\m_x|is_control~q ),
        .datab(gnd),
        .datac(!\m_x|ready_control_p_r~q ),
        .datad(!\m_x|always1~0_combout ),
        .datae(gnd),
        .dataf(!\m_x|always2~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|ready_control_p_r~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|ready_control_p_r~0 .extended_lut = "off";
defparam \m_x|ready_control_p_r~0 .lut_mask = 64'h005F005F5F5F5F5F;
defparam \m_x|ready_control_p_r~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X54_Y5_N38
dffeas \m_x|ready_control_p_r (
        .clk(!\m_x|always3~0_combout ),
        .d(gnd),
        .asdata(\m_x|ready_control_p_r~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|ready_control_p_r~q ),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|ready_control_p_r .is_wysiwyg = "true";
defparam \m_x|ready_control_p_r .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X51_Y5_N15
cyclonev_lcell_comb \m_x|bit_c_1~feeder (
// Equation(s):
// \m_x|bit_c_1~feeder_combout  = ( \A_SPW_TOP|SPW|TX|tx_dout_e~q  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|tx_dout_e~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|bit_c_1~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|bit_c_1~feeder .extended_lut = "off";
defparam \m_x|bit_c_1~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \m_x|bit_c_1~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X51_Y5_N17
dffeas \m_x|bit_c_1 (
        .clk(\m_x|always3~0_combout ),
        .d(\m_x|bit_c_1~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|bit_c_1~q ),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|bit_c_1 .is_wysiwyg = "true";
defparam \m_x|bit_c_1 .power_up = "low";
// synopsys translate_on

// Location: FF_X55_Y5_N26
dffeas \m_x|control_r[1] (
        .clk(\m_x|always1~0_combout ),
        .d(gnd),
        .asdata(\m_x|bit_c_1~q ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|control_r [1]),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|control_r[1] .is_wysiwyg = "true";
defparam \m_x|control_r[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X55_Y5_N36
cyclonev_lcell_comb \m_x|control_p_r[1]~feeder (
// Equation(s):
// \m_x|control_p_r[1]~feeder_combout  = ( \m_x|control_r [1] )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\m_x|control_r [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|control_p_r[1]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|control_p_r[1]~feeder .extended_lut = "off";
defparam \m_x|control_p_r[1]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \m_x|control_p_r[1]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X55_Y5_N37
dffeas \m_x|control_p_r[1] (
        .clk(\m_x|always2~0_combout ),
        .d(\m_x|control_p_r[1]~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|control_p_r [1]),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|control_p_r[1] .is_wysiwyg = "true";
defparam \m_x|control_p_r[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X53_Y9_N45
cyclonev_lcell_comb \m_x|control~1 (
// Equation(s):
// \m_x|control~1_combout  = ( \m_x|control [1] & ( \m_x|control_p_r [1] ) ) # ( !\m_x|control [1] & ( \m_x|control_p_r [1] & ( \m_x|ready_control_p_r~q  ) ) ) # ( \m_x|control [1] & ( !\m_x|control_p_r [1] & ( !\m_x|ready_control_p_r~q  ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\m_x|ready_control_p_r~q ),
        .datad(gnd),
        .datae(!\m_x|control [1]),
        .dataf(!\m_x|control_p_r [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|control~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|control~1 .extended_lut = "off";
defparam \m_x|control~1 .lut_mask = 64'h0000F0F00F0FFFFF;
defparam \m_x|control~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X53_Y5_N36
cyclonev_lcell_comb \m_x|ready_data (
// Equation(s):
// \m_x|ready_data~combout  = LCELL(( \m_x|Selector1~0_combout  & ( !\m_x|always3~0_combout  & ( (!\m_x|always1~0_combout  & (!\m_x|counter_neg [4] & \m_x|counter_neg [5])) ) ) ))

        .dataa(!\m_x|always1~0_combout ),
        .datab(gnd),
        .datac(!\m_x|counter_neg [4]),
        .datad(!\m_x|counter_neg [5]),
        .datae(!\m_x|Selector1~0_combout ),
        .dataf(!\m_x|always3~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|ready_data~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|ready_data .extended_lut = "off";
defparam \m_x|ready_data .lut_mask = 64'h000000A000000000;
defparam \m_x|ready_data .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X54_Y5_N33
cyclonev_lcell_comb \m_x|ready_data_p (
// Equation(s):
// \m_x|ready_data_p~combout  = LCELL(( \m_x|Selector1~0_combout  & ( \m_x|always3~0_combout  & ( (\m_x|counter_neg [5] & (!\m_x|always2~0_combout  & !\m_x|counter_neg [4])) ) ) ))

        .dataa(gnd),
        .datab(!\m_x|counter_neg [5]),
        .datac(!\m_x|always2~0_combout ),
        .datad(!\m_x|counter_neg [4]),
        .datae(!\m_x|Selector1~0_combout ),
        .dataf(!\m_x|always3~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|ready_data_p~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|ready_data_p .extended_lut = "off";
defparam \m_x|ready_data_p .lut_mask = 64'h0000000000003000;
defparam \m_x|ready_data_p .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X54_Y5_N18
cyclonev_lcell_comb \m_x|ready_data_p_r~0 (
// Equation(s):
// \m_x|ready_data_p_r~0_combout  = ( \m_x|ready_data_p~combout  & ( (!\m_x|is_control~q ) # (\m_x|ready_data_p_r~q ) ) ) # ( !\m_x|ready_data_p~combout  & ( (\m_x|ready_data~combout  & ((!\m_x|is_control~q ) # (\m_x|ready_data_p_r~q ))) ) )

        .dataa(!\m_x|is_control~q ),
        .datab(gnd),
        .datac(!\m_x|ready_data_p_r~q ),
        .datad(!\m_x|ready_data~combout ),
        .datae(gnd),
        .dataf(!\m_x|ready_data_p~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|ready_data_p_r~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|ready_data_p_r~0 .extended_lut = "off";
defparam \m_x|ready_data_p_r~0 .lut_mask = 64'h00AF00AFAFAFAFAF;
defparam \m_x|ready_data_p_r~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X54_Y5_N35
dffeas \m_x|ready_data_p_r (
        .clk(!\m_x|always3~0_combout ),
        .d(gnd),
        .asdata(\m_x|ready_data_p_r~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|ready_data_p_r~q ),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|ready_data_p_r .is_wysiwyg = "true";
defparam \m_x|ready_data_p_r .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X54_Y9_N3
cyclonev_lcell_comb \m_x|next_state_data_process.01~0 (
// Equation(s):
// \m_x|next_state_data_process.01~0_combout  = ( \m_x|ready_data_p_r~q  & ( \m_x|ready_control_p_r~q  & ( !\m_x|state_data_process.01~q  ) ) ) # ( !\m_x|ready_data_p_r~q  & ( \m_x|ready_control_p_r~q  & ( !\m_x|state_data_process.01~q  ) ) ) # ( 
// \m_x|ready_data_p_r~q  & ( !\m_x|ready_control_p_r~q  & ( !\m_x|state_data_process.01~q  ) ) )

        .dataa(!\m_x|state_data_process.01~q ),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\m_x|ready_data_p_r~q ),
        .dataf(!\m_x|ready_control_p_r~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|next_state_data_process.01~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|next_state_data_process.01~0 .extended_lut = "off";
defparam \m_x|next_state_data_process.01~0 .lut_mask = 64'h0000AAAAAAAAAAAA;
defparam \m_x|next_state_data_process.01~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X54_Y9_N56
dffeas \m_x|state_data_process.01 (
        .clk(!\m_x|always3~0_combout ),
        .d(gnd),
        .asdata(\m_x|next_state_data_process.01~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|state_data_process.01~q ),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|state_data_process.01 .is_wysiwyg = "true";
defparam \m_x|state_data_process.01 .power_up = "low";
// synopsys translate_on

// Location: FF_X53_Y9_N23
dffeas \m_x|control[1] (
        .clk(!\m_x|always3~0_combout ),
        .d(gnd),
        .asdata(\m_x|control~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(!\m_x|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|control [1]),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|control[1] .is_wysiwyg = "true";
defparam \m_x|control[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X53_Y9_N21
cyclonev_lcell_comb \m_x|control_l_r~1 (
// Equation(s):
// \m_x|control_l_r~1_combout  = ( \m_x|control [1] & ( \m_x|control_l_r [1] ) ) # ( !\m_x|control [1] & ( \m_x|control_l_r [1] & ( !\m_x|ready_control_p_r~q  ) ) ) # ( \m_x|control [1] & ( !\m_x|control_l_r [1] & ( \m_x|ready_control_p_r~q  ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\m_x|ready_control_p_r~q ),
        .datad(gnd),
        .datae(!\m_x|control [1]),
        .dataf(!\m_x|control_l_r [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|control_l_r~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|control_l_r~1 .extended_lut = "off";
defparam \m_x|control_l_r~1 .lut_mask = 64'h00000F0FF0F0FFFF;
defparam \m_x|control_l_r~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X53_Y9_N20
dffeas \m_x|control_l_r[1] (
        .clk(!\m_x|always3~0_combout ),
        .d(gnd),
        .asdata(\m_x|control_l_r~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(!\m_x|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|control_l_r [1]),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|control_l_r[1] .is_wysiwyg = "true";
defparam \m_x|control_l_r[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X53_Y9_N11
dffeas \m_x|info[11] (
        .clk(!\m_x|always3~0_combout ),
        .d(gnd),
        .asdata(\m_x|control_l_r [1]),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\m_x|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|info [11]),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|info[11] .is_wysiwyg = "true";
defparam \m_x|info[11] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y37_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_017|src_payload~13 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_017|src_payload~13_combout  = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout  & ( \u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_017|src_payload~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~13 .lut_mask = 64'h0F0F0F0F00000000;
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~13 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y33_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y33_N41
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y33_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout  = !\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]

        .dataa(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .lut_mask = 64'hAAAAAAAAAAAAAAAA;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y33_N47
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y33_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override~feeder (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y33_N38
dffeas \u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y33_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|write~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|write~0_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0_combout  & ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~0_combout  ) ) # ( 
// !\u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0_combout  & ( (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~0_combout  & \u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~0_combout ),
        .datab(!\u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0_combout ),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|write~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|write~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h1111111155555555;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|write~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y32_N5
dffeas \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_busy (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y37_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y37_N44
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y33_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0_combout  & ( 
// (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0_combout  & ( 
// (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & \u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datad(!\u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h000A000A0A0A0A0A;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y33_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout  = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg 
// [2] & ( (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) # 
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) ) ) 
// # ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) # 
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) # (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) 
// ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .lut_mask = 64'h33CF33CF30CC30CC;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y33_N53
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y33_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout  = ( 
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) # 
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) 
// # (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) # 
// ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) # 
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) 
// # (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .lut_mask = 64'h54BA54BA10FE10FE;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y33_N17
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";
// synopsys translate_on

// Location: FF_X21_Y33_N26
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y33_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout  = ( 
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( 
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]) # 
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])))) # (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] 
// & ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & 
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) # (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) ) # ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] 
// & ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datae(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .lut_mask = 64'h0000FFFFE2222EEE;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y33_N14
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y33_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  = ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( 
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) 
// ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h3000300000000000;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y33_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout  = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  
// & ( (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg 
// [5])))) # (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// ((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) # 
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg 
// [2])))) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  & ( 
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) # 
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) 
// # (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .lut_mask = 64'h10FE10FEDC32DC32;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y33_N19
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y33_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout  = ( 
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  & ( 
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) 
// # (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # 
// ((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )))) ) ) ) # ( 
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  & ( 
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg 
// [5])))) # (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & 
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ))) ) ) ) # ( 
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  & ( 
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # ((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) # 
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ) ) # ( 
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  & ( 
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datae(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .lut_mask = 64'h0202FEFECE0232FE;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y33_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout  = ( 
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout  & ( 
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout  & ( 
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout  & 
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout  & 
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout )) ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
        .datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
        .datae(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .lut_mask = 64'hC000000000000000;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y33_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout  = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout  & ( 
// ((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) # (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout  & ( (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
        .datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h004400440F4F0F4F;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y33_N17
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y33_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  = ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .lut_mask = 64'hFFFF000000000000;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y33_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout  = ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & ( 
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h0101010100000000;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y33_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout  = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout  & ( (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ) ) ) ) # ( 
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout  & ( 
// ((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout )) # 
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ) ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout  & ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout  ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
        .datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datae(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h0F0F0FCF000000CC;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y33_N29
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";
// synopsys translate_on

// Location: FF_X21_Y33_N35
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][75] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][75]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y33_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~6 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~6_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][75]~q  ) ) # ( 
// !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][75]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h0303030300FF00FF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y33_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0_combout  & ( (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [0]) # 
// (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0_combout  & ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [0] ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hAAAAAAAAFAFAFAFA;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y32_N41
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][75] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~6_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][75]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";
// synopsys translate_on

// Location: FF_X21_Y33_N47
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][78] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][78]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y33_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~3 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~3_combout  = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( 
// (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) # 
// (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][78]~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][78]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][78]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h005500550A5F0A5F;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y32_N53
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][78] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~3_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][78]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";
// synopsys translate_on

// Location: FF_X21_Y33_N32
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][76] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][76]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y33_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~5 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~5_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][76]~q  ) ) # ( 
// !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][76]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h0303030300FF00FF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y32_N44
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][76] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~5_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][76]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";
// synopsys translate_on

// Location: FF_X21_Y33_N59
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][77] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][77]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y33_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~4 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~4_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][77]~q  & ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] ) ) # ( 
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][77]~q  & ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ( 
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) 
// ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][77]~q  & ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ( 
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) 
// ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][77]~q ),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~4 .lut_mask = 64'h030303030000FFFF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y32_N47
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][77] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~4_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][77]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";
// synopsys translate_on

// Location: FF_X21_Y33_N38
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][74] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~7_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][74]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y33_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~7 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~7_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][74]~q  & ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] ) ) # ( 
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][74]~q  & ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ( 
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))) # 
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg 
// [2])) ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][74]~q  & ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ( 
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))) # 
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg 
// [2])) ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datae(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][74]~q ),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h03CF03CF0000FFFF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y32_N11
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][74] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~7_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][74]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y32_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~0_combout  = ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][77]~q  & ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][74]~q  & ( 
// (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_busy~q  & (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][75]~q  & (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][78]~q  & 
// !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][76]~q ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .datab(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][78]~q ),
        .datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datae(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][77]~q ),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h0000000080000000;
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y32_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~0_combout  = ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][74]~q  & ( (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][76]~q  & 
// (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][77]~q  & !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][75]~q )) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][77]~q ),
        .datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~0 .lut_mask = 64'hC000C00000000000;
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y32_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout  & ( (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][74]~q  $ 
// (((\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][75]~q ))))) # (\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (((\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout  & ( (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][74]~q  $ 
// (((\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][75]~q ))))) # (\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (((!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datab(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datae(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h00000000D8728D27;
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y32_N56
dffeas \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y32_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~1_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][75]~q  & ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][77]~q  ) ) # ( 
// !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][75]~q  & ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][77]~q  $ (((!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][74]~q  & 
// !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][76]~q ))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][77]~q ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h3CCC3CCCCCCCCCCC;
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y32_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~0_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3] 
// & !\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( 
// (\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) # (\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3]) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datad(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h0FFF0FFFF000F000;
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y32_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][74]~q  & ( \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout  & ( 
// (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ((\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][76]~q ))) # 
// (\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~0_combout )) ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][74]~q  & ( 
// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout  & ( (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ((!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][76]~q  $ 
// (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][75]~q )))) # (\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~0_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~0_combout ),
        .datab(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datae(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][74]~q ),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h00000000CA3A3A3A;
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y32_N26
dffeas \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y32_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~2_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( !\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [5] 
// ) ) # ( !\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( !\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [5] $ 
// (((!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & !\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3]))) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datab(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datac(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h78787878F0F0F0F0;
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~2 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y32_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout  & ( 
// (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~1_combout )) # 
// (\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ((!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~2_combout ))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~1_combout ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~2_combout ),
        .datad(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h00000000CCF0CCF0;
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y32_N32
dffeas \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y32_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~1_combout  = ( !\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter 
// [3] & (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & !\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [5])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datac(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datad(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~1 .lut_mask = 64'hC000C00000000000;
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y32_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( 
// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout  & ( (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][78]~q  $ 
// ((!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~0_combout )))) # (\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (((!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~1_combout )))) 
// ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout  & ( 
// (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][78]~q  $ ((!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~0_combout )))) # 
// (\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (((\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~1_combout )))) ) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][78]~q ),
        .datab(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~0_combout ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datad(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~1_combout ),
        .datae(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h00000000606F6F60;
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y32_N14
dffeas \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y32_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~1_combout  & ( \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout  & 
// ( (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (((!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][78]~q  & \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~0_combout )))) # 
// (\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6])) ) ) ) # ( 
// !\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~1_combout  & ( \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout  & ( (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  
// & (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][78]~q  & \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~0_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datab(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .datac(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][78]~q ),
        .datad(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~0_combout ),
        .datae(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~1_combout ),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h0000000000A044E4;
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y32_N2
dffeas \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y32_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~1_combout  = ( !\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( 
// (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & 
// !\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3])) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datad(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'hA000A00000000000;
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y32_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( 
// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_busy~q  ) ) # ( !\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( 
// (\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_busy~q  & ((!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~1_combout ) # (\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter 
// [7]))) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .datad(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h00F500F500FF00FF;
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y32_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout  & ( 
// (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~2_combout  & ((!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][74]~q ) # (\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) 
// ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datad(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h00000000C0CCC0CC;
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y32_N23
dffeas \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y32_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~2_combout  = (\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_busy~q  & \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2])

        .dataa(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h0505050505050505;
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y33_N23
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";
// synopsys translate_on

// Location: FF_X21_Y33_N2
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][66]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y33_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~2_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][66]~q  & ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] ) ) # ( 
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][66]~q  & ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] ) ) ) 
// # ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][66]~q  & ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] ) 
// ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][66]~q ),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~2 .lut_mask = 64'h0F0F0F0F0000FFFF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y32_N8
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~2_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][66]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y32_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout  = ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][66]~q  & ( (!\u0|mm_interconnect_0|data_info_s1_agent|comb~0_combout ) # 
// ((!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~0_combout  & ((!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~2_combout ) # 
// (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~1_combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .datab(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .datad(!\u0|mm_interconnect_0|data_info_s1_agent|comb~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][66]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h00000000FFA8FFA8;
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y33_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[0]~1_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout  & ( (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [0]) # 
// (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|write~0_combout ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout  & ( ((\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [0] & 
// ((!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0_combout ) # (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1])))) # (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|write~0_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0_combout ),
        .datab(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|write~0_combout ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h33BF33BF33FF33FF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y33_N35
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X22_Y33_N13
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][129] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][129]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y33_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~1_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ( ((\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~0_combout  & 
// \u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0_combout )) # (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][129]~q ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ( 
// (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~0_combout  & \u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~0_combout ),
        .datab(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][129]~q ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h0505050537373737;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y33_N23
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][129] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][129]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y33_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|comb~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent|comb~0_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [0] ) ) # ( 
// !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [0] & ((\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][129]~q ) # 
// (\u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg [0]))) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [0]),
        .datab(!\u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg [0]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent|comb~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent|comb~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent|comb~0 .lut_mask = 64'h1155115555555555;
defparam \u0|mm_interconnect_0|data_info_s1_agent|comb~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y33_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent|comb~0_combout  & ( \u0|hps_0|fpga_interfaces|h2f_RREADY [0] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|data_info_s1_agent|comb~0_combout ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0 .lut_mask = 64'h00000F0F00000F0F;
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y33_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[1]~0_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout  & ( (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|write~0_combout  & 
// ((\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]))) # (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|write~0_combout  & (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [0])) ) ) # ( 
// !\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout  & ( (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0_combout  & ((!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|write~0_combout  & 
// ((\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]))) # (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|write~0_combout  & (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [0])))) # 
// (\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0_combout  & (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|write~0_combout  & ((\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1])))) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0_combout ),
        .datab(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|write~0_combout ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [0]),
        .datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[1]~0 .lut_mask = 64'h029B029B03CF03CF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[1]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y33_N32
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X22_Y33_N56
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y33_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~0_combout  = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & ( (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & 
// ((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]) # (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~0 .lut_mask = 64'h000000000CCC0CCC;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y33_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter~0_combout  = ( \u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override~q  & ( (!\u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0_combout  & 
// (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~0_combout  & !\u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter [0])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0_combout ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~0_combout ),
        .datad(!\u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter~0 .lut_mask = 64'h000000000C000C00;
defparam \u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y33_N53
dffeas \u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y33_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0_combout  = ( \u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter [0] & ( \u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override~q  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y33_N20
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y33_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ( 
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q  & ( (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) # 
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ) ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ( 
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q  & ( (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) # 
// ((!\u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0_combout  & (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q  & !\u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0_combout ))) ) 
// ) ) # ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q  & ( 
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ) ) ) ) # ( 
// !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q  & ( (!\u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0_combout  & 
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q  & 
// !\u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0_combout ),
        .datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .datad(!\u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0_combout ),
        .datae(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .lut_mask = 64'h02000303CECCCFCF;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y33_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0_combout  & ( 
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0_combout  
// & ( (\u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0_combout  & (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1])) 
// ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0_combout ),
        .datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'h1010101030303030;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y33_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout  = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & ( 
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .lut_mask = 64'hFF00FF00F000F000;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y33_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout  = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( 
// ((\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] & (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & \u0|mm_interconnect_0|cmd_mux_017|last_cycle~0_combout ))) # 
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( 
// (\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] & (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & \u0|mm_interconnect_0|cmd_mux_017|last_cycle~0_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_017|last_cycle~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .lut_mask = 64'h001100110F1F0F1F;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y33_N35
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y33_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  = ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ( 
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  ) ) # ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ( 
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # ((\u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0_combout ) # (\u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datab(!\u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0_combout ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hBFBFBFBFAAAAAAAA;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y33_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & ( 
// (\u0|mm_interconnect_0|cmd_mux_017|last_cycle~0_combout  & (\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] & \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q )) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_017|last_cycle~0_combout ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .lut_mask = 64'h0000000000110011;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y33_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout  = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout  & ( 
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & ((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ) # 
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ))) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout  & ( 
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & (((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q )) # (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),
        .datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .lut_mask = 64'h0545054505550555;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y33_N59
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y33_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( 
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) ) ) # ( 
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & 
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) 
// # (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  $ 
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .lut_mask = 64'hC330C33030003000;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y33_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout  = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & ( 
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & ( (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
        .datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .lut_mask = 64'h0055005550505050;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y33_N56
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .power_up = "low";
// synopsys translate_on

// Location: FF_X23_Y33_N29
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";
// synopsys translate_on

// Location: FF_X23_Y33_N1
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X23_Y33_N14
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y33_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~1_combout  = ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & ( 
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & 
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1])) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent|cp_ready~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~1 .lut_mask = 64'hA000A00000000000;
defparam \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X54_Y5_N5
dffeas \m_x|bit_c_0 (
        .clk(!\m_x|always3~0_combout ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|tx_dout_e~q ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|bit_c_0~q ),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|bit_c_0 .is_wysiwyg = "true";
defparam \m_x|bit_c_0 .power_up = "low";
// synopsys translate_on

// Location: FF_X54_Y5_N31
dffeas \m_x|bit_c_2 (
        .clk(!\m_x|always3~0_combout ),
        .d(gnd),
        .asdata(\m_x|bit_c_0~q ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|bit_c_2~q ),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|bit_c_2 .is_wysiwyg = "true";
defparam \m_x|bit_c_2 .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X55_Y5_N0
cyclonev_lcell_comb \m_x|control_r[2]~feeder (
// Equation(s):
// \m_x|control_r[2]~feeder_combout  = ( \m_x|bit_c_2~q  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\m_x|bit_c_2~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|control_r[2]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|control_r[2]~feeder .extended_lut = "off";
defparam \m_x|control_r[2]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \m_x|control_r[2]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X55_Y5_N2
dffeas \m_x|control_r[2] (
        .clk(\m_x|always1~0_combout ),
        .d(\m_x|control_r[2]~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|control_r [2]),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|control_r[2] .is_wysiwyg = "true";
defparam \m_x|control_r[2] .power_up = "low";
// synopsys translate_on

// Location: FF_X55_Y5_N31
dffeas \m_x|control_p_r[2] (
        .clk(\m_x|always2~0_combout ),
        .d(gnd),
        .asdata(\m_x|control_r [2]),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|control_p_r [2]),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|control_p_r[2] .is_wysiwyg = "true";
defparam \m_x|control_p_r[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X53_Y9_N15
cyclonev_lcell_comb \m_x|control~2 (
// Equation(s):
// \m_x|control~2_combout  = (!\m_x|ready_control_p_r~q  & ((\m_x|control [2]))) # (\m_x|ready_control_p_r~q  & (\m_x|control_p_r [2]))

        .dataa(!\m_x|control_p_r [2]),
        .datab(!\m_x|ready_control_p_r~q ),
        .datac(!\m_x|control [2]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|control~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|control~2 .extended_lut = "off";
defparam \m_x|control~2 .lut_mask = 64'h1D1D1D1D1D1D1D1D;
defparam \m_x|control~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X53_Y9_N29
dffeas \m_x|control[2] (
        .clk(!\m_x|always3~0_combout ),
        .d(gnd),
        .asdata(\m_x|control~2_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(!\m_x|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|control [2]),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|control[2] .is_wysiwyg = "true";
defparam \m_x|control[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X53_Y9_N27
cyclonev_lcell_comb \m_x|control_l_r~2 (
// Equation(s):
// \m_x|control_l_r~2_combout  = ( \m_x|control_l_r [2] & ( (!\m_x|ready_control_p_r~q ) # (\m_x|control [2]) ) ) # ( !\m_x|control_l_r [2] & ( (\m_x|ready_control_p_r~q  & \m_x|control [2]) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\m_x|ready_control_p_r~q ),
        .datad(!\m_x|control [2]),
        .datae(gnd),
        .dataf(!\m_x|control_l_r [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|control_l_r~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|control_l_r~2 .extended_lut = "off";
defparam \m_x|control_l_r~2 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \m_x|control_l_r~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X53_Y9_N26
dffeas \m_x|control_l_r[2] (
        .clk(!\m_x|always3~0_combout ),
        .d(gnd),
        .asdata(\m_x|control_l_r~2_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(!\m_x|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|control_l_r [2]),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|control_l_r[2] .is_wysiwyg = "true";
defparam \m_x|control_l_r[2] .power_up = "low";
// synopsys translate_on

// Location: FF_X53_Y9_N13
dffeas \m_x|info[12] (
        .clk(!\m_x|always3~0_combout ),
        .d(gnd),
        .asdata(\m_x|control_l_r [2]),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\m_x|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|info [12]),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|info[12] .is_wysiwyg = "true";
defparam \m_x|info[12] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y16_N18
cyclonev_lcell_comb \u0|data_info|read_mux_out[12] (
// Equation(s):
// \u0|data_info|read_mux_out [12] = ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & ( 
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & \m_x|info [12]) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datab(gnd),
        .datac(!\m_x|info [12]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|data_info|read_mux_out [12]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|data_info|read_mux_out[12] .extended_lut = "off";
defparam \u0|data_info|read_mux_out[12] .lut_mask = 64'h0A0A0A0A00000000;
defparam \u0|data_info|read_mux_out[12] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y16_N19
dffeas \u0|data_info|readdata[12] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|data_info|read_mux_out [12]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|data_info|readdata [12]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|data_info|readdata[12] .is_wysiwyg = "true";
defparam \u0|data_info|readdata[12] .power_up = "low";
// synopsys translate_on

// Location: FF_X31_Y16_N14
dffeas \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[12] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|data_info|readdata [12]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [12]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[12] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[12] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y33_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|read~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|read~0_combout  = ( \u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg [0] & ( (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ((!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used 
// [0]) # (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][129]~q ))) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg [0] & ( (\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [0] & 
// (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ((!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [0]) # (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][129]~q )))) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [0]),
        .datab(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [0]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
        .datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|read~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|read~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|read~0 .lut_mask = 64'h030203020F0A0F0A;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|read~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y33_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[1]~1_combout  = ( !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|read~0_combout  & ( ((\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [0] & 
// \u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1]) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg [0]),
        .datad(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|read~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[1]~1 .lut_mask = 64'h05FF05FF00000000;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[1]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y33_N29
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X31_Y16_N35
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][12] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~12_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][12]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][12] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][12] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y16_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~12 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~12_combout  = (!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1] & (\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [12])) # 
// (\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1] & ((\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][12]~q )))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [12]),
        .datad(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][12]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~12 .lut_mask = 64'h0C3F0C3F0C3F0C3F;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~12 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y33_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always0~0_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|read~0_combout  ) # ( !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|read~0_combout  & ( 
// !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [0] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|read~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always0~0 .lut_mask = 64'hF0F0F0F0FFFFFFFF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y16_N41
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][12] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~12_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][12]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][12] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][12] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y16_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~32 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~32_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][12]~q  & ( (\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout  & 
// ((!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout ) # (\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [12]))) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][12]~q  & ( 
// (\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout  & (\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [12] & \u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout )) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [12]),
        .datad(!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ),
        .datae(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][12]~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~32_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~32 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~32 .lut_mask = 64'h000500AF000500AF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~32 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X54_Y5_N17
dffeas \m_x|bit_c_3 (
        .clk(\m_x|always3~0_combout ),
        .d(gnd),
        .asdata(\m_x|bit_c_1~q ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|bit_c_3~q ),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|bit_c_3 .is_wysiwyg = "true";
defparam \m_x|bit_c_3 .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X55_Y5_N45
cyclonev_lcell_comb \m_x|control_r[3]~feeder (
// Equation(s):
// \m_x|control_r[3]~feeder_combout  = ( \m_x|bit_c_3~q  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\m_x|bit_c_3~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|control_r[3]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|control_r[3]~feeder .extended_lut = "off";
defparam \m_x|control_r[3]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \m_x|control_r[3]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X55_Y5_N47
dffeas \m_x|control_r[3] (
        .clk(\m_x|always1~0_combout ),
        .d(\m_x|control_r[3]~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|control_r [3]),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|control_r[3] .is_wysiwyg = "true";
defparam \m_x|control_r[3] .power_up = "low";
// synopsys translate_on

// Location: FF_X55_Y5_N35
dffeas \m_x|control_p_r[3] (
        .clk(\m_x|always2~0_combout ),
        .d(gnd),
        .asdata(\m_x|control_r [3]),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|control_p_r [3]),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|control_p_r[3] .is_wysiwyg = "true";
defparam \m_x|control_p_r[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X53_Y9_N33
cyclonev_lcell_comb \m_x|control~3 (
// Equation(s):
// \m_x|control~3_combout  = ( \m_x|control_p_r [3] & ( (\m_x|ready_control_p_r~q ) # (\m_x|control [3]) ) ) # ( !\m_x|control_p_r [3] & ( (\m_x|control [3] & !\m_x|ready_control_p_r~q ) ) )

        .dataa(!\m_x|control [3]),
        .datab(gnd),
        .datac(!\m_x|ready_control_p_r~q ),
        .datad(gnd),
        .datae(!\m_x|control_p_r [3]),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|control~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|control~3 .extended_lut = "off";
defparam \m_x|control~3 .lut_mask = 64'h50505F5F50505F5F;
defparam \m_x|control~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X53_Y9_N50
dffeas \m_x|control[3] (
        .clk(!\m_x|always3~0_combout ),
        .d(gnd),
        .asdata(\m_x|control~3_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(!\m_x|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|control [3]),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|control[3] .is_wysiwyg = "true";
defparam \m_x|control[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X53_Y9_N48
cyclonev_lcell_comb \m_x|control_l_r~3 (
// Equation(s):
// \m_x|control_l_r~3_combout  = ( \m_x|control [3] & ( (\m_x|control_l_r [3]) # (\m_x|ready_control_p_r~q ) ) ) # ( !\m_x|control [3] & ( (!\m_x|ready_control_p_r~q  & \m_x|control_l_r [3]) ) )

        .dataa(gnd),
        .datab(!\m_x|ready_control_p_r~q ),
        .datac(!\m_x|control_l_r [3]),
        .datad(gnd),
        .datae(!\m_x|control [3]),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|control_l_r~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|control_l_r~3 .extended_lut = "off";
defparam \m_x|control_l_r~3 .lut_mask = 64'h0C0C3F3F0C0C3F3F;
defparam \m_x|control_l_r~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X53_Y9_N53
dffeas \m_x|control_l_r[3] (
        .clk(!\m_x|always3~0_combout ),
        .d(gnd),
        .asdata(\m_x|control_l_r~3_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(!\m_x|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|control_l_r [3]),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|control_l_r[3] .is_wysiwyg = "true";
defparam \m_x|control_l_r[3] .power_up = "low";
// synopsys translate_on

// Location: FF_X53_Y9_N31
dffeas \m_x|info[13] (
        .clk(!\m_x|always3~0_combout ),
        .d(gnd),
        .asdata(\m_x|control_l_r [3]),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\m_x|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|info [13]),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|info[13] .is_wysiwyg = "true";
defparam \m_x|info[13] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y13_N21
cyclonev_lcell_comb \u0|data_info|read_mux_out[13] (
// Equation(s):
// \u0|data_info|read_mux_out [13] = ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( (\m_x|info [13] & 
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]) ) )

        .dataa(!\m_x|info [13]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|data_info|read_mux_out [13]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|data_info|read_mux_out[13] .extended_lut = "off";
defparam \u0|data_info|read_mux_out[13] .lut_mask = 64'h5050505000000000;
defparam \u0|data_info|read_mux_out[13] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y13_N23
dffeas \u0|data_info|readdata[13] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|data_info|read_mux_out [13]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|data_info|readdata [13]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|data_info|readdata[13] .is_wysiwyg = "true";
defparam \u0|data_info|readdata[13] .power_up = "low";
// synopsys translate_on

// Location: FF_X31_Y13_N20
dffeas \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[13] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|data_info|readdata [13]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [13]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[13] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[13] .power_up = "low";
// synopsys translate_on

// Location: FF_X30_Y16_N50
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][13] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~13_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][13]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][13] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][13] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y16_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~13 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~13_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][13]~q  & ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1] ) ) # ( 
// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][13]~q  & ( !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [13] ) ) ) # ( 
// !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][13]~q  & ( !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [13] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [13]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][13]~q ),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~13 .lut_mask = 64'h0F0F0F0F0000FFFF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~13 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y16_N35
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][13] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~13_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][13]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][13] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][13] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y16_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~33 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~33_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout  & ( (\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [13] & 
// \u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout  & ( (\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout  & 
// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][13]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [13]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ),
        .datad(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][13]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~33_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~33 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~33 .lut_mask = 64'h000F000F05050505;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~33 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y37_N11
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_busy (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y36_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y35_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override~feeder (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y35_N17
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y35_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter [0] & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override~q  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y35_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y35_N2
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y31_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal2~2 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal2~2_combout  = ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & ( \u0|mm_interconnect_0|router_001|Equal2~0_combout  & ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & 
// (\u0|mm_interconnect_0|router_001|Equal1~1_combout  & \u0|mm_interconnect_0|router_001|Equal1~0_combout ))) ) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),
        .datac(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),
        .datad(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),
        .dataf(!\u0|mm_interconnect_0|router_001|Equal2~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router_001|Equal2~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal2~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal2~2 .lut_mask = 64'h0000000000040000;
defparam \u0|mm_interconnect_0|router_001|Equal2~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y31_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal2~1 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal2~1_combout  = (\u0|mm_interconnect_0|router_001|Equal2~0_combout  & (\u0|mm_interconnect_0|router_001|Equal1~0_combout  & \u0|mm_interconnect_0|router_001|Equal1~1_combout ))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|router_001|Equal2~0_combout ),
        .datac(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),
        .datad(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router_001|Equal2~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal2~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal2~1 .lut_mask = 64'h0003000300030003;
defparam \u0|mm_interconnect_0|router_001|Equal2~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y31_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal1~3 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal1~3_combout  = ( \u0|mm_interconnect_0|router_001|Equal1~1_combout  & ( (\u0|mm_interconnect_0|router_001|Equal1~0_combout  & \u0|mm_interconnect_0|router_001|Equal1~2_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|router_001|Equal1~2_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router_001|Equal1~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal1~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal1~3 .lut_mask = 64'h0000000005050505;
defparam \u0|mm_interconnect_0|router_001|Equal1~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y30_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|src_data[102]~0 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|src_data[102]~0_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & ( \u0|mm_interconnect_0|router_001|Equal1~3_combout  & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & ((!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]) 
// # ((!\u0|mm_interconnect_0|router_001|Equal2~1_combout )))) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & ((!\u0|mm_interconnect_0|router_001|Equal2~1_combout ) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR 
// [16])))) ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & ( \u0|mm_interconnect_0|router_001|Equal1~3_combout  & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] $ 
// (((\u0|mm_interconnect_0|router_001|Equal2~1_combout  & \u0|hps_0|fpga_interfaces|h2f_ARADDR [18]))))) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & (!\u0|mm_interconnect_0|router_001|Equal2~1_combout  & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & 
// \u0|hps_0|fpga_interfaces|h2f_ARADDR [19]))) ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & ( !\u0|mm_interconnect_0|router_001|Equal1~3_combout  & ( (!\u0|mm_interconnect_0|router_001|Equal2~1_combout ) # (!\u0|hps_0|fpga_interfaces|h2f_ARADDR 
// [16] $ (\u0|hps_0|fpga_interfaces|h2f_ARADDR [18])) ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & ( !\u0|mm_interconnect_0|router_001|Equal1~3_combout  & ( (!\u0|mm_interconnect_0|router_001|Equal2~1_combout ) # 
// ((!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & !\u0|hps_0|fpga_interfaces|h2f_ARADDR [18])) ) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),
        .datab(!\u0|mm_interconnect_0|router_001|Equal2~1_combout ),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),
        .dataf(!\u0|mm_interconnect_0|router_001|Equal1~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router_001|src_data[102]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|src_data[102]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|src_data[102]~0 .lut_mask = 64'hECECEDEDA842EDE0;
defparam \u0|mm_interconnect_0|router_001|src_data[102]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y30_N56
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|router_001|src_data[102]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y30_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|src_data[100]~1 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|src_data[100]~1_combout  = ( \u0|mm_interconnect_0|router_001|Equal2~1_combout  & ( \u0|mm_interconnect_0|router_001|Equal1~3_combout  & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & 
// ((!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [16])) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & ((!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]))))) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & 
// (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] $ (((!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [19]))))) ) ) ) # ( !\u0|mm_interconnect_0|router_001|Equal2~1_combout  & ( 
// \u0|mm_interconnect_0|router_001|Equal1~3_combout  & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] $ (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19])))) # 
// (\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] $ (((!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [19]))))) ) ) ) # ( \u0|mm_interconnect_0|router_001|Equal2~1_combout  & ( 
// !\u0|mm_interconnect_0|router_001|Equal1~3_combout  & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & ((\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]))) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & 
// ((!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]))) ) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),
        .datae(!\u0|mm_interconnect_0|router_001|Equal2~1_combout ),
        .dataf(!\u0|mm_interconnect_0|router_001|Equal1~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router_001|src_data[100]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|src_data[100]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|src_data[100]~1 .lut_mask = 64'h00007C7C26527C52;
defparam \u0|mm_interconnect_0|router_001|src_data[100]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y30_N25
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|router_001|src_data[100]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y30_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|src_data[101]~2 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|src_data[101]~2_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & ( \u0|mm_interconnect_0|router_001|Equal1~3_combout  & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & ((!\u0|hps_0|fpga_interfaces|h2f_ARADDR 
// [19]))) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [18])) ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & ( \u0|mm_interconnect_0|router_001|Equal1~3_combout  & ( 
// (!\u0|mm_interconnect_0|router_001|Equal2~1_combout  & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]))) # (\u0|mm_interconnect_0|router_001|Equal2~1_combout  & ((!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & 
// (\u0|hps_0|fpga_interfaces|h2f_ARADDR [16])) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & ((!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]))))) ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & ( !\u0|mm_interconnect_0|router_001|Equal1~3_combout  & ( 
// (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & (\u0|mm_interconnect_0|router_001|Equal2~1_combout  & \u0|hps_0|fpga_interfaces|h2f_ARADDR [18])) ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & ( !\u0|mm_interconnect_0|router_001|Equal1~3_combout  & 
// ( (\u0|mm_interconnect_0|router_001|Equal2~1_combout  & ((\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]))) ) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),
        .datab(!\u0|mm_interconnect_0|router_001|Equal2~1_combout ),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),
        .dataf(!\u0|mm_interconnect_0|router_001|Equal1~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router_001|src_data[101]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|src_data[101]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|src_data[101]~2 .lut_mask = 64'h131302021B18AF05;
defparam \u0|mm_interconnect_0|router_001|src_data[101]~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y30_N43
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|router_001|src_data[101]~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y30_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~0_combout  = ( \u0|mm_interconnect_0|router_001|src_data[100]~1_combout  & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id [0] & 
// (!\u0|mm_interconnect_0|router_001|src_data[101]~2_combout  $ (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id [1]))) ) ) # ( !\u0|mm_interconnect_0|router_001|src_data[100]~1_combout  & ( 
// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id [0] & (!\u0|mm_interconnect_0|router_001|src_data[101]~2_combout  $ (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id [1]))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id [0]),
        .datac(!\u0|mm_interconnect_0|router_001|src_data[101]~2_combout ),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|router_001|src_data[100]~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~0 .lut_mask = 64'hC00CC00C30033003;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y30_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|src_data[103]~3 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|src_data[103]~3_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & ( \u0|mm_interconnect_0|router_001|Equal1~3_combout  & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & ((!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & 
// (!\u0|mm_interconnect_0|router_001|Equal2~1_combout  & !\u0|hps_0|fpga_interfaces|h2f_ARADDR [18])) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & ((\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]))))) ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & ( 
// \u0|mm_interconnect_0|router_001|Equal1~3_combout  & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & ((!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] $ (\u0|hps_0|fpga_interfaces|h2f_ARADDR [19])))) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & 
// (((!\u0|mm_interconnect_0|router_001|Equal2~1_combout  & \u0|hps_0|fpga_interfaces|h2f_ARADDR [18])) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]))) ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & ( !\u0|mm_interconnect_0|router_001|Equal1~3_combout 
//  & ( (!\u0|mm_interconnect_0|router_001|Equal2~1_combout ) # ((\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [18])) ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & ( 
// !\u0|mm_interconnect_0|router_001|Equal1~3_combout  & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]) # (!\u0|mm_interconnect_0|router_001|Equal2~1_combout ) ) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),
        .datab(!\u0|mm_interconnect_0|router_001|Equal2~1_combout ),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),
        .dataf(!\u0|mm_interconnect_0|router_001|Equal1~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router_001|src_data[103]~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|src_data[103]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|src_data[103]~3 .lut_mask = 64'hEEEECDCDA45F8500;
defparam \u0|mm_interconnect_0|router_001|src_data[103]~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y30_N37
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|router_001|src_data[103]~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y30_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|src_data[104]~4 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|src_data[104]~4_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & ( \u0|mm_interconnect_0|router_001|Equal1~3_combout  & ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [19] ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR 
// [17] & ( \u0|mm_interconnect_0|router_001|Equal1~3_combout  & ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & ((!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]) # (\u0|mm_interconnect_0|router_001|Equal2~1_combout 
// )))) ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & ( !\u0|mm_interconnect_0|router_001|Equal1~3_combout  & ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & (\u0|mm_interconnect_0|router_001|Equal2~1_combout  & !\u0|hps_0|fpga_interfaces|h2f_ARADDR 
// [18])) ) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),
        .datab(!\u0|mm_interconnect_0|router_001|Equal2~1_combout ),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),
        .dataf(!\u0|mm_interconnect_0|router_001|Equal1~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router_001|src_data[104]~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|src_data[104]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|src_data[104]~4 .lut_mask = 64'h10100000501000FF;
defparam \u0|mm_interconnect_0|router_001|src_data[104]~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y30_N31
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|router_001|src_data[104]~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y30_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~1 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~1_combout  = ( \u0|mm_interconnect_0|router_001|src_data[104]~4_combout  & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id [4] & 
// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id [3] $ (\u0|mm_interconnect_0|router_001|src_data[103]~3_combout ))) ) ) # ( !\u0|mm_interconnect_0|router_001|src_data[104]~4_combout  & ( 
// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id [4] & (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id [3] $ (\u0|mm_interconnect_0|router_001|src_data[103]~3_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id [3]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id [4]),
        .datad(!\u0|mm_interconnect_0|router_001|src_data[103]~3_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|router_001|src_data[104]~4_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~1 .lut_mask = 64'hA050A0500A050A05;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y30_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout  = ( \u0|mm_interconnect_0|router_001|src_data[102]~0_combout  & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~1_combout  & ( 
// (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) # ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id [2] & 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~0_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|router_001|src_data[102]~0_combout  & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~1_combout  & ( 
// (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) # ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id [2] & 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~0_combout )))) ) ) ) # ( \u0|mm_interconnect_0|router_001|src_data[102]~0_combout  & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~1_combout  & ( 
// (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) ) ) ) # ( !\u0|mm_interconnect_0|router_001|src_data[102]~0_combout  & ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~1_combout  & ( (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) ) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id [2]),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~0_combout ),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
        .datae(!\u0|mm_interconnect_0|router_001|src_data[102]~0_combout ),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0 .lut_mask = 64'h0F000F000F020F01;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y31_N37
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[16] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|router_001|Equal2~2_combout ),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [16]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[16] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[16] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y36_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_016|last_cycle~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_016|last_cycle~0_combout  = ( \u0|mm_interconnect_0|router_001|Equal2~2_combout  & ( (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [16]))) ) )

        .dataa(gnd),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [16]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|router_001|Equal2~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_016|last_cycle~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_016|last_cycle~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_016|last_cycle~0 .lut_mask = 64'h0000000030333033;
defparam \u0|mm_interconnect_0|cmd_mux_016|last_cycle~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y36_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout  = ( \u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] & ( 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  & 
// \u0|mm_interconnect_0|cmd_mux_016|last_cycle~0_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_016|last_cycle~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h0000000000500050;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y36_N5
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y31_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal9~0 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal9~0_combout  = ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [18] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router_001|Equal9~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal9~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal9~0 .lut_mask = 64'h00000000FFFF0000;
defparam \u0|mm_interconnect_0|router_001|Equal9~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y31_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal9~1 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal9~1_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & ( \u0|mm_interconnect_0|router_001|Equal9~0_combout  & ( (\u0|mm_interconnect_0|router_001|Equal1~1_combout  & 
// (\u0|mm_interconnect_0|router_001|Equal1~2_combout  & (\u0|mm_interconnect_0|router_001|Equal1~0_combout  & !\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]))) ) ) )

        .dataa(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),
        .datab(!\u0|mm_interconnect_0|router_001|Equal1~2_combout ),
        .datac(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),
        .dataf(!\u0|mm_interconnect_0|router_001|Equal9~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router_001|Equal9~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal9~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal9~1 .lut_mask = 64'h0000000000000100;
defparam \u0|mm_interconnect_0|router_001|Equal9~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y31_N26
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|router_001|Equal9~1_combout ),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y31_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_005|last_cycle~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [5] & ( (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & \u0|mm_interconnect_0|router_001|Equal9~1_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [5] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q  & (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & \u0|mm_interconnect_0|router_001|Equal9~1_combout 
// )) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|router_001|Equal9~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_005|last_cycle~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_005|last_cycle~0 .lut_mask = 64'h0022002200330033;
defparam \u0|mm_interconnect_0|cmd_mux_005|last_cycle~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X10_Y31_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override~feeder (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y31_N5
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y31_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y31_N23
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y31_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout  = ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout  & ( (\u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout  & (\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] & 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q )) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h0003000300000000;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";
// synopsys translate_on

// Location: FF_X9_Y31_N2
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";
// synopsys translate_on

// Location: FF_X9_Y31_N14
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";
// synopsys translate_on

// Location: FF_X9_Y31_N38
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y31_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg~0_combout  = ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout  & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~0_combout  & ( 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override~q  & \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter [0]) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter [0]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout ),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg~0 .lut_mask = 64'h0000000005050000;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y31_N56
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X10_Y31_N20
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][129] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][129]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y31_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~1_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~0_combout  & ( ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][129]~q )) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~0_combout  & ( 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][129]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][129]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h003300330F3F0F3F;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X9_Y31_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  = ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .lut_mask = 64'hF0F0F0F000000000;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X9_Y31_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  = ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0_combout ) # 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'h1515151500000000;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X8_Y31_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X8_Y31_N11
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y32_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARLEN [0] & ( 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] 
// $ (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0] & ( 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] 
// $ (((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))))) # 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1])))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .lut_mask = 64'h278D278D22882288;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y32_N23
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y22_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|src_payload[0] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|src_payload [0] = ( \u0|hps_0|fpga_interfaces|h2f_WLAST [0] & ( (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]) # (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_WLAST [0] & 
// ( \u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_WLAST [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_009|src_payload [0]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|src_payload[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|src_payload[0] .lut_mask = 64'h5555555577777777;
defparam \u0|mm_interconnect_0|cmd_mux_009|src_payload[0] .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y31_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal1~4 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal1~4_combout  = ( \u0|mm_interconnect_0|router_001|Equal1~0_combout  & ( \u0|mm_interconnect_0|router_001|Equal1~1_combout  & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & 
// (\u0|mm_interconnect_0|router_001|Equal1~2_combout  & \u0|hps_0|fpga_interfaces|h2f_ARADDR [16])) ) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|router_001|Equal1~2_combout ),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),
        .datae(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),
        .dataf(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router_001|Equal1~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal1~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal1~4 .lut_mask = 64'h000000000000000A;
defparam \u0|mm_interconnect_0|router_001|Equal1~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y27_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal15~0 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal15~0_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & ( (\u0|mm_interconnect_0|router_001|Equal1~4_combout  & !\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]) ) )

        .dataa(!\u0|mm_interconnect_0|router_001|Equal1~4_combout ),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router_001|Equal15~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal15~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal15~0 .lut_mask = 64'h0000000050505050;
defparam \u0|mm_interconnect_0|router_001|Equal15~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y27_N17
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[9] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|router_001|Equal15~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [9]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[9] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[9] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y27_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|src9_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|src9_valid~0_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [9]) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [9]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux_001|src9_valid~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|src9_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|src9_valid~0 .lut_mask = 64'h00000000FF0FFF0F;
defparam \u0|mm_interconnect_0|cmd_demux_001|src9_valid~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y27_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|src_valid~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|src_valid~1_combout  = ( \u0|mm_interconnect_0|router_001|Equal1~4_combout  & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & 
// (\u0|mm_interconnect_0|cmd_demux_001|src9_valid~0_combout  & \u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]))) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),
        .datac(!\u0|mm_interconnect_0|cmd_demux_001|src9_valid~0_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|router_001|Equal1~4_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_009|src_valid~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|src_valid~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|src_valid~1 .lut_mask = 64'h0000000000020002;
defparam \u0|mm_interconnect_0|cmd_mux_009|src_valid~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y25_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|packet_in_progress~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|packet_in_progress~0_combout  = !\u0|mm_interconnect_0|cmd_mux_009|update_grant~0_combout 

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_009|update_grant~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_009|packet_in_progress~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|packet_in_progress~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|packet_in_progress~0 .lut_mask = 64'hF0F0F0F0F0F0F0F0;
defparam \u0|mm_interconnect_0|cmd_mux_009|packet_in_progress~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y25_N25
dffeas \u0|mm_interconnect_0|cmd_mux_009|packet_in_progress (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_009|packet_in_progress~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_009|packet_in_progress~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|packet_in_progress .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_009|packet_in_progress .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y22_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|src_data[33] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|src_data [33] = ((\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_WSTRB [1])) # (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1])

        .dataa(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_009|src_data [33]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[33] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[33] .lut_mask = 64'h5757575757575757;
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[33] .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y22_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout  & ( 
// !\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout  & ( (!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & 
// !\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .lut_mask = 64'h88888888AAAAAAAA;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y22_N32
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";
// synopsys translate_on

// Location: FF_X15_Y22_N59
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_009|src_payload [0]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y21_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y21_N47
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y22_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~2 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~2_combout  = ( \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~0_combout  & ( !\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [0] $ 
// (!\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [1]) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [0]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~2 .lut_mask = 64'h0000000055AA55AA;
defparam \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y22_N5
dffeas \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y22_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override~feeder (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y22_N32
dffeas \u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y22_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~0_combout  = ( \u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override~q  & ( !\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [1] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~0 .lut_mask = 64'h00000000FF00FF00;
defparam \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y22_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y22_N53
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y25_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|src_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|src_valid~0_combout  = ( \u0|mm_interconnect_0|router|Equal7~1_combout  & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout  & ( 
// (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & (\u0|mm_interconnect_0|router|Equal14~0_combout  & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout  & \u0|mm_interconnect_0|cmd_demux|src9_valid~0_combout 
// ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|router|Equal14~0_combout ),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_demux|src9_valid~0_combout ),
        .datae(!\u0|mm_interconnect_0|router|Equal7~1_combout ),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_009|src_valid~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|src_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|src_valid~0 .lut_mask = 64'h0000000100000000;
defparam \u0|mm_interconnect_0|cmd_mux_009|src_valid~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y25_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout  = ( \u0|mm_interconnect_0|cmd_mux_009|src_valid~0_combout  & ( 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  ) ) # ( !\u0|mm_interconnect_0|cmd_mux_009|src_valid~0_combout  & ( 
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) # (!\u0|mm_interconnect_0|cmd_mux_009|src_valid~1_combout ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_009|src_valid~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_009|src_valid~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .lut_mask = 64'hFFF0FFF0F0F0F0F0;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y22_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout  = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout  ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( 
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ) # (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .lut_mask = 64'hFF33FF33FF00FF00;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y22_N26
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .power_up = "low";
// synopsys translate_on

// Location: FF_X17_Y22_N8
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y22_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|local_write~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent|local_write~0_combout  = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] & ( 
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_agent|local_write~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|local_write~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|local_write~0 .lut_mask = 64'h0000000000FF00FF;
defparam \u0|mm_interconnect_0|link_disable_s1_agent|local_write~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y22_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~4 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~4_combout  = ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~0_combout  & 
// \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [0]) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~0_combout  & 
// (!\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [0] $ (((!\u0|mm_interconnect_0|link_disable_s1_agent|local_write~0_combout ) # (\u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0_combout ))))) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~0_combout ),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_agent|local_write~0_combout ),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0_combout ),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~4 .lut_mask = 64'h1045104500550055;
defparam \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y22_N11
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";
// synopsys translate_on

// Location: FF_X17_Y22_N17
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y22_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|m0_read~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent|m0_read~0_combout  = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & ( 
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & ( 
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_agent|m0_read~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|m0_read~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|m0_read~0 .lut_mask = 64'h030303030F0F0F0F;
defparam \u0|mm_interconnect_0|link_disable_s1_agent|m0_read~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y22_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|write~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|write~0_combout  = ( \u0|mm_interconnect_0|link_disable_s1_agent|m0_read~0_combout  & ( 
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & 
// ((\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~4_combout ) # (\u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_agent|m0_read~0_combout  & ( 
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( (\u0|mm_interconnect_0|link_disable_s1_agent|local_write~0_combout  & 
// (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~4_combout ) # (\u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0_combout )))) ) ) ) # ( 
// \u0|mm_interconnect_0|link_disable_s1_agent|m0_read~0_combout  & ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( 
// (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~4_combout ) # (\u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0_combout ),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~4_combout ),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_agent|local_write~0_combout ),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),
        .datae(!\u0|mm_interconnect_0|link_disable_s1_agent|m0_read~0_combout ),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|write~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|write~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h0000770007007700;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|write~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y22_N50
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][69] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][69]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][69] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y22_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~1_combout  = ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][69]~q  ) ) # ( 
// !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][69]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h3333333300FF00FF;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y22_N8
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y22_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout  = ( 
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  
// & ( (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) # 
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) ) ) ) # ( 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  
// & ( (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) ) ) ) # ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg 
// [3] & ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) # 
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) ) ) ) # ( 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q 
//  & ( (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) ) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datae(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .lut_mask = 64'h5500AAFF5050FAFA;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y22_N5
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y22_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  = ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg 
// [3] & \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h00C000C000000000;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y22_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout  = ( 
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & ( (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q 
//  & (((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout )))) # (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// ((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) # 
// ((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) # ( 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & ( 
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout )))) # 
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .lut_mask = 64'h10DC10DCFE32FE32;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y22_N53
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y22_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout  = ( 
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  
// & ( (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # 
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) ) ) ) # ( 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  
// & ( (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & 
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) ) ) ) # ( 
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  
// & ( (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) # (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) ) 
// ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  & 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) ) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datae(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 .lut_mask = 64'h5050AFAF00CCFFCC;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y22_N26
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";
// synopsys translate_on

// Location: FF_X13_Y22_N59
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][78] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~9_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][78]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y22_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~9 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~9_combout  = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6])) # 
// (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][78]~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][78]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][78]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~9 .lut_mask = 64'h000F000F505F505F;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~9 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y22_N23
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][78] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~9_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][78]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";
// synopsys translate_on

// Location: FF_X13_Y22_N38
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][77] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][77]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y22_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~8 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~8_combout  = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])) # 
// (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][77]~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][77]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][77]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~8 .lut_mask = 64'h003300330C3F0C3F;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y22_N2
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][77] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~8_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][77]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";
// synopsys translate_on

// Location: FF_X13_Y22_N41
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][74] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][74]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y22_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~5 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~5_combout  = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) # 
// (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][74]~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & 
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & 
// ((\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][74]~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][74]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h0C3F0C3F44774477;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y22_N5
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][74] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~5_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][74]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";
// synopsys translate_on

// Location: FF_X13_Y22_N35
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][76] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~7_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][76]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y22_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~7 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~7_combout  = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4])) # 
// (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][76]~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][76]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][76]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h005500550A5F0A5F;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y22_N17
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][76] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~7_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][76]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";
// synopsys translate_on

// Location: FF_X13_Y22_N32
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][75] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][75]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y22_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~6 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~6_combout  = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) # 
// (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][75]~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][75]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][75]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h005500550A5F0A5F;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y22_N29
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][75] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~6_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][75]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";
// synopsys translate_on

// Location: FF_X10_Y22_N35
dffeas \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_busy (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y22_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~0_combout  = ( !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][75]~q  & ( !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_busy~q  & ( 
// (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][78]~q  & (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][77]~q  & (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][74]~q  & 
// !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][76]~q ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][78]~q ),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][77]~q ),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datae(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][75]~q ),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h0800000000000000;
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y22_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg~0_combout  = ( !\u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0_combout  & ( (\u0|mm_interconnect_0|link_disable_s1_agent|m0_read~0_combout  & 
// !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_agent|m0_read~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg~0 .lut_mask = 64'h5050505000000000;
defparam \u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y22_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg~1_combout  = (\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~4_combout  & \u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg~0_combout )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~4_combout ),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg~0_combout ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg~1 .lut_mask = 64'h000F000F000F000F;
defparam \u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y22_N20
dffeas \u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X17_Y22_N38
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][129] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][129]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y22_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~0_combout  = ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][129]~q  & ( \u0|mm_interconnect_0|link_disable_s1_agent|local_write~0_combout  & ( 
// (((\u0|mm_interconnect_0|link_disable_s1_agent|m0_read~0_combout  & \u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0_combout )) # 
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout )) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # ( 
// !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][129]~q  & ( \u0|mm_interconnect_0|link_disable_s1_agent|local_write~0_combout  & ( (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & 
// (((\u0|mm_interconnect_0|link_disable_s1_agent|m0_read~0_combout  & \u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0_combout )) # 
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ))) ) ) ) # ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][129]~q  & ( 
// !\u0|mm_interconnect_0|link_disable_s1_agent|local_write~0_combout  & ( ((\u0|mm_interconnect_0|link_disable_s1_agent|m0_read~0_combout  & \u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0_combout )) # 
// (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][129]~q  & ( !\u0|mm_interconnect_0|link_disable_s1_agent|local_write~0_combout  & ( 
// (\u0|mm_interconnect_0|link_disable_s1_agent|m0_read~0_combout  & (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_agent|m0_read~0_combout ),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0_combout ),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datae(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][129]~q ),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_agent|local_write~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~0 .lut_mask = 64'h0404373704CC37FF;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y22_N5
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][129] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][129]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y22_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|read~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|read~0_combout  = ( \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][129]~q  & 
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [0]) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg [0]) # 
// ((\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][129]~q  & \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [0])) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [0]),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|read~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|read~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|read~0 .lut_mask = 64'hF1F1F1F111111111;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|read~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y22_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|read~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|read~1_combout  = ( !\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|read~0_combout  & ( \u0|mm_interconnect_0|rsp_demux_009|WideOr0~0_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|rsp_demux_009|WideOr0~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|read~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|read~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|read~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|read~1 .lut_mask = 64'h0F0F0F0F00000000;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|read~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y22_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[1]~1_combout  = ( !\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|read~1_combout  & ( ((\u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg [0] & 
// \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [1]) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [0]),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|read~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[1]~1 .lut_mask = 64'h05FF05FF00000000;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[1]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y22_N32
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y22_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[0]~0_combout  = ( \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|read~1_combout  & ( ((\u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg [0] & 
// \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|read~1_combout  & ( 
// ((\u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [1])) # (\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [0]) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|read~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h50FF50FF0F5F0F5F;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y22_N35
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y22_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|comb~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent|comb~0_combout  = ( \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [0] ) ) # ( 
// !\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [0] & ((\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][129]~q ) # 
// (\u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg [0]))) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg [0]),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_agent|comb~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|comb~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|comb~0 .lut_mask = 64'h0555055555555555;
defparam \u0|mm_interconnect_0|link_disable_s1_agent|comb~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X10_Y22_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~2 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~2_combout  = ( \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_busy~q  & ( 
// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [2] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X10_Y22_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout  = ( \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( 
// (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout  & !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~2_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][74]~q  & 
// (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout  & !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~2_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout ),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h0A000A000F000F00;
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y22_N44
dffeas \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y22_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~0_combout  = ( !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][77]~q  & ( (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][74]~q  & 
// (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][76]~q  & !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][75]~q )) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][77]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~0 .lut_mask = 64'hA000A00000000000;
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X10_Y22_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~2 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~2_combout  = ( \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [5] ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [5] $ (((!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & 
// !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [4]))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h3FC03FC0FF00FF00;
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X10_Y22_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~1_combout  = ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][77]~q  & ( (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][75]~q  & 
// (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][76]~q  & !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][74]~q )) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][77]~q  & ( 
// ((\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][74]~q ) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][76]~q )) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][75]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][77]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h5FFF5FFFA000A000;
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X10_Y22_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout  = ( \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~1_combout  & ( 
// (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout  & (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~2_combout )) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~1_combout  & ( (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout  & 
// ((!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ) # (!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~2_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~2_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h5550555005000500;
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y22_N41
dffeas \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y22_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~1_combout  = ( !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// (!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & 
// !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [5])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~1 .lut_mask = 64'hC000C00000000000;
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X10_Y22_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout  = ( \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( 
// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~1_combout  & ( (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout  & 
// (!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][78]~q  $ (!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~0_combout )))) ) ) 
// ) # ( !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~1_combout  & ( 
// (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][78]~q  $ (!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~0_combout )) # 
// (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( 
// !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~1_combout  & ( (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][78]~q  $ 
// (!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~0_combout )) # (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( 
// !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~1_combout  & ( 
// (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout  & (!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][78]~q 
//  $ (!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~0_combout )))) ) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][78]~q ),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout ),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~0_combout ),
        .datae(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h1020132313231020;
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y22_N56
dffeas \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y22_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout  = ( \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~0_combout  & ( \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~1_combout  & ( 
// (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// ((!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][78]~q ))) # (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [6])))) ) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~0_combout  & ( 
// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~1_combout  & ( (!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & 
// (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout )) ) ) ) # ( 
// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~0_combout  & ( !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~1_combout  & ( (!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  
// & (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][78]~q  & \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][78]~q ),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout ),
        .datae(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~0_combout ),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h000000C0002200E2;
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y22_N32
dffeas \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y22_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  = ( \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_busy~q  & ( 
// (!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~1_combout ) # ((\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [7]) # 
// (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [2])) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h00000000BFBFBFBF;
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X10_Y22_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout  = ( \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout  & ( (!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][74]~q  $ ((\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][75]~q )))) # (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (((\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout  & ( (!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][74]~q  $ ((\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][75]~q )))) # (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (((!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datae(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h00000000B78484B7;
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y22_N8
dffeas \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y22_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~0_combout  = ( \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( 
// !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [4] ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( 
// !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [4] $ (!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [3]) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h66666666AAAAAAAA;
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X10_Y22_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout  = ( \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout  & ( 
// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~0_combout  ) ) ) # ( 
// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout  & ( !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( 
// !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][76]~q  $ (((\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][75]~q ) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][74]~q ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~0_combout ),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datae(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout ),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h0000A05F0000CCCC;
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y22_N50
dffeas \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y22_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~1_combout  = ( !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & ( 
// (!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & 
// !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [6])) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'h8800880000000000;
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y22_N29
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][66]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y22_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~3 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~3_combout  = (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg 
// [66])) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][66]~q )))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][66]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h0C3F0C3F0C3F0C3F;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y22_N44
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~3_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][66]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y22_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout  = ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][66]~q  & ( (!\u0|mm_interconnect_0|link_disable_s1_agent|comb~0_combout ) # 
// ((!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~0_combout  & ((!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~1_combout ) # 
// (!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~2_combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_agent|comb~0_combout ),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][66]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h00000000EEECEEEC;
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y22_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[0]~1_combout  = ( \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout  & ( (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [0]) # 
// (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|write~0_combout ) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout  & ( ((\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [0] & 
// ((!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0_combout ) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1])))) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|write~0_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|write~0_combout ),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0_combout ),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h33F733F733FF33FF;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y22_N23
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y22_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout  = ( \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout  & ( !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [0] ) ) # ( 
// !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout  & ( (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [0]) # (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hAFAFAFAFAAAAAAAA;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y22_N25
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][69] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][69]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][69] .power_up = "low";
// synopsys translate_on

// Location: FF_X11_Y22_N37
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][68] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~2_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][68]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][68] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][68] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y22_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~2 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~2_combout  = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] & ( (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used 
// [1]) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][68]~q ) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] & ( 
// (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][68]~q  & \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][68]~q ),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~2 .lut_mask = 64'h03030303F3F3F3F3;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y22_N10
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][68] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~2_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][68]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][68] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][68] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y22_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_009|src0_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_009|src0_valid~0_combout  = ( !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][66]~q  & ( (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][69]~q  & 
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][68]~q ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][69]~q ),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][68]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][66]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_demux_009|src0_valid~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_009|src0_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_009|src0_valid~0 .lut_mask = 64'h00F000F000000000;
defparam \u0|mm_interconnect_0|rsp_demux_009|src0_valid~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y22_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_009|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_009|WideOr0~0_combout  = ( \u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ( (!\u0|mm_interconnect_0|rsp_demux_009|src0_valid~0_combout ) # (\u0|hps_0|fpga_interfaces|h2f_BREADY [0]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_RREADY 
// [0] & ( (\u0|mm_interconnect_0|rsp_demux_009|src0_valid~0_combout  & \u0|hps_0|fpga_interfaces|h2f_BREADY [0]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|rsp_demux_009|src0_valid~0_combout ),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_BREADY [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_demux_009|WideOr0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_009|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_009|WideOr0~0 .lut_mask = 64'h03030303CFCFCFCF;
defparam \u0|mm_interconnect_0|rsp_demux_009|WideOr0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y22_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0_combout  = ( \u0|mm_interconnect_0|link_disable_s1_agent|comb~0_combout  & ( \u0|mm_interconnect_0|rsp_demux_009|WideOr0~0_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|rsp_demux_009|WideOr0~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_agent|comb~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y22_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[1]~0_combout  = ( \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout  & ( (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|write~0_combout  & 
// ((\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]))) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|write~0_combout  & (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [0])) ) ) # ( 
// !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout  & ( (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|write~0_combout  & (!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0_combout  & 
// ((\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1])))) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|write~0_combout  & ((!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0_combout  & 
// (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [0])) # (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0_combout  & ((\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]))))) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|write~0_combout ),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0_combout ),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [0]),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[1]~0 .lut_mask = 64'h049D049D05AF05AF;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[1]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y22_N56
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y22_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|m0_write (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent|m0_write~combout  = ( \u0|mm_interconnect_0|link_disable_s1_agent|local_write~0_combout  & ( (!\u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0_combout  & 
// !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_agent|local_write~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_agent|m0_write~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|m0_write .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|m0_write .lut_mask = 64'h00000000A0A0A0A0;
defparam \u0|mm_interconnect_0|link_disable_s1_agent|m0_write .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y22_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~0_combout  = ( \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [0] & ( (\u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override~q  & 
// (((\u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg~0_combout  & \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [1])) # (\u0|mm_interconnect_0|link_disable_s1_agent|m0_write~combout ))) ) ) # ( 
// !\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [0] & ( (\u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override~q  & ((!\u0|mm_interconnect_0|link_disable_s1_agent|m0_write~combout  & 
// (\u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg~0_combout )) # (\u0|mm_interconnect_0|link_disable_s1_agent|m0_write~combout  & ((\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [1]))))) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_agent|m0_write~combout ),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override~q ),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg~0_combout ),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~0 .lut_mask = 64'h0213021311131113;
defparam \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y22_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~1_combout  = ( \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~0_combout  & ( !\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [0] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~0_combout ),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~1 .lut_mask = 64'h0000FFFF00000000;
defparam \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y22_N20
dffeas \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y22_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~1_combout  = ( \u0|mm_interconnect_0|link_disable_s1_agent|local_write~0_combout  & ( (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & 
// (((!\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [0] & \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~0_combout )) # (\u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0_combout ))) ) ) # ( 
// !\u0|mm_interconnect_0|link_disable_s1_agent|local_write~0_combout  & ( (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & (((\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [0] & 
// \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~0_combout )) # (\u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [0]),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0_combout ),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_agent|local_write~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~1 .lut_mask = 64'h0C4C0C4C0C8C0C8C;
defparam \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y22_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  = ( 
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & ( \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~1_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h0000000000FF00FF;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y22_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout  = ( 
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  
// & ( (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # 
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) ) ) ) # ( 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  
// & ( (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & 
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) ) ) ) # ( 
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  
// & ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  ) ) ) # ( 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q 
//  & ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .lut_mask = 64'h0F0FF0F00C0CFCFC;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y22_N50
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y22_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout  = ( 
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  
// & ( (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # 
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) ) ) ) # ( 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  
// & ( (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & 
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) ) ) ) # ( 
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  
// & ( ((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) # 
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) # (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg 
// [2]) ) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg 
// [2] & (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & 
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datae(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .lut_mask = 64'h00A0FF5F00CCFFCC;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y22_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout  = ( 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout  & ( 
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout  & 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0 .lut_mask = 64'hF000F00000000000;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y22_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout  = ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( 
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// (((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout )) # (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q 
// ))) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .lut_mask = 64'h010F010F00000000;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y22_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout  = ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .lut_mask = 64'hF0F0F0F000000000;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y22_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout  = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & ( 
// \u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & ( (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ) # 
// ((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ) # 
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) ) ) ) # ( 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & ( \u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & ( 
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) ) ) 
// # ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & ( !\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & ( 
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) ) ) 
// # ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & ( !\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & ( 
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datae(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .lut_mask = 64'h005500550055F0FD;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y22_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout  = (!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & 
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout  & 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout )))

        .dataa(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16 .lut_mask = 64'h0200020002000200;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y22_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  = (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ))

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .lut_mask = 64'h0500050005000500;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y22_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17_combout  = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout  & ( 
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout  & ( 
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  ) ) # ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout  & ( 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout  & ( 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  & ( (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout  & 
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout  & 
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout  & 
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),
        .datae(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout ),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17 .lut_mask = 64'h0040FFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y22_N56
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y22_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout  = ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( 
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & ((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ) # 
// ((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h0E0C0E0C00000000;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y23_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|src_payload[0] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|src_payload [0] = ( \u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] ) # ( !\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & ( (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_WLAST 
// [0]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
        .datac(gnd),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_WLAST [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_011|src_payload [0]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|src_payload[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|src_payload[0] .lut_mask = 64'h00330033FFFFFFFF;
defparam \u0|mm_interconnect_0|cmd_mux_011|src_payload[0] .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y23_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|src_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|src_valid~0_combout  = ( \u0|mm_interconnect_0|cmd_demux|src11_valid~0_combout  & ( \u0|mm_interconnect_0|router|Equal7~1_combout  & ( 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout  & (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] & (\u0|mm_interconnect_0|router|Equal14~0_combout  & 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
        .datac(!\u0|mm_interconnect_0|router|Equal14~0_combout ),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout ),
        .datae(!\u0|mm_interconnect_0|cmd_demux|src11_valid~0_combout ),
        .dataf(!\u0|mm_interconnect_0|router|Equal7~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_011|src_valid~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|src_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|src_valid~0 .lut_mask = 64'h0000000000000001;
defparam \u0|mm_interconnect_0|cmd_mux_011|src_valid~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y23_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|packet_in_progress~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|packet_in_progress~0_combout  = !\u0|mm_interconnect_0|cmd_mux_011|update_grant~0_combout 

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_011|update_grant~0_combout ),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_011|packet_in_progress~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|packet_in_progress~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|packet_in_progress~0 .lut_mask = 64'hCCCCCCCCCCCCCCCC;
defparam \u0|mm_interconnect_0|cmd_mux_011|packet_in_progress~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y23_N2
dffeas \u0|mm_interconnect_0|cmd_mux_011|packet_in_progress (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_011|packet_in_progress~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_011|packet_in_progress~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|packet_in_progress .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_011|packet_in_progress .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y20_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~0_combout  = ( !\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [1] & ( \u0|mm_interconnect_0|write_en_tx_s1_translator|waitrequest_reset_override~q  ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_translator|waitrequest_reset_override~q ),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~0 .lut_mask = 64'h3333333300000000;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y20_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & ( 
// \u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0_combout  & ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] ) ) ) # ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & ( \u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0_combout  ) ) # ( 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0_combout  & ( (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & 
// (\u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~0_combout  & (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] $ (!\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter 
// [0])))) ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0_combout  ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [0]),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~0_combout ),
        .datae(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hFFFF0028FFFFAAAA;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y20_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout  & ( 
// !\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout  & ( (!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & 
// !\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .lut_mask = 64'h88888888AAAAAAAA;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y23_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y23_N56
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y23_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & ( 
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) # 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'h000000003F003F00;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y27_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal17~0 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal17~0_combout  = (\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & (\u0|mm_interconnect_0|router_001|Equal1~4_combout  & \u0|hps_0|fpga_interfaces|h2f_ARADDR [17]))

        .dataa(gnd),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),
        .datac(!\u0|mm_interconnect_0|router_001|Equal1~4_combout ),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router_001|Equal17~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal17~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal17~0 .lut_mask = 64'h0003000300030003;
defparam \u0|mm_interconnect_0|router_001|Equal17~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y27_N2
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[11] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|router_001|Equal17~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [11]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[11] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[11] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y27_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|src11_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|src11_valid~0_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [11]) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [11]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux_001|src11_valid~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|src11_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|src11_valid~0 .lut_mask = 64'h00000000F0FFF0FF;
defparam \u0|mm_interconnect_0|cmd_demux_001|src11_valid~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y23_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|src_valid~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|src_valid~1_combout  = ( \u0|mm_interconnect_0|router_001|Equal1~4_combout  & ( \u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] 
// & \u0|mm_interconnect_0|cmd_demux_001|src11_valid~0_combout )) ) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),
        .datac(!\u0|mm_interconnect_0|cmd_demux_001|src11_valid~0_combout ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|router_001|Equal1~4_combout ),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_011|src_valid~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|src_valid~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|src_valid~1 .lut_mask = 64'h0000000000000101;
defparam \u0|mm_interconnect_0|cmd_mux_011|src_valid~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y23_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout  = ( \u0|mm_interconnect_0|cmd_mux_011|src_valid~1_combout  & ( 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & ((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ) # 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ))) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_011|src_valid~1_combout  & ( 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & (\u0|mm_interconnect_0|cmd_mux_011|src_valid~0_combout  & 
// ((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )))) ) 
// )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_011|src_valid~0_combout ),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_011|src_valid~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h0105010511551155;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y20_N35
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y20_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y20_N11
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on

// Location: FF_X27_Y27_N14
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount[2] .power_up = "low";
// synopsys translate_on

// Location: FF_X15_Y33_N8
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~14_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][110]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][110] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y33_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_017|src_payload~5 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_017|src_payload~5_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [5] & ( \u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_017|src_payload~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~5 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y33_N34
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_017|src_payload~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y33_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~14 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~14_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][110]~q  & ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110] ) 
// ) # ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][110]~q  & ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110] & ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used 
// [1] ) ) ) # ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][110]~q  & ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110] & ( 
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][110]~q ),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~14 .lut_mask = 64'h00000F0FF0F0FFFF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~14 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y33_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][110]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][110]~feeder_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~14_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~14_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][110]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][110]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][110]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][110]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y33_N37
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][110]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][110]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][110] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y31_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_016|src_payload~5 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_016|src_payload~5_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [5] & ( \u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_016|src_payload~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~5 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y31_N50
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_016|src_payload~5_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .power_up = "low";
// synopsys translate_on

// Location: FF_X19_Y31_N44
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~14_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][110]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][110] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y31_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~14 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~14_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][110]~q  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][110]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~14 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~14 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y35_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0_combout  & 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [0] )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hFFFFFFFF50505050;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y31_N14
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~14_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][110]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][110] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y29_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y29_N2
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y29_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~2 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~2_combout  = ( \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~0_combout  & ( !\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0] $ 
// (!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [1]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~2 .lut_mask = 64'h0000000033CC33CC;
defparam \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y29_N38
dffeas \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X25_Y29_N14
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";
// synopsys translate_on

// Location: FF_X21_Y29_N35
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y29_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|m0_read~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent|m0_read~0_combout  = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & ( 
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]) # (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
        .datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_agent|m0_read~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|m0_read~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent|m0_read~0 .lut_mask = 64'h000000000FFF0FFF;
defparam \u0|mm_interconnect_0|link_start_s1_agent|m0_read~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y29_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg~0_combout  = (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & (!\u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout  & 
// \u0|mm_interconnect_0|link_start_s1_agent|m0_read~0_combout ))

        .dataa(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),
        .datab(!\u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout ),
        .datac(!\u0|mm_interconnect_0|link_start_s1_agent|m0_read~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg~0 .lut_mask = 64'h0808080808080808;
defparam \u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y29_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|m0_write (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent|m0_write~combout  = ( !\u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout  & ( (\u0|mm_interconnect_0|link_start_s1_agent|local_write~0_combout  & 
// !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_start_s1_agent|local_write~0_combout ),
        .datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_agent|m0_write~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|m0_write .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent|m0_write .lut_mask = 64'h0F000F0000000000;
defparam \u0|mm_interconnect_0|link_start_s1_agent|m0_write .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y30_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~feeder (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y30_N11
dffeas \u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y29_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~0_combout  = ( \u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~q  & ( (!\u0|mm_interconnect_0|link_start_s1_agent|m0_write~combout  & 
// (\u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg~0_combout  & ((!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0]) # (\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [1])))) # 
// (\u0|mm_interconnect_0|link_start_s1_agent|m0_write~combout  & (((\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0])) # (\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [1]))) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [1]),
        .datab(!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0]),
        .datac(!\u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg~0_combout ),
        .datad(!\u0|mm_interconnect_0|link_start_s1_agent|m0_write~combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~0 .lut_mask = 64'h000000000D770D77;
defparam \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y29_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~1_combout  = ( \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~0_combout  & ( !\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~1 .lut_mask = 64'h00000000FF00FF00;
defparam \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y29_N14
dffeas \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y29_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0_combout  = ( \u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~q  & ( !\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [1] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0 .lut_mask = 64'h00000000FF00FF00;
defparam \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y29_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~1_combout  = ( \u0|mm_interconnect_0|link_start_s1_agent|local_write~0_combout  & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & 
// (((!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0] & \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0_combout )) # (\u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout ))) ) ) # ( 
// !\u0|mm_interconnect_0|link_start_s1_agent|local_write~0_combout  & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & (((\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0] & 
// \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0_combout )) # (\u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),
        .datab(!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0]),
        .datac(!\u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout ),
        .datad(!\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_agent|local_write~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~1 .lut_mask = 64'h0A2A0A2A0A8A0A8A;
defparam \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y36_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y36_N16
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y31_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal19~0 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal19~0_combout  = (\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [19])

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router_001|Equal19~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal19~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal19~0 .lut_mask = 64'h0055005500550055;
defparam \u0|mm_interconnect_0|router_001|Equal19~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y31_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal19~1 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal19~1_combout  = ( \u0|mm_interconnect_0|router_001|Equal19~0_combout  & ( \u0|mm_interconnect_0|router_001|Equal1~0_combout  & ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & 
// (\u0|mm_interconnect_0|router_001|Equal1~2_combout  & (\u0|mm_interconnect_0|router_001|Equal1~1_combout  & !\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]))) ) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),
        .datab(!\u0|mm_interconnect_0|router_001|Equal1~2_combout ),
        .datac(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),
        .datae(!\u0|mm_interconnect_0|router_001|Equal19~0_combout ),
        .dataf(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router_001|Equal19~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal19~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal19~1 .lut_mask = 64'h0000000000000100;
defparam \u0|mm_interconnect_0|router_001|Equal19~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y31_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[13]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[13]~feeder_combout  = ( \u0|mm_interconnect_0|router_001|Equal19~1_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|router_001|Equal19~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[13]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[13]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[13]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[13]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y31_N37
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[13] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[13]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [13]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[13] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[13] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y38_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_013|last_cycle~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout  = ( \u0|mm_interconnect_0|router_001|Equal19~1_combout  & ( (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [13]))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [13]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|router_001|Equal19~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_013|last_cycle~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_013|last_cycle~0 .lut_mask = 64'h000000000F030F03;
defparam \u0|mm_interconnect_0|cmd_mux_013|last_cycle~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y21_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y21_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout  & ( 
// !\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout  & ( (!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & 
// !\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .lut_mask = 64'hF000F000FF00FF00;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y22_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y22_N5
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y23_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|src_valid~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [15] & ( \u0|mm_interconnect_0|router_001|Equal21~0_combout  & ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & 
// \u0|hps_0|fpga_interfaces|h2f_ARVALID [0]) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [15] & ( \u0|mm_interconnect_0|router_001|Equal21~0_combout  & ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & 
// (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q )) ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [15]),
        .dataf(!\u0|mm_interconnect_0|router_001|Equal21~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_015|src_valid~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|src_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_015|src_valid~0 .lut_mask = 64'h0000000010101111;
defparam \u0|mm_interconnect_0|cmd_mux_015|src_valid~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y23_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout  = ( \u0|mm_interconnect_0|cmd_demux|src15_valid~1_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) # ((!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & !\u0|mm_interconnect_0|cmd_mux_015|src_valid~0_combout )) ) ) # ( 
// !\u0|mm_interconnect_0|cmd_demux|src15_valid~1_combout  & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) # (!\u0|mm_interconnect_0|cmd_mux_015|src_valid~0_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|cmd_mux_015|src_valid~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_demux|src15_valid~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .lut_mask = 64'hFFAAFFAAEEAAEEAA;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y21_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18_combout  = ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ) # 
// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) # (((!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & !\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0])) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ))) ) ) # ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q 
//  & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ) # 
// (((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
        .datag(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18 .extended_lut = "on";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18 .lut_mask = 64'hFFEAAAAAFFFFAAAF;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y21_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1_combout  = ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1 .lut_mask = 64'hFFFFFFFF00000000;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y21_N35
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y21_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout  = ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  
// & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .lut_mask = 64'hF0F0F0F000000000;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y21_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout  & ( 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & ((\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0])))) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & \u0|mm_interconnect_0|cmd_mux_015|saved_grant [0])) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ))) ) ) ) # ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout  & ( 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & 
// (((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & \u0|mm_interconnect_0|cmd_mux_015|saved_grant [0])) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & ((\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0])))) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & \u0|mm_interconnect_0|cmd_mux_015|saved_grant [0])) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
        .datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .lut_mask = 64'h0537050705370505;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y21_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout  = ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout  & ( 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & (!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16 .lut_mask = 64'h0050005000000000;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y21_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q 
//  & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .lut_mask = 64'h0010001050505050;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y21_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  = (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~1_combout  & 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~1_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h000F000F000F000F;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y21_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout  = ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .lut_mask = 64'h33CF33CF30CC30CC;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y21_N44
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on

// Location: FF_X17_Y21_N59
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y21_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout  = ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) # 
// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) ) ) # ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .lut_mask = 64'h0A0FF5FF0A00F5F0;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y21_N2
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y21_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout  = ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) # 
// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])))) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) ) ) ) # ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) # 
// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .lut_mask = 64'h3111DFFF2000CEEE;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y21_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout  = ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout  & 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0 .lut_mask = 64'hF000F00000000000;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y21_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  = ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4])) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h00000000A000A000;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y21_N8
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y21_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout  = ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout )) ) ) ) # ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) 
// # (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout )))) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 .lut_mask = 64'h11B1FF5F00A0EE4E;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y21_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout 
//  & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .lut_mask = 64'h000000000F000F00;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y21_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17_combout  = ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout  & ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout  & ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  ) ) # ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout  & ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout  ) ) 
// ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout  & ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  & ( 
// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout  & 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout  & \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ))) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ),
        .datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17 .lut_mask = 64'h555D5555FFFFFFFF;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y21_N26
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y21_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  = ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'h0077000000770000;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y23_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout  = ( \u0|mm_interconnect_0|cmd_mux_015|src_valid~0_combout  & ( 
// \u0|mm_interconnect_0|cmd_demux|src15_valid~1_combout  & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & 
// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_015|src_valid~0_combout  & ( 
// \u0|mm_interconnect_0|cmd_demux|src15_valid~1_combout  & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & 
// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )))) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_015|src_valid~0_combout  & ( 
// !\u0|mm_interconnect_0|cmd_demux|src15_valid~1_combout  & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & 
// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
        .datae(!\u0|mm_interconnect_0|cmd_mux_015|src_valid~0_combout ),
        .dataf(!\u0|mm_interconnect_0|cmd_demux|src15_valid~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h0000151500151515;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y21_N17
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y23_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_payload[0] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|src_payload [0] = ( \u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] ) # ( !\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_WLAST 
// [0]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_WLAST [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_015|src_payload [0]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|src_payload[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_015|src_payload[0] .lut_mask = 64'h03030303FFFFFFFF;
defparam \u0|mm_interconnect_0|cmd_mux_015|src_payload[0] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y23_N44
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_015|src_payload [0]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y21_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_data[87] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|src_data [87] = ( \u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] ) ) # ( !\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] & ( 
// (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & ( !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] & ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] 
// & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & ( !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] & ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]) ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
        .datae(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_015|src_data [87]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[87] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[87] .lut_mask = 64'h005500550055FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[87] .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y21_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_data[88] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|src_data [88] = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & ( ((\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & \u0|mm_interconnect_0|cmd_mux_015|saved_grant [0])) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & ( (\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & \u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_015|src_data [88]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[88] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[88] .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[88] .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y21_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout  = ( !\u0|mm_interconnect_0|cmd_mux_015|src_data [88] & ( !\u0|mm_interconnect_0|cmd_mux_015|src_data [87] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|cmd_mux_015|src_data [87]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_015|src_data [88]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .lut_mask = 64'hFF00FF0000000000;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y21_N17
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y21_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_data[33] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|src_data [33] = ((\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_WSTRB [1])) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1])

        .dataa(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_015|src_data [33]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[33] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[33] .lut_mask = 64'h3737373737373737;
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[33] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y21_N44
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_015|src_data [33]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y31_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal12~0 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal12~0_combout  = ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & ( (\u0|mm_interconnect_0|router_001|Equal1~0_combout  & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & 
// (\u0|mm_interconnect_0|router_001|Equal1~1_combout  & \u0|mm_interconnect_0|router_001|Equal2~0_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),
        .datac(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),
        .datad(!\u0|mm_interconnect_0|router_001|Equal2~0_combout ),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router_001|Equal12~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal12~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal12~0 .lut_mask = 64'h0000000000010000;
defparam \u0|mm_interconnect_0|router_001|Equal12~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y31_N1
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[21] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|router_001|Equal12~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [21]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[21] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[21] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y31_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_021|last_cycle~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_021|last_cycle~0_combout  = (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & (\u0|mm_interconnect_0|router_001|Equal12~0_combout  & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [21]))))

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
        .datac(!\u0|mm_interconnect_0|router_001|Equal12~0_combout ),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [21]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_021|last_cycle~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_021|last_cycle~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_021|last_cycle~0 .lut_mask = 64'h0203020302030203;
defparam \u0|mm_interconnect_0|cmd_mux_021|last_cycle~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y35_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y35_N41
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y33_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout  = ( \u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] & ( 
// \u0|mm_interconnect_0|cmd_mux_021|last_cycle~0_combout  & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ) ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_021|last_cycle~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h0000000000003030;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y33_N2
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";
// synopsys translate_on

// Location: FF_X27_Y33_N5
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y31_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout  = ( !\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .lut_mask = 64'hFFFFFFFF00000000;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y31_N35
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";
// synopsys translate_on

// Location: FF_X27_Y33_N14
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y33_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0_combout  & ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q  & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) # 
// ((\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q  & \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1])) ) ) ) # ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0_combout  & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q  & ( 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) # 
// ((\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q  & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout ) # 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1])))) ) ) ) # ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0_combout  & ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q  & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q  & \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1])) ) ) ) # ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0_combout  & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q  & ( 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q  
// & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout ) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1])))) ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout ),
        .datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0_combout ),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .lut_mask = 64'h11010101BBABABAB;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y32_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y32_N35
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y32_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout  = ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ( (\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] & !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]) ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( (\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] & !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]) ) ) ) # ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] ) ) ) # ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  
// & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .lut_mask = 64'h0F0FF0F044444444;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y32_N8
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y32_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout  = ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ( (\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ) ) ) ) # ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ( (\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ) ) ) ) # ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]) ) ) ) # ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  
// & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]) ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),
        .datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .lut_mask = 64'h4444BBBB000F000F;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y32_N38
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y32_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] $ 
// (((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) ) # ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg 
// [4] ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .lut_mask = 64'hF0F0F0F078787878;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y32_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout  = ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout  & \u0|mm_interconnect_0|cmd_mux_021|saved_grant [1])) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  & ( 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout  & \u0|mm_interconnect_0|cmd_mux_021|saved_grant [1])) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .lut_mask = 64'hAAAFAAAF00050005;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y32_N59
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y32_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  = ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] & 
// ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg 
// [2] & !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .lut_mask = 64'h0C000C0000000000;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y32_N55
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y32_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout  & ( 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  $ 
// (((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))))) # 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1])))) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout  & 
// ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  $ 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .lut_mask = 64'h22882288278D278D;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y33_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  = (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .lut_mask = 64'h0044004400440044;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y33_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  = ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  ) ) ) # ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ) 
// ) ) # ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0_combout  & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout  & 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q )) ) ) ) # ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) # ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0_combout  & 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout  & \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0_combout ),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout ),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'hAAEA00C0AAFF00FF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y33_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout  & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  
// ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h000000000000F0F0;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y34_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4]~feeder_combout  = ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y34_N32
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y33_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~1_combout  = ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0_combout ) # 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~1 .lut_mask = 64'h5F5F5F5F00000000;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y33_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  = ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~1_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h0000000000FF00FF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y34_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout  = ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) # 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) ) ) # ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) # 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) # 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .lut_mask = 64'h55AF55AF50AA50AA;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y34_N17
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y34_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout  = ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) # 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) ) ) ) # ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) ) ) ) # ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) # 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) ) ) ) # ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .lut_mask = 64'h4444BBBB5050FAFA;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y34_N8
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y34_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout  = ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] 
// ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] ) ) ) # ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] $ 
// (((\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]) # 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) ) ) ) # ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .lut_mask = 64'h3333C3333333AAAA;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y34_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5]~feeder_combout  = ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y34_N56
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y34_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  = ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & 
// ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h5000500000000000;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y34_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout  = ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) # 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) # 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  
// & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (((\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) # 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) # 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .lut_mask = 64'h333A333AC3CAC3CA;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y34_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout  = ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout  & ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0 .lut_mask = 64'hF0F0F0F000000000;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y34_N2
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y34_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout  = ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) # 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) # 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg 
// [2])) ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout 
// )))) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) ) # ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg 
// [5])) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ) ) ) # ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout )) ) 
// ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .lut_mask = 64'h00C0FF3F22E2EE2E;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y33_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout  & ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout  & ( 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ) ) ) ) # ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout  & ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout  & ( 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ) ) ) ) # ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout  & ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout  & ( 
// ((\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout  & 
// ((\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ) # 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout )))) # 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ) ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout  
// & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout  & ( 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),
        .datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout ),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .lut_mask = 64'h7777577777777777;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y33_N38
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y33_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout  = ( \u0|mm_interconnect_0|cmd_mux_021|last_cycle~0_combout  & ( 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & 
// \u0|mm_interconnect_0|cmd_mux_021|saved_grant [1])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_021|last_cycle~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .lut_mask = 64'h0000000000030003;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y33_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout  & ( 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & ((\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ) # 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ))) ) ) # ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout  & ( 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// (((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q )) 
// # (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .lut_mask = 64'h0545054505550555;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y33_N32
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y33_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q  & ( 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q 
//  & !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q  & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h0A0A0A0A08000800;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y33_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout  = (!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]) # ((!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & 
// !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]))

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .lut_mask = 64'hFFA0FFA0FFA0FFA0;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y33_N35
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .power_up = "low";
// synopsys translate_on

// Location: FF_X27_Y33_N59
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X27_Y33_N43
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X27_Y33_N32
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y33_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~2_combout  = ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & ( 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~2 .lut_mask = 64'hC000C00000000000;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y33_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~3 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~3_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0_combout  & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] ) ) # ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0_combout  & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q  & \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~2_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~2_combout ),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0_combout ),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~3 .lut_mask = 64'h2222FFFF00000000;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y33_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~3_combout  & ( 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) # 
// ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~3_combout  & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .lut_mask = 64'h5050505055005500;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y33_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  = ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  & ( 
// ((!\u0|mm_interconnect_0|cmd_mux_021|last_cycle~0_combout ) # ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) # (!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]))) # 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_021|last_cycle~0_combout ),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
        .datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .lut_mask = 64'hFFFD0000FFFD0000;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y22_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|rp_valid (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent|rp_valid~combout  = ( !\u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg [0] & ( (!\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [0] & 
// ((!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [0]) # (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][129]~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [0]),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_agent|rp_valid~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|rp_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|rp_valid .lut_mask = 64'hAAA0AAA000000000;
defparam \u0|mm_interconnect_0|link_disable_s1_agent|rp_valid .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y24_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_009|src1_valid (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout  = ( !\u0|mm_interconnect_0|link_disable_s1_agent|rp_valid~combout  & ( !\u0|mm_interconnect_0|rsp_demux_009|src0_valid~0_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|link_disable_s1_agent|rp_valid~combout ),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_009|src0_valid~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_009|src1_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_009|src1_valid .lut_mask = 64'hFFFF000000000000;
defparam \u0|mm_interconnect_0|rsp_demux_009|src1_valid .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y23_N35
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~21_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][116]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";
// synopsys translate_on

// Location: HPSINTERFACEHPS2FPGA_X32_Y24_N111
cyclonev_hps_interface_hps2fpga \u0|hps_0|fpga_interfaces|hps2fpga (
        .arready(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|cmd_sink_ready~0_combout ),
        .awready(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~0_combout ),
        .bvalid(\u0|mm_interconnect_0|rsp_mux|WideOr1~combout ),
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .rlast(\u0|mm_interconnect_0|rsp_mux_001|src_payload [0]),
        .rvalid(\u0|mm_interconnect_0|rsp_mux_001|WideOr1~combout ),
        .wready(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ),
        .bid({\u0|mm_interconnect_0|rsp_mux|src_data [116],\u0|mm_interconnect_0|rsp_mux|src_data [115],\u0|mm_interconnect_0|rsp_mux|src_data [114],\u0|mm_interconnect_0|rsp_mux|src_data [113],\u0|mm_interconnect_0|rsp_mux|src_data [112],\u0|mm_interconnect_0|rsp_mux|src_data [111],
\u0|mm_interconnect_0|rsp_mux|src_data [110],\u0|mm_interconnect_0|rsp_mux|src_data [109],\u0|mm_interconnect_0|rsp_mux|src_data [108],\u0|mm_interconnect_0|rsp_mux|src_data [107],\u0|mm_interconnect_0|rsp_mux|src_data [106],\u0|mm_interconnect_0|rsp_mux|src_data [105]}),
        .bresp({gnd,gnd}),
        .port_size_config({gnd,gnd}),
        .rdata({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,\u0|mm_interconnect_0|rsp_mux_001|src_payload~33_combout ,\u0|mm_interconnect_0|rsp_mux_001|src_payload~32_combout ,
\u0|mm_interconnect_0|rsp_mux_001|src_payload~31_combout ,\u0|mm_interconnect_0|rsp_mux_001|src_payload~30_combout ,\u0|mm_interconnect_0|rsp_mux_001|src_payload~29_combout ,\u0|mm_interconnect_0|rsp_mux_001|src_data[8]~85_combout ,
\u0|mm_interconnect_0|rsp_mux_001|src_data[7]~206_combout ,\u0|mm_interconnect_0|rsp_mux_001|src_data[6]~210_combout ,\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~74_combout ,\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~214_combout ,
\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~222_combout ,\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~230_combout ,\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~238_combout ,\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~29_combout }),
        .rid({\u0|mm_interconnect_0|rsp_mux_001|src_data [116],\u0|mm_interconnect_0|rsp_mux_001|src_data [115],\u0|mm_interconnect_0|rsp_mux_001|src_data [114],\u0|mm_interconnect_0|rsp_mux_001|src_data [113],\u0|mm_interconnect_0|rsp_mux_001|src_data [112],
\u0|mm_interconnect_0|rsp_mux_001|src_data [111],\u0|mm_interconnect_0|rsp_mux_001|src_data [110],\u0|mm_interconnect_0|rsp_mux_001|src_data [109],\u0|mm_interconnect_0|rsp_mux_001|src_data [108],\u0|mm_interconnect_0|rsp_mux_001|src_data [107],
\u0|mm_interconnect_0|rsp_mux_001|src_data [106],\u0|mm_interconnect_0|rsp_mux_001|src_data [105]}),
        .rresp({gnd,gnd}),
        .arvalid(\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
        .awvalid(\u0|hps_0|fpga_interfaces|h2f_AWVALID [0]),
        .bready(\u0|hps_0|fpga_interfaces|h2f_BREADY [0]),
        .rready(\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
        .wlast(\u0|hps_0|fpga_interfaces|h2f_WLAST [0]),
        .wvalid(\u0|hps_0|fpga_interfaces|h2f_WVALID [0]),
        .araddr(\u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus ),
        .arburst(\u0|hps_0|fpga_interfaces|hps2fpga_ARBURST_bus ),
        .arcache(),
        .arid(\u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus ),
        .arlen(\u0|hps_0|fpga_interfaces|hps2fpga_ARLEN_bus ),
        .arlock(),
        .arprot(),
        .arsize(\u0|hps_0|fpga_interfaces|hps2fpga_ARSIZE_bus ),
        .awaddr(\u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus ),
        .awburst(\u0|hps_0|fpga_interfaces|hps2fpga_AWBURST_bus ),
        .awcache(),
        .awid(\u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus ),
        .awlen(\u0|hps_0|fpga_interfaces|hps2fpga_AWLEN_bus ),
        .awlock(),
        .awprot(),
        .awsize(\u0|hps_0|fpga_interfaces|hps2fpga_AWSIZE_bus ),
        .wdata(\u0|hps_0|fpga_interfaces|hps2fpga_WDATA_bus ),
        .wid(),
        .wstrb(\u0|hps_0|fpga_interfaces|hps2fpga_WSTRB_bus ));
// synopsys translate_off
defparam \u0|hps_0|fpga_interfaces|hps2fpga .data_width = 32;
// synopsys translate_on

// Location: LABCELL_X18_Y23_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|src_data[116] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|src_data [116] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [11] & ( \u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_ARID [11]) # (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]) ) ) ) # 
// ( !\u0|hps_0|fpga_interfaces|h2f_AWID [11] & ( \u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [11] ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_AWID [11] & ( !\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & ( 
// \u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),
        .datad(gnd),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_AWID [11]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_011|src_data [116]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[116] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[116] .lut_mask = 64'h000033330F0F3F3F;
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[116] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y23_N26
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_011|src_data [116]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y23_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~21 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~21_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][116]~q  & ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg 
// [116] ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][116]~q  & ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] & ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] ) ) ) # ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][116]~q  & ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] & ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][116]~q ),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~21_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~21 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~21 .lut_mask = 64'h00000F0FF0F0FFFF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~21 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y18_N41
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_busy (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";
// synopsys translate_on

// Location: FF_X18_Y20_N47
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on

// Location: FF_X18_Y20_N53
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][74] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][74]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y20_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~5 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~5_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) # 
// (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][74]~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) # (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & 
// ((\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][74]~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][74]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h227722770A5F0A5F;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y18_N23
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][74] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~5_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][74]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y20_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout  = ( 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) # 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg 
// [3]))) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg 
// [2])))) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) # 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg 
// [3]))) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg 
// [2])))) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .lut_mask = 64'h54BA54BA10FE10FE;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y20_N44
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y20_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout  = ( 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) # 
// ((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg 
// [3]) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])))) ) ) ) # ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg 
// [3] & (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) ) ) # ( 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// (((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) # 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg 
// [3])) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) ) ) ) # ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg 
// [3])) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datae(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .lut_mask = 64'h080FF7FF0800F7F0;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y20_N56
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y20_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  = ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( 
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg 
// [2] & \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h00A000A000000000;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y20_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout  = ( 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  $ 
// (((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))))) # 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) 
// ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] $ (((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) # 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .lut_mask = 64'h44BB44BB74B874B8;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y20_N59
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y20_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout  = ( 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  & ( 
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6])) # 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg 
// [6])) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg 
// [2]))))) ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & ( 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  & ( (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6])))) # 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// ((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6])) # 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))))) ) ) ) # ( 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  & ( 
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6])) # 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg 
// [6])) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg 
// [2]))))) ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  & ( 
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6])) # 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg 
// [6])) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg 
// [2]))))) ) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datae(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 .lut_mask = 64'h37323732C7C23732;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y20_N8
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";
// synopsys translate_on

// Location: FF_X18_Y20_N23
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][78] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~9_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][78]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y20_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~9 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~9_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6])) # 
// (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][78]~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][78]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][78]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~9 .lut_mask = 64'h005500550A5F0A5F;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~9 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y18_N35
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][78] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~9_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][78]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";
// synopsys translate_on

// Location: FF_X18_Y20_N50
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][75] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][75]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y20_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~6 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~6_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( 
// (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) # 
// (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][75]~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][75]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][75]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h005500550A5F0A5F;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y18_N32
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][75] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~6_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][75]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";
// synopsys translate_on

// Location: FF_X18_Y20_N20
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][77] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][77]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y20_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~8 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~8_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])) # 
// (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][77]~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][77]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][77]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~8 .lut_mask = 64'h0055005522772277;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~8 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y18_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][77]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][77]~feeder_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~8_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~8_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][77]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][77]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][77]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][77]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y18_N29
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][77] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][77]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][77]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";
// synopsys translate_on

// Location: FF_X18_Y20_N29
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][76] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~7_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][76]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y20_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~7 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~7_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4])) # 
// (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][76]~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][76]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][76]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h000F000F505F505F;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y18_N53
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][76] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~7_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][76]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y18_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~0_combout  = ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][76]~q  & ( (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][74]~q  & 
// (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][75]~q  & !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][77]~q )) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][77]~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~0 .lut_mask = 64'h8080808000000000;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y18_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout  & 
// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout  & 
// !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) ) ) # ( \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout  & (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][75]~q  
// $ (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][74]~q ))) ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout  & (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][75]~q  
// $ (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][74]~q ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout ),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datae(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h4141414155000055;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y18_N44
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y18_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~0_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( 
// (!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]) ) ) # ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]) # 
// (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h3F3F3F3FC0C0C0C0;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y18_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout  = ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~0_combout  & ( 
// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout  ) ) ) # ( 
// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~0_combout  & ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( 
// (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout  & (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][76]~q  $ (((\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][75]~q ) # 
// (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][74]~q ))))) ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~0_combout  & ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout 
//  & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout  & (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][76]~q  $ (((\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][75]~q ) # 
// (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][74]~q ))))) ) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout ),
        .datae(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~0_combout ),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h0087008700FF0000;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y18_N26
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y18_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~2 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~2_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [5] ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [5] $ (((!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & 
// !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h3FC03FC0FF00FF00;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y18_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~1_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][76]~q  & ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][77]~q  ) ) # ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][76]~q  & ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][77]~q  $ (((!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][75]~q  & 
// !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][74]~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][77]~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h5AAA5AAAAAAAAAAA;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y18_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~1_combout  & ( 
// (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout  & 
// !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~2_combout )) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~1_combout  & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout  & 
// ((!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ) # (!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~2_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout ),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~2_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h0F0A0F0A05000500;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y18_N5
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y18_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~1_combout  = ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// (!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & 
// !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [5])) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~1 .lut_mask = 64'hA000A00000000000;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y18_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( 
// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~1_combout  & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout  & 
// (!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][78]~q  $ (!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~0_combout )))) ) ) ) 
// # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~1_combout  & ( 
// (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][78]~q  $ (!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~0_combout )) # 
// (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~1_combout  & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][78]~q  $ 
// (!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~0_combout )) # (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~1_combout  & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout  
// & (!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][78]~q  $ (!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~0_combout )))) ) ) 
// )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][78]~q ),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout ),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~0_combout ),
        .datae(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h1020132313231020;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y18_N14
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y18_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~0_combout  & ( \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~1_combout  & ( 
// (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ((!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][78]~q 
// ))) # (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6])))) ) ) ) # ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~0_combout  & ( \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~1_combout  & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout  & 
// (!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout )) ) ) ) # ( 
// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~0_combout  & ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~1_combout  & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout  & 
// (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][78]~q  & !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout ),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][78]~q ),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datae(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~0_combout ),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h0000500000445044;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y18_N37
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y18_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~1_combout  = ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( 
// (!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & 
// !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [5])) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'h8800880000000000;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y18_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_busy~q  & ( 
// ((!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~1_combout ) # (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2])) # 
// (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [7]) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h00000000F7F7F7F7;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y18_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( 
// (!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~2_combout  & \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout ) ) ) # ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][74]~q  & 
// (!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~2_combout  & \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout )) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h00A000A000F000F0;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y18_N8
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y18_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~2 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~2_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( 
// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_busy~q  ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y18_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~0_combout  = ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][77]~q  & ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][78]~q  & ( 
// (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][74]~q  & (!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_busy~q  & (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][76]~q  & 
// !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][75]~q ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datae(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][77]~q ),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][78]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h4000000000000000;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y18_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][66]~q  & ( \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~1_combout  & ( 
// (!\u0|mm_interconnect_0|write_en_tx_s1_agent|comb~0_combout ) # ((!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~2_combout  & !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~0_combout )) ) ) ) # ( 
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][66]~q  & ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~1_combout  & ( (!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~0_combout ) # 
// (!\u0|mm_interconnect_0|write_en_tx_s1_agent|comb~0_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent|comb~0_combout ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][66]~q ),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h0000FCFC0000F8F8;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y18_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|always0~0_combout  & ( (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [0]) # 
// (!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|always0~0_combout  & ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [0] ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|always0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hAAAAAAAAFAFAFAFA;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y23_N56
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~21_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][116]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y27_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal20~0 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal20~0_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & \u0|mm_interconnect_0|router_001|Equal3~0_combout ) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|router_001|Equal3~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router_001|Equal20~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal20~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal20~0 .lut_mask = 64'h0000000005050505;
defparam \u0|mm_interconnect_0|router_001|Equal20~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y27_N59
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[14] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|router_001|Equal20~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [14]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[14] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[14] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y27_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|src14_valid~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|src14_valid~1_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [14] & ( \u0|mm_interconnect_0|router_001|Equal3~0_combout  & ( (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & 
// (\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [19])) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [14] & ( \u0|mm_interconnect_0|router_001|Equal3~0_combout  & ( 
// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q  & (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [19]))) ) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),
        .datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [14]),
        .dataf(!\u0|mm_interconnect_0|router_001|Equal3~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux_001|src14_valid~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|src14_valid~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|src14_valid~1 .lut_mask = 64'h0000000000020003;
defparam \u0|mm_interconnect_0|cmd_demux_001|src14_valid~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y22_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~0_combout  = ( !\u0|mm_interconnect_0|cmd_demux_001|src14_valid~1_combout  & ( !\u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_demux_001|src14_valid~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~0 .lut_mask = 64'hF0F0F0F000000000;
defparam \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y22_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_payload[0] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_payload [0] = ( \u0|hps_0|fpga_interfaces|h2f_WLAST [0] & ( (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]) # (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_WLAST [0] & 
// ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_WLAST [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_014|src_payload [0]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_payload[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_payload[0] .lut_mask = 64'h3333333333FF33FF;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_payload[0] .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y22_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y22_N5
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y27_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|src14_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|src14_valid~0_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [14]) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [14]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux_001|src14_valid~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|src14_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|src14_valid~0 .lut_mask = 64'h00000000F0FFF0FF;
defparam \u0|mm_interconnect_0|cmd_demux_001|src14_valid~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y27_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_valid~0_combout  = ( \u0|mm_interconnect_0|cmd_demux_001|src14_valid~0_combout  & ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & 
// (\u0|mm_interconnect_0|router_001|Equal3~0_combout  & \u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]))) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),
        .datac(!\u0|mm_interconnect_0|router_001|Equal3~0_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_demux_001|src14_valid~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_014|src_valid~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_valid~0 .lut_mask = 64'h0000000000010001;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_valid~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y23_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout  = ( \u0|mm_interconnect_0|cmd_mux_014|src_valid~0_combout  & ( \u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout  & ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_014|src_valid~0_combout  & ( \u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout  & ( 
// (!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]) # (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_014|src_valid~0_combout  & ( 
// !\u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout  & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_014|src_valid~0_combout  & ( 
// !\u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout  ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_014|src_valid~0_combout ),
        .dataf(!\u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .lut_mask = 64'hFFFFF0F0FCFCF0F0;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y19_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_data[33] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_data [33] = ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_WSTRB [1] ) ) # ( !\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_WSTRB [1] & ( 
// \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & ( !\u0|hps_0|fpga_interfaces|h2f_WSTRB [1] ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_014|src_data [33]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[33] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[33] .lut_mask = 64'h0000FFFF5555FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[33] .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y20_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y20_N17
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on

// Location: FF_X22_Y19_N17
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y19_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout  & ( 
// !\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout  & ( (!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & 
// !\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .lut_mask = 64'hA0A0A0A0AAAAAAAA;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y19_N32
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y19_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_data[35] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_data [35] = ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & ( (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]) # (\u0|hps_0|fpga_interfaces|h2f_WSTRB [3]) ) ) # ( 
// !\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [3]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_014|src_data [35]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[35] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[35] .lut_mask = 64'h00FF00FF55FF55FF;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[35] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y19_N47
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_014|src_data [35]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y19_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_data[34] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_data [34] = ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & ( (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]) # (\u0|hps_0|fpga_interfaces|h2f_WSTRB [2]) ) ) # ( 
// !\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [2]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_014|src_data [34]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[34] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[34] .lut_mask = 64'h00FF00FF0FFF0FFF;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[34] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y19_N59
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_014|src_data [34]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y19_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_data[32] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_data [32] = ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] ) # ( !\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_WSTRB [0] & \u0|mm_interconnect_0|cmd_mux_014|saved_grant 
// [0]) ) )

        .dataa(gnd),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [0]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_014|src_data [32]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[32] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[32] .lut_mask = 64'h0303FFFF0303FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[32] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y19_N14
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_014|src_data [32]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y19_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~2_combout  = ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & ( 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~2 .lut_mask = 64'hC000C00000000000;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~2 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y19_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~feeder (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y19_N5
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y19_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg~0_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_read~0_combout  & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout  & 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_read~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg~0 .lut_mask = 64'h0000000088888888;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y19_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_write (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_write~combout  = (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~0_combout  & 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout ))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_write~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_write .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_write .lut_mask = 64'h0C000C000C000C00;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_write .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y19_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~0_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_write~combout  & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~q  & 
// ((\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [0]) # (\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [1]))) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_write~combout  & ( 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~q  & (\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg~0_combout  & ((!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter 
// [0]) # (\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [1])))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [1]),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [0]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~q ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_write~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~0 .lut_mask = 64'h000D000D07070707;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y19_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~1_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~0_combout  & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter 
// [0] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~1 .lut_mask = 64'h00000000FF00FF00;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y19_N44
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y19_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~2_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~0_combout  & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter 
// [0] $ (!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [1]) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [0]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~2 .lut_mask = 64'h000000000FF00FF0;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y19_N35
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y19_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~0_combout  = ( !\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [1] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~q  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~0 .lut_mask = 64'h00FF00FF00000000;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y20_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_data[88] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_data [88] = ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & ( ((\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0])) # (\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]) ) ) # ( 
// !\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_014|src_data [88]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[88] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[88] .lut_mask = 64'h111111111F1F1F1F;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[88] .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y20_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_data[87] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_data [87] = ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] & ( ((\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1])) # (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] & ( (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_014|src_data [87]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[87] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[87] .lut_mask = 64'h0303030357575757;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[87] .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y19_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout  = ( !\u0|mm_interconnect_0|cmd_mux_014|src_data [88] & ( !\u0|mm_interconnect_0|cmd_mux_014|src_data [87] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_014|src_data [88]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_014|src_data [87]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .lut_mask = 64'hFFFF000000000000;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y19_N41
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y19_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~3_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [0] & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~2_combout  & 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~0_combout  & (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~0_combout ))) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~2_combout  & 
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ) # ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~0_combout  & 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~0_combout )))) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [0] & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~2_combout  & 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~0_combout  & (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~0_combout ))) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~2_combout  & 
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ) # ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~0_combout  & 
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~0_combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~2_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~0_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~3 .lut_mask = 64'h5703570375307530;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y19_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~3_combout  & ( 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & 
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q )))) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~3_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q  & 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h00AA00AA00CA00CA;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y19_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout  & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) # 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ))) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout  & ( 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout 
// )) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout  & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  
// & ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) # 
// ((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ) # (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout 
// )))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout  & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  
// & (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// ((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ) # (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout 
// )))) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
        .datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .lut_mask = 64'h0111455500114455;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y19_N38
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .power_up = "low";
// synopsys translate_on

// Location: FF_X25_Y22_N35
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_014|src_payload [0]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y19_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) # ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~1_combout  & 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q )) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~1_combout  & 
// ((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )))) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q  & ( 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~1_combout  & 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q )) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~1_combout  & 
// ((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~1_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .lut_mask = 64'h00530053FF53FF53;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y19_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout  = ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) # (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ) 
// ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .lut_mask = 64'hFF00FF00FFF0FFF0;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y19_N59
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .power_up = "low";
// synopsys translate_on

// Location: FF_X27_Y19_N56
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";
// synopsys translate_on

// Location: FF_X27_Y19_N17
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y19_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_read~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_read~0_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & ( 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_read~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_read~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_read~0 .lut_mask = 64'h000F000F0F0F0F0F;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_read~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y19_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|write~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|write~0_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~4_combout  & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~0_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) # 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_read~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~4_combout  & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~0_combout  & ( 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout  & (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & 
// ((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_read~0_combout )))) ) ) ) # ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~4_combout  & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~0_combout  & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_read~0_combout ) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~4_combout  & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~0_combout  & ( 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout  & (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_read~0_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_read~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~4_combout ),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|write~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|write~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h04040C0C04440CCC;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|write~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y19_N8
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][129] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][129]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y19_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~0_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][129]~q  & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~0_combout  & ( 
// (((\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout  & \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_read~0_combout )) # 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout )) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][129]~q  & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~0_combout  & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & 
// (((\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout  & \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_read~0_combout )) # 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ))) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][129]~q  & ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~0_combout  & ( ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout  & \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_read~0_combout )) # 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][129]~q  & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~0_combout  & ( 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout  & (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_read~0_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_read~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][129]~q ),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~0 .lut_mask = 64'h0404373704CC37FF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y19_N53
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][66]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y19_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~3_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][66]~q  & ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][66]~q  & ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] ) ) ) # ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][66]~q  & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][66]~q ),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h00005555AAAAFFFF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y19_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66]~feeder_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~3_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y19_N35
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";
// synopsys translate_on

// Location: FF_X21_Y19_N23
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][68] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][68]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][68] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][68] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y19_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~2_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][68]~q  & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] ) ) # ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][68]~q  & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][68]~q  & ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][68]~q ),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~2 .lut_mask = 64'h0F0F0F0F0000FFFF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y19_N59
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][68] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~2_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][68]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][68] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][68] .power_up = "low";
// synopsys translate_on

// Location: FF_X21_Y19_N14
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][69] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][69]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][69] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y19_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~1_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][69]~q  & ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][69]~q  & ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] ) ) ) # ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][69]~q  & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][69]~q ),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h00000F0FF0F0FFFF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y19_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][69]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][69]~feeder_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~1_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][69]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][69]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][69]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][69]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y19_N26
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][69] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][69]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][69]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][69] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y19_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_014|src0_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_014|src0_valid~0_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][68]~q  & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][69]~q  & ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66]~q  ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66]~q ),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][68]~q ),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][69]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_demux_014|src0_valid~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_014|src0_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_014|src0_valid~0 .lut_mask = 64'h0000AAAA00000000;
defparam \u0|mm_interconnect_0|rsp_demux_014|src0_valid~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y18_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_014|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_014|WideOr0~0_combout  = ( \u0|hps_0|fpga_interfaces|h2f_BREADY [0] & ( (\u0|hps_0|fpga_interfaces|h2f_RREADY [0]) # (\u0|mm_interconnect_0|rsp_demux_014|src0_valid~0_combout ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_BREADY 
// [0] & ( (!\u0|mm_interconnect_0|rsp_demux_014|src0_valid~0_combout  & \u0|hps_0|fpga_interfaces|h2f_RREADY [0]) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_014|src0_valid~0_combout ),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_BREADY [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_demux_014|WideOr0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_014|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_014|WideOr0~0 .lut_mask = 64'h00AA00AA55FF55FF;
defparam \u0|mm_interconnect_0|rsp_demux_014|WideOr0~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y18_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|comb~0_combout  & ( \u0|mm_interconnect_0|rsp_demux_014|WideOr0~0_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|rsp_demux_014|WideOr0~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|comb~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y18_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[0]~1_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|write~0_combout ) # 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0]) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & ( ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0] & 
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0_combout ) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout )))) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|write~0_combout ) 
// ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0]),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|write~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h51FF51FF55FF55FF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y18_N35
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y18_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0_combout  & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0]) # 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0_combout  & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0] ) 
// )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hF0F0F0F0FFF0FFF0;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y18_N41
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][129] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][129]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y18_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|comb~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|comb~0_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0] ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0] & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0] & ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][129]~q ) # 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0]))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0]),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0]),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|comb~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|comb~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|comb~0 .lut_mask = 64'h07070F0F07070F0F;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|comb~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y19_N50
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][74] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][74]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y19_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~5 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~5_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & (((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) # 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & 
// (((\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][74]~q )))) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & 
// (((\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][74]~q )))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][74]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h083B083B4C7F4C7F;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y18_N2
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~5_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y19_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout  = ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) # 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg 
// [2]))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) # 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg 
// [2]))) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .lut_mask = 64'h0000FFFFDD887722;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y19_N59
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y19_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout  = ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) # 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) # 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg 
// [2])))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & 
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])))) # 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg 
// [2])))) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .lut_mask = 64'h0000FFFFD85072FA;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y19_N26
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";
// synopsys translate_on

// Location: FF_X22_Y19_N2
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][76] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~7_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][76]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y19_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~7 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~7_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][76]~q  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][76]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h0505050500FF00FF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y18_N5
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][76] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~7_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][76]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";
// synopsys translate_on

// Location: FF_X22_Y19_N53
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][75] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][75]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y19_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~6 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~6_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][75]~q  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][75]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h0505050500FF00FF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y18_N14
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][75] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~6_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][75]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y18_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~q  & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout  & 
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][75]~q )) # 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))))) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~q  & ( 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][75]~q )) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))))) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~q  & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout  & 
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][75]~q )) # 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))))) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~q  & ( 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][75]~q )) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))))) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout ),
        .datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h00D8008D00720027;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y18_N44
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y18_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~0_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [4] ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [4] $ (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [3]) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h5A5A5A5AAAAAAAAA;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y18_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~q  & ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout  & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][76]~q )) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~q  & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout  
// & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][76]~q  $ 
// ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][75]~q )))) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~0_combout )))) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~0_combout ),
        .datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~q ),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h000000009F905F50;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y18_N38
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y16_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~1_combout  = ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [3]) ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~1 .lut_mask = 64'hC0C0000000000000;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y19_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  = ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h00000000A000A000;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y19_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout  = ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & ( 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout )) 
// # (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) # 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & ( 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout )) # 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .lut_mask = 64'h27222722DDD8DDD8;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y19_N29
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y19_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout  = ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & ( 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # 
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) # 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & ( 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q 
//  & \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ) ) # ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & ( 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout 
// )))) # (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # 
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )))) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & ( 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout 
// )))) # (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & 
// ((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )))) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 .lut_mask = 64'h303ACFCA000AFFFA;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y19_N8
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";
// synopsys translate_on

// Location: FF_X22_Y19_N5
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][78] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~9_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][78]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y19_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~9 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~9_combout  = (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]))) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & 
// (((\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][78]~q ))))

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][78]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~9 .lut_mask = 64'h0437043704370437;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~9 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y18_N17
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][78] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~9_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][78]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";
// synopsys translate_on

// Location: FF_X22_Y19_N32
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][77] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][77]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y19_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~8 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~8_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & ( 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) # 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][77]~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][77]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][77]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~8 .lut_mask = 64'h003300330C3F0C3F;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y18_N35
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][77] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~8_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][77]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y18_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~0_combout  = ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][77]~q  & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~q  & 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][76]~q  & !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][75]~q )) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][77]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~0 .lut_mask = 64'hC000C00000000000;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y18_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~0_combout  & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout  & 
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][78]~q ))) # 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~1_combout )))) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~0_combout  & ( 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][78]~q ))) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~1_combout )))) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~0_combout  & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout  & 
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][78]~q ))) # 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~1_combout )))) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~0_combout  & ( 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][78]~q ))) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~1_combout )))) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~1_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][78]~q ),
        .datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h0131023231013202;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y18_N26
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y18_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout  & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & 
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~1_combout ) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout  & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~0_combout  & !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][78]~q ) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~1_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][78]~q ),
        .datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h000000000F002222;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y18_N7
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";
// synopsys translate_on

// Location: FF_X23_Y18_N11
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_busy (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y18_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_busy~q  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~1_combout ) # ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [7]) # 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [2])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h00000000CFFFCFFF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y18_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~2_combout  = (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_busy~q  & 
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [2])

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h000F000F000F000F;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y18_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout  = ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~2_combout  & ( 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~q ) # 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h0A0F0A0F00000000;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y18_N53
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y16_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~2_combout  = ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [3]) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [5] ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [3]) # 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h3F3FFFFFC0C00000;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y18_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~1_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][77]~q  & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~q  & 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][75]~q  & !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][76]~q )) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][77]~q  & ( 
// ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][76]~q ) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][75]~q )) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][77]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h7F7F7F7F80808080;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y18_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout  & !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~2_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout  & 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~1_combout ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~2_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h3300330030303030;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y18_N50
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y18_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~1_combout  = ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [4])) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'hA000A00000000000;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y18_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~0_combout  = ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][76]~q  & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_busy~q  
// & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][77]~q  & (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][78]~q  & (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~q  & 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][75]~q ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][77]~q ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][78]~q ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][76]~q ),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h0800000000000000;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y18_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~0_combout  & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|comb~0_combout  & 
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66]~q ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~0_combout  & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66]~q  & 
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|comb~0_combout ) # ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~1_combout ) # (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~2_combout 
// )))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|comb~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h00FE00FE00AA00AA;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y18_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[1]~0_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0_combout  & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|write~0_combout  & 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout  & ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1])))) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|write~0_combout  & 
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout  & ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]))) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout 
//  & (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0])))) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0_combout  & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|write~0_combout  & 
// ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]))) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|write~0_combout  & (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0])) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|write~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[1]~0 .lut_mask = 64'h05AF05AF01670167;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[1]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y18_N20
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y19_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~1_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [0] & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & 
// (((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~0_combout  & \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~0_combout )) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout ))) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [0] & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & (((\u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~0_combout  & 
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~0_combout )) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~1 .lut_mask = 64'h444C444C44C444C4;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y19_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  = ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~1_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h0000000000FF00FF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y19_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout  = ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) # 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg 
// [2])) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .lut_mask = 64'h00FF00FFFA50FA50;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y19_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout  = ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout  & 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0 .lut_mask = 64'hC0C0C0C000000000;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y19_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout  = ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h0010001030303030;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y19_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & ( 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h000000000F000F00;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y19_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout  ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout  & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout  & 
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ) # 
// ((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ) # 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h00BF00BFFFFFFFFF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y19_N23
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y19_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  = ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// ((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) # 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'h000000005F005F00;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y23_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout  = ( \u0|mm_interconnect_0|cmd_mux_014|src_valid~0_combout  & ( 
// \u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout  & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & 
// ((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ) # 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_014|src_valid~0_combout  & ( \u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout  
// & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & 
// ((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ) # 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )))) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_014|src_valid~0_combout  & ( !\u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout 
//  & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & ((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout 
// ) # (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
        .datae(!\u0|mm_interconnect_0|cmd_mux_014|src_valid~0_combout ),
        .dataf(!\u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h0000070700070707;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y19_N53
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_014|src_data [33]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y19_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout  = ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ) # 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )))) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0 .lut_mask = 64'hA080000000000000;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y19_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] & ( 
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # ((!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [0] & 
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~0_combout ))) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout ) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] & ( 
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # ((\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [0] & 
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~0_combout ))) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [0]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~0_combout ),
        .datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hF5F7F0F0F5FDF0F0;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y19_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18_combout  = ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ) # 
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) # (((!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & !\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1])) # 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ))) ) ) # ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & 
// ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ) # 
// ((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout 
// ))))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
        .datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
        .datag(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18 .extended_lut = "on";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18 .lut_mask = 64'hFEEEAAAAFFFFABAB;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y19_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1_combout  = ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1 .lut_mask = 64'hFFFFFFFF00000000;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y19_N5
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y19_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  = ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  $ 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ))) # 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .lut_mask = 64'hA50AA50A0A000A00;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y19_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout  = ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .lut_mask = 64'hFF00FF0000000000;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y19_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  
// & ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( ((\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & 
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ) # (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout )))) # 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  ) ) ) # ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),
        .datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .lut_mask = 64'h0000303055557775;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y19_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout  = ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout  & ( 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout  & 
// !\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16 .lut_mask = 64'h0300030000000000;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y19_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout  = ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// ((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) # 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .lut_mask = 64'h04040404040C040C;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y19_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  = ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  
// & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .lut_mask = 64'h0505050500000000;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y19_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  & ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  & ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout  & ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout  ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  & ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  & ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout  & ( 
// ((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout  & 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout  & 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ))) # (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),
        .datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17 .lut_mask = 64'h5575FFFF5555FFFF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y19_N38
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y19_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  = ( !\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & ( (((!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & 
// ((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ))))) ) ) # ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & ( 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ) # (((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q  & 
// ((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) # 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) # 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datae(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datag(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .extended_lut = "on";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .lut_mask = 64'h0000F1F3F0F0FFFF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y22_N20
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y27_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add6~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add6~0_combout  = ( \u0|hps_0|fpga_interfaces|h2f_AWLEN [1] & ( \u0|hps_0|fpga_interfaces|h2f_AWLEN [0] & ( \u0|hps_0|fpga_interfaces|h2f_AWLEN [2] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [2]),
        .datad(gnd),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [1]),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add6~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add6~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add6~0 .lut_mask = 64'h0000000000000F0F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add6~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y27_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~2 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~2_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3_combout  & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout  ) ) # ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3_combout  & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~4_combout  $ (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~4_combout ),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~2 .lut_mask = 64'h0FF00FF000FF00FF;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y27_N25
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y27_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout  = ( \u0|hps_0|fpga_interfaces|h2f_AWLEN [0] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (!\u0|hps_0|fpga_interfaces|h2f_AWLEN [2] $ 
// ((!\u0|hps_0|fpga_interfaces|h2f_AWLEN [1])))) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount [4])))) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_AWLEN [0] & ( 
// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (\u0|hps_0|fpga_interfaces|h2f_AWLEN [2])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount [4]))) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [2]),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [1]),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount [4]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2 .lut_mask = 64'h550F550F660F660F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y27_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~1 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~1_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3_combout  & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~1_combout  ) ) # ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3_combout  & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~1_combout  $ (((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~4_combout ) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout ))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~4_combout ),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~1_combout ),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~1 .lut_mask = 64'h3C0F3C0F0F0F0F0F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y27_N50
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y27_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~1 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~1_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add6~0_combout  & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount [5] & ( 
// (!\u0|hps_0|fpga_interfaces|h2f_AWLEN [3]) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add6~0_combout  & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount 
// [5] & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ) # (\u0|hps_0|fpga_interfaces|h2f_AWLEN [3]) ) ) ) # ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add6~0_combout  & ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount [5] & ( (!\u0|hps_0|fpga_interfaces|h2f_AWLEN [3] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ) ) ) ) # ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add6~0_combout  & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount [5] & ( (\u0|hps_0|fpga_interfaces|h2f_AWLEN [3] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ) ) ) 
// )

        .dataa(gnd),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [3]),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add6~0_combout ),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~1 .lut_mask = 64'h3030C0C03F3FCFCF;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y20_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~5 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~5_combout  = ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & ( (!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]) # 
// ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~4_combout  & \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0])) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & ( 
// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~4_combout  & \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~4_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~5 .lut_mask = 64'h00F000F0AAFAAAFA;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y20_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~6 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~6_combout  = ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~5_combout  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] $ 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~5_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~6 .lut_mask = 64'h0FF00FF055555555;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y20_N53
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y20_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & ( 
// ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3_combout  & \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3_combout  & \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0 .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y20_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout  = ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0_combout  & ( 
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])) # (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q 
// ) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0_combout  & ( 
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg 
// [2])) # (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) ) # ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg 
// [2] & \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1 .lut_mask = 64'h00A0AA0A55F5FF5F;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y20_N26
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y20_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & 
// ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] $ 
// (((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .lut_mask = 64'hCF30CF30FF00FF00;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y20_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout  & ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout  & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout )))) # (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0])) # (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]))) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout  & ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout  & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ))) # (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0])) ) ) ) # ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout  & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ))) # 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1])) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout  & ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout  & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  & 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .lut_mask = 64'hF000F055F033F077;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y20_N38
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y20_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] ) 
// # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( 
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4])) # 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .lut_mask = 64'hF5FFF5FFFFFFFFFF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y22_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7_combout  = ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg 
// [5] $ ((((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout )))) ) ) # ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( ((!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & (((\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~1_combout )))) # (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & (((\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~1_combout )) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
        .datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~1_combout ),
        .datag(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7 .extended_lut = "on";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7 .lut_mask = 64'hA5A50303A5A503FF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y22_N56
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y22_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~2_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~0_combout  & ( 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout )) # 
// (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]))) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~0_combout  & ( (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout  & \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~2 .lut_mask = 64'h0003000300570057;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~2 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y22_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3_combout  = ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~2_combout  ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~2_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg 
// [6] $ (((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]) # 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ))))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3 .lut_mask = 64'h802A802AFFFFFFFF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y20_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Equal0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Equal0~0_combout  = ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~6_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7_combout  & 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3_combout  & 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout )) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~6_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Equal0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Equal0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Equal0~0 .lut_mask = 64'h00000000C000C000;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Equal0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y19_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout  
// & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Equal0~0_combout  & 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout  & ( ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout 
// ) # ((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Equal0~0_combout  & 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout ))) # 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Equal0~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .lut_mask = 64'hDFDDDFDD0F000F00;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y19_N44
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y19_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  = ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( 
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) ) ) # ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # 
// ((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~1_combout ))))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~1_combout ),
        .datag(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .extended_lut = "on";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .lut_mask = 64'h0C00F0F00C00F5F5;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y22_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  = ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .lut_mask = 64'hF0F0F0F000000000;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y22_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|packet_in_progress~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|packet_in_progress~0_combout  = ( !\u0|mm_interconnect_0|cmd_mux_014|update_grant~0_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_014|update_grant~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_014|packet_in_progress~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|packet_in_progress~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|packet_in_progress~0 .lut_mask = 64'hFFFFFFFF00000000;
defparam \u0|mm_interconnect_0|cmd_mux_014|packet_in_progress~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y22_N2
dffeas \u0|mm_interconnect_0|cmd_mux_014|packet_in_progress (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_014|packet_in_progress~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_014|packet_in_progress~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|packet_in_progress .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_014|packet_in_progress .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y22_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|update_grant~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|update_grant~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & ( \u0|mm_interconnect_0|cmd_mux_014|src_valid~0_combout  & ( (\u0|mm_interconnect_0|cmd_mux_014|src_payload [0] & 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & ( \u0|mm_interconnect_0|cmd_mux_014|src_valid~0_combout  & ( 
// (\u0|mm_interconnect_0|cmd_mux_014|src_payload [0] & !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & ( 
// !\u0|mm_interconnect_0|cmd_mux_014|src_valid~0_combout  & ( (!\u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout  & (((!\u0|mm_interconnect_0|cmd_mux_014|packet_in_progress~q )))) # (\u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout  & 
// (\u0|mm_interconnect_0|cmd_mux_014|src_payload [0] & (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & ( 
// !\u0|mm_interconnect_0|cmd_mux_014|src_valid~0_combout  & ( !\u0|mm_interconnect_0|cmd_mux_014|packet_in_progress~q  ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_014|src_payload [0]),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_014|packet_in_progress~q ),
        .datad(!\u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout ),
        .datae(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_014|src_valid~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_014|update_grant~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|update_grant~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|update_grant~0 .lut_mask = 64'hF0F0F04444444444;
defparam \u0|mm_interconnect_0|cmd_mux_014|update_grant~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y22_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~2 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~2_combout  = ( \u0|mm_interconnect_0|cmd_mux_014|update_grant~0_combout  & ( (!\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~0_combout  & 
// (!\u0|mm_interconnect_0|cmd_mux_014|arb|grant[1]~0_combout )) # (\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~0_combout  & ((\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg [0]))) ) ) # ( 
// !\u0|mm_interconnect_0|cmd_mux_014|update_grant~0_combout  & ( \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg [0] ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_014|arb|grant[1]~0_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_014|update_grant~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~2 .lut_mask = 64'h00FF00FFA0F5A0F5;
defparam \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y22_N2
dffeas \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y22_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~1_combout  = ( \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg [1] & ( \u0|mm_interconnect_0|cmd_mux_014|update_grant~0_combout  & ( 
// (\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~0_combout ) # (\u0|mm_interconnect_0|cmd_mux_014|arb|grant[0]~1_combout ) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg [1] & ( 
// \u0|mm_interconnect_0|cmd_mux_014|update_grant~0_combout  & ( (\u0|mm_interconnect_0|cmd_mux_014|arb|grant[0]~1_combout  & !\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~0_combout ) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg 
// [1] & ( !\u0|mm_interconnect_0|cmd_mux_014|update_grant~0_combout  ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_014|arb|grant[0]~1_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~0_combout ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg [1]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_014|update_grant~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~1 .lut_mask = 64'h0000FFFF50505F5F;
defparam \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y22_N56
dffeas \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y22_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|arb|grant[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|arb|grant[1]~0_combout  = ( \u0|mm_interconnect_0|cmd_demux_001|src14_valid~1_combout  & ( ((!\u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout  & !\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg [0])) # 
// (\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg [1]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg [0]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_demux_001|src14_valid~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_014|arb|grant[1]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|arb|grant[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|arb|grant[1]~0 .lut_mask = 64'h00000000C0FFC0FF;
defparam \u0|mm_interconnect_0|cmd_mux_014|arb|grant[1]~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y22_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|saved_grant[1]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|saved_grant[1]~feeder_combout  = ( \u0|mm_interconnect_0|cmd_mux_014|arb|grant[1]~0_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_014|arb|grant[1]~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_014|saved_grant[1]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|saved_grant[1]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|saved_grant[1]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|cmd_mux_014|saved_grant[1]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y22_N44
dffeas \u0|mm_interconnect_0|cmd_mux_014|saved_grant[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_014|saved_grant[1]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|cmd_mux_014|update_grant~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|saved_grant[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_014|saved_grant[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y23_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_data[116] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_data [116] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [11] & ( ((\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [11])) # (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_AWID [11] & ( (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [11]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
        .datac(gnd),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [11]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_014|src_data [116]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[116] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[116] .lut_mask = 64'h0055005533773377;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[116] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y23_N44
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_014|src_data [116]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";
// synopsys translate_on

// Location: FF_X23_Y23_N17
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~21_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][116]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y23_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~21 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~21_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][116]~q  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][116]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~21_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~21 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~21 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~21 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y23_N26
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~21_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][116]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y18_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|rp_valid (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|rp_valid~combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0] & 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][129]~q  & !\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0])) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0] & ( 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0] & !\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0]) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0]),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|rp_valid~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|rp_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|rp_valid .lut_mask = 64'hAA00AA0088008800;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|rp_valid .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y18_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_014|src1_valid (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout  = ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|rp_valid~combout  & ( !\u0|mm_interconnect_0|rsp_demux_014|src0_valid~0_combout  ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_014|src0_valid~0_combout ),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|rp_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_014|src1_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_014|src1_valid .lut_mask = 64'hAAAAAAAA00000000;
defparam \u0|mm_interconnect_0|rsp_demux_014|src1_valid .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y23_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~201 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~201_combout  = ( \u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout  & ( ((\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout  & \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][116]~q )) # 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][116]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout  & ( (\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout  & 
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][116]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][116]~q ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][116]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~201_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~201 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~201 .lut_mask = 64'h0505050505FF05FF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~201 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y24_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_data[116] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_data [116] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [11] & ( ((\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [11])) # (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_ARID [11] & ( (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [11]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
        .datac(gnd),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_AWID [11]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_010|src_data [116]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[116] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[116] .lut_mask = 64'h0055005533773377;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[116] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y24_N17
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_010|src_data [116]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";
// synopsys translate_on

// Location: FF_X22_Y24_N26
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~21_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][116]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y24_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~21 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~21_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][116]~q  ) ) # ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][116]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~21_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~21 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~21 .lut_mask = 64'h3333333300FF00FF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~21 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y24_N26
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~21_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][116]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y24_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|src_data[116] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|src_data [116] = ( \u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & ( ((\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [11])) # (\u0|hps_0|fpga_interfaces|h2f_ARID [11]) ) ) # ( 
// !\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & ( (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [11]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_AWID [11]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_009|src_data [116]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[116] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[116] .lut_mask = 64'h111111111F1F1F1F;
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[116] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y24_N20
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_009|src_data [116]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";
// synopsys translate_on

// Location: FF_X17_Y24_N2
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~21_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][116]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y24_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~21 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~21_combout  = ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][116]~q  & ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] ) ) # ( 
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][116]~q  & ( !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg 
// [116] ) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][116]~q  & ( !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ( 
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][116]~q ),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~21_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~21 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~21 .lut_mask = 64'h0F0F0F0F0000FFFF;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~21 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y24_N38
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~21_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][116]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y24_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~200 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~200_combout  = ( \u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout  & ( ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][116]~q  & 
// \u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout )) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][116]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout  & ( 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][116]~q  & \u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ) ) )

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][116]~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][116]~q ),
        .datae(!\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~200_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~200 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~200 .lut_mask = 64'h050505FF050505FF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~200 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y33_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override~feeder (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y33_N5
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y33_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg~0_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override~q  & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~0_combout  & 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout  & \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter [0])) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~0_combout ),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout ),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg~0 .lut_mask = 64'h0000000004040404;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y33_N2
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X30_Y33_N38
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][129] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][129]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y33_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~1_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( ((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout  & 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~0_combout )) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][129]~q ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout  & \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~0_combout ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout ),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~0_combout ),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][129]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h0303030303FF03FF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y34_N38
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][77] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][77]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y34_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~4 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~4_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][77]~q  & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] ) ) # ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][77]~q  & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][77]~q  & ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][77]~q ),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~4 .lut_mask = 64'h030303030000FFFF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y34_N5
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][77] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~4_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][77]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";
// synopsys translate_on

// Location: FF_X27_Y34_N8
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][74] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~7_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][74]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y34_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~7 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~7_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]) # 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][74]~q ) ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][74]~q ) ) ) ) # ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & 
// ((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][74]~q ))) ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & 
// ((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][74]~q ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][74]~q ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h474747470303CFCF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y34_N53
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~7_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";
// synopsys translate_on

// Location: FF_X27_Y34_N14
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][75] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][75]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y34_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~6 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~6_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][75]~q  & ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][75]~q  & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) ) ) ) # ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][75]~q  & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][75]~q ),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h000033330C0C3F3F;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y34_N38
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~6_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";
// synopsys translate_on

// Location: FF_X30_Y34_N35
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_busy (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";
// synopsys translate_on

// Location: FF_X27_Y34_N59
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][78] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][78]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y34_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~3 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~3_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][78]~q  & ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]) # 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][78]~q  & ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][78]~q  & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][78]~q ),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h00000F0F50505F5F;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y34_N2
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][78] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~3_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][78]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";
// synopsys translate_on

// Location: FF_X27_Y34_N35
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][76] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][76]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y34_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~5 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~5_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][76]~q  & ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]) # 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]) ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][76]~q  & ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][76]~q  & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][76]~q ),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h00000F0F50505F5F;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y34_N11
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][76] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~5_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][76]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y34_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~0_combout  = ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][78]~q  & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][76]~q  & ( 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][77]~q  & (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q  & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q  & 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][77]~q ),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][78]~q ),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h2000000000000000;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y34_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~0_combout  = ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q  & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q  & 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][76]~q  & !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][77]~q )) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][77]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~0 .lut_mask = 64'hC000C00000000000;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y34_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~2 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h0000000000FF00FF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y34_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q  & ( 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout  & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout  & 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout )) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q  & ( 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout  & !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h5050505000500050;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y34_N14
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y34_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q  & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout  & 
// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ))) # 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ) # ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q  & ( 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// ((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ))) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ) # ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q  & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout  & 
// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ))) # 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ) # ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q  & ( 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ))) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h5404510104540151;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y34_N26
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y34_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~2 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~2_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [5] ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [5] $ (((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4]))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h3FC03FC0FF00FF00;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y34_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~1_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q  & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][77]~q  ) ) # ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q  & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][77]~q  $ (((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][76]~q  & 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][77]~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h5AAA5AAAAAAAAAAA;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y34_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~1_combout  & ( 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~2_combout  & (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout  & 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout )) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~1_combout  & ( 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~2_combout ) # 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~2_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h0F0A0F0A000A000A;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y34_N23
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y34_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1_combout  = ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1 .lut_mask = 64'hC000C00000000000;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y34_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1_combout  & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout  & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][78]~q  $ (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~0_combout )))) ) ) ) # ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1_combout  & ( 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][78]~q  $ (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~0_combout )) # 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1_combout  & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][78]~q  $ 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~0_combout )) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1_combout  & ( 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout  & 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][78]~q  $ (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~0_combout )))) ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][78]~q ),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~0_combout ),
        .datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h0220133113310220;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y34_N44
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y34_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1_combout  & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout ) ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1_combout  & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][78]~q  & (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout  & 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~0_combout )) ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1_combout  & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][78]~q  & (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout  & 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~0_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][78]~q ),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~0_combout ),
        .datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h000A0000000A0C0C;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y34_N31
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y34_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout  & ( 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q  & ((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) # 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [7]))) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout  & ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q  ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h0F0F0F0F07070707;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y34_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~0_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4] ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4] $ (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h5A5A5A5AAAAAAAAA;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y34_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q  & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q  & ( 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][76]~q )) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~0_combout ))))) ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q  & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q  & ( 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][76]~q )) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~0_combout ))))) ) ) ) # ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q  & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q  & ( 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][76]~q )) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~0_combout ))))) ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q  & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q  & ( 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][76]~q )) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~0_combout ))))) ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~0_combout ),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),
        .datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h00D8007200720072;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y34_N56
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y34_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout  = ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [5])) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'hA000A00000000000;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y33_N56
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][66]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y33_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~2 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~2_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][66]~q  ) ) # ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][66]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~2 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y33_N50
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~2_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][66]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y33_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][66]~q  & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|comb~0_combout ) # 
// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~0_combout  & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout ) # 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|comb~0_combout ),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][66]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h00000000EEEAEEEA;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y33_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout  & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0] ) ) # ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout  & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0]) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0]),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hCFCFCFCFCCCCCCCC;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y33_N53
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][129] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][129]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y33_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|read~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|read~0_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][129]~q  & ((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0]) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0])))) ) ) # ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0]) # 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0]))) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0]),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|read~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|read~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|read~0 .lut_mask = 64'h1133113310301030;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|read~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X31_Y15_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[1]~1_combout  = (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|read~0_combout  & (((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0] & 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [1])))

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|read~0_combout ),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0]),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[1]~1 .lut_mask = 64'h0A2A0A2A0A2A0A2A;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[1]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y15_N20
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y33_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[0]~0_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|read~0_combout  & ( ((\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0] & 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|read~0_combout  & ( 
// ((\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [1])) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0]) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|read~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h50FF50FF0F5F0F5F;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y33_N47
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y33_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|comb~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|comb~0_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0] & ( ((\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0]) # 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][129]~q )) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0]),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|comb~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|comb~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|comb~0 .lut_mask = 64'h000000003FFF3FFF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|comb~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y35_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|comb~0_combout  & ( \u0|hps_0|fpga_interfaces|h2f_RREADY [0] ) )

        .dataa(gnd),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|comb~0_combout ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0 .lut_mask = 64'h0000333300003333;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y33_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[0]~1_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0]) # 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|write~0_combout ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( ((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0] & 
// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout ) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout )))) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|write~0_combout ) ) 
// )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|write~0_combout ),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout ),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h55DF55DF55FF55FF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y33_N8
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y33_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][129]~q  & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0] & 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0])) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][129]~q  & ( 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0]),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0]),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid .lut_mask = 64'hF000F000C000C000;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y34_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y34_N38
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";
// synopsys translate_on

// Location: FF_X23_Y35_N8
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y35_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h0000000044444444;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y35_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y35_N59
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y35_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override~feeder (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y35_N17
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y35_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter~0_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override~q  & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~0_combout  & 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout  & !\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter [0])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~0_combout ),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout ),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter~0 .lut_mask = 64'h0000000030003000;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y35_N44
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y35_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter [0] & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override~q  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y35_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~1_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout  & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] ) ) # ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout  & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~1 .lut_mask = 64'h00AA00AAAAAAAAAA;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y35_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  = (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~1_combout  & 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~1_combout ),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h000F000F000F000F;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y35_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout  = ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) # 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) # ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  $ 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .lut_mask = 64'h33CC33CC22EE22EE;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y35_N8
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y35_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout  = ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) # 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) # ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] $ 
// (((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) # 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .lut_mask = 64'h30CF30CF22EE22EE;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y35_N29
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y35_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout  = ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg 
// [2]) # (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) ) ) ) # ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) # 
// ((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]) # 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) ) ) ) # ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg 
// [2] & \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) ) ) ) # ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .lut_mask = 64'h30002222CFFFEEEE;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y35_N50
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y35_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  = ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & 
// ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h3000300000000000;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y35_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout  = ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) # 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) # ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] $ (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) ) 
// )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .lut_mask = 64'h0FF00FF02E2E2E2E;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y35_N59
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";
// synopsys translate_on

// Location: FF_X25_Y35_N55
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y35_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout  = ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg 
// [2]) # (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) ) ) ) # ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] 
// & \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) ) ) ) # ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) # 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) ) ) ) # ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  & 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .lut_mask = 64'h0F00F0FF2222EEEE;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y35_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout  = ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout  & ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0 .lut_mask = 64'hF0F0F0F000000000;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y35_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout  = ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout  & ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout  & ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout  ) ) ) # ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout  & ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout  & ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout  ) ) ) # ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout  & ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout  & ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout  ) ) ) # ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout  & ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout  & ( 
// ((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout  & 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout  & 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout ))) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout ),
        .datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h3373333333333333;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y35_N38
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y35_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout  = ( \u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout  & ( 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & 
// \u0|mm_interconnect_0|cmd_mux_020|saved_grant [1])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .lut_mask = 64'h0000000000030003;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y35_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout  = ( !\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .lut_mask = 64'hFFFFFFFF00000000;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y35_N38
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y35_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout  & ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q 
//  & \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout  & ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q 
//  & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout ) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]))) ) ) ) # ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout  & ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q  ) ) ) # ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout  & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q  ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout ),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),
        .datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout ),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .lut_mask = 64'h0F0F0F0F44550055;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y35_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~1_combout  & ( 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ))) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~1_combout  & ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .lut_mask = 64'hCCCCCCCCCCC0CCC0;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y35_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & ( 
// ((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) 
// # (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout )))) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ) 
// ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .lut_mask = 64'h0000000055DF55DF;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y35_N32
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y35_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & ( 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  $ 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) # 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) ) # ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .lut_mask = 64'hC000C0003CC03CC0;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y35_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q 
//  & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  ) ) ) # ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) # 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ) ) ) # ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout  & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout  & 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q )) ) ) ) # ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) # ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout  & 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout  & \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout ),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout ),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'hFF080808FF0F0F0F;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y35_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout  & ( 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout 
// ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h000000000F000F00;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y35_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q 
//  & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .lut_mask = 64'h0000000044444444;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y35_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout  = ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout  & ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout  & ( 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ) ) ) ) # ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout  & ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout  & ( 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ) ) ) ) # ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout  & ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout  & ( 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ) ) ) ) # ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout  & ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout  & ( 
// ((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout  & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout ) # 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout )))) # 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout ),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),
        .datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .lut_mask = 64'h45FF55FF55FF55FF;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y35_N14
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y35_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & ( 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ) # 
// ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h00000000C888C888;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y34_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & ( !\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & ( (!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]) # (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
        .datac(gnd),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .lut_mask = 64'hFFCCFFCCCCCCCCCC;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y34_N47
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .power_up = "low";
// synopsys translate_on

// Location: FF_X23_Y35_N23
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";
// synopsys translate_on

// Location: FF_X23_Y35_N32
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X23_Y35_N41
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y35_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~2_combout  = ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & ( 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1])) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~2 .lut_mask = 64'hA000A00000000000;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y35_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~3 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~3_combout  = (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & 
// (((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q  & \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~2_combout )) # 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout )))

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout ),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~2_combout ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~3 .lut_mask = 64'h22A222A222A222A2;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y35_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~3_combout  & ( 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ) # 
// ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~3_combout  & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .lut_mask = 64'h0F000F000A0A0A0A;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y35_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & ( 
// \u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout  & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  & ((!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]) # 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q 
//  & ( \u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout  & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  ) ) ) # ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & ( !\u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout  & ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  ) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & 
// ( !\u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout  & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
        .datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .lut_mask = 64'hFF00FF00FF00AF00;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y35_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & ( 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) # 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .lut_mask = 64'h000000003F303F30;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y35_N17
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y35_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout  & ( 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// ((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout )))) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & 
// (((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout 
// )) # (\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]))) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout  & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .lut_mask = 64'h0033003305370537;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y35_N53
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y35_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout  & ( 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]) # (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ) ) # ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout  & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # 
// ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout ),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hFF0AFF0AFFAAFFAA;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y35_N5
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y35_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout  = ( \u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & ( 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] $ 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])))) # 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0])) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & ( 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] $ 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .lut_mask = 64'h30C030C03ACA3ACA;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y35_N56
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y35_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout  = ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) 
// # ((\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout )) ) ) ) # ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout )) ) ) ) # ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg 
// [3] & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & ( 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) # 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ))) ) ) ) # ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  
// & (((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .lut_mask = 64'h01ABAB010101ABAB;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y35_N44
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y35_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] ) ) # ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] $ 
// (((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg 
// [2]))) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .lut_mask = 64'hA6A6A6A6AAAAAAAA;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y35_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout  = ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  & ( 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # ((\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .lut_mask = 64'hAABBAABB00110011;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y35_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  = ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & 
// ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg 
// [2] & !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .lut_mask = 64'h0C000C0000000000;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y35_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout  = ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) # 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ))) ) ) # ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) # 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .lut_mask = 64'h01AB01ABAB01AB01;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y35_N1
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .power_up = "low";
// synopsys translate_on

// Location: FF_X22_Y35_N8
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y35_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout  = ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( \u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & ( 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ) # 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q 
//  & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout )) ) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( 
// \u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout 
// )))) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout )) ) ) ) # ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( !\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & ( 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ) # 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) ) ) ) # ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( !\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & ( 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] 
// & \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .lut_mask = 64'h00A0AA0A11B1BB1B;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y35_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout  = ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout  & ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  ) ) # ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout  & ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  ) ) # ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout  & ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  & ( 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout  & 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout  & 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout  & 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),
        .datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .lut_mask = 64'h00008000FFFFFFFF;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y35_N20
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y35_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  = ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ) ) # 
// ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & 
// ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) # 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & (((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q )))) 
// ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .lut_mask = 64'h7430743030303030;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y35_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  = ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout 
//  & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~1_combout  & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// (((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )))) # 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout )))) ) ) ) # ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~1_combout  & ( 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q 
// ) ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .lut_mask = 64'h3F3F00002E0C0000;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y35_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout  = ( \u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & ( 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  & 
// \u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout )) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h0000000000300030;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y35_N5
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y35_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout  = ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) # 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q )))) ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0 .lut_mask = 64'h8880000000000000;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y35_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|write~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|write~0_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout  & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~0_combout  ) ) # ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout  & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~0_combout  & \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~0_combout ),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|write~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|write~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h000F000F0F0F0F0F;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|write~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y35_N41
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][129] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][129]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y35_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~1_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~0_combout  & ( ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][129]~q )) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout ) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~0_combout  & ( 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][129]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout ),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][129]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h005500550F5F0F5F;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y35_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout  & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0]) # 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout ) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout  & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0] ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hAAAAAAAAFAFAFAFA;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y35_N11
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][129] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][129]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y35_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|comb~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|comb~0_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0] & ( ((\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0]) # 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][129]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0]),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|comb~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|comb~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|comb~0 .lut_mask = 64'h000000003FFF3FFF;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|comb~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y35_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|comb~0_combout  & ( \u0|hps_0|fpga_interfaces|h2f_RREADY [0] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|comb~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y35_N23
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_busy (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";
// synopsys translate_on

// Location: FF_X25_Y35_N2
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][76] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][76]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y35_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~5 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~5_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4])) # 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][76]~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][76]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][76]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h003300330C3F0C3F;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y35_N29
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][76] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~5_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][76]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";
// synopsys translate_on

// Location: FF_X25_Y35_N47
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][75] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][75]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y35_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~6 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~6_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) # 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][75]~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][75]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][75]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h005500550A5F0A5F;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y35_N56
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][75] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~6_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";
// synopsys translate_on

// Location: FF_X25_Y35_N5
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][77] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][77]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y35_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~4 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~4_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])) # 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][77]~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][77]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][77]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~4 .lut_mask = 64'h003300330C3F0C3F;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y35_N59
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][77] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~4_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][77]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";
// synopsys translate_on

// Location: FF_X25_Y35_N44
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][74] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~7_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][74]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y35_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~7 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~7_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) # 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][74]~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & 
// ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][74]~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][74]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h0A5F0A5F22772277;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y35_N5
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~7_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";
// synopsys translate_on

// Location: FF_X30_Y35_N11
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][78] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][78]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y35_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~3 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~3_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][78]~q  & ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][78]~q  & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]) ) ) ) # ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][78]~q  & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][78]~q ),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h000033330C0C3F3F;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y35_N35
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][78] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~3_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][78]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y35_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~0_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74]~q  & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][78]~q  & ( 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q  & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][76]~q  & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][75]~q  & 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][77]~q ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][77]~q ),
        .datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][78]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h0000800000000000;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y35_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout  & 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout  & 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) ) ) # ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout  & 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][75]~q  $ (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ))) ) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & 
// ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout  & 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][75]~q  $ (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h2121212133000033;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y35_N44
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y35_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~0_combout  = ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][76]~q  & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74]~q  & 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][77]~q  & !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][75]~q )) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][77]~q ),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~0 .lut_mask = 64'hA000A00000000000;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y35_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~0_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4] ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2] $ (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4]) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h66666666CCCCCCCC;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y35_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout  & ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][76]~q  & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][75]~q )) # 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ))) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~0_combout )))) ) ) ) # ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout  & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][76]~q  
// & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74]~q  & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][75]~q 
// )))) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~0_combout )))) ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~0_combout ),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h0000A0CC00005FCC;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y35_N14
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y35_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~2 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~2_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [5] ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [5] $ (((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h3CF03CF0F0F0F0F0;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y35_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~1_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][76]~q  & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][77]~q  ) ) # ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][76]~q  & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][77]~q  $ (((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][75]~q  & 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][77]~q ),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h5AF05AF0F0F0F0F0;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y35_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~2_combout  & \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout ) ) ) # ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout  & 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~1_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~2_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h0F000F000A0A0A0A;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y35_N41
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y35_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~1_combout  = ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [5])) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~1 .lut_mask = 64'h8080808000000000;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y35_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~1_combout  & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout  & 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][78]~q  $ (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~0_combout 
// )))) ) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~1_combout  & ( 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][78]~q  $ (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~0_combout )) # 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~1_combout  & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][78]~q  $ 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~0_combout )) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~1_combout  & ( 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout  & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][78]~q  $ (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~0_combout )))) ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][78]~q ),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~0_combout ),
        .datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h1020132313231020;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y35_N50
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y35_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout  = ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [5])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'hC000C00000000000;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y35_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout  & ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~1_combout  & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][78]~q 
//  & (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~0_combout ))) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6])))) ) ) ) # ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout  & ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~1_combout  & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][78]~q  & (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~0_combout  & 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][78]~q ),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~0_combout ),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h00002200000022F0;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y35_N20
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y35_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [7] & ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q  ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [7] & ( 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q  & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout ) # 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h5151515155555555;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y35_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout  & !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74]~q  & 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout  & !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h2020202030303030;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y35_N8
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y35_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~2 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h0000000000FF00FF;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y35_N47
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";
// synopsys translate_on

// Location: FF_X27_Y35_N13
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~2_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][66]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y35_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~2 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~2_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][66]~q  ) ) # ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][66]~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~2 .lut_mask = 64'h555555550F0F0F0F;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y35_N50
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~2_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][66]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y35_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|comb~0_combout  & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~0_combout  & 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][66]~q  & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout ) # (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout 
// )))) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|comb~0_combout  & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][66]~q  ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][66]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|comb~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h00FF00FF00A800A8;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y35_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[1]~0_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout  & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|write~0_combout  & 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout )))) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|write~0_combout  & 
// ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout  & (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1])) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout  & 
// ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0]))))) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout  & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|write~0_combout  & 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1])) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|write~0_combout  & ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0]))) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|write~0_combout ),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0]),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[1]~0 .lut_mask = 64'h4747474711471147;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[1]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y35_N38
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y35_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[0]~1_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout  & ( ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0] & 
// ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout ) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1])))) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|write~0_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout  & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0]) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|write~0_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|write~0_combout ),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h33FF33FF337F337F;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y35_N35
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y35_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout  = ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0] & 
// ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0]) # (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][129]~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid .lut_mask = 64'hFA00FA0000000000;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y34_N26
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~20_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][116]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y32_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_021|src_payload~11 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_021|src_payload~11_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [11] & ( \u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_021|src_payload~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~11 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~11 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y32_N34
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_021|src_payload~11_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y34_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~20 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~20_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][116]~q  & ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][116]~q  & ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] ) ) ) # ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][116]~q  & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] & ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][116]~q ),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~20 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~20 .lut_mask = 64'h00003333CCCCFFFF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~20 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y34_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][116]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][116]~feeder_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~20_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~20_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][116]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][116]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][116]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][116]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y34_N5
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][116]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][116]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";
// synopsys translate_on

// Location: FF_X21_Y32_N41
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~20_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][116]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y32_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_020|src_payload~11 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_020|src_payload~11_combout  = ( \u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [11] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_020|src_payload~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~11 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~11 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y32_N25
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_020|src_payload~11_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y32_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~20 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~20_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] & ( 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][116]~q ) ) ) # ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][116]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][116]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~20 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~20 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~20 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y32_N47
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~20_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][116]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y31_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal14~0 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal14~0_combout  = (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & !\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]))

        .dataa(gnd),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router_001|Equal14~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal14~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal14~0 .lut_mask = 64'h0C000C000C000C00;
defparam \u0|mm_interconnect_0|router_001|Equal14~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y31_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal14~1 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal14~1_combout  = ( \u0|mm_interconnect_0|router_001|Equal1~1_combout  & ( (\u0|mm_interconnect_0|router_001|Equal1~0_combout  & (\u0|mm_interconnect_0|router_001|Equal1~2_combout  & 
// (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & \u0|mm_interconnect_0|router_001|Equal14~0_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),
        .datab(!\u0|mm_interconnect_0|router_001|Equal1~2_combout ),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),
        .datad(!\u0|mm_interconnect_0|router_001|Equal14~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router_001|Equal14~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal14~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal14~1 .lut_mask = 64'h0000000000100010;
defparam \u0|mm_interconnect_0|router_001|Equal14~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y31_N53
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[8] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|router_001|Equal14~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [8]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[8] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y31_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|src8_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|src8_valid~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [8] & ( \u0|hps_0|fpga_interfaces|h2f_ARVALID [0] ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel 
// [8] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q  & \u0|hps_0|fpga_interfaces|h2f_ARVALID [0]) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [8]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux_001|src8_valid~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|src8_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|src8_valid~0 .lut_mask = 64'h00AA00AA00FF00FF;
defparam \u0|mm_interconnect_0|cmd_demux_001|src8_valid~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y31_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|src8_valid~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|src8_valid~1_combout  = ( \u0|mm_interconnect_0|router_001|Equal14~0_combout  & ( \u0|mm_interconnect_0|cmd_demux_001|src8_valid~0_combout  & ( (\u0|mm_interconnect_0|router_001|Equal1~2_combout  & 
// (\u0|mm_interconnect_0|router_001|Equal1~1_combout  & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & \u0|mm_interconnect_0|router_001|Equal1~0_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|router_001|Equal1~2_combout ),
        .datab(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),
        .datad(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),
        .datae(!\u0|mm_interconnect_0|router_001|Equal14~0_combout ),
        .dataf(!\u0|mm_interconnect_0|cmd_demux_001|src8_valid~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux_001|src8_valid~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|src8_valid~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|src8_valid~1 .lut_mask = 64'h0000000000000010;
defparam \u0|mm_interconnect_0|cmd_demux_001|src8_valid~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y25_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|arb|grant[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|arb|grant[1]~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg [0] & ( \u0|mm_interconnect_0|cmd_demux|src8_valid~1_combout  & ( (\u0|mm_interconnect_0|cmd_demux_001|src8_valid~1_combout  & 
// \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg [1]) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg [0] & ( \u0|mm_interconnect_0|cmd_demux|src8_valid~1_combout  & ( (\u0|mm_interconnect_0|cmd_demux_001|src8_valid~1_combout  & 
// \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg [1]) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg [0] & ( !\u0|mm_interconnect_0|cmd_demux|src8_valid~1_combout  & ( (\u0|mm_interconnect_0|cmd_demux_001|src8_valid~1_combout  & 
// \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg [1]) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg [0] & ( !\u0|mm_interconnect_0|cmd_demux|src8_valid~1_combout  & ( \u0|mm_interconnect_0|cmd_demux_001|src8_valid~1_combout  ) ) 
// )

        .dataa(!\u0|mm_interconnect_0|cmd_demux_001|src8_valid~1_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg [1]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg [0]),
        .dataf(!\u0|mm_interconnect_0|cmd_demux|src8_valid~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_008|arb|grant[1]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|arb|grant[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|arb|grant[1]~0 .lut_mask = 64'h5555050505050505;
defparam \u0|mm_interconnect_0|cmd_mux_008|arb|grant[1]~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y24_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y24_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~4_combout  & ( 
// (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~4_combout  & ( ((\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & 
// !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0])) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~4_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 .lut_mask = 64'h5F555F550F000F00;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y24_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout  = ( 
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout  & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg 
// [2] $ (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) 
// ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout  & ( 
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] $ 
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 .lut_mask = 64'h50A050A05FAF5FAF;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y24_N5
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";
// synopsys translate_on

// Location: FF_X13_Y24_N2
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y24_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3_combout  & ( 
// ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout  & \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1])) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]) ) ) # ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3_combout  & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout  & \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5 .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y24_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout  = ( 
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout  & ( 
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] $ (((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # 
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])))) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) # ( 
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout  & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  
// & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] $ (((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # 
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))))) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6 .lut_mask = 64'h408C408C73BF73BF;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y24_N56
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y24_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] & ( 
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & 
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3])) ) ) # ( 
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] & ( ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # 
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3])) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg 
// [2]) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .lut_mask = 64'hF5FFF5FF0A000A00;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y24_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout  = ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & ( 
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout )))) # 
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout )) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & ( 
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ))) # 
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout )) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant 
// [1] & ( !\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ))) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & ( !\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & ( 
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout ),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
        .datae(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .lut_mask = 64'hCC00DD11CF03DF13;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y25_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y25_N2
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y25_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|router|Equal14~1 (
// Equation(s):
// \u0|mm_interconnect_0|router|Equal14~1_combout  = ( \u0|mm_interconnect_0|router|Equal7~1_combout  & ( (\u0|mm_interconnect_0|router|Equal14~0_combout  & (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout  & 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|router|Equal14~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout ),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|router|Equal7~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router|Equal14~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router|Equal14~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router|Equal14~1 .lut_mask = 64'h0000000050005000;
defparam \u0|mm_interconnect_0|router|Equal14~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y25_N59
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[8] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|router|Equal14~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [8]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[8] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y25_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|src8_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|src8_valid~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout  & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q ) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [8]) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [8]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux|src8_valid~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|src8_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|src8_valid~0 .lut_mask = 64'h00000000FF0FFF0F;
defparam \u0|mm_interconnect_0|cmd_demux|src8_valid~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y25_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|src_valid~0_combout  = ( \u0|mm_interconnect_0|router|Equal7~1_combout  & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout  & ( 
// (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & (\u0|mm_interconnect_0|router|Equal14~0_combout  & (\u0|mm_interconnect_0|cmd_demux|src8_valid~0_combout  & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout 
// ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|router|Equal14~0_combout ),
        .datac(!\u0|mm_interconnect_0|cmd_demux|src8_valid~0_combout ),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout ),
        .datae(!\u0|mm_interconnect_0|router|Equal7~1_combout ),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_008|src_valid~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|src_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|src_valid~0 .lut_mask = 64'h0000010000000000;
defparam \u0|mm_interconnect_0|cmd_mux_008|src_valid~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y25_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_valid~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout  = ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & ( \u0|mm_interconnect_0|cmd_demux_001|src8_valid~1_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_demux_001|src8_valid~1_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|src_valid~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|src_valid~1 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_008|src_valid~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y25_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout  = ( \u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout  & ( 
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  ) ) # ( !\u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout  & ( 
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) # (!\u0|mm_interconnect_0|cmd_mux_008|src_valid~0_combout ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_008|src_valid~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .lut_mask = 64'hFFF0FFF0F0F0F0F0;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y25_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18_combout  = ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & ( 
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ) # ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) 
// # (((!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & !\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0])) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ))) ) ) # ( 
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ) # 
// ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & 
// ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ))))) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
        .datae(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
        .datag(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18 .extended_lut = "on";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18 .lut_mask = 64'hFEEEAAAAFFFFABAB;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y25_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1_combout  = ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1 .lut_mask = 64'hFFFFFFFF00000000;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y25_N56
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y25_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_payload[0] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|src_payload [0] = ( \u0|hps_0|fpga_interfaces|h2f_WLAST [0] & ( (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_WLAST [0] & 
// ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_WLAST [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_008|src_payload [0]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|src_payload[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|src_payload[0] .lut_mask = 64'h3333333377777777;
defparam \u0|mm_interconnect_0|cmd_mux_008|src_payload[0] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y25_N32
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_008|src_payload [0]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";
// synopsys translate_on

// Location: FF_X11_Y25_N11
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y25_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  
// & ( \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~1_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h000000000000FFFF;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y25_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout  = ( 
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & ( 
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) ) ) ) # ( 
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & ( 
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) # (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) ) ) ) # 
// ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & ( 
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .lut_mask = 64'h0000FFFFFAFA5050;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y25_N2
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y25_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout  = ( 
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) # 
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] $ 
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg 
// [2] & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) # 
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] $ (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg 
// [3])) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .lut_mask = 64'h23DF23DF20DC20DC;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y25_N38
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y25_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout  = ( 
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & 
// ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) # ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # 
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ) ) # ( 
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] 
// & ( (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & 
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ) ) # ( 
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] 
// & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) # 
// ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg 
// [2]))) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg 
// [2]))) ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( 
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( 
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg 
// [2]))) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg 
// [2])))) ) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datae(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .lut_mask = 64'h00E4FF4E0044FFEE;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y25_N8
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y25_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg 
// [4] & !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h00000000A000A000;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y25_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout  = ( 
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] $ 
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout )))) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) # ( 
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] $ (((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) # 
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .lut_mask = 64'h33C333C33ACA3ACA;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y25_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout  = ( 
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout  & ( 
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout  & 
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0 .lut_mask = 64'hF000F00000000000;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y25_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout  = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  
// & (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h0100010055005500;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y25_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout  = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & ( 
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q 
// ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h0000000000F000F0;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y25_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout  = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout  & ( 
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout  ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout  & ( 
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout  ) ) # ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout  & ( 
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout  & ( ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ) # 
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout )) # 
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h0000F7F7FFFFFFFF;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y25_N29
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y25_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout  = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q )) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) # (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q )))) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h5040504050005000;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y25_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout  & ( 
// !\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout  & ( (!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & 
// !\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .lut_mask = 64'hF000F000FF00FF00;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y25_N8
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y25_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_data[34] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|src_data [34] = ((\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_WSTRB [2])) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1])

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [2]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_008|src_data [34]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[34] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[34] .lut_mask = 64'h333F333F333F333F;
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[34] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y25_N26
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_008|src_data [34]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y25_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_data[32] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|src_data [32] = ( \u0|hps_0|fpga_interfaces|h2f_WSTRB [0] & ( (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_WSTRB [0] & ( 
// \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_008|src_data [32]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[32] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[32] .lut_mask = 64'h0F0F0F0F5F5F5F5F;
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[32] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y25_N47
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_008|src_data [32]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y25_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_data[35] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|src_data [35] = ((\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_WSTRB [3])) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1])

        .dataa(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [3]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_008|src_data [35]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[35] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[35] .lut_mask = 64'h05FF05FF05FF05FF;
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[35] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y25_N38
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_008|src_data [35]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y25_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~2_combout  = ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & ( 
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & 
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~2 .lut_mask = 64'hC000C00000000000;
defparam \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y25_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_data[88] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|src_data [88] = ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & ( ((\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1])) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & ( (\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_008|src_data [88]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[88] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[88] .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[88] .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y24_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_data[87] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|src_data [87] = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & ( ((\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWSIZE [1])) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & ( (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
        .datac(gnd),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_008|src_data [87]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[87] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[87] .lut_mask = 64'h0033003355775577;
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[87] .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y25_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout  = ( !\u0|mm_interconnect_0|cmd_mux_008|src_data [87] & ( !\u0|mm_interconnect_0|cmd_mux_008|src_data [88] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_008|src_data [88]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_008|src_data [87]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .lut_mask = 64'hF0F0F0F000000000;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y25_N11
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y25_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~3 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~3_combout  = ( \u0|mm_interconnect_0|auto_start_s1_agent|local_write~0_combout  & ( (!\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout  & 
// (((\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~2_combout  & !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q )))) # (\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout  & 
// ((!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0]) # ((\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~2_combout  & 
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q )))) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent|local_write~0_combout  & ( 
// (!\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout  & (((\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~2_combout  & !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q )))) # 
// (\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout  & (((\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~2_combout  & !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q )) # 
// (\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0]))) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout ),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0]),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~2_combout ),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|local_write~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~3 .lut_mask = 64'h1F111F114F444F44;
defparam \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~3 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y25_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q  & 
// ((!\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~3_combout ) # (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1])))) ) ) # ( 
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ) # ((!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~3_combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~3_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .lut_mask = 64'h3032303230103010;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y25_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout  & ( 
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  ) ) ) # ( 
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout  & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( 
// (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  & ((!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]) # 
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout )))) ) ) ) # ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout  & ( 
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  ) ) ) # ( 
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout  & ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( 
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  & ((!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]) # 
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
        .datae(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .lut_mask = 64'hF500FF003100FF00;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y24_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~1_combout  & ( 
// ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout  & \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1])) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]) ) ) # ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~1_combout  & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout  & \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 .lut_mask = 64'h0303030303FF03FF;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y24_N46
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y24_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  = ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] & ( 
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & 
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .lut_mask = 64'h0A000A0000000000;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y24_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout  = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  & ( 
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) # 
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout )) ) 
// ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout )) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 .lut_mask = 64'h03CF03CFCF03CF03;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y24_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout 
//  ) ) # ( !\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout  & ( (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~0_combout ) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout  & ( 
// (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~0_combout ) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout  & ( (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~0_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~0_combout ),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .lut_mask = 64'h111111111111FFFF;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y24_N44
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y24_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout  = ( 
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]))) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout )) ) ) # ( 
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  $ (((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]))))) # 
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout 
// )))) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 .lut_mask = 64'h478B478B03CF03CF;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y24_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout  = ( 
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout  & ( 
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout  & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  
// ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout  & ( 
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout  & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  
// ) ) ) # ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout  & ( 
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout  & ( 
// ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout  & 
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout  & 
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ))) # 
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) ) # ( 
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout  & ( 
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout  & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout 
//  ) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout ),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ),
        .datae(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .lut_mask = 64'h0F0F8F0F0F0F0F0F;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y24_N8
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y25_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  = ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( 
// ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & 
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) ) ) # ( 
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # 
// ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~1_combout ))))) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datae(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~1_combout ),
        .datag(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .extended_lut = "on";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .lut_mask = 64'h0C00F0F00C00F5F5;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y25_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout  = ( \u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout  & ( 
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ) # 
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ))) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout  & ( 
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & (\u0|mm_interconnect_0|cmd_mux_008|src_valid~0_combout  & 
// ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_008|src_valid~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h0007000707070707;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y25_N20
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y25_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  = ( \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout  & ( 
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # 
// ((!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ((!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0]) # (\u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout )))) ) ) ) # ( 
// !\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout  & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] & ( 
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # ((!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout )) ) ) 
// ) # ( \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout  & ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] & ( 
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # ((!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout ) # 
// (\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0])))) ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout  & ( 
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # 
// ((!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0]),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout ),
        .datae(!\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout ),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hAAFABAFAAAFAEAFA;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y24_N20
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on

// Location: FF_X11_Y25_N19
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y25_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout  = ( 
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( 
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) # 
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  
// & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg 
// [6] & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  & 
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  
// & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) ) # ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg 
// [6] & ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) # ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) # 
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) ) ) # ( 
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( 
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  
// & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])) 
// ) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datae(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 .lut_mask = 64'h3000CFFF3A0ACAFA;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y25_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout  = ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( 
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .lut_mask = 64'hF0F0F0F000000000;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y25_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout  = ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & ( 
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ) # 
// ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ) # 
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & ( 
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & ( (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & ( 
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & ( (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & ( 
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & ( (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datae(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .lut_mask = 64'h003300330033F0FB;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y25_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout  = ( !\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & ( 
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout  & (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout )) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16 .lut_mask = 64'h0500050000000000;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y25_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout  = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & ( 
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q 
// )))) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & ( 
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .lut_mask = 64'h000A000A020A020A;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y25_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & ( 
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .lut_mask = 64'h000000000C0C0C0C;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y25_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17_combout  = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  & ( 
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout  ) ) # ( 
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  & ( 
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout  & ( 
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout  ) ) ) # ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  & ( 
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout  ) ) # ( 
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  & ( 
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout  & ( 
// ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout  & 
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout  & \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ))) # 
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout ),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),
        .datae(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17 .lut_mask = 64'h0F2FFFFF0F0FFFFF;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y25_N50
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y25_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q )) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  $ 
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ))) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q )) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .lut_mask = 64'hC03CC03C00C000C0;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y25_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout  = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  & ( 
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  & ( 
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) # 
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .lut_mask = 64'h1155115500440044;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y25_N50
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y25_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & ( 
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) # 
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'h000000000AAA0AAA;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y25_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|packet_in_progress~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|packet_in_progress~0_combout  = ( !\u0|mm_interconnect_0|cmd_mux_008|update_grant~0_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_008|update_grant~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_008|packet_in_progress~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|packet_in_progress~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|packet_in_progress~0 .lut_mask = 64'hFFFFFFFF00000000;
defparam \u0|mm_interconnect_0|cmd_mux_008|packet_in_progress~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y25_N35
dffeas \u0|mm_interconnect_0|cmd_mux_008|packet_in_progress (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_008|packet_in_progress~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_008|packet_in_progress~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|packet_in_progress .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_008|packet_in_progress .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y25_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|update_grant~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|update_grant~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_008|src_valid~0_combout  & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & ( 
// \u0|mm_interconnect_0|cmd_mux_008|src_payload [0] ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_008|src_valid~0_combout  & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & ( 
// (!\u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout  & ((!\u0|mm_interconnect_0|cmd_mux_008|packet_in_progress~q ))) # (\u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout  & (\u0|mm_interconnect_0|cmd_mux_008|src_payload [0])) ) ) ) # ( 
// \u0|mm_interconnect_0|cmd_mux_008|src_valid~0_combout  & ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & ( 
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & \u0|mm_interconnect_0|cmd_mux_008|src_payload [0]) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_008|src_valid~0_combout  & ( 
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & ( (!\u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout  & (((!\u0|mm_interconnect_0|cmd_mux_008|packet_in_progress~q )))) # 
// (\u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout  & (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & (\u0|mm_interconnect_0|cmd_mux_008|src_payload [0]))) ) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_008|src_payload [0]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_008|packet_in_progress~q ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout ),
        .datae(!\u0|mm_interconnect_0|cmd_mux_008|src_valid~0_combout ),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_008|update_grant~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|update_grant~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|update_grant~0 .lut_mask = 64'hF0111111F0333333;
defparam \u0|mm_interconnect_0|cmd_mux_008|update_grant~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y25_N41
dffeas \u0|mm_interconnect_0|cmd_mux_008|saved_grant[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_008|arb|grant[1]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|cmd_mux_008|update_grant~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|saved_grant[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_008|saved_grant[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X15_Y25_N28
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";
// synopsys translate_on

// Location: FF_X18_Y25_N20
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][66]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y25_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~3 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~3_combout  = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][66]~q  ) ) # ( 
// !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][66]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y25_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66]~feeder_combout  = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~3_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y25_N56
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y25_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|m0_read~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent|m0_read~0_combout  = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & ( 
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_agent|m0_read~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|m0_read~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|m0_read~0 .lut_mask = 64'h0000000055FF55FF;
defparam \u0|mm_interconnect_0|auto_start_s1_agent|m0_read~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y25_N26
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][129] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][129]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y25_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~0_combout  = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][129]~q  & ( \u0|mm_interconnect_0|auto_start_s1_agent|local_write~0_combout  & ( 
// (((\u0|mm_interconnect_0|auto_start_s1_agent|m0_read~0_combout  & \u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout )) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout )) # 
// (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][129]~q  & ( \u0|mm_interconnect_0|auto_start_s1_agent|local_write~0_combout  & ( 
// (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & (((\u0|mm_interconnect_0|auto_start_s1_agent|m0_read~0_combout  & \u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout )) # 
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ))) ) ) ) # ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][129]~q  & ( 
// !\u0|mm_interconnect_0|auto_start_s1_agent|local_write~0_combout  & ( ((\u0|mm_interconnect_0|auto_start_s1_agent|m0_read~0_combout  & \u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout )) # 
// (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][129]~q  & ( !\u0|mm_interconnect_0|auto_start_s1_agent|local_write~0_combout  & ( 
// (\u0|mm_interconnect_0|auto_start_s1_agent|m0_read~0_combout  & (\u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout  & !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1])) ) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_agent|m0_read~0_combout ),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout ),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datae(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][129]~q ),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|local_write~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~0 .lut_mask = 64'h10101F1F10F01FFF;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y25_N38
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][129] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][129]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y25_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|comb~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent|comb~0_combout  = ( \u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [0] ) ) # ( 
// !\u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg [0] & ( (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [0] & ((\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][129]~q ) # 
// (\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used [0]))) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [0]),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_agent|comb~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|comb~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|comb~0 .lut_mask = 64'h050F050F0F0F0F0F;
defparam \u0|mm_interconnect_0|auto_start_s1_agent|comb~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y25_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout  = ( \u0|hps_0|fpga_interfaces|h2f_BREADY [0] & ( \u0|mm_interconnect_0|auto_start_s1_agent|comb~0_combout  & ( (\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ) # 
// (\u0|hps_0|fpga_interfaces|h2f_RREADY [0]) ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_BREADY [0] & ( \u0|mm_interconnect_0|auto_start_s1_agent|comb~0_combout  & ( (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & 
// !\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ) ) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ),
        .datad(gnd),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_BREADY [0]),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|comb~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0 .lut_mask = 64'h0000000050505F5F;
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y25_N32
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][74] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][74]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y25_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~5 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~5_combout  = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) # 
// (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][74]~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & 
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) # (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][74]~q 
// ))) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][74]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h447744770C3F0C3F;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y25_N14
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~5_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";
// synopsys translate_on

// Location: FF_X17_Y25_N53
dffeas \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_busy (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y25_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~2 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~2_combout  = ( \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_busy~q  & ( \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter 
// [2] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h0000000000FF00FF;
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y25_N35
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][77] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][77]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y25_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~8 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~8_combout  = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])) # 
// (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][77]~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][77]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][77]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~8 .lut_mask = 64'h003300330C3F0C3F;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y25_N29
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~8_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";
// synopsys translate_on

// Location: FF_X14_Y25_N41
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][75] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][75]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y25_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~6 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~6_combout  = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( 
// (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) # 
// (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][75]~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][75]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][75]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h005500550A5F0A5F;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y25_N41
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~6_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";
// synopsys translate_on

// Location: FF_X11_Y25_N47
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][76] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~7_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][76]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y25_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~7 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~7_combout  = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4])) # 
// (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][76]~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][76]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][76]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h003300330C3F0C3F;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y25_N23
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~7_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y25_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~0_combout  = (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77]~q  & (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q  & 
// (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75]~q  & !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76]~q )))

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77]~q ),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~0 .lut_mask = 64'h8000800080008000;
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y25_N44
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][78] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~9_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][78]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y25_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~9 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~9_combout  = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( 
// (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) # 
// (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][78]~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][78]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][78]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~9 .lut_mask = 64'h003300330C3F0C3F;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~9 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y25_N17
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][78] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~9_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][78]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y25_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout  = ( \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75]~q  & ( (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// ((\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q ))) # (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75]~q  & ( (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// ((\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q ))) # (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ) # ( \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75]~q  & ( (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// ((!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q ))) # (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75]~q  & ( (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// ((!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q ))) # (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout ),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datae(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h0E040B01040E010B;
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y25_N32
dffeas \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y25_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~0_combout  = ( \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter 
// [2] & !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3]) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( 
// (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3]) # (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h3F3F3F3FC0C0C0C0;
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y25_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout  = ( \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout  & ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75]~q  & ( 
// (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ((\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76]~q ))) # 
// (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~0_combout )) ) ) ) # ( 
// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout  & ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75]~q  & ( (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// ((!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76]~q  $ (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q )))) # (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~0_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~0_combout ),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datae(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout ),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h0000E22E00002E2E;
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y25_N44
dffeas \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y25_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~1_combout  = ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter 
// [5] & (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2])) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~1 .lut_mask = 64'h8080808000000000;
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y25_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout  = ( \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( 
// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~1_combout  & ( (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout 
//  & (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~0_combout  $ (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][78]~q )))) ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( 
// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~1_combout  & ( (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~0_combout  $ 
// (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][78]~q )) # (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( 
// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~1_combout  & ( (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout  & 
// ((!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~0_combout  $ (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][78]~q )) # (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # 
// ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~1_combout  & ( 
// (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout  & (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~0_combout 
//  $ (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][78]~q )))) ) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~0_combout ),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][78]~q ),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout ),
        .datae(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h0060006F006F0060;
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y25_N26
dffeas \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y25_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout  = ( \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout  & ( \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~1_combout  
// & ( (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (((!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][78]~q  & \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~0_combout )))) # 
// (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6])) ) ) ) # ( 
// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout  & ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~1_combout  & ( (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][78]~q  & 
// (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~0_combout  & !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][78]~q ),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~0_combout ),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datae(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout ),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h00000C0000000CAA;
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y25_N50
dffeas \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y25_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  = ( \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_busy~q  & ( 
// ((!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~1_combout ) # (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2])) # 
// (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [7]) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h00000000F7F7F7F7;
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y25_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout  = ( \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( 
// (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout  & !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~2_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q  & (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout  & 
// !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~2_combout )) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout ),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h0C000C000F000F00;
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y25_N59
dffeas \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y25_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~2 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~2_combout  = ( \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter 
// [5] ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [5] $ 
// (((!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4]))) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h6A6A6A6AAAAAAAAA;
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y25_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~1_combout  = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q  & ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77]~q  ) ) # ( 
// !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q  & ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77]~q  $ (((!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75]~q  & 
// !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76]~q ))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77]~q ),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h3CF03CF0F0F0F0F0;
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y25_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout  = ( \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( 
// (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout  & !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~2_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout  & !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~1_combout 
// ) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~2_combout ),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h5500550050505050;
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y25_N5
dffeas \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y25_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~1 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~1_combout  = ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( 
// (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & 
// !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3])) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'h8080808000000000;
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y25_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~0_combout  = ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76]~q  & ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][78]~q  & ( 
// (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_busy~q  & (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q  & (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77]~q  & 
// !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75]~q ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77]~q ),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datae(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76]~q ),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][78]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h2000000000000000;
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y25_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout  = ( \u0|mm_interconnect_0|auto_start_s1_agent|comb~0_combout  & ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66]~q  & ( 
// (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~0_combout  & ((!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~1_combout ) # 
// (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~2_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent|comb~0_combout  & ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66]~q  ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|auto_start_s1_agent|comb~0_combout ),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h00000000FFFFC8C8;
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y25_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[0]~1_combout  = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [0] & ( \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout  ) ) # ( 
// !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [0] & ( \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout  & ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|write~0_combout  ) ) ) # ( 
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [0] & ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout  & ( ((!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout ) # 
// (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1])) # (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|write~0_combout ) ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [0] & ( 
// !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout  & ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|write~0_combout  ) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|write~0_combout ),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout ),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [0]),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h5555DFDF5555FFFF;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y25_N5
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y25_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout  = ( \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout  & ( (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [0]) # 
// (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout  & ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [0] ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [0]),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout ),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hAAAAAAAAEEEEEEEE;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y25_N50
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";
// synopsys translate_on

// Location: FF_X18_Y25_N11
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][68] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~2_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][68]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][68] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][68] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y25_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~2 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~2_combout  = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] & ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ( 
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][68]~q  ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] & ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used 
// [1] & ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][68]~q  ) ) ) # ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] & ( 
// !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][68]~q ),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~2 .lut_mask = 64'h0000FFFF33333333;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y25_N56
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][68] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~2_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][68]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][68] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][68] .power_up = "low";
// synopsys translate_on

// Location: FF_X18_Y25_N59
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][69] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][69]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][69] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y25_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~1 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~1_combout  = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][69]~q  & ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] ) ) # ( 
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][69]~q  & ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] ) ) 
// ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][69]~q  & ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg 
// [69] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][69]~q ),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h0F0F0F0F0000FFFF;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y25_N44
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][69] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][69]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][69] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y25_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_008|src0_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout  = ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][69]~q  & ( (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66]~q  & 
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][68]~q ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66]~q ),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][68]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][69]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_008|src0_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_008|src0_valid~0 .lut_mask = 64'h00F000F000000000;
defparam \u0|mm_interconnect_0|rsp_demux_008|src0_valid~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y25_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|rp_valid (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout  = ( !\u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg [0] & ( (!\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used [0] & 
// ((!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [0]) # (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][129]~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used [0]),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|rp_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|rp_valid .lut_mask = 64'hF0A0F0A000000000;
defparam \u0|mm_interconnect_0|auto_start_s1_agent|rp_valid .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y31_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal7~0 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal7~0_combout  = (\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & !\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]))

        .dataa(gnd),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router_001|Equal7~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal7~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal7~0 .lut_mask = 64'h3000300030003000;
defparam \u0|mm_interconnect_0|router_001|Equal7~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y31_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal8~0 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal8~0_combout  = ( \u0|mm_interconnect_0|router_001|Equal7~0_combout  & ( (\u0|mm_interconnect_0|router_001|Equal2~0_combout  & (\u0|mm_interconnect_0|router_001|Equal1~0_combout  & 
// \u0|mm_interconnect_0|router_001|Equal1~1_combout )) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|router_001|Equal2~0_combout ),
        .datac(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),
        .datad(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|router_001|Equal7~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router_001|Equal8~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal8~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal8~0 .lut_mask = 64'h0000000000030003;
defparam \u0|mm_interconnect_0|router_001|Equal8~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y31_N46
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[19] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|router_001|Equal8~0_combout ),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [19]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[19] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[19] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y38_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_019|last_cycle~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout  = ( \u0|mm_interconnect_0|router_001|Equal8~0_combout  & ( (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [19]))) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [19]),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|router_001|Equal8~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_019|last_cycle~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_019|last_cycle~0 .lut_mask = 64'h000000000F050F05;
defparam \u0|mm_interconnect_0|cmd_mux_019|last_cycle~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y36_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y38_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y38_N29
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y38_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout  = ( \u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout  & ( (\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & 
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout  & \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q )) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h0000000000440044;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y38_N38
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y36_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override~feeder (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y36_N11
dffeas \u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override .power_up = "low";
// synopsys translate_on

// Location: FF_X25_Y36_N29
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y38_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout  & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout  & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] 
// & (\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout  & \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout ),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'h000A000A00AA00AA;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y36_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout  = !\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .lut_mask = 64'hCCCCCCCCCCCCCCCC;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y36_N50
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";
// synopsys translate_on

// Location: FF_X25_Y38_N17
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y38_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( 
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q  & ( (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q  & 
// (((!\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout  & !\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout )) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]))) ) ) ) # ( 
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q  ) ) # ( 
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q  & ( 
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q  & (((!\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout  & !\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout )) # 
// (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]))) ) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout ),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout ),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .datae(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .lut_mask = 64'h000000D5FFFF00D5;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y38_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout  = ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( 
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) # (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .lut_mask = 64'hFFF0FFF000000000;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y38_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout  & ( (!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & 
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout )))) # 
// (\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & (((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout )) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout  & ( (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .lut_mask = 64'h0033003305370537;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y38_N11
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .power_up = "low";
// synopsys translate_on

// Location: FF_X25_Y36_N13
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y36_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & ( 
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]) ) ) # ( 
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & ( (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & 
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1])) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0 .lut_mask = 64'h1010101030303030;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y36_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter~0_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override~q  & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout  & 
// (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0_combout  & !\u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter [0])) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0_combout ),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter~0 .lut_mask = 64'h000000000A000A00;
defparam \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y36_N23
dffeas \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y36_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout  = (\u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override~q  & \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter [0])

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override~q ),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter [0]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0 .lut_mask = 64'h000F000F000F000F;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y38_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & ( 
// (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout ) # (\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout ))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout ),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h0000000030F030F0;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y36_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg 
// [2] & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) # 
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) ) ) # 
// ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) # 
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) 
// )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .lut_mask = 64'h55AF55AF50AA50AA;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y36_N44
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on

// Location: FF_X22_Y36_N20
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y36_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg 
// [2] & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) # 
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] $ 
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & 
// ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) # 
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] $ (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) # 
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .lut_mask = 64'h31DF31DF20CE20CE;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y36_N35
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y36_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout  = ( 
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( 
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) # 
// ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) # (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg 
// [2])) ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( 
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg 
// [2])) ) ) ) # ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( 
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( 
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) # 
// ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) # 
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) ) # ( 
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( 
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) # 
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))))) ) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datae(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .lut_mask = 64'h0D08F7F20500FFFA;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y36_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  = ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( 
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & 
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h00A000A000000000;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y36_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg 
// [2] & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  $ 
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & 
// ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  $ 
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])) # 
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .lut_mask = 64'h1BF51BF50AE40AE4;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y36_N32
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";
// synopsys translate_on

// Location: FF_X22_Y36_N56
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y36_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout  = ( 
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  & ( 
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) # 
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # 
// ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )))) ) ) ) # ( 
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  & ( 
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) 
// # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & 
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ))) ) ) ) # ( 
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  & ( 
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) # ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # 
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ) ) # ( 
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  & ( 
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & 
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datae(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .lut_mask = 64'h0404FEFEAE0454FE;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y36_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout  = ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout  
// & ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout  & ( 
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout  & 
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout  & 
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout )) ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),
        .datae(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .lut_mask = 64'hC000000000000000;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y38_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout  & ( 
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout  & ( 
// ((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h0F4F0F4F00440044;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y38_N44
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y38_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  = ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .lut_mask = 64'hFF00FF0000000000;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y38_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout  & ( 
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h0000000010101010;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y38_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout  & ( 
// ((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout  & ( (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h004400440F4F0F4F;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y38_N41
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y38_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & ( 
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & (\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & \u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .lut_mask = 64'h0000000000050005;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y38_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  & ( 
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  & ( 
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & 
// ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .lut_mask = 64'h0045004555555555;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y38_N47
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y38_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q )) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  $ 
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ))) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q )) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .lut_mask = 64'hC03CC03C00C000C0;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y38_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q  & ( 
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & 
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q )) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q  & ( 
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h00CC00CC000C000C;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y38_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  = (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout  & 
// (\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & \u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout )))

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .lut_mask = 64'h0002000200020002;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y38_N29
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";
// synopsys translate_on

// Location: FF_X25_Y38_N59
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X25_Y38_N35
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y38_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~1_combout  = ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & ( 
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & 
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1])) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~1 .lut_mask = 64'hA000A00000000000;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y36_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout  = (!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]) # ((!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & 
// !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]))

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .lut_mask = 64'hECECECECECECECEC;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y36_N8
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y38_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~2_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout  & ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] ) ) # ( 
// !\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout  & ( (\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~1_combout  & (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & 
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q )) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~1_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~2 .lut_mask = 64'h50005000F0F0F0F0;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~2 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y38_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~2_combout  & ( 
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) # ( 
// !\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~2_combout  & ( (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .lut_mask = 64'h3030303033003300;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y38_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & ( 
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & ((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) # 
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ))) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & ( 
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .lut_mask = 64'h1111111105550555;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y38_N20
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y38_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q  & ( 
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & 
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & 
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]))) ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q  & ( 
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & 
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1])) ) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .datae(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0 .lut_mask = 64'hA000800000000000;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y36_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|write~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|write~0_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout  & ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0_combout  ) ) # ( 
// !\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout  & ( (\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout  & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout ),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0_combout ),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|write~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|write~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h1111111133333333;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|write~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y36_N41
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][75] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][75]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y36_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~6 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~6_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used 
// [1] & (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & 
// ((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][75]~q ))) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( 
// (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][75]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][75]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h0055005522772277;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y36_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~feeder_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~6_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~6_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y36_N38
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][129] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][129]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y36_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~1 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~1_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0_combout  & ( ((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][129]~q )) # (\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0_combout  & ( 
// (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][129]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout ),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][129]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h003300330F3F0F3F;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y36_N44
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][129] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][129]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y36_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg~0_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override~q  & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout  & 
// (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0_combout  & \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter [0])) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout ),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0_combout ),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg~0 .lut_mask = 64'h0000000002020202;
defparam \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y36_N32
dffeas \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y36_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|read~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|read~0_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][129]~q  & (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & 
// ((\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0]) # (\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0])))) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0] & ( 
// (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ((\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0]) # (\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0]))) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0]),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|read~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|read~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|read~0 .lut_mask = 64'h003F003F002A002A;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|read~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y15_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[1]~1_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0] & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|read~0_combout  & 
// ((\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [1]) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0]))) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0] & ( 
// (!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|read~0_combout  & \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [1]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|read~0_combout ),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0]),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[1]~1 .lut_mask = 64'h00CC00CC0CCC0CCC;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[1]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y15_N14
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y36_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[0]~0_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|read~0_combout  & ( ((\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0] & 
// \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|read~0_combout  & ( 
// ((\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [1])) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0]),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|read~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h30FF30FF0F3F0F3F;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y36_N53
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y36_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|comb~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent|comb~0_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0] & ( ((\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0]) # 
// (\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][129]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0]),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_agent|comb~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|comb~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|comb~0 .lut_mask = 64'h000000007F7F7F7F;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|comb~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y36_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_agent|comb~0_combout  & ( \u0|hps_0|fpga_interfaces|h2f_RREADY [0] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|comb~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y36_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[0]~1_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout  & ( ((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0] & 
// ((\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout ) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1])))) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|write~0_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout  & ( (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0]) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|write~0_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|write~0_combout ),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout ),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h55FF55FF557F557F;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y36_N41
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y36_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout  & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0]) # 
// (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout  & ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0]),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hCCCCCCCCFCFCFCFC;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y36_N38
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";
// synopsys translate_on

// Location: FF_X22_Y36_N38
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][78] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][78]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y36_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~3 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~3_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][78]~q  ) ) # ( 
// !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][78]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h0303030300FF00FF;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y36_N35
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][78] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~3_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][78]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";
// synopsys translate_on

// Location: FF_X22_Y36_N53
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][77] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][77]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y36_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~4 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~4_combout  = (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & 
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) 
// # (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & (((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][77]~q ))))

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][77]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~4 .lut_mask = 64'h0257025702570257;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y36_N5
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][77] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~4_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][77]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";
// synopsys translate_on

// Location: FF_X22_Y36_N50
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][74] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~7_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][74]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y36_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~7 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~7_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & 
// ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) # ((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg 
// [2])))) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & (((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][74]~q )))) ) ) # ( 
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & 
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) 
// # (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & (((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][74]~q )))) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][74]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h025702578ADF8ADF;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y36_N23
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~7_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";
// synopsys translate_on

// Location: FF_X22_Y36_N14
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][76] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][76]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y36_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~5 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~5_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][76]~q  ) ) # ( 
// !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][76]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h0303030300FF00FF;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y36_N26
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~5_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y36_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~0_combout  = ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q  & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][77]~q  & 
// (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q  & !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76]~q )) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][77]~q ),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~0 .lut_mask = 64'hC000C00000000000;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y36_N44
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_busy (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y36_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~2 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~2_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_busy~q  & ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2] ) 
// )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h0000000000FF00FF;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y36_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout  = ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~2_combout  & ( 
// (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q ) # (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout ),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h5151515100000000;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y36_N56
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y36_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~0_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4] ) ) 
// # ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3] $ 
// (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4]) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h66666666CCCCCCCC;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y36_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~0_combout  & ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q  & ( 
// (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76]~q  & (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout  & !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout )) ) ) ) # ( 
// !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~0_combout  & ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q  & ( (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout  & 
// ((\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76]~q ))) ) ) ) # ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~0_combout  & ( 
// !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q  & ( (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout  & (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76]~q  $ (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q )))) ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~0_combout  & ( 
// !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q  & ( (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76]~q  $ 
// (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q )) # (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout ),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datae(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~0_combout ),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h2133210011331100;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y36_N14
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y34_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~2 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~2_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( 
// !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [5] ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( 
// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [5] ) ) ) # ( 
// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( 
// !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [5] ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( 
// !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [5] $ 
// (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3]) ) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h5A5AAAAAAAAAAAAA;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y36_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~1_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76]~q  & ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][77]~q  ) ) # ( 
// !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76]~q  & ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][77]~q  $ (((!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q  & 
// !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][77]~q ),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h5AF05AF0F0F0F0F0;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y36_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~1_combout  & ( (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout  & 
// (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~2_combout )) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~1_combout  & ( 
// (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ) # (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~2_combout ))) 
// ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout ),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~2_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h5454545410101010;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y36_N59
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y36_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~1_combout  = ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & 
// (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [5])) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~1 .lut_mask = 64'hA000A00000000000;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y36_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( 
// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~1_combout  & ( (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout  & (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~0_combout  $ (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][78]~q )))) ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( 
// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~1_combout  & ( (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~0_combout  $ 
// (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][78]~q )) # (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( 
// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~1_combout  & ( (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout  & 
// ((!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~0_combout  $ (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][78]~q )) # (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( 
// !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~1_combout  & ( (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout  & 
// (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~0_combout  $ (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][78]~q )))) ) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~0_combout ),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout ),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][78]~q ),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datae(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h1200123312331200;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y36_N8
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y36_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout  & ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~1_combout  & ( 
// (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][78]~q  & ((\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~0_combout )))) # 
// (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (((!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6])))) ) ) ) # ( 
// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout  & ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~1_combout  & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][78]~q  & 
// (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~0_combout  & !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][78]~q ),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~0_combout ),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datae(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout ),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h00000A0000000ACC;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y36_N38
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y36_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( 
// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_busy~q  ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_busy~q 
//  & ((!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~1_combout ) # (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [7]))) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h00AF00AF00FF00FF;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y36_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q  $ 
// (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q )) # (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( 
// !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( 
// (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout  & (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q  $ 
// (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q )))) ) ) ) # ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter 
// [2] & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout  & (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q  $ 
// (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q )))) ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter 
// [2] & ( (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q  $ (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q )) # 
// (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout ),
        .datae(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h00B70084008400B7;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y36_N50
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y36_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~1 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~1_combout  = ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( 
// (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & 
// !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [5])) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'h8800880000000000;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y36_N20
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][66]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y36_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~2 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~2_combout  = (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66])) # 
// (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][66]~q )))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][66]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~2 .lut_mask = 64'h0C3F0C3F0C3F0C3F;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y36_N2
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~2_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][66]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y36_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~0_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q  & ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][78]~q  & ( 
// (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q  & (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_busy~q  & (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76]~q  & 
// !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][77]~q ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][77]~q ),
        .datae(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q ),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][78]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h0000800000000000;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y36_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout  = ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~0_combout  & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent|comb~0_combout  & 
// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][66]~q ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~0_combout  & ( (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][66]~q  & 
// ((!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~1_combout ) # ((!\u0|mm_interconnect_0|fsm_info_s1_agent|comb~0_combout ) # (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~2_combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|comb~0_combout ),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][66]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h00FE00FE00CC00CC;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y36_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[1]~0_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout  & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|write~0_combout  & 
// (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout  & ((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1])))) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|write~0_combout  & 
// ((!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout  & ((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]))) # (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout  & 
// (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0])))) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout  & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|write~0_combout  & 
// ((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]))) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|write~0_combout  & (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0])) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|write~0_combout ),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout ),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0]),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[1]~0 .lut_mask = 64'h05AF05AF01670167;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[1]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y36_N59
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y38_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & ( 
// (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout ) # (\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout ))) ) ) # ( 
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout ),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hFFFFFFFF2A2A2A2A;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y36_N47
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y38_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARLEN [0] & ( 
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] $ 
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0] & ( 
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] $ 
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])))) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1])) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .lut_mask = 64'h1DD11DD10CC00CC0;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y38_N14
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";
// synopsys translate_on

// Location: FF_X23_Y38_N32
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y38_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg 
// [3] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout  & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])))) # 
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1])) ) ) ) # ( 
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout  & ( 
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & 
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])))) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1])) ) ) ) # ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout  
// & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # 
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) ) ) # ( 
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout  & ( 
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & 
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])) ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datae(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1 .lut_mask = 64'h0C00C0CC1D11D1DD;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y38_N29
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y38_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( 
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] 
// & ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] $ (((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & 
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .lut_mask = 64'hB4B4B4B4F0F0F0F0;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y38_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  & ( 
// (\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) ) ) # ( 
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # 
// ((\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0 .lut_mask = 64'hF0F3F0F300030003;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y38_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  = ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & ( 
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & 
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4])) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .lut_mask = 64'h5000500000000000;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y38_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  & ( 
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) # 
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ))) ) ) # ( 
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 .lut_mask = 64'h01CD01CDCD01CD01;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y38_N16
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .power_up = "low";
// synopsys translate_on

// Location: FF_X23_Y38_N56
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y38_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~2 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~2_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg 
// [6] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout  & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ) # ((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) # 
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1])))) ) ) ) # ( 
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout  & ( 
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  & 
// ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1])))) ) ) ) # ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout  & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) ) ) ) # ( 
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout  & ( 
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  & (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & 
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~2 .lut_mask = 64'h5000AF005033AF33;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y38_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Equal0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Equal0~0_combout  = ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout  & ( 
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout  & 
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~2_combout ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~2_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Equal0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Equal0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Equal0~0 .lut_mask = 64'h0F000F0000000000;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Equal0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y38_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  & ( 
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout  & 
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0_combout  & \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Equal0~0_combout )) ) ) 
// # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) # 
// ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout  & 
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0_combout  & \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Equal0~0_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout ),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0_combout ),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Equal0~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .lut_mask = 64'hF0F8F0F800880088;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y38_N8
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y38_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  = ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( 
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & 
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & ((\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout ) # (\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout )))) ) ) 
// ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & ( 
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  ) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout ),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout ),
        .datae(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .lut_mask = 64'hF0F0000020A00000;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y38_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & ( 
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & ( ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ))) # 
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3 .lut_mask = 64'h08FF08FF08000800;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y38_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout  = ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & ( 
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  & 
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ) ) ) ) # ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & ( 
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  & !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout )) ) ) ) # ( 
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( 
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  & !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4 .lut_mask = 64'hC0C08080C0C00000;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y38_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_019|packet_in_progress~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_019|packet_in_progress~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout  & ( (!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & ((\u0|mm_interconnect_0|cmd_mux_019|packet_in_progress~q ))) # 
// (\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout  & ( 
// \u0|mm_interconnect_0|cmd_mux_019|packet_in_progress~q  ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_019|packet_in_progress~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_019|packet_in_progress~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_019|packet_in_progress~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_019|packet_in_progress~0 .lut_mask = 64'h00FF00FF03F303F3;
defparam \u0|mm_interconnect_0|cmd_mux_019|packet_in_progress~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y38_N1
dffeas \u0|mm_interconnect_0|cmd_mux_019|packet_in_progress (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_019|packet_in_progress~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_019|packet_in_progress~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_019|packet_in_progress .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_019|packet_in_progress .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y38_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_019|update_grant~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_019|update_grant~0_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout  & ( (!\u0|mm_interconnect_0|cmd_mux_019|packet_in_progress~q  & 
// ((!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]) # (!\u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout ))) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout  & ( 
// (!\u0|mm_interconnect_0|cmd_mux_019|packet_in_progress~q ) # ((\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & \u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_019|packet_in_progress~q ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_019|update_grant~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_019|update_grant~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_019|update_grant~0 .lut_mask = 64'hF0F5F0F5F0A0F0A0;
defparam \u0|mm_interconnect_0|cmd_mux_019|update_grant~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y38_N38
dffeas \u0|mm_interconnect_0|cmd_mux_019|saved_grant[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|cmd_mux_019|update_grant~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_019|saved_grant[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_019|saved_grant[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y32_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_019|src_payload~11 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_019|src_payload~11_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [11] & ( \u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_019|src_payload~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~11 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~11 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y32_N26
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_019|src_payload~11_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";
// synopsys translate_on

// Location: FF_X25_Y32_N20
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~20_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][116]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y32_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~20 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~20_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][116]~q  ) ) # ( 
// !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][116]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~20 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~20 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~20 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y32_N35
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~20_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][116]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y36_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout  = ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][129]~q  & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0] & 
// (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0] & !\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0])) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][129]~q  & ( 
// (!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0] & !\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0]) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0]),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0]),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid .lut_mask = 64'hA0A0A0A080808080;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y32_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~198 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~198_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout  & ( (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][116]~q  & (!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout  
// & !\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout )) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout  & ( ((\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][116]~q  & 
// (!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout  & !\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ))) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][116]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][116]~q ),
        .datab(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][116]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~198_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~198 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~198 .lut_mask = 64'h40FF40FF40404040;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~198 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y32_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~199 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~199_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][116]~q  & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~198_combout  & ( 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout  & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][116]~q ) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ))) ) ) ) # ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][116]~q  & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~198_combout  & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][116]~q ) # 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][116]~q ),
        .datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][116]~q ),
        .dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~198_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~199_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~199 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~199 .lut_mask = 64'hFF550F0500000000;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~199 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y33_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_017|src_payload~11 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_017|src_payload~11_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [11] & ( \u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_017|src_payload~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~11 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~11 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y33_N29
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_017|src_payload~11_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";
// synopsys translate_on

// Location: FF_X19_Y33_N32
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~20_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][116]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y33_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~20 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~20_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][116]~q  ) ) # ( 
// !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
        .datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][116]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~20 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~20 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~20 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y33_N22
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~20_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][116]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y31_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_016|src_payload~11 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_016|src_payload~11_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [11] & ( \u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_016|src_payload~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~11 .lut_mask = 64'h000000000000FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~11 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y31_N32
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_016|src_payload~11_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";
// synopsys translate_on

// Location: FF_X17_Y31_N41
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~20_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][116]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y31_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~20 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~20_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][116]~q  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][116]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~20 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~20 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~20 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y30_N17
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~20_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][116]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";
// synopsys translate_on

// Location: FF_X21_Y29_N56
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][66]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y29_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~3 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~3_combout  = (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66])) # 
// (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][66]~q )))

        .dataa(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][66]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y29_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~4 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~4_combout  = ( \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0] & ( (\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0_combout  & 
// (((!\u0|mm_interconnect_0|link_start_s1_agent|local_write~0_combout ) # (\u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout )) # (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]))) ) ) # ( 
// !\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0] & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & (!\u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout  & 
// (\u0|mm_interconnect_0|link_start_s1_agent|local_write~0_combout  & \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),
        .datab(!\u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout ),
        .datac(!\u0|mm_interconnect_0|link_start_s1_agent|local_write~0_combout ),
        .datad(!\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~4 .lut_mask = 64'h0008000800F700F7;
defparam \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y29_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg~1_combout  = ( \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~4_combout  & ( \u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg~0_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~4_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg~1 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y29_N41
dffeas \u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y29_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~0_combout  = ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][129]~q  & ( ((!\u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg [0] & 
// !\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [0]) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][129]~q  & ( 
// (!\u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [0]) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg [0]),
        .datad(!\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~0 .lut_mask = 64'hF000F000F555F555;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y29_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~1_combout  = ( \u0|hps_0|fpga_interfaces|h2f_BREADY [0] & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~0_combout  & ((\u0|hps_0|fpga_interfaces|h2f_RREADY [0]) # 
// (\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ))) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_BREADY [0] & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~0_combout  & (!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout  & 
// \u0|hps_0|fpga_interfaces|h2f_RREADY [0])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~0_combout ),
        .datac(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_BREADY [0]),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~1 .lut_mask = 64'h00C00CCC00C00CCC;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y29_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[1]~1_combout  = ( \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~1_combout  & 
// ((\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [1]) # (\u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg [0]))) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [0] & ( 
// (!\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~1_combout  & \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [1]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg [0]),
        .datac(!\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~1_combout ),
        .datad(!\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[1]~1 .lut_mask = 64'h00F000F030F030F0;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[1]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y29_N56
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y29_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[0]~0_combout  = ( \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~1_combout  & ( ((\u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg [0] & 
// \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~1_combout  & ( 
// ((!\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [1] & \u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [0]) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg [0]),
        .datad(!\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h0AFF0AFF555F555F;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y29_N59
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y29_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|comb~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent|comb~0_combout  = ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [0] & ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][129]~q  ) ) # ( 
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [0] & ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][129]~q  & ( (\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [0]) # 
// (\u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg [0]) ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg [0]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [0]),
        .datae(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [0]),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_agent|comb~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|comb~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent|comb~0 .lut_mask = 64'h000033FF0000FFFF;
defparam \u0|mm_interconnect_0|link_start_s1_agent|comb~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y29_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0_combout  = ( \u0|hps_0|fpga_interfaces|h2f_BREADY [0] & ( \u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ( \u0|mm_interconnect_0|link_start_s1_agent|comb~0_combout  ) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_BREADY [0] & ( \u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ( (!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout  & \u0|mm_interconnect_0|link_start_s1_agent|comb~0_combout ) ) ) ) # ( 
// \u0|hps_0|fpga_interfaces|h2f_BREADY [0] & ( !\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ( (\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout  & \u0|mm_interconnect_0|link_start_s1_agent|comb~0_combout ) ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ),
        .datad(!\u0|mm_interconnect_0|link_start_s1_agent|comb~0_combout ),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_BREADY [0]),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0 .lut_mask = 64'h0000000F00F000FF;
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y29_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout  = ( \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0_combout  & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [0]) # 
// (!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0_combout  & ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [0] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [0]),
        .datad(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hF0F0F0F0FFF0FFF0;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y29_N53
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~3_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][66]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";
// synopsys translate_on

// Location: FF_X21_Y29_N59
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][69] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][69]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][69] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y29_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~1_combout  = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]) 
// # (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][69]~q ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & ( 
// (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][69]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][69]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y29_N47
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][69] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][69]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][69] .power_up = "low";
// synopsys translate_on

// Location: FF_X22_Y29_N38
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][68] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][68]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][68] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][68] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y29_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~2 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~2_combout  = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]) 
// # (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][68]~q ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] & ( 
// (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][68]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][68]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~2 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y29_N17
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][68] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~2_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][68]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][68] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][68] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y29_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_007|src0_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout  = ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][68]~q  & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][66]~q  & 
// !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][69]~q ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][66]~q ),
        .datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][69]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][68]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_007|src0_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_007|src0_valid~0 .lut_mask = 64'h00000000F000F000;
defparam \u0|mm_interconnect_0|rsp_demux_007|src0_valid~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y31_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_013|src_payload~11 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_013|src_payload~11_combout  = ( \u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [11] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_013|src_payload~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~11 .lut_mask = 64'h0000000000FF00FF;
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~11 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y38_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout  = ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  & (\u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout  & \u0|mm_interconnect_0|cmd_mux_013|saved_grant [1])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h00000000000C000C;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y31_N50
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_013|src_payload~11_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";
// synopsys translate_on

// Location: FF_X17_Y31_N23
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~20_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][116]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";
// synopsys translate_on

// Location: FF_X17_Y38_N11
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";
// synopsys translate_on

// Location: FF_X17_Y38_N8
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y38_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~0_combout  = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & ( 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~0 .lut_mask = 64'h030003000F000F00;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y38_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override~feeder (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y38_N41
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y38_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter~0_combout  = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override~q  & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout 
//  & (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~0_combout  & !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter [0])) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~0_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter~0 .lut_mask = 64'h000000000A000A00;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y38_N53
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y38_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0_combout  = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override~q  & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter [0] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y38_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~1_combout  = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout  & ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout  & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0_combout  & !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~1 .lut_mask = 64'h0F000F00FF00FF00;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y39_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~1_combout  & ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~1_combout ),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h000000000000FFFF;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y38_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y38_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  = ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & 
// ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0_combout ) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout ))) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hFFFFFFFF50F050F0;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y38_N22
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on

// Location: FF_X19_Y38_N32
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y38_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout  = ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) # 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .lut_mask = 64'h00FF00FFFC0CFC0C;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y38_N8
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y38_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  = ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & ( 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h4040404000000000;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y38_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout  = ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  $ 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) # 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] $ 
// (((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) # 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .lut_mask = 64'h0AF50AF54EE44EE4;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y38_N47
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";
// synopsys translate_on

// Location: FF_X19_Y38_N44
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y38_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout  = ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] 
// & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] $ 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6])))) # 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6])))) ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] 
// & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & 
// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) # 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) ) ) # ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  & ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] 
// & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] $ 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6])))) # 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6])) # 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ))) ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  & ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg 
// [2] & ( ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) # 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .lut_mask = 64'h0F5FC35F0F0AC30A;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y38_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout  & ( ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) # 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout  & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ) ) ) # ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout  & ( ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) # 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout  & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) # 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0_combout ) # 
// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'hDC50DD55CC00DD55;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y38_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout  = ( \u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & ( (\u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout  & 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout )) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .lut_mask = 64'h0000000000050005;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y38_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout  = ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & ( 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// (((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout  & 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q )) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout 
// ))) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & ( 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout 
// ))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .lut_mask = 64'h050F050F05070507;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y38_N26
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y38_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  = ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  $ 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) # 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .lut_mask = 64'hA000A0005AA05AA0;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y38_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout  = ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & ( 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout  & 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h000000000F000F00;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y38_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout  = ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & ( 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h0055005500000000;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y38_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout  = ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout  & ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0 .lut_mask = 64'hF0F0F0F000000000;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y38_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout  = ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout  & ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout  & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout  
// ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout  & ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout  & ( 
// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout  & 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout  & 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ))) # 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ) ) ) ) # ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout  & ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout  & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout 
//  ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout  & ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout  & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout 
//  ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
        .datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h00FF00FF20FF00FF;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y38_N56
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y38_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout  = ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] $ 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) # 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .lut_mask = 64'h00FF00FFE44EE44E;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y38_N53
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y38_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout  = ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4])) # 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))) ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] ) ) ) # ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4])) # 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))) ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] $ 
// (((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) # 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .lut_mask = 64'h339933F0333333F0;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y38_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  = ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .lut_mask = 64'h000000000A0A0A0A;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y38_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout  = ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout  & ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout  & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout 
// ) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ) ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout  & ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout  & ( ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout 
//  & ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ) # 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout )))) # 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ) ) ) ) # ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout  & ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout  & ( 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ) 
// ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout  & ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout  & ( 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ) 
// ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),
        .datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .lut_mask = 64'h33FF33FF13FF33FF;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y38_N50
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";
// synopsys translate_on

// Location: FF_X19_Y38_N59
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][74] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~7_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][74]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y38_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~7 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~7_combout  = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) # 
// ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])))) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & 
// (((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][74]~q )))) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & 
// (((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][74]~q )))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][74]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h043704378CBF8CBF;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y38_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|write~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|write~0_combout  = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0_combout  & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~0_combout  ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0_combout  & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout  & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~0_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~0_combout ),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|write~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|write~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h1111111133333333;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|write~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y38_N38
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][129] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][129]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y38_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~1_combout  = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~0_combout  & ( ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][129]~q )) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~0_combout  & ( 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][129]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][129]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y38_N23
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][129] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y38_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|read~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|read~0_combout  = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg [0] & ( (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & 
// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0]) # (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][129]~q ))) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg [0] & 
// ( (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0] & ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0]) # 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][129]~q )))) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
        .datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|read~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|read~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|read~0 .lut_mask = 64'h0504050455445544;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|read~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y38_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[1]~1_combout  = ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|read~0_combout  & ( ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg 
// [0] & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [1]) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|read~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[1]~1 .lut_mask = 64'h05FF05FF00000000;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[1]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y38_N47
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y38_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[0]~0_combout  = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|read~0_combout  & ( ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg 
// [0] & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|read~0_combout  & ( 
// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [1] & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg [0]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|read~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h0CFF0CFF333F333F;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y38_N44
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y38_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|comb~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|comb~0_combout  = (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0] & (((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0]) # 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][129]~q )) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg [0])))

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg [0]),
        .datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|comb~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|comb~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|comb~0 .lut_mask = 64'h1333133313331333;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|comb~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y38_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout  = ( \u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|comb~0_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|comb~0_combout ),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0 .lut_mask = 64'h0000000000FF00FF;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y38_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[0]~1_combout  = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout  & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used 
// [0]) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|write~0_combout ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout  & ( 
// ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0] & ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout ) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1])))) # 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|write~0_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|write~0_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h33F733F733FF33FF;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y38_N32
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y38_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout  = (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0]) # ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout  
// & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout ))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hCCFCCCFCCCFCCCFC;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y38_N14
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~7_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";
// synopsys translate_on

// Location: FF_X19_Y38_N56
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][75] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][75]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y38_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~6 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~6_combout  = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][75]~q  ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][75]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h0505050500FF00FF;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y38_N29
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~6_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";
// synopsys translate_on

// Location: FF_X19_Y38_N1
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][77] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~4_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][77]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y38_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~4 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~4_combout  = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][77]~q  & ( 
// ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][77]~q  & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][77]~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~4 .lut_mask = 64'h0404373704043737;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y38_N26
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][77] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~4_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][77]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";
// synopsys translate_on

// Location: FF_X19_Y38_N5
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][76] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][76]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y38_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~5 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~5_combout  = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4])) # 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][76]~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][76]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][76]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h000F000F303F303F;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y38_N38
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][76] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~5_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][76]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y38_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~1_combout  = ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][77]~q  & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][76]~q  ) ) # ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][77]~q  & ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][76]~q  & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q  & 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ) ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][77]~q  & ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][76]~q  & ( 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ) ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][77]~q ),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h3F3FC0C0FFFF0000;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y38_N11
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_busy (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y38_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout  = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q  & ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y38_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout  = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout  & ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ) # 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h00000000CC0CCC0C;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y38_N32
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y38_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~0_combout  = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) # 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h5F5F5F5FA0A0A0A0;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y38_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout  = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~0_combout  & ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout  & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][76]~q  $ (((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ))))) ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~0_combout  & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][76]~q  $ (((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75]~q )))) # 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~0_combout ),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h00000000B7778444;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y38_N26
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y38_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~1_combout  = ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~1 .lut_mask = 64'hC000C00000000000;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y38_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~0_combout  = ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][77]~q  & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][76]~q  & 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q  & !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75]~q )) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][77]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~0 .lut_mask = 64'hA000A00000000000;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y38_N41
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][78] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][78]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y38_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~3 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~3_combout  = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6])) # 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][78]~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][78]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][78]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h003300330C3F0C3F;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y38_N20
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][78] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~3_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][78]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y38_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout  = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout  & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~0_combout  $ (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][78]~q )))) # 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~1_combout )) ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~0_combout  $ 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][78]~q )))) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~1_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~1_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~0_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][78]~q ),
        .datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h000000001BB14EE4;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y38_N50
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y38_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout  = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~0_combout  & ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout  & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][78]~q )))) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~1_combout ))) ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~0_combout  & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~1_combout  & 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~1_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][78]~q ),
        .datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~0_combout ),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h000000000202F202;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y38_N7
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y38_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q  ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q  & ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout ) # 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [7]))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h0A0F0A0F0F0F0F0F;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y38_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout  = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout  & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75]~q  $ (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q )))) # 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2])) ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75]~q  $ 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q )))) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2])) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h00000000E44EB11B;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y38_N56
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y38_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~2_combout  = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5] ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5] $ (((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h78787878F0F0F0F0;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y38_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout  = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout  & !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~2_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~1_combout  & 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~1_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~2_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h0A0A0A0A0F000F00;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y38_N47
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y38_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout  = ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'hC000C00000000000;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y38_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~0_combout  = ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75]~q  & ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][77]~q  & 
// ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][76]~q  & (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q  & (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][78]~q  & 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][78]~q ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][77]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h2000000000000000;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y38_N35
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][66]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y38_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~2_combout  = (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66])) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & 
// ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][66]~q )))

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][66]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~2 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y38_N41
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~2_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][66]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y38_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout  = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][66]~q  & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|comb~0_combout ) # 
// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~0_combout  & ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout ) # 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|comb~0_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][66]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h00000000FEF0FEF0;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y38_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[1]~0_combout  = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|write~0_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout  & (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used 
// [0])) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout  & ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]))))) # 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout  & (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0])) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|write~0_combout  & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout ) # 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),
        .datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|write~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[1]~0 .lut_mask = 64'h00F500F5313B313B;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[1]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y38_N2
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y31_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~20 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~20_combout  = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][116]~q  ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][116]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~20 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~20 .lut_mask = 64'h5555555500FF00FF;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~20 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y31_N17
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~20_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][116]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";
// synopsys translate_on

// Location: FF_X18_Y29_N8
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~21_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][116]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y29_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|src_data[116] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|src_data [116] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [11] & ( ((\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [11])) # (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_AWID [11] & ( (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [11]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [11]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_007|src_data [116]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[116] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[116] .lut_mask = 64'h0505050537373737;
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[116] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y29_N46
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_007|src_data [116]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y29_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~21 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~21_combout  = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] & ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & 
// ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][116]~q  ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] & ( 
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][116]~q  ) ) ) # ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg 
// [116] & ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][116]~q ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~21_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~21 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~21 .lut_mask = 64'h0000FFFF0F0F0F0F;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~21 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y29_N2
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~21_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][116]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y31_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~196 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~196_combout  = ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][116]~q  & ( (!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout  & 
// ((!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ) # ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout  & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][116]~q )))) # 
// (\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout  & (((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout  & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][116]~q )))) ) ) # ( 
// !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][116]~q  & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout  & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][116]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout ),
        .datab(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][116]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][116]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~196_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~196 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~196 .lut_mask = 64'h00F000F088F888F8;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~196 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y30_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~197 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~197_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][116]~q  & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~196_combout  & ( 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout  & ((!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][116]~q ) # (!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ))) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][116]~q  & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~196_combout  & ( (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][116]~q ) # 
// (!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][116]~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout ),
        .datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][116]~q ),
        .dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~196_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~197_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~197 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~197 .lut_mask = 64'hFAFA00FA00000000;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~197 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y24_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_data[116] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|src_data [116] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [11] & ( ((\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [11])) # (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_ARID [11] & ( (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [11]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
        .datac(gnd),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_AWID [11]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_018|src_data [116]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[116] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[116] .lut_mask = 64'h0033003355775577;
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[116] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y24_N37
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_018|src_data [116]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";
// synopsys translate_on

// Location: FF_X25_Y24_N11
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~21_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][116]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y21_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y21_N38
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y23_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_payload[0] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|src_payload [0] = ((\u0|hps_0|fpga_interfaces|h2f_WLAST [0] & \u0|mm_interconnect_0|cmd_mux_018|saved_grant [0])) # (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1])

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_WLAST [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_018|src_payload [0]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|src_payload[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|src_payload[0] .lut_mask = 64'h3377337733773377;
defparam \u0|mm_interconnect_0|cmd_mux_018|src_payload[0] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y23_N59
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_018|src_payload [0]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y21_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~4_combout  & ( 
// (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~4_combout  & ( ((\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & 
// !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0])) # (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
        .datac(gnd),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~4_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 .lut_mask = 64'h7755775533003300;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y21_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout  = ( 
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout  & ( (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] 
// $ (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])) # (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) # ( 
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout  & ( (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] $ (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 .lut_mask = 64'h0AA00AA05FF55FF5;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y21_N17
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";
// synopsys translate_on

// Location: FF_X25_Y21_N35
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y21_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3_combout  & ( 
// ((\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout )) # (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]) ) ) # ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3_combout  & ( (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5 .lut_mask = 64'h0303030357575757;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y21_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout  = ( 
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout  & ( 
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] $ (((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # 
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])))) # (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) # ( 
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout  & ( (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] $ (((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # 
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))))) ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6 .lut_mask = 64'h08A208A25DF75DF7;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y21_N2
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y21_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( 
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg 
// [3] & ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] $ 
// (((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .lut_mask = 64'hF03CF03CF0F0F0F0;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y21_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout  = ( \u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & ( 
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  & ( (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout ))) ) ) ) # ( 
// !\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  & ( 
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) ) ) ) # ( 
// \u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  & ( 
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # (((\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout )) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & ( 
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  & ( (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # 
// ((\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout ),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),
        .datae(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .lut_mask = 64'hAABBAFBF00110515;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y21_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout  & ( ((\u0|mm_interconnect_0|cmd_mux_018|saved_grant 
// [0] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~1_combout )) # (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout  & ( 
// (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~1_combout ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 .lut_mask = 64'h000F000F333F333F;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y21_N47
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y21_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  = ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( 
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] & (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & 
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .lut_mask = 64'h00A000A000000000;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y21_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  & ( 
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) # 
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout )) ) ) 
// # ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  & ( (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) # (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 .lut_mask = 64'h05AF05AFAF05AF05;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y21_N59
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y21_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout  = ( 
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) # 
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg 
// [2])) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  $ 
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .lut_mask = 64'h0FF00FF00AFA0AFA;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y21_N29
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y21_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout  = ( 
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # ((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) # 
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ) ) # ( 
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & 
// ( (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ) ) # ( 
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & 
// ( (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) # 
// ((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) 
// # (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))) ) ) ) # 
// ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] 
// & ( (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) 
// # (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datae(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .lut_mask = 64'h00CAFF3A000AFFFA;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y21_N32
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y21_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  = ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( 
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & 
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h0C000C0000000000;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y21_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout  = ( 
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) # 
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg 
// [2])) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] $ (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .lut_mask = 64'h0FF00FF02E2E2E2E;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y21_N35
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";
// synopsys translate_on

// Location: FF_X28_Y21_N7
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y21_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout  = ( 
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # 
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) ) ) ) # ( 
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout 
// ) ) ) ) # ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( 
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) # 
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) ) ) ) # ( 
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  & !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) ) ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datae(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 .lut_mask = 64'h3030CFCF00AAFFAA;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y21_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout  = ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .lut_mask = 64'hFF00FF0000000000;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y21_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout  = ( \u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & ( 
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & ( (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ) # 
// ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ) # 
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & ( 
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & ( (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & 
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & ( 
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & ( (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & 
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & ( 
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & ( (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & 
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ) ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datae(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .lut_mask = 64'h005500550055F4F5;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y23_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_valid~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|src_valid~1_combout  = ( \u0|mm_interconnect_0|cmd_demux_001|src18_valid~1_combout  & ( \u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_demux_001|src18_valid~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_018|src_valid~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|src_valid~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|src_valid~1 .lut_mask = 64'h0000000000FF00FF;
defparam \u0|mm_interconnect_0|cmd_mux_018|src_valid~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y23_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y23_N35
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y23_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout  = ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & ( 
// \u0|mm_interconnect_0|cmd_mux_018|src_valid~0_combout  ) ) # ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & ( !\u0|mm_interconnect_0|cmd_mux_018|src_valid~0_combout  & ( 
// !\u0|mm_interconnect_0|cmd_mux_018|src_valid~1_combout  ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & ( !\u0|mm_interconnect_0|cmd_mux_018|src_valid~0_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_018|src_valid~1_combout ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_018|src_valid~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .lut_mask = 64'hFFFFF0F0FFFF0000;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y21_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout  = ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & ( 
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout  & ( (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ) ) ) ) # ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  
// & ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout  & ( (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout  & 
// (!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout )) ) ) ) # ( 
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout  & ( 
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & (((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout  & 
// !\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1])) # (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datae(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .lut_mask = 64'h0073005000330000;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y21_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .lut_mask = 64'h0100010055005500;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y21_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  & ( 
// ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout  & 
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout  & 
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ))) # 
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  & ( 
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout  ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16 .lut_mask = 64'h0F0F0F0F4F0F4F0F;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y21_N44
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y21_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  = ( !\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & ( 
// ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & (!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]))) ) ) # ( \u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & ( 
// ((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ) # ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q  & 
// ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) # (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q 
// ))))) # (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datae(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .extended_lut = "on";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .lut_mask = 64'h3030F3F73030F7F7;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y20_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_data[35] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|src_data [35] = ( \u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] ) # ( !\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & ( (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_WSTRB 
// [3]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [3]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_018|src_data [35]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[35] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[35] .lut_mask = 64'h0505FFFF0505FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[35] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y20_N53
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_018|src_data [35]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y20_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_data[34] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|src_data [34] = ( \u0|hps_0|fpga_interfaces|h2f_WSTRB [2] & ( (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]) # (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_WSTRB [2] & ( 
// \u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_018|src_data [34]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[34] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[34] .lut_mask = 64'h00FF00FF55FF55FF;
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[34] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y20_N44
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_018|src_data [34]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y20_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_data[33] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|src_data [33] = ( \u0|hps_0|fpga_interfaces|h2f_WSTRB [1] & ( (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]) # (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_WSTRB [1] & ( 
// \u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_018|src_data [33]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[33] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[33] .lut_mask = 64'h333333333F3F3F3F;
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[33] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y20_N32
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_018|src_data [33]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y20_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~2_combout  = ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & ( 
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & 
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2])) ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~2 .lut_mask = 64'hA000A00000000000;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y20_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_data[88] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|src_data [88] = ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & ( ((\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [2])) # (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & ( (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_018|src_data [88]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[88] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[88] .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[88] .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y20_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_data[87] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|src_data [87] = ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] & ( ((\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1])) # (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] & ( (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_018|src_data [87]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[87] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[87] .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[87] .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y20_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout  = (!\u0|mm_interconnect_0|cmd_mux_018|src_data [88] & !\u0|mm_interconnect_0|cmd_mux_018|src_data [87])

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_018|src_data [88]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_018|src_data [87]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .lut_mask = 64'hF000F000F000F000;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y20_N56
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y20_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~3 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~3_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q  & ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ( 
// (\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~0_combout  & (!\u0|mm_interconnect_0|clock_sel_s1_agent|local_write~0_combout  $ (!\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [0]))) ) ) ) # ( 
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q  & ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ( ((\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~0_combout  & 
// (!\u0|mm_interconnect_0|clock_sel_s1_agent|local_write~0_combout  $ (!\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [0])))) # (\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~2_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~0_combout ),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~2_combout ),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_agent|local_write~0_combout ),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [0]),
        .datae(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~3 .lut_mask = 64'h3773055000000000;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y20_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout  = ( !\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & ( (!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]) # 
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .lut_mask = 64'hF0FFF0FF00000000;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y20_N26
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y21_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( 
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout  & ( (!\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~3_combout  & 
// ((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ))) # (\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~3_combout  & 
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) ) # ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( 
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout  & ( ((!\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~3_combout  & 
// ((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ))) # (\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~3_combout  & 
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) # (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ) ) ) ) # ( 
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout  & ( 
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  ) ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~3_combout ),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .datae(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h5555FD5D0000FC0C;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y21_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout  & ( 
// ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~0_combout  & \u0|mm_interconnect_0|cmd_mux_018|saved_grant [0])) # (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]) ) ) # ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout  & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~0_combout  & \u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~0_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .lut_mask = 64'h000F000F333F333F;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y21_N14
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y21_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  & ( 
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] $ 
// (((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]))))) # (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout )))) ) ) # ( 
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  & ( (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]))) # (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 .lut_mask = 64'h05AF05AF8D278D27;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y21_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout  = ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout  & ( 
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout  ) ) # ( 
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout  & ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout  
// & ( (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout  & 
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout  & 
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout  & 
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ))) ) ) ) # ( 
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout  & ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout  
// ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout ),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ),
        .datae(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .lut_mask = 64'hFFFF0080FFFF0000;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y21_N56
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y21_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~1_combout  & ( 
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q )) # 
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~1_combout  & ( (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q )) # (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .lut_mask = 64'h550F550F55335533;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y21_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17_combout  = ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & ( 
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ) # ((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) # 
// (((!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & !\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1])) # (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ))) ) ) # ( 
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & ( ((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ) # 
// ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datae(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
        .datag(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17 .extended_lut = "on";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17 .lut_mask = 64'hFFECCCCCFFFFCCCF;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y21_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1_combout  = ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1 .lut_mask = 64'hFFFFFFFF00000000;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y21_N56
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y21_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) ) ) # ( 
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & 
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) # 
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  $ 
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .lut_mask = 64'hA550A55050005000;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y21_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout  & ( 
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) # 
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ))) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout  & 
// ( (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .lut_mask = 64'h0022002211331133;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y21_N59
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y21_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( 
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout  ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( 
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ) # (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .lut_mask = 64'hF3F3F3F3F0F0F0F0;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y21_N44
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .power_up = "low";
// synopsys translate_on

// Location: FF_X28_Y20_N26
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y20_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|local_write~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent|local_write~0_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] & ( 
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_agent|local_write~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|local_write~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|local_write~0 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|local_write~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y20_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~1_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [0] & ( (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & 
// (((\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~0_combout  & !\u0|mm_interconnect_0|clock_sel_s1_agent|local_write~0_combout )) # (\u0|mm_interconnect_0|clock_sel_s1_agent|WideOr0~0_combout ))) ) ) # ( 
// !\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [0] & ( (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & (((\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~0_combout  & 
// \u0|mm_interconnect_0|clock_sel_s1_agent|local_write~0_combout )) # (\u0|mm_interconnect_0|clock_sel_s1_agent|WideOr0~0_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~0_combout ),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_agent|WideOr0~0_combout ),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_agent|local_write~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~1 .lut_mask = 64'h0C4C0C4C4C0C4C0C;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y21_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & 
// ( \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~1_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~1_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y21_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout  = ( 
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) # 
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg 
// [2])) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] $ 
// (((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) # 
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .lut_mask = 64'h30CF30CF22EE22EE;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y21_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout  = ( 
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout  & ( 
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout  & 
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0 .lut_mask = 64'hF000F00000000000;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y21_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout  = ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( 
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & (((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout )) # (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q 
// ))) ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h1113111300000000;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y21_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & ( 
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) 
// ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h0000000033003300;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y21_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout  ) # ( 
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout  & ( (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout  & 
// ((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ) # 
// ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ) # 
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h0B0F0B0FFFFFFFFF;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y21_N47
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";
// synopsys translate_on

// Location: FF_X28_Y21_N20
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][75] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][75]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y21_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~6 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~6_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( 
// (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) # 
// (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][75]~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][75]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][75]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h0055005522772277;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y22_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|always0~0_combout  & 
// !\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [0] )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|always0~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hFFFFFFFF50505050;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y21_N59
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][75] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~6_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][75]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";
// synopsys translate_on

// Location: FF_X28_Y21_N23
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][76] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~7_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][76]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y21_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~7 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~7_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][76]~q  ) ) # ( 
// !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][76]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h0303030300FF00FF;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y21_N29
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][76] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~7_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][76]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";
// synopsys translate_on

// Location: FF_X28_Y21_N5
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][74] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][74]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y21_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~5 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~5_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] 
// & ((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) # 
// ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])))) # (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & 
// (((\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][74]~q )))) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) # (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & 
// (((\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][74]~q )))) ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][74]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h025702578ADF8ADF;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y21_N17
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][74] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~5_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][74]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y21_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout  & ( (!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][74]~q  $ 
// (((\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][75]~q ))))) # (\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (((\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout  & ( (!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][74]~q  $ 
// (((\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][75]~q ))))) # (\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (((!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datae(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h00000000D8728D27;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y21_N32
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y21_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~0_combout  = !\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [4] $ (((!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [3] 
// & !\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h5AAA5AAA5AAA5AAA;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y21_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~0_combout  & ( \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout  & 
// ( (!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][76]~q  $ (((\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][74]~q ) # 
// (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][75]~q ))))) ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~0_combout  & ( \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout  & ( 
// (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][76]~q  $ (((\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][74]~q ) # (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][75]~q )))) # 
// (\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datae(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~0_combout ),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h00000000D75F820A;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y21_N8
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";
// synopsys translate_on

// Location: FF_X28_Y21_N53
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][78] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~9_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][78]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y21_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~9 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~9_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( 
// (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) # 
// (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][78]~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][78]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][78]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~9 .lut_mask = 64'h0055005522772277;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~9 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y21_N56
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][78] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~9_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][78]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";
// synopsys translate_on

// Location: FF_X28_Y21_N50
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][77] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][77]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y21_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~8 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~8_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][77]~q  ) ) # ( 
// !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][77]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~8 .lut_mask = 64'h0303030300FF00FF;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y21_N14
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][77] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~8_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][77]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y21_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~0_combout  = (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][76]~q  & (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][77]~q  & 
// (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][74]~q  & !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][75]~q )))

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][77]~q ),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~0 .lut_mask = 64'h8000800080008000;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y21_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~1_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][74]~q  & ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][77]~q  ) ) # ( 
// !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][74]~q  & ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][77]~q  $ (((!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][76]~q  & 
// !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][75]~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][77]~q ),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h66CC66CCCCCCCCCC;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y21_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~2 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~2_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & ( (!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [2] 
// & (!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & !\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [3])) ) ) # ( 
// !\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & ( ((\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [3]) # 
// (\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [4])) # (\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h7F7F7F7F80808080;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y21_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~2_combout  & ( 
// (!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout  & !\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~1_combout )) 
// ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~2_combout  & ( (\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~1_combout ) # 
// (\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout ),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h0F050F050A000A00;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y21_N50
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y21_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~1_combout  = ( !\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( (!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter 
// [2] & (!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & !\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [5])) ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~1 .lut_mask = 64'h8080808000000000;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y21_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( 
// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout  & ( (!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][78]~q  $ 
// ((!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~0_combout )))) # (\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (((!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~1_combout )))) 
// ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout  & ( 
// (!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][78]~q  $ ((!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~0_combout )))) # 
// (\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (((\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~1_combout )))) ) ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][78]~q ),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~0_combout ),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~1_combout ),
        .datae(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h00000000606F6F60;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y21_N38
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y21_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~1 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~1_combout  = ( !\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & ( 
// (!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & 
// !\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [6])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'hC000C00000000000;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y21_N47
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_busy (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y21_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~0_combout  & ( \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout  & 
// ( (!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][78]~q )) # 
// (\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (((!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & 
// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~1_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~0_combout  & ( \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout  & ( 
// (\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & 
// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~1_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][78]~q ),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~1_combout ),
        .datae(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~0_combout ),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h00000000003088B8;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y21_N44
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y21_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [7] & ( 
// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_busy~q  ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [7] & ( 
// (\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_busy~q  & ((!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~1_combout ) # (\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter 
// [2]))) ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h00AF00AF00FF00FF;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y21_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout  & ( 
// (!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][74]~q  & ((!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_busy~q ) # 
// (!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) # (\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (((!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_busy~q ) # (!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h00000000DDD0DDD0;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y21_N53
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";
// synopsys translate_on

// Location: FF_X27_Y20_N34
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";
// synopsys translate_on

// Location: FF_X28_Y20_N23
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][66]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y20_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~3 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~3_combout  = (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66])) # 
// (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][66]~q )))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][66]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h0C3F0C3F0C3F0C3F;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y22_N20
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~3_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][66]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y21_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~0_combout  = ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][75]~q  & ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][77]~q  & ( 
// (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][78]~q  & (!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_busy~q  & (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][76]~q  & 
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][74]~q ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][78]~q ),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datae(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][75]~q ),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][77]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h0080000000000000;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y21_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout  = ( \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~1_combout  & ( \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~0_combout  & ( 
// (!\u0|mm_interconnect_0|clock_sel_s1_agent|comb~0_combout  & \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][66]~q ) ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~1_combout  & ( 
// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~0_combout  & ( (!\u0|mm_interconnect_0|clock_sel_s1_agent|comb~0_combout  & \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][66]~q ) ) ) ) # ( 
// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~1_combout  & ( !\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~0_combout  & ( (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][66]~q  & 
// ((!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) # ((!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_busy~q ) # (!\u0|mm_interconnect_0|clock_sel_s1_agent|comb~0_combout )))) ) ) ) # ( 
// !\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~1_combout  & ( !\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~0_combout  & ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][66]~q  ) ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_agent|comb~0_combout ),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][66]~q ),
        .datae(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h00FF00FE00F000F0;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y22_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|write~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|write~0_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_agent|m0_read~0_combout  & ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & 
// ( (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|clock_sel_s1_agent|WideOr0~0_combout ) # (\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~4_combout ))) ) ) ) # ( 
// !\u0|mm_interconnect_0|clock_sel_s1_agent|m0_read~0_combout  & ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & 
// (\u0|mm_interconnect_0|clock_sel_s1_agent|local_write~0_combout  & ((\u0|mm_interconnect_0|clock_sel_s1_agent|WideOr0~0_combout ) # (\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~4_combout )))) ) ) ) # ( 
// \u0|mm_interconnect_0|clock_sel_s1_agent|m0_read~0_combout  & ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & 
// ((\u0|mm_interconnect_0|clock_sel_s1_agent|WideOr0~0_combout ) # (\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~4_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~4_combout ),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_agent|WideOr0~0_combout ),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_agent|local_write~0_combout ),
        .datae(!\u0|mm_interconnect_0|clock_sel_s1_agent|m0_read~0_combout ),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|write~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|write~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h0000707000707070;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|write~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y22_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used[1]~0_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|write~0_combout  & ( (!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|always0~0_combout  & 
// (((\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [0])))) # (\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|always0~0_combout  & ((!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout  & 
// ((\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]))) # (\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout  & (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [0])))) ) ) # ( 
// !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|write~0_combout  & ( (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ((!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|always0~0_combout ) # 
// (\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|always0~0_combout ),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout ),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [0]),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|write~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used[1]~0 .lut_mask = 64'h00BB00BB0B4F0B4F;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used[1]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y22_N2
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y24_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~21 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~21_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][116]~q  & ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] ) ) # ( 
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][116]~q  & ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] ) ) 
// ) # ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][116]~q  & ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg 
// [116] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][116]~q ),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~21_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~21 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~21 .lut_mask = 64'h0F0F0F0F0000FFFF;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~21 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y26_N2
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~21_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][116]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y23_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_data[116] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|src_data [116] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [11] & ( ((\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [11])) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_ARID [11] & ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [11]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_AWID [11]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_015|src_data [116]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[116] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[116] .lut_mask = 64'h005500550F5F0F5F;
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[116] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y23_N17
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_015|src_data [116]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";
// synopsys translate_on

// Location: FF_X18_Y23_N35
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~21_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][116]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y23_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~21 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~21_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][116]~q  & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] ) ) # ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][116]~q  & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][116]~q  & ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][116]~q ),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~21_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~21 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~21 .lut_mask = 64'h0F0F0F0F0000FFFF;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~21 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y19_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_015|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_015|WideOr0~0_combout  = ( \u0|mm_interconnect_0|rsp_demux_015|src0_valid~0_combout  & ( \u0|hps_0|fpga_interfaces|h2f_BREADY [0] ) ) # ( !\u0|mm_interconnect_0|rsp_demux_015|src0_valid~0_combout  & ( 
// \u0|hps_0|fpga_interfaces|h2f_RREADY [0] ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_BREADY [0]),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_015|src0_valid~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_demux_015|WideOr0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_015|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_015|WideOr0~0 .lut_mask = 64'h0F0F0F0F55555555;
defparam \u0|mm_interconnect_0|rsp_demux_015|WideOr0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y21_N14
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y21_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write~0_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write~0 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y21_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter~1_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter~0_combout  & ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [0] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter~1 .lut_mask = 64'h00000000FF00FF00;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y21_N53
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y21_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~4 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~4_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|WideOr0~0_combout  & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~0_combout  & 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [0]) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|WideOr0~0_combout  & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~0_combout  & 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [0] $ (((!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write~0_combout ) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]))))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|WideOr0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~4 .lut_mask = 64'h0451045100550055;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~4 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y19_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg~1_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~4_combout  & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg~0_combout  
// ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg~0_combout ),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~4_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg~1 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y19_N41
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X19_Y19_N32
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][129] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][129]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";
// synopsys translate_on

// Location: FF_X21_Y21_N29
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y21_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_read~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_read~0_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & ( 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_read~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_read~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_read~0 .lut_mask = 64'h000000000FFF0FFF;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_read~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y19_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~0_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][129]~q  & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_read~0_combout  & ( 
// (((\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write~0_combout  & \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout )) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1])) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|WideOr0~0_combout ) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][129]~q  & ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_read~0_combout  & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & (((\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write~0_combout  & 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout )) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|WideOr0~0_combout ))) ) ) ) # ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][129]~q  & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_read~0_combout  & ( ((\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write~0_combout  & 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout )) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][129]~q  & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_read~0_combout  & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write~0_combout  & \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|WideOr0~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][129]~q ),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_read~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~0 .lut_mask = 64'h000C333F444C777F;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y19_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][129]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][129]~feeder_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~0_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][129]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][129]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][129]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][129]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y19_N59
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][129] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][129]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][129]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y19_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|read~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|read~0_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [0] & ( ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [0] & 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][129]~q ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [0] & ( 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [0] & !\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg [0]) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [0]),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg [0]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|read~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|read~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|read~0 .lut_mask = 64'h8888888888FF88FF;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|read~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y19_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|read~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|read~1_combout  = ( \u0|mm_interconnect_0|rsp_demux_015|WideOr0~0_combout  & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|read~0_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|rsp_demux_015|WideOr0~0_combout ),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|read~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|read~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|read~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|read~1 .lut_mask = 64'h0000FFFF00000000;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|read~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y19_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[1]~1_combout  = ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|read~1_combout  & ( ((\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg [0] & 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [1]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg [0]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [0]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|read~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[1]~1 .lut_mask = 64'h03FF03FF00000000;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[1]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y19_N38
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y19_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[0]~0_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|read~1_combout  & ( ((\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg [0] & 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|read~1_combout  & ( 
// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [1] & \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [0]) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg [0]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|read~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h0AFF0AFF555F555F;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y19_N29
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y19_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|comb~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|comb~0_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][129]~q  & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg [0] & ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [0] ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][129]~q  & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg [0] & ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [0] ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][129]~q  & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg [0] & ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [0] ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][129]~q  & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg [0] & ( 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [0] & \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [0]) ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [0]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [0]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][129]~q ),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|comb~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|comb~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|comb~0 .lut_mask = 64'h0303333333333333;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|comb~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y19_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|always0~0_combout  = ( \u0|mm_interconnect_0|rsp_demux_015|WideOr0~0_combout  & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|comb~0_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|rsp_demux_015|WideOr0~0_combout ),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|comb~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|always0~0 .lut_mask = 64'h000000000000FFFF;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y19_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|write~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|write~0_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write~0_combout  & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~4_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_read~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write~0_combout  & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~4_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_read~0_combout ) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write~0_combout  & ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~4_combout  & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|WideOr0~0_combout  & (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & 
// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_read~0_combout )))) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write~0_combout  & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~4_combout  & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|WideOr0~0_combout  & 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_read~0_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|WideOr0~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_read~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write~0_combout ),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~4_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|write~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|write~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h040404440C0C0CCC;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|write~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y19_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used[0]~1_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [0] & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout  ) ) 
// # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [0] & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout  & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|write~0_combout  ) ) ) 
// # ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [0] & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|always0~0_combout ) # ((\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|write~0_combout )) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [0] & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout  & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|write~0_combout  ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|always0~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|write~0_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [0]),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h3333BFBF3333FFFF;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y19_N14
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y19_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|always0~0_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout ) # (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [0]) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|always0~0_combout  & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [0] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|always0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hF0F0F0F0FCFCFCFC;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y26_N44
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~21_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][116]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y19_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|rp_valid (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|rp_valid~combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [0] & 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][129]~q )) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [0] & ( 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [0] & !\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg [0]) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [0]),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg [0]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|rp_valid~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|rp_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|rp_valid .lut_mask = 64'h8888888888008800;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|rp_valid .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y22_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_015|src1_valid (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout  = (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|rp_valid~combout  & !\u0|mm_interconnect_0|rsp_demux_015|src0_valid~0_combout )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|rp_valid~combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|rsp_demux_015|src0_valid~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_015|src1_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_015|src1_valid .lut_mask = 64'hA0A0A0A0A0A0A0A0;
defparam \u0|mm_interconnect_0|rsp_demux_015|src1_valid .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y26_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~202 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~202_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][116]~q  & ( \u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][116]~q  & ( \u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout  & ( (\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout  & 
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][116]~q ) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][116]~q  & ( !\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout  & ( 
// (\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout  & \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][116]~q ) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][116]~q  & ( 
// !\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout  & ( (\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout  & \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][116]~q ) ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][116]~q ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][116]~q ),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~202_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~202 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~202 .lut_mask = 64'h050505050505FFFF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~202 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y31_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal18~0 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal18~0_combout  = ( \u0|mm_interconnect_0|router_001|Equal7~0_combout  & ( (\u0|mm_interconnect_0|router_001|Equal1~0_combout  & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & 
// (\u0|mm_interconnect_0|router_001|Equal1~2_combout  & \u0|mm_interconnect_0|router_001|Equal1~1_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),
        .datac(!\u0|mm_interconnect_0|router_001|Equal1~2_combout ),
        .datad(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|router_001|Equal7~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router_001|Equal18~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal18~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal18~0 .lut_mask = 64'h0000000000010001;
defparam \u0|mm_interconnect_0|router_001|Equal18~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y31_N10
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[12] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|router_001|Equal18~0_combout ),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [12]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[12] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[12] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y32_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_012|last_cycle~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout  = ( \u0|mm_interconnect_0|router_001|Equal18~0_combout  & ( (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [12]))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [12]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|router_001|Equal18~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_012|last_cycle~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_012|last_cycle~0 .lut_mask = 64'h000000000C0F0C0F;
defparam \u0|mm_interconnect_0|cmd_mux_012|last_cycle~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y32_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y32_N41
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y32_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout  = ( \u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout  & ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout  & ( (\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout ),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h0000050500000000;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y32_N29
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X15_Y32_N47
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";
// synopsys translate_on

// Location: FF_X15_Y31_N11
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";
// synopsys translate_on

// Location: FF_X11_Y35_N5
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y35_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y35_N53
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y35_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARLEN [0] & ( 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] 
// $ (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0] & ( 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg 
// [2] $ (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])))) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1])) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .lut_mask = 64'h1BB11BB10AA00AA0;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y35_N2
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y35_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout  = ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & ( 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg 
// [2])) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout )))) ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & ( 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q 
//  & (((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout )))) ) ) ) # ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( 
// !\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( !\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & ( 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),
        .datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .lut_mask = 64'h0808A2A2085DA2F7;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y35_N56
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y35_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & 
// ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] $ 
// (((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]))) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .lut_mask = 64'hAAAAAAAA66AA66AA;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y35_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout  = ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # ((\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .lut_mask = 64'hABABABAB01010101;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y35_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  = ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & ( 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] & 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3])) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .lut_mask = 64'h0A000A0000000000;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y35_N50
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y35_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout  = ( \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & ( 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  $ 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & 
// ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  $ 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .lut_mask = 64'h30C030C035C535C5;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y32_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout  
// & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h0000000010101010;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y31_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  = ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & 
// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout ) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout ))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h000000000CCC0CCC;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y32_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout  = ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .lut_mask = 64'h55AF55AF50AA50AA;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y32_N53
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y32_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout  = ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .lut_mask = 64'h54AE54AE04FE04FE;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y32_N41
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y32_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout  = ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) # 
// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])))) ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) ) ) ) # ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// (((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .lut_mask = 64'h0B03F7FF0800F4FC;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y32_N14
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y32_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  = ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h4040404000000000;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y32_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout  = ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .lut_mask = 64'h04FE04FEF40EF40E;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y32_N38
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";
// synopsys translate_on

// Location: FF_X13_Y32_N31
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y32_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout  = ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) # 
// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))) ) ) ) # ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) # 
// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  & ( 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .lut_mask = 64'h0044FFEEF0440FEE;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y32_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout  = ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout  & ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout  & 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout  & 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout )) ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
        .datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .lut_mask = 64'hC000000000000000;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y32_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout  & ( 
// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout  & ( 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h004400440F4F0F4F;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y32_N17
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y32_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  = ( \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & ( 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & (\u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout  & 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q )) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .lut_mask = 64'h0000000000030003;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y32_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  & ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  & ( 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & 
// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .lut_mask = 64'h0045004555555555;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y32_N59
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y32_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  = ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & ( 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  $ 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & ( 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .lut_mask = 64'hC000C0003CC03CC0;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y32_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout  & ( 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout  & ( 
// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h0F4F0F4F00440044;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y32_N47
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y32_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  = ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .lut_mask = 64'hFF00FF0000000000;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y32_N44
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y32_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q  & ( 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q 
// )) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q  & ( 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q 
// ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h00AA00AA000A000A;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y32_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & ( (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & 
// !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .lut_mask = 64'hFFFFFFFFF000F000;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y32_N11
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .power_up = "low";
// synopsys translate_on

// Location: FF_X15_Y32_N8
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";
// synopsys translate_on

// Location: FF_X15_Y32_N50
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X15_Y32_N41
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y32_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~1_combout  = ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & ( 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1])) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~1 .lut_mask = 64'hA000A00000000000;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y32_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~2_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~1_combout  & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & 
// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout ))) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~1_combout  & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout  & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~2 .lut_mask = 64'h0F000F00CF00CF00;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y32_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout  = ( !\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .lut_mask = 64'hFFFFFFFF00000000;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y32_N52
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y32_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~2_combout  & 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q )) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~2_combout ))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~2_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .lut_mask = 64'h3303330330003000;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y32_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  = ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  & ( (!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]) # ((!\u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout ) # 
// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout 
// ))) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .lut_mask = 64'hFFEFFFEF00000000;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y35_N20
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y35_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout  = ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1])) ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout )))) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1])) ) ) ) # ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout  & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .lut_mask = 64'h00A0AA0A11B1BB1B;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y35_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout  = ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout  & ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout  & ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout  & ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout  & ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  ) ) ) # ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout  & ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout  & ( 
// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout  & 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout  & 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ))) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout  & ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout  & ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
        .datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .lut_mask = 64'h00FF80FF00FF00FF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y35_N26
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y32_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q  & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) 
// # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q  & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) 
// # ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout  & (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q  & 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout ))) ) ) ) # ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q  & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  
// & \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q  & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout  & 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q  & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout ),
        .datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .lut_mask = 64'h02000303CECCCFCF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y32_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout  & ( 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout  & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout  & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1])) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'h0500050055005500;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y32_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout  = ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout 
// ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .lut_mask = 64'hFF00FF00F000F000;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y32_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout  = ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( ((\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & (\u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout  & 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ))) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( (\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & (\u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout  & 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q )) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .lut_mask = 64'h001100110F1F0F1F;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y32_N17
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y31_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~0_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & ( 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~0 .lut_mask = 64'h0000000030F030F0;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y31_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override~feeder (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y31_N41
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y31_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg~0_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override~q  & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout  
// & (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~0_combout  & \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter [0])) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~0_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg~0 .lut_mask = 64'h0000000002020202;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y31_N20
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y31_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|comb~0_combout  & ( \u0|hps_0|fpga_interfaces|h2f_RREADY [0] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|comb~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y31_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|write~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|write~0_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout  & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~0_combout  ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout  & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~0_combout  & \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~0_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|write~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|write~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h000F000F0F0F0F0F;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|write~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y31_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[0]~1_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|write~0_combout  ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|write~0_combout  & ( 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0] & (((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout ) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1])) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|write~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h00F700F7FFFFFFFF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y31_N5
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X15_Y31_N2
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][129] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][129]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y31_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~1_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~0_combout  & ( ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][129]~q )) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~0_combout  & ( 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][129]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][129]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h003300330F3F0F3F;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y31_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout  = (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0]) # ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout  & 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout ))

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0]),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hBABABABABABABABA;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y31_N26
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][129] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y31_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|read~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|read~0_combout  = ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0] & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][129]~q  & ( 
// (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0]) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0]))) ) ) ) # ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0] & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][129]~q  & ( (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & 
// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0]) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0]))) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0] & ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][129]~q  & ( (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0]) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0]))) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0]),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0]),
        .datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0]),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|read~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|read~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|read~0 .lut_mask = 64'h050F050F050F0000;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|read~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y31_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[1]~1_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|read~0_combout  & 
// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [1]) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0]))) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0] & ( 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|read~0_combout  & \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [1]) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|read~0_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[1]~1 .lut_mask = 64'h00F000F050F050F0;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[1]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y31_N53
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y31_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[0]~0_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|read~0_combout  & ( ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0] 
// & \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|read~0_combout  & ( 
// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [1])) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0]) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|read~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h50FF50FF0F5F0F5F;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y31_N50
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y31_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|comb~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|comb~0_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][129]~q  & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0] ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][129]~q  & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0] & ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0]) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0]))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0]),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|comb~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|comb~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|comb~0 .lut_mask = 64'h005F005F00FF00FF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|comb~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y32_N23
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][76] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][76]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y32_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~5 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~5_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][76]~q  ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][76]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h0505050500FF00FF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y32_N11
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][76] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~5_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][76]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";
// synopsys translate_on

// Location: FF_X13_Y32_N59
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][75] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][75]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y32_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~6 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~6_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][75]~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][75]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][75]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h003300330C3F0C3F;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y32_N59
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~6_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";
// synopsys translate_on

// Location: FF_X13_Y32_N20
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][74] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~7_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][74]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y32_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~7 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~7_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) # 
// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])))) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & 
// (((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][74]~q )))) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & 
// (((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][74]~q )))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][74]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h043704378CBF8CBF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y32_N35
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~7_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";
// synopsys translate_on

// Location: FF_X13_Y32_N56
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][77] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][77]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y32_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~4 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~4_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][77]~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][77]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][77]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~4 .lut_mask = 64'h003300330C3F0C3F;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y32_N32
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][77] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~4_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][77]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y32_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~0_combout  = (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][76]~q  & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75]~q  & 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q  & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][77]~q )))

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][77]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~0 .lut_mask = 64'h8000800080008000;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y32_N23
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_busy (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y32_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q  & ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y32_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout  & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout  & 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout  & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q )) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h3000300030303030;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y32_N50
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y32_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~2_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & ( 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4])) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & ( 
// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3])) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h7F7F7F7F80808080;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~2 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y32_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~1_combout  = !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][77]~q  $ (((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][76]~q  & 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75]~q  & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ))))

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][77]~q ),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h78F078F078F078F0;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y32_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~1_combout  & ( 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout  & 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~2_combout )) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~1_combout  & ( 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ) # 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~2_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~2_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h0F0A0F0A05000500;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y32_N17
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y32_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1_combout  = ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3])) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1 .lut_mask = 64'h8080808000000000;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y32_N29
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][78] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][78]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y32_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~3 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~3_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][78]~q  & ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][78]~q  & ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][78]~q  & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][78]~q ),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h00000F0F50505F5F;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y32_N56
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][78] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~3_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][78]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y32_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][78]~q  & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout  & 
// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~0_combout )) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1_combout ))))) ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][78]~q  & ( 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~0_combout )) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1_combout ))))) ) ) ) # ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][78]~q  & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout  & 
// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~0_combout )) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1_combout ))))) ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][78]~q  & ( 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~0_combout )) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1_combout ))))) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~0_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][78]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h1103113022032230;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y32_N2
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y32_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1_combout  & ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][78]~q  & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout  & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6])) ) ) ) # ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1_combout  & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][78]~q  & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout  & 
// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~0_combout ))) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6])))) ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1_combout  & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][78]~q  & ( 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout  & 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~0_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~0_combout ),
        .datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1_combout ),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][78]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h0022103200001010;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y32_N19
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y32_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q  ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q  & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout ) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [7]))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h00AF00AF00FF00FF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y32_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q  & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout  & 
// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75]~q )) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))))) ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q  & ( 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75]~q )) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))))) ) ) ) # ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q  & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout  & 
// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75]~q )) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))))) ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q  & ( 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75]~q )) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))))) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),
        .datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h00D8008D00720027;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y32_N44
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y32_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~0_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4] ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] $ (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h33CC33CCFF00FF00;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y32_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout  & ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q  & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][76]~q ))) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~0_combout )) ) ) ) # ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout  & ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q  & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][76]~q  $ (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75]~q )))) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~0_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~0_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h0000CA3A00003A3A;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y32_N38
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y32_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout  = ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6])) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'h8080808000000000;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y32_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~0_combout  = ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75]~q  & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q  & ( 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q  & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][76]~q  & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][78]~q  & 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][77]~q ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][78]~q ),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][77]~q ),
        .datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h0000000080000000;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y30_N20
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][66]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y30_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~2_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & ( 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][66]~q ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][66]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][66]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~2 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y30_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][66]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][66]~feeder_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~2_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][66]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][66]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][66]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][66]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y30_N38
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][66]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][66]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y30_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][66]~q  & ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout  & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|comb~0_combout ) # 
// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout  & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~0_combout )) ) ) ) # ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][66]~q  & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout  & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|comb~0_combout ) # 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~0_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|comb~0_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][66]~q ),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h0000FAFA0000EAEA;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y31_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[1]~0_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|write~0_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout  & ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used 
// [0]))) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout  & (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1])))) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout  & (((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0])))) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|write~0_combout  & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout ) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0]),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|write~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[1]~0 .lut_mask = 64'h331133110F270F27;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[1]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y31_N14
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y31_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  = ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & 
// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout ) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout ))) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hFFFFFFFF0CCC0CCC;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y32_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  
// & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ) ) ) ) # ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  & ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  & ( 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ) ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .lut_mask = 64'h03030F0F00000C0C;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y32_N32
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y32_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout  = ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q  & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg 
// [1] & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]))) ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q  & 
// ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] 
// & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3])) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0 .lut_mask = 64'hA000000080000000;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y31_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter~0_combout  = (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout  & (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~0_combout  & 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override~q  & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter [0])))

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~0_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override~q ),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter [0]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter~0 .lut_mask = 64'h0200020002000200;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y31_N23
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y31_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override~q  & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter [0] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0 .lut_mask = 64'h0000000000FF00FF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y32_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & 
// (((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout )) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .lut_mask = 64'hCC4CCC0000000000;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y32_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q 
//  & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & ( 
// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3 .lut_mask = 64'h5D555D5508000800;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y32_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout  = ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  & 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout  & 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  & 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout  & 
// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4 .lut_mask = 64'hA080A000A080A000;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y32_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~0_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout  & ( 
// ((\u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout  & \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1])) # (\u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~q ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout  & ( (\u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~q  & ((!\u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout ) # 
// (!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]))) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~0 .lut_mask = 64'h00FA00FA05FF05FF;
defparam \u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y32_N2
dffeas \u0|mm_interconnect_0|cmd_mux_012|packet_in_progress (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_012|packet_in_progress .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_012|packet_in_progress .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y32_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_012|update_grant~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_012|update_grant~0_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout  & ( (!\u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~q  & 
// ((!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]) # (!\u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout ))) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout  
// & ( (!\u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~q ) # ((\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & \u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_012|update_grant~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_012|update_grant~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_012|update_grant~0 .lut_mask = 64'hAAAFAAAFAAA0AAA0;
defparam \u0|mm_interconnect_0|cmd_mux_012|update_grant~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y32_N50
dffeas \u0|mm_interconnect_0|cmd_mux_012|saved_grant[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|cmd_mux_012|update_grant~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_012|saved_grant[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_012|saved_grant[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y32_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_012|src_payload~11 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_012|src_payload~11_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [11] & ( \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_012|src_payload~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~11 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~11 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y32_N43
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_012|src_payload~11_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";
// synopsys translate_on

// Location: FF_X13_Y32_N44
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~20_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][116]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y32_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~20 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~20_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][116]~q  & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] ) ) # ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][116]~q  & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][116]~q  & ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][116]~q ),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~20 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~20 .lut_mask = 64'h0F0F0F0F0000FFFF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~20 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y30_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][116]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][116]~feeder_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~20_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~20_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][116]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][116]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][116]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][116]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y30_N19
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][116]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][116]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y31_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal1~5 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal1~5_combout  = ( \u0|mm_interconnect_0|router_001|Equal1~4_combout  & ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] ) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|router_001|Equal1~4_combout ),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router_001|Equal1~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal1~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal1~5 .lut_mask = 64'h0000AAAA00000000;
defparam \u0|mm_interconnect_0|router_001|Equal1~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y31_N1
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|router_001|Equal1~5_combout ),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y27_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_001|last_cycle~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q  & ( \u0|mm_interconnect_0|router_001|Equal1~4_combout  & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & 
// (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [1]))) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q  
// & ( \u0|mm_interconnect_0|router_001|Equal1~4_combout  & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & !\u0|hps_0|fpga_interfaces|h2f_ARADDR [19])) ) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [1]),
        .datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
        .dataf(!\u0|mm_interconnect_0|router_001|Equal1~4_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_001|last_cycle~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_001|last_cycle~0 .lut_mask = 64'h0000000020200020;
defparam \u0|mm_interconnect_0|cmd_mux_001|last_cycle~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y23_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override~feeder (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y23_N20
dffeas \u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y23_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override~q  & ( \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter [0] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y23_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y23_N53
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y23_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout  & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used 
// [1] & \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout 
// )) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'h0202020222222222;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y20_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y20_N14
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y20_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg 
// [2] & ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg 
// [2])))) # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & (!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]))) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])))) # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & (!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]))) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .lut_mask = 64'h10DC10DCDC10DC10;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y20_N35
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y20_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout  = ( 
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) # 
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1])))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout  & ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & ((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) 
// # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1])))) ) ) ) # ( 
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # 
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datae(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .lut_mask = 64'h0088CC44038BCF47;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y20_N56
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .power_up = "low";
// synopsys translate_on

// Location: FF_X13_Y20_N32
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y20_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] & ( 
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & 
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3])) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] & ( ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # 
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3])) # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg 
// [2]) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .lut_mask = 64'hF5FFF5FF0A000A00;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y20_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  & 
// ( (\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  & ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # 
// ((\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .lut_mask = 64'hCCDDCCDD00110011;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y20_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  = ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & ( 
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] & 
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3])) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .lut_mask = 64'h5000500000000000;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y20_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout  = ( \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & ( 
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  $ 
// (((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))))) # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout )))) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  $ (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .lut_mask = 64'h44884488478B478B;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y20_N41
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .power_up = "low";
// synopsys translate_on

// Location: FF_X13_Y20_N2
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y20_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout  = ( 
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ) # 
// ((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1])))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout  & ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) # 
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1])))) ) ) ) # ( 
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ) # 
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout  & ( 
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & 
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .lut_mask = 64'h4400BB00440FBB0F;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y23_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  = ( \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & ( 
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & 
// \u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout )) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .lut_mask = 64'h0000000000030003;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y23_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  & ( 
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  & ( 
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & 
// ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout 
// )))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .lut_mask = 64'h0045004555555555;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y23_N11
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y23_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q 
//  & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout ) # (\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout ))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h0000000030F030F0;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y23_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout  = ( 
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg 
// [2]))) # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg 
// [2])) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .lut_mask = 64'h00FF00FFFA0AFA0A;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y23_N5
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y23_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout  = ( 
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] 
// $ (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) # 
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) # 
// ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .lut_mask = 64'h00FF00FFE22EE22E;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y23_N2
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y23_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout  = ( 
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( 
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg 
// [2])) # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) # 
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) 
// ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( 
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] 
// & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) # 
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) 
// ) ) # ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datae(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .lut_mask = 64'h0000FFFFB3807F4C;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y23_N14
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y23_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  = ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( 
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg 
// [2])) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h5000500000000000;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y23_N41
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y23_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout  = ( 
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  $ (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) # 
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg 
// [2] & ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  $ 
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) # 
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg 
// [5])) # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .lut_mask = 64'h1DF31DF30CE20CE2;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y23_N19
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y23_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout  = ( 
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] 
// & ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) # 
// ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) # (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) 
// ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( 
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & ( 
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) ) # 
// ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg 
// [5] & ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout 
// )))) # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) # 
// ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg 
// [5] & ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout )))) 
// # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .datae(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .lut_mask = 64'h10DCFE321010FEFE;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y23_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout  = ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout  & 
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout  & 
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout  & 
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .lut_mask = 64'h8000800000000000;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y23_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout  = (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & 
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout )))

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h0010001000100010;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y23_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout  & ( 
// ((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout  & ( (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) 
// )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h004400440F4F0F4F;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y23_N8
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y23_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  = ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  
// & ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .lut_mask = 64'hCCCCCCCC00000000;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y23_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout  = ( \u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout  & ( (\u0|mm_interconnect_0|cmd_mux_001|saved_grant 
// [1] & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout  & \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q )) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h0000000004040404;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y23_N17
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y23_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q  & ( 
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & 
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout )) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q  & ( 
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h0C0C0C0C000C000C;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y23_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout  = !\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .lut_mask = 64'hF0F0F0F0F0F0F0F0;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y23_N38
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";
// synopsys translate_on

// Location: FF_X14_Y23_N5
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";
// synopsys translate_on

// Location: FF_X14_Y23_N38
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X14_Y23_N55
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y23_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~1_combout  = ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & ( 
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & 
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0])) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~1 .lut_mask = 64'hA000A00000000000;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y23_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & ( (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & 
// !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .lut_mask = 64'hFFFFFFFFF000F000;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y23_N41
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y23_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~2_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout  & ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] ) ) # ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout  & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~1_combout  & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q  & 
// !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1])) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~1_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~2 .lut_mask = 64'h44004400FF00FF00;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~2 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y23_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( 
// (!\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~2_combout  & ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ))) # 
// (\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~2_combout  & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~2_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .lut_mask = 64'h00000000F0CCF0CC;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y23_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  = ( \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & ( \u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  & ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) # 
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & ( \u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout  & ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & ( !\u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout  & ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & ( !\u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout  & ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
        .datae(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .lut_mask = 64'hFF00FF00FF00AF00;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y20_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  & ( 
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  & ( 
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout  & 
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout  & 
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout  & 
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ))) ) ) ) # ( 
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  & ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout  ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),
        .datae(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .lut_mask = 64'h0000FFFF8000FFFF;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y20_N44
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y23_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) ) # 
// ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .lut_mask = 64'hFF00FF00F000F000;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y23_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & ( 
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ))) # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & 
// (((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout )) # 
// (\u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout ))) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & ( (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .lut_mask = 64'h0303030303570357;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y23_N53
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y23_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & ( 
// (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout ) # (\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout ))) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hFFFFFFFF0AAA0AAA;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y23_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout  & ( 
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout  
// & ( ((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))) # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h0F4F0F4F00440044;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y23_N53
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y23_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & ( 
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  $ (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ))) # 
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q 
//  & !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & ( 
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .lut_mask = 64'h8080808068686868;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y23_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  & ( 
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  & ( 
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & ((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) # 
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .lut_mask = 64'h0555055500500050;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y23_N59
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y23_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q  & ( 
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q  & ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) # 
// (((!\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout  & !\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout )) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1])) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q  & ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q  & ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  ) ) ) # ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q  
// & ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q  & ( (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// (((!\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout  & !\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout )) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]))) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout ),
        .datae(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .lut_mask = 64'h00002303CCCCEFCF;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y23_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  
// & ( (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q 
//  & (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) # 
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & (((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q )))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3 .lut_mask = 64'h7430743030303030;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y23_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & 
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ) ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & 
// (((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # (\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout )) # (\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout ))) 
// ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .datae(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .lut_mask = 64'hF700F00000000000;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y23_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout  = ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout  & ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) # 
// ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4 .lut_mask = 64'hF080F08000000000;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y23_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~q  & ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout  ) ) # 
// ( !\u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~q  & ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout  & ( (\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & 
// \u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout ) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~q  & ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout  & ( 
// (!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]) # (!\u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~q ),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~0 .lut_mask = 64'h0000FAFA0505FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y23_N35
dffeas \u0|mm_interconnect_0|cmd_mux_001|packet_in_progress (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_001|packet_in_progress .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_001|packet_in_progress .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y23_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_001|update_grant~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_001|update_grant~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout  & ( 
// (!\u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~q  & !\u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout ) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & ( 
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout  & ( !\u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~q  ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout  & ( (!\u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~q ) # (\u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout ) ) ) ) # ( 
// !\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout  & ( !\u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~q  ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_001|update_grant~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_001|update_grant~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_001|update_grant~0 .lut_mask = 64'hAAAAAFAFAAAAA0A0;
defparam \u0|mm_interconnect_0|cmd_mux_001|update_grant~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y23_N23
dffeas \u0|mm_interconnect_0|cmd_mux_001|saved_grant[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|cmd_mux_001|update_grant~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_001|saved_grant[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_001|saved_grant[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X14_Y23_N35
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y23_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout  = ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & ( 
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & 
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & 
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & 
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1])) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .datae(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0 .lut_mask = 64'h8080000080000000;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y23_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter~0_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override~q  & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~0_combout  & 
// (!\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout  & !\u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter [0])) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter~0 .lut_mask = 64'h0000000050005000;
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y23_N35
dffeas \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y23_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg~0_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override~q  & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~0_combout  & 
// (\u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter [0] & !\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter [0]),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg~0 .lut_mask = 64'h0000000005000500;
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y23_N26
dffeas \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X11_Y23_N38
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][129] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][129]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y23_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~1_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ( ((\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout  & 
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~0_combout )) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][129]~q ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ( 
// (\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout  & \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~0_combout ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][129]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h0303030303FF03FF;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y23_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_agent|comb~0_combout  & ( \u0|hps_0|fpga_interfaces|h2f_RREADY [0] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent|comb~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0 .lut_mask = 64'h0000000000FF00FF;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y23_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0_combout  & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [0]) # 
// (!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2_combout ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0_combout  & ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [0] ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hAAAAAAAAFAFAFAFA;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y23_N59
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][129] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][129]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y23_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|read~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|read~0_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][129]~q  
// & ((\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0]) # (\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0])))) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [0] & ( 
// (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ((\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0]) # (\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0]))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0]),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0]),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|read~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|read~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|read~0 .lut_mask = 64'h1313131313001300;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|read~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y23_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[1]~1_combout  = ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|read~0_combout  & ( ((\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0] & 
// \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0]),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0]),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|read~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[1]~1 .lut_mask = 64'h03FF03FF00000000;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[1]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y23_N8
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y23_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[0]~0_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|read~0_combout  & ( ((\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0] & 
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|read~0_combout  & ( 
// ((\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1])) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0]) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|read~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h50FF50FF0F5F0F5F;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y23_N41
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y23_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|comb~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent|comb~0_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [0] ) ) # ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0] & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [0] & ((\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][129]~q ) # 
// (\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0]))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [0]),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|comb~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|comb~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|comb~0 .lut_mask = 64'h1155115555555555;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|comb~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y23_N29
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_busy (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";
// synopsys translate_on

// Location: FF_X13_Y23_N47
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][77] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][77]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y23_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~5 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~5_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][77]~q  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][77]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h0505050500FF00FF;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y23_N53
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][77] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~5_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][77]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";
// synopsys translate_on

// Location: FF_X14_Y23_N29
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][76] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~6_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][76]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y23_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~6 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~6_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]))) # 
// (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][76]~q )) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][76]~q  & 
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][76]~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h005500550F550F55;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y23_N32
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][76] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~6_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][76]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";
// synopsys translate_on

// Location: FF_X13_Y23_N44
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][74] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][74]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y23_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~8 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~8_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) # 
// ((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])))) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & 
// (((\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][74]~q )))) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & 
// (((\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][74]~q )))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][74]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~8 .lut_mask = 64'h043704378CBF8CBF;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y23_N17
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~8_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";
// synopsys translate_on

// Location: FF_X15_Y23_N50
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][75] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~7_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][75]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y23_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~7 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~7_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( 
// (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) # 
// (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][75]~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][75]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][75]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h000F000F303F303F;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y23_N8
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~7_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y23_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~1_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75]~q  & ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][77]~q  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75]~q  & ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][77]~q  $ (((!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][76]~q  & 
// !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74]~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][77]~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h5AAA5AAAAAAAAAAA;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X10_Y23_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2_combout  & 
// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2_combout  & 
// !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) ) ) # ( \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2_combout  & (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74]~q 
//  $ (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75]~q ))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2_combout  & (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74]~q 
//  $ (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75]~q ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datae(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h4411441150500505;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y23_N20
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y21_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~0_combout  = ( !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( 
// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] ) ) # ( \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( 
// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h5555AAAAFFFF0000;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X10_Y23_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2_combout  & ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74]~q  
// & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][76]~q )) # 
// (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ((!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~0_combout ))) ) ) ) # ( 
// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2_combout  & ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74]~q  & ( 
// (!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][76]~q  $ (((\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75]~q ))))) # 
// (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (((!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~0_combout )))) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datae(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h0000D87200007272;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y23_N44
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";
// synopsys translate_on

// Location: FF_X13_Y23_N56
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][78] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][78]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y23_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~4 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~4_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( 
// (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) # 
// (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][78]~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][78]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][78]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~4 .lut_mask = 64'h003300330C3F0C3F;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y23_N11
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][78] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~4_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][78]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y23_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~0_combout  = ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74]~q  & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75]~q  & 
// (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][77]~q  & !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][76]~q )) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][77]~q ),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~0 .lut_mask = 64'hC000C00000000000;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X10_Y21_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~1_combout  = ( !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & 
// !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~1 .lut_mask = 64'hA0A0000000000000;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X10_Y23_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( 
// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2_combout  & 
// !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~1_combout ) ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( 
// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2_combout  & 
// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~1_combout ) ) ) ) # ( \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2_combout  & (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][78]~q 
//  $ (!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2_combout  & (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][78]~q 
//  $ (!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~0_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][78]~q ),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~1_combout ),
        .datae(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h1414141400555500;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y23_N56
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y23_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~3_combout  = ( !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// (!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & 
// !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~3 .lut_mask = 64'hC000C00000000000;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X10_Y23_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2_combout  & ( 
// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & 
// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~1_combout ) ) ) ) # ( \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2_combout  & ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][78]~q  & \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~0_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][78]~q ),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~1_combout ),
        .datae(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h00000C0C000000AA;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y23_N26
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y23_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [7] & ( 
// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_busy~q  ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [7] & ( 
// (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_busy~q  & ((!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~3_combout ) # 
// (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~3_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h5055505555555555;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X10_Y23_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( 
// (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2_combout  & ((!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) # 
// (!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_busy~q ))) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74]~q  & (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2_combout  & ((!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) # 
// (!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_busy~q )))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h00C800C800FA00FA;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y23_N2
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y23_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~2_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5] ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5] $ (((!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & 
// !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h5FA05FA0FF00FF00;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X10_Y23_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( 
// (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2_combout  & !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~2_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2_combout  & 
// !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~1_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~1_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~2_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h5050505055005500;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y23_N41
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y23_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~0_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_busy~q  & 
// (!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & (!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & 
// !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]))) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datae(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h0000400000000000;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X10_Y23_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~1_combout  = ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75]~q  & ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74]~q  & ( 
// (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][77]~q  & (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][76]~q  & (!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_busy~q  & 
// !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][78]~q ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][77]~q ),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][78]~q ),
        .datae(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75]~q ),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'h0000000080000000;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y23_N41
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";
// synopsys translate_on

// Location: FF_X15_Y23_N47
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][66]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y23_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~3_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][66]~q  & ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] ) ) # ( 
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][66]~q  & ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] 
// ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][66]~q  & ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ( 
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][66]~q ),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h0F0F0F0F0000FFFF;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y23_N14
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~3_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][66]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y23_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][66]~q  & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent|comb~0_combout ) # 
// ((!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~0_combout  & !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~1_combout )) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent|comb~0_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][66]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h00000000FCCCFCCC;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y23_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[1]~0_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0_combout  & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|write~0_combout  & 
// (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2_combout  & ((\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1])))) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|write~0_combout  & 
// ((!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2_combout  & ((\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]))) # (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2_combout  & 
// (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [0])))) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0_combout  & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|write~0_combout  & 
// ((\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]))) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|write~0_combout  & (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [0])) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|write~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [0]),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[1]~0 .lut_mask = 64'h05AF05AF01670167;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[1]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y23_N50
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X15_Y23_N59
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y23_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~0_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used 
// [1] & ((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]) # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~0 .lut_mask = 64'h000000000CCC0CCC;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y23_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|write~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|write~0_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout  & ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~0_combout  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout  & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~0_combout  & \u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~0_combout ),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|write~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|write~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h0055005555555555;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|write~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y23_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[0]~1_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [0]) # 
// (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|write~0_combout ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ( ((\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [0] & 
// ((!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0_combout ) # (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2_combout )))) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|write~0_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|write~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h55F755F755FF55FF;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y23_N53
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y23_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][129]~q  & ( !\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0] & ( 
// (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [0] & !\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0]) ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][129]~q  & ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0] & ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0] ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][129]~q ),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid .lut_mask = 64'hF0F0A0A000000000;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y25_N56
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~21_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][116]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y24_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|src_data[116] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|src_data [116] = ( \u0|mm_interconnect_0|cmd_mux|saved_grant [1] & ( ((\u0|hps_0|fpga_interfaces|h2f_AWID [11] & \u0|mm_interconnect_0|cmd_mux|saved_grant [0])) # (\u0|hps_0|fpga_interfaces|h2f_ARID [11]) ) ) # ( 
// !\u0|mm_interconnect_0|cmd_mux|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_AWID [11] & \u0|mm_interconnect_0|cmd_mux|saved_grant [0]) ) )

        .dataa(gnd),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_AWID [11]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),
        .datad(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux|src_data [116]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|src_data[116] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|src_data[116] .lut_mask = 64'h003300330F3F0F3F;
defparam \u0|mm_interconnect_0|cmd_mux|src_data[116] .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y19_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y19_N50
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";
// synopsys translate_on

// Location: FF_X27_Y30_N14
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_demux_001|src0_valid~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y30_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|src_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|src_valid~0_combout  = ( \u0|mm_interconnect_0|cmd_mux|saved_grant [1] & ( \u0|mm_interconnect_0|cmd_demux_001|src0_valid~0_combout  & ( (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & 
// ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [0]))) ) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [0]),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
        .dataf(!\u0|mm_interconnect_0|cmd_demux_001|src0_valid~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux|src_valid~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|src_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|src_valid~0 .lut_mask = 64'h0000000000005151;
defparam \u0|mm_interconnect_0|cmd_mux|src_valid~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y25_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|router|src_data[103]~0 (
// Equation(s):
// \u0|mm_interconnect_0|router|src_data[103]~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout  & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout  & 
// (\u0|mm_interconnect_0|router|Equal7~1_combout  & (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~3_combout  & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout ))) ) ) # ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout  & ( (\u0|mm_interconnect_0|router|Equal7~1_combout  & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout  & 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~3_combout  & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout )) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout  & (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~3_combout  & 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout ),
        .datab(!\u0|mm_interconnect_0|router|Equal7~1_combout ),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~3_combout ),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router|src_data[103]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router|src_data[103]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router|src_data[103]~0 .lut_mask = 64'h0210021000100010;
defparam \u0|mm_interconnect_0|router|src_data[103]~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y25_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|router|Equal6~7 (
// Equation(s):
// \u0|mm_interconnect_0|router|Equal6~7_combout  = ( \u0|mm_interconnect_0|router|Equal6~6_combout  & ( \u0|mm_interconnect_0|router|Equal6~8_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|router|Equal6~6_combout ),
        .dataf(!\u0|mm_interconnect_0|router|Equal6~8_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router|Equal6~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router|Equal6~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router|Equal6~7 .lut_mask = 64'h000000000000FFFF;
defparam \u0|mm_interconnect_0|router|Equal6~7 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y25_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|src0_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|src0_valid~0_combout  = ( \u0|mm_interconnect_0|router|Equal7~1_combout  & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout  & 
// ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~3_combout  & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout  & 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout )) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~3_combout  & 
// ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout ))))) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~3_combout ),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout ),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout ),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|router|Equal7~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux|src0_valid~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|src0_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|src0_valid~0 .lut_mask = 64'h0000000002110211;
defparam \u0|mm_interconnect_0|cmd_demux|src0_valid~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y25_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|src0_valid~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|src0_valid~1_combout  = ( !\u0|mm_interconnect_0|router|src_data[103]~0_combout  & ( (!\u0|mm_interconnect_0|router|Equal6~7_combout  & (!\u0|mm_interconnect_0|router|Equal14~1_combout  & 
// (!\u0|mm_interconnect_0|router|Equal20~0_combout  & !\u0|mm_interconnect_0|cmd_demux|src0_valid~0_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|router|Equal6~7_combout ),
        .datab(!\u0|mm_interconnect_0|router|Equal14~1_combout ),
        .datac(!\u0|mm_interconnect_0|router|Equal20~0_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_demux|src0_valid~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|router|src_data[103]~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux|src0_valid~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|src0_valid~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|src0_valid~1 .lut_mask = 64'h8000800000000000;
defparam \u0|mm_interconnect_0|cmd_demux|src0_valid~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y25_N8
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_demux|src0_valid~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y25_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|src0_valid~2 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|src0_valid~2_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout  & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q ) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [0]) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [0]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux|src0_valid~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|src0_valid~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|src0_valid~2 .lut_mask = 64'h00000000FF0FFF0F;
defparam \u0|mm_interconnect_0|cmd_demux|src0_valid~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y25_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|src0_valid~3 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|src0_valid~3_combout  = ( !\u0|mm_interconnect_0|cmd_demux|src0_valid~0_combout  & ( \u0|mm_interconnect_0|cmd_demux|src0_valid~2_combout  & ( (!\u0|mm_interconnect_0|router|src_data[103]~0_combout  & 
// (!\u0|mm_interconnect_0|router|Equal20~0_combout  & (!\u0|mm_interconnect_0|router|Equal14~1_combout  & !\u0|mm_interconnect_0|router|Equal6~7_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|router|src_data[103]~0_combout ),
        .datab(!\u0|mm_interconnect_0|router|Equal20~0_combout ),
        .datac(!\u0|mm_interconnect_0|router|Equal14~1_combout ),
        .datad(!\u0|mm_interconnect_0|router|Equal6~7_combout ),
        .datae(!\u0|mm_interconnect_0|cmd_demux|src0_valid~0_combout ),
        .dataf(!\u0|mm_interconnect_0|cmd_demux|src0_valid~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux|src0_valid~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|src0_valid~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|src0_valid~3 .lut_mask = 64'h0000000080000000;
defparam \u0|mm_interconnect_0|cmd_demux|src0_valid~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y24_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout  = ( \u0|mm_interconnect_0|cmd_mux|src_valid~0_combout  & ( \u0|mm_interconnect_0|cmd_demux|src0_valid~3_combout  
// & ( (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) ) ) ) # 
// ( !\u0|mm_interconnect_0|cmd_mux|src_valid~0_combout  & ( \u0|mm_interconnect_0|cmd_demux|src0_valid~3_combout  & ( (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & 
// (\u0|mm_interconnect_0|cmd_mux|saved_grant [0] & \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q )) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux|src_valid~0_combout  & ( 
// !\u0|mm_interconnect_0|cmd_demux|src0_valid~3_combout  & ( (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & 
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) ) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .datab(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datae(!\u0|mm_interconnect_0|cmd_mux|src_valid~0_combout ),
        .dataf(!\u0|mm_interconnect_0|cmd_demux|src0_valid~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h000000AA002200AA;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y24_N2
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux|src_data [116]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y25_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~21 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~21_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] & ( 
// (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][116]~q ) ) ) # ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] & ( (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][116]~q ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][116]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~21_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~21 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~21 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~21 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y18_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|src_data[35] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|src_data [35] = ( \u0|mm_interconnect_0|cmd_mux|saved_grant [0] & ( (\u0|mm_interconnect_0|cmd_mux|saved_grant [1]) # (\u0|hps_0|fpga_interfaces|h2f_WSTRB [3]) ) ) # ( !\u0|mm_interconnect_0|cmd_mux|saved_grant [0] & ( 
// \u0|mm_interconnect_0|cmd_mux|saved_grant [1] ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [3]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux|src_data [35]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|src_data[35] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|src_data[35] .lut_mask = 64'h0F0F5F5F0F0F5F5F;
defparam \u0|mm_interconnect_0|cmd_mux|src_data[35] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y18_N41
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux|src_data [35]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y17_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|src_data[34] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|src_data [34] = ( \u0|hps_0|fpga_interfaces|h2f_WSTRB [2] & ( (\u0|mm_interconnect_0|cmd_mux|saved_grant [1]) # (\u0|mm_interconnect_0|cmd_mux|saved_grant [0]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_WSTRB [2] & ( 
// \u0|mm_interconnect_0|cmd_mux|saved_grant [1] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
        .datad(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux|src_data [34]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|src_data[34] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|src_data[34] .lut_mask = 64'h00FF00FF0FFF0FFF;
defparam \u0|mm_interconnect_0|cmd_mux|src_data[34] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y17_N32
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux|src_data [34]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y24_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|src_data[32] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|src_data [32] = ( \u0|mm_interconnect_0|cmd_mux|saved_grant [1] ) # ( !\u0|mm_interconnect_0|cmd_mux|saved_grant [1] & ( (\u0|mm_interconnect_0|cmd_mux|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_WSTRB [0]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux|src_data [32]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|src_data[32] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|src_data[32] .lut_mask = 64'h03030303FFFFFFFF;
defparam \u0|mm_interconnect_0|cmd_mux|src_data[32] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y24_N56
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux|src_data [32]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y18_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|src_data[33] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|src_data [33] = ( \u0|mm_interconnect_0|cmd_mux|saved_grant [1] ) # ( !\u0|mm_interconnect_0|cmd_mux|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_WSTRB [1] & \u0|mm_interconnect_0|cmd_mux|saved_grant [0]) ) )

        .dataa(gnd),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [1]),
        .datac(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux|src_data [33]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|src_data[33] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|src_data[33] .lut_mask = 64'h0303FFFF0303FFFF;
defparam \u0|mm_interconnect_0|cmd_mux|src_data[33] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y18_N20
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux|src_data [33]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y24_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|src_data[88] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|src_data [88] = ( \u0|mm_interconnect_0|cmd_mux|saved_grant [0] & ( ((\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & \u0|mm_interconnect_0|cmd_mux|saved_grant [1])) # (\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]) ) ) # ( 
// !\u0|mm_interconnect_0|cmd_mux|saved_grant [0] & ( (\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & \u0|mm_interconnect_0|cmd_mux|saved_grant [1]) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]),
        .datac(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux|src_data [88]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|src_data[88] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|src_data[88] .lut_mask = 64'h0505050537373737;
defparam \u0|mm_interconnect_0|cmd_mux|src_data[88] .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y24_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|src_data[87] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|src_data [87] = ( \u0|mm_interconnect_0|cmd_mux|saved_grant [0] & ( ((\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & \u0|mm_interconnect_0|cmd_mux|saved_grant [1])) # (\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]) ) ) # ( 
// !\u0|mm_interconnect_0|cmd_mux|saved_grant [0] & ( (\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & \u0|mm_interconnect_0|cmd_mux|saved_grant [1]) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]),
        .datac(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux|src_data [87]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|src_data[87] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|src_data[87] .lut_mask = 64'h0505050537373737;
defparam \u0|mm_interconnect_0|cmd_mux|src_data[87] .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y24_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout  = ( !\u0|mm_interconnect_0|cmd_mux|src_data [87] & ( !\u0|mm_interconnect_0|cmd_mux|src_data [88] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|cmd_mux|src_data [88]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux|src_data [87]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .lut_mask = 64'hFF00FF0000000000;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y24_N20
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y17_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent|WideOr0~0_combout  = ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q  & ( 
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & 
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]))) ) ) ) # ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q  & ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & 
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]))) ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q  & ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & 
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]))) ) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .datae(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent|WideOr0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|WideOr0~0 .lut_mask = 64'h8000800080000000;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|WideOr0~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y17_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter~2 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter~2_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter~0_combout  & ( !\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [0] $ 
// (!\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [1]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [0]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter~2 .lut_mask = 64'h0000000033CC33CC;
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y17_N26
dffeas \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y17_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_translator|waitrequest_reset_override~feeder (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_translator|waitrequest_reset_override~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_translator|waitrequest_reset_override~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y17_N41
dffeas \u0|mm_interconnect_0|led_pio_test_s1_translator|waitrequest_reset_override (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_translator|waitrequest_reset_override~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_translator|waitrequest_reset_override~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|waitrequest_reset_override .power_up = "low";
// synopsys translate_on

// Location: FF_X28_Y17_N46
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y17_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent|m0_read~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent|m0_read~0_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & ( 
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]) # (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent|m0_read~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|m0_read~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|m0_read~0 .lut_mask = 64'h000000000FFF0FFF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|m0_read~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y17_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg~0_combout  = ( !\u0|mm_interconnect_0|led_pio_test_s1_agent|WideOr0~0_combout  & ( (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|led_pio_test_s1_agent|m0_read~0_combout ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent|m0_read~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent|WideOr0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg~0 .lut_mask = 64'h0C0C0C0C00000000;
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y17_N14
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y17_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent|local_write~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent|local_write~0_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & ( 
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent|local_write~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|local_write~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|local_write~0 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|local_write~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y17_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent|m0_write (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent|m0_write~combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_agent|local_write~0_combout  & ( (!\u0|mm_interconnect_0|led_pio_test_s1_agent|WideOr0~0_combout  & 
// !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent|WideOr0~0_combout ),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent|local_write~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent|m0_write~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|m0_write .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|m0_write .lut_mask = 64'h00000000AA00AA00;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|m0_write .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y17_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter~0_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_agent|m0_write~combout  & ( (\u0|mm_interconnect_0|led_pio_test_s1_translator|waitrequest_reset_override~q  & 
// ((\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [0]) # (\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [1]))) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_agent|m0_write~combout  & ( 
// (\u0|mm_interconnect_0|led_pio_test_s1_translator|waitrequest_reset_override~q  & (\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg~0_combout  & ((!\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [0]) # 
// (\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [1])))) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [1]),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_translator|waitrequest_reset_override~q ),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [0]),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent|m0_write~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter~0 .lut_mask = 64'h0031003113131313;
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y17_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter~1_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter~0_combout  & ( !\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [0] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter~1 .lut_mask = 64'h00000000FF00FF00;
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y17_N11
dffeas \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y17_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~0_combout  = ( !\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [1] & ( \u0|mm_interconnect_0|led_pio_test_s1_translator|waitrequest_reset_override~q  ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_translator|waitrequest_reset_override~q ),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~0 .lut_mask = 64'h3333333300000000;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y17_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~4 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~4_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_agent|local_write~0_combout  & ( (\u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~0_combout  & 
// (!\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [0] $ (((\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|led_pio_test_s1_agent|WideOr0~0_combout ))))) ) ) # ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_agent|local_write~0_combout  & ( (\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [0] & \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~0_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent|WideOr0~0_combout ),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [0]),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~0_combout ),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent|local_write~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~4 .lut_mask = 64'h0303030309030903;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y17_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|write~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|write~0_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_agent|m0_read~0_combout  & ( 
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & 
// ((\u0|mm_interconnect_0|led_pio_test_s1_agent|WideOr0~0_combout ) # (\u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~4_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_agent|m0_read~0_combout  & ( 
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( (\u0|mm_interconnect_0|led_pio_test_s1_agent|local_write~0_combout  & 
// (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|led_pio_test_s1_agent|WideOr0~0_combout ) # (\u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~4_combout )))) ) ) ) # ( 
// \u0|mm_interconnect_0|led_pio_test_s1_agent|m0_read~0_combout  & ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( 
// (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|led_pio_test_s1_agent|WideOr0~0_combout ) # (\u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~4_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~4_combout ),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent|local_write~0_combout ),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent|WideOr0~0_combout ),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]),
        .datae(!\u0|mm_interconnect_0|led_pio_test_s1_agent|m0_read~0_combout ),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|write~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|write~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h00005F0013005F00;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|write~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y26_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y26_N26
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y19_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & ( 
// (!\u0|mm_interconnect_0|cmd_mux|src_valid~0_combout  & ((!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]) # (!\u0|mm_interconnect_0|cmd_demux|src0_valid~3_combout ))) ) ) # ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  )

        .dataa(!\u0|mm_interconnect_0|cmd_mux|src_valid~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
        .datad(!\u0|mm_interconnect_0|cmd_demux|src0_valid~3_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .lut_mask = 64'hFFFFFFFFAAA0AAA0;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y19_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout  = ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & ( 
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) # 
// ((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ) # (((!\u0|mm_interconnect_0|cmd_mux|saved_grant [1] & !\u0|mm_interconnect_0|cmd_mux|saved_grant [0])) # 
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ))) ) ) # ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & ( 
// ((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ) # 
// ((\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & 
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datae(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
        .datag(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .extended_lut = "on";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .lut_mask = 64'hFFECFF00FFFFFF03;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y19_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1_combout  = ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1 .lut_mask = 64'hFFFFFFFF00000000;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y19_N20
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y19_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( 
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & \u0|mm_interconnect_0|cmd_mux|saved_grant [0]) ) ) ) # ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q 
//  & ( (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & 
// \u0|mm_interconnect_0|cmd_mux|saved_grant [0])) ) ) ) # ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & (\u0|mm_interconnect_0|cmd_mux|saved_grant [0] & 
// ((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ) # (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )))) ) ) ) 
// # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & 
// \u0|mm_interconnect_0|cmd_mux|saved_grant [0])) ) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .datad(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
        .datae(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .lut_mask = 64'h0030003100300033;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y19_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  & ( 
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & !\u0|mm_interconnect_0|cmd_mux|saved_grant [1]) ) ) # ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  & ( (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// !\u0|mm_interconnect_0|cmd_mux|saved_grant [1]))) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .lut_mask = 64'h010001000F000F00;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y17_N8
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y17_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~0_combout  & ( 
// \u0|mm_interconnect_0|led_pio_test_s1_agent|WideOr0~0_combout  & ( (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]) ) 
// ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~0_combout  & ( \u0|mm_interconnect_0|led_pio_test_s1_agent|WideOr0~0_combout  & ( 
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # ( 
// \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~0_combout  & ( !\u0|mm_interconnect_0|led_pio_test_s1_agent|WideOr0~0_combout  & ( (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & 
// (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & (!\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [0] $ 
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68])))) ) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [0]),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
        .datae(!\u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~0_combout ),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent|WideOr0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h0000044044444444;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y17_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout  = ( 
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg 
// [2]))) # (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg 
// [2])) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 .lut_mask = 64'h00FF00FFEE22EE22;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y17_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3_combout  = ( 
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg 
// [2] $ (((\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))))) # 
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) 
// ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3 .lut_mask = 64'h00FF00FFB874B874;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y17_N47
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";
// synopsys translate_on

// Location: FF_X27_Y17_N26
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y17_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout  = ( 
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( 
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (((\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg 
// [3]) # (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])))) # 
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) 
// ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( 
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg 
// [2] & !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) # 
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) 
// ) # ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datae(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 .lut_mask = 64'h0000FFFFE2222EEE;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y17_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  = ( 
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg 
// [4] & !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h00000000A000A000;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y17_N49
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y17_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout  = ( 
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( 
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) # 
// ((\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) # 
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) 
// ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( 
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  & 
// ((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) # 
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) 
// ) ) ) # ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// ((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) # (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])) # 
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ) ) ) # ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  & 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])) ) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datae(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 .lut_mask = 64'h2200DDFF7250D8FA;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y17_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout  = ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout  & ( 
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout  & 
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout  & 
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout  & 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0 .lut_mask = 64'h8000800000000000;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y19_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & ( 
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) 
// ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h0000000000F000F0;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y19_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// ((\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) # (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q 
// )))) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & 
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h00440044004C004C;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y19_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout  & ( 
// (((\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout  & !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout )) # 
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout )) # (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ) ) ) # ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout  & ( ((\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout  & 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout )) # (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .lut_mask = 64'h50FF50FF73FF73FF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y19_N2
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y17_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout  = ( 
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  $ 
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) # 
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) 
// # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] $ (((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) # 
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .lut_mask = 64'h0CF30CF32EE22EE2;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y17_N11
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";
// synopsys translate_on

// Location: FF_X27_Y17_N5
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][77] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][77]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y17_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~8 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~8_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])) # 
// (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][77]~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][77]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][77]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~8 .lut_mask = 64'h003300330C3F0C3F;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~8 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y17_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][77]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][77]~feeder_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~8_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~8_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][77]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][77]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][77]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][77]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y17_N53
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][77] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][77]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][77]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";
// synopsys translate_on

// Location: FF_X27_Y17_N23
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][75] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][75]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y17_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~6 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~6_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) # 
// (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][75]~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][75]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][75]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h003300330C3F0C3F;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y17_N41
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][75] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~6_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][75]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";
// synopsys translate_on

// Location: FF_X27_Y17_N2
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][76] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~7_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][76]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y17_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~7 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~7_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4])) # 
// (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][76]~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][76]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][76]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h003300330C3F0C3F;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y17_N23
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][76] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~7_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][76]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";
// synopsys translate_on

// Location: FF_X21_Y17_N56
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_busy (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";
// synopsys translate_on

// Location: FF_X27_Y17_N56
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][78] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~9_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][78]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y17_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~9 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~9_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( 
// (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) # 
// (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][78]~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][78]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][78]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~9 .lut_mask = 64'h003300330C3F0C3F;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~9 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y17_N2
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][78] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~9_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][78]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";
// synopsys translate_on

// Location: FF_X27_Y17_N20
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][74] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][74]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y17_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~5 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~5_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & ((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) # 
// ((\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])))) # (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & 
// (((\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][74]~q )))) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) # (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & 
// (((\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][74]~q )))) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][74]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h043704378CBF8CBF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y17_N11
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][74] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~5_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][74]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y17_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~0_combout  = ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][78]~q  & ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][74]~q  & ( 
// (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][77]~q  & (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][75]~q  & (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][76]~q  & 
// !\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_busy~q ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][77]~q ),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .datae(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][78]~q ),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h0000000080000000;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y17_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add1~0_combout  = ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][77]~q  & ( (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][75]~q  & 
// (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][76]~q  & !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][74]~q )) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][77]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add1~0 .lut_mask = 64'hA000A00000000000;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add1~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y17_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~2 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~2_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_busy~q  & ( 
// \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [2] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h000000000000FFFF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y17_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~2_combout  & ( \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout  ) ) ) # ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( !\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~2_combout  & ( 
// (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout  & !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][74]~q ) ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout ),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datae(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h0F000F0F00000000;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y17_N17
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y17_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add1~1_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][76]~q  & ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][77]~q  ) ) # ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][76]~q  & ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][77]~q  $ (((!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][75]~q  & 
// !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][74]~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][77]~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h5AAA5AAAAAAAAAAA;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add1~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y17_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout  & 
// \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout  & 
// !\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) ) ) # ( \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout  & 
// (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][75]~q  $ (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][74]~q ))) ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout  & 
// (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][75]~q  $ (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][74]~q ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout ),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datae(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h2121212133000033;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y17_N8
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y17_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~0_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [4] ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [2] $ (!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [4]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h3C3C3C3CF0F0F0F0;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y17_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][74]~q  & ( 
// \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout  & 
// !\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~0_combout ) ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][74]~q  & ( \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  
// & ( (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout  & !\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~0_combout ) ) ) ) # ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][74]~q  & ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout  & \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][76]~q 
// ) ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][74]~q  & ( !\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( 
// (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout  & (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][75]~q  $ (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][76]~q ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout ),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~0_combout ),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datae(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][74]~q ),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h2211003330303030;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y17_N38
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y17_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~2 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~2_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [5] ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [5] $ (((!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & 
// !\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [4]))) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h5AAA5AAAAAAAAAAA;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y17_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( 
// (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout  & !\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~2_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout  & 
// !\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add1~1_combout ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout ),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add1~1_combout ),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~2_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h3030303033003300;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y17_N20
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y17_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~1_combout  = ( !\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// (!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & 
// !\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [4])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~1 .lut_mask = 64'hC000C00000000000;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y17_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout  & ( 
// \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~1_combout  & ( (!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (((!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][78]~q  & 
// \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add1~0_combout )))) # (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [6])) ) ) ) # ( \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout  & ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~1_combout  & ( (!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][78]~q  & 
// \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add1~0_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][78]~q ),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add1~0_combout ),
        .datae(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout ),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h000000A0000044E4;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y17_N50
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y17_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( 
// \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_busy~q  ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( 
// (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_busy~q  & ((!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~1_combout ) # 
// (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [7]))) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h00F500F500FF00FF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y17_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( 
// \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~1_combout  & ( (!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout  & (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][78]~q  $ (!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add1~0_combout )))) ) ) ) # ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~1_combout  & ( (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout 
//  & ((!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][78]~q  $ (!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add1~0_combout )) # (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) 
// ) ) ) # ( \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( !\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~1_combout  & ( 
// (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][78]~q  $ (!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add1~0_combout )) # 
// (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~1_combout  & ( (!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout  & (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][78]~q  $ (!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add1~0_combout )))) ) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout ),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][78]~q ),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add1~0_combout ),
        .datae(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h0220133113310220;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y17_N44
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y17_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~1 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~1_combout  = ( !\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & ( 
// (!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & 
// !\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [4])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'hC000C00000000000;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y17_N44
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][66]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y17_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~3 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~3_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & ( (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used 
// [1]) # (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][66]~q ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & ( 
// (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][66]~q ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][66]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y17_N35
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~3_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][66]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y17_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg~1_combout  = (\u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~4_combout  & \u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg~0_combout )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~4_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg~1 .lut_mask = 64'h0505050505050505;
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y17_N17
dffeas \u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X27_Y17_N31
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][129] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][129]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y17_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~0_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & ( 
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][129]~q  ) ) ) # ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( 
// ((\u0|mm_interconnect_0|led_pio_test_s1_agent|WideOr0~0_combout  & \u0|mm_interconnect_0|led_pio_test_s1_agent|m0_read~0_combout )) # (\u0|mm_interconnect_0|led_pio_test_s1_agent|local_write~0_combout ) ) ) ) # ( 
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( 
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][129]~q  ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( (\u0|mm_interconnect_0|led_pio_test_s1_agent|WideOr0~0_combout  & \u0|mm_interconnect_0|led_pio_test_s1_agent|m0_read~0_combout 
// ) ) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent|WideOr0~0_combout ),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent|m0_read~0_combout ),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][129]~q ),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent|local_write~0_combout ),
        .datae(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~0 .lut_mask = 64'h11110F0F11FF0F0F;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y17_N5
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][129] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][129]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y17_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|read~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|read~0_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [0] & 
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][129]~q ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg [0]) # 
// ((\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [0] & \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][129]~q )) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [0]),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg [0]),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|read~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|read~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|read~0 .lut_mask = 64'hF0F3F0F300330033;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|read~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y17_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|read~1 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|read~1_combout  = ( \u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout  & ( (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|read~0_combout  & \u0|hps_0|fpga_interfaces|h2f_BREADY [0]) ) ) # 
// ( !\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout  & ( (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|read~0_combout  & \u0|hps_0|fpga_interfaces|h2f_RREADY [0]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|read~0_combout ),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_BREADY [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|read~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|read~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|read~1 .lut_mask = 64'h0C0C0C0C00CC00CC;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|read~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y17_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used[1]~1_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [1] & ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|read~1_combout  ) ) # ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg [0] & (\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [0] & 
// !\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|read~1_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg [0]),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [0]),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|read~1_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used[1]~1 .lut_mask = 64'h10101010F0F0F0F0;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used[1]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y17_N56
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y17_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used[0]~0_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|read~1_combout  & ( ((\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [0] & 
// \u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|read~1_combout  & ( 
// ((!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [1] & \u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [0]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [0]),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|read~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h33F333F30F3F0F3F;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y17_N44
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y17_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent|comb~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent|comb~0_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [0] ) ) # ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg [0] & ( (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [0] & ((\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][129]~q ) # 
// (\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [0]))) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [0]),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [0]),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent|comb~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|comb~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|comb~0 .lut_mask = 64'h1313131333333333;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|comb~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y17_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][66]~q  & ( \u0|mm_interconnect_0|led_pio_test_s1_agent|comb~0_combout  & ( 
// (!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~0_combout  & ((!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~1_combout ) # 
// (!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~2_combout ))) ) ) ) # ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][66]~q  & ( !\u0|mm_interconnect_0|led_pio_test_s1_agent|comb~0_combout  ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .datae(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][66]~q ),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent|comb~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h0000FFFF0000AAA0;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y17_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used[0]~1_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout  & ( (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [0]) # 
// (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|write~0_combout ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout  & ( ((\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [0] & 
// ((!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|always0~0_combout ) # (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1])))) # (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|write~0_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|write~0_combout ),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|always0~0_combout ),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h33F733F733FF33FF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y17_N47
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y17_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|always0~0_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|always0~0_combout  & ( (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [0]) # 
// (!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|always0~0_combout  & ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [0] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [0]),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|always0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hCCCCCCCCFCFCFCFC;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y24_N53
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~21_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][116]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y17_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout  = ( !\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg [0] & ( (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [0] & 
// ((!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [0]) # (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][129]~q ))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [0]),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [0]),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid .lut_mask = 64'hF0C0F0C000000000;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y23_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_001|src_payload~11 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_001|src_payload~11_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [11] & ( \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_001|src_payload~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~11 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~11 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y23_N56
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_001|src_payload~11_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";
// synopsys translate_on

// Location: FF_X15_Y23_N2
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~20_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][116]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y23_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~20 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~20_combout  = (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg 
// [116])) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][116]~q )))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][116]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~20 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~20 .lut_mask = 64'h0C3F0C3F0C3F0C3F;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~20 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y27_N32
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~20_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][116]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y27_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|waitrequest_reset_override~feeder (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|waitrequest_reset_override~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|waitrequest_reset_override~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y27_N35
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|waitrequest_reset_override (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|waitrequest_reset_override~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|waitrequest_reset_override~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|waitrequest_reset_override .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y31_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal3~1 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal3~1_combout  = ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & \u0|mm_interconnect_0|router_001|Equal3~0_combout ) ) )

        .dataa(gnd),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),
        .datac(!\u0|mm_interconnect_0|router_001|Equal3~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router_001|Equal3~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal3~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal3~1 .lut_mask = 64'h0C0C0C0C00000000;
defparam \u0|mm_interconnect_0|router_001|Equal3~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y31_N50
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|router_001|Equal3~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y31_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_002|last_cycle~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_002|last_cycle~0_combout  = ( \u0|mm_interconnect_0|router_001|Equal3~0_combout  & ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & ( (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & 
// ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [2])))) ) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [2]),
        .datae(!\u0|mm_interconnect_0|router_001|Equal3~0_combout ),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_002|last_cycle~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_002|last_cycle~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_002|last_cycle~0 .lut_mask = 64'h0000404400000000;
defparam \u0|mm_interconnect_0|cmd_mux_002|last_cycle~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y28_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y28_N11
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y28_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout  = ( \u0|mm_interconnect_0|cmd_mux_002|last_cycle~0_combout  & ( 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout  & 
// \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_002|last_cycle~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h0000000000300030;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y28_N52
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";
// synopsys translate_on

// Location: FF_X10_Y28_N44
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y27_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter~0_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~0_combout  & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|waitrequest_reset_override~q  & 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0_combout  & !\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter [0])) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|waitrequest_reset_override~q ),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0_combout ),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter~0 .lut_mask = 64'h0000000044004400;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y27_N23
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y27_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|waitrequest_reset_override~q  & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter [0] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|waitrequest_reset_override~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0 .lut_mask = 64'h0000000000FF00FF;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X10_Y28_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]) # (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0_combout  & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # 
// ((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0_combout  & !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1])) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hF4F4F4F4FCFCFCFC;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X10_Y28_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  = ( 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & 
// ((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0_combout ) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h0000000050F050F0;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y26_N32
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y26_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y26_N31
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y26_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout  = ( 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .lut_mask = 64'h33DD33DD22CC22CC;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X10_Y26_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout  = ( 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] $ 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] $ 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .lut_mask = 64'h31DF31DF20CE20CE;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y26_N35
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y26_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout  = ( 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) # 
// ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// ((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])))) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ))) ) ) ) # ( 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// (((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .lut_mask = 64'h00D5FF7F0080FF2A;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y26_N8
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y26_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  = ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg 
// [4] & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h00C000C000000000;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y26_N53
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y26_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout  = ( 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & ( 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout 
// )))) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # 
// ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )))) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & ( 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout 
// )))) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & 
// ((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .lut_mask = 64'h0C2E0C2EF3E2F3E2;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y26_N14
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y26_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout  = ( 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout 
// ) # ((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )))) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  & 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])) ) ) ) # ( 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) # 
// ((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  & 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )))) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .lut_mask = 64'h4073BFBF4040BF8C;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X10_Y26_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout  = ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout  & ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout  & 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout  & 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
        .datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .lut_mask = 64'h8800000000000000;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y28_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout  & ( 
// ((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout 
// ) ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout  & ( 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h004400440F4F0F4F;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y28_N38
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y28_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  = 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .lut_mask = 64'hAA00AA00AA00AA00;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X10_Y28_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout  = ( !\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .lut_mask = 64'hFFFFFFFF00000000;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y28_N35
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";
// synopsys translate_on

// Location: FF_X10_Y28_N14
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y28_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0_combout  & ( 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q  & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) # 
// ((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q )) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0_combout  & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q  & ( 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) # 
// ((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q  & ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0_combout ) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1])))) ) ) ) # ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0_combout  & ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q  & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q )) ) ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0_combout  & ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q  & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q  & ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0_combout ) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1])))) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0_combout ),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .lut_mask = 64'h000B0003F0FBF0F3;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y28_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout  = ( \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & ( 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] $ 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])))) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0])) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & ( 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] $ 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .lut_mask = 64'h30C030C03ACA3ACA;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y28_N38
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y28_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout  = ( 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])))) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout  & ((\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1])))) ) ) ) # 
// ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])))) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout  & ((\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1])))) ) ) ) # 
// ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # 
// ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout  & \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1])) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout  & \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1])) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
        .datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .lut_mask = 64'h0011AABBA0B10A1B;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y28_N2
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .power_up = "low";
// synopsys translate_on

// Location: FF_X13_Y28_N53
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y28_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] 
// & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3])) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] & ( 
// ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3])) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .lut_mask = 64'hF5FFF5FF0A000A00;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y28_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout  = ( 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # ((\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .lut_mask = 64'hAAAFAAAF00050005;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X10_Y28_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & ( (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & 
// !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .lut_mask = 64'hFFFFFFFFA0A0A0A0;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y28_N47
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .power_up = "low";
// synopsys translate_on

// Location: FF_X10_Y28_N32
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";
// synopsys translate_on

// Location: FF_X10_Y28_N19
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X10_Y28_N26
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y28_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~1_combout  = ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & ( 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~1 .lut_mask = 64'hC000C00000000000;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X10_Y28_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~2_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~1_combout  & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & 
// ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0_combout ))) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~1_combout  & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0_combout  & !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~2 .lut_mask = 64'h44444444CC44CC44;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X10_Y28_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  = ( 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q  & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~2_combout  & 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) 
// ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q  & ( 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~2_combout ) # 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~2_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .lut_mask = 64'h0F0A0F0A05000500;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y28_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & ( 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & (\u0|mm_interconnect_0|cmd_mux_002|last_cycle~0_combout  & \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_002|last_cycle~0_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .lut_mask = 64'h0000000000030003;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y28_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  & ( 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout 
//  & (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & 
// ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .lut_mask = 64'h0045004555555555;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y28_N41
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y28_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout  = ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q 
//  & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h3303330300000000;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y28_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  = ( \u0|mm_interconnect_0|cmd_mux_002|last_cycle~0_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  & ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) # 
// ((!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout )))) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_002|last_cycle~0_combout  & ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_002|last_cycle~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .lut_mask = 64'hAAAAAAAAAA8AAA8A;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y28_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  = ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg 
// [2] & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] & 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .lut_mask = 64'h3000300000000000;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y28_N49
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y28_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout  = ( \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & ( 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  $ 
// (((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))))) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout )))) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] 
// & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  $ 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .lut_mask = 64'h22882288278D278D;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y28_N26
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y28_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout  = ( 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & ( 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout )) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & ( 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  & 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout )) ) ) ) # ( 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( !\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & ( 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( !\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & ( 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  & (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])) ) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .lut_mask = 64'h3000C0F03505C5F5;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y28_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout  = ( 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout  & ( 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout  & ( 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout  & ( 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout  & ( 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  ) ) ) # ( 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout  & ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout  & ( 
// ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout  & 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout  & 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ))) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout  & ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout  & ( 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),
        .datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .lut_mask = 64'h3333B33333333333;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y28_N20
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y28_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0_combout  & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0_combout  & (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'h040404040C0C0C0C;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X10_Y28_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout  = ( 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) 
// ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .lut_mask = 64'hF0F0F0F0F000F000;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y28_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout  & ( 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h0000000005000500;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y28_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout  & ( 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout  & ( 
// ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h555D555D000C000C;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y28_N29
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y28_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & 
// ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  $ 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & ( 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .lut_mask = 64'hA000A0005AA05AA0;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y28_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  & ( 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  & ( 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// ((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .lut_mask = 64'h1155115500440044;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y28_N44
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y28_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_002|last_cycle~0_combout  & ( 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & ( ((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout )) # (\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_002|last_cycle~0_combout  & ( 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_002|last_cycle~0_combout  & ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_002|last_cycle~0_combout  & ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ) ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
        .datae(!\u0|mm_interconnect_0|cmd_mux_002|last_cycle~0_combout ),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .lut_mask = 64'h03030303030303FF;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y28_N53
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y28_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~0_combout  = ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & ( 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & ((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~0 .lut_mask = 64'h0707070700000000;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y27_N32
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][129] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][129]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y27_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~1_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & ( ((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~0_combout  & 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0_combout )) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][129]~q ) ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & ( 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~0_combout  & \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][129]~q ),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h0505050537373737;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y26_N41
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][78] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][78]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y26_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~3_combout  = (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]))) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & 
// (((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][78]~q ))))

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][78]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h0257025702570257;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y26_N47
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][78] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~3_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][78]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";
// synopsys translate_on

// Location: FF_X10_Y26_N56
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][75] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][75]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y26_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~6 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~6_combout  = (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & 
// (((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][75]~q ))))

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][75]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h0257025702570257;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y26_N5
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][75] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~6_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][75]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";
// synopsys translate_on

// Location: FF_X10_Y26_N38
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][77] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][77]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y26_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~4 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~4_combout  = (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & 
// (((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][77]~q ))))

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][77]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~4 .lut_mask = 64'h0257025702570257;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y26_N44
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][77] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~4_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][77]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";
// synopsys translate_on

// Location: FF_X10_Y26_N23
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][74] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~7_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][74]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y26_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~7 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~7_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & (((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & 
// (((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][74]~q )))) ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & 
// (((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][74]~q )))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][74]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h02570257A2F7A2F7;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y26_N29
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~7_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";
// synopsys translate_on

// Location: FF_X10_Y26_N59
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][76] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][76]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y26_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~5 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~5_combout  = (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]))) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & 
// (((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][76]~q ))))

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][76]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h0257025702570257;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y26_N26
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][76] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~5_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][76]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y26_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~0_combout  = (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][75]~q  & (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][77]~q  & 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74]~q  & !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][76]~q )))

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][77]~q ),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~0 .lut_mask = 64'h8000800080008000;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X10_Y26_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~1_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][76]~q  & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][77]~q  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][76]~q  & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][77]~q  $ (((!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][75]~q  & 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74]~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][77]~q ),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h5AF05AF0F0F0F0F0;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y26_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~1_combout  & ( 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout  & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~0_combout  & (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][78]~q ))) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (((!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6])))) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~1_combout  & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout  & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~0_combout  & 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][78]~q )) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][78]~q ),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~1_combout ),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h0000000040407340;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y26_N49
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";
// synopsys translate_on

// Location: FF_X11_Y26_N20
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_busy (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y26_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_busy~q  & ( 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~1_combout ) # ((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [7])) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h00000000AFFFAFFF;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y26_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~2_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_busy~q  & ( 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y26_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout  = ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~2_combout  & ( 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74]~q ) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h00AF00AF00000000;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y26_N5
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y26_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout  & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74]~q  $ ((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][75]~q )))) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout  & ( 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74]~q  $ ((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][75]~q 
// )))) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (((!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h0000000099F0990F;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y26_N32
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y26_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~0_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h0FFF0FFFF000F000;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y26_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout  & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~0_combout  ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout  & ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][76]~q  $ (((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][75]~q ) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74]~q ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~0_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h00000000A50FCCCC;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y26_N44
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y26_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~2_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5] ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5] $ (((!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h78787878F0F0F0F0;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y26_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout  & ( 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~1_combout )) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~2_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~1_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~2_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h00000000AAF0AAF0;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y26_N8
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y26_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~1_combout  = ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~1 .lut_mask = 64'hC000C00000000000;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y26_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout  & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][78]~q  $ ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~0_combout )))) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (((!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~1_combout )))) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout  & ( 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][78]~q  $ 
// ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~0_combout )))) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~1_combout )))) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][78]~q ),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~0_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~1_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h00000000660F66F0;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y26_N14
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y26_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~1_combout  = ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & ( 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'hC000C00000000000;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X10_Y26_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~0_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74]~q  & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][77]~q  & ( 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][76]~q  & (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_busy~q  & (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][78]~q  & 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][75]~q ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][78]~q ),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74]~q ),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][77]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h0000800000000000;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y28_N20
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][66]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y28_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~2_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & ( 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][66]~q ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][66]~q ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][66]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~2 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y26_N38
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~2_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][66]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y26_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][66]~q  & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|comb~0_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~0_combout  & ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~1_combout ) # 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~2_combout ))) ) ) ) # ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][66]~q  & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|comb~0_combout  ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][66]~q ),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|comb~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h0000FFFF0000FA00;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y27_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout  & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0] ) ) # ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout  & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0]) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hAFAFAFAFAAAAAAAA;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y27_N38
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y27_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|comb~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|comb~0_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0] ) ) # ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0] & ((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q ) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|comb~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|comb~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|comb~0 .lut_mask = 64'h0555055555555555;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|comb~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y27_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0_combout  = (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|comb~0_combout  & \u0|hps_0|fpga_interfaces|h2f_RREADY [0])

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|comb~0_combout ),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0 .lut_mask = 64'h000F000F000F000F;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y27_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|write~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|write~0_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~0_combout  & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0_combout ) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0_combout ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|write~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|write~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h000000000FFF0FFF;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|write~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y27_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[0]~1_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0] & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|write~0_combout  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0] & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|write~0_combout  ) ) # ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0] & ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|write~0_combout  & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0_combout ) # ((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout 
// ) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1])) ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout ),
        .datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0]),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|write~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h0000CFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y27_N29
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y27_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[1]~0_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout  & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|write~0_combout  & 
// ((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]))) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|write~0_combout  & (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0])) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout  & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|write~0_combout  & (((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0_combout )))) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|write~0_combout  & ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0_combout  & 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0])) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0_combout  & ((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]))))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0]),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|write~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[1]~0 .lut_mask = 64'h3503350335353535;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[1]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y27_N11
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y28_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  = ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & 
// ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// ((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0_combout ) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0_combout )))) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  
// & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .lut_mask = 64'hFF0000004C000000;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y28_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout  = ( 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  ) 
// ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  ) 
// ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3 .lut_mask = 64'h22220000F0F0F0F0;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X10_Y28_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout  = ( 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  & 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout )) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  & 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout  & 
// ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) # (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q 
// )))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4 .lut_mask = 64'hA080A08080808080;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y28_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_002|packet_in_progress~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_002|packet_in_progress~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_002|last_cycle~0_combout  & ( (!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & ((\u0|mm_interconnect_0|cmd_mux_002|packet_in_progress~q ))) # 
// (\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_002|last_cycle~0_combout  & ( 
// \u0|mm_interconnect_0|cmd_mux_002|packet_in_progress~q  ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_002|packet_in_progress~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_002|last_cycle~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_002|packet_in_progress~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_002|packet_in_progress~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_002|packet_in_progress~0 .lut_mask = 64'h00FF00FF05F505F5;
defparam \u0|mm_interconnect_0|cmd_mux_002|packet_in_progress~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y28_N8
dffeas \u0|mm_interconnect_0|cmd_mux_002|packet_in_progress (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_002|packet_in_progress~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_002|packet_in_progress~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_002|packet_in_progress .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_002|packet_in_progress .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y28_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_002|update_grant~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_002|update_grant~0_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout  & ( (!\u0|mm_interconnect_0|cmd_mux_002|packet_in_progress~q  & 
// ((!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]) # (!\u0|mm_interconnect_0|cmd_mux_002|last_cycle~0_combout ))) ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout  & 
// ( (!\u0|mm_interconnect_0|cmd_mux_002|packet_in_progress~q ) # ((\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & \u0|mm_interconnect_0|cmd_mux_002|last_cycle~0_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_002|packet_in_progress~q ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_002|last_cycle~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_002|update_grant~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_002|update_grant~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_002|update_grant~0 .lut_mask = 64'hF0F5F0F5F0A0F0A0;
defparam \u0|mm_interconnect_0|cmd_mux_002|update_grant~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y28_N5
dffeas \u0|mm_interconnect_0|cmd_mux_002|saved_grant[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_002|last_cycle~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|cmd_mux_002|update_grant~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_002|saved_grant[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_002|saved_grant[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X10_Y28_N2
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y28_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0_combout  = ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q 
// ) # (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q )))) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0 .lut_mask = 64'hA800000000000000;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y27_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg~0_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~0_combout  & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|waitrequest_reset_override~q  & 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0_combout  & \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter [0])) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|waitrequest_reset_override~q ),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg~0 .lut_mask = 64'h0000000004040404;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y27_N20
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y27_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|read~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|read~0_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q  & ((\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0])))) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ((\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]))) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|read~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|read~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|read~0 .lut_mask = 64'h1155115510501050;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|read~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y27_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[1]~1_combout  = ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|read~0_combout  & ( ((\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0] & 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [1]) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|read~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[1]~1 .lut_mask = 64'h05FF05FF00000000;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[1]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y27_N47
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y27_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[0]~0_combout  = (!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0] & ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|read~0_combout  & 
// ((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]))) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|read~0_combout  & (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [1])))) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0] & ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [1] $ (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|read~0_combout )) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0])))

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|read~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h43F743F743F743F7;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y27_N44
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y27_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_002|src_payload~11 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_002|src_payload~11_combout  = (\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [11])

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_002|src_payload~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~11 .lut_mask = 64'h000F000F000F000F;
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~11 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y27_N29
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_002|src_payload~11_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";
// synopsys translate_on

// Location: FF_X13_Y27_N56
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~20_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][116]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y27_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~20 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~20_combout  = (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116])) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & 
// ((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][116]~q )))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][116]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~20 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~20 .lut_mask = 64'h0C3F0C3F0C3F0C3F;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~20 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y27_N7
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~20_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][116]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y27_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~56 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~56_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][116]~q  & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q  & ( 
// ((\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0])) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]) ) ) ) # ( 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][116]~q  & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q  & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0]),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][116]~q ),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~56_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~56 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~56 .lut_mask = 64'h00005F5F00007F7F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~56 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y27_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~203 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~203_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][116]~q  & ( !\u0|mm_interconnect_0|rsp_mux_001|src_payload~56_combout  & ( 
// (\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout  & ((!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][116]~q ) # ((\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ) # 
// (\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout )))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][116]~q  & ( !\u0|mm_interconnect_0|rsp_mux_001|src_payload~56_combout  & ( 
// (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][116]~q ) # ((\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ) # (\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][116]~q ),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ),
        .datad(!\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ),
        .datae(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][116]~q ),
        .dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~56_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~203_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~203 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~203 .lut_mask = 64'hCFFF455500000000;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~203 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y31_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][129]~q  & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0] & 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0])) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][129]~q  & ( 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0] & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0]) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0]),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid .lut_mask = 64'hA0A0A0A0A000A000;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y34_N32
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][129] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][129]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";
// synopsys translate_on

// Location: FF_X22_Y31_N59
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|router_001|Equal5~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y31_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_003|last_cycle~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_003|last_cycle~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [3] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q  & ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR 
// [17] & (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & \u0|mm_interconnect_0|router_001|Equal1~4_combout ))) ) ) ) # ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [3] & ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q  & ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & 
// \u0|mm_interconnect_0|router_001|Equal1~4_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [3] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q  & ( 
// (\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & \u0|mm_interconnect_0|router_001|Equal1~4_combout ))) ) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),
        .datad(!\u0|mm_interconnect_0|router_001|Equal1~4_combout ),
        .datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [3]),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_003|last_cycle~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_003|last_cycle~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_003|last_cycle~0 .lut_mask = 64'h0010001000000010;
defparam \u0|mm_interconnect_0|cmd_mux_003|last_cycle~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y34_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_translator|waitrequest_reset_override~feeder (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_translator|waitrequest_reset_override~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_translator|waitrequest_reset_override~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y34_N44
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_translator|waitrequest_reset_override (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_translator|waitrequest_reset_override~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_translator|waitrequest_reset_override~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|waitrequest_reset_override .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y34_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter~0_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_translator|waitrequest_reset_override~q  & ( (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~0_combout  & 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_agent|WideOr0~0_combout  & !\u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter [0])) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|WideOr0~0_combout ),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|waitrequest_reset_override~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter~0 .lut_mask = 64'h0000000050005000;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y34_N17
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y34_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~0_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_translator|waitrequest_reset_override~q  & ( \u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter [0] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|waitrequest_reset_override~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~0 .lut_mask = 64'h0000000000FF00FF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y34_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y34_N35
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y34_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout  = ( !\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .lut_mask = 64'hFFFFFFFF00000000;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y34_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout  = ( \u0|mm_interconnect_0|cmd_mux_003|last_cycle~0_combout  & ( 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout  & (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & 
// \u0|mm_interconnect_0|cmd_mux_003|saved_grant [1])) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_003|last_cycle~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h00000000000A000A;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y34_N47
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y36_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y36_N28
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y36_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout  = ( \u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] & ( 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] $ 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])))) # (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0])) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] $ (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) 
// ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .lut_mask = 64'h30C030C03ACA3ACA;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y36_N53
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y36_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout  = ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( \u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] & ( 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # 
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])))) # (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout )) ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( \u0|mm_interconnect_0|cmd_mux_003|saved_grant 
// [1] & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])))) # (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout )) ) ) ) # ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( !\u0|mm_interconnect_0|cmd_mux_003|saved_grant 
// [1] & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # 
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) ) ) # ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( !\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] & ( 
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .lut_mask = 64'h3000CF003055CF55;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y36_N56
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y36_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] & ( 
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3])) ) ) # ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) 
// # ((\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]) # 
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .lut_mask = 64'hCFFFCFFF30003000;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y36_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  
// & ( (\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] & (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) ) ) # ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # 
// ((\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .lut_mask = 64'hCDCDCDCD01010101;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y36_N11
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y36_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  = ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & ( 
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] & 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .lut_mask = 64'h3000300000000000;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y36_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  
// & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg 
// [5])))) # (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ))) ) ) 
// # ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) # (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .lut_mask = 64'h01CD01CDCD01CD01;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y36_N7
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .power_up = "low";
// synopsys translate_on

// Location: FF_X14_Y36_N38
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y36_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout  = ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( \u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] & ( 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout )) # 
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) # (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( 
// \u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & ((\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout )))) # 
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout )))) ) ) ) # ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( !\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] & ( 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ) # 
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) ) ) ) # ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( !\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] & ( 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .datae(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .lut_mask = 64'h0088CC44038BCF47;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y36_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout  = ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout  & ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout  & ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  ) ) ) # ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout  & ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout  & ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  ) ) ) # ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout  & ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout  & ( 
// ((!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout  & 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout  & 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ))) # 
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) ) # ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout  & ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout  & ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  ) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),
        .datae(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .lut_mask = 64'h0F0F8F0F0F0F0F0F;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y36_N44
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y34_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & ( !\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & ( (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]) # (!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .lut_mask = 64'hFFF0FFF0FF00FF00;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y34_N53
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .power_up = "low";
// synopsys translate_on

// Location: FF_X19_Y34_N29
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X19_Y34_N43
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X19_Y34_N11
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y34_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~1_combout  = ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & ( 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1])) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~1 .lut_mask = 64'hA000A00000000000;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y34_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~2_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~1_combout  & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & 
// ((!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~0_combout ))) ) ) # ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~1_combout  & ( (\u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~0_combout  & !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~2 .lut_mask = 64'h55005500F500F500;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~2 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y34_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~2_combout  & ( 
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) # ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~2_combout  & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q  & 
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .lut_mask = 64'h0C0C0C0C0F000F00;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y34_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout  = ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & ( 
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h0011001100000000;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y34_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|WideOr0~0_combout  & ( 
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]) ) ) # ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent|WideOr0~0_combout  & ( (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] 
// & \u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~0_combout )) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|WideOr0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h0030003030303030;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y34_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout  = ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) # 
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q 
//  & ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  $ 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .lut_mask = 64'h55AA55AA50FA50FA;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y34_N41
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y34_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout  = ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) # 
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q 
//  & ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] $ 
// (((!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) # 
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .lut_mask = 64'h50AF50AF44EE44EE;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y34_N32
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y34_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout  = ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  
// & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) ) ) ) # ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  
// & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & 
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) ) ) ) # ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  
// & ( ((!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) # 
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) # (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg 
// [2]) ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg 
// [2] & (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) ) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datae(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .lut_mask = 64'h0A00F5FF0C0CFCFC;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y34_N44
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y34_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  = ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( 
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg 
// [2])) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h4040404000000000;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y34_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout  = ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) # 
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q 
//  & ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  $ (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) ) 
// )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .lut_mask = 64'h0FF00FF044EE44EE;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y34_N35
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";
// synopsys translate_on

// Location: FF_X15_Y34_N26
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y34_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout  = ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  
// & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) # 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) ) ) ) # ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  
// & ( (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) ) ) ) # ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg 
// [6] & ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) 
// # (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) ) ) ) # ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q 
//  & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) ) ) 
// )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .datae(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .lut_mask = 64'h00F0FF0F4444EEEE;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y34_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout  = ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout  & ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout  & ( 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout  & 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout  & 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout )) ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
        .datae(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .lut_mask = 64'hC000000000000000;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y34_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout  & ( 
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  
// & \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) ) ) # ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout  & ( ((\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))) # (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ) ) 
// )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h0F4F0F4F00440044;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y34_N23
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y34_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  = ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .lut_mask = 64'hAAAA0000AAAA0000;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y34_N35
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y34_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ) # 
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ) ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h0000F3F300000000;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y34_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  = ( \u0|mm_interconnect_0|cmd_mux_003|last_cycle~0_combout  & ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout  & ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  ) ) ) # ( 
// !\u0|mm_interconnect_0|cmd_mux_003|last_cycle~0_combout  & ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout  & ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_003|last_cycle~0_combout  & ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout  & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  & 
// ((!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]) # (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ))) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_003|last_cycle~0_combout  & ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout  & ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datae(!\u0|mm_interconnect_0|cmd_mux_003|last_cycle~0_combout ),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .lut_mask = 64'hF0F0F0A0F0F0F0F0;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y34_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ) ) ) ) # ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q 
//  & ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  & ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  ) 
// ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  
// & ( (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout 
// ) ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .lut_mask = 64'h03030F0F00000C0C;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y34_N50
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y34_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|WideOr0~0_combout  & ( 
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]) ) ) # ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent|WideOr0~0_combout  & ( (\u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~0_combout  & 
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1])) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|WideOr0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'h050005000F000F00;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y34_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q  & ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q  & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) # 
// (((!\u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~0_combout  & !\u0|mm_interconnect_0|data_flag_rx_s1_agent|WideOr0~0_combout )) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1])) ) ) ) # ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q  & ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q  & ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  ) ) ) # ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q 
//  & ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q  & ( (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// (((!\u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~0_combout  & !\u0|mm_interconnect_0|data_flag_rx_s1_agent|WideOr0~0_combout )) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]))) ) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~0_combout ),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|WideOr0~0_combout ),
        .datae(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .lut_mask = 64'h00002303CCCCEFCF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y34_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout  = ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) # (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .lut_mask = 64'hFFF0FFF000000000;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y34_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_003|last_cycle~0_combout  & ( 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout  & 
// ((\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )))) # (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & 
// (((\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout  & \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) # 
// (\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]))) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_003|last_cycle~0_combout  & ( (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout  & 
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_003|last_cycle~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .lut_mask = 64'h0033003305370537;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y34_N41
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y34_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|WideOr0~0_combout  & ( 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]) # (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ) ) # ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent|WideOr0~0_combout  & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # ((!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used 
// [1] & \u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~0_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~0_combout ),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|WideOr0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hFF0AFF0AFFAAFFAA;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y34_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & ( 
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & (\u0|mm_interconnect_0|cmd_mux_003|last_cycle~0_combout  & \u0|mm_interconnect_0|cmd_mux_003|saved_grant [1])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_003|last_cycle~0_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .lut_mask = 64'h0000000000030003;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y34_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  & ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  & ( 
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & 
// ((!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) # (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout 
// )))) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .lut_mask = 64'h0045004555555555;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y34_N47
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y34_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) ) ) # ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  $ (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))) # 
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .lut_mask = 64'hA50AA50A0A000A00;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y34_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout  & ( ((\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout )) # (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ) ) ) ) 
// # ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout  & ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout  ) ) ) # ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout  & ( (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
        .datae(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h0000505000FF50FF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y34_N29
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y34_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & ( 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ))) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & ( 
// ((!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ))) # 
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3 .lut_mask = 64'h08FF08FF08000800;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y34_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  = ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ((\u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~0_combout ) # 
// (\u0|mm_interconnect_0|data_flag_rx_s1_agent|WideOr0~0_combout )))) ) ) ) # ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|WideOr0~0_combout ),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~0_combout ),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datae(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .lut_mask = 64'hAA00AA002A000000;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y34_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout  & 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout )) ) 
// ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout  & (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout )) ) ) ) # ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout  & 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout )) ) 
// ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout  & !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ) ) ) 
// )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
        .datae(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4 .lut_mask = 64'hAA00A000A000A000;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y34_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_003|packet_in_progress~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_003|packet_in_progress~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_003|packet_in_progress~q  & ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout  ) ) 
// # ( !\u0|mm_interconnect_0|cmd_mux_003|packet_in_progress~q  & ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout  & ( (\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] & 
// \u0|mm_interconnect_0|cmd_mux_003|last_cycle~0_combout ) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_003|packet_in_progress~q  & ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout  & ( 
// (!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]) # (!\u0|mm_interconnect_0|cmd_mux_003|last_cycle~0_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|cmd_mux_003|last_cycle~0_combout ),
        .datae(!\u0|mm_interconnect_0|cmd_mux_003|packet_in_progress~q ),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_003|packet_in_progress~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_003|packet_in_progress~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_003|packet_in_progress~0 .lut_mask = 64'h0000FFAA0055FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_003|packet_in_progress~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y34_N17
dffeas \u0|mm_interconnect_0|cmd_mux_003|packet_in_progress (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_003|packet_in_progress~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_003|packet_in_progress~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_003|packet_in_progress .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_003|packet_in_progress .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y34_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_003|update_grant~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_003|update_grant~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_003|packet_in_progress~q  & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout  & 
// (\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] & \u0|mm_interconnect_0|cmd_mux_003|last_cycle~0_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_003|packet_in_progress~q  & ( 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ) # ((!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]) # (!\u0|mm_interconnect_0|cmd_mux_003|last_cycle~0_combout )) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_003|last_cycle~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_003|packet_in_progress~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_003|update_grant~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_003|update_grant~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_003|update_grant~0 .lut_mask = 64'hFFFCFFFC000C000C;
defparam \u0|mm_interconnect_0|cmd_mux_003|update_grant~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y34_N2
dffeas \u0|mm_interconnect_0|cmd_mux_003|saved_grant[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_003|last_cycle~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|cmd_mux_003|update_grant~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_003|saved_grant[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_003|saved_grant[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X19_Y34_N5
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y34_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent|WideOr0~0_combout  = ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q  & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]))) ) ) ) # ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q  & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]))) ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q  & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]))) ) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .datae(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent|WideOr0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|WideOr0~0 .lut_mask = 64'h8000800080000000;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|WideOr0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y34_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~1_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|WideOr0~0_combout  & ( ((\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][129]~q )) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~0_combout ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent|WideOr0~0_combout  & ( 
// (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][129]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][129]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|WideOr0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y34_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|write~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|write~0_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|WideOr0~0_combout  & ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~0_combout  ) ) # ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent|WideOr0~0_combout  & ( (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~0_combout  & \u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~0_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~0_combout ),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|WideOr0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|write~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|write~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h0055005555555555;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|write~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y34_N47
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][66]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";
// synopsys translate_on

// Location: FF_X19_Y34_N14
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y34_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~2_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used 
// [1]) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][66]~q ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & ( 
// (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][66]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][66]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~2 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y34_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][66]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][66]~feeder_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~2_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][66]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][66]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][66]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][66]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y34_N38
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][66]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][66]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";
// synopsys translate_on

// Location: FF_X15_Y34_N53
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][77] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][77]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y34_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~4 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~4_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][77]~q  & ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][77]~q  & ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) ) ) ) # ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][77]~q  & ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] ) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datae(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][77]~q ),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~4 .lut_mask = 64'h0000555500AA55FF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y34_N44
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][77] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~4_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][77]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";
// synopsys translate_on

// Location: FF_X15_Y34_N56
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][78] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][78]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y34_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~3 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~3_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][78]~q  & ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][78]~q  & ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]) ) ) ) # ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][78]~q  & ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] ) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][78]~q ),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h000055550A0A5F5F;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y34_N11
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][78] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~3_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][78]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";
// synopsys translate_on

// Location: FF_X17_Y34_N29
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_busy (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";
// synopsys translate_on

// Location: FF_X15_Y34_N17
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][75] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][75]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y34_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~6 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~6_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][75]~q  & ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][75]~q  & ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]) ) ) ) # ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][75]~q  & ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] ) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][75]~q ),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h000055550A0A5F5F;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y34_N47
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][75] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~6_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][75]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";
// synopsys translate_on

// Location: FF_X15_Y34_N8
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][74] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~7_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][74]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y34_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~7 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~7_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][74]~q  & ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & ( 
// ((\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) # (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg 
// [2])) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][74]~q  & ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & 
// ((\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) # (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg 
// [2]))) ) ) ) # ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][74]~q  & ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & ( 
// ((\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q 
// )) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][74]~q  & ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & 
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) 
// ) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][74]~q ),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h202075752A2A7F7F;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y34_N23
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][74] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~7_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][74]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";
// synopsys translate_on

// Location: FF_X15_Y34_N2
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][76] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][76]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y34_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~5 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~5_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][76]~q  & ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][76]~q  & ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]) ) ) ) # ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][76]~q  & ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] ) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .datae(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][76]~q ),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h0000555500AA55FF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y34_N20
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][76] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~5_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][76]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y34_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~0_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][74]~q  & ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][76]~q  & ( 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][77]~q  & (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][78]~q  & (!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_busy~q  & 
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][75]~q ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][77]~q ),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][78]~q ),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datae(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][74]~q ),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h0000800000000000;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y34_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add1~0_combout  = (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][77]~q  & (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][75]~q  & 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][74]~q  & !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][76]~q )))

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][77]~q ),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add1~0 .lut_mask = 64'h8000800080008000;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add1~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y34_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~2_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_busy~q  & ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h000000000000FFFF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y34_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~2_combout  & \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout ) ) ) # ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~2_combout  & 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][74]~q  & \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout )) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h00A000A000AA00AA;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y34_N50
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y34_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~0_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & !\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]) ) ) # ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( (\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]) # 
// (\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h33FF33FFCC00CC00;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y34_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout  & ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~0_combout  & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][76]~q  $ 
// (((\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][74]~q ) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][75]~q ))))) ) ) ) # ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout  & ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~0_combout  & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][76]~q  $ (((\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][74]~q ) # 
// (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][75]~q )))) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datae(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout ),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h000095FF00009500;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y34_N14
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y34_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~2_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5] ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5] $ (((!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & 
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h3CCC3CCCCCCCCCCC;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~2 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y34_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add1~1_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][76]~q  & ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][77]~q  ) ) # ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][76]~q  & ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][77]~q  $ (((!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][75]~q  & 
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][74]~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][77]~q ),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h66AA66AAAAAAAAAA;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add1~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y34_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add1~1_combout  & ( 
// (\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout  & (\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~2_combout )) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add1~1_combout  & ( (\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout  & 
// ((!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ) # (!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~2_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~2_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add1~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h5550555005000500;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y34_N59
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y34_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~1_combout  = ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & 
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5])) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~1 .lut_mask = 64'h8800880000000000;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y34_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~1_combout  & ( (\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout  & 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add1~0_combout  $ (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][78]~q )))) ) ) 
// ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~1_combout  & ( 
// (\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add1~0_combout  $ (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][78]~q )) # 
// (\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~1_combout  & ( (\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add1~0_combout  $ 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][78]~q )) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~1_combout  & ( 
// (\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout  & (!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add1~0_combout  $ (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][78]~q )))) ) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add1~0_combout ),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][78]~q ),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout ),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datae(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h0600060F060F0600;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y34_N2
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y34_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add1~0_combout  & ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~1_combout  & ( 
// (\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// ((!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][78]~q ))) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6])))) ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add1~0_combout  & ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~1_combout  & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout  
// & \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout )) ) ) ) # ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add1~0_combout  & ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~1_combout  & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][78]~q  & (\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout  & 
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][78]~q ),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout ),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datae(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add1~0_combout ),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h00000C00000A0C0A;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y34_N31
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y34_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_busy~q  & ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] ) ) # ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_busy~q  & ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~1_combout ) # 
// (\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [7]) ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h0000CFCF0000FFFF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y34_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( (\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][75]~q  $ 
// (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][74]~q )) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( 
// (\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout  & (!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][75]~q 
//  $ (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][74]~q )))) ) ) ) # ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( (\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout  & 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][75]~q  $ (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][74]~q )))) ) ) ) # ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( 
// (\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][75]~q  $ (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][74]~q )) # 
// (\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout ),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datae(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h4155410041004155;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y34_N38
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y34_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~1_combout  = (!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & 
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5])))

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'h8000800080008000;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y34_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~2_combout  & ( (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][66]~q  & 
// ((!\u0|mm_interconnect_0|data_flag_rx_s1_agent|comb~0_combout ) # ((!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~0_combout  & !\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~1_combout )))) ) ) # ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~2_combout  & ( (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][66]~q  & ((!\u0|mm_interconnect_0|data_flag_rx_s1_agent|comb~0_combout ) # 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~0_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][66]~q ),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|comb~0_combout ),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h5454545454445444;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y34_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used[0]~1_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout  & ( (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [0]) # 
// (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|write~0_combout ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout  & ( ((\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [0] & 
// ((!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|always0~0_combout ) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1])))) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|write~0_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|write~0_combout ),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|always0~0_combout ),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h33F733F733FF33FF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y34_N59
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y34_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|always0~0_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout  & ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [0] ) ) # ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout  & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [0]) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|always0~0_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|always0~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [0]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hF5F5F0F0F5F5F0F0;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y34_N53
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][129] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][129]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y34_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|read~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|read~0_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg [0] & ( (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & 
// ((!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][129]~q ) # (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [0]))) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg [0] & ( 
// (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [0] & (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ((!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][129]~q ) # (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used 
// [0])))) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [0]),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|read~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|read~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|read~0 .lut_mask = 64'h050405040F0C0F0C;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|read~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y34_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used[1]~1_combout  = ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|read~0_combout  & ( ((\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [0] & 
// \u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1]) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [0]),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg [0]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|read~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used[1]~1 .lut_mask = 64'h11FF11FF00000000;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used[1]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y34_N53
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y34_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used[0]~0_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|read~0_combout  & ( ((\u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg [0] & 
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|read~0_combout  & ( 
// ((\u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1])) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [0]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg [0]),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|read~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h30FF30FF0F3F0F3F;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y34_N50
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y34_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent|comb~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent|comb~0_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [0] ) ) # ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg [0] & ( (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [0] & ((\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [0]) # 
// (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][129]~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [0]),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [0]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg [0]),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent|comb~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|comb~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|comb~0 .lut_mask = 64'h07070F0F07070F0F;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|comb~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y34_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|always0~0_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|comb~0_combout  & ( \u0|hps_0|fpga_interfaces|h2f_RREADY [0] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|comb~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|always0~0 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y34_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used[1]~0_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|write~0_combout  & ( 
// ((\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|always0~0_combout  & !\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout )) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [0]) ) ) ) # ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|write~0_combout  & ( (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [0] & 
// ((!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|always0~0_combout ) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout ))) ) ) ) # ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|write~0_combout  & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|always0~0_combout ) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|always0~0_combout ),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [0]),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|write~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used[1]~0 .lut_mask = 64'h0000AFAF23237373;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used[1]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y34_N26
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X11_Y34_N53
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y34_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~0_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] ) ) ) # ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & ( 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]) ) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~0 .lut_mask = 64'h000000000A0AAAAA;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y34_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg~0_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_translator|waitrequest_reset_override~q  & ( (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~0_combout  & 
// (\u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter [0] & !\u0|mm_interconnect_0|data_flag_rx_s1_agent|WideOr0~0_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~0_combout ),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter [0]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|WideOr0~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|waitrequest_reset_override~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg~0 .lut_mask = 64'h0000000011001100;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y34_N8
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y34_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout  = ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg [0] & 
// ((!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][129]~q ) # (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [0]))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg [0]),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid .lut_mask = 64'hCCC0CCC000000000;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y33_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_003|src_payload~11 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_003|src_payload~11_combout  = (\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [11])

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_003|src_payload~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~11 .lut_mask = 64'h0303030303030303;
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~11 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y33_N8
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_003|src_payload~11_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";
// synopsys translate_on

// Location: FF_X17_Y33_N53
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~20_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][116]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y33_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~20 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~20_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][116]~q  ) ) # ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][116]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~20 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~20 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~20 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y30_N5
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~20_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][116]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y35_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|waitrequest_reset_override~feeder (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|waitrequest_reset_override~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|waitrequest_reset_override~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y35_N17
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|waitrequest_reset_override (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|waitrequest_reset_override~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|waitrequest_reset_override~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|waitrequest_reset_override .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y31_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal11~0 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal11~0_combout  = (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & \u0|mm_interconnect_0|router_001|Equal3~0_combout ))

        .dataa(gnd),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),
        .datad(!\u0|mm_interconnect_0|router_001|Equal3~0_combout ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router_001|Equal11~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal11~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal11~0 .lut_mask = 64'h000C000C000C000C;
defparam \u0|mm_interconnect_0|router_001|Equal11~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y31_N53
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|router_001|Equal11~0_combout ),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y31_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_006|last_cycle~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout  = ( \u0|mm_interconnect_0|router_001|Equal3~0_combout  & ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & ( (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & 
// ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [6])))) ) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [6]),
        .datae(!\u0|mm_interconnect_0|router_001|Equal3~0_combout ),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_006|last_cycle~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_006|last_cycle~0 .lut_mask = 64'h0000000000002030;
defparam \u0|mm_interconnect_0|cmd_mux_006|last_cycle~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y35_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y35_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout  = !\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .lut_mask = 64'hF0F0F0F0F0F0F0F0;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y35_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y35_N53
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y35_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout  = ( \u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & ( 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout  & \u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h0000000000500050;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y35_N50
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y35_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0_combout  = (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter [0] & \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|waitrequest_reset_override~q )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter [0]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|waitrequest_reset_override~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0 .lut_mask = 64'h0055005500550055;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y35_N56
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";
// synopsys translate_on

// Location: FF_X14_Y35_N41
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X14_Y35_N16
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X14_Y35_N8
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y35_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~1_combout  = ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & ( 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] 
// & !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1])) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~1 .lut_mask = 64'hA000A00000000000;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y35_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~2_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~1_combout  & ( (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & 
// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0_combout ))) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~1_combout  & ( (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0_combout ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~2 .lut_mask = 64'h00CC00CCC0CCC0CC;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y35_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  = ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~2_combout  & 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q  & ( 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~2_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~2_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .lut_mask = 64'h00FA00FA000A000A;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y35_N20
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y35_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  = ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .lut_mask = 64'hFF00FF0000000000;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y35_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & 
// ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & (\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & \u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout )) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .lut_mask = 64'h0000000000030003;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y35_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  & 
// ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  & ( 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & 
// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .lut_mask = 64'h0045004555555555;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y35_N32
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y35_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  
// & ( (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h00000000C0CCC0CC;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y35_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  = ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout  & ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  & 
// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) # ((!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]) # (!\u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .lut_mask = 64'hF0E0F0E0F0F0F0F0;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y35_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  
// & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  & ( 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .lut_mask = 64'h0555055500500050;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y35_N47
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y35_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0_combout  & ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q  & ( (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q 
// ) # ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q  & \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1])) ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0_combout  & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) # 
// ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q  & ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0_combout ) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1])))) ) ) ) # ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0_combout  & ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q  & ( 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q  & (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0_combout  & ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q  & ( 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q  & 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0_combout ) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1])))) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0_combout ),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .lut_mask = 64'h00450005FF45FF05;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y35_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  = ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & 
// ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0_combout ) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0_combout ))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'h0000000030F030F0;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y35_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout  = ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .lut_mask = 64'hF0F0F0F0F000F000;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y35_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout  = 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout  & 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout )))

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h0100010001000100;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y35_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & 
// (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout )))) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & 
// (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout )) # (\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]))) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout  & 
// ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .lut_mask = 64'h000F000F111F111F;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y35_N23
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y35_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0_combout  & ( 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0_combout  & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0_combout  & 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1])) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h050005000F000F00;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y35_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout  = ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) # 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) ) ) ) # ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .lut_mask = 64'h0000FFFFFCFC3030;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y35_N50
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y35_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout  = ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .lut_mask = 64'h0EF20EF202FE02FE;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y35_N41
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y35_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout  = ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) # 
// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) # 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & ( 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) ) # ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) # 
// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))) ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & ( 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .lut_mask = 64'h5410BAFE1010FEFE;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y35_N32
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y35_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  = ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h0C000C0000000000;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y35_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout  = ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .lut_mask = 64'h02FE02FECE32CE32;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y35_N38
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";
// synopsys translate_on

// Location: FF_X13_Y35_N25
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y35_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout  = ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout )))) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) ) # ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .lut_mask = 64'h00C0FF3F22E2EE2E;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y35_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout  = ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout  & 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout  & 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout  & 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .lut_mask = 64'h8000800000000000;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y35_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout  & 
// ( ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ))) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout  & ( 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h0050005033733373;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y35_N26
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y35_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  = ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  $ 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ))) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .lut_mask = 64'hA000A0005AA05AA0;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y35_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout  & 
// ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout  & ( 
// ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h0F4F0F4F00440044;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y35_N11
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";
// synopsys translate_on

// Location: FF_X13_Y35_N23
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][74] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~7_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][74]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y35_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~7 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~7_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][74]~q  & ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & ( 
// ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1])) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][74]~q  & ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & ( (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & 
// ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))) ) ) ) # ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][74]~q  & ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & ( 
// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][74]~q  & ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][74]~q ),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h00A00FAF50F05FFF;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y35_N32
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";
// synopsys translate_on

// Location: FF_X14_Y35_N11
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y35_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~0_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & ( 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69])) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~0 .lut_mask = 64'h0044004444444444;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y35_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|write~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|write~0_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0_combout  & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~0_combout  ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0_combout  & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~0_combout  & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0_combout  ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0_combout ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0_combout ),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|write~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|write~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h000000000F0FFFFF;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|write~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y35_N29
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][129] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][129]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y35_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~1_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~0_combout  & ( ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][129]~q )) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0_combout ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~0_combout  & ( 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][129]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][129]~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h0303030357575757;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y33_N17
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y35_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|read~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|read~0_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q  & ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0])))) ) ) # 
// ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]))) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|read~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|read~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|read~0 .lut_mask = 64'h1155115510501050;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|read~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y35_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[1]~1_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [1] & ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|read~0_combout  ) ) # 
// ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [1] & ( (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|read~0_combout  & (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0] & 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0])) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|read~0_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[1]~1 .lut_mask = 64'h02020202AAAAAAAA;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[1]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y35_N44
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y35_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[0]~0_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|read~0_combout  & ( ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg 
// [0] & \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|read~0_combout  & ( 
// ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [1])) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|read~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h30FF30FF0F3F0F3F;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y35_N23
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y33_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|comb~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|comb~0_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0] ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0] & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0] & ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|comb~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|comb~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|comb~0 .lut_mask = 64'h1515151555555555;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|comb~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y35_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|comb~0_combout  & ( \u0|hps_0|fpga_interfaces|h2f_RREADY [0] ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|comb~0_combout ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0 .lut_mask = 64'h0000555500005555;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y35_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[0]~1_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0_combout  & ( ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0] & 
// ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout )))) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|write~0_combout 
// ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0_combout  & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|write~0_combout 
// ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|write~0_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h55FF55FF557F557F;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y35_N11
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y35_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0_combout  & ( (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]) # 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0_combout  & ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hCCCCCCCCFCFCFCFC;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y34_N29
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~7_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";
// synopsys translate_on

// Location: FF_X13_Y35_N5
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][75] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][75]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y35_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~6 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~6_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][75]~q  & ( 
// ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][75]~q  & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][75]~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h0404373704043737;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y34_N5
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][75] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~6_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][75]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y34_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout  & 
// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][75]~q  $ (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74]~q )) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout  & 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][75]~q  $ 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74]~q )))) ) ) ) # ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout  & 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][75]~q  $ 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74]~q )))) ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout  & 
// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][75]~q  $ (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74]~q )) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h2133210021002133;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y34_N8
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y34_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~0_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4] ) ) # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4] $ (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h5A5A5A5AAAAAAAAA;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y35_N8
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][76] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][76]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y35_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~5 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~5_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][76]~q  & ( 
// ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4])) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][76]~q  & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4])) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][76]~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h0044337700443377;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y34_N23
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][76] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~5_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][76]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y34_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~0_combout  & ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][76]~q  & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout  & 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][75]~q )))) ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~0_combout  & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][76]~q  & ( 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout  & (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74]~q )) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][75]~q ))) ) ) ) # ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~0_combout  & ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][76]~q  & ( (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][75]~q  & (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout  & 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74]~q  & !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~0_combout  & ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][76]~q  & ( 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout  & (((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][75]~q  & !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74]~q )) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~0_combout ),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h2033200013331300;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y34_N38
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";
// synopsys translate_on

// Location: FF_X13_Y35_N47
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][78] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][78]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y35_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~3 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~3_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][78]~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][78]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][78]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h000F000F505F505F;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y34_N20
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][78] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~3_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][78]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";
// synopsys translate_on

// Location: FF_X13_Y35_N14
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][77] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][77]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y35_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~4 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~4_combout  = (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & 
// (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][77]~q ))))

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][77]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~4 .lut_mask = 64'h0437043704370437;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y34_N47
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][77] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~4_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][77]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y34_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~0_combout  = ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][76]~q  & ( (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74]~q  & 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][77]~q  & !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][75]~q )) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][77]~q ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~0 .lut_mask = 64'hA000A00000000000;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y34_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~2_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5] ) ) # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5] $ (((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h3FC03FC0FF00FF00;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y34_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~1_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][76]~q  & ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][77]~q  ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][76]~q  & ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][77]~q  $ (((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][75]~q  & 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][77]~q ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h5AF05AF0F0F0F0F0;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y34_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~1_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~2_combout  & (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout  & 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout )) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~1_combout  & ( 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~2_combout ) # 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~2_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h0F0A0F0A000A000A;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y34_N59
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y34_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~1_combout  = ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~1 .lut_mask = 64'hC000C00000000000;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y34_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~1_combout  & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout  & 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][78]~q  $ 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~0_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~1_combout  & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][78]~q 
//  $ (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~0_combout )) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~1_combout  & ( 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][78]~q  $ (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~0_combout 
// )) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~1_combout  & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout  & 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][78]~q  $ 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~0_combout )))) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][78]~q ),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~0_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h1200123312331200;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y34_N14
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y34_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~1_combout  = (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5])))

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'h8000800080008000;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y34_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~1_combout  & ( (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout ) ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~1_combout  & ( (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][78]~q  & (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~0_combout  & 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout )) ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~1_combout  & ( (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][78]~q  & (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~0_combout  & 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][78]~q ),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~0_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),
        .datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h000A0000000A00CC;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y34_N32
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";
// synopsys translate_on

// Location: FF_X13_Y34_N35
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_busy (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y34_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_busy~q  & ( 
// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~1_combout ) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [7])) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h00000000DFDFDFDF;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y34_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout  = ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout  & ( 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h2233223300000000;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y34_N50
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y34_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_busy~q  & ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y34_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~0_combout  = ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][75]~q  & ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_busy~q  & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74]~q  & (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][77]~q  & 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][78]~q  & !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][76]~q ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][77]~q ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][78]~q ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][75]~q ),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h4000000000000000;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y33_N35
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][66]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y33_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~2_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & ( 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][66]~q ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][66]~q ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][66]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~2 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y33_N32
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~2_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][66]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y33_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][66]~q  & ( (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|comb~0_combout ) # 
// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~0_combout  & ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout ) # 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~1_combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|comb~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][66]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h00000000FFE0FFE0;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y35_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[1]~0_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout  & ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|write~0_combout ))) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|write~0_combout ) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]))) 
// ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0_combout  & ( 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout  & (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0] & \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|write~0_combout )) ) ) 
// ) # ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0_combout  & ( (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|write~0_combout ) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]) ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0_combout  & ( 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0] & \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|write~0_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|write~0_combout ),
        .datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[1]~0 .lut_mask = 64'h000FFF0F000555AF;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[1]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y35_N41
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y35_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  = 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & 
// ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0_combout ) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0_combout ))))

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hFF4CFF4CFF4CFF4C;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y35_N56
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y35_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout  = ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])))) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & (!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]))) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])))) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & (!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .lut_mask = 64'h10BA10BABA10BA10;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y35_N44
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y35_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout  = ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg 
// [2])) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1])))) ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1])))) ) ) ) # ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg 
// [2]) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
        .datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .lut_mask = 64'h0808A2A2085DA2F7;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y35_N32
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y35_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  = ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] $ 
// (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .lut_mask = 64'hB4B4B4B4F0F0F0F0;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y35_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout  = ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # ((\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .lut_mask = 64'hABABABAB01010101;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y35_N47
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y35_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  = ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .lut_mask = 64'h0C000C0000000000;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y35_N52
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y35_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout  = ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & ( \u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & ( 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout )) 
// # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ))) ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & ( \u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & ( 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout )) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ))) ) ) ) # ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & ( !\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & ( 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ) ) 
// ) ) # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & ( !\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & ( 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ) ) ) 
// )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .lut_mask = 64'h2222888827278D8D;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y35_N38
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y35_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout  = ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ) 
// # ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1])))) ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  & 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1])))) ) ) ) # ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ) 
// # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  & 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
        .datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .lut_mask = 64'h20208A8A20758ADF;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X10_Y35_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout  = ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout  & ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout  & ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout  & ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout  & ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  ) ) ) # ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout  & ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout  & ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout  & ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout  & ( 
// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout  & 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout  & 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ))) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
        .datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .lut_mask = 64'h20FF00FF00FF00FF;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y35_N20
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y35_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  = ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & 
// ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0_combout ) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0_combout )))) ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0_combout ),
        .datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .lut_mask = 64'hAAAA088800000000;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y35_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout  = ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// (((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q )))) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q )) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3 .lut_mask = 64'h0CAA0CAA00AA00AA;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y35_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout  = ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  & 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout  & 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ))) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  & 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4 .lut_mask = 64'hC0C0C0C080008000;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y35_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_006|packet_in_progress~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_006|packet_in_progress~0_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout  & ( 
// ((\u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout  & \u0|mm_interconnect_0|cmd_mux_006|saved_grant [1])) # (\u0|mm_interconnect_0|cmd_mux_006|packet_in_progress~q ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout  & ( (\u0|mm_interconnect_0|cmd_mux_006|packet_in_progress~q  & ((!\u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout ) 
// # (!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]))) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_006|packet_in_progress~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_006|packet_in_progress~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_006|packet_in_progress~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_006|packet_in_progress~0 .lut_mask = 64'h00FA00FA05FF05FF;
defparam \u0|mm_interconnect_0|cmd_mux_006|packet_in_progress~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y35_N41
dffeas \u0|mm_interconnect_0|cmd_mux_006|packet_in_progress (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_006|packet_in_progress~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_006|packet_in_progress~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_006|packet_in_progress .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_006|packet_in_progress .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y35_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_006|update_grant~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_006|update_grant~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_006|packet_in_progress~q  & ( (\u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout  & (\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_006|packet_in_progress~q  & ( 
// (!\u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout ) # ((!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]) # (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_006|packet_in_progress~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_006|update_grant~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_006|update_grant~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_006|update_grant~0 .lut_mask = 64'hFEFEFEFE10101010;
defparam \u0|mm_interconnect_0|cmd_mux_006|update_grant~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y35_N17
dffeas \u0|mm_interconnect_0|cmd_mux_006|saved_grant[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|cmd_mux_006|update_grant~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_006|saved_grant[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_006|saved_grant[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y35_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & ( !\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & ( (!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]) # (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
        .datac(gnd),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .lut_mask = 64'hFFCCCCCCFFCCCCCC;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y35_N32
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y35_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0_combout  = ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q  & (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] 
// & (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg 
// [1]))) ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] 
// & !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1])) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0 .lut_mask = 64'hC000000080000000;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y35_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter~0_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~0_combout  & ( (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0_combout  & 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|waitrequest_reset_override~q  & !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter [0])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|waitrequest_reset_override~q ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter~0 .lut_mask = 64'h000000000C000C00;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y35_N5
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y35_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg~0_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~0_combout  & ( 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|waitrequest_reset_override~q  & (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter [0] & !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0_combout )) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|waitrequest_reset_override~q ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter [0]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg~0 .lut_mask = 64'h0000000003000300;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y35_N44
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y33_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_006|src_payload~11 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_006|src_payload~11_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [11] & ( \u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_006|src_payload~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~11 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~11 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y33_N11
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_006|src_payload~11_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";
// synopsys translate_on

// Location: FF_X11_Y33_N47
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~20_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][116]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y33_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~20 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~20_combout  = (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116])) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & 
// ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][116]~q )))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][116]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~20 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~20 .lut_mask = 64'h0C3F0C3F0C3F0C3F;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~20 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y33_N2
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~20_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][116]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y33_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~57 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~57_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][116]~q  ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][116]~q  & (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q  & 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0])) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][116]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~57_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~57 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~57 .lut_mask = 64'h0057005700FF00FF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~57 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y31_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal7~1 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal7~1_combout  = ( \u0|mm_interconnect_0|router_001|Equal7~0_combout  & ( (\u0|mm_interconnect_0|router_001|Equal1~1_combout  & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & 
// (\u0|mm_interconnect_0|router_001|Equal1~0_combout  & \u0|mm_interconnect_0|router_001|Equal1~2_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),
        .datac(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),
        .datad(!\u0|mm_interconnect_0|router_001|Equal1~2_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|router_001|Equal7~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router_001|Equal7~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal7~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal7~1 .lut_mask = 64'h0000000000040004;
defparam \u0|mm_interconnect_0|router_001|Equal7~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y31_N20
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|router_001|Equal7~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y31_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|src4_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|src4_valid~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [4] & ( \u0|hps_0|fpga_interfaces|h2f_ARVALID [0] ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel 
// [4] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q  & \u0|hps_0|fpga_interfaces|h2f_ARVALID [0]) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux_001|src4_valid~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|src4_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|src4_valid~0 .lut_mask = 64'h00AA00AA00FF00FF;
defparam \u0|mm_interconnect_0|cmd_demux_001|src4_valid~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y31_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|src4_valid~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|src4_valid~1_combout  = ( \u0|mm_interconnect_0|router_001|Equal1~2_combout  & ( \u0|mm_interconnect_0|router_001|Equal7~0_combout  & ( (\u0|mm_interconnect_0|router_001|Equal1~0_combout  & 
// (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & (\u0|mm_interconnect_0|cmd_demux_001|src4_valid~0_combout  & \u0|mm_interconnect_0|router_001|Equal1~1_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),
        .datac(!\u0|mm_interconnect_0|cmd_demux_001|src4_valid~0_combout ),
        .datad(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),
        .datae(!\u0|mm_interconnect_0|router_001|Equal1~2_combout ),
        .dataf(!\u0|mm_interconnect_0|router_001|Equal7~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux_001|src4_valid~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|src4_valid~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|src4_valid~1 .lut_mask = 64'h0000000000000004;
defparam \u0|mm_interconnect_0|cmd_demux_001|src4_valid~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y27_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|router|Equal7~2 (
// Equation(s):
// \u0|mm_interconnect_0|router|Equal7~2_combout  = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout  & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout  & 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout ),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router|Equal7~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router|Equal7~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router|Equal7~2 .lut_mask = 64'hF000F00000000000;
defparam \u0|mm_interconnect_0|router|Equal7~2 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y27_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|router|Equal7~3 (
// Equation(s):
// \u0|mm_interconnect_0|router|Equal7~3_combout  = ( \u0|mm_interconnect_0|router|Equal7~2_combout  & ( (\u0|mm_interconnect_0|router|Equal7~1_combout  & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~3_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|router|Equal7~1_combout ),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~3_combout ),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|router|Equal7~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router|Equal7~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router|Equal7~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router|Equal7~3 .lut_mask = 64'h0000000011111111;
defparam \u0|mm_interconnect_0|router|Equal7~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y27_N46
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|router|Equal7~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y27_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|src4_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|src4_valid~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q  & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout  & 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [4]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q  & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout ),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [4]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux|src4_valid~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|src4_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|src4_valid~0 .lut_mask = 64'h0F0F0F0F000F000F;
defparam \u0|mm_interconnect_0|cmd_demux|src4_valid~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y27_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|src4_valid~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|src4_valid~1_combout  = ( \u0|mm_interconnect_0|cmd_demux|src4_valid~0_combout  & ( (\u0|mm_interconnect_0|router|Equal7~2_combout  & 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~3_combout  & \u0|mm_interconnect_0|router|Equal7~1_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|router|Equal7~2_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~3_combout ),
        .datad(!\u0|mm_interconnect_0|router|Equal7~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_demux|src4_valid~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux|src4_valid~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|src4_valid~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|src4_valid~1 .lut_mask = 64'h0000000000050005;
defparam \u0|mm_interconnect_0|cmd_demux|src4_valid~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y27_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|src_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|src_valid~0_combout  = ( \u0|mm_interconnect_0|router|Equal7~2_combout  & ( \u0|mm_interconnect_0|router|Equal7~1_combout  & ( (\u0|mm_interconnect_0|cmd_demux|src4_valid~0_combout  & 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~3_combout  & \u0|mm_interconnect_0|cmd_mux_004|saved_grant [0])) ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_demux|src4_valid~0_combout ),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~3_combout ),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
        .datae(!\u0|mm_interconnect_0|router|Equal7~2_combout ),
        .dataf(!\u0|mm_interconnect_0|router|Equal7~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_004|src_valid~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|src_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|src_valid~0 .lut_mask = 64'h0000000000000011;
defparam \u0|mm_interconnect_0|cmd_mux_004|src_valid~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y27_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|arb|grant[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|arb|grant[1]~0_combout  = ( \u0|mm_interconnect_0|cmd_demux_001|src4_valid~1_combout  & ( ((!\u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg [0] & !\u0|mm_interconnect_0|cmd_demux|src4_valid~1_combout )) # 
// (\u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg [1]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg [0]),
        .datad(!\u0|mm_interconnect_0|cmd_demux|src4_valid~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_demux_001|src4_valid~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_004|arb|grant[1]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|arb|grant[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|arb|grant[1]~0 .lut_mask = 64'h00000000F555F555;
defparam \u0|mm_interconnect_0|cmd_mux_004|arb|grant[1]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y27_N17
dffeas \u0|mm_interconnect_0|cmd_mux_004|saved_grant[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_004|arb|grant[1]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|cmd_mux_004|update_grant~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|saved_grant[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_004|saved_grant[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y27_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|src_valid~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|src_valid~1_combout  = ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & ( \u0|mm_interconnect_0|cmd_demux_001|src4_valid~1_combout  ) )

        .dataa(!\u0|mm_interconnect_0|cmd_demux_001|src4_valid~1_combout ),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_004|src_valid~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|src_valid~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|src_valid~1 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_004|src_valid~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y27_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|src_payload[0] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|src_payload [0] = ( \u0|hps_0|fpga_interfaces|h2f_WLAST [0] & ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_WLAST [0] & ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] ) ) 
// # ( \u0|hps_0|fpga_interfaces|h2f_WLAST [0] & ( !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
        .datad(gnd),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_WLAST [0]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_004|src_payload [0]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|src_payload[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|src_payload[0] .lut_mask = 64'h00000F0FFFFFFFFF;
defparam \u0|mm_interconnect_0|cmd_mux_004|src_payload[0] .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y27_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|src_data[33] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|src_data [33] = ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] ) # ( !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_WSTRB [1] & \u0|mm_interconnect_0|cmd_mux_004|saved_grant 
// [0]) ) )

        .dataa(gnd),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [1]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_004|src_data [33]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[33] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[33] .lut_mask = 64'h00330033FFFFFFFF;
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[33] .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y27_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y27_N50
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y27_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & ( 
// (!\u0|mm_interconnect_0|cmd_mux_004|src_valid~1_combout  & !\u0|mm_interconnect_0|cmd_mux_004|src_valid~0_combout ) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_004|src_valid~1_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_004|src_valid~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .lut_mask = 64'hFFFFFFFFF000F000;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y27_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout  & ( 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) 
// ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout  )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .lut_mask = 64'hFFFFFFFF50505050;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y27_N56
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y27_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write~0_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] & ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write~0 .lut_mask = 64'h0000000000FF00FF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y27_N23
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";
// synopsys translate_on

// Location: FF_X14_Y27_N50
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y27_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_read~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_read~0_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & ( 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_read~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_read~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_read~0 .lut_mask = 64'h000F000F0F0F0F0F;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_read~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y27_N38
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][129] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][129]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y27_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~0_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][129]~q  & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout  & ( 
// (((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & \u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write~0_combout )) # 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_read~0_combout )) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][129]~q  & ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout  & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & 
// (((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & \u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write~0_combout )) # 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_read~0_combout ))) ) ) ) # ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][129]~q  & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout  & ( 
// ((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & \u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write~0_combout )) # 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][129]~q  & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout  & ( 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & 
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write~0_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write~0_combout ),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_read~0_combout ),
        .datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][129]~q ),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~0 .lut_mask = 64'h0202575702AA57FF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y29_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][129]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][129]~feeder_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~0_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][129]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][129]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][129]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][129]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y27_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~feeder (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y27_N53
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y27_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter~2_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter~0_combout  & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [0] $ 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [1]) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [0]),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter~2 .lut_mask = 64'h000000000FF00FF0;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y27_N26
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y27_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~0_combout  = ( !\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [1] & ( \u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~q  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~0 .lut_mask = 64'h0F0F0F0F00000000;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y27_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~4 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~4_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout  & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [0] & 
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~0_combout ) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout  & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~0_combout  & 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [0] $ (((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write~0_combout ) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]))))) ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [0]),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~0_combout ),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~4 .lut_mask = 64'h1121112111111111;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y27_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|write~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|write~0_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~4_combout  & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_read~0_combout  & ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] ) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~4_combout  & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_read~0_combout  & ( 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout  & !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~4_combout  & ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_read~0_combout  & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write~0_combout  & 
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout )) ) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~4_combout  & ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_read~0_combout  & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout  & (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write~0_combout  & \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout ),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write~0_combout ),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~4_combout ),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_read~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|write~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|write~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h0004000C4444CCCC;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|write~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y27_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y27_N26
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y27_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~1_combout  & ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y29_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout  = ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) # 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) # ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  $ 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .lut_mask = 64'h0FF00FF00AFA0AFA;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y29_N56
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y29_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout  = ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) # 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) # ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] $ 
// (((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) # 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .lut_mask = 64'h0AF50AF50CFC0CFC;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y29_N38
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";
// synopsys translate_on

// Location: FF_X14_Y29_N53
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][75] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][75]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y29_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout  = ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) # 
// ((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) # 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) ) # ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) # 
// ((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) # 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg 
// [2])))) ) ) ) # ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) ) # ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) # 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg 
// [2]))))) ) ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .lut_mask = 64'h0B080300F7F4FFFC;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y29_N8
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y29_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  = ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h00000000C000C000;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y29_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout  = ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & ( 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout 
// )))) # (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// ((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # 
// ((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )))) ) ) # ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & ( 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout )))) 
// # (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg 
// [2] & ((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .lut_mask = 64'h330A330ACCFACCFA;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y29_N11
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";
// synopsys translate_on

// Location: FF_X14_Y29_N31
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y29_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout  = ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg 
// [2]) # (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) ) ) ) # ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] 
// & \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) ) ) ) # ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) # 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) ) ) ) # ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) ) 
// ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 .lut_mask = 64'h00CCFF330A0AFAFA;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y29_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout  = ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout  & ( 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout  & 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0 .lut_mask = 64'hC0C0C0C000000000;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y29_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// ((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) # 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))) ) ) ) # ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h0505070700000000;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y29_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & ( 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h000000000F000F00;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y29_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout  = ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout  & ( 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ) # (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout  & ( 
// ((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout  & ((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ) # 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout )))) # 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h0DFF0DFF0FFF0FFF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y29_N5
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y29_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~6 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~6_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) # 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][75]~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][75]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][75]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h000F000F505F505F;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y29_N29
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][75] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~6_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][75]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";
// synopsys translate_on

// Location: FF_X14_Y29_N50
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][74] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~5_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][74]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y29_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~5 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~5_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][74]~q  ) ) # ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// ((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))) # 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][74]~q ),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h335533550F0F0F0F;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y29_N26
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][74] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~5_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][74]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";
// synopsys translate_on

// Location: FF_X14_Y29_N23
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][78] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~9_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][78]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y29_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~9 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~9_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) # 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][78]~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][78]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][78]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~9 .lut_mask = 64'h000F000F505F505F;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~9 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y29_N14
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][78] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~9_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][78]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";
// synopsys translate_on

// Location: FF_X13_Y29_N5
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_busy (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y29_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~2_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_busy~q  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h0000000000FF00FF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y29_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout  = ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~2_combout  & ( 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][74]~q ) # 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~combout ),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h3131313100000000;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y29_N44
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y28_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~0_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] $ (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h0FF00FF0F0F0F0F0;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y29_N47
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][76] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~7_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][76]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y29_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~7 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~7_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4])) # 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][76]~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][76]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][76]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h005500550A5F0A5F;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y29_N17
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][76] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~7_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][76]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y29_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][75]~q  & ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~combout  & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// ((\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][76]~q ))) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~0_combout )) ) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][75]~q  & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~combout  & ( 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][76]~q  $ (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][74]~q )))) 
// # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~0_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~0_combout ),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][75]~q ),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h00000000E44E4E4E;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y29_N8
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";
// synopsys translate_on

// Location: FF_X14_Y29_N20
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][77] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][77]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y29_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~8 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~8_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][77]~q  ) ) # ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][77]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~8 .lut_mask = 64'h1111111100FF00FF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~8 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y29_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][77]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][77]~feeder_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~8_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~8_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][77]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][77]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][77]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][77]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y29_N59
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][77] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][77]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][77]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y29_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add1~1_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][74]~q  & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][77]~q  ) ) # ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][74]~q  & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][77]~q  $ (((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][76]~q  & 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][75]~q ))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][77]~q ),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h3CF03CF0F0F0F0F0;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add1~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y29_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~2_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5] ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5] $ (((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h3FC03FC0FF00FF00;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y29_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~combout  & ( 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add1~1_combout )) # 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~2_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add1~1_combout ),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~2_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h00000000F5A0F5A0;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y29_N59
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y29_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~1_combout  = ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~1 .lut_mask = 64'hC000C00000000000;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y29_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add1~0_combout  = ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][75]~q  & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][74]~q  & 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][76]~q  & !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][77]~q )) ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][77]~q ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][75]~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add1~0 .lut_mask = 64'h8080000080800000;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add1~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y29_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add1~0_combout  & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~combout  & 
// ((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][78]~q ))) # 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~1_combout )))) ) ) ) # ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add1~0_combout  & ( 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// ((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][78]~q ))) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~1_combout )))) ) ) ) # ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add1~0_combout  & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~combout  & 
// ((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ((\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][78]~q ))) # 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~1_combout )))) ) ) ) # ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add1~0_combout  & ( 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// ((\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][78]~q ))) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~1_combout )))) ) ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~combout ),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~1_combout ),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][78]~q ),
        .datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add1~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h0123103223013210;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y29_N50
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y29_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~1_combout  & ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add1~0_combout  & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~combout  & 
// ((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][78]~q )) # 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]))))) ) ) ) # ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~1_combout  & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add1~0_combout  & ( 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][78]~q  & 
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~combout )) ) ) ) # ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~1_combout  & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add1~0_combout  
// & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & 
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][78]~q ),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~combout ),
        .datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~1_combout ),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add1~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h00000050008800D8;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y29_N14
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y29_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_busy~q  ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_busy~q  & ((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~1_combout ) # 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [7]))) ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h00AF00AF00FF00FF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y29_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~combout  & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][75]~q  $ ((\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][74]~q )))) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (((\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~combout  & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][75]~q  $ ((\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][74]~q )))) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h000000009F90909F;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y29_N32
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y29_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~1_combout  = ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'hC000C00000000000;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y29_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~0_combout  = ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_busy~q  & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][74]~q  & ( 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][78]~q  & (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][76]~q  & (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][75]~q  & 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][77]~q ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][78]~q ),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][77]~q ),
        .datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h0000000080000000;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y29_N41
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][66]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y29_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~3 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~3_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][66]~q  & ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][66]~q  & ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] ) ) ) # ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][66]~q  & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][66]~q ),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h00000F0FF0F0FFFF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y29_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][66]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][66]~feeder_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~3_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][66]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][66]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][66]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][66]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y29_N32
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][66]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][66]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y29_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~2_combout  & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][66]~q  & 
// ((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|comb~0_combout ) # ((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~1_combout  & !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~0_combout )))) 
// ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~2_combout  & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][66]~q  & 
// ((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~0_combout ) # (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|comb~0_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|comb~0_combout ),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][66]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h00FC00FC00F800F8;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y29_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used[0]~1_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [0]) # 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|write~0_combout ) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & ( ((\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [0] & 
// ((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|always0~0_combout ) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~combout )))) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|write~0_combout ) ) 
// )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|always0~0_combout ),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|write~0_combout ),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~combout ),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h33BF33BF33FF33FF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y29_N38
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y29_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~combout  & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|always0~0_combout  & ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [0] ) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~combout  & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|always0~0_combout  ) ) # 
// ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~combout  & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|always0~0_combout  & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [0] ) ) ) # ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~combout  & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|always0~0_combout  & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [0] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [0]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~combout ),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|always0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hF0F0F0F0FFFFF0F0;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y29_N38
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][129] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][129]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][129]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y27_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg~0_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_read~0_combout  & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout  & 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]) ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout ),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_read~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg~0 .lut_mask = 64'h0000000088888888;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y27_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg~1_combout  = (\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg~0_combout  & \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~4_combout )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg~0_combout ),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~4_combout ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg~1 .lut_mask = 64'h0055005500550055;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y29_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg[0]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg[0]~feeder_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg~1_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg[0]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg[0]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg[0]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg[0]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y29_N38
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg[0]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y29_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~0_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [0] & ( ((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [0] & 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][129]~q ) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [0] & ( 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [0] & !\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg [0]) ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [0]),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~0 .lut_mask = 64'hF000F000F555F555;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y29_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~1_combout  = ( \u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~0_combout  & 
// ((!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ) # (\u0|hps_0|fpga_interfaces|h2f_BREADY [0]))) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ( (\u0|hps_0|fpga_interfaces|h2f_BREADY [0] & 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~0_combout  & \u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout )) ) )

        .dataa(gnd),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_BREADY [0]),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~0_combout ),
        .datad(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~1 .lut_mask = 64'h00300030F030F030;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y29_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[1]~1_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [0] & ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~1_combout  ) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [0] & ( 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~1_combout  & \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg [0]) ) ) ) # ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [1] & ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [0] & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~1_combout  ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~1_combout ),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg [0]),
        .datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [1]),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[1]~1 .lut_mask = 64'h0000F0F000F0F0F0;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[1]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y29_N11
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y29_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[0]~0_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~1_combout  & ( 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [1]) # (\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg [0]) ) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [0] & ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~1_combout  & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [1] ) ) ) # ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [0] & ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~1_combout  ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [0] & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~1_combout  & ( 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [1]) ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg [0]),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [1]),
        .datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [0]),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h0F00FFFF00FF0FFF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y29_N26
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y29_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|comb~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|comb~0_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [0] ) ) # ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg [0] & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [0] & ((\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [0]) # 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][129]~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [0]),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|comb~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|comb~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|comb~0 .lut_mask = 64'h005F005F00FF00FF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|comb~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y29_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|always0~0_combout  = ( \u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|comb~0_combout  & ((!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ) 
// # (\u0|hps_0|fpga_interfaces|h2f_BREADY [0]))) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|comb~0_combout  & (\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout  & 
// \u0|hps_0|fpga_interfaces|h2f_BREADY [0])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|comb~0_combout ),
        .datac(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_BREADY [0]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|always0~0 .lut_mask = 64'h0003000330333033;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y29_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used[1]~0_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|write~0_combout  & 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & ((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|always0~0_combout ) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~combout )))) # 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|write~0_combout  & ((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|always0~0_combout ) # ((\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]) # 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~combout )))) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|write~0_combout  $ (((\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|always0~0_combout  & !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~combout ))))) ) 
// )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|always0~0_combout ),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|write~0_combout ),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~combout ),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used[1]~0 .lut_mask = 64'h009C009C23BF23BF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used[1]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y29_N41
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y27_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_write (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_write~combout  = ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout  & 
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write~0_combout ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout ),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_write~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_write .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_write .lut_mask = 64'h00F000F000000000;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_write .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y27_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter~0_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~q  & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_write~combout  & 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg~0_combout  & ((!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [0]) # (\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [1])))) # 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_write~combout  & (((\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [1])) # (\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [0]))) ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [0]),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_write~combout ),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg~0_combout ),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter~0 .lut_mask = 64'h00000000193F193F;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y27_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter~1_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter~0_combout  & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [0] ) 
// )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter~1 .lut_mask = 64'h00000000FF00FF00;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y27_N23
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y27_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & 
// (((!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [0] & \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~0_combout )) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout ))) ) ) ) # ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] ) ) # ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] & ( 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & (((\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [0] & \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~0_combout )) # 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [0]),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~0_combout ),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout ),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hFFFF1F00FFFF2F00;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y29_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout 
// ) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & 
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .lut_mask = 64'h0010001050505050;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y27_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout  = ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .lut_mask = 64'hF0F0F0F000000000;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y27_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout  = ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( 
// ((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & ((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout 
// ) # (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q )))) # 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  
// ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) 
// ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datae(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .lut_mask = 64'h000000F0333333FB;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y27_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout  = ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout  & ( 
// (!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout  & 
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16 .lut_mask = 64'h0202020200000000;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y29_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & ( 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .lut_mask = 64'h000000000F000F00;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y29_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  & ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout  ) ) # ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  & ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout  & ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout  ) ) ) # ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  & ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout  ) ) # ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  & ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout  & ( 
// ((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout  & (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout  & 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ))) # 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout ),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ),
        .datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17 .lut_mask = 64'h1F0FFFFF0F0FFFFF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y29_N44
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";
// synopsys translate_on

// Location: FF_X21_Y27_N59
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_004|src_payload [0]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y27_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// ( (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q )) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  
// & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// ((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) # (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q 
// )))) ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h5040504050005000;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y28_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout  & ( 
// !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout  & ( (!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & 
// !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .lut_mask = 64'h88888888CCCCCCCC;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y28_N17
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y27_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|src_data[35] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|src_data [35] = ( \u0|hps_0|fpga_interfaces|h2f_WSTRB [3] & ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_WSTRB [3] & ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & ( 
// \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_WSTRB [3] & ( !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_WSTRB 
// [3] & ( !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [3]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_004|src_data [35]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[35] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[35] .lut_mask = 64'h333333333333FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[35] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y27_N32
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_004|src_data [35]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y27_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|src_data[32] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|src_data [32] = ( \u0|hps_0|fpga_interfaces|h2f_WSTRB [0] & ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_WSTRB [0] & ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] ) ) # 
// ( \u0|hps_0|fpga_interfaces|h2f_WSTRB [0] & ( !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
        .datad(gnd),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [0]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_004|src_data [32]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[32] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[32] .lut_mask = 64'h00000F0FFFFFFFFF;
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[32] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y27_N5
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_004|src_data [32]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y27_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|src_data[34] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|src_data [34] = ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & ( (\u0|hps_0|fpga_interfaces|h2f_WSTRB [2]) # (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]) ) ) # ( 
// !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [2]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_004|src_data [34]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[34] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[34] .lut_mask = 64'h55555F5F55555F5F;
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[34] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y27_N5
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_004|src_data [34]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y27_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~2_combout  = ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & ( 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0])) ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~2 .lut_mask = 64'hA000A00000000000;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y28_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|src_data[88] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|src_data [88] = ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & ( (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]) # (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]) ) ) ) # 
// ( !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & ( !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & ( 
// \u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
        .datad(gnd),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_004|src_data [88]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[88] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[88] .lut_mask = 64'h000055550F0F5F5F;
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[88] .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y28_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|src_data[87] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|src_data [87] = ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & ( ((\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1])) # (\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]) ) ) # ( 
// !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & ( (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_004|src_data [87]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[87] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[87] .lut_mask = 64'h003300330F3F0F3F;
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[87] .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y28_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout  = ( !\u0|mm_interconnect_0|cmd_mux_004|src_data [87] & ( !\u0|mm_interconnect_0|cmd_mux_004|src_data [88] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|cmd_mux_004|src_data [88]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_004|src_data [87]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .lut_mask = 64'hFF00FF0000000000;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y28_N5
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y27_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~3 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~3_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q  & ( 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~0_combout  & (!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [0] $ (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write~0_combout ))) ) ) # ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q  & ( ((\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~0_combout  & 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [0] $ (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write~0_combout )))) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~2_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~2_combout ),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~0_combout ),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [0]),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~3 .lut_mask = 64'h5775577503300330;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y27_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & ( 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q 
// ) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// ((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~3_combout  & (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q )) # 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~3_combout  & ((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))))) ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~3_combout ),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .lut_mask = 64'h4540454044444444;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y27_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout  & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  ) ) ) # 
// ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout  & ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  ) ) ) # ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout  & ( 
// (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  & ((!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]) # 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout )))) ) ) ) # ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout  & ( 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  & ((!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]) # 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
        .datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .lut_mask = 64'hAF002300FF00FF00;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y27_N44
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y27_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~4_combout  & ( 
// (!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0] & \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~4_combout  & ( ((!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0] & 
// \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1])) # (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~4_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 .lut_mask = 64'h55F555F500F000F0;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y27_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout  = ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout  ) ) # ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] $ 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]) ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout ),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 .lut_mask = 64'h55AA55AA0F0F0F0F;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y27_N41
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y27_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3_combout  & ( 
// ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout  & \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1])) # (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]) ) ) # ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3_combout  & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout  & \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5 .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y27_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout  = ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout  & ( 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] $ 
// (((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])))) # (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q 
// ) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout  & ( 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] 
// $ (((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))))) ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6 .lut_mask = 64'h40B040B04FBF4FBF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y27_N38
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y27_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] ) ) # ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] $ (((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg 
// [2] & !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .lut_mask = 64'hC3CCC3CCCCCCCCCC;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y27_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout  = ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout )) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ))) ) ) ) # ( 
// !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  & ( (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout )) ) ) ) # ( 
// \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  & ( 
// ((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # ((\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout 
// ))) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout 
//  & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # ((\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout ),
        .datae(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .lut_mask = 64'hF0F5F3F700050307;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y27_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  = ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & 
// ( (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg 
// [4] & !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3])) ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .lut_mask = 64'h5000500000000000;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y27_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~1_combout  & ( 
// ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout  & \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1])) # (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]) ) ) # ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~1_combout  & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout  & \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y27_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout  = ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout  & ( 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ) # (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) ) # ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout  & ( 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ) # (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) ) # ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout  & ( 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ) ) ) ) # ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout  & ( 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 .lut_mask = 64'h222288887777DDDD;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y27_N13
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .power_up = "low";
// synopsys translate_on

// Location: FF_X14_Y27_N29
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y27_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~0_combout  ) ) # ( !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~0_combout  & ( 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout  & \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~0_combout  & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout  & \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]) ) ) ) # ( 
// !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~0_combout  & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout  & \u0|mm_interconnect_0|cmd_mux_004|saved_grant 
// [1]) ) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
        .datae(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .lut_mask = 64'h005500550055FFFF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y27_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout  = ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout  & ( 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] $ (((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout 
// ) # (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) # 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) # ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout  & ( 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] 
// $ (((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ) # (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg 
// [5]))))) ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 .lut_mask = 64'h208A208A75DF75DF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y27_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout  = ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout  & ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout  & ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  ) ) ) # ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout  & ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout  & ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  ) ) ) # ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout  & ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout  & ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  ) ) ) # ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout  & ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout  & ( 
// ((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout  & 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout  & 
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ))) # 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout ),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ),
        .datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .lut_mask = 64'h55D5555555555555;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y27_N56
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y27_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  = ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  
// & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q 
// ))) ) ) # ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( 
// (((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # ((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~1_combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~1_combout ),
        .datag(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .extended_lut = "on";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .lut_mask = 64'h0808F0F00808F0FF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y27_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout  = ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & ((\u0|mm_interconnect_0|cmd_mux_004|src_valid~0_combout ) # (\u0|mm_interconnect_0|cmd_mux_004|src_valid~1_combout )))) # 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & (((\u0|mm_interconnect_0|cmd_mux_004|src_valid~0_combout ) # (\u0|mm_interconnect_0|cmd_mux_004|src_valid~1_combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_004|src_valid~1_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_004|src_valid~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h0000000007770777;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y27_N38
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_004|src_data [33]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y27_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ))) ) ) ) # ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & ( 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2])) ) ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0 .lut_mask = 64'h8080800000000000;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y27_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~1_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~0_combout  & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & 
// ((!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [0] $ (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write~0_combout )) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout ))) ) ) # ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~0_combout  & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout  & !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]) ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout ),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [0]),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~1 .lut_mask = 64'h444444444CC44CC4;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y27_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q  
// & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & (((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q )))) 
// # (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~1_combout ) # 
// ((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )))) ) ) # ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q  & ( 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & (((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q )))) # 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~1_combout  & 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~1_combout ),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .lut_mask = 64'h01AB01AB45EF45EF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y27_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18_combout  = ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & ( 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ) # 
// ((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) # (((!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1])) # 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ))) ) ) # ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & ( 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ) # 
// (((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout )))) 
// ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
        .datag(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18 .extended_lut = "on";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18 .lut_mask = 64'hFFEAAAAAFFFFAAAF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y27_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1_combout  = ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1 .lut_mask = 64'hFFFFFFFF00000000;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y27_N38
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y27_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  = (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q 
// ))) # (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & 
// ((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  $ 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ))) # 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q 
// ))))

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .lut_mask = 64'h9440944094409440;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y27_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  & ( 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  
// & !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout )) ) ) # ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  
// & ((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) # 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .lut_mask = 64'h050F050F05000500;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y27_N23
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y27_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q 
//  & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) ) # ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout )) ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'h000A000A00AA00AA;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y27_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|packet_in_progress~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|packet_in_progress~0_combout  = ( !\u0|mm_interconnect_0|cmd_mux_004|update_grant~0_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_004|update_grant~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_004|packet_in_progress~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|packet_in_progress~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|packet_in_progress~0 .lut_mask = 64'hFFFFFFFF00000000;
defparam \u0|mm_interconnect_0|cmd_mux_004|packet_in_progress~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y27_N32
dffeas \u0|mm_interconnect_0|cmd_mux_004|packet_in_progress (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_004|packet_in_progress~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_004|packet_in_progress~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|packet_in_progress .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_004|packet_in_progress .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y27_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|update_grant~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|update_grant~0_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & ( \u0|mm_interconnect_0|cmd_mux_004|packet_in_progress~q  & ( 
// (\u0|mm_interconnect_0|cmd_mux_004|src_payload [0] & ((\u0|mm_interconnect_0|cmd_mux_004|src_valid~1_combout ) # (\u0|mm_interconnect_0|cmd_mux_004|src_valid~0_combout ))) ) ) ) # ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & ( \u0|mm_interconnect_0|cmd_mux_004|packet_in_progress~q  & ( (\u0|mm_interconnect_0|cmd_mux_004|src_payload [0] & 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & ((\u0|mm_interconnect_0|cmd_mux_004|src_valid~1_combout ) # (\u0|mm_interconnect_0|cmd_mux_004|src_valid~0_combout )))) ) ) ) 
// # ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & ( !\u0|mm_interconnect_0|cmd_mux_004|packet_in_progress~q  & ( ((!\u0|mm_interconnect_0|cmd_mux_004|src_valid~0_combout  & 
// !\u0|mm_interconnect_0|cmd_mux_004|src_valid~1_combout )) # (\u0|mm_interconnect_0|cmd_mux_004|src_payload [0]) ) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & ( 
// !\u0|mm_interconnect_0|cmd_mux_004|packet_in_progress~q  & ( (!\u0|mm_interconnect_0|cmd_mux_004|src_valid~0_combout  & ((!\u0|mm_interconnect_0|cmd_mux_004|src_valid~1_combout ) # ((\u0|mm_interconnect_0|cmd_mux_004|src_payload [0] & 
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )))) # (\u0|mm_interconnect_0|cmd_mux_004|src_valid~0_combout  & (((\u0|mm_interconnect_0|cmd_mux_004|src_payload [0] & 
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )))) ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_004|src_valid~0_combout ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_004|src_valid~1_combout ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_004|src_payload [0]),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_004|packet_in_progress~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_004|update_grant~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|update_grant~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|update_grant~0 .lut_mask = 64'h888F8F8F00070707;
defparam \u0|mm_interconnect_0|cmd_mux_004|update_grant~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y27_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_004|update_grant~0_combout  & ( (!\u0|mm_interconnect_0|cmd_demux_001|src4_valid~1_combout  & (((!\u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg 
// [0] & \u0|mm_interconnect_0|cmd_demux|src4_valid~1_combout )) # (\u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg [1]))) # (\u0|mm_interconnect_0|cmd_demux_001|src4_valid~1_combout  & (!\u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg [0] & 
// (\u0|mm_interconnect_0|cmd_demux|src4_valid~1_combout ))) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_004|update_grant~0_combout  & ( \u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg [1] ) )

        .dataa(!\u0|mm_interconnect_0|cmd_demux_001|src4_valid~1_combout ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg [0]),
        .datac(!\u0|mm_interconnect_0|cmd_demux|src4_valid~1_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_004|update_grant~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg~0 .lut_mask = 64'h00FF00FF0CAE0CAE;
defparam \u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y27_N56
dffeas \u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y27_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg~1_combout  = ( \u0|mm_interconnect_0|cmd_mux_004|update_grant~0_combout  & ( (!\u0|mm_interconnect_0|cmd_demux_001|src4_valid~1_combout  & (((\u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg 
// [0])) # (\u0|mm_interconnect_0|cmd_demux|src4_valid~1_combout ))) # (\u0|mm_interconnect_0|cmd_demux_001|src4_valid~1_combout  & (!\u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg [1] & ((\u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg [0]) # 
// (\u0|mm_interconnect_0|cmd_demux|src4_valid~1_combout )))) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_004|update_grant~0_combout  & ( \u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg [0] ) )

        .dataa(!\u0|mm_interconnect_0|cmd_demux_001|src4_valid~1_combout ),
        .datab(!\u0|mm_interconnect_0|cmd_demux|src4_valid~1_combout ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg [1]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_004|update_grant~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg~1 .lut_mask = 64'h00FF00FF32FA32FA;
defparam \u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y27_N8
dffeas \u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y27_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|arb|grant[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|arb|grant[0]~1_combout  = ( \u0|mm_interconnect_0|cmd_demux_001|src4_valid~1_combout  & ( (!\u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg [0] & \u0|mm_interconnect_0|cmd_demux|src4_valid~1_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|cmd_demux_001|src4_valid~1_combout  & ( (\u0|mm_interconnect_0|cmd_demux|src4_valid~1_combout  & ((!\u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg [0]) # (\u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg [1]))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg [0]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg [1]),
        .datad(!\u0|mm_interconnect_0|cmd_demux|src4_valid~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_demux_001|src4_valid~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_004|arb|grant[0]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|arb|grant[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|arb|grant[0]~1 .lut_mask = 64'h00CF00CF00CC00CC;
defparam \u0|mm_interconnect_0|cmd_mux_004|arb|grant[0]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y27_N26
dffeas \u0|mm_interconnect_0|cmd_mux_004|saved_grant[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_004|arb|grant[0]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|cmd_mux_004|update_grant~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|saved_grant[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_004|saved_grant[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X18_Y27_N32
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] .power_up = "low";
// synopsys translate_on

// Location: FF_X17_Y29_N53
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][68] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][68]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][68] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][68] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y29_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~2_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][68]~q  & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]) # 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][68]~q  & ( 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] & !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][68]~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~2 .lut_mask = 64'h30303F3F30303F3F;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y29_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][68]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][68]~feeder_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~2_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][68]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][68]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][68]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][68]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y29_N44
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][68] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][68]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][68]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][68] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][68] .power_up = "low";
// synopsys translate_on

// Location: FF_X17_Y29_N26
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][69] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][69]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][69] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y29_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~1_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & ( 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][69]~q ) ) ) # ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][69]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][69]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y29_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][69]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][69]~feeder_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~1_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][69]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][69]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][69]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][69]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y29_N59
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][69] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][69]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][69]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][69] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y29_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_004|src0_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout  = ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][66]~q  & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][68]~q  & 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][69]~q ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][68]~q ),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][69]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][66]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_004|src0_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_004|src0_valid~0 .lut_mask = 64'h0F000F0000000000;
defparam \u0|mm_interconnect_0|rsp_demux_004|src0_valid~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y26_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|src_data[116] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|src_data [116] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [11] & ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_AWID [11] & ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & ( 
// (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [11]) ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_AWID [11] & ( !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & ( (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & 
// \u0|hps_0|fpga_interfaces|h2f_ARID [11]) ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_AWID [11] & ( !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & ( (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [11]) ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_AWID [11]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_004|src_data [116]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[116] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[116] .lut_mask = 64'h005500550055FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[116] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y26_N28
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_004|src_data [116]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";
// synopsys translate_on

// Location: FF_X22_Y26_N1
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~21_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][116]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y26_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~21 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~21_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][116]~q  ) ) # ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][116]~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~21_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~21 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~21 .lut_mask = 64'h555555550F0F0F0F;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~21 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y26_N41
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~21_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][116]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y30_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_005|src_payload~11 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_005|src_payload~11_combout  = (\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [11])

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_005|src_payload~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~11 .lut_mask = 64'h0303030303030303;
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~11 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y30_N8
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_005|src_payload~11_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";
// synopsys translate_on

// Location: FF_X11_Y30_N47
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~20_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][116]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y30_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~20 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~20_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][116]~q  ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][116]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~20 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~20 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~20 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y30_N32
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~20_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][116]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y29_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][129]~q  & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg [0] & ( 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [0] & !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [0]) ) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][129]~q  & ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg [0] & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [0] ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [0]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [0]),
        .datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][129]~q ),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid .lut_mask = 64'hFF00CC0000000000;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y30_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~204 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~204_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][116]~q  & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout  & ( 
// (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~57_combout  & \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout ) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][116]~q  & ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout  & ( !\u0|mm_interconnect_0|rsp_mux_001|src_payload~57_combout  ) ) ) # ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][116]~q  & ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout  & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~57_combout  & (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout  & 
// ((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][116]~q ) # (\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][116]~q  & ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout  & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~57_combout  & ((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][116]~q ) # 
// (\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~57_combout ),
        .datab(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][116]~q ),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout ),
        .datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][116]~q ),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~204_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~204 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~204 .lut_mask = 64'hA2A200A2AAAA00AA;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~204 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y30_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~205 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~205_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][116]~q  & ( \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~204_combout  & ( 
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~203_combout  & (\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout  & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][116]~q ) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout )))) ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][116]~q  & ( \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~204_combout  & ( 
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~203_combout  & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][116]~q ) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][116]~q ),
        .datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~203_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout ),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout ),
        .datae(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][116]~q ),
        .dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~204_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~205_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~205 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~205 .lut_mask = 64'h0000000023230023;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~205 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y30_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[116] (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data [116] = ( \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~202_combout  & ( \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~205_combout  ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~202_combout  & ( 
// \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~205_combout  & ( (((!\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~199_combout ) # (!\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~197_combout )) # 
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~200_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~201_combout ) ) ) ) # ( \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~202_combout  & ( 
// !\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~205_combout  ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~202_combout  & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~205_combout  ) )

        .dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~201_combout ),
        .datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~200_combout ),
        .datac(!\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~199_combout ),
        .datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~197_combout ),
        .datae(!\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~202_combout ),
        .dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~205_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data [116]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116] .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116] .lut_mask = 64'hFFFFFFFFFFF7FFFF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116] .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y22_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|src_data[115] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|src_data [115] = (!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & (\u0|hps_0|fpga_interfaces|h2f_AWID [10]))) # (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] 
// & (((\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [10])) # (\u0|hps_0|fpga_interfaces|h2f_ARID [10])))

        .dataa(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [10]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [10]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_009|src_data [115]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[115] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[115] .lut_mask = 64'h0357035703570357;
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[115] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y22_N26
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_009|src_data [115]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .power_up = "low";
// synopsys translate_on

// Location: FF_X15_Y22_N50
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~20_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][115]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][115] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y22_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~20 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~20_combout  = ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][115]~q  ) ) # ( 
// !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][115]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~20 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~20 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~20 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y24_N41
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~20_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][115]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][115] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y24_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_data[115] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_data [115] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [10] & ( ((\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [10])) # (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_ARID [10] & ( (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [10]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [10]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [10]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_010|src_data [115]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[115] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[115] .lut_mask = 64'h0505050537373737;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[115] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y24_N14
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_010|src_data [115]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .power_up = "low";
// synopsys translate_on

// Location: FF_X22_Y24_N53
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~20_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][115]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][115] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y24_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~20 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~20_combout  = (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115])) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & 
// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][115]~q )))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][115]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~20 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~20 .lut_mask = 64'h0C3F0C3F0C3F0C3F;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~20 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y24_N29
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~20_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][115]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][115] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y24_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~190 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~190_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][115]~q  & ( \u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout  & ( 
// (\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][115]~q ) ) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][115]~q  & ( 
// \u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout  & ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][115]~q  ) ) ) # ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][115]~q  & ( 
// !\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout  & ( \u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout  ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][115]~q ),
        .datac(!\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][115]~q ),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~190_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~190 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~190 .lut_mask = 64'h00000F0F33333F3F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~190 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y32_N41
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~19_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][115]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][115] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y32_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_019|src_payload~10 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_019|src_payload~10_combout  = (\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [10])

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
        .datac(gnd),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [10]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_019|src_payload~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~10 .lut_mask = 64'h0033003300330033;
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~10 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y32_N53
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_019|src_payload~10_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y32_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~19 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~19_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115] & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]) # 
// (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][115]~q ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115] & ( (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] 
// & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][115]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][115]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~19 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~19 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~19 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y32_N59
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~19_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][115]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][115] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y25_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_data[115] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|src_data [115] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [10] & ( ((\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [10])) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_ARID [10] & ( (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [10]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_AWID [10]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [10]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_008|src_data [115]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[115] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[115] .lut_mask = 64'h1111111111FF11FF;
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[115] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y25_N43
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_008|src_data [115]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .power_up = "low";
// synopsys translate_on

// Location: FF_X18_Y28_N23
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~20_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][115]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][115] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y28_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~20 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~20_combout  = (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115])) 
// # (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][115]~q )))

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][115]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~20 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~20 .lut_mask = 64'h505F505F505F505F;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~20 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y28_N56
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~20_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][115]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][115] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y32_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~188 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~188_combout  = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][115]~q  & ( (!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout  & 
// ((!\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ) # ((!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout  & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][115]~q )))) # 
// (\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout  & (!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout  & ((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][115]~q )))) ) ) # ( 
// !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][115]~q  & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout  & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][115]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout ),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][115]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][115]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~188_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~188 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~188 .lut_mask = 64'h00CC00CCA0ECA0EC;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~188 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y32_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_021|src_payload~10 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_021|src_payload~10_combout  = (\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [10])

        .dataa(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [10]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_021|src_payload~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~10 .lut_mask = 64'h0505050505050505;
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~10 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y32_N13
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_021|src_payload~10_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .power_up = "low";
// synopsys translate_on

// Location: FF_X27_Y34_N53
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~19_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][115]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][115] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y34_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~19 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~19_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][115]~q  & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] ) ) # ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][115]~q  & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115] ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][115]~q  & ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115] ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][115]~q ),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~19 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~19 .lut_mask = 64'h555555550000FFFF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~19 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y34_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][115]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][115]~feeder_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~19_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~19_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][115]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][115]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][115]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][115]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y34_N44
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][115]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][115]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][115] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y32_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_020|src_payload~10 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_020|src_payload~10_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [10] & ( \u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [10]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_020|src_payload~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~10 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~10 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y32_N23
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_020|src_payload~10_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .power_up = "low";
// synopsys translate_on

// Location: FF_X21_Y32_N2
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~19_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][115]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][115] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y32_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~19 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~19_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][115]~q  ) ) # ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][115]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~19 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~19 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~19 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y32_N50
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~19_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][115]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][115] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y32_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~189 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~189_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout  & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~188_combout  & 
// ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][115]~q ) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ))) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout  & ( 
// (!\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~188_combout  & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][115]~q  & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][115]~q ) # 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~188_combout ),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][115]~q ),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][115]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~189_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~189 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~189 .lut_mask = 64'hA020A020AA22AA22;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~189 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y22_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_data[115] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|src_data [115] = (!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & (\u0|hps_0|fpga_interfaces|h2f_AWID [10]))) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] 
// & (((\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [10])) # (\u0|hps_0|fpga_interfaces|h2f_ARID [10])))

        .dataa(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [10]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [10]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_015|src_data [115]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[115] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[115] .lut_mask = 64'h0357035703570357;
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[115] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y22_N53
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_015|src_data [115]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .power_up = "low";
// synopsys translate_on

// Location: FF_X19_Y22_N44
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~20_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][115]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][115] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y22_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~20 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~20_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][115]~q  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][115]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~20 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~20 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~20 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y26_N56
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~20_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][115]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][115] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y26_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_data[115] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|src_data [115] = ( \u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & ( \u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & ( (\u0|hps_0|fpga_interfaces|h2f_AWID [10]) # (\u0|hps_0|fpga_interfaces|h2f_ARID [10]) ) ) ) # 
// ( !\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & ( \u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_AWID [10] ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & ( 
// !\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [10] ) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARID [10]),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [10]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_018|src_data [115]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[115] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[115] .lut_mask = 64'h000055550F0F5F5F;
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[115] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y26_N40
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_018|src_data [115]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .power_up = "low";
// synopsys translate_on

// Location: FF_X22_Y26_N38
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~20_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][115]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][115] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y26_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~20 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~20_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][115]~q  ) ) # ( 
// !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][115]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~20 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~20 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~20 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y26_N17
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~20_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][115]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][115] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y26_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~192 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~192_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][115]~q  & ( \u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout  & ( (\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout ) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][115]~q ) ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][115]~q  & ( \u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout  & ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][115]~q  ) ) ) # ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][115]~q  & ( !\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout  & ( 
// \u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout  ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][115]~q ),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout ),
        .datae(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][115]~q ),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~192_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~192 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~192 .lut_mask = 64'h000000FF555555FF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~192 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y27_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_002|src_payload~10 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_002|src_payload~10_combout  = (\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [10])

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [10]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_002|src_payload~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~10 .lut_mask = 64'h000F000F000F000F;
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~10 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y27_N35
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_002|src_payload~10_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .power_up = "low";
// synopsys translate_on

// Location: FF_X13_Y27_N2
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~19_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][115]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][115] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y27_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~19 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~19_combout  = (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115])) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & 
// ((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][115]~q )))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][115]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~19 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~19 .lut_mask = 64'h0C3F0C3F0C3F0C3F;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~19 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y27_N47
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~19_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][115]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][115] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y27_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~54 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~54_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][115]~q  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][115]~q  & (((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q  & 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0])) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0]),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][115]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~54_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~54 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~54 .lut_mask = 64'h0037003700FF00FF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~54 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y23_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_001|src_payload~10 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_001|src_payload~10_combout  = (\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [10])

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [10]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_001|src_payload~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~10 .lut_mask = 64'h000F000F000F000F;
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~10 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y23_N14
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_001|src_payload~10_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .power_up = "low";
// synopsys translate_on

// Location: FF_X15_Y23_N5
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~19_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][115]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][115] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y23_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~19 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~19_combout  = (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg 
// [115])) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][115]~q )))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][115]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~19 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~19 .lut_mask = 64'h0C3F0C3F0C3F0C3F;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~19 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y27_N38
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~19_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][115]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][115] .power_up = "low";
// synopsys translate_on

// Location: FF_X19_Y24_N2
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~20_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][115]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][115] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y24_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|src_data[115] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|src_data [115] = ( \u0|mm_interconnect_0|cmd_mux|saved_grant [1] & ( ((\u0|hps_0|fpga_interfaces|h2f_AWID [10] & \u0|mm_interconnect_0|cmd_mux|saved_grant [0])) # (\u0|hps_0|fpga_interfaces|h2f_ARID [10]) ) ) # ( 
// !\u0|mm_interconnect_0|cmd_mux|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_AWID [10] & \u0|mm_interconnect_0|cmd_mux|saved_grant [0]) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARID [10]),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [10]),
        .datad(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux|src_data [115]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|src_data[115] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|src_data[115] .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|cmd_mux|src_data[115] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y24_N16
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux|src_data [115]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y24_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~20 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~20_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115] & ( 
// (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][115]~q ) ) ) # ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115] & ( (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][115]~q ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][115]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~20 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~20 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~20 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y24_N44
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~20_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][115]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][115] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y27_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~193 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~193_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][115]~q  & ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][115]~q  & ( 
// (\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout  & (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~54_combout  & ((\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ) # (\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout )))) ) ) 
// ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][115]~q  & ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][115]~q  & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~54_combout  & 
// ((\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ) # (\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ))) ) ) ) # ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][115]~q  & ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][115]~q  & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout  & !\u0|mm_interconnect_0|rsp_mux_001|src_payload~54_combout ) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][115]~q  & ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][115]~q  & ( !\u0|mm_interconnect_0|rsp_mux_001|src_payload~54_combout  ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ),
        .datab(!\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ),
        .datad(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~54_combout ),
        .datae(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][115]~q ),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][115]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~193_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~193 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~193 .lut_mask = 64'hFF0055003F001500;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~193 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y30_N47
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~19_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][115]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][115] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y30_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_012|src_payload~10 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_012|src_payload~10_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [10] & ( \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [10]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_012|src_payload~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~10 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~10 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y30_N40
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_012|src_payload~10_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y30_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~19 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~19_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115] & ( 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][115]~q ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115] & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][115]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][115]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~19 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~19 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~19 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y30_N16
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~19_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][115]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][115] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y33_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_003|src_payload~10 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_003|src_payload~10_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [10] & ( \u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [10]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_003|src_payload~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~10 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~10 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y33_N41
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_003|src_payload~10_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .power_up = "low";
// synopsys translate_on

// Location: FF_X11_Y33_N59
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~19_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][115]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][115] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y33_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~19 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~19_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][115]~q  ) ) # ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][115]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~19 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~19 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~19 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y30_N2
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~19_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][115]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][115] .power_up = "low";
// synopsys translate_on

// Location: FF_X18_Y26_N14
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~20_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][115]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][115] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y26_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|src_data[115] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|src_data [115] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [10] & ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_AWID [10] & ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & ( 
// (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [10]) ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_AWID [10] & ( !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & ( (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & 
// \u0|hps_0|fpga_interfaces|h2f_ARID [10]) ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_AWID [10] & ( !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & ( (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [10]) ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [10]),
        .datad(gnd),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_AWID [10]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_004|src_data [115]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[115] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[115] .lut_mask = 64'h050505050505FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[115] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y26_N7
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_004|src_data [115]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y26_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~20 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~20_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][115]~q  ) ) # ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][115]~q ),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~20 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~20 .lut_mask = 64'h0F0F0F0F33333333;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~20 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y26_N47
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~20_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][115]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][115] .power_up = "low";
// synopsys translate_on

// Location: FF_X11_Y33_N44
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~19_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][115]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][115] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y33_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_006|src_payload~10 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_006|src_payload~10_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [10] & ( \u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [10]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_006|src_payload~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~10 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~10 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y33_N7
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_006|src_payload~10_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y33_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~19 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~19_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115] & ( 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][115]~q ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115] & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][115]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][115]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~19 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~19 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~19 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y33_N44
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~19_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][115]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][115] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y33_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~55 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~55_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q  & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][115]~q  & 
// (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]))) ) ) # 
// ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q  & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][115]~q  & ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][115]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~55_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~55 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~55 .lut_mask = 64'h00770077007F007F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~55 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y30_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_005|src_payload~10 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_005|src_payload~10_combout  = (\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [10])

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
        .datac(gnd),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [10]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_005|src_payload~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~10 .lut_mask = 64'h0033003300330033;
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~10 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y30_N17
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_005|src_payload~10_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .power_up = "low";
// synopsys translate_on

// Location: FF_X11_Y30_N23
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~19_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][115]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][115] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y30_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~19 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~19_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][115]~q  ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][115]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~19 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~19 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~19 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y30_N56
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~19_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][115]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][115] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y30_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~194 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~194_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][115]~q  & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout  & ( 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout  & !\u0|mm_interconnect_0|rsp_mux_001|src_payload~55_combout ) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][115]~q  & ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout  & ( !\u0|mm_interconnect_0|rsp_mux_001|src_payload~55_combout  ) ) ) # ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][115]~q  & ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout  & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout  & (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~55_combout  & 
// ((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][115]~q ) # (\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][115]~q  & ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout  & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~55_combout  & ((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][115]~q ) # 
// (\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout ),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][115]~q ),
        .datac(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ),
        .datad(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~55_combout ),
        .datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][115]~q ),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~194_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~194 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~194 .lut_mask = 64'hCF004500FF005500;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~194 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y30_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~195 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~195_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][115]~q  & ( \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~194_combout  & ( 
// (\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout  & (\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~193_combout  & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][115]~q ) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout )))) ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][115]~q  & ( \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~194_combout  & ( 
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~193_combout  & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][115]~q ) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout ),
        .datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~193_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][115]~q ),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout ),
        .datae(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][115]~q ),
        .dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~194_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~195_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~195 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~195 .lut_mask = 64'h0000000030331011;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~195 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y33_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_017|src_payload~10 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_017|src_payload~10_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [10] & ( \u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [10]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_017|src_payload~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~10 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~10 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y33_N44
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_017|src_payload~10_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .power_up = "low";
// synopsys translate_on

// Location: FF_X19_Y33_N11
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~19_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][115]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][115] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y33_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~19 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~19_combout  = (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115])) # 
// (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][115]~q )))

        .dataa(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
        .datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][115]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~19 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~19 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~19 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y33_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][115]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][115]~feeder_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~19_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~19_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][115]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][115]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][115]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][115]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y33_N4
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][115]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][115]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][115] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y31_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_016|src_payload~10 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_016|src_payload~10_combout  = ( \u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [10] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [10]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_016|src_payload~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~10 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~10 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y31_N29
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_016|src_payload~10_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .power_up = "low";
// synopsys translate_on

// Location: FF_X17_Y31_N38
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~19_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][115]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][115] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y31_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~19 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~19_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][115]~q  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][115]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~19 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~19 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~19 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y30_N23
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~19_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][115]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][115] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y31_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_013|src_payload~10 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_013|src_payload~10_combout  = ( \u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [10] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [10]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_013|src_payload~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~10 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~10 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y31_N47
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_013|src_payload~10_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .power_up = "low";
// synopsys translate_on

// Location: FF_X17_Y31_N20
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~19_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][115]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][115] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y31_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~19 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~19_combout  = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][115]~q  ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][115]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~19 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~19 .lut_mask = 64'h3333333300FF00FF;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~19 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y31_N14
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~19_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][115]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][115] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y29_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|src_data[115] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|src_data [115] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [10] & ( ((\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [10])) # (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_ARID [10] & ( (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [10]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [10]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [10]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_007|src_data [115]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[115] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[115] .lut_mask = 64'h0303030357575757;
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[115] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y29_N32
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_007|src_data [115]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .power_up = "low";
// synopsys translate_on

// Location: FF_X21_Y29_N5
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~20_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][115]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][115] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y29_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~20 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~20_combout  = (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115])) 
// # (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][115]~q )))

        .dataa(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
        .datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][115]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~20 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~20 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~20 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y29_N50
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~20_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][115]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][115] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y31_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~186 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~186_combout  = ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][115]~q  & ( (!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout  & 
// ((!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ) # ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout  & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][115]~q )))) # 
// (\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout  & (((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout  & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][115]~q )))) ) ) # ( 
// !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][115]~q  & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout  & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][115]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout ),
        .datab(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][115]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][115]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~186_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~186 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~186 .lut_mask = 64'h00F000F088F888F8;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~186 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y30_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~187 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~187_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][115]~q  & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~186_combout  & ( 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout  & ((!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][115]~q ) # (!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ))) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][115]~q  & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~186_combout  & ( (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][115]~q ) # 
// (!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout ),
        .datab(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][115]~q ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][115]~q ),
        .dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~186_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~187_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~187 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~187 .lut_mask = 64'hFCFC545400000000;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~187 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y22_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|src_data[115] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|src_data [115] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [10] & ( ((\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [10])) # (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_AWID [10] & ( (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [10]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [10]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [10]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_011|src_data [115]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[115] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[115] .lut_mask = 64'h0505050537373737;
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[115] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y22_N11
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_011|src_data [115]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .power_up = "low";
// synopsys translate_on

// Location: FF_X19_Y22_N5
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~20_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][115]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][115] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y22_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~20 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~20_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][115]~q  & ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] ) ) # ( 
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][115]~q  & ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg 
// [115] ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][115]~q  & ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & ( 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][115]~q ),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~20 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~20 .lut_mask = 64'h0F0F0F0F0000FFFF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~20 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y22_N38
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~20_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][115]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][115] .power_up = "low";
// synopsys translate_on

// Location: FF_X21_Y22_N25
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~20_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][115]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][115] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y22_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_data[115] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_data [115] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [10] & ( ((\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [10])) # (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_AWID [10] & ( (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [10]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [10]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [10]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_014|src_data [115]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[115] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[115] .lut_mask = 64'h003300330F3F0F3F;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[115] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y22_N13
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_014|src_data [115]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y22_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~20 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~20_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][115]~q  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][115]~q ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~20 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~20 .lut_mask = 64'h0F0F0F0F33333333;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~20 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y22_N13
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][115] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~20_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][115]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][115] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y22_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~191 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~191_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][115]~q  & ( ((\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout  & 
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][115]~q )) # (\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][115]~q  & ( 
// (\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout  & \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][115]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout ),
        .datac(!\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout ),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][115]~q ),
        .datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][115]~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~191_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~191 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~191 .lut_mask = 64'h00330F3F00330F3F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~191 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y30_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[115] (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data [115] = ( \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~187_combout  & ( \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~191_combout  ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~187_combout  & ( 
// \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~191_combout  ) ) # ( \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~187_combout  & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~191_combout  & ( 
// ((!\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~189_combout ) # ((!\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~195_combout ) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~192_combout ))) # 
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~190_combout ) ) ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~187_combout  & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~191_combout  ) )

        .dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~190_combout ),
        .datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~189_combout ),
        .datac(!\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~192_combout ),
        .datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~195_combout ),
        .datae(!\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~187_combout ),
        .dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~191_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data [115]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115] .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115] .lut_mask = 64'hFFFFFFDFFFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115] .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y24_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|src_data[114] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|src_data [114] = ( \u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & ( ((\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [9])) # (\u0|hps_0|fpga_interfaces|h2f_ARID [9]) ) ) # ( 
// !\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & ( (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [9]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [9]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [9]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_009|src_data [114]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[114] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[114] .lut_mask = 64'h0505050505FF05FF;
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[114] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y24_N17
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_009|src_data [114]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .power_up = "low";
// synopsys translate_on

// Location: FF_X17_Y24_N29
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~19_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][114]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][114] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y24_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~19 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~19_combout  = ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][114]~q  & ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] ) ) # ( 
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][114]~q  & ( !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg 
// [114] ) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][114]~q  & ( !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ( 
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][114]~q ),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~19 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~19 .lut_mask = 64'h0F0F0F0F0000FFFF;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~19 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y24_N5
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~19_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][114]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][114] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y24_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_data[114] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_data [114] = ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_AWID [9] & ( (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]) # (\u0|hps_0|fpga_interfaces|h2f_ARID [9]) ) ) ) # ( 
// !\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_AWID [9] & ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & ( !\u0|hps_0|fpga_interfaces|h2f_AWID [9] & ( 
// \u0|hps_0|fpga_interfaces|h2f_ARID [9] ) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARID [9]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
        .datae(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [9]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_010|src_data [114]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[114] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[114] .lut_mask = 64'h0000555500FF55FF;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[114] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y24_N10
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_010|src_data [114]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .power_up = "low";
// synopsys translate_on

// Location: FF_X19_Y24_N23
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~19_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][114]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][114] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y24_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~19 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~19_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][114]~q  ) ) # ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114] ) )

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][114]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~19 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~19 .lut_mask = 64'h5555555500FF00FF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~19 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y24_N17
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~19_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][114]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][114] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y24_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~180 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~180_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][114]~q  & ( ((\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout  & 
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][114]~q )) # (\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][114]~q  & ( 
// (\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout  & \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][114]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout ),
        .datab(!\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][114]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][114]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~180_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~180 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~180 .lut_mask = 64'h0055005533773377;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~180 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y29_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|src_data[114] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|src_data [114] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [9] & ( ((\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [9])) # (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_ARID [9] & ( (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [9]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
        .datac(gnd),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_AWID [9]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [9]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_007|src_data [114]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[114] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[114] .lut_mask = 64'h0033003355775577;
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[114] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y29_N43
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_007|src_data [114]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .power_up = "low";
// synopsys translate_on

// Location: FF_X18_Y29_N41
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~19_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][114]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][114] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y29_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~19 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~19_combout  = (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114])) 
// # (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][114]~q )))

        .dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][114]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~19 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~19 .lut_mask = 64'h505F505F505F505F;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~19 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y29_N26
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~19_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][114]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][114] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y31_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_013|src_payload~9 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_013|src_payload~9_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [9] & ( \u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [9]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_013|src_payload~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~9 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~9 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y31_N44
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_013|src_payload~9_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .power_up = "low";
// synopsys translate_on

// Location: FF_X17_Y31_N5
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~18_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][114]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][114] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y31_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~18 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~18_combout  = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][114]~q  ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][114]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~18 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~18 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y31_N41
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~18_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][114]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][114] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y31_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~176 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~176_combout  = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][114]~q  & ( \u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout  & ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout  ) ) ) # ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][114]~q  & ( !\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout ) # ((!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout  & \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][114]~q )) ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][114]~q  & ( !\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout  & ( (!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout  & 
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][114]~q ) ) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout ),
        .datab(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][114]~q ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][114]~q ),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~176_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~176 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~176 .lut_mask = 64'h2222F2F20000F0F0;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~176 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y31_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_016|src_payload~9 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_016|src_payload~9_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [9] & ( \u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [9]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_016|src_payload~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~9 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~9 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y31_N26
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_016|src_payload~9_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .power_up = "low";
// synopsys translate_on

// Location: FF_X17_Y31_N2
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~18_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][114]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][114] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y31_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~18 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~18_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][114]~q  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][114]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~18 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~18 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y30_N5
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~18_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][114]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][114] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y33_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_017|src_payload~9 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_017|src_payload~9_combout  = (\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [9])

        .dataa(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [9]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_017|src_payload~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~9 .lut_mask = 64'h0505050505050505;
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~9 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y33_N41
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_017|src_payload~9_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .power_up = "low";
// synopsys translate_on

// Location: FF_X19_Y33_N17
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~18_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][114]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][114] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y33_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~18 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~18_combout  = (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114])) # 
// (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][114]~q )))

        .dataa(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
        .datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][114]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~18 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~18 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y33_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][114]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][114]~feeder_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~18_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~18_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][114]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][114]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][114]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][114]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y33_N49
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][114]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][114]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][114] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y30_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~177 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~177_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][114]~q  & ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][114]~q  & ( 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout  & (!\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~176_combout  & !\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout )) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][114]~q  & ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][114]~q  & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~176_combout  & 
// !\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][114]~q  & ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][114]~q  & ( 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout  & !\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~176_combout ) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][114]~q  & ( 
// !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][114]~q  & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~176_combout  ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout ),
        .datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~176_combout ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][114]~q ),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][114]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~177_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~177 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~177 .lut_mask = 64'hCCCC4444C0C04040;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~177 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y33_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_006|src_payload~9 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_006|src_payload~9_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [9] & ( \u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [9]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_006|src_payload~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~9 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~9 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y33_N53
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_006|src_payload~9_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .power_up = "low";
// synopsys translate_on

// Location: FF_X11_Y33_N17
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~18_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][114]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][114] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y33_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~18 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~18_combout  = (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114])) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & 
// ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][114]~q )))

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][114]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~18 .lut_mask = 64'h4477447744774477;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~18 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y33_N14
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~18_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][114]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][114] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y33_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~53 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~53_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q  & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][114]~q  & 
// (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0])) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]))) ) ) # 
// ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q  & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][114]~q  & ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][114]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~53_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~53 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~53 .lut_mask = 64'h005F005F007F007F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~53 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y30_N53
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~18_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][114]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][114] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y30_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_005|src_payload~9 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_005|src_payload~9_combout  = (\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [9])

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
        .datac(gnd),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [9]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_005|src_payload~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~9 .lut_mask = 64'h0033003300330033;
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~9 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y30_N4
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_005|src_payload~9_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y30_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~18 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~18_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][114]~q  & ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114] ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][114]~q  & ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114] & ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] ) ) ) # ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][114]~q  & ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114] & ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][114]~q ),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~18 .lut_mask = 64'h00005555AAAAFFFF;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~18 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y30_N38
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~18_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][114]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][114] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y26_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|src_data[114] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|src_data [114] = ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & ( (\u0|hps_0|fpga_interfaces|h2f_ARID [9]) # (\u0|hps_0|fpga_interfaces|h2f_AWID [9]) ) ) ) # ( 
// !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_AWID [9] ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & ( 
// !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [9] ) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_AWID [9]),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARID [9]),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_004|src_data [114]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[114] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[114] .lut_mask = 64'h0000333355557777;
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[114] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y26_N40
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_004|src_data [114]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .power_up = "low";
// synopsys translate_on

// Location: FF_X18_Y26_N2
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~19_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][114]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][114] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y26_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~19 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~19_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][114]~q  ) ) # ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][114]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~19 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~19 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~19 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y26_N37
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~19_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][114]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][114] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y30_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~184 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~184_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][114]~q  & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][114]~q  & ( 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout  & (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~53_combout  & ((\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ) # 
// (\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][114]~q  & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][114]~q  & ( 
// (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~53_combout  & ((\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ) # (\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ))) ) ) ) # ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][114]~q  & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][114]~q  & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout  & 
// !\u0|mm_interconnect_0|rsp_mux_001|src_payload~53_combout ) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][114]~q  & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][114]~q  & ( 
// !\u0|mm_interconnect_0|rsp_mux_001|src_payload~53_combout  ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout ),
        .datab(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~53_combout ),
        .datac(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ),
        .datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][114]~q ),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][114]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~184_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~184 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~184 .lut_mask = 64'hCCCC44440CCC0444;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~184 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y30_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_012|src_payload~9 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_012|src_payload~9_combout  = ( \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [9] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [9]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_012|src_payload~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~9 .lut_mask = 64'h000000000000FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~9 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y30_N7
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_012|src_payload~9_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .power_up = "low";
// synopsys translate_on

// Location: FF_X15_Y30_N50
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~18_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][114]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][114] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y30_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~18 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~18_combout  = (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114])) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & 
// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][114]~q )))

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][114]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~18 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~18 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y30_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][114]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][114]~feeder_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~18_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~18_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][114]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][114]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][114]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][114]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y30_N25
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][114]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][114]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][114] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y33_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_003|src_payload~9 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_003|src_payload~9_combout  = ( \u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [9] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [9]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_003|src_payload~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~9 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~9 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y33_N26
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_003|src_payload~9_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .power_up = "low";
// synopsys translate_on

// Location: FF_X11_Y33_N32
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~18_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][114]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][114] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y33_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~18 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~18_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][114]~q  ) ) # ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][114]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~18 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~18 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y30_N56
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~18_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][114]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][114] .power_up = "low";
// synopsys translate_on

// Location: FF_X13_Y27_N59
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~18_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][114]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][114] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y27_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_002|src_payload~9 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_002|src_payload~9_combout  = ( \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [9] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [9]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_002|src_payload~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~9 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~9 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y27_N19
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_002|src_payload~9_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y27_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~18 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~18_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114] & ( 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][114]~q ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114] & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][114]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][114]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~18 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~18 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y27_N13
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~18_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][114]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][114] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y27_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~52 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~52_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][114]~q  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0] & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][114]~q  & (((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q  & 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0])) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][114]~q ),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~52_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~52 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~52 .lut_mask = 64'h1113111333333333;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~52 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y24_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_001|src_payload~9 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_001|src_payload~9_combout  = (\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [9])

        .dataa(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [9]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_001|src_payload~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~9 .lut_mask = 64'h0055005500550055;
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~9 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y24_N17
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_001|src_payload~9_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .power_up = "low";
// synopsys translate_on

// Location: FF_X15_Y24_N47
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~18_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][114]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][114] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y24_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~18 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~18_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][114]~q  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][114]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~18 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~18 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y26_N32
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~18_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][114]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][114] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y24_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|src_data[114] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|src_data [114] = ( \u0|mm_interconnect_0|cmd_mux|saved_grant [1] & ( ((\u0|hps_0|fpga_interfaces|h2f_AWID [9] & \u0|mm_interconnect_0|cmd_mux|saved_grant [0])) # (\u0|hps_0|fpga_interfaces|h2f_ARID [9]) ) ) # ( 
// !\u0|mm_interconnect_0|cmd_mux|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_AWID [9] & \u0|mm_interconnect_0|cmd_mux|saved_grant [0]) ) )

        .dataa(gnd),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_AWID [9]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [9]),
        .datad(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux|src_data [114]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|src_data[114] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|src_data[114] .lut_mask = 64'h003300330F3F0F3F;
defparam \u0|mm_interconnect_0|cmd_mux|src_data[114] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y24_N14
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux|src_data [114]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .power_up = "low";
// synopsys translate_on

// Location: FF_X19_Y26_N11
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~19_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][114]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][114] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y26_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~19 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~19_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][114]~q  & ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] ) ) # ( 
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][114]~q  & ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg 
// [114] ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][114]~q  & ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & ( 
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][114]~q ),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~19 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~19 .lut_mask = 64'h0F0F0F0F0000FFFF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~19 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y26_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][114]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][114]~feeder_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~19_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~19_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][114]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][114]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][114]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][114]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y26_N29
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][114]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][114]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][114] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y26_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~183 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~183_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][114]~q  & ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][114]~q  & ( 
// (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~52_combout  & (\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout  & ((\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ) # (\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout )))) ) ) 
// ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][114]~q  & ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][114]~q  & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~52_combout  & 
// ((\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ) # (\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ))) ) ) ) # ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][114]~q  & ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][114]~q  & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~52_combout  & \u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][114]~q  & ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][114]~q  & ( !\u0|mm_interconnect_0|rsp_mux_001|src_payload~52_combout  ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ),
        .datab(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~52_combout ),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ),
        .datae(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][114]~q ),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][114]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~183_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~183 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~183 .lut_mask = 64'hCCCC00CC4C4C004C;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~183 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y30_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~185 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~185_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][114]~q  & ( \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~183_combout  & ( 
// (\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout  & (\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~184_combout  & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][114]~q ) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout )))) ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][114]~q  & ( \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~183_combout  & ( 
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~184_combout  & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][114]~q ) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout ),
        .datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~184_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][114]~q ),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout ),
        .datae(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][114]~q ),
        .dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~183_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~185_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~185 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~185 .lut_mask = 64'h0000000030331011;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~185 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y32_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_020|src_payload~9 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_020|src_payload~9_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [9] & ( \u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [9]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_020|src_payload~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~9 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~9 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y32_N20
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_020|src_payload~9_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .power_up = "low";
// synopsys translate_on

// Location: FF_X21_Y32_N38
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~18_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][114]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][114] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y32_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~18 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~18_combout  = (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114])) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & 
// ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][114]~q )))

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][114]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~18 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~18 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y32_N7
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~18_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][114]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][114] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y32_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_021|src_payload~9 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_021|src_payload~9_combout  = (\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [9])

        .dataa(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [9]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_021|src_payload~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~9 .lut_mask = 64'h0055005500550055;
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~9 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y32_N11
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_021|src_payload~9_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .power_up = "low";
// synopsys translate_on

// Location: FF_X25_Y32_N23
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~18_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][114]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][114] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y32_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~18 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~18_combout  = (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114])) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & 
// ((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][114]~q )))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][114]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~18 .lut_mask = 64'h0C3F0C3F0C3F0C3F;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~18 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y32_N35
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~18_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][114]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][114] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y32_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_019|src_payload~9 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_019|src_payload~9_combout  = (\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [9])

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [9]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_019|src_payload~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~9 .lut_mask = 64'h0303030303030303;
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~9 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y32_N50
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_019|src_payload~9_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .power_up = "low";
// synopsys translate_on

// Location: FF_X25_Y32_N2
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~18_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][114]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][114] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y32_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~18 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~18_combout  = (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114])) # 
// (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][114]~q )))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][114]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~18 .lut_mask = 64'h0C3F0C3F0C3F0C3F;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~18 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y32_N14
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~18_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][114]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][114] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y24_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_data[114] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|src_data [114] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [9] & ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_AWID [9] & ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & ( 
// (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [9]) ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_AWID [9] & ( !\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & ( (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & 
// \u0|hps_0|fpga_interfaces|h2f_ARID [9]) ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_AWID [9] & ( !\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & ( (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [9]) ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [9]),
        .datad(gnd),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_AWID [9]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_008|src_data [114]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[114] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[114] .lut_mask = 64'h050505050505FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[114] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y24_N7
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_008|src_data [114]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .power_up = "low";
// synopsys translate_on

// Location: FF_X18_Y28_N19
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~19_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][114]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][114] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y28_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~19 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~19_combout  = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][114]~q  & ( (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg 
// [114]) # (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][114]~q  & ( (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][114]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~19 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~19 .lut_mask = 64'h0C0C0C0C3F3F3F3F;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~19 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y28_N49
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~19_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][114]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][114] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y32_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~178 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~178_combout  = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][114]~q  & ( (!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout  & 
// ((!\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ) # ((!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout  & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][114]~q )))) # 
// (\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout  & (!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout  & ((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][114]~q )))) ) ) # ( 
// !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][114]~q  & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout  & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][114]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout ),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][114]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][114]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~178_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~178 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~178 .lut_mask = 64'h00CC00CCA0ECA0EC;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~178 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y32_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~179 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~179_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][114]~q  & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~178_combout  & ( 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout  & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][114]~q ) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ))) ) ) ) # ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][114]~q  & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~178_combout  & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][114]~q ) # 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][114]~q ),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][114]~q ),
        .dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~178_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~179_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~179 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~179 .lut_mask = 64'hBBBB0B0B00000000;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~179 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y24_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_data[114] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_data [114] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [9] & ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARID [9] & ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & ( 
// (\u0|hps_0|fpga_interfaces|h2f_AWID [9] & \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]) ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_ARID [9] & ( !\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_AWID [9] & 
// \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]) ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARID [9] & ( !\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_AWID [9] & \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]) ) 
// ) )

        .dataa(gnd),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_AWID [9]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
        .datad(gnd),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_ARID [9]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_014|src_data [114]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[114] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[114] .lut_mask = 64'h030303030303FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[114] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y24_N52
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_014|src_data [114]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .power_up = "low";
// synopsys translate_on

// Location: FF_X21_Y22_N29
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~19_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][114]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][114] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y22_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~19 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~19_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][114]~q  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][114]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~19 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~19 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~19 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y22_N32
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~19_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][114]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][114] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y23_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|src_data[114] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|src_data [114] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [9] & ( \u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARID [9] & ( \u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & ( 
// (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [9]) ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_ARID [9] & ( !\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & ( (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] & 
// \u0|hps_0|fpga_interfaces|h2f_AWID [9]) ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARID [9] & ( !\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & ( (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [9]) ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [9]),
        .datad(gnd),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_ARID [9]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_011|src_data [114]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[114] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[114] .lut_mask = 64'h030303030303FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[114] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y23_N52
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_011|src_data [114]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .power_up = "low";
// synopsys translate_on

// Location: FF_X21_Y22_N23
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~19_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][114]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][114] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y22_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~19 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~19_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][114]~q  ) ) # ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][114]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~19 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~19 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~19 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y22_N50
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~19_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][114]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][114] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y22_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~181 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~181_combout  = ( \u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout  & ( ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][114]~q  & \u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout 
// )) # (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][114]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout  & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][114]~q  & 
// \u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][114]~q ),
        .datac(!\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout ),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][114]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~181_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~181 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~181 .lut_mask = 64'h0303030303FF03FF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~181 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y24_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_data[114] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|src_data [114] = ( \u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & ( ((\u0|hps_0|fpga_interfaces|h2f_AWID [9] & \u0|mm_interconnect_0|cmd_mux_018|saved_grant [0])) # (\u0|hps_0|fpga_interfaces|h2f_ARID [9]) ) ) # ( 
// !\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_AWID [9] & \u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]) ) )

        .dataa(gnd),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_AWID [9]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [9]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_018|src_data [114]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[114] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[114] .lut_mask = 64'h003300330F3F0F3F;
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[114] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y24_N50
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_018|src_data [114]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .power_up = "low";
// synopsys translate_on

// Location: FF_X27_Y24_N20
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~19_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][114]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][114] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y24_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~19 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~19_combout  = (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114])) # 
// (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][114]~q )))

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][114]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~19 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~19 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~19 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y26_N26
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~19_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][114]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][114] .power_up = "low";
// synopsys translate_on

// Location: FF_X18_Y23_N47
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~19_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][114]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][114] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y23_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_data[114] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|src_data [114] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [9] & ( \u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARID [9] & ( \u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & ( 
// (\u0|hps_0|fpga_interfaces|h2f_AWID [9] & \u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]) ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_ARID [9] & ( !\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_AWID [9] & 
// \u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]) ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARID [9] & ( !\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_AWID [9] & \u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]) ) 
// ) )

        .dataa(gnd),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_AWID [9]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
        .datad(gnd),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_ARID [9]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_015|src_data [114]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[114] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[114] .lut_mask = 64'h030303030303FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[114] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y23_N19
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_015|src_data [114]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y23_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~19 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~19_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][114]~q  & ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114] ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][114]~q  & ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114] & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] ) ) ) # ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][114]~q  & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114] & ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][114]~q ),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~19 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~19 .lut_mask = 64'h00000F0FF0F0FFFF;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~19 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y26_N20
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][114] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~19_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][114]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][114] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y26_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~182 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~182_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][114]~q  & ( \u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][114]~q  & ( \u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout  & ( (\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout  & 
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][114]~q ) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][114]~q  & ( !\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout  & ( 
// (\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout  & \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][114]~q ) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][114]~q  & ( 
// !\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout  & ( (\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout  & \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][114]~q ) ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][114]~q ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][114]~q ),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~182_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~182 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~182 .lut_mask = 64'h050505050505FFFF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~182 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y28_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[114] (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data [114] = ( \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~181_combout  & ( \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~182_combout  ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~181_combout  & ( 
// \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~182_combout  ) ) # ( \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~181_combout  & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~182_combout  ) ) # ( 
// !\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~181_combout  & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~182_combout  & ( ((!\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~177_combout ) # 
// ((!\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~185_combout ) # (!\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~179_combout ))) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~180_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~180_combout ),
        .datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~177_combout ),
        .datac(!\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~185_combout ),
        .datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~179_combout ),
        .datae(!\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~181_combout ),
        .dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~182_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data [114]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114] .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114] .lut_mask = 64'hFFFDFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114] .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y26_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARLEN [2] & ( \u0|hps_0|fpga_interfaces|h2f_ARLEN [1] & ( (\u0|hps_0|fpga_interfaces|h2f_ARLEN [0] & \u0|hps_0|fpga_interfaces|h2f_ARLEN [3]) ) ) )

        .dataa(gnd),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [3]),
        .datad(gnd),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [2]),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0 .lut_mask = 64'h0000000000000303;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y32_N50
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y32_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout  = ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout  & \u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]) ) ) ) # ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout  & \u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]) ) ) ) # ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg 
// [5]) ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] 
// & \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .lut_mask = 64'h00AAFF5503030303;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y32_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  & 
// ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout  ) ) # ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  & ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout  ) ) # ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  & ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout  & ( 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout  & 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout  & 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout  & 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),
        .datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .lut_mask = 64'h0080FFFF0000FFFF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y32_N2
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y33_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~1_combout ))) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .lut_mask = 64'hCCCCCCCCCCC0CCC0;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y33_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout  
// & ( ((\u0|mm_interconnect_0|cmd_mux_021|last_cycle~0_combout  & (\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] & \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ))) # 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ) # ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout  & ( (\u0|mm_interconnect_0|cmd_mux_021|last_cycle~0_combout  & (\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] & 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q )) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_021|last_cycle~0_combout ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .lut_mask = 64'h0003000355575557;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y33_N26
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y33_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~0_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & ( 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]) # 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~0 .lut_mask = 64'h000000000CCC0CCC;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y33_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter~0_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override~q  & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~0_combout  & 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout  & !\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter [0])) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout ),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter~0 .lut_mask = 64'h0000000050005000;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y33_N23
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y33_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override~q  & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter [0] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0 .lut_mask = 64'h0000000000FF00FF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y33_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & ( 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0_combout ) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout ))) ) ) # ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout ),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0_combout ),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hFFFFFFFF70707070;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y33_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h0000000044444444;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y33_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout  & ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout  & ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout  ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout  & 
// ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout  & ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout  ) ) ) # ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout  & ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout  & ( 
// ((\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout  & 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout  & 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ))) # 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ) ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout  
// & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout  & ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout  ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),
        .datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout ),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h5555755555555555;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y33_N8
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y33_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & ( 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  $ 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))) # 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q 
//  & !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) ) ) # ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .lut_mask = 64'hA000A0005AA05AA0;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y33_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  
// & !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) ) ) # ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  & 
// ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  ) ) ) # ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  & 
// ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .lut_mask = 64'h0505555500005050;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y33_N53
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y33_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & ( 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) # 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & (((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q )))) 
// ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & ( 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .lut_mask = 64'h50505050D850D850;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y33_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & ( 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & 
// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) # (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~1_combout ))) ) ) ) # ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & ( 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & 
// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) # 
// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) # (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~1_combout )))) ) ) ) # ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & ( 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~1_combout  & 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout )) ) ) ) # ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & ( 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  
// & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) # (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~1_combout )))) ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~1_combout ),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .lut_mask = 64'h54005000FE00FA00;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y33_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_021|packet_in_progress~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_021|packet_in_progress~0_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  & ( ((\u0|mm_interconnect_0|cmd_mux_021|last_cycle~0_combout  
// & \u0|mm_interconnect_0|cmd_mux_021|saved_grant [1])) # (\u0|mm_interconnect_0|cmd_mux_021|packet_in_progress~q ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  & ( 
// (\u0|mm_interconnect_0|cmd_mux_021|packet_in_progress~q  & ((!\u0|mm_interconnect_0|cmd_mux_021|last_cycle~0_combout ) # (!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]))) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_021|last_cycle~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_021|packet_in_progress~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_021|packet_in_progress~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_021|packet_in_progress~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_021|packet_in_progress~0 .lut_mask = 64'h00FA00FA05FF05FF;
defparam \u0|mm_interconnect_0|cmd_mux_021|packet_in_progress~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y33_N20
dffeas \u0|mm_interconnect_0|cmd_mux_021|packet_in_progress (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_021|packet_in_progress~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_021|packet_in_progress~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_021|packet_in_progress .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_021|packet_in_progress .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y33_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_021|update_grant~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_021|update_grant~0_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  & ( (!\u0|mm_interconnect_0|cmd_mux_021|packet_in_progress~q  & 
// ((!\u0|mm_interconnect_0|cmd_mux_021|last_cycle~0_combout ) # (!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]))) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  & ( 
// (!\u0|mm_interconnect_0|cmd_mux_021|packet_in_progress~q ) # ((\u0|mm_interconnect_0|cmd_mux_021|last_cycle~0_combout  & \u0|mm_interconnect_0|cmd_mux_021|saved_grant [1])) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_021|packet_in_progress~q ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_021|last_cycle~0_combout ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_021|update_grant~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_021|update_grant~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_021|update_grant~0 .lut_mask = 64'hABABABABA8A8A8A8;
defparam \u0|mm_interconnect_0|cmd_mux_021|update_grant~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y33_N56
dffeas \u0|mm_interconnect_0|cmd_mux_021|saved_grant[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_021|last_cycle~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|cmd_mux_021|update_grant~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_021|saved_grant[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_021|saved_grant[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X27_Y33_N53
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y33_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout  = ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q  & 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]))) ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] 
// & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] 
// & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2])) ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0 .lut_mask = 64'h8800000080000000;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y33_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|write~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|write~0_combout  = (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~0_combout  & ((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0_combout ) # 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout )))

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout ),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0_combout ),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|write~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|write~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h0707070707070707;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|write~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y33_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[1]~0_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout  & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|write~0_combout  & 
// ((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]))) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|write~0_combout  & (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0])) ) ) # ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout  & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|write~0_combout  & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout  & 
// ((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1])))) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|write~0_combout  & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout  & 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0])) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout  & ((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]))))) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|write~0_combout ),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout ),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0]),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[1]~0 .lut_mask = 64'h049D049D05AF05AF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[1]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y33_N11
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X27_Y32_N11
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~17_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][113]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][113] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y32_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_021|src_payload~8 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_021|src_payload~8_combout  = (\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [8])

        .dataa(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [8]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_021|src_payload~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~8 .lut_mask = 64'h0505050505050505;
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y32_N16
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_021|src_payload~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y32_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~17 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~17_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113] & ( 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][113]~q ) ) ) # ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113] & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][113]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][113]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~17 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~17 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y32_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][113]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][113]~feeder_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~17_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~17_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][113]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][113]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][113]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][113]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y32_N22
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][113]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][113]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][113] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y24_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_data[113] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|src_data [113] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [8] & ( ((\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [8])) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_AWID [8] & ( (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [8]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [8]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [8]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_008|src_data [113]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[113] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[113] .lut_mask = 64'h0505050537373737;
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[113] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y24_N35
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_008|src_data [113]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .power_up = "low";
// synopsys translate_on

// Location: FF_X15_Y24_N56
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~18_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][113]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][113] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y24_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~18 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~18_combout  = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][113]~q  ) ) # ( 
// !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][113]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~18 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~18 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y28_N59
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~18_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][113]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][113] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y32_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_019|src_payload~8 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_019|src_payload~8_combout  = ( \u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [8] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [8]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_019|src_payload~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~8 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y32_N8
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_019|src_payload~8_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .power_up = "low";
// synopsys translate_on

// Location: FF_X22_Y32_N2
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~17_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][113]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][113] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y32_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~17 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~17_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][113]~q  ) ) # ( 
// !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][113]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~17 .lut_mask = 64'h3333333300FF00FF;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~17 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y32_N44
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~17_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][113]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][113] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y32_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~168 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~168_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout  & ( (!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout  & (!\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout  & 
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][113]~q )) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout  & ( ((!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout  & 
// (!\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout  & \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][113]~q ))) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][113]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][113]~q ),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][113]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~168_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~168 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~168 .lut_mask = 64'h08FF08FF08080808;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~168 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y32_N59
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~17_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][113]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][113] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y32_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_020|src_payload~8 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_020|src_payload~8_combout  = (\u0|hps_0|fpga_interfaces|h2f_ARID [8] & \u0|mm_interconnect_0|cmd_mux_020|saved_grant [1])

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [8]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_020|src_payload~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~8 .lut_mask = 64'h000F000F000F000F;
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y32_N10
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_020|src_payload~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y32_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~17 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~17_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113] & ( 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][113]~q ) ) ) # ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113] & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][113]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][113]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~17 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~17 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y32_N11
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~17_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][113]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][113] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y32_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~169 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~169_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout  & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~168_combout  & 
// ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][113]~q ) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ))) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout  & ( 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][113]~q  & (!\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~168_combout  & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][113]~q ) # 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][113]~q ),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ),
        .datac(!\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~168_combout ),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][113]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~169_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~169 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~169 .lut_mask = 64'hA020A020F030F030;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~169 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y30_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_012|src_payload~8 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_012|src_payload~8_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [8] & ( \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [8]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_012|src_payload~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~8 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y30_N34
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_012|src_payload~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .power_up = "low";
// synopsys translate_on

// Location: FF_X15_Y30_N35
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~17_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][113]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][113] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y30_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~17 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~17_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][113]~q  ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][113]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~17 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~17 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y30_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][113]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][113]~feeder_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~17_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~17_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][113]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][113]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][113]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][113]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y30_N40
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][113]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][113]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][113] .power_up = "low";
// synopsys translate_on

// Location: FF_X19_Y24_N44
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~18_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][113]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][113] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y26_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|src_data[113] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|src_data [113] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [8] & ( ((\u0|mm_interconnect_0|cmd_mux|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [8])) # (\u0|mm_interconnect_0|cmd_mux|saved_grant [1]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_ARID [8] & ( (\u0|mm_interconnect_0|cmd_mux|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [8]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [8]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [8]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux|src_data [113]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|src_data[113] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|src_data[113] .lut_mask = 64'h0505050537373737;
defparam \u0|mm_interconnect_0|cmd_mux|src_data[113] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y26_N53
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux|src_data [113]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y24_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~18 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~18_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113] & ( 
// (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][113]~q ) ) ) # ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113] & ( (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][113]~q ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][113]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~18 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~18 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y26_N26
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~18_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][113]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][113] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y24_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_001|src_payload~8 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_001|src_payload~8_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [8] & ( \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [8]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_001|src_payload~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~8 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y24_N14
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_001|src_payload~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .power_up = "low";
// synopsys translate_on

// Location: FF_X15_Y24_N59
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~17_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][113]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][113] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y24_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~17 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~17_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][113]~q  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][113]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~17 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~17 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y26_N41
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~17_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][113]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][113] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y27_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_002|src_payload~8 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_002|src_payload~8_combout  = (\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [8])

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [8]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_002|src_payload~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~8 .lut_mask = 64'h0303030303030303;
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y27_N20
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_002|src_payload~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .power_up = "low";
// synopsys translate_on

// Location: FF_X10_Y27_N2
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~17_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][113]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][113] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y27_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~17 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~17_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][113]~q  & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] ) ) # ( 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][113]~q  & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & ( 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113] ) ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][113]~q  & ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][113]~q ),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~17 .lut_mask = 64'h0F0F0F0F0000FFFF;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~17 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y27_N41
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~17_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][113]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][113] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y27_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~50 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~50_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][113]~q  & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0] ) ) # ( 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][113]~q  & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0] & ( ((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q  & 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0])) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0]),
        .datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][113]~q ),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~50_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~50 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~50 .lut_mask = 64'h00000F5F0000FFFF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~50 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y26_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~173 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~173_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][113]~q  & ( !\u0|mm_interconnect_0|rsp_mux_001|src_payload~50_combout  & ( 
// (\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout  & ((!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][113]~q ) # ((\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ) # 
// (\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][113]~q  & ( !\u0|mm_interconnect_0|rsp_mux_001|src_payload~50_combout  & ( 
// (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][113]~q ) # ((\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ) # (\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][113]~q ),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ),
        .datac(!\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ),
        .datae(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][113]~q ),
        .dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~50_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~173_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~173 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~173 .lut_mask = 64'hAFFF233300000000;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~173 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y33_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_003|src_payload~8 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_003|src_payload~8_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [8] & ( \u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [8]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_003|src_payload~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~8 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y33_N47
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_003|src_payload~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .power_up = "low";
// synopsys translate_on

// Location: FF_X17_Y33_N50
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~17_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][113]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][113] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y33_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~17 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~17_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][113]~q  ) ) # ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][113]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~17 .lut_mask = 64'h3333333300FF00FF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~17 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y30_N44
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~17_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][113]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][113] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y33_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_006|src_payload~8 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_006|src_payload~8_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [8] & ( \u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [8]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_006|src_payload~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~8 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y33_N35
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_006|src_payload~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .power_up = "low";
// synopsys translate_on

// Location: FF_X14_Y33_N38
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~17_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][113]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][113] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y33_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~17 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~17_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][113]~q  ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][113]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~17 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~17 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y33_N29
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~17_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][113]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][113] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y33_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~51 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~51_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q  & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][113]~q  & 
// (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]))) ) ) # 
// ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q  & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][113]~q  & ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][113]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~51_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~51 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~51 .lut_mask = 64'h00770077007F007F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~51 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y26_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|src_data[113] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|src_data [113] = ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & ( ((\u0|hps_0|fpga_interfaces|h2f_AWID [8] & \u0|mm_interconnect_0|cmd_mux_004|saved_grant [0])) # (\u0|hps_0|fpga_interfaces|h2f_ARID [8]) ) ) # ( 
// !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_AWID [8] & \u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_AWID [8]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [8]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_004|src_data [113]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[113] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[113] .lut_mask = 64'h111111111F1F1F1F;
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[113] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y26_N37
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_004|src_data [113]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .power_up = "low";
// synopsys translate_on

// Location: FF_X18_Y26_N5
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~18_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][113]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][113] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y26_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~18 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~18_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][113]~q  ) ) # ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][113]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~18 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~18 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y26_N8
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~18_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][113]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][113] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y30_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_005|src_payload~8 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_005|src_payload~8_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [8] & ( \u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [8]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_005|src_payload~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~8 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y30_N14
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_005|src_payload~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .power_up = "low";
// synopsys translate_on

// Location: FF_X11_Y30_N44
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~17_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][113]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][113] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y30_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~17 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~17_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][113]~q  ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][113]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~17 .lut_mask = 64'h3333333300FF00FF;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~17 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y30_N8
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~17_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][113]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][113] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y30_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~174 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~174_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][113]~q  & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout  & ( 
// (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~51_combout  & (((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][113]~q ) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout )) # 
// (\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][113]~q  & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout  & ( 
// (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~51_combout  & (((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][113]~q ) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout )) # 
// (\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][113]~q  & ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout  & ( 
// (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~51_combout  & (((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][113]~q ) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout )) # 
// (\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ),
        .datab(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~51_combout ),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][113]~q ),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ),
        .datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][113]~q ),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~174_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~174 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~174 .lut_mask = 64'hC4CC0000C4CCC4CC;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~174 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y30_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~175 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~175_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][113]~q  & ( \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~174_combout  & ( 
// (\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout  & (\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~173_combout  & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][113]~q ) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout )))) ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][113]~q  & ( \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~174_combout  & ( 
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~173_combout  & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][113]~q ) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout ),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout ),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][113]~q ),
        .datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~173_combout ),
        .datae(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][113]~q ),
        .dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~174_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~175_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~175 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~175 .lut_mask = 64'h0000000000F30051;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~175 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y24_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|src_data[113] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|src_data [113] = ( \u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & ( ((\u0|hps_0|fpga_interfaces|h2f_AWID [8] & \u0|mm_interconnect_0|cmd_mux_009|saved_grant [0])) # (\u0|hps_0|fpga_interfaces|h2f_ARID [8]) ) ) # ( 
// !\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_AWID [8] & \u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_AWID [8]),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARID [8]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_009|src_data [113]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[113] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[113] .lut_mask = 64'h0055005533773377;
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[113] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y24_N53
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_009|src_data [113]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .power_up = "low";
// synopsys translate_on

// Location: FF_X17_Y24_N44
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~18_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][113]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][113] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y24_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~18 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~18_combout  = ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][113]~q  & ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] ) ) # ( 
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][113]~q  & ( !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg 
// [113] ) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][113]~q  & ( !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ( 
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][113]~q ),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~18 .lut_mask = 64'h0F0F0F0F0000FFFF;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~18 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y24_N56
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~18_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][113]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][113] .power_up = "low";
// synopsys translate_on

// Location: FF_X22_Y24_N50
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~18_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][113]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][113] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y24_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_data[113] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_data [113] = ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_AWID [8] & ( (\u0|hps_0|fpga_interfaces|h2f_ARID [8]) # (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]) ) ) ) # ( 
// !\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_AWID [8] & ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & ( !\u0|hps_0|fpga_interfaces|h2f_AWID [8] & ( 
// \u0|hps_0|fpga_interfaces|h2f_ARID [8] ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [8]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [8]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_010|src_data [113]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[113] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[113] .lut_mask = 64'h00000F0F55555F5F;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[113] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y24_N37
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_010|src_data [113]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y24_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~18 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~18_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113] & ( 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][113]~q ) ) ) # ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113] & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][113]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][113]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~18 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~18 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y24_N8
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~18_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][113]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][113] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y24_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~170 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~170_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][113]~q  & ( ((\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout  & 
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][113]~q )) # (\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][113]~q  & ( 
// (\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout  & \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][113]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ),
        .datac(!\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout ),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][113]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][113]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~170_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~170 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~170 .lut_mask = 64'h000F000F333F333F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~170 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y22_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_data[113] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|src_data [113] = (!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & (\u0|hps_0|fpga_interfaces|h2f_AWID [8]))) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & 
// (((\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [8])) # (\u0|hps_0|fpga_interfaces|h2f_ARID [8])))

        .dataa(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [8]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [8]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_015|src_data [113]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[113] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[113] .lut_mask = 64'h0357035703570357;
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[113] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y22_N50
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_015|src_data [113]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .power_up = "low";
// synopsys translate_on

// Location: FF_X19_Y22_N56
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~18_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][113]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][113] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y22_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~18 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~18_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][113]~q  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][113]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~18 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~18 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y26_N50
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~18_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][113]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][113] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y26_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~172 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~172_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][113]~q  & ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][113]~q  & ( 
// (\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout ) # (\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout ) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][113]~q  & ( 
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][113]~q  & ( \u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout  ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][113]~q  & ( 
// !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][113]~q  & ( \u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout  ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout ),
        .datac(!\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][113]~q ),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][113]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~172_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~172 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~172 .lut_mask = 64'h000033330F0F3F3F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~172 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y29_N41
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~18_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][113]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][113] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y29_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|src_data[113] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|src_data [113] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [8] & ( ((\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [8])) # (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_ARID [8] & ( (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [8]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_AWID [8]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [8]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_007|src_data [113]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[113] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[113] .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[113] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y29_N22
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_007|src_data [113]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y29_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~18 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~18_combout  = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113] & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used 
// [1]) # (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][113]~q ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113] & ( 
// (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][113]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][113]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~18 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~18 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y31_N2
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~18_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][113]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][113] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y33_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_013|src_payload~8 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_013|src_payload~8_combout  = (\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [8])

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [8]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_013|src_payload~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~8 .lut_mask = 64'h0303030303030303;
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y33_N32
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_013|src_payload~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .power_up = "low";
// synopsys translate_on

// Location: FF_X18_Y33_N47
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~17_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][113]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][113] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y33_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~17 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~17_combout  = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][113]~q  ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][113]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~17 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~17 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y31_N38
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~17_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][113]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][113] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y31_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~166 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~166_combout  = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][113]~q  & ( \u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout  & ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout  ) ) ) # ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][113]~q  & ( !\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout ) # ((!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout  & \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][113]~q )) ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][113]~q  & ( !\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout  & ( (!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout  & 
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][113]~q ) ) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout ),
        .datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][113]~q ),
        .datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][113]~q ),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~166_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~166 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~166 .lut_mask = 64'h00AAF0FA0000F0F0;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~166 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y31_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_016|src_payload~8 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_016|src_payload~8_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [8] & ( \u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [8]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_016|src_payload~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~8 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y31_N8
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_016|src_payload~8_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .power_up = "low";
// synopsys translate_on

// Location: FF_X19_Y31_N56
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~17_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][113]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][113] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y31_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~17 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~17_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][113]~q  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][113]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~17 .lut_mask = 64'h3333333300FF00FF;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~17 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y31_N29
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~17_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][113]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][113] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y33_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_017|src_payload~8 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_017|src_payload~8_combout  = (\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [8])

        .dataa(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [8]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_017|src_payload~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~8 .lut_mask = 64'h0505050505050505;
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y33_N55
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_017|src_payload~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .power_up = "low";
// synopsys translate_on

// Location: FF_X19_Y33_N14
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~17_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][113]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][113] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y33_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~17 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~17_combout  = (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113])) # 
// (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][113]~q )))

        .dataa(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
        .datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][113]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~17 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~17 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y33_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][113]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][113]~feeder_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~17_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~17_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][113]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][113]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][113]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][113]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y33_N55
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][113]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][113]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][113] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y31_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~167 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~167_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][113]~q  & ( (!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout  & 
// (!\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~166_combout  & ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][113]~q ) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout )))) ) ) # ( 
// !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][113]~q  & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~166_combout  & ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][113]~q ) # 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout ),
        .datab(!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ),
        .datac(!\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~166_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][113]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][113]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~167_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~167 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~167 .lut_mask = 64'hF050F050C040C040;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~167 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y22_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_data[113] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_data [113] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [8] & ( ((\u0|hps_0|fpga_interfaces|h2f_AWID [8] & \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0])) # (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_ARID [8] & ( (\u0|hps_0|fpga_interfaces|h2f_AWID [8] & \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [8]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [8]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_014|src_data [113]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[113] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[113] .lut_mask = 64'h000F000F333F333F;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[113] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y22_N8
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_014|src_data [113]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .power_up = "low";
// synopsys translate_on

// Location: FF_X21_Y22_N20
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~18_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][113]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][113] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y22_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~18 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~18_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][113]~q  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][113]~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~18 .lut_mask = 64'h333333330F0F0F0F;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~18 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y22_N2
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~18_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][113]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][113] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y22_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|src_data[113] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|src_data [113] = (!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] & (\u0|hps_0|fpga_interfaces|h2f_AWID [8]))) # (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & 
// (((\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [8])) # (\u0|hps_0|fpga_interfaces|h2f_ARID [8])))

        .dataa(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [8]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [8]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_011|src_data [113]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[113] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[113] .lut_mask = 64'h0357035703570357;
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[113] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y22_N8
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_011|src_data [113]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .power_up = "low";
// synopsys translate_on

// Location: FF_X19_Y22_N59
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~18_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][113]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][113] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y22_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~18 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~18_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][113]~q  ) ) # ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][113]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~18 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~18 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y22_N8
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~18_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][113]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][113] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y22_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~171 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~171_combout  = ( \u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout  & ( ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][113]~q  & \u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout 
// )) # (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][113]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout  & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][113]~q  & 
// \u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][113]~q ),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][113]~q ),
        .datac(!\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~171_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~171 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~171 .lut_mask = 64'h0505050537373737;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~171 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y28_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[113] (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data [113] = ( \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~167_combout  & ( \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~171_combout  ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~167_combout  & ( 
// \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~171_combout  ) ) # ( \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~167_combout  & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~171_combout  & ( 
// (!\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~169_combout ) # ((!\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~175_combout ) # ((\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~172_combout ) # 
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~170_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~167_combout  & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~171_combout  ) )

        .dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~169_combout ),
        .datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~175_combout ),
        .datac(!\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~170_combout ),
        .datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~172_combout ),
        .datae(!\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~167_combout ),
        .dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~171_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data [113]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113] .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113] .lut_mask = 64'hFFFFEFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113] .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y21_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_data[35] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|src_data [35] = ( \u0|hps_0|fpga_interfaces|h2f_WSTRB [3] & ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_WSTRB [3] & ( 
// \u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_015|src_data [35]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[35] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[35] .lut_mask = 64'h00FF00FF55FF55FF;
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[35] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y21_N41
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_015|src_data [35]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y21_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_data[34] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|src_data [34] = ( \u0|hps_0|fpga_interfaces|h2f_WSTRB [2] & ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_WSTRB [2] & ( 
// \u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_015|src_data [34]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[34] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[34] .lut_mask = 64'h3333333377777777;
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[34] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y21_N32
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_015|src_data [34]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y21_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~2_combout  = ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]) ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~2 .lut_mask = 64'hF000000000000000;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y21_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~3_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~0_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q  & ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write~0_combout  $ 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [0])) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~2_combout ))) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q  & ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write~0_combout  $ 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [0])))) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~0_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q  & \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~2_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~2_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~3 .lut_mask = 64'h222222222FF22FF2;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y21_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  = ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q  & ( 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  
// & (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~3_combout  & !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]))) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q  & ( 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q 
// ) # ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~3_combout ) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1])))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~3_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .lut_mask = 64'h5455545504000400;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y21_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout  = ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  
// & !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q )) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  
// & ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) # 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q )))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h2220222022002200;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y21_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  = ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout  
// & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout  
// & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  ) ) ) # ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout  
// & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  & (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & ((!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout )))) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout 
//  & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  & ((!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
        .datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .lut_mask = 64'hA2A200A2AAAAAAAA;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y21_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARLEN [0] & ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~4_combout ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0] & ( ((\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~4_combout )) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~4_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 .lut_mask = 64'h7373737350505050;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y21_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout  = ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] $ 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 .lut_mask = 64'h55AA55AA0F0F0F0F;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y21_N47
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y21_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout  & ( 
// ((\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3_combout )) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]) ) ) # ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout  & ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5 .lut_mask = 64'h005500550F5F0F5F;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y21_N59
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y21_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout  = ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] $ 
// (((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6 .lut_mask = 64'h44BB44BB0F0F0F0F;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y21_N32
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y21_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg 
// [4] & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3])) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] & ( 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # 
// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .lut_mask = 64'hBFBFBFBF40404040;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y21_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout  & ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout  & \u0|mm_interconnect_0|cmd_mux_015|saved_grant [1])) # 
// (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout  & ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout  & \u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]) ) ) ) # ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout  & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout  & ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
        .datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout ),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .lut_mask = 64'hF0F0F0F000335577;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y21_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~1_combout  & ( 
// ((\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout )) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]) ) ) # ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~1_combout  & ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 .lut_mask = 64'h0303030303FF03FF;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y21_N53
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y21_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  = ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg 
// [3] & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] & 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .lut_mask = 64'h0C000C0000000000;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y21_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout  = ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout )) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout )) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 .lut_mask = 64'h03CF03CFCF03CF03;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y21_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout  = (!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & 
// ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout )))) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & (((\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout )) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~0_combout )))

        .dataa(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~0_combout ),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .lut_mask = 64'h0537053705370537;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y21_N20
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y21_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout  = ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] $ 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6])))) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout )) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]))) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 .lut_mask = 64'h11DD11DDD11DD11D;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y21_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout  = ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout  & ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout  & ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout  & ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout  & ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  ) ) ) # ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout  & ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout  & ( 
// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout  & 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout  & 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ))) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout  & ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout  & ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ),
        .datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .lut_mask = 64'h5555D55555555555;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y21_N8
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y21_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~1_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q )) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q 
// ))) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~1_combout  & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ))) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  
// & (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q )) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .lut_mask = 64'h33553355330F330F;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y21_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q 
//  & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & 
// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h1010101010501050;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y21_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  
// & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h0000000030303030;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y21_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout  = ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout  & ( 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ) ) ) 
// # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout  & ( 
// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout  & ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ) 
// # (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout )))) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h5F1F5F1F5F5F5F5F;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y21_N17
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y21_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  
// & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  $ 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ))) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .lut_mask = 64'hC000C0003CC03CC0;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y21_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  & ( 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout )) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  & ( 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .lut_mask = 64'h050F050F05000500;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y21_N38
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y21_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout 
//  & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .lut_mask = 64'hFFFFFFFF0F000F00;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y21_N20
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y21_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [0] & ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [0] & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [0] & ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # 
// (((\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~0_combout  & !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68])) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|WideOr0~0_combout )) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [0] & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & ( 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # (((\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~0_combout  & 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68])) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|WideOr0~0_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|WideOr0~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
        .datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [0]),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hCFDFDFCFCCCCCCCC;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y21_N23
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y21_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout  = ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  $ 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] $ 
// (((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .lut_mask = 64'h30CF30CF3ACA3ACA;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y21_N56
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";
// synopsys translate_on

// Location: FF_X18_Y19_N35
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][77] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~8_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][77]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y19_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~8 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~8_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][77]~q  & ( 
// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][77]~q  & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][77]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~8 .lut_mask = 64'h0202020257575757;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y19_N5
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][77] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~8_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][77]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";
// synopsys translate_on

// Location: FF_X17_Y21_N35
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][78] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~9_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][78]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y21_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~9 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~9_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6])) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][78]~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][78]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][78]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~9 .lut_mask = 64'h005500550A5F0A5F;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~9 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y19_N41
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][78] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~9_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][78]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";
// synopsys translate_on

// Location: FF_X17_Y21_N17
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][75] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][75]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y21_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~6 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~6_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][75]~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][75]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][75]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h005500550A5F0A5F;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y19_N38
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][75] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~6_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][75]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";
// synopsys translate_on

// Location: FF_X17_Y19_N59
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_busy (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";
// synopsys translate_on

// Location: FF_X17_Y21_N20
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][76] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~7_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][76]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y21_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~7 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~7_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][76]~q  & ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][76]~q  & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]) ) ) ) # ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][76]~q  & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][76]~q ),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h000055550A0A5F5F;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y19_N32
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][76] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~7_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][76]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";
// synopsys translate_on

// Location: FF_X17_Y21_N14
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][74] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][74]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y21_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~5 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~5_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) # 
// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])))) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & 
// (((\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][74]~q )))) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & 
// (((\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][74]~q )))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][74]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h025702578ADF8ADF;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y19_N35
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][74] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~5_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][74]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y19_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~0_combout  = ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][76]~q  & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][74]~q  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][77]~q  & (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][78]~q  & (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][75]~q  & 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_busy~q ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][77]~q ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][78]~q ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][76]~q ),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h0000000080000000;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y19_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout  & 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout  & 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout  & 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][74]~q  $ (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][75]~q ))) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout  & (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][74]~q  $ (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][75]~q ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h2121212133000033;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y19_N50
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y19_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~0_combout  = !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [4] $ 
// (((!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h6C6C6C6C6C6C6C6C;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y19_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout  = ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~0_combout  & ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout  ) ) ) # ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~0_combout  & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout  & (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][76]~q  $ (((\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][75]~q ) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][74]~q ))))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~0_combout  & ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout  & 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][76]~q  $ (((\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][75]~q ) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][74]~q ))))) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~0_combout ),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h2013201333330000;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y19_N8
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y19_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~2_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [5] ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [5] $ (((!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h5FA05FA0FF00FF00;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y19_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add1~1_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][76]~q  & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][77]~q  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][76]~q  & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][77]~q  $ (((!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][74]~q  & 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][75]~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][77]~q ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h5AF05AF0F0F0F0F0;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add1~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y19_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add1~1_combout  & ( 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout  & (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~2_combout  & 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout )) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add1~1_combout  & ( 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~2_combout ) # 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~2_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add1~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h3330333000300030;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y19_N47
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y19_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add1~0_combout  = ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][76]~q  & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][74]~q  & 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][77]~q  & !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][75]~q )) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][77]~q ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add1~0 .lut_mask = 64'hA000A00000000000;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add1~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y19_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~1_combout  = ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [2])) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~1 .lut_mask = 64'hA000A00000000000;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y19_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~1_combout  & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout  & (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add1~0_combout  $ (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][78]~q )))) ) 
// ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~1_combout  & ( 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add1~0_combout  $ (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][78]~q )) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~1_combout  & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout  & 
// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add1~0_combout  $ (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][78]~q )) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~1_combout  & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout  & (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add1~0_combout  $ (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][78]~q )))) ) 
// ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add1~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][78]~q ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout ),
        .datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h0060006F006F0060;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y19_N20
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y19_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~1_combout  = ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [5])) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'hA000A00000000000;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y19_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout  & ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~1_combout  & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (((\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add1~0_combout  & !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][78]~q )))) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [6])) ) ) ) # ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout  & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~1_combout  & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add1~0_combout 
//  & (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][78]~q )) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add1~0_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][78]~q ),
        .datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout ),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h0000300000003A0A;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y19_N55
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y19_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_busy~q  ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_busy~q  & ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~1_combout ) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [7]))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h0B0B0B0B0F0F0F0F;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y19_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout  & !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~2_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][74]~q  & 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout  & !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~2_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h0A000A000F000F00;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y19_N17
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y19_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~2_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_busy~q  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h0000000000FF00FF;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y19_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][66]~q  & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|comb~0_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~0_combout  & ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~2_combout ) # 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~1_combout ))) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][66]~q  & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|comb~0_combout  ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][66]~q ),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|comb~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h0000FFFF0000A8A8;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y19_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used[1]~0_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [0] & ( 
// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|always0~0_combout ) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|write~0_combout )) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout ) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [0] & ( 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|write~0_combout  & ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|always0~0_combout ) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout 
// ))) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [0] & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|write~0_combout  $ 
// (((!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout  & \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|always0~0_combout ))) ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|write~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|always0~0_combout ),
        .datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used[1]~0 .lut_mask = 64'h0000F03C0F03FF3F;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used[1]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y19_N53
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X19_Y22_N32
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~17_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][112]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][112] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y22_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_data[112] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|src_data [112] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [7] & ( ((\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [7])) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_AWID [7] & ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [7]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
        .datac(gnd),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [7]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [7]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_015|src_data [112]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[112] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[112] .lut_mask = 64'h0055005533773377;
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[112] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y22_N28
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_015|src_data [112]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y22_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~17 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~17_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112] & ( 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][112]~q ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112] & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][112]~q ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][112]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~17 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~17 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y26_N50
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~17_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][112]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][112] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y26_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_data[112] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|src_data [112] = ( \u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & ( ((\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [7])) # (\u0|hps_0|fpga_interfaces|h2f_AWID [7]) ) ) # ( 
// !\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & ( (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [7]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [7]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [7]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_018|src_data [112]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[112] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[112] .lut_mask = 64'h003300330F3F0F3F;
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[112] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y26_N26
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_018|src_data [112]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .power_up = "low";
// synopsys translate_on

// Location: FF_X30_Y26_N20
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~17_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][112]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][112] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y26_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~17 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~17_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][112]~q  ) ) # ( 
// !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][112]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~17 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~17 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y26_N56
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~17_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][112]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][112] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y26_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~162 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~162_combout  = ( \u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout  & ( ((\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout  & \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][112]~q )) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][112]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout  & ( (\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout  & 
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][112]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][112]~q ),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][112]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~162_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~162 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~162 .lut_mask = 64'h003300330F3F0F3F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~162 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y32_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_019|src_payload~7 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_019|src_payload~7_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [7] & ( \u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [7]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_019|src_payload~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~7 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~7 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y32_N41
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_019|src_payload~7_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .power_up = "low";
// synopsys translate_on

// Location: FF_X25_Y32_N5
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~16_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][112]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][112] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y32_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~16 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~16_combout  = (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112])) # 
// (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][112]~q )))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][112]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~16 .lut_mask = 64'h0C3F0C3F0C3F0C3F;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~16 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y32_N56
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~16_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][112]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][112] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y24_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_data[112] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|src_data [112] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [7] & ( ((\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [7])) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_ARID [7] & ( (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [7]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [7]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [7]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_008|src_data [112]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[112] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[112] .lut_mask = 64'h0303030357575757;
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[112] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y24_N32
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_008|src_data [112]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .power_up = "low";
// synopsys translate_on

// Location: FF_X15_Y24_N44
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~17_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][112]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][112] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y24_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~17 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~17_combout  = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][112]~q  ) ) # ( 
// !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][112]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~17 .lut_mask = 64'h3333333300FF00FF;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~17 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y28_N10
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~17_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][112]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][112] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y32_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~158 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~158_combout  = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][112]~q  & ( (!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout  & 
// ((!\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ) # ((!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout  & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][112]~q )))) # 
// (\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout  & (!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout  & ((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][112]~q )))) ) ) # ( 
// !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][112]~q  & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout  & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][112]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout ),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][112]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][112]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~158_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~158 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~158 .lut_mask = 64'h00CC00CCA0ECA0EC;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~158 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y32_N56
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~16_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][112]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][112] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y32_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_021|src_payload~7 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_021|src_payload~7_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [7] & ( \u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [7]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_021|src_payload~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~7 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~7 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y32_N32
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_021|src_payload~7_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y32_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~16 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~16_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112] & ( 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][112]~q ) ) ) # ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112] & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][112]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][112]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~16 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~16 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y32_N31
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~16_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][112]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][112] .power_up = "low";
// synopsys translate_on

// Location: FF_X21_Y32_N56
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~16_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][112]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][112] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y32_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_020|src_payload~7 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_020|src_payload~7_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [7] & ( \u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [7]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_020|src_payload~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~7 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~7 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y32_N22
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_020|src_payload~7_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y32_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~16 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~16_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112] & ( 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][112]~q ) ) ) # ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112] & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][112]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][112]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~16 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~16 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y32_N17
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~16_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][112]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][112] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y32_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~159 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~159_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][112]~q  & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~158_combout  & 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout  & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][112]~q ) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout )))) ) ) # ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][112]~q  & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~158_combout  & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][112]~q ) # 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ),
        .datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~158_combout ),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][112]~q ),
        .datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][112]~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~159_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~159 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~159 .lut_mask = 64'hCC440C04CC440C04;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~159 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y33_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_017|src_payload~7 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_017|src_payload~7_combout  = (\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [7])

        .dataa(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [7]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_017|src_payload~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~7 .lut_mask = 64'h0055005500550055;
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~7 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y33_N38
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_017|src_payload~7_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .power_up = "low";
// synopsys translate_on

// Location: FF_X19_Y33_N8
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~16_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][112]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][112] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y33_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~16 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~16_combout  = (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112])) # 
// (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][112]~q )))

        .dataa(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
        .datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][112]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~16 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~16 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y33_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][112]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][112]~feeder_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~16_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~16_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][112]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][112]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][112]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][112]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y33_N1
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][112]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][112]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][112] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y31_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_016|src_payload~7 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_016|src_payload~7_combout  = ( \u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [7] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [7]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_016|src_payload~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~7 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~7 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y31_N13
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_016|src_payload~7_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .power_up = "low";
// synopsys translate_on

// Location: FF_X19_Y31_N38
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~16_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][112]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][112] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y31_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~16 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~16_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][112]~q  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][112]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~16 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~16 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y31_N26
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~16_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][112]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][112] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y29_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|src_data[112] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|src_data [112] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [7] & ( ((\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [7])) # (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_ARID [7] & ( (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [7]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [7]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [7]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_007|src_data [112]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[112] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[112] .lut_mask = 64'h0303030357575757;
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[112] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y29_N20
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_007|src_data [112]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .power_up = "low";
// synopsys translate_on

// Location: FF_X21_Y29_N38
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~17_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][112]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][112] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y29_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~17 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~17_combout  = (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112])) 
// # (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][112]~q )))

        .dataa(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
        .datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][112]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~17 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~17 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y31_N59
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~17_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][112]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][112] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y33_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_013|src_payload~7 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_013|src_payload~7_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [7] & ( \u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [7]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_013|src_payload~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~7 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~7 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y33_N53
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_013|src_payload~7_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .power_up = "low";
// synopsys translate_on

// Location: FF_X18_Y33_N26
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~16_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][112]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][112] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y33_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~16 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~16_combout  = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][112]~q  ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][112]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~16 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~16 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y31_N53
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~16_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][112]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][112] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y31_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~156 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~156_combout  = ( \u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout  & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout  & 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][112]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout  & ( (!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout  & 
// (((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout  & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][112]~q )) # (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][112]~q ))) # 
// (\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout  & (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout  & ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][112]~q )))) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout ),
        .datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout ),
        .datac(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][112]~q ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][112]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~156_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~156 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~156 .lut_mask = 64'h0ACE0ACE00CC00CC;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~156 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y31_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~157 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~157_combout  = ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~156_combout  & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout  & 
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][112]~q  & ((!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ) # (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][112]~q )))) # 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout  & ((!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ) # ((!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][112]~q )))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout ),
        .datab(!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][112]~q ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][112]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~156_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~157_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~157 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~157 .lut_mask = 64'hFC54FC5400000000;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~157 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y33_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_006|src_payload~7 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_006|src_payload~7_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [7] & ( \u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [7]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_006|src_payload~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~7 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~7 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y33_N50
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_006|src_payload~7_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .power_up = "low";
// synopsys translate_on

// Location: FF_X11_Y33_N14
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~16_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][112]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][112] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y33_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~16 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~16_combout  = (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112])) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & 
// ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][112]~q )))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][112]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~16 .lut_mask = 64'h0C3F0C3F0C3F0C3F;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~16 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y33_N26
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~16_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][112]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][112] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y33_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~49 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~49_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q  & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][112]~q  & 
// (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]))) ) ) # 
// ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q  & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][112]~q  & ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][112]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~49_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~49 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~49 .lut_mask = 64'h00770077007F007F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~49 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y30_N26
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~16_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][112]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][112] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y30_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_005|src_payload~7 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_005|src_payload~7_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [7] & ( \u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_ARID [7]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_005|src_payload~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~7 .lut_mask = 64'h000000000000FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~7 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y30_N31
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_005|src_payload~7_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y30_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~16 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~16_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][112]~q  & ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112] ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][112]~q  & ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112] & ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] ) ) ) # ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][112]~q  & ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112] & ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][112]~q ),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~16 .lut_mask = 64'h00000F0FF0F0FFFF;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~16 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y30_N2
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~16_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][112]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][112] .power_up = "low";
// synopsys translate_on

// Location: FF_X22_Y26_N56
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~17_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][112]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][112] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y26_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|src_data[112] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|src_data [112] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [7] & ( ((\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [7])) # (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_ARID [7] & ( (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [7]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [7]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [7]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_004|src_data [112]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[112] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[112] .lut_mask = 64'h0303030357575757;
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[112] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y26_N52
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_004|src_data [112]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y26_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~17 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~17_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112] & ( 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][112]~q ) ) ) # ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112] & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][112]~q ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][112]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~17 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~17 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y26_N26
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~17_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][112]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][112] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y30_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~164 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~164_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][112]~q  & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][112]~q  & ( 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout  & (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~49_combout  & ((\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ) # 
// (\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][112]~q  & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][112]~q  & ( 
// (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~49_combout  & ((\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ) # (\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ))) ) ) ) # ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][112]~q  & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][112]~q  & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout  & 
// !\u0|mm_interconnect_0|rsp_mux_001|src_payload~49_combout ) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][112]~q  & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][112]~q  & ( 
// !\u0|mm_interconnect_0|rsp_mux_001|src_payload~49_combout  ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout ),
        .datad(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~49_combout ),
        .datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][112]~q ),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][112]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~164_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~164 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~164 .lut_mask = 64'hFF000F0077000700;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~164 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y30_N29
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~16_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][112]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][112] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y30_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_012|src_payload~7 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_012|src_payload~7_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [7] & ( \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [7]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_012|src_payload~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~7 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~7 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y30_N31
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_012|src_payload~7_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y30_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~16 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~16_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][112]~q  & ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112] ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][112]~q  & ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112] & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] ) ) ) # ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][112]~q  & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112] & ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][112]~q ),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~16 .lut_mask = 64'h00005555AAAAFFFF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~16 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y30_N55
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~16_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][112]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][112] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y24_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_001|src_payload~7 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_001|src_payload~7_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [7] & ( \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [7]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_001|src_payload~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~7 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~7 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y24_N53
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_001|src_payload~7_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .power_up = "low";
// synopsys translate_on

// Location: FF_X15_Y24_N29
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~16_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][112]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][112] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y24_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~16 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~16_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][112]~q  & ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] ) ) # ( 
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][112]~q  & ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg 
// [112] ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][112]~q  & ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ( 
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
        .datae(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][112]~q ),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~16 .lut_mask = 64'h00FF00FF0000FFFF;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~16 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y26_N56
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~16_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][112]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][112] .power_up = "low";
// synopsys translate_on

// Location: FF_X10_Y27_N26
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~16_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][112]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][112] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y27_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_002|src_payload~7 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_002|src_payload~7_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [7] & ( \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [7]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_002|src_payload~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~7 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~7 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y27_N16
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_002|src_payload~7_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y27_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~16 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~16_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112] & ( 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][112]~q ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112] & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][112]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][112]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~16 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~16 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y27_N17
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~16_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][112]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][112] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y27_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~48 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~48_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][112]~q  & 
// (((\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][112]~q  & ((\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][112]~q ),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]),
        .datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0]),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~48_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~48 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~48 .lut_mask = 64'h0333133303331333;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~48 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y26_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~163 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~163_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][112]~q  & ( !\u0|mm_interconnect_0|rsp_mux_001|src_payload~48_combout  & ( 
// (\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout  & ((!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][112]~q ) # ((\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ) # 
// (\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout )))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][112]~q  & ( !\u0|mm_interconnect_0|rsp_mux_001|src_payload~48_combout  & ( 
// (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][112]~q ) # ((\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ) # (\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][112]~q ),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ),
        .datad(!\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ),
        .datae(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][112]~q ),
        .dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~48_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~163_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~163 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~163 .lut_mask = 64'hAFFF233300000000;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~163 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y33_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_003|src_payload~7 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_003|src_payload~7_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [7] & ( \u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [7]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_003|src_payload~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~7 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~7 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y33_N38
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_003|src_payload~7_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .power_up = "low";
// synopsys translate_on

// Location: FF_X11_Y33_N56
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~16_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][112]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][112] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y33_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~16 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~16_combout  = (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg 
// [112])) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][112]~q )))

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][112]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~16 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~16 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y30_N8
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~16_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][112]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][112] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y30_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~165 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~165_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][112]~q  & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout  & ( 
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~164_combout  & (\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout  & \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~163_combout )) ) ) ) # ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][112]~q  & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout  & ( (\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~164_combout  & 
// \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~163_combout ) ) ) ) # ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][112]~q  & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout  & ( 
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~164_combout  & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][112]~q  & (\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout  & 
// \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~163_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][112]~q  & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout  & ( 
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~164_combout  & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][112]~q  & \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~163_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~164_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][112]~q ),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout ),
        .datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~163_combout ),
        .datae(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][112]~q ),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~165_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~165 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~165 .lut_mask = 64'h0044000400550005;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~165 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y24_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|src_data[112] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|src_data [112] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [7] & ( \u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARID [7] & ( \u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & ( 
// (\u0|hps_0|fpga_interfaces|h2f_AWID [7] & \u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]) ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_ARID [7] & ( !\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_AWID [7] & 
// \u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]) ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARID [7] & ( !\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_AWID [7] & \u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]) ) 
// ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_AWID [7]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_ARID [7]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_009|src_data [112]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[112] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[112] .lut_mask = 64'h005500550055FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[112] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y24_N59
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_009|src_data [112]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .power_up = "low";
// synopsys translate_on

// Location: FF_X17_Y24_N35
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~17_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][112]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][112] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y24_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~17 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~17_combout  = ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][112]~q  & ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] ) ) # ( 
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][112]~q  & ( !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg 
// [112] ) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][112]~q  & ( !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ( 
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][112]~q ),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~17 .lut_mask = 64'h0F0F0F0F0000FFFF;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~17 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y24_N47
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~17_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][112]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][112] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y24_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_data[112] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_data [112] = (!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & ((\u0|hps_0|fpga_interfaces|h2f_ARID [7])))) # (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] 
// & (((\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [7])) # (\u0|hps_0|fpga_interfaces|h2f_AWID [7])))

        .dataa(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [7]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [7]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_010|src_data [112]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[112] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[112] .lut_mask = 64'h0537053705370537;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[112] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y24_N32
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_010|src_data [112]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .power_up = "low";
// synopsys translate_on

// Location: FF_X22_Y24_N47
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~17_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][112]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][112] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y24_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~17 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~17_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][112]~q  ) ) # ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][112]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~17 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~17 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y24_N41
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~17_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][112]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][112] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y24_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~160 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~160_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][112]~q  & ( ((\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout  & 
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][112]~q )) # (\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][112]~q  & ( 
// (\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout  & \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][112]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][112]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][112]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~160_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~160 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~160 .lut_mask = 64'h005500550F5F0F5F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~160 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y23_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_data[112] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_data [112] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [7] & ( ((\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [7])) # (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_AWID [7] & ( (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [7]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [7]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [7]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_014|src_data [112]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[112] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[112] .lut_mask = 64'h0505050537373737;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[112] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y23_N47
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_014|src_data [112]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .power_up = "low";
// synopsys translate_on

// Location: FF_X23_Y23_N11
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~17_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][112]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][112] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y23_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~17 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~17_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][112]~q  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][112]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~17 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~17 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y23_N28
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~17_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][112]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][112] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y22_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|src_data[112] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|src_data [112] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [7] & ( ((\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [7])) # (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_AWID [7] & ( (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [7]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
        .datac(gnd),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [7]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [7]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_011|src_data [112]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[112] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[112] .lut_mask = 64'h0055005533773377;
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[112] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y22_N17
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_011|src_data [112]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .power_up = "low";
// synopsys translate_on

// Location: FF_X19_Y22_N35
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~17_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][112]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][112] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y22_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~17 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~17_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][112]~q  ) ) # ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][112]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~17 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~17 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y23_N47
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~17_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][112]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][112] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y23_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~161 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~161_combout  = ( \u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout  & ( ((\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout  & \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][112]~q )) # 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][112]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout  & ( (\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout  & 
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][112]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][112]~q ),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][112]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~161_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~161 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~161 .lut_mask = 64'h005500550F5F0F5F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~161 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y28_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[112] (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data [112] = ( \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~160_combout  & ( \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~161_combout  ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~160_combout  & ( 
// \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~161_combout  ) ) # ( \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~160_combout  & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~161_combout  ) ) # ( 
// !\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~160_combout  & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~161_combout  & ( ((!\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~159_combout ) # 
// ((!\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~157_combout ) # (!\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~165_combout ))) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~162_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~162_combout ),
        .datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~159_combout ),
        .datac(!\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~157_combout ),
        .datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~165_combout ),
        .datae(!\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~160_combout ),
        .dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~161_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data [112]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112] .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112] .lut_mask = 64'hFFFDFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112] .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y26_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARLEN [1] & ( !\u0|hps_0|fpga_interfaces|h2f_ARLEN [3] $ (((!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]) # (!\u0|hps_0|fpga_interfaces|h2f_ARLEN [2]))) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_ARLEN [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARLEN [3] ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [3]),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [2]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1 .lut_mask = 64'h55555555555A555A;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y38_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout  = ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( (\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg 
// [2] $ (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .lut_mask = 64'h33CC33CC50505050;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y38_N53
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y38_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout  = ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( (\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ) ) ) ) # 
// ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( (\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ) ) ) ) # 
// ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg 
// [2]) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]) ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg 
// [2] & !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]) ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),
        .datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .lut_mask = 64'h3030CFCF00550055;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y38_N14
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y38_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  = ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] $ 
// (((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .lut_mask = 64'hF50AF50AFF00FF00;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y38_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout  = ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # ((\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .lut_mask = 64'hCCCFCCCF00030003;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y38_N38
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y38_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  = ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .lut_mask = 64'h3000300000000000;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y38_N25
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y38_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout  = ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( (\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ) ) ) ) # 
// ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( (\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ) ) ) ) # 
// ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  ) 
// ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  ) ) 
// )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .lut_mask = 64'h0F0FF0F011111111;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y38_N32
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y38_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout  = ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( (\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ) ) ) ) # 
// ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( (\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ) ) ) ) # 
// ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ) 
// # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]) ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),
        .datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .lut_mask = 64'h0C0CF3F300550055;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y38_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout  = ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout  & ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout  & ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout  & ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout  & ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  ) ) ) # ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout  & ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout  & ( 
// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout  & 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout  & 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ))) # 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout  & ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout  & ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),
        .datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .lut_mask = 64'h0F0F8F0F0F0F0F0F;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y38_N44
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y38_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout  = !\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .lut_mask = 64'hFF00FF00FF00FF00;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y38_N41
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";
// synopsys translate_on

// Location: FF_X21_Y38_N8
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y38_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q  & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q 
// ) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ) ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q  & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q 
// ) # ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0_combout  & (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q  & 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout ))) ) ) ) # ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q  & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q 
//  & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ) ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q  & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q 
//  & (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0_combout  & (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q  & 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout ),
        .datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .lut_mask = 64'h04000505AEAAAFAF;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y38_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout  = ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) # 
// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~1_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .lut_mask = 64'hFFFAFFFA00000000;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y38_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout  = ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & (((\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & \u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout )))) # 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & (((\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & \u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout )) # 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ))) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & ( 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .lut_mask = 64'h11111111111F111F;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y38_N26
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y38_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  = ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// (((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) # 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q )) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  
// & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .lut_mask = 64'h0A0A0A0ACA0ACA0A;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y38_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~1_combout  & ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~1_combout  & ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & 
// ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) # 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ))) ) ) ) # ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~1_combout  & ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & 
// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )) # 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))))) ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~1_combout  & ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & 
// ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) # 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~1_combout ),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .lut_mask = 64'h2A2A2A202A2A2020;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y38_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_013|packet_in_progress~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_013|packet_in_progress~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout  & ( (!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & ((\u0|mm_interconnect_0|cmd_mux_013|packet_in_progress~q ))) # 
// (\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout  & ( 
// \u0|mm_interconnect_0|cmd_mux_013|packet_in_progress~q  ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_013|packet_in_progress~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_013|packet_in_progress~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_013|packet_in_progress~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_013|packet_in_progress~0 .lut_mask = 64'h00FF00FF03CF03CF;
defparam \u0|mm_interconnect_0|cmd_mux_013|packet_in_progress~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y38_N20
dffeas \u0|mm_interconnect_0|cmd_mux_013|packet_in_progress (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_013|packet_in_progress~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_013|packet_in_progress~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_013|packet_in_progress .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_013|packet_in_progress .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y38_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_013|update_grant~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_013|update_grant~0_combout  = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  & ( (!\u0|mm_interconnect_0|cmd_mux_013|packet_in_progress~q  
// & ((!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]) # (!\u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout ))) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  & ( (!\u0|mm_interconnect_0|cmd_mux_013|packet_in_progress~q ) # ((\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & 
// \u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout )) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_013|packet_in_progress~q ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_013|update_grant~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_013|update_grant~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_013|update_grant~0 .lut_mask = 64'hF0F3F0F3F0C0F0C0;
defparam \u0|mm_interconnect_0|cmd_mux_013|update_grant~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y38_N8
dffeas \u0|mm_interconnect_0|cmd_mux_013|saved_grant[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|cmd_mux_013|update_grant~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_013|saved_grant[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_013|saved_grant[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y38_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout  = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q  & 
// ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q  & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h4444444440004000;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y34_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & ( (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & 
// !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .lut_mask = 64'hFFFFFFFFAA00AA00;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y38_N47
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .power_up = "low";
// synopsys translate_on

// Location: FF_X21_Y38_N20
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X21_Y38_N59
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";
// synopsys translate_on

// Location: FF_X21_Y38_N17
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X21_Y38_N32
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y38_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~2_combout  = ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & ( 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] 
// & !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1])) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~2 .lut_mask = 64'hA000A00000000000;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y38_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~3 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~3_combout  = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~2_combout  & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & 
// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0_combout ))) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~2_combout  & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0_combout  & !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~3 .lut_mask = 64'h0F000F00CF00CF00;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y38_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~3_combout  & ( 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~3_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q  & 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .lut_mask = 64'h0C0C0C0C0F000F00;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y38_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  = ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) # ((!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]) # ((!\u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout ) # 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .lut_mask = 64'hFFEFFFEF00000000;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y38_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout  = ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  & 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & ( 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .lut_mask = 64'h0033003300F000F0;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y38_N47
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y38_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout  = ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg 
// [2] & (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & 
// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) # 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q )))) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0 .lut_mask = 64'hC800000000000000;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y38_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg~0_combout  = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override~q  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout  & (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~0_combout  & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter [0])) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~0_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg~0 .lut_mask = 64'h0000000002020202;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y38_N26
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y38_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout  = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg [0] & 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0] & !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][129]~q )) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0] & ( 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0]) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg [0]),
        .datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid .lut_mask = 64'h8888888888008800;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y33_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_013|src_payload~6 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_013|src_payload~6_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [6] & ( \u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [6]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_013|src_payload~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~6 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y33_N11
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_013|src_payload~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .power_up = "low";
// synopsys translate_on

// Location: FF_X18_Y33_N44
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~15_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][111]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][111] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y33_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~15 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~15_combout  = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][111]~q  ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][111]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~15 .lut_mask = 64'h3333333300FF00FF;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~15 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y31_N50
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~15_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][111]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][111] .power_up = "low";
// synopsys translate_on

// Location: FF_X18_Y29_N11
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~16_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][111]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][111] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y27_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|src_data[111] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|src_data [111] = ( \u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & ( ((\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [6])) # (\u0|hps_0|fpga_interfaces|h2f_AWID [6]) ) ) # ( 
// !\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & ( (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [6]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [6]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_AWID [6]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_007|src_data [111]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[111] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[111] .lut_mask = 64'h0505050505FF05FF;
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[111] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y27_N13
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_007|src_data [111]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y29_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~16 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~16_combout  = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used 
// [1]) # (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][111]~q ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] & ( 
// (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][111]~q ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][111]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~16 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~16 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y29_N23
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~16_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][111]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][111] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y31_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~146 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~146_combout  = ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][111]~q  & ( (!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout  & 
// ((!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ) # ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout  & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][111]~q )))) # 
// (\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout  & (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout  & ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][111]~q )))) ) ) # ( 
// !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][111]~q  & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout  & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][111]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout ),
        .datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout ),
        .datac(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][111]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][111]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~146_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~146 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~146 .lut_mask = 64'h00CC00CCA0ECA0EC;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~146 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y33_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_017|src_payload~6 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_017|src_payload~6_combout  = (\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [6])

        .dataa(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [6]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_017|src_payload~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~6 .lut_mask = 64'h0505050505050505;
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y33_N26
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_017|src_payload~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .power_up = "low";
// synopsys translate_on

// Location: FF_X17_Y33_N38
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~15_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][111]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][111] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y33_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~15 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~15_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][111]~q  ) ) # ( 
// !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
        .datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][111]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~15 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~15 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y33_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][111]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][111]~feeder_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~15_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~15_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][111]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][111]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][111]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][111]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y33_N58
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][111]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][111]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][111] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y31_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_016|src_payload~6 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_016|src_payload~6_combout  = (\u0|hps_0|fpga_interfaces|h2f_ARID [6] & \u0|mm_interconnect_0|cmd_mux_016|saved_grant [1])

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [6]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_016|src_payload~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~6 .lut_mask = 64'h000F000F000F000F;
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y31_N11
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_016|src_payload~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .power_up = "low";
// synopsys translate_on

// Location: FF_X19_Y31_N2
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~15_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][111]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][111] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y31_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~15 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~15_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][111]~q  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][111]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~15 .lut_mask = 64'h3333333300FF00FF;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~15 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y31_N19
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~15_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][111]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][111] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y31_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~147 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~147_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][111]~q  & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~146_combout  & 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout  & ((!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ) # (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][111]~q )))) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][111]~q  & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~146_combout  & ((!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ) # 
// (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][111]~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~146_combout ),
        .datab(!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout ),
        .datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][111]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][111]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~147_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~147 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~147 .lut_mask = 64'hAA88AA880A080A08;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~147 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y24_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|src_data[111] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|src_data [111] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [6] & ( \u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARID [6] & ( \u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & ( 
// (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [6]) ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_ARID [6] & ( !\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & ( (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & 
// \u0|hps_0|fpga_interfaces|h2f_AWID [6]) ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARID [6] & ( !\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & ( (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [6]) ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [6]),
        .datad(gnd),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_ARID [6]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_009|src_data [111]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[111] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[111] .lut_mask = 64'h050505050505FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[111] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y24_N8
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_009|src_data [111]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .power_up = "low";
// synopsys translate_on

// Location: FF_X17_Y24_N38
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~16_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][111]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][111] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y24_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~16 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~16_combout  = ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][111]~q  & ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] ) ) # ( 
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][111]~q  & ( !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg 
// [111] ) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][111]~q  & ( !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ( 
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
        .datae(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][111]~q ),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~16 .lut_mask = 64'h00FF00FF0000FFFF;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~16 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y24_N43
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~16_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][111]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][111] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y24_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~150 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~150_combout  = ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][111]~q  & ( ((\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout  & 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][111]~q )) # (\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout ) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][111]~q  & ( 
// (\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout  & \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][111]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ),
        .datac(!\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout ),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][111]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][111]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~150_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~150 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~150 .lut_mask = 64'h003300330F3F0F3F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~150 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y23_N8
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~16_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][111]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][111] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y23_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|src_data[111] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|src_data [111] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [6] & ( \u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARID [6] & ( \u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & ( 
// (\u0|hps_0|fpga_interfaces|h2f_AWID [6] & \u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]) ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_ARID [6] & ( !\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_AWID [6] & 
// \u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]) ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARID [6] & ( !\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_AWID [6] & \u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]) ) 
// ) )

        .dataa(gnd),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_AWID [6]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
        .datad(gnd),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_ARID [6]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_011|src_data [111]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[111] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[111] .lut_mask = 64'h030303030303FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[111] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y23_N58
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_011|src_data [111]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y23_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~16 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~16_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][111]~q  & ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg 
// [111] ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][111]~q  & ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] & ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] ) ) ) # ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][111]~q  & ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] & ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][111]~q ),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~16 .lut_mask = 64'h00000F0FF0F0FFFF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~16 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y23_N38
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~16_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][111]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][111] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y23_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_data[111] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_data [111] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [6] & ( ((\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [6])) # (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_ARID [6] & ( (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [6]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [6]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [6]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_014|src_data [111]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[111] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[111] .lut_mask = 64'h0303030357575757;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[111] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y23_N20
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_014|src_data [111]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .power_up = "low";
// synopsys translate_on

// Location: FF_X23_Y23_N8
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~16_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][111]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][111] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y23_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~16 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~16_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][111]~q  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][111]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~16 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~16 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y23_N35
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~16_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][111]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][111] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y23_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~151 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~151_combout  = ( \u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout  & ( ((\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout  & \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][111]~q 
// )) # (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][111]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout  & ( (\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout  & 
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][111]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][111]~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][111]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~151_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~151 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~151 .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~151 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y32_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_012|src_payload~6 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_012|src_payload~6_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [6] & ( \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [6]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_012|src_payload~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~6 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y32_N52
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_012|src_payload~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .power_up = "low";
// synopsys translate_on

// Location: FF_X15_Y30_N53
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~15_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][111]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][111] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y30_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~15 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~15_combout  = (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111])) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & 
// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][111]~q )))

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][111]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~15 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~15 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y30_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][111]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][111]~feeder_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~15_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~15_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][111]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][111]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][111]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][111]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y30_N28
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][111]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][111]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][111] .power_up = "low";
// synopsys translate_on

// Location: FF_X13_Y27_N41
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~15_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][111]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][111] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y27_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_002|src_payload~6 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_002|src_payload~6_combout  = ( \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [6] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [6]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_002|src_payload~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~6 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y27_N31
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_002|src_payload~6_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y27_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~15 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~15_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] & ( 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][111]~q ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][111]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][111]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~15 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~15 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y27_N11
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~15_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][111]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][111] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y27_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~46 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~46_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][111]~q  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0] & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][111]~q  & (((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q  & 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0])) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0]),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][111]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~46_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~46 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~46 .lut_mask = 64'h0037003700FF00FF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~46 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y24_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_001|src_payload~6 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_001|src_payload~6_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [6] & ( \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [6]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_001|src_payload~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~6 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y24_N50
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_001|src_payload~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .power_up = "low";
// synopsys translate_on

// Location: FF_X15_Y24_N20
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~15_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][111]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][111] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y24_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~15 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~15_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][111]~q  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][111]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~15 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~15 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y26_N14
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~15_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][111]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][111] .power_up = "low";
// synopsys translate_on

// Location: FF_X19_Y26_N53
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~16_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][111]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][111] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y24_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|src_data[111] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|src_data [111] = ( \u0|mm_interconnect_0|cmd_mux|saved_grant [1] & ( ((\u0|hps_0|fpga_interfaces|h2f_AWID [6] & \u0|mm_interconnect_0|cmd_mux|saved_grant [0])) # (\u0|hps_0|fpga_interfaces|h2f_ARID [6]) ) ) # ( 
// !\u0|mm_interconnect_0|cmd_mux|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_AWID [6] & \u0|mm_interconnect_0|cmd_mux|saved_grant [0]) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_AWID [6]),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [6]),
        .datad(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux|src_data [111]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|src_data[111] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|src_data[111] .lut_mask = 64'h005500550F5F0F5F;
defparam \u0|mm_interconnect_0|cmd_mux|src_data[111] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y24_N5
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux|src_data [111]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y26_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~16 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~16_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][111]~q  & ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg 
// [111] ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][111]~q  & ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] & ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] ) ) ) # ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][111]~q  & ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] & ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] ) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][111]~q ),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~16 .lut_mask = 64'h00005555AAAAFFFF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~16 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y26_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][111]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][111]~feeder_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~16_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~16_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][111]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][111]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][111]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][111]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y26_N47
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][111]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][111]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][111] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y26_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~153 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~153_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][111]~q  & ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][111]~q  & ( 
// (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~46_combout  & (\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout  & ((\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ) # (\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout )))) ) ) 
// ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][111]~q  & ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][111]~q  & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~46_combout  & 
// ((\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ) # (\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ))) ) ) ) # ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][111]~q  & ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][111]~q  & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~46_combout  & \u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][111]~q  & ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][111]~q  & ( !\u0|mm_interconnect_0|rsp_mux_001|src_payload~46_combout  ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~46_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ),
        .datad(!\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ),
        .datae(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][111]~q ),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][111]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~153_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~153 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~153 .lut_mask = 64'hAAAA22220AAA0222;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~153 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y33_N23
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~15_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][111]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][111] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y33_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_006|src_payload~6 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_006|src_payload~6_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [6] & ( \u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [6]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_006|src_payload~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~6 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y33_N31
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_006|src_payload~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y33_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~15 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~15_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] & ( 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][111]~q ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][111]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][111]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~15 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~15 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y33_N47
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~15_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][111]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][111] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y33_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~47 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~47_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][111]~q  & 
// (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]))) ) ) 
// # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][111]~q  & ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][111]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~47_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~47 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~47 .lut_mask = 64'h00770077007F007F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~47 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y30_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_005|src_payload~6 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_005|src_payload~6_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [6] & ( \u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [6]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_005|src_payload~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~6 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y30_N2
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_005|src_payload~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .power_up = "low";
// synopsys translate_on

// Location: FF_X11_Y30_N32
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~15_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][111]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][111] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y30_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~15 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~15_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][111]~q  ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][111]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~15 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~15 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y30_N32
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~15_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][111]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][111] .power_up = "low";
// synopsys translate_on

// Location: FF_X22_Y26_N53
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~16_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][111]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][111] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y26_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|src_data[111] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|src_data [111] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [6] & ( ((\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [6])) # (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_ARID [6] & ( (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [6]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [6]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [6]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_004|src_data [111]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[111] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[111] .lut_mask = 64'h0303030357575757;
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[111] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y26_N49
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_004|src_data [111]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y26_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~16 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~16_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] & ( 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][111]~q ) ) ) # ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][111]~q ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][111]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~16 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~16 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y26_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][111]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][111]~feeder_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~16_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~16_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][111]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][111]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][111]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][111]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y26_N47
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][111]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][111]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][111] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y30_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~154 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~154_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][111]~q  & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][111]~q  & ( 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout  & (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~47_combout  & ((\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ) # 
// (\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][111]~q  & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][111]~q  & ( 
// (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~47_combout  & ((\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ) # (\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ))) ) ) ) # ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][111]~q  & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][111]~q  & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout  & 
// !\u0|mm_interconnect_0|rsp_mux_001|src_payload~47_combout ) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][111]~q  & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][111]~q  & ( 
// !\u0|mm_interconnect_0|rsp_mux_001|src_payload~47_combout  ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout ),
        .datab(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~47_combout ),
        .datac(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ),
        .datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][111]~q ),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][111]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~154_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~154 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~154 .lut_mask = 64'hCCCC44440CCC0444;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~154 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y33_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_003|src_payload~6 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_003|src_payload~6_combout  = (\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [6])

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [6]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_003|src_payload~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~6 .lut_mask = 64'h0303030303030303;
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y33_N44
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_003|src_payload~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .power_up = "low";
// synopsys translate_on

// Location: FF_X17_Y33_N23
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~15_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][111]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][111] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y33_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~15 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~15_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][111]~q  ) ) # ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][111]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~15 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~15 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y30_N38
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~15_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][111]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][111] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y30_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~155 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~155_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][111]~q  & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout  & ( 
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~153_combout  & (\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout  & \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~154_combout )) ) ) ) # ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][111]~q  & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout  & ( (\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~153_combout  & 
// \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~154_combout ) ) ) ) # ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][111]~q  & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout  & ( 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][111]~q  & (\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~153_combout  & (\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout  & 
// \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~154_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][111]~q  & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout  & ( 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][111]~q  & (\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~153_combout  & \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~154_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][111]~q ),
        .datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~153_combout ),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout ),
        .datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~154_combout ),
        .datae(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][111]~q ),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~155_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~155 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~155 .lut_mask = 64'h0022000200330003;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~155 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y23_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_data[111] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|src_data [111] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [6] & ( \u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARID [6] & ( \u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & ( 
// (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [6]) ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_ARID [6] & ( !\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & 
// \u0|hps_0|fpga_interfaces|h2f_AWID [6]) ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARID [6] & ( !\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [6]) ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [6]),
        .datad(gnd),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_ARID [6]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_015|src_data [111]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[111] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[111] .lut_mask = 64'h050505050505FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[111] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y23_N41
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_015|src_data [111]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .power_up = "low";
// synopsys translate_on

// Location: FF_X18_Y23_N11
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~16_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][111]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][111] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y23_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~16 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~16_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][111]~q  & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] ) ) # ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][111]~q  & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][111]~q  & ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][111]~q ),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~16 .lut_mask = 64'h0F0F0F0F0000FFFF;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~16 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y26_N35
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~16_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][111]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][111] .power_up = "low";
// synopsys translate_on

// Location: FF_X25_Y26_N41
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~16_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][111]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][111] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y24_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_data[111] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|src_data [111] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [6] & ( ((\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [6])) # (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_AWID [6] & ( (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [6]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [6]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [6]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_018|src_data [111]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[111] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[111] .lut_mask = 64'h0505050537373737;
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[111] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y24_N40
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_018|src_data [111]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y26_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~16 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~16_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] & ( (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]) # 
// (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][111]~q ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] & ( (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used 
// [1] & \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][111]~q ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][111]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~16 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~16 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y26_N10
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~16_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][111]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][111] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y26_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~152 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~152_combout  = ( \u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout  & ( ((\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout  & 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][111]~q )) # (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][111]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout  & ( 
// (\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout  & \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][111]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][111]~q ),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][111]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~152_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~152 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~152 .lut_mask = 64'h0303030303FF03FF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~152 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y34_N32
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~15_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][111]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][111] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y34_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_020|src_payload~6 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_020|src_payload~6_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [6] & ( \u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [6]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_020|src_payload~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~6 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y34_N43
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_020|src_payload~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y34_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~15 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~15_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][111]~q  & ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][111]~q  & ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] ) ) ) # ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][111]~q  & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] & ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][111]~q ),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~15 .lut_mask = 64'h00000F0FF0F0FFFF;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~15 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y32_N14
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~15_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][111]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][111] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y32_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_019|src_payload~6 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_019|src_payload~6_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [6] & ( \u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [6]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_019|src_payload~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~6 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y32_N38
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_019|src_payload~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .power_up = "low";
// synopsys translate_on

// Location: FF_X25_Y32_N44
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~15_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][111]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][111] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y32_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~15 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~15_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][111]~q  ) ) # ( 
// !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][111]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~15 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~15 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y32_N29
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~15_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][111]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][111] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y25_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_data[111] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|src_data [111] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [6] & ( ((\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [6])) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_ARID [6] & ( (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [6]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [6]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [6]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_008|src_data [111]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[111] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[111] .lut_mask = 64'h0505050537373737;
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[111] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y25_N4
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_008|src_data [111]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .power_up = "low";
// synopsys translate_on

// Location: FF_X18_Y25_N47
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~16_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][111]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][111] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y25_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~16 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~16_combout  = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][111]~q  ) ) # ( 
// !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][111]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~16 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~16 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y29_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][111]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][111]~feeder_combout  = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~16_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~16_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][111]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][111]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][111]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][111]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y29_N14
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][111]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][111]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][111] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y32_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~148 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~148_combout  = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][111]~q  & ( (!\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout  & 
// ((!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ) # ((!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout  & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][111]~q )))) # 
// (\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout  & (!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout  & ((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][111]~q )))) ) ) # ( 
// !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][111]~q  & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout  & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][111]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout ),
        .datac(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][111]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][111]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~148_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~148 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~148 .lut_mask = 64'h00CC00CCA0ECA0EC;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~148 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y32_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_021|src_payload~6 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_021|src_payload~6_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [6] & ( \u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [6]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_021|src_payload~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~6 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y32_N8
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_021|src_payload~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .power_up = "low";
// synopsys translate_on

// Location: FF_X25_Y32_N47
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~15_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][111]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][111] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y32_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~15 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~15_combout  = (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111])) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & 
// ((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][111]~q )))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][111]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~15 .lut_mask = 64'h0C3F0C3F0C3F0C3F;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~15 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y32_N37
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~15_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][111]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][111] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y32_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~149 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~149_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][111]~q  & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout  & 
// (!\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~148_combout  & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][111]~q ) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout )))) ) ) # ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][111]~q  & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~148_combout  & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][111]~q ) # 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][111]~q ),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ),
        .datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~148_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][111]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~149_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~149 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~149 .lut_mask = 64'hCF00CF0045004500;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~149 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y28_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[111] (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data [111] = ( \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~152_combout  & ( \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~149_combout  ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~152_combout  & ( 
// \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~149_combout  & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~147_combout ) # (((!\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~155_combout ) # 
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~151_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~150_combout )) ) ) ) # ( \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~152_combout  & ( 
// !\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~149_combout  ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~152_combout  & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~149_combout  ) )

        .dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~147_combout ),
        .datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~150_combout ),
        .datac(!\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~151_combout ),
        .datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~155_combout ),
        .datae(!\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~152_combout ),
        .dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~149_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data [111]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111] .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111] .lut_mask = 64'hFFFFFFFFFFBFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111] .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y27_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~3 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~3_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3_combout  & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~4_combout  ) ) # ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3_combout  & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~4_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~4_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~3 .lut_mask = 64'h0F0F0F0FF0F0F0F0;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y27_N35
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y27_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount [3] & ( (!\u0|hps_0|fpga_interfaces|h2f_AWLEN [0] $ (!\u0|hps_0|fpga_interfaces|h2f_AWLEN [1])) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount [3] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (!\u0|hps_0|fpga_interfaces|h2f_AWLEN [0] 
// $ (!\u0|hps_0|fpga_interfaces|h2f_AWLEN [1]))) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [0]),
        .datac(gnd),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3 .lut_mask = 64'h2288228877DD77DD;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y28_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3_combout  & ( 
// ((\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout )) # (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]) ) ) # ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3_combout  & ( (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5 .lut_mask = 64'h0033003355775577;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y30_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y30_N32
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y28_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout  = ( \u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & ( 
// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~4_combout ) # ((\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0])) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & ( 
// (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~4_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 .lut_mask = 64'h0F000F00AFAAAFAA;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y28_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout  = ( 
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout  & ( (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg 
// [2] $ (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])) # (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) 
// ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout  & ( 
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] $ 
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 .lut_mask = 64'h0CC00CC03FF33FF3;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y28_N38
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";
// synopsys translate_on

// Location: FF_X25_Y28_N5
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y28_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout  = ( 
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) # 
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout )) ) 
// ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] 
// & ( (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) # 
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout )) ) 
// ) ) # ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] 
// & ( (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # 
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout ) ) ) ) # ( 
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout  & \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) 
// )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout ),
        .datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datae(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6 .lut_mask = 64'h1111DDDDDD1111DD;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y27_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout  & ( 
// ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~0_combout  & \u0|mm_interconnect_0|cmd_mux_007|saved_grant [0])) # (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]) ) ) # ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout  & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~0_combout  & \u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
        .datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .lut_mask = 64'h050505FF050505FF;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y28_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~1_combout  & ( 
// ((\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout )) # (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]) ) ) # ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~1_combout  & ( (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 .lut_mask = 64'h0033003355775577;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y28_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] & ( 
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & 
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])) ) ) # ( 
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] & ( ((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # 
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])) # (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg 
// [3]) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .lut_mask = 64'hDDFFDDFF22002200;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y28_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout  = ( \u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & ( 
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  & ( (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout )) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ))) ) ) ) # ( 
// !\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  & ( (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout  & \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_007|saved_grant 
// [1] & ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  & ( ((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # 
// ((\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout ))) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ) ) ) ) # ( 
// !\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  & ( 
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # ((\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout )) ) 
// ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout ),
        .datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .lut_mask = 64'hFF05FF3700050037;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y28_N50
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y28_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  = ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] & ( 
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & 
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .lut_mask = 64'h3000300000000000;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y28_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout  = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  & ( 
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) # 
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout )) ) 
// ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  & ( (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) # (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout )) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ),
        .datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 .lut_mask = 64'h03CF03CFCF03CF03;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y28_N44
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .power_up = "low";
// synopsys translate_on

// Location: FF_X25_Y28_N47
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y28_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout  = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  & ( 
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] $ 
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6])))) # (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout )) ) ) # ( 
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  & ( (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]))) # (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
        .datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 .lut_mask = 64'h11DD11DDD11DD11D;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y29_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|src_payload[0] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|src_payload [0] = ( \u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] ) # ( !\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & ( (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_WLAST 
// [0]) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_WLAST [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_007|src_payload [0]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|src_payload[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|src_payload[0] .lut_mask = 64'h000F000FFFFFFFFF;
defparam \u0|mm_interconnect_0|cmd_mux_007|src_payload[0] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y29_N32
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_007|src_payload [0]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y31_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal13~0 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal13~0_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [18] ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router_001|Equal13~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal13~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal13~0 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|router_001|Equal13~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y31_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal13~1 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal13~1_combout  = ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & ( \u0|mm_interconnect_0|router_001|Equal13~0_combout  & ( (\u0|mm_interconnect_0|router_001|Equal1~0_combout  & 
// (\u0|mm_interconnect_0|router_001|Equal1~2_combout  & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & \u0|mm_interconnect_0|router_001|Equal1~1_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),
        .datab(!\u0|mm_interconnect_0|router_001|Equal1~2_combout ),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),
        .datad(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),
        .dataf(!\u0|mm_interconnect_0|router_001|Equal13~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router_001|Equal13~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal13~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal13~1 .lut_mask = 64'h0000000000010000;
defparam \u0|mm_interconnect_0|router_001|Equal13~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y29_N50
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[7] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|router_001|Equal13~1_combout ),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [7]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[7] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y29_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|src_valid~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|src_valid~1_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & ( (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & (\u0|mm_interconnect_0|router_001|Equal13~1_combout  & 
// ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [7])))) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [7]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|router_001|Equal13~1_combout ),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_007|src_valid~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|src_valid~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|src_valid~1 .lut_mask = 64'h0000000003010301;
defparam \u0|mm_interconnect_0|cmd_mux_007|src_valid~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y27_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~2 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~2_combout  = ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [0] & ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]),
        .datad(gnd),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0]),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~2 .lut_mask = 64'h0000000000000F0F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y27_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~3 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~3_combout  = ( !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0] & ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] ) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0]),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~3 .lut_mask = 64'h0000000055550000;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y27_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~0_combout  = ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [0] & ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & ( !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]),
        .datad(gnd),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0]),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~0 .lut_mask = 64'h000000000000F0F0;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y29_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[4]~5 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[4]~5_combout  = ( \u0|hps_0|fpga_interfaces|h2f_AWADDR [4] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [4]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_AWADDR [4] & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [4]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [4]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[4]~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[4]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[4]~5 .lut_mask = 64'h03030303CFCFCFCF;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[4]~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y27_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~1 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~1_combout  = ( !\u0|hps_0|fpga_interfaces|h2f_AWLEN [3] & ( \u0|hps_0|fpga_interfaces|h2f_AWLEN [1] & ( \u0|hps_0|fpga_interfaces|h2f_AWLEN [2] ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_AWLEN [3] & 
// ( !\u0|hps_0|fpga_interfaces|h2f_AWLEN [1] & ( (\u0|hps_0|fpga_interfaces|h2f_AWLEN [2]) # (\u0|hps_0|fpga_interfaces|h2f_AWLEN [0]) ) ) )

        .dataa(gnd),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [0]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [2]),
        .datad(gnd),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [3]),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~1 .lut_mask = 64'h3F3F00000F0F0000;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y27_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~0_combout  = ( \u0|hps_0|fpga_interfaces|h2f_AWLEN [2] & ( \u0|hps_0|fpga_interfaces|h2f_AWLEN [1] & ( !\u0|hps_0|fpga_interfaces|h2f_AWLEN [3] ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_AWLEN [2] & 
// ( \u0|hps_0|fpga_interfaces|h2f_AWLEN [1] & ( !\u0|hps_0|fpga_interfaces|h2f_AWLEN [3] ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_AWLEN [2] & ( !\u0|hps_0|fpga_interfaces|h2f_AWLEN [1] & ( !\u0|hps_0|fpga_interfaces|h2f_AWLEN [3] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [3]),
        .datad(gnd),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [2]),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~0 .lut_mask = 64'h0000F0F0F0F0F0F0;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y29_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|LessThan14~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|LessThan14~0_combout  = ( !\u0|hps_0|fpga_interfaces|h2f_AWLEN [3] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~0_combout  & ( (!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & 
// ((!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]) # ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~1_combout  & !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0])))) ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_AWLEN [3] & ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~0_combout  & ( (!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~1_combout  & (!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0] & 
// !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]))) ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_AWLEN [3] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~0_combout  & ( (!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]) # 
// ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~1_combout  & (!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0] & !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]))) ) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~1_combout ),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [3]),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|LessThan14~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|LessThan14~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|LessThan14~0 .lut_mask = 64'hEAAA8000AA800000;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|LessThan14~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y27_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~1 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~1_combout  = ( !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0] & ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & ( !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]),
        .datad(gnd),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0]),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~1 .lut_mask = 64'h00000000F0F00000;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y27_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~4 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~4_combout  = ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [0] & ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] & ( !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]),
        .datad(gnd),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0]),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~4 .lut_mask = 64'h000000000000F0F0;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y27_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~0_combout  = ( !\u0|hps_0|fpga_interfaces|h2f_AWLEN [3] & ( \u0|hps_0|fpga_interfaces|h2f_AWLEN [1] & ( (\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0] & \u0|hps_0|fpga_interfaces|h2f_AWLEN [2]) ) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_AWLEN [3] & ( !\u0|hps_0|fpga_interfaces|h2f_AWLEN [1] & ( (\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0] & ((\u0|hps_0|fpga_interfaces|h2f_AWLEN [2]) # (\u0|hps_0|fpga_interfaces|h2f_AWLEN [0]))) ) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0]),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [0]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [2]),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [3]),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~0 .lut_mask = 64'h0555000000550000;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y29_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector28~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector28~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~0_combout  & ( (!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & (!\u0|hps_0|fpga_interfaces|h2f_AWSIZE 
// [1] & (!\u0|hps_0|fpga_interfaces|h2f_AWLEN [3] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~0_combout ))) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~0_combout  & ( (!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & 
// (!\u0|hps_0|fpga_interfaces|h2f_AWLEN [3] & ((!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]) # (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~0_combout )))) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [3]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector28~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector28~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector28~0 .lut_mask = 64'hA080A08080008000;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector28~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y27_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~5 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~5_combout  = ( !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0] & ( !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]),
        .datad(gnd),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0]),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~5 .lut_mask = 64'h0F0F000000000000;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y29_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|LessThan12~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|LessThan12~0_combout  = ( !\u0|hps_0|fpga_interfaces|h2f_AWLEN [3] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~0_combout  & ( (!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & 
// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~1_combout  & (!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0] & !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]))) ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_AWLEN [3] & ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~0_combout  & ( (!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & ((!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]) # ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~1_combout  & 
// !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0])))) ) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~1_combout ),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [3]),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|LessThan12~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|LessThan12~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|LessThan12~0 .lut_mask = 64'hAA80000080000000;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|LessThan12~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y29_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~6 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~6_combout  = ( !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & ( (!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] & \u0|hps_0|fpga_interfaces|h2f_AWSIZE [0]) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~6 .lut_mask = 64'h00F000F000000000;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~6 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y29_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|aligned_address_bits[1] (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|aligned_address_bits [1] = ( \u0|hps_0|fpga_interfaces|h2f_AWADDR [1] & ( (!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|aligned_address_bits [1]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|aligned_address_bits[1] .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|aligned_address_bits[1] .lut_mask = 64'h0000000088888888;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|aligned_address_bits[1] .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y29_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~7 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~7_combout  = ( !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] & ( (!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0]) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~7 .lut_mask = 64'hAA00AA0000000000;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~7 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y29_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~21 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~21_sumout  = SUM(( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~7_combout  ) + ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & 
// ((\u0|hps_0|fpga_interfaces|h2f_AWADDR [0]))) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [0])) ) + ( !VCC ))
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~22  = CARRY(( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~7_combout  ) + ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & 
// ((\u0|hps_0|fpga_interfaces|h2f_AWADDR [0]))) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [0])) ) + ( !VCC ))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [0]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~7_combout ),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~21_sumout ),
        .cout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~22 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~21 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~21 .lut_mask = 64'h0000FC30000000FF;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~21 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y29_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~77 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~77_sumout  = SUM(( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (((\u0|hps_0|fpga_interfaces|h2f_AWADDR [0] & 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~7_combout )))) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [0])) ) + ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~7_combout  ) + ( !VCC ))
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~78  = CARRY(( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (((\u0|hps_0|fpga_interfaces|h2f_AWADDR [0] & 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~7_combout )))) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [0])) ) + ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~7_combout  ) + ( !VCC ))

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [0]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [0]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~7_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~7_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~77_sumout ),
        .cout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~78 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~77 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~77 .lut_mask = 64'h0000FF000000111B;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~77 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y29_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|LessThan10~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|LessThan10~0_combout  = ( !\u0|hps_0|fpga_interfaces|h2f_AWLEN [3] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~0_combout  & ( (!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0] & 
// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~1_combout  & (!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]))) ) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0]),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~1_combout ),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [3]),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|LessThan10~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|LessThan10~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|LessThan10~0 .lut_mask = 64'h8000000000000000;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|LessThan10~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y29_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout  = ( \u0|hps_0|fpga_interfaces|h2f_AWADDR [0] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [0]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_AWADDR [0] & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [0]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9 .lut_mask = 64'h03030303CFCFCFCF;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y29_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector29~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector29~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|LessThan10~0_combout  & ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout  & ( (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~77_sumout ) ) ) ) # ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|LessThan10~0_combout  & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout  & ( (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & 
// (((!\u0|hps_0|fpga_interfaces|h2f_AWBURST [1])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~21_sumout ))) # (\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & 
// (((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~77_sumout )))) ) ) ) # ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|LessThan10~0_combout  & ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout  & ( (\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~77_sumout ) ) ) ) # ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|LessThan10~0_combout  & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout  & ( (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~21_sumout  & (\u0|hps_0|fpga_interfaces|h2f_AWBURST [1]))) # (\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & 
// (((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~77_sumout )))) ) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~21_sumout ),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [1]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~77_sumout ),
        .datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|LessThan10~0_combout ),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector29~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector29~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector29~0 .lut_mask = 64'h04370033C4F7CCFF;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector29~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y29_N56
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector29~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y29_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~73 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~73_sumout  = SUM(( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~6_combout  ) + ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & 
// ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|aligned_address_bits [1]))) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst 
// [1])) ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~78  ))
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~74  = CARRY(( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~6_combout  ) + ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & 
// ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|aligned_address_bits [1]))) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst 
// [1])) ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~78  ))

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [1]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~6_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|aligned_address_bits [1]),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~78 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~73_sumout ),
        .cout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~74 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~73 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~73 .lut_mask = 64'h0000FA50000000FF;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~73 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y27_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~1_combout  = ( \u0|hps_0|fpga_interfaces|h2f_AWLEN [3] & ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_AWLEN [3] & ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] & ( 
// (!\u0|hps_0|fpga_interfaces|h2f_AWLEN [2] & (!\u0|hps_0|fpga_interfaces|h2f_AWLEN [1] & ((!\u0|hps_0|fpga_interfaces|h2f_AWLEN [0]) # (!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0])))) # (\u0|hps_0|fpga_interfaces|h2f_AWLEN [2] & 
// (((\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0])))) ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_AWLEN [3] & ( !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] & ( (!\u0|hps_0|fpga_interfaces|h2f_AWLEN [2] & (((\u0|hps_0|fpga_interfaces|h2f_AWLEN [0] & 
// \u0|hps_0|fpga_interfaces|h2f_AWSIZE [0])) # (\u0|hps_0|fpga_interfaces|h2f_AWLEN [1]))) # (\u0|hps_0|fpga_interfaces|h2f_AWLEN [2] & (((!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0])))) ) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [2]),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [0]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [1]),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [3]),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~1 .lut_mask = 64'h52FA0000AD05FFFF;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y29_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [1] & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ) 
// # (\u0|hps_0|fpga_interfaces|h2f_AWADDR [1]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [1] & ( (\u0|hps_0|fpga_interfaces|h2f_AWADDR [1] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ) 
// ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [1]),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8 .lut_mask = 64'h4444444477777777;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y29_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~17 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~17_sumout  = SUM(( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~6_combout  ) + ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & 
// ((\u0|hps_0|fpga_interfaces|h2f_AWADDR [1]))) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [1])) ) + ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~22  ))
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~18  = CARRY(( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~6_combout  ) + ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & 
// ((\u0|hps_0|fpga_interfaces|h2f_AWADDR [1]))) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [1])) ) + ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~22  ))

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [1]),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~6_combout ),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [1]),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~22 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~17_sumout ),
        .cout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~18 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~17 .lut_mask = 64'h0000EE22000000FF;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~17 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y29_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector28~1 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector28~1_combout  = ( !\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & ( (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [1] & 
// ((((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout ))))) # (\u0|hps_0|fpga_interfaces|h2f_AWBURST [1] & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector28~0_combout  & 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~17_sumout )) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector28~0_combout  & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~1_combout  
// & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout ))) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~1_combout  & 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~17_sumout )))))) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & ( (((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~73_sumout ))) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [1]),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector28~0_combout ),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~73_sumout ),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~1_combout ),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout ),
        .datag(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~17_sumout ),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector28~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector28~1 .extended_lut = "on";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector28~1 .lut_mask = 64'h04050F0FBFAF0F0F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector28~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y29_N20
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector28~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y29_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~69 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~69_sumout  = SUM(( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~5_combout  ) + ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & 
// (\u0|hps_0|fpga_interfaces|h2f_AWADDR [2])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [2]))) ) + ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~74  ))
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~70  = CARRY(( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~5_combout  ) + ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & 
// (\u0|hps_0|fpga_interfaces|h2f_AWADDR [2])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [2]))) ) + ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~74  ))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [2]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~5_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [2]),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~74 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~69_sumout ),
        .cout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~70 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~69 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~69 .lut_mask = 64'h0000F3C0000000FF;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~69 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y29_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~13 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~13_sumout  = SUM(( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [2])) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [2]))) ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~5_combout  ) + ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~18  ))
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~14  = CARRY(( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [2])) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [2]))) ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~5_combout  ) + ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~18  ))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [2]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~5_combout ),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~18 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~13_sumout ),
        .cout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~14 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~13 .lut_mask = 64'h0000FF0000000C3F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y29_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [2] & ( (\u0|hps_0|fpga_interfaces|h2f_AWADDR [2]) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [2] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & 
// \u0|hps_0|fpga_interfaces|h2f_AWADDR [2]) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [2]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7 .lut_mask = 64'h0A0A0A0A5F5F5F5F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y29_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector27~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector27~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~13_sumout  & ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout  & ( (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~69_sumout ) ) ) ) # ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~13_sumout  & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout  & ( (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & 
// ((!\u0|hps_0|fpga_interfaces|h2f_AWBURST [1]) # ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|LessThan12~0_combout )))) # (\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & 
// (((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~69_sumout )))) ) ) ) # ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~13_sumout  & ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout  & ( (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & (\u0|hps_0|fpga_interfaces|h2f_AWBURST [1] & 
// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|LessThan12~0_combout ))) # (\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & (((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~69_sumout )))) ) ) ) # ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~13_sumout  & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout  & ( (\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~69_sumout ) ) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [1]),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|LessThan12~0_combout ),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~69_sumout ),
        .datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~13_sumout ),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector27~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector27~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector27~0 .lut_mask = 64'h000F404FB0BFF0FF;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector27~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y29_N26
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector27~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y29_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~65 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~65_sumout  = SUM(( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [3])) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [3]))) ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~4_combout  ) + ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~70  ))
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~66  = CARRY(( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [3])) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [3]))) ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~4_combout  ) + ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~70  ))

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [3]),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~4_combout ),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [3]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~70 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~65_sumout ),
        .cout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~66 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~65 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~65 .lut_mask = 64'h0000F0F000004477;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~65 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y29_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~9 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~9_sumout  = SUM(( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~4_combout  ) + ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & 
// (\u0|hps_0|fpga_interfaces|h2f_AWADDR [3])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [3]))) ) + ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~14  ))
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~10  = CARRY(( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~4_combout  ) + ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & 
// (\u0|hps_0|fpga_interfaces|h2f_AWADDR [3])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [3]))) ) + ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~14  ))

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~4_combout ),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [3]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [3]),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~14 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~9_sumout ),
        .cout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~10 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~9 .lut_mask = 64'h0000F3C000005555;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y29_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout  = (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ((\u0|hps_0|fpga_interfaces|h2f_AWADDR [3]))) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [3]))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [3]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [3]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6 .lut_mask = 64'h03CF03CF03CF03CF;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y29_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector26~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector26~0_combout  = ( \u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout  & ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~65_sumout  ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout  & ( 
// (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [1]) # ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~9_sumout ) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector28~0_combout )) ) ) ) # ( 
// \u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout  & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~65_sumout  ) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout  & ( (\u0|hps_0|fpga_interfaces|h2f_AWBURST [1] & 
// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector28~0_combout  & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~9_sumout )) ) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [1]),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector28~0_combout ),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~65_sumout ),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~9_sumout ),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector26~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector26~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector26~0 .lut_mask = 64'h00440F0FBBFF0F0F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector26~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y29_N50
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector26~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y29_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~5 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~5_sumout  = SUM(( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [4])) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [4]))) ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~1_combout  ) + ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~10  ))
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~6  = CARRY(( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [4])) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [4]))) ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~1_combout  ) + ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~10  ))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [4]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [4]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~1_combout ),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~10 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~5_sumout ),
        .cout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~6 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~5 .lut_mask = 64'h0000FF0000000C3F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y29_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~9 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~9_sumout  = SUM(( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [4])) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [4]))) ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~1_combout  ) + ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~66  ))
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~10  = CARRY(( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [4])) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [4]))) ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~1_combout  ) + ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~66  ))

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [4]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [4]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~1_combout ),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~66 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~9_sumout ),
        .cout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~10 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~9 .lut_mask = 64'h0000FF0000000A5F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y29_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector25~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector25~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~5_sumout  & ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~9_sumout  & ( (((\u0|hps_0|fpga_interfaces|h2f_AWBURST [1] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|LessThan14~0_combout )) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[4]~5_combout )) # (\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~5_sumout  & ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~9_sumout  & ( ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[4]~5_combout  & ((!\u0|hps_0|fpga_interfaces|h2f_AWBURST [1]) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|LessThan14~0_combout )))) # (\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]) ) ) ) # ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~5_sumout  & ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~9_sumout  & ( (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & (((\u0|hps_0|fpga_interfaces|h2f_AWBURST [1] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|LessThan14~0_combout 
// )) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[4]~5_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~5_sumout  & ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~9_sumout  & ( (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[4]~5_combout  & 
// ((!\u0|hps_0|fpga_interfaces|h2f_AWBURST [1]) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|LessThan14~0_combout )))) ) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [1]),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[4]~5_combout ),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|LessThan14~0_combout ),
        .datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~5_sumout ),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~9_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector25~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector25~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector25~0 .lut_mask = 64'h080C4C0C3B3F7F3F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector25~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y29_N38
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector25~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y29_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~5 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~5_sumout  = SUM(( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~0_combout  ) + ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & 
// (\u0|hps_0|fpga_interfaces|h2f_AWADDR [5])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [5]))) ) + ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~10  ))
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~6  = CARRY(( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~0_combout  ) + ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & 
// (\u0|hps_0|fpga_interfaces|h2f_AWADDR [5])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [5]))) ) + ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~10  ))

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [5]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [5]),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~10 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~5_sumout ),
        .cout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~6 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~5 .lut_mask = 64'h0000F5A0000000FF;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y29_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~17 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~17_sumout  = SUM(( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [6])) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [6]))) ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~3_combout  ) + ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~6  ))
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~18  = CARRY(( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [6])) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [6]))) ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~3_combout  ) + ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~6  ))

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [6]),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~3_combout ),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [6]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~6 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~17_sumout ),
        .cout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~18 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~17 .lut_mask = 64'h0000F0F000002277;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~17 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y29_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector23~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector23~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~17_sumout  & ( ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & 
// (\u0|hps_0|fpga_interfaces|h2f_AWADDR [6])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [6])))) # (\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]) ) 
// ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~17_sumout  & ( (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [6])) 
// # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [6]))))) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [6]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [6]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~17_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector23~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector23~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector23~0 .lut_mask = 64'h207020702F7F2F7F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector23~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y29_N2
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector23~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y29_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~13 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~13_sumout  = SUM(( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~2_combout  ) + ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & 
// (\u0|hps_0|fpga_interfaces|h2f_AWADDR [7])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [7]))) ) + ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~18  ))
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~14  = CARRY(( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~2_combout  ) + ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & 
// (\u0|hps_0|fpga_interfaces|h2f_AWADDR [7])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [7]))) ) + ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~18  ))

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [7]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~2_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [7]),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~18 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~13_sumout ),
        .cout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~14 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~13 .lut_mask = 64'h0000F5A0000000FF;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y29_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector22~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector22~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~13_sumout  & ( ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & 
// (\u0|hps_0|fpga_interfaces|h2f_AWADDR [7])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [7])))) # (\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]) ) 
// ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~13_sumout  & ( (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [7])) 
// # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [7]))))) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [7]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [7]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~13_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector22~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector22~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector22~0 .lut_mask = 64'h082A082A5D7F5D7F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector22~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y29_N8
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[7] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector22~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [7]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y29_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~25 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~25_sumout  = SUM(( GND ) + ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [8])) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [8]))) ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~14  ))
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~26  = CARRY(( GND ) + ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [8])) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [8]))) ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~14  ))

        .dataa(gnd),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [8]),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [8]),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~14 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~25_sumout ),
        .cout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~26 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~25 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~25 .lut_mask = 64'h0000CFC000000000;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~25 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y29_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector21~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector21~0_combout  = ( \u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~25_sumout  ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [8])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & 
// ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [8]))) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [8]),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~25_sumout ),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [8]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector21~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector21~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector21~0 .lut_mask = 64'h227722770F0F0F0F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector21~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y29_N20
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[8] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector21~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [8]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[8] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y29_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~21 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~21_sumout  = SUM(( GND ) + ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [9])) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [9]))) ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~26  ))
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~22  = CARRY(( GND ) + ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [9])) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [9]))) ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~26  ))

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [9]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [9]),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~26 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~21_sumout ),
        .cout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~22 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~21 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~21 .lut_mask = 64'h0000F5A000000000;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~21 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y29_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector20~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector20~0_combout  = ( \u0|hps_0|fpga_interfaces|h2f_AWADDR [9] & ( (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ) 
// # ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [9])))) # (\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & (((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~21_sumout )))) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_AWADDR [9] & ( (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [9])))) # 
// (\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & (((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~21_sumout )))) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~21_sumout ),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [9]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [9]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector20~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector20~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector20~0 .lut_mask = 64'h052705278DAF8DAF;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector20~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y29_N11
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[9] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector20~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [9]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[9] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[9] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y28_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~41 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~41_sumout  = SUM(( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [10])) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [10]))) ) + ( GND ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~22 
//  ))
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~42  = CARRY(( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [10])) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [10]))) ) + ( GND ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~22 
//  ))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [10]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [10]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~22 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~41_sumout ),
        .cout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~42 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~41 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~41 .lut_mask = 64'h0000FFFF00000C3F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~41 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y28_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector19~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector19~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~41_sumout  & ( ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & 
// (\u0|hps_0|fpga_interfaces|h2f_AWADDR [10])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [10])))) # (\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]) 
// ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~41_sumout  & ( (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (\u0|hps_0|fpga_interfaces|h2f_AWADDR 
// [10])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [10]))))) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [10]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [10]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~41_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector19~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector19~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector19~0 .lut_mask = 64'h082A082A5D7F5D7F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector19~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y28_N23
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[10] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector19~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [10]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[10] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[10] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y28_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~37 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~37_sumout  = SUM(( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [11])) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [11]))) ) + ( GND ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~42 
//  ))
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~38  = CARRY(( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [11])) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [11]))) ) + ( GND ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~42 
//  ))

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [11]),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [11]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~42 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~37_sumout ),
        .cout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~38 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~37 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~37 .lut_mask = 64'h0000FFFF00004747;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~37 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y28_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector18~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector18~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~37_sumout  & ( ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & 
// (\u0|hps_0|fpga_interfaces|h2f_AWADDR [11])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [11])))) # (\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]) 
// ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~37_sumout  & ( (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (\u0|hps_0|fpga_interfaces|h2f_AWADDR 
// [11])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [11]))))) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [11]),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [11]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~37_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector18~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector18~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector18~0 .lut_mask = 64'h407040704F7F4F7F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector18~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y28_N8
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[11] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector18~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [11]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[11] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[11] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y28_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~33 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~33_sumout  = SUM(( GND ) + ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [12])) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [12]))) ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~38  ))
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~34  = CARRY(( GND ) + ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [12])) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [12]))) ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~38  ))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [12]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [12]),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~38 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~33_sumout ),
        .cout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~34 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~33 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~33 .lut_mask = 64'h0000F3C000000000;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~33 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y28_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector17~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector17~0_combout  = ( \u0|hps_0|fpga_interfaces|h2f_AWADDR [12] & ( (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ) 
// # ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [12])))) # (\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & (((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~33_sumout )))) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_AWADDR [12] & ( (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [12])))) 
// # (\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & (((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~33_sumout )))) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~33_sumout ),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [12]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [12]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector17~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector17~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector17~0 .lut_mask = 64'h052705278DAF8DAF;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector17~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y28_N20
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[12] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector17~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [12]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[12] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[12] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y28_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~49 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~49_sumout  = SUM(( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [13])) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [13]))) ) + ( GND ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~34 
//  ))
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~50  = CARRY(( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [13])) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [13]))) ) + ( GND ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~34 
//  ))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [13]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [13]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~34 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~49_sumout ),
        .cout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~50 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~49 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~49 .lut_mask = 64'h0000FFFF00000C3F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~49 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y28_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector16~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector16~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [13] & ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~49_sumout  & ( ((\u0|hps_0|fpga_interfaces|h2f_AWADDR [13]) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q )) # (\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]) ) ) ) 
// # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [13] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~49_sumout  & ( ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  
// & \u0|hps_0|fpga_interfaces|h2f_AWADDR [13])) # (\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]) ) ) ) # ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [13] & ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~49_sumout  & ( (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & ((\u0|hps_0|fpga_interfaces|h2f_AWADDR [13]) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ))) ) ) 
// ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [13] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~49_sumout  & ( (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & 
// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & \u0|hps_0|fpga_interfaces|h2f_AWADDR [13])) ) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [13]),
        .datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [13]),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~49_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector16~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector16~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector16~0 .lut_mask = 64'h00A00AAA55F55FFF;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector16~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y28_N53
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[13] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector16~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [13]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[13] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[13] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y28_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~29 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~29_sumout  = SUM(( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [14])) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [14]))) ) + ( GND ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~50 
//  ))
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~30  = CARRY(( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [14])) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [14]))) ) + ( GND ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~50 
//  ))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [14]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [14]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~50 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~29_sumout ),
        .cout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~30 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~29 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~29 .lut_mask = 64'h0000FFFF00000C3F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~29 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y28_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector15~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector15~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~29_sumout  & ( ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & 
// (\u0|hps_0|fpga_interfaces|h2f_AWADDR [14])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [14])))) # (\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]) 
// ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~29_sumout  & ( (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (\u0|hps_0|fpga_interfaces|h2f_AWADDR 
// [14])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [14]))))) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [14]),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [14]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~29_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector15~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector15~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector15~0 .lut_mask = 64'h407040704F7F4F7F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector15~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y28_N2
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[14] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector15~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [14]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[14] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[14] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y28_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~45 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~45_sumout  = SUM(( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [15])) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [15]))) ) + ( GND ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~30 
//  ))
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~46  = CARRY(( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [15])) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [15]))) ) + ( GND ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~30 
//  ))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [15]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [15]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~30 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~45_sumout ),
        .cout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~46 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~45 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~45 .lut_mask = 64'h0000FFFF00000C3F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~45 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y28_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~61 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~61_sumout  = SUM(( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [16])) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [16]))) ) + ( GND ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~46 
//  ))
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~62  = CARRY(( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [16])) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [16]))) ) + ( GND ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~46 
//  ))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [16]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [16]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~46 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~61_sumout ),
        .cout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~62 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~61 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~61 .lut_mask = 64'h0000FFFF00000C3F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~61 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y28_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector13~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector13~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~61_sumout  & ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout  ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~61_sumout  & ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout  & ( !\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] ) ) ) # ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~61_sumout  & ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout  & ( \u0|hps_0|fpga_interfaces|h2f_AWBURST [0] ) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~61_sumout ),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector13~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector13~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector13~0 .lut_mask = 64'h00005555AAAAFFFF;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector13~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y28_N59
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[16] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector13~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [16]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[16] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[16] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y28_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~1_sumout  = SUM(( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [17])) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [17]))) ) + ( GND ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~62 
//  ))
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~2  = CARRY(( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [17])) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [17]))) ) + ( GND ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~62 
//  ))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [17]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [17]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~62 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~1_sumout ),
        .cout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~2 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~1 .lut_mask = 64'h0000FFFF00000C3F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y28_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector12~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector12~0_combout  = ( \u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout  & ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~1_sumout  ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout  ) ) # ( 
// \u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout  & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~1_sumout  ) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~1_sumout ),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector12~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector12~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector12~0 .lut_mask = 64'h00005555FFFF5555;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector12~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y28_N41
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[17] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector12~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [17]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[17] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[17] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y28_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~57 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~57_sumout  = SUM(( GND ) + ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [18])) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [18]))) ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~2  ))
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~58  = CARRY(( GND ) + ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [18])) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [18]))) ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~2  ))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [18]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [18]),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~2 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~57_sumout ),
        .cout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~58 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~57 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~57 .lut_mask = 64'h0000F3C000000000;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~57 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y28_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~53 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~53_sumout  = SUM(( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [19])) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [19]))) ) + ( GND ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~58 
//  ))

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [19]),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [19]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~58 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~53_sumout ),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~53 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~53 .lut_mask = 64'h0000FFFF00004747;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~53 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y28_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector10~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector10~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout  & ( (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~53_sumout ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout  & ( 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~53_sumout  & \u0|hps_0|fpga_interfaces|h2f_AWBURST [0]) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~53_sumout ),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector10~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector10~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector10~0 .lut_mask = 64'h000F000FFF0FFF0F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector10~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y28_N17
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[19] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector10~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [19]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[19] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[19] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y28_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|router|Equal6~5 (
// Equation(s):
// \u0|mm_interconnect_0|router|Equal6~5_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [16] & 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [19]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ( (!\u0|hps_0|fpga_interfaces|h2f_AWADDR [19] & \u0|hps_0|fpga_interfaces|h2f_AWADDR 
// [16]) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [16]),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [19]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [19]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [16]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router|Equal6~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router|Equal6~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router|Equal6~5 .lut_mask = 64'h00F000F044444444;
defparam \u0|mm_interconnect_0|router|Equal6~5 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y28_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|src_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|src_valid~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~3_combout  & ( \u0|mm_interconnect_0|router|Equal7~1_combout  & ( (\u0|mm_interconnect_0|router|Equal6~5_combout 
//  & (\u0|mm_interconnect_0|cmd_demux|src7_valid~0_combout  & (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|router|Equal6~5_combout ),
        .datab(!\u0|mm_interconnect_0|cmd_demux|src7_valid~0_combout ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout ),
        .datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~3_combout ),
        .dataf(!\u0|mm_interconnect_0|router|Equal7~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_007|src_valid~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|src_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|src_valid~0 .lut_mask = 64'h0000000000000001;
defparam \u0|mm_interconnect_0|cmd_mux_007|src_valid~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y29_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout  = ( \u0|mm_interconnect_0|cmd_mux_007|src_valid~0_combout  & ( 
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  ) ) # ( !\u0|mm_interconnect_0|cmd_mux_007|src_valid~0_combout  & ( (!\u0|mm_interconnect_0|cmd_mux_007|src_valid~1_combout ) # 
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_007|src_valid~1_combout ),
        .datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_007|src_valid~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .lut_mask = 64'hFFF0FFF0FF00FF00;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y30_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18_combout  = ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & ( 
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) # ((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ) 
// # (((!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & !\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1])) # (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ))) ) ) # ( 
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & ( ((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ) # 
// ((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & 
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datae(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
        .datag(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18 .extended_lut = "on";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18 .lut_mask = 64'hFFECFF00FFFFFF03;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y30_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1_combout  = ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1 .lut_mask = 64'hFFFFFFFF00000000;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y30_N8
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y30_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout  = ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( 
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .lut_mask = 64'hF0F0F0F000000000;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y30_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout  = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// \u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & ( ((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q )) # (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) ) ) # ( 
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( \u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & ( 
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & ((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ) # 
// ((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout )))) ) ) ) # ( 
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( !\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & ( 
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  ) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),
        .datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .datae(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .lut_mask = 64'h0000555533107755;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y30_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout  = ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout  & ( 
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout  & (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// !\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),
        .datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16 .lut_mask = 64'h0300030000000000;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y30_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout  = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & 
// ((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) # (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout )))) 
// ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & 
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .lut_mask = 64'h0050005010501050;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y30_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout  = ( 
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg 
// [2]))) # (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) 
// ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .lut_mask = 64'h00FF00FFFC30FC30;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y30_N41
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on

// Location: FF_X23_Y30_N35
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y30_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout  = ( 
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] $ 
// (((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))))) # 
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) 
// # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .lut_mask = 64'h00FF00FFB874B874;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y30_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout  = ( 
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout  & ( 
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout  & 
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
        .datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0 .lut_mask = 64'hF000F00000000000;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y30_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  = (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ))

        .dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .lut_mask = 64'h0500050005000500;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y30_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17_combout  = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout  & ( 
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout  & ( 
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  ) ) # ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout  & ( 
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  & ( ((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout  & 
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout  & 
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ))) # 
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout ) ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout  & ( 
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  & ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout  ) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout ),
        .datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),
        .datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),
        .datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ),
        .datae(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17 .lut_mask = 64'h55557555FFFFFFFF;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y30_N2
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y29_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout  = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q  & 
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q )) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & 
// ((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ) # (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h00A800A800880088;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y29_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout  = ( !\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & ( (!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]) # 
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .lut_mask = 64'hF0FFF0FF00000000;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y29_N17
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y27_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|src_data[35] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|src_data [35] = ( \u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & ( (\u0|hps_0|fpga_interfaces|h2f_WSTRB [3]) # (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]) ) ) # ( 
// !\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & ( \u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [3]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_007|src_data [35]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[35] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[35] .lut_mask = 64'h555555555F5F5F5F;
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[35] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y27_N56
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_007|src_data [35]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y27_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|src_data[33] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|src_data [33] = ( \u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] ) # ( !\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & ( (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_WSTRB 
// [1]) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_007|src_data [33]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[33] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[33] .lut_mask = 64'h000F000FFFFFFFFF;
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[33] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y27_N5
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_007|src_data [33]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y27_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|src_data[34] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|src_data [34] = ( \u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & ( (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]) # (\u0|hps_0|fpga_interfaces|h2f_WSTRB [2]) ) ) # ( 
// !\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & ( \u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [2]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_007|src_data [34]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[34] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[34] .lut_mask = 64'h00FF00FF55FF55FF;
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[34] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y27_N41
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_007|src_data [34]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y29_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~2_combout  = ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & ( 
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & 
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1])) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~2 .lut_mask = 64'h8080808000000000;
defparam \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y27_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|src_data[88] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|src_data [88] = ( \u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & ( ((\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [2])) # (\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]) ) ) # ( 
// !\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & ( (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_007|src_data [88]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[88] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[88] .lut_mask = 64'h005500550F5F0F5F;
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[88] .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y27_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|src_data[87] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|src_data [87] = ( \u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & ( ((\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1])) # (\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]) ) ) # ( 
// !\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & ( (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_007|src_data [87]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[87] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[87] .lut_mask = 64'h0505050505FF05FF;
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[87] .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y27_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout  = ( !\u0|mm_interconnect_0|cmd_mux_007|src_data [87] & ( !\u0|mm_interconnect_0|cmd_mux_007|src_data [88] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_007|src_data [88]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_007|src_data [87]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .lut_mask = 64'hCCCCCCCC00000000;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y27_N20
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y29_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~3 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~3_combout  = ( \u0|mm_interconnect_0|link_start_s1_agent|local_write~0_combout  & ( (!\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~2_combout  & 
// (!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0] & (\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0_combout ))) # (\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~2_combout  & 
// ((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ) # ((!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0] & 
// \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0_combout )))) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent|local_write~0_combout  & ( (!\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~2_combout  & 
// (\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0] & (\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0_combout ))) # (\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~2_combout  & 
// ((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ) # ((\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0] & 
// \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0_combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~2_combout ),
        .datab(!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0]),
        .datac(!\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0_combout ),
        .datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_agent|local_write~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~3 .lut_mask = 64'h570357035D0C5D0C;
defparam \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~3 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y29_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q  & (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// ((!\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~3_combout ) # (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1])))) ) ) # ( 
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// ((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ) # ((!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~3_combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),
        .datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .datac(!\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~3_combout ),
        .datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .lut_mask = 64'h00CE00CE00C400C4;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y29_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout  & ( 
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout  & ( 
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  & ( (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout  & 
// (!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & ((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) # (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0])))) # 
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout  & (((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) # 
// (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]))) ) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
        .datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
        .datae(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .lut_mask = 64'hF351FFFF00000000;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y28_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout  = ( 
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout  & ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  
// ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout  & ( 
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  ) ) # ( 
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout  & ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout 
//  & ( (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout  & 
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout  & 
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout  & 
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout ),
        .datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ),
        .datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),
        .datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ),
        .datae(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .lut_mask = 64'h00008000FFFFFFFF;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y28_N8
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y29_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  = ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( 
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & (((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & 
// ((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))))) ) ) # ( 
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( ((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # 
// ((\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~1_combout  & (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )))) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datab(!\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~1_combout ),
        .datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datag(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .extended_lut = "on";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .lut_mask = 64'h0A0AF0F30000F0F3;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y29_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// ( (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ) 
// # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'h050005000F000F00;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y29_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout  = ( \u0|mm_interconnect_0|cmd_mux_007|src_valid~0_combout  & ( 
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & ((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) # 
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ))) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_007|src_valid~0_combout  & ( 
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & (\u0|mm_interconnect_0|cmd_mux_007|src_valid~1_combout  & 
// ((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) # (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_007|src_valid~1_combout ),
        .datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_007|src_valid~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h0105010511551155;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y29_N59
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y29_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|local_write~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent|local_write~0_combout  = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & ( 
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_agent|local_write~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|local_write~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent|local_write~0 .lut_mask = 64'h0000000000FF00FF;
defparam \u0|mm_interconnect_0|link_start_s1_agent|local_write~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y29_N32
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][129] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][129]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y29_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~0_combout  = ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][129]~q  & ( 
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( (((\u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout  & \u0|mm_interconnect_0|link_start_s1_agent|m0_read~0_combout )) # 
// (\u0|mm_interconnect_0|link_start_s1_agent|local_write~0_combout )) # (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][129]~q  & ( 
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & (((\u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout  
// & \u0|mm_interconnect_0|link_start_s1_agent|m0_read~0_combout )) # (\u0|mm_interconnect_0|link_start_s1_agent|local_write~0_combout ))) ) ) ) # ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][129]~q  & ( 
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( ((\u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout  & \u0|mm_interconnect_0|link_start_s1_agent|m0_read~0_combout )) # 
// (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][129]~q  & ( 
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout  
// & \u0|mm_interconnect_0|link_start_s1_agent|m0_read~0_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),
        .datab(!\u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout ),
        .datac(!\u0|mm_interconnect_0|link_start_s1_agent|local_write~0_combout ),
        .datad(!\u0|mm_interconnect_0|link_start_s1_agent|m0_read~0_combout ),
        .datae(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][129]~q ),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~0 .lut_mask = 64'h002255770A2A5F7F;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y29_N44
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][129] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][129]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y29_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|rp_valid (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout  = ( !\u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg [0] & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [0] & 
// ((!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][129]~q ) # (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [0]))) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datab(!\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [0]),
        .datac(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|rp_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent|rp_valid .lut_mask = 64'hC8C8C8C800000000;
defparam \u0|mm_interconnect_0|link_start_s1_agent|rp_valid .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y29_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|src_data[110] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|src_data [110] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [5] & ( ((\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [5])) # (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_ARID [5] & ( (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [5]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [5]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_007|src_data [110]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[110] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[110] .lut_mask = 64'h0303030357575757;
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[110] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y29_N52
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_007|src_data [110]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .power_up = "low";
// synopsys translate_on

// Location: FF_X18_Y29_N56
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~15_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][110]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][110] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y29_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~15 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~15_combout  = (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110])) 
// # (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][110]~q )))

        .dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][110]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~15 .lut_mask = 64'h505F505F505F505F;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~15 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y29_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][110]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][110]~feeder_combout  = ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~15_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~15_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][110]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][110]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][110]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][110]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y29_N5
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][110]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][110]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][110] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y33_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_013|src_payload~5 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_013|src_payload~5_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [5] & ( \u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_013|src_payload~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~5 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y33_N50
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_013|src_payload~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .power_up = "low";
// synopsys translate_on

// Location: FF_X18_Y33_N5
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~14_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][110]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][110] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y33_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~14 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~14_combout  = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][110]~q  ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110] ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][110]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~14 .lut_mask = 64'h5555555500FF00FF;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~14 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y31_N23
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~14_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][110]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][110] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y31_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~136 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~136_combout  = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout  & ( (!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout  & 
// (!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout  & \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][110]~q )) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout  & ( 
// ((!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout  & (!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout  & \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][110]~q ))) # 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][110]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout ),
        .datab(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ),
        .datac(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][110]~q ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][110]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~136_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~136 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~136 .lut_mask = 64'h08FF08FF08080808;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~136 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y31_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~137 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~137_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout  & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~136_combout  & 
// ((!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][110]~q ) # (!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ))) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][110]~q  & (!\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~136_combout  & ((!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][110]~q ) # 
// (!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][110]~q ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][110]~q ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ),
        .datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~136_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~137_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~137 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~137 .lut_mask = 64'hC800C800FA00FA00;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~137 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y22_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|src_data[110] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|src_data [110] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [5] & ( ((\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [5])) # (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_ARID [5] & ( (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [5]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [5]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_009|src_data [110]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[110] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[110] .lut_mask = 64'h0303030357575757;
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[110] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y22_N41
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_009|src_data [110]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .power_up = "low";
// synopsys translate_on

// Location: FF_X15_Y22_N17
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~15_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][110]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][110] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y22_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~15 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~15_combout  = (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg 
// [110])) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][110]~q )))

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][110]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~15 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~15 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y24_N35
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~15_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][110]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][110] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y24_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~140 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~140_combout  = ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][110]~q  & ( ((\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout  & 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][110]~q )) # (\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout ) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][110]~q  & ( 
// (\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout  & \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][110]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][110]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][110]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~140_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~140 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~140 .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~140 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y32_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_021|src_payload~5 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_021|src_payload~5_combout  = (\u0|hps_0|fpga_interfaces|h2f_ARID [5] & \u0|mm_interconnect_0|cmd_mux_021|saved_grant [1])

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [5]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_021|src_payload~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~5 .lut_mask = 64'h000F000F000F000F;
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y32_N56
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_021|src_payload~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .power_up = "low";
// synopsys translate_on

// Location: FF_X27_Y32_N8
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~14_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][110]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][110] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y32_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~14 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~14_combout  = (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110])) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & 
// ((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][110]~q )))

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][110]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~14 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~14 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y32_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][110]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][110]~feeder_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~14_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~14_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][110]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][110]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][110]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][110]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y32_N25
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][110]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][110]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][110] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y32_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_019|src_payload~5 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_019|src_payload~5_combout  = (\u0|hps_0|fpga_interfaces|h2f_ARID [5] & \u0|mm_interconnect_0|cmd_mux_019|saved_grant [1])

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [5]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_019|src_payload~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~5 .lut_mask = 64'h000F000F000F000F;
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y32_N11
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_019|src_payload~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .power_up = "low";
// synopsys translate_on

// Location: FF_X22_Y32_N53
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~14_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][110]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][110] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y32_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~14 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~14_combout  = (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110])) # 
// (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][110]~q )))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][110]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~14 .lut_mask = 64'h0C3F0C3F0C3F0C3F;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~14 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y32_N26
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~14_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][110]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][110] .power_up = "low";
// synopsys translate_on

// Location: FF_X18_Y28_N29
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~15_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][110]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][110] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y25_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_data[110] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|src_data [110] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [5] & ( ((\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [5])) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_ARID [5] & ( (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [5]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [5]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_008|src_data [110]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[110] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[110] .lut_mask = 64'h0505050537373737;
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[110] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y25_N22
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_008|src_data [110]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y28_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~15 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~15_combout  = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110] & ( (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used 
// [1]) # (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][110]~q ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110] & ( 
// (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][110]~q ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][110]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~15 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~15 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y28_N32
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~15_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][110]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][110] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y32_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~138 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~138_combout  = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][110]~q  & ( (!\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout  & 
// ((!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ) # ((!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout  & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][110]~q )))) # 
// (\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout  & (!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout  & ((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][110]~q )))) ) ) # ( 
// !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][110]~q  & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout  & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][110]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout ),
        .datac(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][110]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][110]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~138_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~138 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~138 .lut_mask = 64'h00CC00CCA0ECA0EC;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~138 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y32_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_020|src_payload~5 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_020|src_payload~5_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [5] & ( \u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_020|src_payload~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~5 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y32_N32
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_020|src_payload~5_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .power_up = "low";
// synopsys translate_on

// Location: FF_X23_Y32_N41
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~14_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][110]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][110] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y32_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~14 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~14_combout  = (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110])) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & 
// ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][110]~q )))

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][110]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~14 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~14 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y32_N53
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~14_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][110]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][110] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y32_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~139 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~139_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout  & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~138_combout  & 
// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][110]~q ) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ))) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout  & ( 
// (!\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~138_combout  & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][110]~q  & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][110]~q ) # 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][110]~q ),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ),
        .datac(!\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~138_combout ),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][110]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~139_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~139 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~139 .lut_mask = 64'hB000B000B0B0B0B0;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~139 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y26_N56
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~15_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][110]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][110] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y26_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|src_data[110] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|src_data [110] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [5] & ( \u0|hps_0|fpga_interfaces|h2f_AWID [5] & ( (\u0|mm_interconnect_0|cmd_mux|saved_grant [0]) # (\u0|mm_interconnect_0|cmd_mux|saved_grant [1]) ) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_ARID [5] & ( \u0|hps_0|fpga_interfaces|h2f_AWID [5] & ( \u0|mm_interconnect_0|cmd_mux|saved_grant [0] ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_ARID [5] & ( !\u0|hps_0|fpga_interfaces|h2f_AWID [5] & ( 
// \u0|mm_interconnect_0|cmd_mux|saved_grant [1] ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
        .datad(gnd),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_ARID [5]),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux|src_data [110]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|src_data[110] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|src_data[110] .lut_mask = 64'h000033330F0F3F3F;
defparam \u0|mm_interconnect_0|cmd_mux|src_data[110] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y26_N1
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux|src_data [110]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y26_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~15 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~15_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][110]~q  & ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg 
// [110] ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][110]~q  & ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110] & ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] ) ) ) # ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][110]~q  & ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110] & ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][110]~q ),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~15 .lut_mask = 64'h00000F0FF0F0FFFF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~15 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y26_N23
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~15_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][110]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][110] .power_up = "low";
// synopsys translate_on

// Location: FF_X11_Y24_N17
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~14_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][110]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][110] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y24_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_001|src_payload~5 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_001|src_payload~5_combout  = ( \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [5] ) )

        .dataa(gnd),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARID [5]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_001|src_payload~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~5 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y24_N31
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_001|src_payload~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y24_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~14 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~14_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][110]~q  & ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg 
// [110] ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][110]~q  & ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110] & ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] ) ) ) # ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][110]~q  & ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110] & ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][110]~q ),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~14 .lut_mask = 64'h00005555AAAAFFFF;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~14 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y26_N44
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~14_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][110]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][110] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y27_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_002|src_payload~5 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_002|src_payload~5_combout  = (\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [5])

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [5]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_002|src_payload~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~5 .lut_mask = 64'h0303030303030303;
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y27_N14
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_002|src_payload~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .power_up = "low";
// synopsys translate_on

// Location: FF_X10_Y27_N50
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~14_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][110]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][110] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y27_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~14 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~14_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][110]~q  & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] ) ) # ( 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][110]~q  & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & ( 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110] ) ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][110]~q  & ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
        .datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][110]~q ),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~14 .lut_mask = 64'h00FF00FF0000FFFF;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~14 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y27_N59
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~14_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][110]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][110] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y27_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~44 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~44_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][110]~q  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][110]~q  & (((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q  & 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0])) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0]),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][110]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~44_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~44 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~44 .lut_mask = 64'h0037003700FF00FF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~44 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y26_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~143 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~143_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][110]~q  & ( !\u0|mm_interconnect_0|rsp_mux_001|src_payload~44_combout  & ( 
// (\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout  & ((!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][110]~q ) # ((\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ) # 
// (\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][110]~q  & ( !\u0|mm_interconnect_0|rsp_mux_001|src_payload~44_combout  & ( 
// (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][110]~q ) # ((\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ) # (\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][110]~q ),
        .datab(!\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ),
        .datae(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][110]~q ),
        .dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~44_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~143_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~143 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~143 .lut_mask = 64'hBFBF00BF00000000;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~143 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y30_N23
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~14_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][110]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][110] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y30_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_012|src_payload~5 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_012|src_payload~5_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [5] & ( \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_012|src_payload~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~5 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y30_N37
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_012|src_payload~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y30_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~14 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~14_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110] & ( 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][110]~q ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110] & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][110]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][110]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~14 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~14 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y30_N58
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~14_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][110]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][110] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y33_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_003|src_payload~5 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_003|src_payload~5_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [5] & ( \u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_003|src_payload~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~5 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y33_N17
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_003|src_payload~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .power_up = "low";
// synopsys translate_on

// Location: FF_X17_Y33_N20
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~14_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][110]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][110] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y33_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~14 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~14_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][110]~q  ) ) # ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][110]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~14 .lut_mask = 64'h3333333300FF00FF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~14 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y30_N41
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~14_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][110]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][110] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y33_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_006|src_payload~5 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_006|src_payload~5_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [5] & ( \u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_006|src_payload~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~5 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y33_N47
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_006|src_payload~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .power_up = "low";
// synopsys translate_on

// Location: FF_X14_Y33_N20
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~14_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][110]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][110] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y33_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~14 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~14_combout  = (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110])) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & 
// ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][110]~q )))

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][110]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~14 .lut_mask = 64'h2277227722772277;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~14 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y33_N11
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~14_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][110]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][110] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y33_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~45 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~45_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][110]~q  & 
// (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q )) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]))) ) ) 
// # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][110]~q  & ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][110]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~45_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~45 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~45 .lut_mask = 64'h005F005F007F007F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~45 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y30_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_005|src_payload~5 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_005|src_payload~5_combout  = ( \u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [5] ) )

        .dataa(gnd),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARID [5]),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_005|src_payload~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~5 .lut_mask = 64'h0000333300003333;
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y30_N26
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_005|src_payload~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .power_up = "low";
// synopsys translate_on

// Location: FF_X11_Y30_N56
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~14_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][110]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][110] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y30_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~14 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~14_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][110]~q  ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][110]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~14 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~14 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y30_N53
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~14_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][110]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][110] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y26_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|src_data[110] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|src_data [110] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [5] & ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & ( (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]) # (\u0|hps_0|fpga_interfaces|h2f_AWID [5]) ) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_ARID [5] & ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_AWID [5] ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_ARID [5] & ( !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & ( 
// \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] ) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_AWID [5]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_ARID [5]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_004|src_data [110]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[110] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[110] .lut_mask = 64'h0000333355557777;
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[110] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y26_N19
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_004|src_data [110]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .power_up = "low";
// synopsys translate_on

// Location: FF_X22_Y26_N5
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~15_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][110]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][110] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y26_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~15 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~15_combout  = (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110])) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & 
// ((\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][110]~q )))

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][110]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~15 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~15 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y26_N32
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~15_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][110]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][110] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y30_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~144 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~144_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][110]~q  & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][110]~q  & ( 
// (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~45_combout  & (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout  & ((\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ) # 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout )))) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][110]~q  & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][110]~q  & ( 
// (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~45_combout  & ((\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ))) ) ) ) # ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][110]~q  & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][110]~q  & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~45_combout  & 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout ) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][110]~q  & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][110]~q  & ( 
// !\u0|mm_interconnect_0|rsp_mux_001|src_payload~45_combout  ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~45_combout ),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ),
        .datac(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout ),
        .datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][110]~q ),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][110]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~144_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~144 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~144 .lut_mask = 64'hAAAA00AA2A2A002A;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~144 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y30_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~145 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~145_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][110]~q  & ( \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~144_combout  & ( 
// (\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout  & (\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~143_combout  & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][110]~q ) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout )))) ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][110]~q  & ( \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~144_combout  & ( 
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~143_combout  & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][110]~q ) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout ),
        .datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~143_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout ),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][110]~q ),
        .datae(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][110]~q ),
        .dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~144_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~145_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~145 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~145 .lut_mask = 64'h0000000033031101;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~145 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y23_N17
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~15_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][110]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][110] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y23_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|src_data[110] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|src_data [110] = ( \u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & ( ((\u0|hps_0|fpga_interfaces|h2f_AWID [5] & \u0|mm_interconnect_0|cmd_mux_011|saved_grant [0])) # (\u0|hps_0|fpga_interfaces|h2f_ARID [5]) ) ) # ( 
// !\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_AWID [5] & \u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_AWID [5]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [5]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_011|src_data [110]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[110] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[110] .lut_mask = 64'h0505050505FF05FF;
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[110] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y23_N22
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_011|src_data [110]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y23_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~15 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~15_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110] & ( (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used 
// [1]) # (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][110]~q ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110] & ( 
// (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][110]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][110]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~15 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~15 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y23_N58
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~15_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][110]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][110] .power_up = "low";
// synopsys translate_on

// Location: FF_X23_Y23_N2
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~15_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][110]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][110] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y24_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_data[110] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_data [110] = ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_AWID [5] ) ) # ( !\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_AWID [5] & ( 
// (\u0|hps_0|fpga_interfaces|h2f_ARID [5] & \u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & ( !\u0|hps_0|fpga_interfaces|h2f_AWID [5] & ( (\u0|hps_0|fpga_interfaces|h2f_ARID [5] & 
// \u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & ( !\u0|hps_0|fpga_interfaces|h2f_AWID [5] & ( (\u0|hps_0|fpga_interfaces|h2f_ARID [5] & \u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]) ) 
// ) )

        .dataa(gnd),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARID [5]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_014|src_data [110]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[110] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[110] .lut_mask = 64'h030303030303FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[110] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y24_N2
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_014|src_data [110]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y23_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~15 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~15_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110] & ( 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][110]~q ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110] & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][110]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][110]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~15 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~15 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y23_N53
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~15_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][110]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][110] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y23_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~141 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~141_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][110]~q  & ( ((\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout  & 
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][110]~q )) # (\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][110]~q  & ( 
// (\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout  & \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][110]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout ),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][110]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][110]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~141_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~141 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~141 .lut_mask = 64'h005500550F5F0F5F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~141 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y26_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_data[110] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|src_data [110] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [5] & ( ((\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [5])) # (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_AWID [5] & ( (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [5]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
        .datac(gnd),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [5]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_018|src_data [110]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[110] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[110] .lut_mask = 64'h0033003355775577;
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[110] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y26_N32
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_018|src_data [110]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .power_up = "low";
// synopsys translate_on

// Location: FF_X30_Y26_N23
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~15_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][110]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][110] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y26_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~15 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~15_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][110]~q  ) ) # ( 
// !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][110]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~15 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~15 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y26_N8
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~15_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][110]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][110] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y22_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_data[110] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|src_data [110] = ( \u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & ( ((\u0|hps_0|fpga_interfaces|h2f_AWID [5] & \u0|mm_interconnect_0|cmd_mux_015|saved_grant [0])) # (\u0|hps_0|fpga_interfaces|h2f_ARID [5]) ) ) # ( 
// !\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_AWID [5] & \u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARID [5]),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [5]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_015|src_data [110]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[110] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[110] .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[110] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y22_N41
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_015|src_data [110]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .power_up = "low";
// synopsys translate_on

// Location: FF_X19_Y22_N47
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~15_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][110]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][110] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y22_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~15 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~15_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][110]~q  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][110]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~15 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~15 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y26_N26
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~15_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][110]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][110] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y26_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~142 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~142_combout  = ( \u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout  & ( ((\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout  & 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][110]~q )) # (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][110]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout  & ( 
// (\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout  & \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][110]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][110]~q ),
        .datac(!\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][110]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~142_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~142 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~142 .lut_mask = 64'h000F000F333F333F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~142 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y28_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[110] (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data [110] = ( \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~141_combout  & ( \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~142_combout  ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~141_combout  & ( 
// \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~142_combout  ) ) # ( \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~141_combout  & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~142_combout  ) ) # ( 
// !\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~141_combout  & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~142_combout  & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~137_combout ) # 
// (((!\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~139_combout ) # (!\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~145_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~140_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~137_combout ),
        .datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~140_combout ),
        .datac(!\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~139_combout ),
        .datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~145_combout ),
        .datae(!\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~141_combout ),
        .dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~142_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data [110]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110] .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110] .lut_mask = 64'hFFFBFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110] .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y27_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~4 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~4_combout  = ( \u0|hps_0|fpga_interfaces|h2f_AWLEN [0] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ) # 
// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount [2]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_AWLEN [0] & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount [2]) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount [2]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~4 .lut_mask = 64'h0F000F00FFF0FFF0;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y20_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout  = (!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] & (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & 
// ((!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0])))) # (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~4_combout ) # ((\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & 
// !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]))))

        .dataa(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~4_combout ),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 .lut_mask = 64'h7350735073507350;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y20_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout  = ( 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout  & ( (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg 
// [2] $ (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) 
// ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout  & ( 
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] $ 
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 .lut_mask = 64'h0AA00AA05FF55FF5;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y20_N53
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y20_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3_combout  & ( 
// ((\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout )) # (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]) ) ) # ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3_combout  & ( (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5 .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y20_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout  = ( 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout  & ( 
// ((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) # 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]) ) ) ) # ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout  & ( 
// ((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) # 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) ) # ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & 
// ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout  & ( 
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) ) ) # ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout  & ( 
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datae(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6 .lut_mask = 64'h00A0F0500FAFFF5F;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y20_N56
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y20_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] $ (((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg 
// [2] & !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]))) ) ) # ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .lut_mask = 64'hCCCCCCCC3CCC3CCC;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y20_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  & 
// ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout  & ( (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] 
// & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) # (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]))) ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  & ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout  & ( ((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # ((\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] 
// & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ))) # (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]) ) ) ) # ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  & ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout  & ( (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  & ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout  & ( (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # ((\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] 
// & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),
        .datae(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .lut_mask = 64'hF0F30003F5F70507;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y20_N14
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y20_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  = ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & ( 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] & 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .lut_mask = 64'h3000300000000000;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y20_N8
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y20_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout  = ( \u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] & ( ((\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout )) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~1_combout ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] & ( 
// (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 .lut_mask = 64'h0303030303FF03FF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y20_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout  = ( 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout  & ( (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  
// $ (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) 
// # ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout  & ( 
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  $ 
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 .lut_mask = 64'h50A050A05FAF5FAF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y23_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout  = ( \u0|mm_interconnect_0|cmd_mux_011|src_valid~1_combout  & ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  ) ) # ( !\u0|mm_interconnect_0|cmd_mux_011|src_valid~1_combout  & ( 
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) # (!\u0|mm_interconnect_0|cmd_mux_011|src_valid~0_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|cmd_mux_011|src_valid~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_011|src_valid~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .lut_mask = 64'hFFAAFFAAAAAAAAAA;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y20_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18_combout  = ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & ( 
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ) # ((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout 
// ) # (((!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] & !\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1])) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ))) ) ) # ( 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & ( (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ) # 
// (((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datae(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
        .datag(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18 .extended_lut = "on";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18 .lut_mask = 64'hFFEAAAAAFFFFAAAF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y20_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1_combout  = ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1 .lut_mask = 64'hFFFFFFFF00000000;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y20_N23
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";
// synopsys translate_on

// Location: FF_X21_Y23_N32
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_011|src_payload [0]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y20_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q )) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// ((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) # (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q )))) ) 
// )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h4440444044004400;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y20_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|src_data[32] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|src_data [32] = ((\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_WSTRB [0])) # (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1])

        .dataa(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_011|src_data [32]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[32] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[32] .lut_mask = 64'h5757575757575757;
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[32] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y20_N32
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_011|src_data [32]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y20_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|src_data[35] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|src_data [35] = ( \u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_WSTRB [3] ) ) # ( !\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_WSTRB [3] & ( 
// \u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] & ( !\u0|hps_0|fpga_interfaces|h2f_WSTRB [3] & ( \u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] ) ) ) # ( 
// !\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] & ( !\u0|hps_0|fpga_interfaces|h2f_WSTRB [3] & ( \u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_011|src_data [35]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[35] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[35] .lut_mask = 64'h555555555555FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[35] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y20_N11
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_011|src_data [35]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y20_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|src_data[34] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|src_data [34] = ( \u0|hps_0|fpga_interfaces|h2f_WSTRB [2] & ( (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]) # (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_WSTRB [2] & ( 
// \u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_011|src_data [34]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[34] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[34] .lut_mask = 64'h555555555F5F5F5F;
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[34] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y20_N47
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_011|src_data [34]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y20_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|src_data[33] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|src_data [33] = ( \u0|hps_0|fpga_interfaces|h2f_WSTRB [1] & ( (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]) # (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_WSTRB [1] & ( 
// \u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
        .datad(gnd),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [1]),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_011|src_data [33]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[33] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[33] .lut_mask = 64'h55555F5F55555F5F;
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[33] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y20_N17
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_011|src_data [33]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y20_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~2_combout  = ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & ( 
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~2 .lut_mask = 64'hC000C00000000000;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y20_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~3 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~3_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_agent|local_write~0_combout  & ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q  & ( 
// (!\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [0] & \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~0_combout ) ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|local_write~0_combout  & ( 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q  & ( (\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [0] & 
// \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~0_combout ) ) ) ) # ( \u0|mm_interconnect_0|write_en_tx_s1_agent|local_write~0_combout  & ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q  & ( ((!\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [0] & 
// \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~0_combout )) # (\u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~2_combout ) ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|local_write~0_combout  & ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q  & ( ((\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [0] & 
// \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~0_combout )) # (\u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~2_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [0]),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~0_combout ),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~2_combout ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|write_en_tx_s1_agent|local_write~0_combout ),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~3 .lut_mask = 64'h1F1F2F2F11112222;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y20_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q  & ( 
// (\u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~3_combout  & (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q 
//  & !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q  & 
// ( (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ((!\u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~3_combout ) # 
// ((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1])))) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~3_combout ),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .lut_mask = 64'h0F0B0F0B04000400;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y20_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout  & ( 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  ) ) ) # ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout  & ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( 
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  & (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] & ((!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]) # 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout )))) ) ) ) # ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout  & ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  ) ) ) # ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout  & ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( 
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  & ((!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]) # 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
        .datae(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .lut_mask = 64'hC4C4CCCC00C4CCCC;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y20_N41
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y21_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout  = (!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] & (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ))) # (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] & (((\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout )) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~0_combout )))

        .dataa(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~0_combout ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .lut_mask = 64'h0357035703570357;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y20_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout  = ( 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout  & ( ((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout 
// ) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) 
// ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout  & ( 
// ((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout )) # 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) ) # ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & 
// ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout  & ( 
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ) # 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) ) ) ) # ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout  & ( (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q 
//  & (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .datae(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 .lut_mask = 64'h00A0AA0A55F5FF5F;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y20_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout  = ( 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout  & ( 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout  & ( 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  ) ) ) # ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout  & ( 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout  & ( 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  ) ) ) # ( 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout  & ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout  & ( 
// ((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout  & 
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout  & 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ))) # 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) ) # ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout  & ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout  & ( 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  ) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout ),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),
        .datae(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .lut_mask = 64'h0F0F8F0F0F0F0F0F;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y20_N20
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y20_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~1_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [0] & ( (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & 
// (((!\u0|mm_interconnect_0|write_en_tx_s1_agent|local_write~0_combout  & \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~0_combout )) # (\u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0_combout ))) ) ) # ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [0] & ( (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & (((\u0|mm_interconnect_0|write_en_tx_s1_agent|local_write~0_combout  & 
// \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~0_combout )) # (\u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent|local_write~0_combout ),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0_combout ),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~1 .lut_mask = 64'h3070307030B030B0;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y20_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~1_combout  & ( 
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ))) # 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) # ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~1_combout  & ( (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// ((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ))) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q )) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .lut_mask = 64'h11DD11DD03CF03CF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y20_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout  = ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & (((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout )) # 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h0057005700000000;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y20_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout  = ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & ( 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) 
// ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h000F000F00000000;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y20_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout  = ( 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout  & ( 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout  & ( 
// ((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout  & ((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ) # 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout )))) # 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h5F1F5F1F5F5F5F5F;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y20_N2
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y20_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & ( 
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  $ 
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))) # 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  
// & ( (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .lut_mask = 64'hC000C0003CC03CC0;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y20_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  & ( 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout )) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  & 
// ( (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & ((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) 
// # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .lut_mask = 64'h003F003F00300030;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y20_N41
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y20_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout  & ( 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .lut_mask = 64'hFFFFFFFF0F000F00;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y20_N47
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y20_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~1_combout  & ( 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y20_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout  = ( 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) # 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) 
// ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) # 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q 
// ))) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .lut_mask = 64'h55BB55BB44AA44AA;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y20_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout  = ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout  & ( 
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout  & 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0 .lut_mask = 64'hF000F00000000000;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y20_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout  = ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .lut_mask = 64'hF0F0F0F000000000;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y20_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & ( 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  ) ) ) # 
// ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// ((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & \u0|mm_interconnect_0|cmd_mux_011|saved_grant [0])) # 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) ) ) # ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] & (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout  & 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// \u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]) ) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datae(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .lut_mask = 64'h1111001011FF00FF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y20_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout  = ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout  & ( 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & (!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16 .lut_mask = 64'h0050005000000000;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y20_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & ( 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) 
// )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .lut_mask = 64'h0000000030303030;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y20_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & ( 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & 
// ((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) # 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) ) ) # ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & ( (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .lut_mask = 64'h1010101010501050;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y20_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout  & ( 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout  & ( 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout ) ) ) ) # ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout  & ( 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout  & ( 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout ) ) ) ) # ( 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout  & ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout  & ( 
// (((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout  & 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout )) # 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout )) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout ) ) ) ) # ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout  & ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout  & ( 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout ),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),
        .datae(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17 .lut_mask = 64'h3F3F7F3F3F3F3F3F;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y20_N14
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y23_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  = ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( 
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & 
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))))) ) ) # ( 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( ((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # 
// ((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((\u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~1_combout ))))) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datae(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~1_combout ),
        .datag(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .extended_lut = "on";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .lut_mask = 64'h0A00F0F00A00F3F3;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y23_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|update_grant~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|update_grant~0_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & ( \u0|mm_interconnect_0|cmd_mux_011|src_valid~1_combout  & ( 
// \u0|mm_interconnect_0|cmd_mux_011|src_payload [0] ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & ( \u0|mm_interconnect_0|cmd_mux_011|src_valid~1_combout  & ( 
// (\u0|mm_interconnect_0|cmd_mux_011|src_payload [0] & \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ) ) ) ) # ( 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & ( !\u0|mm_interconnect_0|cmd_mux_011|src_valid~1_combout  & ( (!\u0|mm_interconnect_0|cmd_mux_011|src_valid~0_combout  & 
// ((!\u0|mm_interconnect_0|cmd_mux_011|packet_in_progress~q ))) # (\u0|mm_interconnect_0|cmd_mux_011|src_valid~0_combout  & (\u0|mm_interconnect_0|cmd_mux_011|src_payload [0])) ) ) ) # ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & ( !\u0|mm_interconnect_0|cmd_mux_011|src_valid~1_combout  & ( (!\u0|mm_interconnect_0|cmd_mux_011|src_valid~0_combout  & 
// (((!\u0|mm_interconnect_0|cmd_mux_011|packet_in_progress~q )))) # (\u0|mm_interconnect_0|cmd_mux_011|src_valid~0_combout  & (\u0|mm_interconnect_0|cmd_mux_011|src_payload [0] & 
// ((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout )))) ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_011|src_payload [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_011|src_valid~0_combout ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_011|packet_in_progress~q ),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .datae(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_011|src_valid~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_011|update_grant~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|update_grant~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|update_grant~0 .lut_mask = 64'hC0D1D1D100555555;
defparam \u0|mm_interconnect_0|cmd_mux_011|update_grant~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y27_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|src11_valid~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|src11_valid~1_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q  & ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & ( 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [11] & (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & (\u0|mm_interconnect_0|router_001|Equal1~4_combout  & \u0|hps_0|fpga_interfaces|h2f_ARADDR [17]))) ) ) ) # ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q  & ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & ( (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & (\u0|mm_interconnect_0|router_001|Equal1~4_combout  & 
// \u0|hps_0|fpga_interfaces|h2f_ARADDR [17])) ) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [11]),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
        .datac(!\u0|mm_interconnect_0|router_001|Equal1~4_combout ),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),
        .datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux_001|src11_valid~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|src11_valid~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|src11_valid~1 .lut_mask = 64'h0000000000030001;
defparam \u0|mm_interconnect_0|cmd_demux_001|src11_valid~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y23_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg~0_combout  = ( \u0|mm_interconnect_0|router|Equal17~0_combout  & ( (\u0|mm_interconnect_0|cmd_mux_011|update_grant~0_combout  & ((\u0|mm_interconnect_0|cmd_demux|src11_valid~0_combout ) # 
// (\u0|mm_interconnect_0|cmd_demux_001|src11_valid~1_combout ))) ) ) # ( !\u0|mm_interconnect_0|router|Equal17~0_combout  & ( (\u0|mm_interconnect_0|cmd_mux_011|update_grant~0_combout  & \u0|mm_interconnect_0|cmd_demux_001|src11_valid~1_combout ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_011|update_grant~0_combout ),
        .datac(!\u0|mm_interconnect_0|cmd_demux_001|src11_valid~1_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_demux|src11_valid~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|router|Equal17~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg~0 .lut_mask = 64'h0303030303330333;
defparam \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y23_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg~2 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg~2_combout  = ( \u0|mm_interconnect_0|cmd_mux_011|arb|grant[1]~0_combout  & ( (!\u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg~0_combout  & 
// \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg [0]) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_011|arb|grant[1]~0_combout  & ( (\u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg [0]) # 
// (\u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg~0_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg~0_combout ),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_011|arb|grant[1]~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg~2 .lut_mask = 64'h55FF55FF00AA00AA;
defparam \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y23_N44
dffeas \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y23_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg~1_combout  = ( \u0|mm_interconnect_0|cmd_mux_011|arb|grant[0]~1_combout  & ( (\u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg [1]) # 
// (\u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg~0_combout ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_011|arb|grant[0]~1_combout  & ( (!\u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg~0_combout  & 
// \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg [1]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg~0_combout ),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_011|arb|grant[0]~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg~1 .lut_mask = 64'h00AA00AA55FF55FF;
defparam \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y23_N47
dffeas \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y23_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|arb|grant[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|arb|grant[1]~0_combout  = ( \u0|mm_interconnect_0|cmd_demux_001|src11_valid~1_combout  & ( ((!\u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg [0] & ((!\u0|mm_interconnect_0|cmd_demux|src11_valid~0_combout ) # 
// (!\u0|mm_interconnect_0|router|Equal17~0_combout )))) # (\u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg [1]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_demux|src11_valid~0_combout ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg [0]),
        .datac(!\u0|mm_interconnect_0|router|Equal17~0_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_demux_001|src11_valid~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_011|arb|grant[1]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|arb|grant[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|arb|grant[1]~0 .lut_mask = 64'h00000000C8FFC8FF;
defparam \u0|mm_interconnect_0|cmd_mux_011|arb|grant[1]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y23_N41
dffeas \u0|mm_interconnect_0|cmd_mux_011|saved_grant[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_011|arb|grant[1]~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|cmd_mux_011|update_grant~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|saved_grant[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_011|saved_grant[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y20_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|src_data[87] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|src_data [87] = (!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] & (((\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & \u0|mm_interconnect_0|cmd_mux_011|saved_grant [1])))) # (\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] & 
// (((\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & \u0|mm_interconnect_0|cmd_mux_011|saved_grant [1])) # (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0])))

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_011|src_data [87]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[87] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[87] .lut_mask = 64'h111F111F111F111F;
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[87] .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y20_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|src_data[88] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|src_data [88] = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & ( ((\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & \u0|mm_interconnect_0|cmd_mux_011|saved_grant [0])) # (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & ( (\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & \u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]) ) )

        .dataa(gnd),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_011|src_data [88]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[88] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[88] .lut_mask = 64'h003300330F3F0F3F;
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[88] .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y20_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout  = ( !\u0|mm_interconnect_0|cmd_mux_011|src_data [88] & ( !\u0|mm_interconnect_0|cmd_mux_011|src_data [87] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_011|src_data [87]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_011|src_data [88]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .lut_mask = 64'hF0F0F0F000000000;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y20_N20
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y20_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0_combout  = ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & ( (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & 
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & ((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ) # 
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )))) ) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .datae(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0 .lut_mask = 64'hC800000000000000;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y20_N29
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";
// synopsys translate_on

// Location: FF_X22_Y20_N1
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y20_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|m0_read~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent|m0_read~0_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & ( 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|m0_read~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|m0_read~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|m0_read~0 .lut_mask = 64'h000000000FFF0FFF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|m0_read~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y18_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg~0_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_agent|m0_read~0_combout  & ( (!\u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0_combout  & 
// !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0_combout ),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent|m0_read~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg~0 .lut_mask = 64'h00000000C0C0C0C0;
defparam \u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y18_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg~1_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg~0_combout  & ( \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~4_combout  ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~4_combout ),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg~1 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y18_N17
dffeas \u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y18_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_011|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_011|WideOr0~0_combout  = (!\u0|mm_interconnect_0|rsp_demux_011|src0_valid~0_combout  & (\u0|hps_0|fpga_interfaces|h2f_RREADY [0])) # (\u0|mm_interconnect_0|rsp_demux_011|src0_valid~0_combout  & 
// ((\u0|hps_0|fpga_interfaces|h2f_BREADY [0])))

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|rsp_demux_011|src0_valid~0_combout ),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_BREADY [0]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_demux_011|WideOr0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_011|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_011|WideOr0~0 .lut_mask = 64'h505F505F505F505F;
defparam \u0|mm_interconnect_0|rsp_demux_011|WideOr0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y18_N26
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][129] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][129]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y18_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~0_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][129]~q  & ( 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( (((\u0|mm_interconnect_0|write_en_tx_s1_agent|m0_read~0_combout  & \u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0_combout )) 
// # (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1])) # (\u0|mm_interconnect_0|write_en_tx_s1_agent|local_write~0_combout ) ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][129]~q  & ( 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & 
// (((\u0|mm_interconnect_0|write_en_tx_s1_agent|m0_read~0_combout  & \u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0_combout )) # (\u0|mm_interconnect_0|write_en_tx_s1_agent|local_write~0_combout ))) ) ) ) # ( 
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][129]~q  & ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( 
// ((\u0|mm_interconnect_0|write_en_tx_s1_agent|m0_read~0_combout  & \u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0_combout )) # (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][129]~q  & ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( 
// (\u0|mm_interconnect_0|write_en_tx_s1_agent|m0_read~0_combout  & (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent|local_write~0_combout ),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent|m0_read~0_combout ),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0_combout ),
        .datae(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][129]~q ),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~0 .lut_mask = 64'h00300F3F50705F7F;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y18_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][129]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][129]~feeder_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~0_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][129]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][129]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][129]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][129]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y18_N50
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][129] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][129]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][129]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y18_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|read~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|read~0_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][129]~q  & ( 
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [0] ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][129]~q  & ( 
// (!\u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg [0]) # (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [0]) ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used [0] & ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][129]~q  & ( !\u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg [0] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [0]),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg [0]),
        .datae(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used [0]),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|read~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|read~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|read~0 .lut_mask = 64'hFF000000FF0F0F0F;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|read~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y18_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|read~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|read~1_combout  = (\u0|mm_interconnect_0|rsp_demux_011|WideOr0~0_combout  & !\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|read~0_combout )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_011|WideOr0~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|read~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|read~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|read~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|read~1 .lut_mask = 64'h5050505050505050;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|read~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y18_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used[1]~1_combout  = ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|read~1_combout  & ( ((\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used [0] & 
// \u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used [1]) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg [0]),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|read~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used[1]~1 .lut_mask = 64'h05FF05FF00000000;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used[1]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y18_N53
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y18_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used[0]~0_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|read~1_combout  & ( 
// (\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used [1]) # (\u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg [0]) ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used [0] & ( 
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|read~1_combout  & ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used [1] ) ) ) # ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used [0] & ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|read~1_combout  ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used [0] & ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|read~1_combout  & ( 
// (\u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used [1]) ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg [0]),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used [1]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used [0]),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|read~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h3030FFFF0F0F3F3F;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y18_N38
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y18_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|comb~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent|comb~0_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][129]~q  & ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [0] ) ) # ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][129]~q  & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [0] & ((\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used [0]) # 
// (\u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg [0]))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg [0]),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [0]),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|comb~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|comb~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|comb~0 .lut_mask = 64'h030F030F0F0F0F0F;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|comb~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y18_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|always0~0_combout  = (\u0|mm_interconnect_0|write_en_tx_s1_agent|comb~0_combout  & \u0|mm_interconnect_0|rsp_demux_011|WideOr0~0_combout )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent|comb~0_combout ),
        .datad(!\u0|mm_interconnect_0|rsp_demux_011|WideOr0~0_combout ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|always0~0 .lut_mask = 64'h000F000F000F000F;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y18_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used[0]~1_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [0] & ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|write~0_combout  ) ) # ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [0] & ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|write~0_combout  ) ) # ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [0] & ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|write~0_combout  & ( (!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|always0~0_combout ) # ((\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]) # 
// (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|always0~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout ),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),
        .datae(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [0]),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|write~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h0000AFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y18_N47
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y18_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|rp_valid (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent|rp_valid~combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][129]~q  & ( (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [0] & 
// (!\u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used [0])) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][129]~q  & ( 
// (!\u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used [0]) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg [0]),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|rp_valid~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|rp_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|rp_valid .lut_mask = 64'hF000F000A000A000;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|rp_valid .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y22_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_011|src1_valid (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout  = ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|rp_valid~combout  & ( !\u0|mm_interconnect_0|rsp_demux_011|src0_valid~0_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|rsp_demux_011|src0_valid~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent|rp_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_011|src1_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_011|src1_valid .lut_mask = 64'hF0F0F0F000000000;
defparam \u0|mm_interconnect_0|rsp_demux_011|src1_valid .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y22_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|src_data[109] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|src_data [109] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [4] & ( ((\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [4])) # (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_AWID [4] & ( (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [4]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
        .datac(gnd),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [4]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_011|src_data [109]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[109] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[109] .lut_mask = 64'h0055005533773377;
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[109] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y22_N14
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_011|src_data [109]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .power_up = "low";
// synopsys translate_on

// Location: FF_X19_Y22_N23
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~14_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][109]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][109] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y22_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~14 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~14_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][109]~q  ) ) # ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][109]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~14 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~14 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y23_N43
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~14_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][109]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][109] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y23_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_data[109] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_data [109] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [4] & ( ((\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [4])) # (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_ARID [4] & ( (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [4]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [4]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_014|src_data [109]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[109] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[109] .lut_mask = 64'h0303030357575757;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[109] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y23_N53
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_014|src_data [109]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .power_up = "low";
// synopsys translate_on

// Location: FF_X23_Y23_N14
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~14_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][109]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][109] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y23_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~14 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~14_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][109]~q  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][109]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~14 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~14 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y23_N20
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~14_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][109]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][109] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y23_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~131 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~131_combout  = ( \u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout  & ( ((\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout  & \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][109]~q )) # 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][109]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout  & ( (\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout  & 
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][109]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][109]~q ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][109]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~131_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~131 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~131 .lut_mask = 64'h0505050505FF05FF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~131 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y32_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_020|src_payload~4 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_020|src_payload~4_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [4] & ( \u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_020|src_payload~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~4 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y32_N20
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_020|src_payload~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .power_up = "low";
// synopsys translate_on

// Location: FF_X23_Y32_N38
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~13_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][109]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][109] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y32_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~13 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~13_combout  = (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109])) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & 
// ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][109]~q )))

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][109]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~13 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~13 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y32_N50
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~13_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][109]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][109] .power_up = "low";
// synopsys translate_on

// Location: FF_X22_Y32_N38
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~13_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][109]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][109] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y32_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_019|src_payload~4 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_019|src_payload~4_combout  = (\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [4])

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
        .datac(gnd),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [4]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_019|src_payload~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~4 .lut_mask = 64'h0033003300330033;
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y32_N22
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_019|src_payload~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y32_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~13 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~13_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109] & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]) # 
// (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][109]~q ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109] & ( (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] 
// & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][109]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][109]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~13 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~13 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y32_N23
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~13_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][109]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][109] .power_up = "low";
// synopsys translate_on

// Location: FF_X18_Y28_N5
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~14_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][109]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][109] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y25_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_data[109] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|src_data [109] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [4] & ( ((\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [4])) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_AWID [4] & ( (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [4]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [4]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_008|src_data [109]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[109] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[109] .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[109] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y25_N40
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_008|src_data [109]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y28_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~14 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~14_combout  = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109] & ( (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used 
// [1]) # (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][109]~q ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109] & ( 
// (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][109]~q ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][109]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~14 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~14 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y28_N8
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~14_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][109]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][109] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y32_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~128 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~128_combout  = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][109]~q  & ( (!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout  & 
// ((!\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ) # ((!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout  & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][109]~q )))) # 
// (\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout  & (!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout  & ((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][109]~q )))) ) ) # ( 
// !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][109]~q  & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout  & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][109]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout ),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][109]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][109]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~128_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~128 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~128 .lut_mask = 64'h00CC00CCA0ECA0EC;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~128 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y32_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_021|src_payload~4 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_021|src_payload~4_combout  = (\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [4])

        .dataa(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [4]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_021|src_payload~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~4 .lut_mask = 64'h0055005500550055;
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y32_N41
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_021|src_payload~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .power_up = "low";
// synopsys translate_on

// Location: FF_X27_Y32_N35
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~13_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][109]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][109] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y32_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~13 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~13_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][109]~q  ) ) # ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][109]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~13 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~13 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y32_N40
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~13_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][109]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][109] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y32_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~129 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~129_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][109]~q  & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout  & 
// (!\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~128_combout  & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][109]~q ) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout )))) ) ) # ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][109]~q  & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~128_combout  & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][109]~q ) # 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][109]~q ),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ),
        .datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~128_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][109]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~129_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~129 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~129 .lut_mask = 64'hAF00AF0023002300;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~129 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y22_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_data[109] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|src_data [109] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [4] & ( ((\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [4])) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_AWID [4] & ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [4]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
        .datac(gnd),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [4]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_015|src_data [109]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[109] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[109] .lut_mask = 64'h0055005533773377;
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[109] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y22_N26
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_015|src_data [109]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .power_up = "low";
// synopsys translate_on

// Location: FF_X19_Y22_N20
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~14_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][109]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][109] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y22_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~14 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~14_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][109]~q  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][109]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~14 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~14 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y26_N35
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~14_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][109]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][109] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y26_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_data[109] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|src_data [109] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [4] & ( ((\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [4])) # (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_AWID [4] & ( (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [4]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [4]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_018|src_data [109]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[109] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[109] .lut_mask = 64'h0303030357575757;
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[109] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y26_N44
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_018|src_data [109]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .power_up = "low";
// synopsys translate_on

// Location: FF_X30_Y26_N59
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~14_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][109]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][109] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y26_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~14 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~14_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][109]~q  ) ) # ( 
// !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][109]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~14 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~14 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y26_N11
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~14_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][109]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][109] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y26_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~132 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~132_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][109]~q  & ( ((\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout  & 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][109]~q )) # (\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][109]~q  & ( 
// (\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout  & \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][109]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][109]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][109]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~132_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~132 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~132 .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~132 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y33_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_017|src_payload~4 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_017|src_payload~4_combout  = (\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [4])

        .dataa(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [4]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_017|src_payload~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~4 .lut_mask = 64'h0505050505050505;
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y33_N59
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_017|src_payload~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .power_up = "low";
// synopsys translate_on

// Location: FF_X18_Y33_N29
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~13_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][109]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][109] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y33_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~13 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~13_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][109]~q  ) ) # ( 
// !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
        .datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][109]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~13 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y33_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][109]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][109]~feeder_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~13_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~13_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][109]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][109]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][109]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][109]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y33_N43
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][109]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][109]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][109] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y33_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_013|src_payload~4 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_013|src_payload~4_combout  = (\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [4])

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [4]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_013|src_payload~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~4 .lut_mask = 64'h0303030303030303;
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y33_N23
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_013|src_payload~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .power_up = "low";
// synopsys translate_on

// Location: FF_X18_Y33_N38
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~13_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][109]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][109] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y33_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~13 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~13_combout  = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][109]~q  ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][109]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~13 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~13 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y31_N20
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~13_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][109]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][109] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y31_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~126 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~126_combout  = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout  & ( (!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout  & 
// (!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout  & \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][109]~q )) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout  & ( 
// ((!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout  & (!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout  & \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][109]~q ))) # 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][109]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout ),
        .datab(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ),
        .datac(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][109]~q ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][109]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~126_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~126 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~126 .lut_mask = 64'h08FF08FF08080808;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~126 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y31_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_016|src_payload~4 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_016|src_payload~4_combout  = (\u0|hps_0|fpga_interfaces|h2f_ARID [4] & \u0|mm_interconnect_0|cmd_mux_016|saved_grant [1])

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [4]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_016|src_payload~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~4 .lut_mask = 64'h000F000F000F000F;
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y31_N53
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_016|src_payload~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .power_up = "low";
// synopsys translate_on

// Location: FF_X19_Y31_N59
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~13_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][109]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][109] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y31_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~13 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~13_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][109]~q  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109] ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][109]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~13 .lut_mask = 64'h5555555500FF00FF;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~13 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y31_N35
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~13_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][109]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][109] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y31_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~127 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~127_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout  & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~126_combout  & 
// ((!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][109]~q ) # (!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ))) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout  & ( 
// (!\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~126_combout  & (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][109]~q  & ((!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][109]~q ) # 
// (!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][109]~q ),
        .datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~126_combout ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][109]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~127_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~127 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~127 .lut_mask = 64'hC800C800C8C8C8C8;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~127 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y22_N13
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~14_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][109]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][109] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y22_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|src_data[109] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|src_data [109] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [4] & ( ((\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [4])) # (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_ARID [4] & ( (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [4]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [4]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_009|src_data [109]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[109] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[109] .lut_mask = 64'h0303030357575757;
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[109] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y22_N56
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_009|src_data [109]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y22_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~14 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~14_combout  = ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][109]~q  ) ) # ( 
// !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][109]~q ),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~14 .lut_mask = 64'h0F0F0F0F33333333;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~14 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y24_N32
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~14_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][109]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][109] .power_up = "low";
// synopsys translate_on

// Location: FF_X22_Y24_N5
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~14_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][109]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][109] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y24_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_data[109] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_data [109] = ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [4] & ( (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]) # (\u0|hps_0|fpga_interfaces|h2f_AWID [4]) ) ) ) # ( 
// !\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [4] & ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & ( !\u0|hps_0|fpga_interfaces|h2f_ARID [4] & ( 
// \u0|hps_0|fpga_interfaces|h2f_AWID [4] ) ) )

        .dataa(gnd),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_AWID [4]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
        .datae(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_010|src_data [109]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[109] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[109] .lut_mask = 64'h0000333300FF33FF;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[109] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y24_N25
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_010|src_data [109]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y24_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~14 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~14_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109] & ( 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][109]~q ) ) ) # ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109] & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][109]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][109]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~14 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~14 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y24_N17
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~14_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][109]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][109] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y24_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~130 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~130_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][109]~q  & ( ((\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout  & 
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][109]~q )) # (\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][109]~q  & ( 
// (\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout  & \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][109]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ),
        .datac(!\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout ),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][109]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][109]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~130_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~130 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~130 .lut_mask = 64'h000F000F333F333F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~130 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y30_N32
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~13_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][109]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][109] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y32_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_012|src_payload~4 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_012|src_payload~4_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [4] & ( \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_ARID [4]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_012|src_payload~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~4 .lut_mask = 64'h000000000000FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y32_N1
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_012|src_payload~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y30_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~13 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~13_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109] & ( 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][109]~q ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109] & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][109]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][109]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~13 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y30_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][109]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][109]~feeder_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~13_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~13_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][109]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][109]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][109]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][109]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y30_N7
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][109]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][109]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][109] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y26_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|src_data[109] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|src_data [109] = ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [4] ) ) # ( !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [4] & ( 
// (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [4]) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & ( !\u0|hps_0|fpga_interfaces|h2f_ARID [4] & ( (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & 
// \u0|hps_0|fpga_interfaces|h2f_AWID [4]) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & ( !\u0|hps_0|fpga_interfaces|h2f_ARID [4] & ( (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [4]) ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [4]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_004|src_data [109]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[109] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[109] .lut_mask = 64'h030303030303FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[109] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y26_N28
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_004|src_data [109]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .power_up = "low";
// synopsys translate_on

// Location: FF_X18_Y26_N53
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~14_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][109]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][109] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y26_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~14 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~14_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][109]~q  ) ) # ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][109]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~14 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~14 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y26_N10
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~14_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][109]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][109] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y30_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_005|src_payload~4 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_005|src_payload~4_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [4] & ( \u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_ARID [4]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_005|src_payload~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~4 .lut_mask = 64'h000000000000FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y30_N41
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_005|src_payload~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .power_up = "low";
// synopsys translate_on

// Location: FF_X10_Y30_N59
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~13_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][109]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][109] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y30_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~13 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~13_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][109]~q  & ( 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][109]~q  & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][109]~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~13 .lut_mask = 64'h0A0A5F5F0A0A5F5F;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~13 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y30_N50
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~13_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][109]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][109] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y33_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_006|src_payload~4 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_006|src_payload~4_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [4] & ( \u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_006|src_payload~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~4 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y33_N53
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_006|src_payload~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .power_up = "low";
// synopsys translate_on

// Location: FF_X14_Y33_N56
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~13_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][109]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][109] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y33_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~13 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~13_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][109]~q  ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][109]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~13 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~13 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y33_N8
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~13_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][109]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][109] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y33_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~43 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~43_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][109]~q  ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][109]~q  & (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q  & 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0])) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][109]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~43_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~43 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~43 .lut_mask = 64'h0057005700FF00FF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~43 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y30_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~134 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~134_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][109]~q  & ( !\u0|mm_interconnect_0|rsp_mux_001|src_payload~43_combout  & ( 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout  & (((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][109]~q ) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout )) # 
// (\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][109]~q  & ( !\u0|mm_interconnect_0|rsp_mux_001|src_payload~43_combout  & ( 
// ((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][109]~q ) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout )) # (\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][109]~q ),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout ),
        .datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][109]~q ),
        .dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~43_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~134_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~134 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~134 .lut_mask = 64'hF7F700F700000000;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~134 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y33_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_003|src_payload~4 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_003|src_payload~4_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [4] & ( \u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_003|src_payload~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~4 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y33_N17
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_003|src_payload~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .power_up = "low";
// synopsys translate_on

// Location: FF_X14_Y33_N41
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~13_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][109]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][109] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y33_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~13 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~13_combout  = (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg 
// [109])) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][109]~q )))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][109]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~13 .lut_mask = 64'h0C3F0C3F0C3F0C3F;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~13 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y30_N26
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~13_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][109]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][109] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y27_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_002|src_payload~4 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_002|src_payload~4_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [4] & ( \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_002|src_payload~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~4 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y27_N23
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_002|src_payload~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .power_up = "low";
// synopsys translate_on

// Location: FF_X10_Y27_N41
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~13_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][109]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][109] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y27_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~13 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~13_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][109]~q  & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] ) ) # ( 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][109]~q  & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & ( 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109] ) ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][109]~q  & ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
        .datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][109]~q ),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~13 .lut_mask = 64'h00FF00FF0000FFFF;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~13 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y27_N43
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~13_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][109]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][109] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y27_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~42 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~42_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][109]~q  & 
// (((\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q )) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]))) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][109]~q  & ((\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][109]~q ),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~42_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~42 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~42 .lut_mask = 64'h1133113313331333;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~42 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y24_N59
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~13_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][109]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][109] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y24_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_001|src_payload~4 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_001|src_payload~4_combout  = ( \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [4] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [4]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_001|src_payload~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~4 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y24_N22
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_001|src_payload~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y24_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~13 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~13_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][109]~q  & ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg 
// [109] ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][109]~q  & ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109] & ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] ) ) ) # ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][109]~q  & ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109] & ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][109]~q ),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~13 .lut_mask = 64'h00005555AAAAFFFF;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~13 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y26_N11
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~13_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][109]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][109] .power_up = "low";
// synopsys translate_on

// Location: FF_X19_Y26_N41
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~14_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][109]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][109] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y26_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|src_data[109] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|src_data [109] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [4] & ( ((\u0|mm_interconnect_0|cmd_mux|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [4])) # (\u0|mm_interconnect_0|cmd_mux|saved_grant [0]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_AWID [4] & ( (\u0|mm_interconnect_0|cmd_mux|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [4]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [4]),
        .datad(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux|src_data [109]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|src_data[109] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|src_data[109] .lut_mask = 64'h0303030303FF03FF;
defparam \u0|mm_interconnect_0|cmd_mux|src_data[109] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y26_N37
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux|src_data [109]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y26_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~14 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~14_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][109]~q  & ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg 
// [109] ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][109]~q  & ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109] & ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] ) ) ) # ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][109]~q  & ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109] & ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] ) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][109]~q ),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~14 .lut_mask = 64'h00005555AAAAFFFF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~14 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y26_N20
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~14_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][109]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][109] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y26_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~133 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~133_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][109]~q  & ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][109]~q  & ( 
// (\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout  & (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~42_combout  & ((\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ) # (\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout )))) ) ) 
// ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][109]~q  & ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][109]~q  & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~42_combout  & 
// ((\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ) # (\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ))) ) ) ) # ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][109]~q  & ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][109]~q  & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout  & !\u0|mm_interconnect_0|rsp_mux_001|src_payload~42_combout ) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][109]~q  & ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][109]~q  & ( !\u0|mm_interconnect_0|rsp_mux_001|src_payload~42_combout  ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ),
        .datac(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~42_combout ),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ),
        .datae(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][109]~q ),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][109]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~133_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~133 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~133 .lut_mask = 64'hF0F0303050F01030;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~133 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y30_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~135 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~135_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][109]~q  & ( \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~133_combout  & ( 
// (\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout  & (\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~134_combout  & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][109]~q ) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout )))) ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][109]~q  & ( \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~133_combout  & ( 
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~134_combout  & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][109]~q ) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout ),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout ),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][109]~q ),
        .datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~134_combout ),
        .datae(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][109]~q ),
        .dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~133_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~135_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~135 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~135 .lut_mask = 64'h0000000000F30051;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~135 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y28_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[109] (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data [109] = ( \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~130_combout  & ( \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~135_combout  ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~130_combout  & ( 
// \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~135_combout  & ( ((!\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~129_combout ) # ((!\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~127_combout ) # 
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~132_combout ))) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~131_combout ) ) ) ) # ( \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~130_combout  & ( 
// !\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~135_combout  ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~130_combout  & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~135_combout  ) )

        .dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~131_combout ),
        .datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~129_combout ),
        .datac(!\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~132_combout ),
        .datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~127_combout ),
        .datae(!\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~130_combout ),
        .dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~135_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data [109]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109] .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109] .lut_mask = 64'hFFFFFFFFFFDFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109] .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y22_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|src_data[87] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|src_data [87] = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & ( ((\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWSIZE [1])) # (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & ( (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_009|src_data [87]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[87] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[87] .lut_mask = 64'h003300330F3F0F3F;
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[87] .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y22_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|src_data[88] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|src_data [88] = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & ( ((\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWSIZE [2])) # (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & ( (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_009|src_data [88]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[88] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[88] .lut_mask = 64'h0303030357575757;
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[88] .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y22_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout  = ( !\u0|mm_interconnect_0|cmd_mux_009|src_data [88] & ( !\u0|mm_interconnect_0|cmd_mux_009|src_data [87] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_009|src_data [87]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_009|src_data [88]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .lut_mask = 64'hF0F0F0F000000000;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y22_N23
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y22_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|src_data[34] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|src_data [34] = ((\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_WSTRB [2])) # (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1])

        .dataa(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [2]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_009|src_data [34]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[34] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[34] .lut_mask = 64'h555F555F555F555F;
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[34] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y22_N5
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_009|src_data [34]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y22_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|src_data[32] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|src_data [32] = ( \u0|hps_0|fpga_interfaces|h2f_WSTRB [0] & ( (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]) # (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_WSTRB [0] & ( 
// \u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_009|src_data [32]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[32] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[32] .lut_mask = 64'h5555555577777777;
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[32] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y22_N29
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_009|src_data [32]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y22_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|src_data[35] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|src_data [35] = ( \u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] ) # ( !\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_WSTRB [3] & \u0|mm_interconnect_0|cmd_mux_009|saved_grant 
// [0]) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [3]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_009|src_data [35]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[35] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[35] .lut_mask = 64'h000F000FFFFFFFFF;
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[35] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y22_N44
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_009|src_data [35]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y22_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~2_combout  = ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & ( 
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0])) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~2 .lut_mask = 64'hA000A00000000000;
defparam \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y22_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~3 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~3_combout  = ( \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [0] & ( (!\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~0_combout  & 
// (((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q  & \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~2_combout )))) # (\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~0_combout 
//  & ((!\u0|mm_interconnect_0|link_disable_s1_agent|local_write~0_combout ) # ((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q  & 
// \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~2_combout )))) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [0] & ( (!\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~0_combout  & 
// (((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q  & \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~2_combout )))) # (\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~0_combout 
//  & (((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q  & \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~2_combout )) # 
// (\u0|mm_interconnect_0|link_disable_s1_agent|local_write~0_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~0_combout ),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_agent|local_write~0_combout ),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~2_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~3 .lut_mask = 64'h11F111F144F444F4;
defparam \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~3 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y22_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( 
// (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ((!\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~3_combout  & 
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q )) # (\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~3_combout  & 
// ((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))))) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & 
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q )) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~3_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .lut_mask = 64'h00000000AACAAACA;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y22_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout  & ( 
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  ) ) ) # 
// ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout  & ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( 
// (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  & ((!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]) # 
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout )))) ) ) ) # ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout  & ( 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  ) ) ) # 
// ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout  & ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( 
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  & ((!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]) # 
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
        .datae(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .lut_mask = 64'hCF00FF004500FF00;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y21_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout  & ( 
// ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~1_combout  & \u0|mm_interconnect_0|cmd_mux_009|saved_grant [0])) # (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]) ) ) # ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout  & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~1_combout  & \u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~1_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 .lut_mask = 64'h000F000F333F333F;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y21_N17
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y21_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~4_combout  & ( 
// (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~4_combout  & ( ((\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & 
// !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0])) # (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~4_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 .lut_mask = 64'h3F0F3F0F33003300;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y21_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout  = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg 
// [2] & ( (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg 
// [2]))) # (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout )) ) ) # ( 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) # (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout ),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 .lut_mask = 64'h05AF05AFAF05AF05;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y21_N26
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y21_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3_combout  & ( 
// ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout  & \u0|mm_interconnect_0|cmd_mux_009|saved_grant [1])) # (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]) ) ) # ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3_combout  & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout  & \u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5 .lut_mask = 64'h0303030303FF03FF;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y21_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout  = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  
// & ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout  ) ) # ( 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] $ 
// (((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg 
// [2]))) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout ),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6 .lut_mask = 64'h22DD22DD0F0F0F0F;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y21_N23
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y21_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] & ( 
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg 
// [2] & \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) # ( 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] & ( ((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) 
// # (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])) # 
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .lut_mask = 64'hFF5FFF5F00A000A0;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y21_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout  & ( 
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout  & \u0|mm_interconnect_0|cmd_mux_009|saved_grant [0])) # 
// (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout  & ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout  & \u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]) ) ) ) # ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout  & ( 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  ) ) ) # ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout  & ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
        .datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .lut_mask = 64'hCCCCCCCC000F555F;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y21_N8
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y21_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  = ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] & ( 
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3])) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .lut_mask = 64'h2020202000000000;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y21_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout  = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  
// & ( (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg 
// [5]))) # (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout )) ) ) # ( 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  & ( (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) # (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 .lut_mask = 64'h05AF05AFAF05AF05;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y21_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~0_combout  & ( 
// ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout  & \u0|mm_interconnect_0|cmd_mux_009|saved_grant [1])) # (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]) ) ) # ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~0_combout  & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout  & \u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .lut_mask = 64'h0303030303FF03FF;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y21_N29
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y21_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout  = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  
// & ( (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] $ 
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6])))) # (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout )) ) ) # ( 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  & ( (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]))) # (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 .lut_mask = 64'h11BB11BBB11BB11B;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y21_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout  = ( 
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout  & ( 
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout  & ( 
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  ) ) ) # ( 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout  & ( 
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout  & ( 
// ((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout  & 
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout  & 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ))) # 
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) ) # ( 
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout  & ( 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout  & ( 
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  ) ) ) # ( 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout  & ( 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout  & ( 
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  ) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout ),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),
        .datae(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .lut_mask = 64'h55555555D5555555;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y21_N38
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y22_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( 
// (!\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~1_combout  & (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q )) # 
// (\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~1_combout  & ((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q  ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~1_combout ),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .lut_mask = 64'h00FF00FF53535353;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y22_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout  = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & ( 
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & (((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  
// & \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) # 
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h0000000050705070;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y22_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout  = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & ( 
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h000000000F000F00;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y22_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout  = ( 
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout  & ( 
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ) # (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout  & ( 
// ((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout  & ((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ) # 
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout )))) # 
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h7737773777777777;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y22_N44
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y22_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  = ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( 
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & (((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & 
// ((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))))) ) ) # ( 
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( ((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # 
// ((\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~1_combout  & (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )))) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~1_combout ),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datag(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .extended_lut = "on";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .lut_mask = 64'h0A0AF0F30000F0F3;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y25_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout  = ( \u0|mm_interconnect_0|cmd_mux_009|src_valid~0_combout  & ( 
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & ((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) # 
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ))) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_009|src_valid~0_combout  & ( 
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & (\u0|mm_interconnect_0|cmd_mux_009|src_valid~1_combout  & 
// ((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) # (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout )))) 
// ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_009|src_valid~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_009|src_valid~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h0007000707070707;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y22_N38
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_009|src_data [33]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y22_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0_combout  = ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & ( 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & ( (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & 
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & ((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) # 
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q )))) ) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .datae(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0 .lut_mask = 64'hA080000000000000;
defparam \u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y22_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & ( 
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] & ( (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & 
// (((!\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [0] & \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~0_combout )) # (\u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0_combout ))) ) ) ) # ( 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] ) ) # ( 
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] & ( 
// (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & (((\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [0] & \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~0_combout )) # 
// (\u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & ( 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0_combout ),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [0]),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~0_combout ),
        .datae(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hFFFF444CFFFF44C4;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y22_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18_combout  = ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & ( 
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) # 
// (((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ) # ((!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & !\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]))) # 
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout )) ) ) # ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & ( 
// ((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ) # 
// ((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & 
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
        .datae(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datag(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18 .extended_lut = "on";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18 .lut_mask = 64'hFFFFFFFFECFF0003;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y22_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1_combout  = ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1 .lut_mask = 64'hFFFFFFFF00000000;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y22_N35
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y22_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  = ( 
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) ) # ( 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  $ 
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) # (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .lut_mask = 64'hC30CC30C0C000C00;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y22_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout  = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( 
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  & ( (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) ) ) # ( 
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  & ( 
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  ) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q 
//  & ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  & ( (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  
// & \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datae(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .lut_mask = 64'h0033333300003300;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y22_N44
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y22_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  ) ) ) # ( 
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & ( 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ) ) 
// )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'h00000C0C0000CCCC;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y25_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|update_grant~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|update_grant~0_combout  = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & ( \u0|mm_interconnect_0|cmd_mux_009|src_valid~0_combout  & ( 
// \u0|mm_interconnect_0|cmd_mux_009|src_payload [0] ) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & ( \u0|mm_interconnect_0|cmd_mux_009|src_valid~0_combout  & ( 
// (\u0|mm_interconnect_0|cmd_mux_009|src_payload [0] & \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) ) ) ) # ( 
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & ( !\u0|mm_interconnect_0|cmd_mux_009|src_valid~0_combout  & ( (!\u0|mm_interconnect_0|cmd_mux_009|src_valid~1_combout  & 
// ((!\u0|mm_interconnect_0|cmd_mux_009|packet_in_progress~q ))) # (\u0|mm_interconnect_0|cmd_mux_009|src_valid~1_combout  & (\u0|mm_interconnect_0|cmd_mux_009|src_payload [0])) ) ) ) # ( 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & ( !\u0|mm_interconnect_0|cmd_mux_009|src_valid~0_combout  & ( (!\u0|mm_interconnect_0|cmd_mux_009|src_valid~1_combout  & 
// (((!\u0|mm_interconnect_0|cmd_mux_009|packet_in_progress~q )))) # (\u0|mm_interconnect_0|cmd_mux_009|src_valid~1_combout  & (\u0|mm_interconnect_0|cmd_mux_009|src_payload [0] & 
// ((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )))) ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_009|src_payload [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_009|src_valid~1_combout ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_009|packet_in_progress~q ),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datae(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_009|src_valid~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_009|update_grant~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|update_grant~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|update_grant~0 .lut_mask = 64'hC0D1D1D100555555;
defparam \u0|mm_interconnect_0|cmd_mux_009|update_grant~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y27_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|src9_valid~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|src9_valid~1_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q  & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [9] & ( 
// (\u0|mm_interconnect_0|router_001|Equal1~4_combout  & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & \u0|hps_0|fpga_interfaces|h2f_ARVALID [0]))) ) ) ) # ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q  & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [9] & ( (\u0|mm_interconnect_0|router_001|Equal1~4_combout  & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] 
// & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & \u0|hps_0|fpga_interfaces|h2f_ARVALID [0]))) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q  & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel 
// [9] & ( (\u0|mm_interconnect_0|router_001|Equal1~4_combout  & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & \u0|hps_0|fpga_interfaces|h2f_ARVALID [0]))) ) ) )

        .dataa(!\u0|mm_interconnect_0|router_001|Equal1~4_combout ),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
        .datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [9]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux_001|src9_valid~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|src9_valid~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|src9_valid~1 .lut_mask = 64'h0010000000100010;
defparam \u0|mm_interconnect_0|cmd_demux_001|src9_valid~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y25_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg~0_combout  = ( \u0|mm_interconnect_0|cmd_demux_001|src9_valid~1_combout  & ( \u0|mm_interconnect_0|cmd_mux_009|update_grant~0_combout  ) ) # ( !\u0|mm_interconnect_0|cmd_demux_001|src9_valid~1_combout 
//  & ( (\u0|mm_interconnect_0|cmd_demux|src9_valid~0_combout  & (\u0|mm_interconnect_0|router|Equal15~0_combout  & \u0|mm_interconnect_0|cmd_mux_009|update_grant~0_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_demux|src9_valid~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|router|Equal15~0_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_009|update_grant~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_demux_001|src9_valid~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg~0 .lut_mask = 64'h0005000500FF00FF;
defparam \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y25_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg~2 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg~2_combout  = ( \u0|mm_interconnect_0|cmd_mux_009|arb|grant[1]~0_combout  & ( (!\u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg~0_combout  & 
// \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg [0]) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_009|arb|grant[1]~0_combout  & ( (\u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg [0]) # 
// (\u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg~0_combout ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg~0_combout ),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_009|arb|grant[1]~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg~2 .lut_mask = 64'h33FF33FF00CC00CC;
defparam \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y25_N17
dffeas \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y25_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg~1_combout  = ( \u0|mm_interconnect_0|cmd_mux_009|arb|grant[0]~1_combout  & ( (\u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg [1]) # 
// (\u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg~0_combout ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_009|arb|grant[0]~1_combout  & ( (!\u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg~0_combout  & 
// \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg [1]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg~0_combout ),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_009|arb|grant[0]~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg~1 .lut_mask = 64'h00CC00CC33FF33FF;
defparam \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y25_N14
dffeas \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y25_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|arb|grant[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|arb|grant[1]~0_combout  = ( \u0|mm_interconnect_0|router|Equal15~0_combout  & ( \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg [1] & ( \u0|mm_interconnect_0|cmd_demux_001|src9_valid~1_combout  ) ) ) # ( 
// !\u0|mm_interconnect_0|router|Equal15~0_combout  & ( \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg [1] & ( \u0|mm_interconnect_0|cmd_demux_001|src9_valid~1_combout  ) ) ) # ( \u0|mm_interconnect_0|router|Equal15~0_combout  & ( 
// !\u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg [1] & ( (!\u0|mm_interconnect_0|cmd_demux|src9_valid~0_combout  & (!\u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg [0] & \u0|mm_interconnect_0|cmd_demux_001|src9_valid~1_combout )) ) ) ) # ( 
// !\u0|mm_interconnect_0|router|Equal15~0_combout  & ( !\u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg [1] & ( (!\u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg [0] & \u0|mm_interconnect_0|cmd_demux_001|src9_valid~1_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_demux|src9_valid~0_combout ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg [0]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|cmd_demux_001|src9_valid~1_combout ),
        .datae(!\u0|mm_interconnect_0|router|Equal15~0_combout ),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_009|arb|grant[1]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|arb|grant[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|arb|grant[1]~0 .lut_mask = 64'h00CC008800FF00FF;
defparam \u0|mm_interconnect_0|cmd_mux_009|arb|grant[1]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y25_N53
dffeas \u0|mm_interconnect_0|cmd_mux_009|saved_grant[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_009|arb|grant[1]~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|cmd_mux_009|update_grant~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|saved_grant[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_009|saved_grant[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y24_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|src_data[108] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|src_data [108] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [3] & ( ((\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [3])) # (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_ARID [3] & ( (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [3]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_AWID [3]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_009|src_data [108]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[108] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[108] .lut_mask = 64'h003300330F3F0F3F;
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[108] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y24_N17
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_009|src_data [108]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .power_up = "low";
// synopsys translate_on

// Location: FF_X19_Y24_N11
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~13_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][108]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][108] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y24_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~13 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~13_combout  = ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][108]~q  ) ) # ( 
// !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][108]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~13 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~13 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y24_N23
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~13_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][108]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][108] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y24_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~120 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~120_combout  = ( \u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout  & ( ((\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout  & 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][108]~q )) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][108]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout  & ( 
// (\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout  & \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][108]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][108]~q ),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][108]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~120_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~120 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~120 .lut_mask = 64'h003300330F3F0F3F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~120 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y33_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_017|src_payload~3 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_017|src_payload~3_combout  = (\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [3])

        .dataa(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [3]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_017|src_payload~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~3 .lut_mask = 64'h0505050505050505;
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y33_N26
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_017|src_payload~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .power_up = "low";
// synopsys translate_on

// Location: FF_X19_Y33_N35
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~12_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][108]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][108] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y33_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~12 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~12_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][108]~q  ) ) # ( 
// !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108] ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][108]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~12 .lut_mask = 64'h5555555500FF00FF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~12 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y33_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][108]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][108]~feeder_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~12_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~12_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][108]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][108]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][108]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][108]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y33_N59
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][108]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][108]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][108] .power_up = "low";
// synopsys translate_on

// Location: FF_X18_Y29_N38
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~13_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][108]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][108] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y29_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|src_data[108] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|src_data [108] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [3] & ( ((\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [3])) # (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_AWID [3] & ( (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [3]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
        .datac(gnd),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [3]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_007|src_data [108]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[108] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[108] .lut_mask = 64'h0055005533773377;
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[108] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y29_N10
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_007|src_data [108]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y29_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~13 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~13_combout  = ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108] & 
// ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][108]~q  ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg 
// [108] ) ) # ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108] & ( 
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][108]~q  ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][108]~q ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~13 .lut_mask = 64'h00000F0FFFFF0F0F;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~13 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y29_N20
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~13_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][108]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][108] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y33_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_013|src_payload~3 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_013|src_payload~3_combout  = (\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [3])

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
        .datac(gnd),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [3]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_013|src_payload~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~3 .lut_mask = 64'h0033003300330033;
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y33_N35
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_013|src_payload~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .power_up = "low";
// synopsys translate_on

// Location: FF_X18_Y33_N2
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~12_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][108]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][108] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y33_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~12 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~12_combout  = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][108]~q  ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][108]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~12 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~12 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y31_N35
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~12_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][108]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][108] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y31_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~116 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~116_combout  = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][108]~q  & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout ) # 
// ((!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout  & (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][108]~q  & !\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ))) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][108]~q  & ( (!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout  & (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][108]~q  & 
// !\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout ),
        .datab(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][108]~q ),
        .datac(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout ),
        .datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][108]~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~116_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~116 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~116 .lut_mask = 64'h2020FF202020FF20;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~116 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y31_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_016|src_payload~3 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_016|src_payload~3_combout  = ( \u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [3] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_016|src_payload~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~3 .lut_mask = 64'h0000000000FF00FF;
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y31_N58
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_016|src_payload~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .power_up = "low";
// synopsys translate_on

// Location: FF_X19_Y31_N5
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~12_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][108]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][108] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y31_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~12 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~12_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][108]~q  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][108]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~12 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~12 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y31_N23
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~12_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][108]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][108] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y31_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~117 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~117_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout  & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~116_combout  & 
// ((!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][108]~q ) # (!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ))) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout  & ( 
// (!\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~116_combout  & (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][108]~q  & ((!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][108]~q ) # 
// (!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][108]~q ),
        .datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~116_combout ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][108]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~117_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~117 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~117 .lut_mask = 64'hC800C800C8C8C8C8;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~117 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y26_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_data[108] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|src_data [108] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [3] & ( ((\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [3])) # (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_ARID [3] & ( (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [3]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [3]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_018|src_data [108]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[108] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[108] .lut_mask = 64'h0505050537373737;
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[108] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y26_N47
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_018|src_data [108]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .power_up = "low";
// synopsys translate_on

// Location: FF_X30_Y26_N56
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~13_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][108]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][108] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y26_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~13 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~13_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][108]~q  ) ) # ( 
// !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][108]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~13 .lut_mask = 64'h3333333300FF00FF;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~13 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y26_N4
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~13_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][108]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][108] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y23_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_data[108] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|src_data [108] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [3] & ( \u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARID [3] & ( \u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & ( 
// (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [3]) ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_ARID [3] & ( !\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & 
// \u0|hps_0|fpga_interfaces|h2f_AWID [3]) ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARID [3] & ( !\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [3]) ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [3]),
        .datad(gnd),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_ARID [3]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_015|src_data [108]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[108] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[108] .lut_mask = 64'h050505050505FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[108] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y23_N4
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_015|src_data [108]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .power_up = "low";
// synopsys translate_on

// Location: FF_X21_Y23_N14
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~13_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][108]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][108] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y23_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~13 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~13_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][108]~q  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][108]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~13 .lut_mask = 64'h3333333300FF00FF;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~13 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y26_N17
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~13_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][108]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][108] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y26_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~122 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~122_combout  = ( \u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout  & ( ((\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout  & \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][108]~q )) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][108]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout  & ( (\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout  & 
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][108]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout ),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][108]~q ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][108]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~122_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~122 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~122 .lut_mask = 64'h0303030303FF03FF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~122 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y32_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_020|src_payload~3 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_020|src_payload~3_combout  = (\u0|hps_0|fpga_interfaces|h2f_ARID [3] & \u0|mm_interconnect_0|cmd_mux_020|saved_grant [1])

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [3]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_020|src_payload~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~3 .lut_mask = 64'h000F000F000F000F;
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y32_N17
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_020|src_payload~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .power_up = "low";
// synopsys translate_on

// Location: FF_X23_Y32_N56
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~12_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][108]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][108] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y32_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~12 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~12_combout  = (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108])) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & 
// ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][108]~q )))

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][108]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~12 .lut_mask = 64'h2277227722772277;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~12 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y32_N43
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~12_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][108]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][108] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y25_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_data[108] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|src_data [108] = (!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & (\u0|hps_0|fpga_interfaces|h2f_ARID [3]))) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & 
// (((\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [3])) # (\u0|hps_0|fpga_interfaces|h2f_AWID [3])))

        .dataa(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [3]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_AWID [3]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_008|src_data [108]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[108] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[108] .lut_mask = 64'h0357035703570357;
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[108] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y25_N58
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_008|src_data [108]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .power_up = "low";
// synopsys translate_on

// Location: FF_X18_Y25_N44
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~13_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][108]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][108] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y25_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~13 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~13_combout  = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][108]~q  ) ) # ( 
// !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][108]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~13 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~13 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y29_N44
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~13_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][108]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][108] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y34_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_019|src_payload~3 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_019|src_payload~3_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [3] & ( \u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_ARID [3]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_019|src_payload~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~3 .lut_mask = 64'h000000000000FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y34_N26
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_019|src_payload~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .power_up = "low";
// synopsys translate_on

// Location: FF_X22_Y34_N2
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~12_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][108]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][108] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y34_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~12 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~12_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][108]~q  & ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] ) ) # ( 
// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][108]~q  & ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108] ) ) ) # 
// ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][108]~q  & ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108] ) ) 
// )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][108]~q ),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~12 .lut_mask = 64'h0F0F0F0F0000FFFF;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~12 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y32_N31
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~12_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][108]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][108] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y32_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~118 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~118_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout  & ( (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][108]~q  & (!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout  
// & !\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout )) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout  & ( ((\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][108]~q  & 
// (!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout  & !\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ))) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][108]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][108]~q ),
        .datab(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][108]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~118_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~118 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~118 .lut_mask = 64'h40FF40FF40404040;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~118 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y32_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_021|src_payload~3 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_021|src_payload~3_combout  = (\u0|hps_0|fpga_interfaces|h2f_ARID [3] & \u0|mm_interconnect_0|cmd_mux_021|saved_grant [1])

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARID [3]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_021|src_payload~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~3 .lut_mask = 64'h0055005500550055;
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y32_N17
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_021|src_payload~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .power_up = "low";
// synopsys translate_on

// Location: FF_X27_Y32_N47
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~12_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][108]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][108] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y32_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~12 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~12_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][108]~q  ) ) # ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][108]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~12 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~12 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y33_N11
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~12_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][108]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][108] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y32_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~119 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~119_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout  & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~118_combout  & 
// ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][108]~q ) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ))) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout  & ( 
// (!\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~118_combout  & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][108]~q  & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][108]~q ) # 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][108]~q ),
        .datac(!\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~118_combout ),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][108]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~119_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~119 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~119 .lut_mask = 64'hD000D000D0D0D0D0;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~119 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y24_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|src_data[108] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|src_data [108] = ( \u0|mm_interconnect_0|cmd_mux|saved_grant [0] & ( \u0|mm_interconnect_0|cmd_mux|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_AWID [3]) # (\u0|hps_0|fpga_interfaces|h2f_ARID [3]) ) ) ) # ( 
// !\u0|mm_interconnect_0|cmd_mux|saved_grant [0] & ( \u0|mm_interconnect_0|cmd_mux|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [3] ) ) ) # ( \u0|mm_interconnect_0|cmd_mux|saved_grant [0] & ( !\u0|mm_interconnect_0|cmd_mux|saved_grant [1] & ( 
// \u0|hps_0|fpga_interfaces|h2f_AWID [3] ) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARID [3]),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [3]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux|src_data [108]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|src_data[108] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|src_data[108] .lut_mask = 64'h00000F0F55555F5F;
defparam \u0|mm_interconnect_0|cmd_mux|src_data[108] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y24_N55
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux|src_data [108]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .power_up = "low";
// synopsys translate_on

// Location: FF_X25_Y24_N50
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~13_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][108]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][108] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y24_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~13 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~13_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][108]~q  & ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] ) ) # ( 
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][108]~q  & ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg 
// [108] ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][108]~q  & ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & ( 
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][108]~q ),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~13 .lut_mask = 64'h0F0F0F0F0000FFFF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~13 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y26_N29
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~13_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][108]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][108] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y27_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_002|src_payload~3 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_002|src_payload~3_combout  = ( \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [3] ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARID [3]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_002|src_payload~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~3 .lut_mask = 64'h0000555500005555;
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y27_N59
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_002|src_payload~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .power_up = "low";
// synopsys translate_on

// Location: FF_X10_Y27_N35
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~12_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][108]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][108] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y27_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~12 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~12_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][108]~q  & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] ) ) # ( 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][108]~q  & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & ( 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108] ) ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][108]~q  & ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][108]~q ),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~12 .lut_mask = 64'h0F0F0F0F0000FFFF;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~12 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y27_N2
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~12_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][108]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][108] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y27_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~40 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~40_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][108]~q  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][108]~q  & (((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0] & 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q )) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0]),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][108]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~40_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~40 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~40 .lut_mask = 64'h0037003700FF00FF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~40 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y24_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_001|src_payload~3 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_001|src_payload~3_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [3] & ( \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_ARID [3]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_001|src_payload~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~3 .lut_mask = 64'h000000000000FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y24_N41
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_001|src_payload~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .power_up = "low";
// synopsys translate_on

// Location: FF_X11_Y24_N29
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~12_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][108]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][108] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y24_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~12 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~12_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][108]~q  & ( (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg 
// [108]) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][108]~q  & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][108]~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~12 .lut_mask = 64'h0A0A5F5F0A0A5F5F;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~12 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y26_N50
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~12_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][108]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][108] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y26_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~123 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~123_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][108]~q  & ( \u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout  & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~40_combout  & 
// \u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ) ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][108]~q  & ( \u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout  & ( 
// !\u0|mm_interconnect_0|rsp_mux_001|src_payload~40_combout  ) ) ) # ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][108]~q  & ( !\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout  & ( 
// (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~40_combout  & (\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout  & ((!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][108]~q ) # 
// (\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout )))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][108]~q  & ( !\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout  & ( 
// (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~40_combout  & ((!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][108]~q ) # (\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][108]~q ),
        .datab(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~40_combout ),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ),
        .datae(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][108]~q ),
        .dataf(!\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~123_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~123 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~123 .lut_mask = 64'h8C8C008CCCCC00CC;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~123 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y30_N44
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~12_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][108]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][108] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y32_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_012|src_payload~3 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_012|src_payload~3_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [3] & ( \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_ARID [3]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_012|src_payload~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~3 .lut_mask = 64'h000000000000FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y32_N7
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_012|src_payload~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y30_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~12 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~12_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108] & ( 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][108]~q ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108] & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][108]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][108]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~12 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~12 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y30_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][108]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][108]~feeder_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~12_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~12_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][108]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][108]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][108]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][108]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y30_N1
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][108]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][108]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][108] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y33_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_006|src_payload~3 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_006|src_payload~3_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [3] & ( \u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_006|src_payload~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~3 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y33_N50
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_006|src_payload~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .power_up = "low";
// synopsys translate_on

// Location: FF_X14_Y33_N2
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~12_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][108]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][108] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y33_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~12 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~12_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][108]~q  ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][108]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~12 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~12 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y33_N53
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~12_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][108]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][108] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y33_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~41 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~41_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][108]~q  ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0] & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][108]~q  & (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q  & 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0])) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][108]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~41_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~41 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~41 .lut_mask = 64'h0057005700FF00FF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~41 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y30_N20
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~12_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][108]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][108] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y30_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_005|src_payload~3 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_005|src_payload~3_combout  = (\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [3])

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
        .datac(gnd),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [3]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_005|src_payload~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~3 .lut_mask = 64'h0033003300330033;
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y30_N10
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_005|src_payload~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y30_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~12 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~12_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][108]~q  & ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108] ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][108]~q  & ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108] & ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] ) ) ) # ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][108]~q  & ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108] & ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][108]~q ),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~12 .lut_mask = 64'h00000F0FF0F0FFFF;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~12 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y30_N26
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~12_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][108]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][108] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y26_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|src_data[108] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|src_data [108] = ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_AWID [3] & ( (\u0|hps_0|fpga_interfaces|h2f_ARID [3]) # (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]) ) ) ) # ( 
// !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_AWID [3] & ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & ( !\u0|hps_0|fpga_interfaces|h2f_AWID [3] & ( 
// \u0|hps_0|fpga_interfaces|h2f_ARID [3] ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [3]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_004|src_data [108]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[108] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[108] .lut_mask = 64'h00000F0F33333F3F;
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[108] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y26_N56
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_004|src_data [108]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .power_up = "low";
// synopsys translate_on

// Location: FF_X18_Y26_N50
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~13_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][108]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][108] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y26_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~13 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~13_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][108]~q  ) ) # ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][108]~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~13 .lut_mask = 64'h333333330F0F0F0F;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~13 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y26_N32
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~13_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][108]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][108] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y30_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~124 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~124_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][108]~q  & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout  & ( 
// (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~41_combout  & ((\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ) # (\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ))) ) ) ) # ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][108]~q  & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout  & ( !\u0|mm_interconnect_0|rsp_mux_001|src_payload~41_combout  ) ) ) # ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][108]~q  & ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout  & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~41_combout  & 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][108]~q  & ((\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ) # (\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout )))) ) ) ) # ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][108]~q  & ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout  & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~41_combout  & 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][108]~q ) ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ),
        .datac(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~41_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][108]~q ),
        .datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][108]~q ),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~124_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~124 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~124 .lut_mask = 64'hF0007000F0F07070;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~124 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y33_N5
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~12_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][108]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][108] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y33_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_003|src_payload~3 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_003|src_payload~3_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [3] & ( \u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_003|src_payload~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~3 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y33_N13
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_003|src_payload~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y33_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~12 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~12_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108] & ( 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][108]~q ) ) ) # ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108] & ( (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][108]~q ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][108]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~12 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~12 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y30_N20
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~12_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][108]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][108] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y30_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~125 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~125_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][108]~q  & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout  & ( 
// (\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout  & (\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~123_combout  & \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~124_combout )) ) ) ) # ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][108]~q  & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout  & ( (\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~123_combout  & 
// \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~124_combout ) ) ) ) # ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][108]~q  & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout  & ( 
// (\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout  & (\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~123_combout  & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][108]~q  & 
// \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~124_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][108]~q  & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout  & ( 
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~123_combout  & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][108]~q  & \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~124_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout ),
        .datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~123_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][108]~q ),
        .datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~124_combout ),
        .datae(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][108]~q ),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~125_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~125 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~125 .lut_mask = 64'h0030001000330011;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~125 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y23_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|src_data[108] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|src_data [108] = ( \u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & ( ((\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [3])) # (\u0|hps_0|fpga_interfaces|h2f_ARID [3]) ) ) # ( 
// !\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & ( (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [3]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [3]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_011|src_data [108]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[108] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[108] .lut_mask = 64'h0303030303FF03FF;
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[108] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y23_N20
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_011|src_data [108]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .power_up = "low";
// synopsys translate_on

// Location: FF_X21_Y23_N59
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~13_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][108]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][108] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y23_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~13 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~13_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][108]~q  ) ) # ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108] ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][108]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~13 .lut_mask = 64'h5555555500FF00FF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~13 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y23_N2
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~13_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][108]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][108] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y23_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_data[108] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_data [108] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [3] & ( ((\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [3])) # (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_ARID [3] & ( (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [3]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [3]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_014|src_data [108]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[108] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[108] .lut_mask = 64'h0303030357575757;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[108] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y23_N50
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_014|src_data [108]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .power_up = "low";
// synopsys translate_on

// Location: FF_X23_Y23_N38
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~13_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][108]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][108] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y23_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~13 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~13_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][108]~q  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][108]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~13 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~13 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y23_N50
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~13_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][108]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][108] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y23_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~121 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~121_combout  = ( \u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout  & ( ((\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout  & \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][108]~q 
// )) # (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][108]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout  & ( (\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout  & 
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][108]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout ),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][108]~q ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][108]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~121_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~121 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~121 .lut_mask = 64'h003300330F3F0F3F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~121 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y28_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[108] (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data [108] = ( \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~125_combout  & ( \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~121_combout  ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~125_combout  & ( 
// \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~121_combout  ) ) # ( \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~125_combout  & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~121_combout  & ( 
// ((!\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~117_combout ) # ((!\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~119_combout ) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~122_combout ))) # 
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~120_combout ) ) ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~125_combout  & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~121_combout  ) )

        .dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~120_combout ),
        .datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~117_combout ),
        .datac(!\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~122_combout ),
        .datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~119_combout ),
        .datae(!\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~125_combout ),
        .dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~121_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data [108]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108] .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108] .lut_mask = 64'hFFFFFFDFFFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108] .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y30_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout  = ( !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0] & ( \u0|hps_0|fpga_interfaces|h2f_ARLEN [1] ) ) # ( \u0|hps_0|fpga_interfaces|h2f_ARLEN [0] & ( !\u0|hps_0|fpga_interfaces|h2f_ARLEN [1] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3 .lut_mask = 64'h0000FFFFFFFF0000;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X10_Y32_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout  = ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  
// & (((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])))) # 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout )))) ) ) ) 
// # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  
// & (((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])))) # 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout )))) ) ) ) 
// # ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q 
// ) # ((\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout )) ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  
// & (\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),
        .datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .lut_mask = 64'h0011AABBA0B10A1B;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y32_N8
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y32_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg 
// [3] & ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] $ 
// (((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .lut_mask = 64'hC3F0C3F0F0F0F0F0;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X10_Y32_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout  = ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  & ( (\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] & 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # 
// ((\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .lut_mask = 64'hF0F3F0F300030003;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y32_N38
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y32_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & 
// ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4])) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .lut_mask = 64'h00000000A000A000;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y32_N34
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y32_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout  = ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout )) # 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]))) ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout )) # 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]))) ) ) ) # ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ) ) ) 
// ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .lut_mask = 64'h2222888827278D8D;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X9_Y31_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  = ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & ( 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & (\u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout  & \u0|mm_interconnect_0|cmd_mux_005|saved_grant [1])) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .lut_mask = 64'h0000000001010101;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X8_Y31_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  & ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  & ( 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & 
// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) # 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .lut_mask = 64'h0023002333333333;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X8_Y31_N53
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";
// synopsys translate_on

// Location: FF_X9_Y31_N8
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X9_Y31_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout  = ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & ( 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q 
// ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & ( 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q  & 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h3000300033003300;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X10_Y31_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout  = !\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .lut_mask = 64'hF0F0F0F0F0F0F0F0;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X9_Y31_N59
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X9_Y31_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout  = (!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]) # ((!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & 
// !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]))

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .lut_mask = 64'hFAF0FAF0FAF0FAF0;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X9_Y31_N56
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .power_up = "low";
// synopsys translate_on

// Location: FF_X9_Y31_N35
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X9_Y31_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~1_combout  = ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & ( 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~1 .lut_mask = 64'hC000C00000000000;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X9_Y31_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~2_combout  = ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( 
// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q  & \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~1_combout )) # 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~2 .lut_mask = 64'h0FAF0FAF00000000;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X9_Y31_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~2_combout  & ( 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q 
// ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~2_combout  & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .lut_mask = 64'h5500550050505050;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X9_Y31_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  = ( \u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] & ( 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  & ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q 
// ) # ((!\u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout ) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout )))) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_005|saved_grant 
// [1] & ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .lut_mask = 64'hFF00FF00EF00EF00;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y32_N26
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y32_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout  = ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) # 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout  & ((\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1])))) ) ) ) 
// # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) # 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout  & ((\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1])))) ) ) ) 
// # ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # 
// ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout  & \u0|mm_interconnect_0|cmd_mux_005|saved_grant [1])) ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout  & \u0|mm_interconnect_0|cmd_mux_005|saved_grant [1])) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
        .datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .lut_mask = 64'h0011AABBA0B10A1B;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X10_Y32_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout  = ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout  & ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout  & ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout  & ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout  & ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  ) ) ) # ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout  & ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout  & ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout  & ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout  & ( 
// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout  & 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout  & 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ))) # 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),
        .datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .lut_mask = 64'h33B3333333333333;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y32_N2
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y31_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout  = ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) # 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .lut_mask = 64'hFFF0FFF000000000;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X8_Y31_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout  = 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout )))

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h0010001000100010;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X9_Y31_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout  & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0_combout  & (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q )) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h040404040C0C0C0C;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X8_Y31_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout  = ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) # 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  $ 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .lut_mask = 64'h55AA55AA44EE44EE;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X8_Y31_N59
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on

// Location: FF_X8_Y31_N56
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X8_Y31_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout  = ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) # 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] $ 
// (((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) # 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .lut_mask = 64'h50AF50AF44EE44EE;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X8_Y31_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout  = ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) # 
// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ) ) # ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) # 
// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) # 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))) ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) # 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .lut_mask = 64'h0E04F4FE0404FEFE;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X8_Y31_N2
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X8_Y31_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  = ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h5000500000000000;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X8_Y31_N29
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X8_Y31_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout  = ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) # 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  $ 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .lut_mask = 64'h0FF00FF044EE44EE;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X8_Y31_N31
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X8_Y31_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout  = ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & ( 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) # 
// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & ( 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ) ) # ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & ( 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout )))) # 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # 
// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )))) ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & ( 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout )))) # 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .lut_mask = 64'h04AEFE540404FEFE;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X8_Y31_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout  = ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout  & 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout  & 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout  & 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .lut_mask = 64'h8000800000000000;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X8_Y31_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout  & ( 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout  & ( 
// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))) # 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h0F2F0F2F00220022;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X8_Y31_N47
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";
// synopsys translate_on

// Location: FF_X8_Y31_N14
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][74] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~7_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][74]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X8_Y31_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~7 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~7_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) # 
// ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])))) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & 
// (((\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][74]~q )))) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & 
// (((\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][74]~q )))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][74]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h025702578ADF8ADF;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X7_Y31_N23
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][74] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~7_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";
// synopsys translate_on

// Location: FF_X8_Y31_N38
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][76] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][76]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X8_Y31_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~5 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~5_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][76]~q  ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][76]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h0303030300FF00FF;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X7_Y31_N29
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][76] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~5_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][76]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";
// synopsys translate_on

// Location: FF_X8_Y31_N23
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][77] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][77]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X8_Y31_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~4 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~4_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][77]~q  ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][77]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~4 .lut_mask = 64'h0505050500FF00FF;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X7_Y31_N41
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][77] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~4_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][77]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";
// synopsys translate_on

// Location: FF_X8_Y31_N17
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][75] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][75]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X8_Y31_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~6 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~6_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) # 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][75]~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][75]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][75]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h005500550A5F0A5F;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X7_Y31_N53
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][75] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~6_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][75]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X7_Y31_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~0_combout  = ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][75]~q  & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][76]~q  & 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][77]~q  & !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][74]~q )) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][77]~q ),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~0 .lut_mask = 64'hA000A00000000000;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X6_Y31_N29
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][78] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~3_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][78]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X6_Y31_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~3 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~3_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][78]~q  & ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][78]~q  & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]) ) ) ) # ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][78]~q  & ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][78]~q ),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h000033330C0C3F3F;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X6_Y31_N16
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][78] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~3_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][78]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X7_Y31_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout  & 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout  & 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) ) ) # ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout  & 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][74]~q  $ (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][75]~q ))) ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout  & (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][74]~q  $ (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][75]~q ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h2121212133000033;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X7_Y31_N44
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X6_Y31_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~0_combout  = ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] ) ) ) # ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4] ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h3333FFFFCCCC0000;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X7_Y31_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout  & ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][74]~q  & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][76]~q )) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~0_combout ))) ) ) ) # ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout  & ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][74]~q  & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][76]~q  $ ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][75]~q )))) # 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~0_combout )))) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~0_combout ),
        .datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h0000B78400007744;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X7_Y31_N32
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X7_Y31_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~2_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5] ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5] $ (((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h3FC03FC0FF00FF00;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X7_Y31_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~1_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][75]~q  & ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][77]~q  ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][75]~q  & ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][77]~q  $ (((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][76]~q  & 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][77]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h5FA05FA0FF00FF00;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X7_Y31_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~1_combout  & ( 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout  & 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~2_combout )) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~1_combout  & ( 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ) # 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~2_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~2_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h0F0A0F0A05000500;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X7_Y31_N5
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X7_Y31_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~1_combout  = ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3])) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~1 .lut_mask = 64'h8080808000000000;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X7_Y31_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~1_combout  & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout  & (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~0_combout  $ (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][78]~q 
// )))) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~1_combout  & ( 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~0_combout  $ (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][78]~q )) 
// # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~1_combout  & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout  & 
// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~0_combout  $ (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][78]~q )) # 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~1_combout  & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout  & (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~0_combout  $ (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][78]~q 
// )))) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~0_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][78]~q ),
        .datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h0208070D070D0208;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X7_Y31_N8
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X7_Y31_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~1_combout  = ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'hC000C00000000000;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X7_Y31_N59
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_busy (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X7_Y31_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout  & ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~1_combout  & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~0_combout  & ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][78]~q )))) # 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6])))) ) ) ) # ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout  & ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~1_combout  & ( 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~0_combout  & (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][78]~q )) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~0_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][78]~q ),
        .datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h0000500000005C0C;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X7_Y31_N55
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X7_Y31_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [7] & ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_busy~q  ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [7] & ( 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_busy~q  & ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~1_combout ) # 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h00F300F300FF00FF;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X7_Y31_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout  & \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout  & 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][74]~q  & \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout )) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h00A000A000AA00AA;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X7_Y31_N14
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X7_Y31_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout  = (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_busy~q )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h0033003300330033;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X9_Y31_N11
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";
// synopsys translate_on

// Location: FF_X6_Y31_N35
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][66]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X6_Y31_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~2_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][66]~q  & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]) # 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][66]~q  & ( 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][66]~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~2 .lut_mask = 64'h50505F5F50505F5F;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X6_Y31_N14
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~2_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][66]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X7_Y31_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~0_combout  = ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][76]~q  & ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][77]~q  & ( 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][74]~q  & (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_busy~q  & (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][75]~q  & 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][78]~q ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][78]~q ),
        .datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][76]~q ),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][77]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h4000000000000000;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X7_Y31_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~0_combout  & ( 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][66]~q  & !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|comb~0_combout ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~0_combout  & ( 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][66]~q  & ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout ) # ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|comb~0_combout ) # 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~1_combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][66]~q ),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|comb~0_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h3332333230303030;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X10_Y31_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout  & ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0] ) ) 
// # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout  & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0]) # 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0_combout ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0]),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hCFCFCFCFCCCCCCCC;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X6_Y31_N50
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][129] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y31_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|read~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|read~0_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0] & ( (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & 
// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0]) # (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ))) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0] & ( 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg [0] & (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0]) # 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][129]~q )))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg [0]),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0]),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|read~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|read~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|read~0 .lut_mask = 64'h0054005400FC00FC;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|read~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X6_Y31_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[1]~1_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0] & ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|read~0_combout  & ( 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg [0]) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [1]) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0] & ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|read~0_combout  & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [1] ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg [0]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0]),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|read~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[1]~1 .lut_mask = 64'h33333F3F00000000;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[1]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X6_Y31_N11
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X6_Y31_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[0]~0_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|read~0_combout  & ( ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg [0] 
// & \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|read~0_combout  & ( 
// ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [1])) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0]) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|read~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h50FF50FF0F5F0F5F;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X6_Y31_N5
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X6_Y31_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|comb~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|comb~0_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][129]~q  & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0] ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][129]~q  & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0] & ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0]) # 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg [0]))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg [0]),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|comb~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|comb~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|comb~0 .lut_mask = 64'h0555055555555555;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|comb~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y31_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0_combout  = ( \u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|comb~0_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|comb~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0 .lut_mask = 64'h000000000000FFFF;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X10_Y31_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[1]~0_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout  & ( 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|write~0_combout  & ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]))) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|write~0_combout  & 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0])) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout  & ( 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|write~0_combout  & (((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0_combout  & \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1])))) # 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|write~0_combout  & ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0_combout  & (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0])) # 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0_combout  & ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]))))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|write~0_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0]),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[1]~0 .lut_mask = 64'h10B510B511BB11BB;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[1]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y31_N32
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X9_Y31_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]) # (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout  & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # 
// ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0_combout  & !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1])) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hFF44FF44FFCCFFCC;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X8_Y31_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout  & ( 
// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) # 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout  & ( 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h002200220F2F0F2F;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X8_Y31_N50
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X8_Y31_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  = ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  $ 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))) # 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .lut_mask = 64'hA50AA50A0A000A00;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X8_Y31_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout  = ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & ( 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & ( 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .lut_mask = 64'h0033003330303030;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X8_Y31_N20
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X9_Y31_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q  & ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] 
// & (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] 
// & !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ))) ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q  & ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & 
// ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] 
// & !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1])) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0 .lut_mask = 64'h8080800000000000;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X10_Y31_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter~0_combout  = ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout  & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override~q  & 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~0_combout  & !\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter [0])) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override~q ),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~0_combout ),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter~0 .lut_mask = 64'h1100110000000000;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y31_N53
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y31_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter [0] & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override~q  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0 .lut_mask = 64'h0000000000FF00FF;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X9_Y31_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  = ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q  & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ) 
// ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q  & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q  & !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) 
// ) ) # ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q  & ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & (((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q 
// )))) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0_combout  & 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q  & ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q  & 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .lut_mask = 64'h0F000F880F000FFF;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X9_Y31_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q 
//  & ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & 
// ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout ) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0_combout )))) ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout ),
        .datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .lut_mask = 64'hAAAA088800000000;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X9_Y31_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout  = ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q 
// ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// (((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q )))) # 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q 
// )) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3 .lut_mask = 64'h22E222E222222222;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X10_Y31_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q 
//  & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  & 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout  & 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  & 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout  & 
// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) # 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4 .lut_mask = 64'hC080C080C000C000;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X10_Y32_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_005|packet_in_progress~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_005|packet_in_progress~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_005|packet_in_progress~q  & ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout  ) ) # ( !\u0|mm_interconnect_0|cmd_mux_005|packet_in_progress~q  & ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout  & ( (\u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout  & \u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]) ) ) ) # ( 
// \u0|mm_interconnect_0|cmd_mux_005|packet_in_progress~q  & ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout  & ( (!\u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout ) # 
// (!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]) ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_005|packet_in_progress~q ),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_005|packet_in_progress~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_005|packet_in_progress~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_005|packet_in_progress~0 .lut_mask = 64'h0000FAFA0505FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_005|packet_in_progress~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y32_N17
dffeas \u0|mm_interconnect_0|cmd_mux_005|packet_in_progress (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_005|packet_in_progress~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_005|packet_in_progress~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_005|packet_in_progress .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_005|packet_in_progress .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y32_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_005|update_grant~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_005|update_grant~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout  & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout  & ( 
// (!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] & !\u0|mm_interconnect_0|cmd_mux_005|packet_in_progress~q ) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout  & ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout  & ( !\u0|mm_interconnect_0|cmd_mux_005|packet_in_progress~q  ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout 
//  & ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout  & ( (!\u0|mm_interconnect_0|cmd_mux_005|packet_in_progress~q ) # (\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]) ) 
// ) ) # ( !\u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout  & ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout  & ( 
// !\u0|mm_interconnect_0|cmd_mux_005|packet_in_progress~q  ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_005|packet_in_progress~q ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout ),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_005|update_grant~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_005|update_grant~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_005|update_grant~0 .lut_mask = 64'hF0F0F3F3F0F0C0C0;
defparam \u0|mm_interconnect_0|cmd_mux_005|update_grant~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y32_N59
dffeas \u0|mm_interconnect_0|cmd_mux_005|saved_grant[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|cmd_mux_005|update_grant~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_005|saved_grant[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_005|saved_grant[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X9_Y31_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout  = ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout  & ( ((\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] & (\u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout  & 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ))) # 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout  & ( (\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] & (\u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout  & 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q )) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .lut_mask = 64'h001100110F1F0F1F;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X9_Y31_N29
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .power_up = "low";
// synopsys translate_on

// Location: FF_X9_Y31_N20
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X9_Y31_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~0_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & ( 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69])) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~0 .lut_mask = 64'h0050005050505050;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X10_Y31_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|write~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|write~0_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0_combout  & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~0_combout  ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0_combout  & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~0_combout  & \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~0_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|write~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|write~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h0303030333333333;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|write~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X10_Y31_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[0]~1_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0_combout  & ( ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0] & 
// ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout )))) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|write~0_combout ) ) 
// ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0_combout  & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0]) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|write~0_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|write~0_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h55FF55FF557F557F;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y31_N17
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y31_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][129]~q  & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0] & 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0] & !\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg [0])) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][129]~q  & ( 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0] & !\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg [0]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0]),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0]),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid .lut_mask = 64'hF000F000C000C000;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y30_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_005|src_payload~2 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_005|src_payload~2_combout  = (\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [2])

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [2]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_005|src_payload~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~2 .lut_mask = 64'h0303030303030303;
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y30_N41
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_005|src_payload~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .power_up = "low";
// synopsys translate_on

// Location: FF_X11_Y30_N59
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~11_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][107]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][107] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y30_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~11 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~11_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][107]~q  ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][107]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~11 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~11 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y30_N44
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~11_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][107]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][107] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y33_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_006|src_payload~2 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_006|src_payload~2_combout  = (\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [2])

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [2]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_006|src_payload~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~2 .lut_mask = 64'h0303030303030303;
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y33_N44
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_006|src_payload~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .power_up = "low";
// synopsys translate_on

// Location: FF_X14_Y33_N29
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~11_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][107]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][107] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y33_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~11 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~11_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][107]~q  ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][107]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~11 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~11 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y33_N41
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~11_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][107]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][107] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y33_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~39 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~39_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][107]~q  ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0] & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][107]~q  & (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0] & 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q )) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][107]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~39_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~39 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~39 .lut_mask = 64'h001F001F00FF00FF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~39 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y26_N17
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~12_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][107]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][107] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y26_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|src_data[107] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|src_data [107] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [2] & ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & ( (\u0|hps_0|fpga_interfaces|h2f_AWID [2]) # (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]) ) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_ARID [2] & ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_AWID [2] ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_ARID [2] & ( !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & ( 
// \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [2]),
        .datad(gnd),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_ARID [2]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_004|src_data [107]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[107] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[107] .lut_mask = 64'h000055550F0F5F5F;
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[107] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y26_N13
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_004|src_data [107]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y26_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~12 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~12_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107] & ( 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][107]~q ) ) ) # ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107] & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][107]~q ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][107]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~12 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~12 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y26_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][107]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][107]~feeder_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~12_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~12_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][107]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][107]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][107]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][107]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y26_N44
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][107]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][107]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][107] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y30_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~114 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~114_combout  = ( !\u0|mm_interconnect_0|rsp_mux_001|src_payload~39_combout  & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][107]~q  & ( 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout  & (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][107]~q  & ((\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ) # 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout )))) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout  & (((\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ) # 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout )))) ) ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_payload~39_combout  & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][107]~q  & ( 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][107]~q ) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout ),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][107]~q ),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ),
        .datad(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ),
        .datae(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~39_combout ),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][107]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~114_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~114 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~114 .lut_mask = 64'hDDDD00000DDD0000;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~114 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y30_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_012|src_payload~2 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_012|src_payload~2_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [2] & ( \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_012|src_payload~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~2 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y30_N17
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_012|src_payload~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .power_up = "low";
// synopsys translate_on

// Location: FF_X14_Y30_N47
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~11_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][107]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][107] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y30_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~11 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~11_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][107]~q  ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][107]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~11 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~11 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y30_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][107]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][107]~feeder_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~11_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~11_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][107]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][107]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][107]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][107]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y30_N5
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][107]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][107]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][107] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y27_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_002|src_payload~2 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_002|src_payload~2_combout  = (\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [2])

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [2]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_002|src_payload~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~2 .lut_mask = 64'h000F000F000F000F;
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y27_N23
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_002|src_payload~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .power_up = "low";
// synopsys translate_on

// Location: FF_X13_Y27_N38
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~11_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][107]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][107] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y27_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~11 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~11_combout  = (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107])) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & 
// ((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][107]~q )))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][107]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~11 .lut_mask = 64'h0C3F0C3F0C3F0C3F;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~11 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y27_N17
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~11_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][107]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][107] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y27_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~38 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~38_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][107]~q  & 
// (((\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][107]~q  & ((\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][107]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~38_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~38 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~38 .lut_mask = 64'h003F003F007F007F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~38 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y24_N50
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~11_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][107]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][107] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y24_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_001|src_payload~2 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_001|src_payload~2_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [2] & ( \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_001|src_payload~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~2 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y24_N7
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_001|src_payload~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y24_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~11 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~11_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][107]~q  & ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg 
// [107] ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][107]~q  & ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107] & ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] ) ) ) # ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][107]~q  & ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107] & ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][107]~q ),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~11 .lut_mask = 64'h00000F0FF0F0FFFF;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~11 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y26_N2
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~11_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][107]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][107] .power_up = "low";
// synopsys translate_on

// Location: FF_X23_Y26_N56
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~12_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][107]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][107] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y24_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|src_data[107] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|src_data [107] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [2] & ( \u0|mm_interconnect_0|cmd_mux|saved_grant [1] ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARID [2] & ( \u0|mm_interconnect_0|cmd_mux|saved_grant [1] & ( 
// (\u0|hps_0|fpga_interfaces|h2f_AWID [2] & \u0|mm_interconnect_0|cmd_mux|saved_grant [0]) ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_ARID [2] & ( !\u0|mm_interconnect_0|cmd_mux|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_AWID [2] & 
// \u0|mm_interconnect_0|cmd_mux|saved_grant [0]) ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARID [2] & ( !\u0|mm_interconnect_0|cmd_mux|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_AWID [2] & \u0|mm_interconnect_0|cmd_mux|saved_grant [0]) ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [2]),
        .datad(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_ARID [2]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux|src_data [107]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|src_data[107] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|src_data[107] .lut_mask = 64'h000F000F000FFFFF;
defparam \u0|mm_interconnect_0|cmd_mux|src_data[107] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y24_N35
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux|src_data [107]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y26_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~12 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~12_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][107]~q  & ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg 
// [107] ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][107]~q  & ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107] & ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] ) ) ) # ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][107]~q  & ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107] & ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][107]~q ),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~12 .lut_mask = 64'h00000F0FF0F0FFFF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~12 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y26_N23
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~12_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][107]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][107] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y26_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~113 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~113_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][107]~q  & ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][107]~q  & ( 
// (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~38_combout  & (\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout  & ((\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ) # (\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout )))) ) ) 
// ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][107]~q  & ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][107]~q  & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~38_combout  & 
// ((\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ) # (\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ))) ) ) ) # ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][107]~q  & ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][107]~q  & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~38_combout  & \u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][107]~q  & ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][107]~q  & ( !\u0|mm_interconnect_0|rsp_mux_001|src_payload~38_combout  ) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ),
        .datab(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~38_combout ),
        .datac(!\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ),
        .datae(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][107]~q ),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][107]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~113_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~113 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~113 .lut_mask = 64'hCCCC00CC4C4C004C;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~113 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y33_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_003|src_payload~2 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_003|src_payload~2_combout  = (\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [2])

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [2]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_003|src_payload~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~2 .lut_mask = 64'h0303030303030303;
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y33_N14
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_003|src_payload~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .power_up = "low";
// synopsys translate_on

// Location: FF_X17_Y33_N5
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~11_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][107]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][107] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y33_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~11 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~11_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][107]~q  ) ) # ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][107]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~11 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~11 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y30_N14
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~11_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][107]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][107] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y30_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~115 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~115_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][107]~q  & ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout  & ( 
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~114_combout  & (\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~113_combout  & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][107]~q ) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout )))) ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][107]~q  & ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout  & ( 
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~114_combout  & (\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~113_combout  & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][107]~q ) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout )))) ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][107]~q  & ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout  & ( 
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~114_combout  & (\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~113_combout  & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][107]~q ) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout )))) ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~114_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout ),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][107]~q ),
        .datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~113_combout ),
        .datae(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][107]~q ),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~115_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~115 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~115 .lut_mask = 64'h0051000000510051;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~115 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y24_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_data[107] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|src_data [107] = ( \u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & ( ((\u0|hps_0|fpga_interfaces|h2f_AWID [2] & \u0|mm_interconnect_0|cmd_mux_018|saved_grant [0])) # (\u0|hps_0|fpga_interfaces|h2f_ARID [2]) ) ) # ( 
// !\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_AWID [2] & \u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]) ) )

        .dataa(gnd),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_AWID [2]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [2]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_018|src_data [107]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[107] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[107] .lut_mask = 64'h003300330F3F0F3F;
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[107] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y24_N8
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_018|src_data [107]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .power_up = "low";
// synopsys translate_on

// Location: FF_X27_Y24_N23
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~12_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][107]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][107] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y24_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~12 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~12_combout  = (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107])) # 
// (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][107]~q )))

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][107]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~12 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~12 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y26_N59
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~12_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][107]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][107] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y24_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_data[107] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|src_data [107] = ( \u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & ( \u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & ( (\u0|hps_0|fpga_interfaces|h2f_AWID [2]) # (\u0|hps_0|fpga_interfaces|h2f_ARID [2]) ) ) ) # ( 
// !\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & ( \u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_AWID [2] ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & ( 
// !\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [2] ) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARID [2]),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [2]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_015|src_data [107]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[107] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[107] .lut_mask = 64'h000055550F0F5F5F;
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[107] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y24_N50
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_015|src_data [107]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .power_up = "low";
// synopsys translate_on

// Location: FF_X19_Y24_N8
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~12_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][107]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][107] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y24_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~12 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~12_combout  = (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107])) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & 
// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][107]~q )))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][107]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~12 .lut_mask = 64'h0C3F0C3F0C3F0C3F;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~12 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y26_N52
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~12_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][107]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][107] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y26_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~112 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~112_combout  = ( \u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout  & ( ((\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout  & \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][107]~q )) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][107]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout  & ( (\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout  & 
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][107]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout ),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][107]~q ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][107]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~112_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~112 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~112 .lut_mask = 64'h0303030303FF03FF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~112 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y32_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_021|src_payload~2 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_021|src_payload~2_combout  = (\u0|hps_0|fpga_interfaces|h2f_ARID [2] & \u0|mm_interconnect_0|cmd_mux_021|saved_grant [1])

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [2]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_021|src_payload~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~2 .lut_mask = 64'h000F000F000F000F;
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y32_N14
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_021|src_payload~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .power_up = "low";
// synopsys translate_on

// Location: FF_X27_Y32_N44
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~11_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][107]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][107] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y32_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~11 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~11_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][107]~q  ) ) # ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][107]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~11 .lut_mask = 64'h3333333300FF00FF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~11 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y32_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][107]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][107]~feeder_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~11_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~11_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][107]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][107]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][107]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][107]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y32_N28
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][107]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][107]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][107] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y32_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_019|src_payload~2 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_019|src_payload~2_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [2] & ( \u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_019|src_payload~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~2 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y32_N19
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_019|src_payload~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .power_up = "low";
// synopsys translate_on

// Location: FF_X22_Y32_N50
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~11_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][107]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][107] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y32_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~11 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~11_combout  = (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107])) # 
// (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][107]~q )))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][107]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~11 .lut_mask = 64'h0C3F0C3F0C3F0C3F;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~11 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y32_N20
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~11_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][107]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][107] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y25_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_data[107] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|src_data [107] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [2] & ( ((\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [2])) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_ARID [2] & ( (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [2]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_AWID [2]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_008|src_data [107]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[107] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[107] .lut_mask = 64'h005500550F5F0F5F;
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[107] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y25_N17
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_008|src_data [107]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .power_up = "low";
// synopsys translate_on

// Location: FF_X18_Y28_N38
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~12_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][107]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][107] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y28_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~12 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~12_combout  = (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107])) 
// # (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][107]~q )))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][107]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~12 .lut_mask = 64'h0C3F0C3F0C3F0C3F;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~12 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y28_N47
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~12_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][107]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][107] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y32_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~108 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~108_combout  = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][107]~q  & ( (!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout  & 
// ((!\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ) # ((!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout  & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][107]~q )))) # 
// (\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout  & (!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout  & ((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][107]~q )))) ) ) # ( 
// !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][107]~q  & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout  & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][107]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout ),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][107]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][107]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~108_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~108 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~108 .lut_mask = 64'h00CC00CCA0ECA0EC;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~108 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y32_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_020|src_payload~2 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_020|src_payload~2_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [2] & ( \u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_020|src_payload~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~2 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y32_N14
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_020|src_payload~2_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .power_up = "low";
// synopsys translate_on

// Location: FF_X23_Y32_N5
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~11_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][107]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][107] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y32_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~11 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~11_combout  = (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107])) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & 
// ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][107]~q )))

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][107]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~11 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~11 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y32_N29
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~11_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][107]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][107] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y32_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~109 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~109_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout  & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~108_combout  & 
// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][107]~q ) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ))) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout  & ( 
// (!\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~108_combout  & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][107]~q  & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][107]~q ) # 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][107]~q ),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ),
        .datac(!\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~108_combout ),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][107]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~109_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~109 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~109 .lut_mask = 64'hB000B000B0B0B0B0;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~109 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y23_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_data[107] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_data [107] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [2] & ( ((\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [2])) # (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_AWID [2] & ( (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [2]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [2]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_014|src_data [107]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[107] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[107] .lut_mask = 64'h0505050537373737;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[107] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y23_N29
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_014|src_data [107]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .power_up = "low";
// synopsys translate_on

// Location: FF_X23_Y23_N59
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~12_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][107]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][107] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y23_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~12 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~12_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][107]~q  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107] ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][107]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~12 .lut_mask = 64'h5555555500FF00FF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~12 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y23_N32
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~12_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][107]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][107] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y23_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|src_data[107] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|src_data [107] = (!\u0|hps_0|fpga_interfaces|h2f_AWID [2] & (((\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [2])))) # (\u0|hps_0|fpga_interfaces|h2f_AWID [2] & 
// (((\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [2])) # (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0])))

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_AWID [2]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [2]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_011|src_data [107]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[107] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[107] .lut_mask = 64'h111F111F111F111F;
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[107] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y23_N29
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_011|src_data [107]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .power_up = "low";
// synopsys translate_on

// Location: FF_X21_Y23_N56
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~12_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][107]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][107] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y23_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~12 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~12_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][107]~q  ) ) # ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][107]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~12 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~12 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y23_N5
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~12_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][107]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][107] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y23_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~111 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~111_combout  = ( \u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout  & ( ((\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout  & \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][107]~q 
// )) # (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][107]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout  & ( (\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout  & 
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][107]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][107]~q ),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][107]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~111_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~111 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~111 .lut_mask = 64'h0505050505FF05FF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~111 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y33_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_013|src_payload~2 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_013|src_payload~2_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [2] & ( \u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_013|src_payload~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~2 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y33_N20
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_013|src_payload~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .power_up = "low";
// synopsys translate_on

// Location: FF_X18_Y33_N14
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~11_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][107]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][107] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y33_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~11 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~11_combout  = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][107]~q  ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][107]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~11 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~11 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y31_N11
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~11_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][107]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][107] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y29_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|src_data[107] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|src_data [107] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [2] & ( ((\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [2])) # (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_AWID [2] & ( (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [2]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
        .datac(gnd),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [2]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_007|src_data [107]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[107] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[107] .lut_mask = 64'h0055005533773377;
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[107] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y29_N8
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_007|src_data [107]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .power_up = "low";
// synopsys translate_on

// Location: FF_X21_Y29_N17
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~12_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][107]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][107] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y29_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~12 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~12_combout  = (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107])) 
// # (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][107]~q )))

        .dataa(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
        .datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][107]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~12 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~12 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y31_N26
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~12_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][107]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][107] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y31_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~106 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~106_combout  = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][107]~q  & ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][107]~q  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout ) # ((!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout  & !\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout )) ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][107]~q  & ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][107]~q  & ( (!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout  & 
// !\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ) ) ) ) # ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][107]~q  & ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][107]~q  & ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout  ) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout ),
        .datab(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][107]~q ),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][107]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~106_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~106 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~106 .lut_mask = 64'h0000F0F08888F8F8;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~106 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y33_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_017|src_payload~2 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_017|src_payload~2_combout  = (\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [2])

        .dataa(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [2]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_017|src_payload~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~2 .lut_mask = 64'h0055005500550055;
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y33_N28
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_017|src_payload~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .power_up = "low";
// synopsys translate_on

// Location: FF_X18_Y33_N17
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~11_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][107]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][107] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y33_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~11 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~11_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][107]~q  ) ) # ( 
// !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107] ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][107]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~11 .lut_mask = 64'h5555555500FF00FF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~11 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y33_N19
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~11_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][107]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][107] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y31_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_016|src_payload~2 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_016|src_payload~2_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [2] & ( \u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_016|src_payload~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~2 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y31_N55
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_016|src_payload~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .power_up = "low";
// synopsys translate_on

// Location: FF_X19_Y31_N47
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~11_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][107]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][107] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y31_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~11 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~11_combout  = (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107])) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & 
// ((\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][107]~q )))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][107]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~11 .lut_mask = 64'h0C3F0C3F0C3F0C3F;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~11 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y31_N17
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~11_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][107]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][107] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y31_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~107 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~107_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][107]~q  & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout  & 
// (!\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~106_combout  & ((!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ) # (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][107]~q )))) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][107]~q  & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~106_combout  & ((!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ) # 
// (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][107]~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout ),
        .datab(!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ),
        .datac(!\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~106_combout ),
        .datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][107]~q ),
        .datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][107]~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~107_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~107 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~107 .lut_mask = 64'hF0C05040F0C05040;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~107 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y24_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|src_data[107] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|src_data [107] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [2] & ( ((\u0|hps_0|fpga_interfaces|h2f_ARID [2] & \u0|mm_interconnect_0|cmd_mux_009|saved_grant [1])) # (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_AWID [2] & ( (\u0|hps_0|fpga_interfaces|h2f_ARID [2] & \u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [2]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_009|src_data [107]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[107] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[107] .lut_mask = 64'h000F000F333F333F;
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[107] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y24_N14
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_009|src_data [107]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .power_up = "low";
// synopsys translate_on

// Location: FF_X19_Y24_N59
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~12_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][107]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][107] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y24_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~12 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~12_combout  = ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][107]~q  ) ) # ( 
// !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][107]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~12 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~12 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y24_N20
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~12_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][107]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][107] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y24_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_data[107] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_data [107] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [2] & ( ((\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [2])) # (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_ARID [2] & ( (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [2]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [2]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_010|src_data [107]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[107] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[107] .lut_mask = 64'h0505050537373737;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[107] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y24_N38
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_010|src_data [107]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .power_up = "low";
// synopsys translate_on

// Location: FF_X22_Y24_N2
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~12_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][107]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][107] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y24_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~12 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~12_combout  = (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107])) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & 
// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][107]~q )))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][107]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~12 .lut_mask = 64'h0C3F0C3F0C3F0C3F;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~12 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y24_N50
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][107] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~12_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][107]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][107] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y24_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~110 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~110_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][107]~q  & ( ((\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout  & 
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][107]~q )) # (\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][107]~q  & ( 
// (\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout  & \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][107]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ),
        .datac(!\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout ),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][107]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][107]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~110_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~110 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~110 .lut_mask = 64'h000F000F333F333F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~110 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y28_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[107] (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data [107] = ( \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~107_combout  & ( \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~110_combout  ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~107_combout  & ( 
// \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~110_combout  ) ) # ( \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~107_combout  & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~110_combout  & ( 
// (!\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~115_combout ) # (((!\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~109_combout ) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~111_combout )) # 
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~112_combout )) ) ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~107_combout  & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~110_combout  ) )

        .dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~115_combout ),
        .datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~112_combout ),
        .datac(!\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~109_combout ),
        .datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~111_combout ),
        .datae(!\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~107_combout ),
        .dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~110_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data [107]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107] .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107] .lut_mask = 64'hFFFFFBFFFFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107] .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y36_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & ( !\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & ( (!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]) # (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .lut_mask = 64'hFCFCFCFCCCCCCCCC;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y36_N44
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .power_up = "low";
// synopsys translate_on

// Location: FF_X18_Y36_N23
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X18_Y36_N59
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";
// synopsys translate_on

// Location: FF_X18_Y36_N32
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y36_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|WideOr0~0_combout  = ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & 
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ) # 
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )))) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|WideOr0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|WideOr0~0 .lut_mask = 64'hA080000000000000;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|WideOr0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y36_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout  = !\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .lut_mask = 64'hCCCCCCCCCCCCCCCC;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y36_N8
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";
// synopsys translate_on

// Location: FF_X18_Y36_N41
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y36_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  = ( 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q  & ( 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q  & (((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0_combout  & 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|WideOr0~0_combout )) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]))) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q  ) ) # 
// ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q  & ( 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q  & (((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0_combout  & 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|WideOr0~0_combout )) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]))) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|WideOr0~0_combout ),
        .datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .lut_mask = 64'h00002303FFFF2303;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y36_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~1_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|WideOr0~0_combout  & ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|WideOr0~0_combout  & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0_combout  & !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|WideOr0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~1 .lut_mask = 64'h44444444CCCCCCCC;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y36_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~2_combout  = ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & ( 
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~2 .lut_mask = 64'hC000C00000000000;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y36_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~3_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~2_combout  & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & 
// ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0_combout ))) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~2_combout  & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0_combout  & !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~3 .lut_mask = 64'h44444444C4C4C4C4;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y36_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~3_combout  & (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q  & 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~3_combout ))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~3_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .lut_mask = 64'h00F300F300C000C0;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y36_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ))) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ) ) 
// )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h00CC00CC00800080;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y36_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  = ( \u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] & ( 
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  & ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) # 
// ((!\u0|mm_interconnect_0|cmd_mux_016|last_cycle~0_combout ) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout )))) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] & ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_016|last_cycle~0_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .lut_mask = 64'hF0F0F0F0E0F0E0F0;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y36_N13
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y36_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARLEN [0] & ( 
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] $ 
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0] & ( 
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] $ 
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])))) # 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1])) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .lut_mask = 64'h35C535C530C030C0;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y36_N32
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y36_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout  = ( 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])) # 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout )))) ) ) ) # 
// ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])) # 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout )))) ) ) ) # 
// ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # 
// ((\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout )) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),
        .datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .lut_mask = 64'h0005AAAF888D2227;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y36_N56
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y36_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] $ 
// (((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]))) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .lut_mask = 64'hF0F0F0F03CF03CF0;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y36_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout  = ( 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( (\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .lut_mask = 64'hFF00FF0005050505;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y36_N41
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y36_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  = ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg 
// [4] & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & 
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .lut_mask = 64'h3000300000000000;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y36_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout  = ( 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) # 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ))) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) # 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .lut_mask = 64'h01F101F1F101F101;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y36_N8
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y36_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout  = ( 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  
// & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) # 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout  & (\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]))) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout 
//  & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) # 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout  & (\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]))) ) ) ) # ( 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout 
//  & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout  & \u0|mm_interconnect_0|cmd_mux_016|saved_grant [1])) ) ) 
// ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout  & \u0|mm_interconnect_0|cmd_mux_016|saved_grant [1])) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .lut_mask = 64'h0101ABABAB0101AB;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y36_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout  = ( 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout  & ( 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout  & ( 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout  & ( 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout  & ( 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  ) ) ) # ( 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout  & ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout  & ( 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout  & ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout  & ( 
// ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout  & 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout  & 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ))) # 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),
        .datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .lut_mask = 64'h5D55555555555555;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y36_N26
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y36_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & 
// ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) # (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~1_combout ))) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  ) 
// )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .lut_mask = 64'hAAAAAAAAAAA0AAA0;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y36_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout  & ( 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h0000000033003300;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y36_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  = ( 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .lut_mask = 64'h0000000000F000F0;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y36_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout  = ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout  & ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0 .lut_mask = 64'hF0F0F0F000000000;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y36_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  = 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~1_combout )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~1_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h0303030303030303;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y36_N50
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y36_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  = ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg 
// [4] & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & 
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h00A000A000000000;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y36_N41
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y36_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout  = ( 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) # 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) ) ) ) # ( 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  
// $ (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  
// $ (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .lut_mask = 64'h0FF00FF055FF00AA;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y36_N26
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y36_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout  = ( 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  
// & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (((\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) # 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg 
// [2]) # ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )))) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout 
//  & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) # 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg 
// [2] & (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ))) ) ) ) # ( 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout 
//  & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) # 
// ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # 
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  
// & (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .lut_mask = 64'h0404FEFEAE0454FE;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y36_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout  = ( 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout  & ( 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout  & ( 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ) ) ) ) 
// # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout  & ( 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout  & ( 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ) ) ) ) 
// # ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout  & ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout  & ( 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ) ) ) ) 
// # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout  & ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout  & ( 
// ((\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout  & ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout ) # 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout )))) # 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout ),
        .datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .lut_mask = 64'h7737777777777777;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y36_N44
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y36_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  = ( 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ( 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ( 
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q 
// ) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ( 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0_combout  & 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|WideOr0~0_combout )) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) # 
// ((\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0_combout  & 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|WideOr0~0_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|WideOr0~0_combout ),
        .datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'hBAAA3000BBBB3333;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y36_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & 
// ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) # 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & (((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q 
// )))) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) 
// )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .lut_mask = 64'h0C0C0C0CAC0CAC0C;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y36_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  = ( 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & 
// ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )) # 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~1_combout ))))) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & 
// ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )) # 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~1_combout ))))) ) ) ) # ( 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & 
// ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )) # 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~1_combout ))))) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & 
// ((\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) # 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~1_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .lut_mask = 64'h7700740074007400;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y36_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_016|packet_in_progress~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_016|packet_in_progress~0_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  & ( 
// ((\u0|mm_interconnect_0|cmd_mux_016|last_cycle~0_combout  & \u0|mm_interconnect_0|cmd_mux_016|saved_grant [1])) # (\u0|mm_interconnect_0|cmd_mux_016|packet_in_progress~q ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  & ( (\u0|mm_interconnect_0|cmd_mux_016|packet_in_progress~q  & ((!\u0|mm_interconnect_0|cmd_mux_016|last_cycle~0_combout ) # 
// (!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]))) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_016|last_cycle~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_016|packet_in_progress~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_016|packet_in_progress~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_016|packet_in_progress~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_016|packet_in_progress~0 .lut_mask = 64'h00FA00FA05FF05FF;
defparam \u0|mm_interconnect_0|cmd_mux_016|packet_in_progress~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y36_N50
dffeas \u0|mm_interconnect_0|cmd_mux_016|packet_in_progress (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_016|packet_in_progress~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_016|packet_in_progress~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_016|packet_in_progress .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_016|packet_in_progress .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y36_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_016|update_grant~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_016|update_grant~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] & ( (!\u0|mm_interconnect_0|cmd_mux_016|last_cycle~0_combout  & ((!\u0|mm_interconnect_0|cmd_mux_016|packet_in_progress~q ))) # 
// (\u0|mm_interconnect_0|cmd_mux_016|last_cycle~0_combout  & (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] & ( 
// !\u0|mm_interconnect_0|cmd_mux_016|packet_in_progress~q  ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_016|packet_in_progress~q ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_016|last_cycle~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_016|update_grant~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_016|update_grant~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_016|update_grant~0 .lut_mask = 64'hF0F0F0F0F0CCF0CC;
defparam \u0|mm_interconnect_0|cmd_mux_016|update_grant~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y36_N20
dffeas \u0|mm_interconnect_0|cmd_mux_016|saved_grant[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_016|last_cycle~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|cmd_mux_016|update_grant~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_016|saved_grant[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_016|saved_grant[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y36_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout  = ( \u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] & ( 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  
// & \u0|mm_interconnect_0|cmd_mux_016|last_cycle~0_combout )) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_016|last_cycle~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .lut_mask = 64'h0000000000030003;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y36_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout  & 
// ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & ((\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q 
// ) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ))) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout  & ( 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// (((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q )) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .lut_mask = 64'h0545054505550555;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y36_N2
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y36_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  = 
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  
// $ (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))) # 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) # 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .lut_mask = 64'h8608860886088608;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y36_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & ( 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & ( 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) ) # ( 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & ( 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
        .datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .lut_mask = 64'h0000333333003300;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y36_N56
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y36_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] & ( 
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & (((\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  
// & \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout )))) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q 
//  & (((\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout )) # (\u0|mm_interconnect_0|cmd_mux_016|last_cycle~0_combout ))) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] & ( 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout 
// ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_016|last_cycle~0_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .lut_mask = 64'h000F000F111F111F;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y36_N17
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y36_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ( 
// ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|WideOr0~0_combout )) # 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|WideOr0~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hF5FFF5FFF0F0F0F0;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y36_N17
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y36_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout  = 
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (((\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])))) # 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) # 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg 
// [2]))))

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .lut_mask = 64'h0EF40EF40EF40EF4;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y36_N35
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y36_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout  = ( 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg 
// [2] ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] ) ) ) # ( 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] $ 
// (((\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]) # 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .lut_mask = 64'h00FFA05F00FFCCCC;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y36_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout  = ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & ( 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h000F000F00000000;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y36_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout  = ( 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout  & ( 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout  & ( 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout  ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout  & ( 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout  & ( 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout  ) ) ) # ( 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout  & ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout  & ( 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout  ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout  & ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout  & ( 
// ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout  & 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout  & \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout ))) # 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout ),
        .datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h333B333333333333;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y36_N20
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y36_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout  = ( 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] $ 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) # 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg 
// [2])) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .lut_mask = 64'h00FF00FFE44EE44E;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y36_N32
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";
// synopsys translate_on

// Location: FF_X15_Y36_N5
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][75] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][75]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y36_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~6 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~6_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) # 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][75]~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][75]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][75]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h003300330C3F0C3F;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y37_N32
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][75] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~6_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][75]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";
// synopsys translate_on

// Location: FF_X15_Y36_N17
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][74] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~7_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][74]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y36_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~7 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~7_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) # 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][74]~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & 
// ((\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][74]~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][74]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h0C3F0C3F44774477;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y37_N56
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~7_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y37_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74]~q  & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout  & 
// ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][75]~q )) # 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ((\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))))) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74]~q  & ( 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][75]~q )) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))))) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74]~q  & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout  & 
// ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][75]~q )) # 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ((\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))))) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74]~q  & ( 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][75]~q )) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))))) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h4450440511501105;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y37_N38
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";
// synopsys translate_on

// Location: FF_X15_Y36_N56
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][78] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][78]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y36_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~3_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6])) # 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][78]~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][78]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][78]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h003300330C3F0C3F;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y37_N35
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][78] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~3_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][78]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";
// synopsys translate_on

// Location: FF_X15_Y36_N59
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][77] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][77]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y36_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~4 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~4_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])) # 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][77]~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][77]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][77]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~4 .lut_mask = 64'h003300330C3F0C3F;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y37_N59
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][77] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~4_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][77]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";
// synopsys translate_on

// Location: FF_X15_Y36_N2
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][76] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][76]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y36_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~5 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~5_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4])) # 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][76]~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][76]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][76]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h003300330C3F0C3F;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y37_N23
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][76] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~5_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][76]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y37_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~0_combout  = ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][76]~q  & ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][75]~q  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][77]~q  & !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74]~q ) ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][77]~q ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][76]~q ),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~0 .lut_mask = 64'hC0C0000000000000;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y37_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~0_combout  = !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [4] $ 
// (((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [3])))

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h66CC66CC66CC66CC;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y37_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~0_combout  & ( 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74]~q  & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][76]~q  & (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout  & 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout )) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~0_combout  & ( 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74]~q  & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout  & 
// ((\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][76]~q ))) ) ) ) # ( 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~0_combout  & ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74]~q  & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout  & 
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][76]~q  $ (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][75]~q 
// )))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~0_combout  & ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74]~q  & ( 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][76]~q  $ (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][75]~q )) # 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~0_combout ),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h090F0900050F0500;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y37_N26
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y37_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~2_combout  = !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [5] $ 
// (((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [3]))))

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h7F807F807F807F80;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y37_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~1_combout  = !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][77]~q  $ (((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][76]~q  & 
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74]~q  & !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][75]~q ))))

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][77]~q ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h6CCC6CCC6CCC6CCC;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y37_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~1_combout  & ( 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout  & (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~2_combout )) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~1_combout  & ( 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ) # 
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~2_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~2_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h5550555005000500;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y37_N47
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y37_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~1_combout  = ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( 
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [3])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~1 .lut_mask = 64'hC000C00000000000;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y37_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~1_combout  & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout  & 
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][78]~q  $ 
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~0_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~1_combout  & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][78]~q  $ 
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~0_combout )) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~1_combout  & ( 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][78]~q  $ (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~0_combout )) # 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~1_combout  & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout  & 
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][78]~q  $ 
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~0_combout )))) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][78]~q ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h1200123312331200;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y37_N2
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y37_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~1_combout  = ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( 
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [5])) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'hA000A00000000000;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y37_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~0_combout  & ( 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~1_combout  & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout  & 
// ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][78]~q ))) # 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [6])))) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~0_combout  & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~1_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout )) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~0_combout  & ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~1_combout  & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][78]~q  & \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][78]~q ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout ),
        .datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~0_combout ),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h000000C0002200E2;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y37_N7
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y37_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_busy~q  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~1_combout ) # ((\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [7]) # 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [2])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h00000000CFFFCFFF;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y37_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74]~q  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~2_combout  & (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout )) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74]~q  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~2_combout  & \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h00AA00AA000A000A;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y37_N53
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y37_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~2_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_busy~q  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y36_N47
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";
// synopsys translate_on

// Location: FF_X18_Y35_N14
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~2_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][66]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y35_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~2_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][66]~q  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][66]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~2 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y35_N26
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~2_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][66]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y37_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~0_combout  = ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][76]~q  & ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_busy~q  & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][78]~q  & (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][75]~q  & 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74]~q  & !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][77]~q ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][78]~q ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][77]~q ),
        .datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][76]~q ),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h0800000000000000;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y37_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~0_combout  & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|comb~0_combout  & 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][66]~q ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~0_combout  & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][66]~q  & 
// ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~2_combout ) # ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~1_combout ) # 
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|comb~0_combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|comb~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][66]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h00FE00FE00F000F0;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y35_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|write~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|write~0_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0_combout  & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~0_combout  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0_combout  & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|WideOr0~0_combout  & \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~0_combout ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|WideOr0~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|write~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|write~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h000F000F00FF00FF;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|write~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y35_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used[1]~0_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|write~0_combout  & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0_combout  & 
// (((\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [0])))) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0_combout  & ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout  
// & ((\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]))) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout  & (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [0])))) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|write~0_combout  & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0_combout ) # 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [0]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|write~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used[1]~0 .lut_mask = 64'h00BB00BB0B4F0B4F;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used[1]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y35_N53
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X18_Y35_N20
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y35_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~0_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & ( 
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q )) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~0 .lut_mask = 64'h020202020A0A0A0A;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y35_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter~0_combout  = ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|WideOr0~0_combout  & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~0_combout  & 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override~q  & !\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter [0])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~0_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override~q ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|WideOr0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter~0 .lut_mask = 64'h0300030000000000;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y35_N41
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y35_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg~0_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override~q  & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter 
// [0] & (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|WideOr0~0_combout  & \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~0_combout )) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter [0]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|WideOr0~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg~0 .lut_mask = 64'h0000000000300030;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y35_N44
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X18_Y35_N38
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][129] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][129]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y35_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~1_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|WideOr0~0_combout  & ( ((\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][129]~q )) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~0_combout ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|WideOr0~0_combout  & ( 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][129]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~0_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][129]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|WideOr0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h000F000F333F333F;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y35_N56
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][129] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][129]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y35_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|read~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|read~0_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg [0] & ( (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & 
// ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [0]) # (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][129]~q ))) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg [0] & ( 
// (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [0] & ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [0]) # 
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][129]~q )))) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [0]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [0]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|read~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|read~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|read~0 .lut_mask = 64'h0504050455445544;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|read~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y35_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used[1]~1_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [1] & ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|read~0_combout  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [1] & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|read~0_combout  & (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [0] & 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg [0])) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|read~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [0]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg [0]),
        .datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [1]),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used[1]~1 .lut_mask = 64'h000AAAAA000AAAAA;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used[1]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y35_N14
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y35_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used[0]~0_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [0]) # 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|read~0_combout ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [1] & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|read~0_combout  & 
// ((\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [0]) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg [0]))) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|read~0_combout  & 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg [0] & \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [0])) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|read~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg [0]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h0AAF0AAF55FF55FF;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y35_N47
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y35_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|comb~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|comb~0_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [0] & ( ((\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [0]) # 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][129]~q )) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg [0]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg [0]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|comb~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|comb~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|comb~0 .lut_mask = 64'h000000003FFF3FFF;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|comb~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y35_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|comb~0_combout  & ( \u0|hps_0|fpga_interfaces|h2f_RREADY [0] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|comb~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y35_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used[0]~1_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|write~0_combout  ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|write~0_combout  & ( 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [0] & ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0_combout ) # ((\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]) # 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|write~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h00BF00BFFFFFFFFF;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y35_N8
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y35_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout  = ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg [0] & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [0] & 
// ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [0]) # (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][129]~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [0]),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [0]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid .lut_mask = 64'hC8C8C8C800000000;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y33_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_013|src_payload~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_013|src_payload~1_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [1] & ( \u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_013|src_payload~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~1 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y33_N8
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_013|src_payload~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .power_up = "low";
// synopsys translate_on

// Location: FF_X18_Y33_N41
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~10_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][106]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][106] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y33_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~10 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~10_combout  = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][106]~q  ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][106]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~10 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~10 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y31_N32
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~10_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][106]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][106] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y29_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|src_data[106] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|src_data [106] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [1] & ( ((\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [1])) # (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_ARID [1] & ( (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [1]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_007|src_data [106]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[106] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[106] .lut_mask = 64'h0303030357575757;
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[106] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y29_N29
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_007|src_data [106]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .power_up = "low";
// synopsys translate_on

// Location: FF_X18_Y29_N59
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~11_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][106]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][106] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y29_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~11 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~11_combout  = (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106])) 
// # (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][106]~q )))

        .dataa(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
        .datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][106]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~11 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~11 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y29_N29
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~11_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][106]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][106] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y31_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~96 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~96_combout  = ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][106]~q  & ( (!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout  & 
// ((!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ) # ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout  & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][106]~q )))) # 
// (\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout  & (((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout  & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][106]~q )))) ) ) # ( 
// !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][106]~q  & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout  & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][106]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout ),
        .datab(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][106]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][106]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~96_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~96 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~96 .lut_mask = 64'h00F000F088F888F8;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~96 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y36_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_016|src_payload~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_016|src_payload~1_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [1] & ( \u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_016|src_payload~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~1 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y36_N26
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_016|src_payload~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .power_up = "low";
// synopsys translate_on

// Location: FF_X17_Y36_N2
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~10_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][106]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][106] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y36_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~10 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~10_combout  = (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106])) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & 
// ((\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][106]~q )))

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][106]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~10 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~10 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y30_N41
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~10_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][106]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][106] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y33_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_017|src_payload~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_017|src_payload~1_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [1] & ( \u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_017|src_payload~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~1 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y33_N32
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_017|src_payload~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .power_up = "low";
// synopsys translate_on

// Location: FF_X17_Y33_N41
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~10_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][106]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][106] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y33_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~10 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~10_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][106]~q  ) ) # ( 
// !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
        .datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][106]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~10 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~10 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y33_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][106]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][106]~feeder_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~10_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~10_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][106]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][106]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][106]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][106]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y33_N52
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][106]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][106]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][106] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y30_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~97 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~97_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][106]~q  & ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][106]~q  & ( 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout  & (!\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~96_combout  & !\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout )) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][106]~q  & ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][106]~q  & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~96_combout  & 
// !\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][106]~q  & ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][106]~q  & ( 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout  & !\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~96_combout ) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][106]~q  & ( 
// !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][106]~q  & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~96_combout  ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout ),
        .datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~96_combout ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][106]~q ),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][106]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~97_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~97 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~97 .lut_mask = 64'hCCCC4444C0C04040;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~97 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y30_N2
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~10_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][106]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][106] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y30_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_012|src_payload~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_012|src_payload~1_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [1] & ( \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_012|src_payload~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~1 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y30_N13
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_012|src_payload~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y30_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~10 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~10_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][106]~q  & ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106] ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][106]~q  & ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106] & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] ) ) ) # ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][106]~q  & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106] & ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][106]~q ),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~10 .lut_mask = 64'h00000F0FF0F0FFFF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~10 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y30_N56
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~10_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][106]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][106] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y23_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_001|src_payload~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_001|src_payload~1_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [1] & ( \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_001|src_payload~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~1 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y23_N17
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_001|src_payload~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .power_up = "low";
// synopsys translate_on

// Location: FF_X15_Y23_N11
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~10_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][106]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][106] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y23_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~10 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~10_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][106]~q  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][106]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~10 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~10 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y26_N26
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~10_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][106]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][106] .power_up = "low";
// synopsys translate_on

// Location: FF_X13_Y27_N5
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~10_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][106]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][106] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y27_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_002|src_payload~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_002|src_payload~1_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [1] & ( \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_002|src_payload~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~1 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y27_N25
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_002|src_payload~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y27_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~10 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~10_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106] & ( 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][106]~q ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106] & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][106]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][106]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~10 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~10 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y27_N50
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~10_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][106]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][106] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y27_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~36 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~36_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][106]~q  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0] & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][106]~q  & (((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q  & 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0])) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0]),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][106]~q ),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~36_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~36 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~36 .lut_mask = 64'h010F010F0F0F0F0F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~36 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y26_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~103 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~103_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][106]~q  & ( !\u0|mm_interconnect_0|rsp_mux_001|src_payload~36_combout  & ( 
// (\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout  & (((!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][106]~q ) # (\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout )) # 
// (\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][106]~q  & ( !\u0|mm_interconnect_0|rsp_mux_001|src_payload~36_combout  & ( 
// ((!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][106]~q ) # (\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout )) # (\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][106]~q ),
        .datad(!\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ),
        .datae(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][106]~q ),
        .dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~36_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~103_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~103 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~103 .lut_mask = 64'hF5FF313300000000;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~103 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y33_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_006|src_payload~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_006|src_payload~1_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [1] & ( \u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_006|src_payload~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~1 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y33_N11
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_006|src_payload~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .power_up = "low";
// synopsys translate_on

// Location: FF_X14_Y33_N26
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~10_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][106]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][106] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y33_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~10 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~10_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][106]~q  ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][106]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~10 .lut_mask = 64'h3333333300FF00FF;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~10 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y33_N5
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~10_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][106]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][106] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y33_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~37 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~37_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][106]~q  & 
// (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q )) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]))) ) ) 
// # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][106]~q  & ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][106]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~37_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~37 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~37 .lut_mask = 64'h005F005F007F007F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~37 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y30_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_005|src_payload~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_005|src_payload~1_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [1] & ( \u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_005|src_payload~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~1 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y30_N38
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_005|src_payload~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .power_up = "low";
// synopsys translate_on

// Location: FF_X11_Y30_N35
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~10_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][106]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][106] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y30_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~10 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~10_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][106]~q  ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106] ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][106]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~10 .lut_mask = 64'h5555555500FF00FF;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~10 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y30_N20
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~10_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][106]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][106] .power_up = "low";
// synopsys translate_on

// Location: FF_X18_Y26_N56
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~11_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][106]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][106] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y26_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|src_data[106] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|src_data [106] = ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & ( (\u0|hps_0|fpga_interfaces|h2f_AWID [1]) # (\u0|hps_0|fpga_interfaces|h2f_ARID [1]) ) ) ) # ( 
// !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_AWID [1] ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & ( 
// !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [1] ) ) )

        .dataa(gnd),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARID [1]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [1]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_004|src_data [106]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[106] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[106] .lut_mask = 64'h000033330F0F3F3F;
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[106] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y26_N13
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_004|src_data [106]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y26_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~11 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~11_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106] & ( 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][106]~q ) ) ) # ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106] & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][106]~q ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][106]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~11 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~11 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y26_N43
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~11_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][106]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][106] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y30_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~104 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~104_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][106]~q  & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][106]~q  & ( 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout  & (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~37_combout  & ((\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ) # 
// (\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][106]~q  & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][106]~q  & ( 
// (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~37_combout  & ((\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ) # (\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ))) ) ) ) # ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][106]~q  & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][106]~q  & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout  & 
// !\u0|mm_interconnect_0|rsp_mux_001|src_payload~37_combout ) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][106]~q  & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][106]~q  & ( 
// !\u0|mm_interconnect_0|rsp_mux_001|src_payload~37_combout  ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout ),
        .datab(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~37_combout ),
        .datac(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ),
        .datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][106]~q ),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][106]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~104_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~104 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~104 .lut_mask = 64'hCCCC44440CCC0444;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~104 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y33_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_003|src_payload~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_003|src_payload~1_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [1] & ( \u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_003|src_payload~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~1 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y33_N11
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_003|src_payload~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .power_up = "low";
// synopsys translate_on

// Location: FF_X17_Y33_N2
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~10_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][106]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][106] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y33_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~10 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~10_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][106]~q  ) ) # ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][106]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~10 .lut_mask = 64'h3333333300FF00FF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~10 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y30_N32
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~10_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][106]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][106] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y30_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~105 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~105_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][106]~q  & ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout  & ( 
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~103_combout  & (\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~104_combout  & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][106]~q ) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout )))) ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][106]~q  & ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout  & ( 
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~103_combout  & (\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~104_combout  & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][106]~q ) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout )))) ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][106]~q  & ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout  & ( 
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~103_combout  & (\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~104_combout  & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][106]~q ) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout )))) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][106]~q ),
        .datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~103_combout ),
        .datac(!\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~104_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout ),
        .datae(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][106]~q ),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~105_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~105 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~105 .lut_mask = 64'h0203000002030203;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~105 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y32_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_021|src_payload~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_021|src_payload~1_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [1] & ( \u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_021|src_payload~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~1 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y32_N38
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_021|src_payload~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .power_up = "low";
// synopsys translate_on

// Location: FF_X27_Y32_N32
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~10_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][106]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][106] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y32_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~10 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~10_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][106]~q  ) ) # ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][106]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~10 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~10 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y32_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][106]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][106]~feeder_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~10_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~10_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][106]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][106]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][106]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][106]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y32_N19
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][106]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][106]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][106] .power_up = "low";
// synopsys translate_on

// Location: FF_X22_Y36_N26
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~10_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][106]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][106] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y36_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_019|src_payload~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_019|src_payload~1_combout  = ( \u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [1] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_019|src_payload~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~1 .lut_mask = 64'h000000000000FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y36_N26
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_019|src_payload~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y36_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~10 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~10_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][106]~q  & ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106] ) ) # 
// ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][106]~q  & ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106] & ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] ) ) 
// ) # ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][106]~q  & ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106] & ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] ) 
// ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][106]~q ),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~10 .lut_mask = 64'h00000F0FF0F0FFFF;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~10 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y32_N17
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~10_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][106]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][106] .power_up = "low";
// synopsys translate_on

// Location: FF_X18_Y28_N2
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~11_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][106]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][106] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y24_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_data[106] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|src_data [106] = ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & ( (\u0|hps_0|fpga_interfaces|h2f_AWID [1]) # (\u0|hps_0|fpga_interfaces|h2f_ARID [1]) ) ) ) # ( 
// !\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_AWID [1] ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & ( 
// !\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [1] ) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARID [1]),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_AWID [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_008|src_data [106]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[106] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[106] .lut_mask = 64'h0000555533337777;
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[106] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y24_N40
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_008|src_data [106]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y28_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~11 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~11_combout  = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106] & ( (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used 
// [1]) # (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][106]~q ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106] & ( 
// (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][106]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][106]~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~11 .lut_mask = 64'h03030303CFCFCFCF;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~11 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y28_N53
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~11_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][106]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][106] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y32_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~98 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~98_combout  = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][106]~q  & ( (!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout  & 
// ((!\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ) # ((!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout  & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][106]~q )))) # 
// (\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout  & (!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout  & ((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][106]~q )))) ) ) # ( 
// !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][106]~q  & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout  & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][106]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout ),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][106]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][106]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~98_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~98 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~98 .lut_mask = 64'h00CC00CCA0ECA0EC;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~98 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y32_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_020|src_payload~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_020|src_payload~1_combout  = ( \u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [1] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_020|src_payload~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~1 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y32_N8
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_020|src_payload~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .power_up = "low";
// synopsys translate_on

// Location: FF_X23_Y32_N59
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~10_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][106]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][106] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y32_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~10 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~10_combout  = (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106])) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & 
// ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][106]~q )))

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][106]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~10 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~10 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y32_N47
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~10_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][106]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][106] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y32_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~99 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~99_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout  & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~98_combout  & 
// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][106]~q ) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ))) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout  & ( 
// (!\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~98_combout  & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][106]~q  & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][106]~q ) # 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][106]~q ),
        .datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~98_combout ),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][106]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~99_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~99 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~99 .lut_mask = 64'h8C008C008C8C8C8C;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~99 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y24_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|src_data[106] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|src_data [106] = ( \u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [1] ) ) # ( !\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [1] & ( 
// (\u0|hps_0|fpga_interfaces|h2f_AWID [1] & \u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & ( !\u0|hps_0|fpga_interfaces|h2f_ARID [1] & ( (\u0|hps_0|fpga_interfaces|h2f_AWID [1] & 
// \u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & ( !\u0|hps_0|fpga_interfaces|h2f_ARID [1] & ( (\u0|hps_0|fpga_interfaces|h2f_AWID [1] & \u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]) ) 
// ) )

        .dataa(gnd),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_AWID [1]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_009|src_data [106]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[106] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[106] .lut_mask = 64'h030303030303FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[106] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y24_N41
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_009|src_data [106]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .power_up = "low";
// synopsys translate_on

// Location: FF_X19_Y24_N5
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~11_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][106]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][106] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y24_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~11 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~11_combout  = ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][106]~q  ) ) # ( 
// !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][106]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~11 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~11 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y24_N29
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~11_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][106]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][106] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y24_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_data[106] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_data [106] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [1] & ( ((\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [1])) # (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_ARID [1] & ( (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [1]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_010|src_data [106]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[106] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[106] .lut_mask = 64'h0505050537373737;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[106] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y24_N41
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_010|src_data [106]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .power_up = "low";
// synopsys translate_on

// Location: FF_X22_Y24_N29
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~11_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][106]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][106] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y24_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~11 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~11_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][106]~q  ) ) # ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][106]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~11 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~11 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y24_N58
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~11_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][106]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][106] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y24_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~100 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~100_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][106]~q  & ( ((\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout  & 
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][106]~q )) # (\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][106]~q  & ( 
// (\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout  & \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][106]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][106]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][106]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~100_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~100 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~100 .lut_mask = 64'h005500550F5F0F5F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~100 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y23_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_data[106] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_data [106] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [1] & ( ((\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [1])) # (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_ARID [1] & ( (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [1]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
        .datac(gnd),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_AWID [1]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_014|src_data [106]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[106] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[106] .lut_mask = 64'h0033003355775577;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[106] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y23_N26
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_014|src_data [106]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .power_up = "low";
// synopsys translate_on

// Location: FF_X23_Y23_N56
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~11_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][106]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][106] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y23_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~11 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~11_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][106]~q  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][106]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~11 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~11 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y23_N14
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~11_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][106]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][106] .power_up = "low";
// synopsys translate_on

// Location: FF_X21_Y23_N53
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~11_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][106]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][106] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y23_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|src_data[106] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|src_data [106] = ( \u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & ( ((\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [1])) # (\u0|hps_0|fpga_interfaces|h2f_ARID [1]) ) ) # ( 
// !\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & ( (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [1]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [1]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_AWID [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_011|src_data [106]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[106] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[106] .lut_mask = 64'h003300330F3F0F3F;
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[106] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y23_N25
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_011|src_data [106]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y23_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~11 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~11_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106] & ( (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used 
// [1]) # (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][106]~q ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106] & ( 
// (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][106]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][106]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~11 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~11 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y23_N8
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~11_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][106]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][106] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y23_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~101 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~101_combout  = (!\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout  & (((\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][106]~q  & \u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout )))) 
// # (\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout  & (((\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][106]~q  & \u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout )) # 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][106]~q )))

        .dataa(!\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][106]~q ),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][106]~q ),
        .datad(!\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~101_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~101 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~101 .lut_mask = 64'h111F111F111F111F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~101 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y24_N56
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~11_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][106]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][106] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y24_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_data[106] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|src_data [106] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [1] & ( ((\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [1])) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_ARID [1] & ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [1]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [1]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_015|src_data [106]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[106] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[106] .lut_mask = 64'h0505050505FF05FF;
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[106] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y24_N28
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_015|src_data [106]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y24_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~11 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~11_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106] & ( 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][106]~q ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106] & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][106]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][106]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~11 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~11 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y26_N32
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~11_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][106]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][106] .power_up = "low";
// synopsys translate_on

// Location: FF_X25_Y26_N47
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~11_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][106]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][106] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y24_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_data[106] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|src_data [106] = ( \u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_AWID [1] ) ) # ( !\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_AWID [1] & ( 
// (\u0|hps_0|fpga_interfaces|h2f_ARID [1] & \u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & ( !\u0|hps_0|fpga_interfaces|h2f_AWID [1] & ( (\u0|hps_0|fpga_interfaces|h2f_ARID [1] & 
// \u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & ( !\u0|hps_0|fpga_interfaces|h2f_AWID [1] & ( (\u0|hps_0|fpga_interfaces|h2f_ARID [1] & \u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]) ) 
// ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARID [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
        .datae(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_018|src_data [106]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[106] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[106] .lut_mask = 64'h005500550055FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[106] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y24_N28
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_018|src_data [106]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y26_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~11 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~11_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106] & ( (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]) # 
// (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][106]~q ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106] & ( (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used 
// [1] & \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][106]~q ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][106]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~11 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~11 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y26_N23
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~11_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][106]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][106] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y26_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~102 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~102_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][106]~q  & ( \u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout  & ( 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][106]~q ) # (\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout ) ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][106]~q  & ( 
// \u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout  & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][106]~q  ) ) ) # ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][106]~q  & ( 
// !\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout  & ( \u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout  ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][106]~q ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][106]~q ),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~102_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~102 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~102 .lut_mask = 64'h000033330F0F3F3F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~102 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y30_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[106] (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data [106] = ( \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~101_combout  & ( \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~102_combout  ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~101_combout  & ( 
// \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~102_combout  ) ) # ( \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~101_combout  & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~102_combout  ) ) # ( 
// !\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~101_combout  & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~102_combout  & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~97_combout ) # 
// ((!\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~105_combout ) # ((!\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~99_combout ) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~100_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~97_combout ),
        .datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~105_combout ),
        .datac(!\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~99_combout ),
        .datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~100_combout ),
        .datae(!\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~101_combout ),
        .dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~102_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data [106]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106] .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106] .lut_mask = 64'hFEFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106] .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y24_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|src_data[105] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|src_data [105] = ( \u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_AWID [0] & ( (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]) # (\u0|hps_0|fpga_interfaces|h2f_ARID [0]) ) ) ) # ( 
// !\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_AWID [0] & ( \u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & ( !\u0|hps_0|fpga_interfaces|h2f_AWID [0] & ( 
// \u0|hps_0|fpga_interfaces|h2f_ARID [0] ) ) )

        .dataa(gnd),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARID [0]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
        .datae(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_009|src_data [105]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[105] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[105] .lut_mask = 64'h0000333300FF33FF;
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[105] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y24_N32
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_009|src_data [105]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .power_up = "low";
// synopsys translate_on

// Location: FF_X19_Y24_N47
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~10_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][105]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][105] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y24_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~10 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~10_combout  = ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][105]~q  ) ) # ( 
// !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][105]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~10 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~10 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y24_N26
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~10_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][105]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][105] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y24_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_data[105] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_data [105] = ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [0] ) ) # ( !\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [0] & ( 
// (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [0]) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & ( !\u0|hps_0|fpga_interfaces|h2f_ARID [0] & ( (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & 
// \u0|hps_0|fpga_interfaces|h2f_AWID [0]) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & ( !\u0|hps_0|fpga_interfaces|h2f_ARID [0] & ( (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [0]) ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_AWID [0]),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_010|src_data [105]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[105] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[105] .lut_mask = 64'h111111111111FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[105] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y24_N17
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_010|src_data [105]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .power_up = "low";
// synopsys translate_on

// Location: FF_X22_Y24_N23
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~10_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][105]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][105] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y24_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~10 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~10_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][105]~q  & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] ) ) # ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][105]~q  & ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105] ) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][105]~q  & ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
        .datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][105]~q ),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~10 .lut_mask = 64'h00FF00FF0000FFFF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~10 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y24_N14
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~10_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][105]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][105] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y24_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~90 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~90_combout  = ( \u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout  & ( ((\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout  & 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][105]~q )) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][105]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout  & ( 
// (\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout  & \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][105]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][105]~q ),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][105]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~90_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~90 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~90 .lut_mask = 64'h003300330F3F0F3F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~90 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y32_N5
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~9_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][105]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][105] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y32_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_019|src_payload~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_019|src_payload~0_combout  = (\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [0])

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
        .datac(gnd),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [0]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_019|src_payload~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~0 .lut_mask = 64'h0033003300330033;
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y32_N29
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_019|src_payload~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y32_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~9 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~9_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105] & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]) # 
// (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][105]~q ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105] & ( (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] 
// & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][105]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][105]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~9 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~9 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y32_N47
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~9_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][105]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][105] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y32_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~88 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~88_combout  = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][105]~q  & ( (!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout  & 
// ((!\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ) # ((!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout  & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][105]~q )))) # 
// (\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout  & (((!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout  & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][105]~q )))) ) ) # ( 
// !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][105]~q  & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout  & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][105]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout ),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][105]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][105]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~88_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~88 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~88 .lut_mask = 64'h00F000F088F888F8;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~88 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y32_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_020|src_payload~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_020|src_payload~0_combout  = (\u0|hps_0|fpga_interfaces|h2f_ARID [0] & \u0|mm_interconnect_0|cmd_mux_020|saved_grant [1])

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [0]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_020|src_payload~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~0 .lut_mask = 64'h000F000F000F000F;
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y32_N35
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_020|src_payload~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .power_up = "low";
// synopsys translate_on

// Location: FF_X23_Y32_N2
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~9_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][105]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][105] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y32_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~9 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~9_combout  = (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105])) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & 
// ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][105]~q )))

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][105]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~9 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~9 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y32_N26
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~9_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][105]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][105] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y32_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_021|src_payload~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_021|src_payload~0_combout  = (\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [0])

        .dataa(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [0]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_021|src_payload~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~0 .lut_mask = 64'h0055005500550055;
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y32_N17
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_021|src_payload~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .power_up = "low";
// synopsys translate_on

// Location: FF_X25_Y32_N59
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~9_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][105]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][105] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y32_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~9 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~9_combout  = (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105])) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & 
// ((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][105]~q )))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][105]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~9 .lut_mask = 64'h0C3F0C3F0C3F0C3F;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~9 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y33_N40
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~9_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][105]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][105] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y32_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~89 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~89_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][105]~q  & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout  & 
// (!\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~88_combout  & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][105]~q ) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout )))) ) ) # ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][105]~q  & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~88_combout  & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][105]~q ) # 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ),
        .datac(!\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~88_combout ),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][105]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][105]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~89_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~89 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~89 .lut_mask = 64'hF050F05030103010;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~89 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y30_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_005|src_payload~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_005|src_payload~0_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [0] & ( \u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
        .datad(gnd),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_ARID [0]),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_005|src_payload~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~0 .lut_mask = 64'h00000F0F00000F0F;
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y30_N53
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_005|src_payload~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .power_up = "low";
// synopsys translate_on

// Location: FF_X11_Y30_N20
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~9_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][105]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][105] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y30_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~9 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~9_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][105]~q  ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][105]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~9 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~9 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y30_N14
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~9_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][105]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][105] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y33_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_006|src_payload~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_006|src_payload~0_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [0] & ( \u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_006|src_payload~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~0 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y33_N8
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_006|src_payload~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .power_up = "low";
// synopsys translate_on

// Location: FF_X14_Y33_N59
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~9_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][105]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][105] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y33_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~9 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~9_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][105]~q  ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][105]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~9 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~9 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y33_N38
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~9_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][105]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][105] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y33_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~35 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~35_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][105]~q  & ( (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0] & 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q )) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][105]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~35_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~35 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~35 .lut_mask = 64'h000000005F7F5F7F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~35 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y26_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|src_data[105] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|src_data [105] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [0] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [0] & ( (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]) # (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]) ) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_AWID [0] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [0] & ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_AWID [0] & ( !\u0|hps_0|fpga_interfaces|h2f_ARID [0] & ( 
// \u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
        .datad(gnd),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_AWID [0]),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_004|src_data [105]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[105] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[105] .lut_mask = 64'h00000F0F55555F5F;
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[105] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y26_N4
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_004|src_data [105]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .power_up = "low";
// synopsys translate_on

// Location: FF_X18_Y26_N17
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~10_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][105]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][105] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y26_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~10 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~10_combout  = (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105])) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & 
// ((\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][105]~q )))

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][105]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~10 .lut_mask = 64'h505F505F505F505F;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~10 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y26_N34
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~10_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][105]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][105] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y30_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~94 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~94_combout  = ( !\u0|mm_interconnect_0|rsp_mux_001|src_payload~35_combout  & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][105]~q  & ( 
// (!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout  & (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout  & ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][105]~q ) # 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout )))) # (\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout  & (((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][105]~q ) # 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout )))) ) ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_payload~35_combout  & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][105]~q  & ( 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][105]~q ) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][105]~q ),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout ),
        .datae(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~35_combout ),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][105]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~94_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~94 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~94 .lut_mask = 64'hF0FF000070770000;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~94 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y26_N20
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~10_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][105]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][105] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y26_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|src_data[105] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|src_data [105] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [0] & ( ((\u0|hps_0|fpga_interfaces|h2f_AWID [0] & \u0|mm_interconnect_0|cmd_mux|saved_grant [0])) # (\u0|mm_interconnect_0|cmd_mux|saved_grant [1]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_ARID [0] & ( (\u0|hps_0|fpga_interfaces|h2f_AWID [0] & \u0|mm_interconnect_0|cmd_mux|saved_grant [0]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [0]),
        .datad(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux|src_data [105]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|src_data[105] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|src_data[105] .lut_mask = 64'h000F000F333F333F;
defparam \u0|mm_interconnect_0|cmd_mux|src_data[105] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y26_N40
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux|src_data [105]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y26_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~10 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~10_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][105]~q  & ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg 
// [105] ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][105]~q  & ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105] & ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] ) ) ) # ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][105]~q  & ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105] & ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][105]~q ),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~10 .lut_mask = 64'h00000F0FF0F0FFFF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~10 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y26_N23
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~10_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][105]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][105] .power_up = "low";
// synopsys translate_on

// Location: FF_X11_Y24_N2
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~9_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][105]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][105] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y24_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_001|src_payload~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_001|src_payload~0_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [0] & ( \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_ARID [0]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_001|src_payload~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~0 .lut_mask = 64'h000000000000FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y24_N43
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_001|src_payload~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y24_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~9 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~9_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][105]~q  & ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg 
// [105] ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][105]~q  & ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105] & ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] ) ) ) # ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][105]~q  & ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105] & ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][105]~q ),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~9 .lut_mask = 64'h00000F0FF0F0FFFF;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~9 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y26_N20
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~9_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][105]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][105] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y27_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_002|src_payload~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_002|src_payload~0_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [0] & ( \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_ARID [0]),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_002|src_payload~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~0 .lut_mask = 64'h0000333300003333;
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y27_N44
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_002|src_payload~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .power_up = "low";
// synopsys translate_on

// Location: FF_X10_Y27_N29
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~9_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][105]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][105] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y27_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~9 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~9_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][105]~q  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][105]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~9 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~9 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y27_N5
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~9_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][105]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][105] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y27_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~34 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~34_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][105]~q  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][105]~q  & (((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0] & 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q )) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0]),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][105]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~34_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~34 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~34 .lut_mask = 64'h0037003700FF00FF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~34 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y26_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~93 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~93_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][105]~q  & ( !\u0|mm_interconnect_0|rsp_mux_001|src_payload~34_combout  & ( 
// (\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout  & (((!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][105]~q ) # (\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout )) # 
// (\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][105]~q  & ( !\u0|mm_interconnect_0|rsp_mux_001|src_payload~34_combout  & ( 
// ((!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][105]~q ) # (\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout )) # (\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ),
        .datab(!\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][105]~q ),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ),
        .datae(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][105]~q ),
        .dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~34_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~93_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~93 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~93 .lut_mask = 64'hF7F700F700000000;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~93 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y30_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_012|src_payload~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_012|src_payload~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [0] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_012|src_payload~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~0 .lut_mask = 64'h000000000000FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y30_N53
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_012|src_payload~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .power_up = "low";
// synopsys translate_on

// Location: FF_X14_Y30_N44
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~9_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][105]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][105] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y30_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~9 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~9_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][105]~q  ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][105]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~9 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y30_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][105]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][105]~feeder_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~9_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~9_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][105]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][105]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][105]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][105]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y30_N10
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][105]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][105]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][105] .power_up = "low";
// synopsys translate_on

// Location: FF_X11_Y33_N5
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~9_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][105]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][105] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y33_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_003|src_payload~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_003|src_payload~0_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [0] & ( \u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_ARID [0]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_003|src_payload~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~0 .lut_mask = 64'h000000000000FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y33_N22
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_003|src_payload~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y33_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~9 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~9_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][105]~q  & ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg 
// [105] ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][105]~q  & ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105] & ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] ) ) ) # ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][105]~q  & ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105] & ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] ) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][105]~q ),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~9 .lut_mask = 64'h00005555AAAAFFFF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~9 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y30_N50
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~9_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][105]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][105] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y30_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~95 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~95_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][105]~q  & ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout  & ( 
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~94_combout  & (\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~93_combout  & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][105]~q ) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout )))) ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][105]~q  & ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout  & ( 
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~94_combout  & (\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~93_combout  & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][105]~q ) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout )))) ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][105]~q  & ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout  & ( 
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~94_combout  & (\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~93_combout  & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][105]~q ) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout )))) ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~94_combout ),
        .datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~93_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][105]~q ),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout ),
        .datae(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][105]~q ),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~95_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~95 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~95 .lut_mask = 64'h1011000010111011;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~95 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y23_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_data[105] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_data [105] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [0] & ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_AWID [0] & ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & ( 
// (\u0|hps_0|fpga_interfaces|h2f_ARID [0] & \u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]) ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_AWID [0] & ( !\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & ( (\u0|hps_0|fpga_interfaces|h2f_ARID [0] & 
// \u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]) ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_AWID [0] & ( !\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & ( (\u0|hps_0|fpga_interfaces|h2f_ARID [0] & \u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]) ) 
// ) )

        .dataa(gnd),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARID [0]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
        .datad(gnd),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_AWID [0]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_014|src_data [105]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[105] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[105] .lut_mask = 64'h030303030303FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[105] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y23_N32
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_014|src_data [105]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .power_up = "low";
// synopsys translate_on

// Location: FF_X23_Y23_N5
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~10_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][105]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][105] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y23_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~10 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~10_combout  = (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105])) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & 
// ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][105]~q )))

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][105]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~10 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~10 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y23_N22
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~10_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][105]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][105] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y23_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|src_data[105] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|src_data [105] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [0] & ( ((\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [0])) # (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_AWID [0] & ( (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [0]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [0]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_011|src_data [105]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[105] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[105] .lut_mask = 64'h000F000F333F333F;
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[105] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y23_N35
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_011|src_data [105]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .power_up = "low";
// synopsys translate_on

// Location: FF_X21_Y23_N50
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~10_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][105]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][105] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y23_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~10 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~10_combout  = (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg 
// [105])) # (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][105]~q )))

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][105]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~10 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~10 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y23_N41
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~10_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][105]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][105] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y23_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~91 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~91_combout  = ( \u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout  & ( ((\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout  & \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][105]~q )) # 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][105]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout  & ( (\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout  & 
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][105]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][105]~q ),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][105]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~91_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~91 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~91 .lut_mask = 64'h005500550F5F0F5F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~91 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y33_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_017|src_payload~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_017|src_payload~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [0] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [0]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_017|src_payload~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~0 .lut_mask = 64'h00000F0F00000F0F;
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y33_N58
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_017|src_payload~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .power_up = "low";
// synopsys translate_on

// Location: FF_X15_Y33_N26
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~9_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][105]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][105] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y33_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~9 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~9_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][105]~q  & ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] ) ) # ( 
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][105]~q  & ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105] ) ) 
// ) # ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][105]~q  & ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg 
// [105] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][105]~q ),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~9 .lut_mask = 64'h0F0F0F0F0000FFFF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y33_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][105]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][105]~feeder_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~9_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~9_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][105]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][105]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][105]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][105]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y33_N49
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][105]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][105]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][105] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y31_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_013|src_payload~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_013|src_payload~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [0] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_013|src_payload~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~0 .lut_mask = 64'h0000000000FF00FF;
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y31_N53
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_013|src_payload~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .power_up = "low";
// synopsys translate_on

// Location: FF_X17_Y31_N8
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~9_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][105]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][105] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y31_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~9 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~9_combout  = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][105]~q  ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][105]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~9 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~9 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y31_N8
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~9_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][105]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][105] .power_up = "low";
// synopsys translate_on

// Location: FF_X21_Y29_N14
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~10_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][105]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][105] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y29_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|src_data[105] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|src_data [105] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [0] & ( ((\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [0])) # (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_ARID [0] & ( (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [0]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_007|src_data [105]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[105] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[105] .lut_mask = 64'h0303030357575757;
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[105] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y29_N25
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_007|src_data [105]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y29_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~10 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~10_combout  = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105] & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used 
// [1]) # (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][105]~q ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105] & ( 
// (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][105]~q ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][105]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~10 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~10 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y31_N5
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~10_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][105]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][105] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y31_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~86 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~86_combout  = ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][105]~q  & ( \u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout  & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][105]~q ) ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][105]~q  & ( 
// \u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout  & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout  & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][105]~q ) ) ) ) # ( 
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][105]~q  & ( !\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout  & ( (!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout ) # 
// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout  & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][105]~q )) ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][105]~q  & ( 
// !\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout  & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout  & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][105]~q ) ) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][105]~q ),
        .datae(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][105]~q ),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~86_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~86 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~86 .lut_mask = 64'h00F0AAFA00F000F0;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~86 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y31_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_016|src_payload~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_016|src_payload~0_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARID [0] & ( \u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_ARID [0]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_016|src_payload~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~0 .lut_mask = 64'h000000000000FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y31_N17
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_016|src_payload~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .power_up = "low";
// synopsys translate_on

// Location: FF_X17_Y31_N11
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~9_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][105]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][105] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y31_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~9 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~9_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][105]~q  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][105]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~9 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~9 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y31_N31
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~9_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][105]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][105] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y31_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~87 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~87_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout  & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~86_combout  & 
// ((!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][105]~q ) # (!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ))) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout  & ( 
// (!\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~86_combout  & (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][105]~q  & ((!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][105]~q ) # 
// (!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][105]~q ),
        .datab(!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ),
        .datac(!\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~86_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][105]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~87_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~87 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~87 .lut_mask = 64'hE000E000E0E0E0E0;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~87 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y24_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_data[105] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|src_data [105] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [0] & ( ((\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [0])) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_ARID [0] & ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [0]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_AWID [0]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_015|src_data [105]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[105] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[105] .lut_mask = 64'h111111111F1F1F1F;
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[105] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y24_N26
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_015|src_data [105]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .power_up = "low";
// synopsys translate_on

// Location: FF_X19_Y24_N20
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~10_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][105]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][105] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y24_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~10 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~10_combout  = (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105])) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & 
// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][105]~q )))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][105]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~10 .lut_mask = 64'h0C3F0C3F0C3F0C3F;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~10 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y26_N28
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~10_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][105]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][105] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y26_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_data[105] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|src_data [105] = ( \u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [0] ) ) # ( !\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [0] & ( 
// (\u0|hps_0|fpga_interfaces|h2f_AWID [0] & \u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & ( !\u0|hps_0|fpga_interfaces|h2f_ARID [0] & ( (\u0|hps_0|fpga_interfaces|h2f_AWID [0] & 
// \u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & ( !\u0|hps_0|fpga_interfaces|h2f_ARID [0] & ( (\u0|hps_0|fpga_interfaces|h2f_AWID [0] & \u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]) ) 
// ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_AWID [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_018|src_data [105]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[105] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[105] .lut_mask = 64'h050505050505FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[105] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y26_N8
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_018|src_data [105]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .power_up = "low";
// synopsys translate_on

// Location: FF_X30_Y26_N17
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~10_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][105]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][105] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y26_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~10 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~10_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][105]~q  ) ) # ( 
// !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][105]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~10 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~10 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y26_N20
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~10_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][105]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][105] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y26_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~92 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~92_combout  = ( \u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout  & ( ((\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][105]~q  & 
// \u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout )) # (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][105]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout  & ( 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][105]~q  & \u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][105]~q ),
        .datac(!\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout ),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][105]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~92_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~92 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~92 .lut_mask = 64'h0303030303FF03FF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~92 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y28_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[105] (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data [105] = ( \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~87_combout  & ( \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~92_combout  ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~87_combout  & ( 
// \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~92_combout  ) ) # ( \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~87_combout  & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~92_combout  & ( 
// ((!\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~89_combout ) # ((!\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~95_combout ) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~91_combout ))) # 
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~90_combout ) ) ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~87_combout  & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~92_combout  ) )

        .dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~90_combout ),
        .datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~89_combout ),
        .datac(!\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~95_combout ),
        .datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~91_combout ),
        .datae(!\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~87_combout ),
        .dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~92_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data [105]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105] .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105] .lut_mask = 64'hFFFFFDFFFFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105] .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y33_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & ( !\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & ( (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]) # (!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .lut_mask = 64'hFFF0FFF0FF00FF00;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y33_N17
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y33_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~2_combout  = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q  & ( (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0_combout ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q  & ( (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & 
// ((\u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0_combout ) # (\u0|mm_interconnect_0|data_info_s1_agent|cp_ready~1_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_agent|cp_ready~1_combout ),
        .datab(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent|cp_ready~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~2 .lut_mask = 64'h4C4C4C4C0C0C0C0C;
defparam \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y33_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q  & (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// !\u0|mm_interconnect_0|data_info_s1_agent|cp_ready~2_combout )) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ) # 
// (\u0|mm_interconnect_0|data_info_s1_agent|cp_ready~2_combout ))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datad(!\u0|mm_interconnect_0|data_info_s1_agent|cp_ready~2_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .lut_mask = 64'h0C0F0C0F0C000C00;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y33_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout  = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & ( 
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ) ) ) # ( 
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & ( (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q  & \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q )) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h00C000C000CC00CC;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y33_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout  & ( 
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  ) ) # ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout  & ( 
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  & ((!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]) # 
// ((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) # (!\u0|mm_interconnect_0|cmd_mux_017|last_cycle~0_combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_017|last_cycle~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .lut_mask = 64'hF0E0F0E0F0F0F0F0;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y37_N20
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y37_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout  = ( 
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// (\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] & !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]) ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & ( 
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( (\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] & !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]) ) ) ) # ( 
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & 
// ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .lut_mask = 64'h3333CCCC50505050;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y37_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout  = ( 
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// (\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ) ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & 
// ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( (\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ) ) ) ) # ( 
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]) ) ) ) # 
// ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) ) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),
        .datae(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .lut_mask = 64'h2222DDDD000F000F;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y37_N38
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .power_up = "low";
// synopsys translate_on

// Location: FF_X22_Y37_N53
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y37_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] & ( 
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & 
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3])) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg 
// [4] & ( ((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg 
// [3])) # (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .lut_mask = 64'hDDFFDDFF22002200;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y37_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout  = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  & ( 
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) ) ) # ( 
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  & ( (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # 
// ((\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .lut_mask = 64'hABABABAB01010101;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y37_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] & 
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3])) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .lut_mask = 64'h00000000A000A000;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y37_N50
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y37_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout  & ( 
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  $ 
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) # (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1])) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout  & ( (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  $ (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .lut_mask = 64'h0AA00AA01BB11BB1;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y37_N32
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y37_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout  = ( 
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// (\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ) ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & 
// ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( (\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ) ) ) ) # ( 
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ) # (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]) ) ) ) # ( 
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),
        .datae(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .lut_mask = 64'h0A0AF5F500330033;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y37_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout  = ( 
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout  & ( 
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout  & ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  ) 
// ) ) # ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout  & ( 
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout  & ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  ) 
// ) ) # ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout  & ( 
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout  & ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  
// ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout  & ( 
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout  & ( 
// ((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout  & 
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout  & 
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ))) # (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout 
// ) ) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
        .datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),
        .datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),
        .datae(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .lut_mask = 64'h7555555555555555;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y37_N56
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y33_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0_combout  & ( 
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & ( (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// ((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]))) ) ) ) # ( 
// !\u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0_combout  & ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & ( 
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # 
// ((\u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0_combout  & !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1])))) ) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0_combout ),
        .datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),
        .datae(!\u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0_combout ),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .lut_mask = 64'h8C88CC8800000000;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y33_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout  = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & ( 
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))) 
// ) ) # ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & ( ((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & 
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))) 
// # (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3 .lut_mask = 64'h7333733340004000;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y33_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout  = ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( 
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & ( (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  & !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout )) ) ) ) # 
// ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & ( 
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  & !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ) ) ) ) # ( 
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & ( 
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  & !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ) ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
        .datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ),
        .datae(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4 .lut_mask = 64'hF000F000C0000000;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y33_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout  = ( 
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout  & ( (\u0|mm_interconnect_0|cmd_mux_017|last_cycle~0_combout  & (\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] & 
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q )) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_017|last_cycle~0_combout ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h0101010100000000;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y37_N2
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_017|src_payload~13_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .power_up = "low";
// synopsys translate_on

// Location: FF_X25_Y37_N44
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y37_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_017|src_payload~14 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_017|src_payload~14_combout  = ( \u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_017|src_payload~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~14 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~14 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y37_N38
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_017|src_payload~14_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y37_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_017|src_payload~16 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_017|src_payload~16_combout  = ( \u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_017|src_payload~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~16 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~16 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y37_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_017|src_payload~15 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_017|src_payload~15_combout  = ( \u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] ) )

        .dataa(gnd),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_017|src_payload~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~15 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~15 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y37_N32
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_017|src_payload~15_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .power_up = "low";
// synopsys translate_on

// Location: FF_X23_Y37_N59
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_017|src_payload~16_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y37_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_017|src_payload~15_combout  & ( 
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & 
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1])) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_017|src_payload~15_combout  & ( 
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & 
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1])))) # (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|cmd_mux_017|src_payload~16_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_017|src_payload~16_combout ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_017|src_payload~15_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .lut_mask = 64'h11B111B100A000A0;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y37_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout  = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  & ( 
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) # 
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|cmd_mux_017|src_payload~14_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|cmd_mux_017|src_payload~14_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .lut_mask = 64'h00000000BB88BB88;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y37_N16
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y37_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & ( 
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & ( (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (!\u0|mm_interconnect_0|cmd_mux_017|src_payload~16_combout  & !\u0|mm_interconnect_0|cmd_mux_017|src_payload~15_combout )) ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & ( 
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & ( (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (!\u0|mm_interconnect_0|cmd_mux_017|src_payload~16_combout  & !\u0|mm_interconnect_0|cmd_mux_017|src_payload~15_combout )) ) ) ) # ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & ( 
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & ( (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (!\u0|mm_interconnect_0|cmd_mux_017|src_payload~16_combout  & !\u0|mm_interconnect_0|cmd_mux_017|src_payload~15_combout )) ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & ( 
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & ( (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # 
// ((!\u0|mm_interconnect_0|cmd_mux_017|src_payload~16_combout  & !\u0|mm_interconnect_0|cmd_mux_017|src_payload~15_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_017|src_payload~16_combout ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_017|src_payload~15_combout ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .lut_mask = 64'hEAEA404040404040;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y37_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout  = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  & ( 
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) # 
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((\u0|mm_interconnect_0|cmd_mux_017|src_payload~14_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_017|src_payload~14_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .lut_mask = 64'h000000000A5F0A5F;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y37_N49
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y30_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~0_combout  = ( !\u0|hps_0|fpga_interfaces|h2f_ARBURST [0] & ( \u0|hps_0|fpga_interfaces|h2f_ARBURST [1] ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARBURST [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARBURST [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~0 .lut_mask = 64'h5555555500000000;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y30_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~0_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARLEN [1] & ( (\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] & (!\u0|hps_0|fpga_interfaces|h2f_ARLEN [3] & \u0|hps_0|fpga_interfaces|h2f_ARLEN [2])) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_ARLEN [1] & ( (\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] & (!\u0|hps_0|fpga_interfaces|h2f_ARLEN [3] & ((\u0|hps_0|fpga_interfaces|h2f_ARLEN [2]) # (\u0|hps_0|fpga_interfaces|h2f_ARLEN [0])))) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [3]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [2]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~0 .lut_mask = 64'h1050105000500050;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y30_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~2 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~2_combout  = ( !\u0|hps_0|fpga_interfaces|h2f_ARLEN [1] & ( !\u0|hps_0|fpga_interfaces|h2f_ARLEN [2] ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [2]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~2 .lut_mask = 64'hAAAAAAAA00000000;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y30_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout  = ( !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~2_combout  & ( (!\u0|hps_0|fpga_interfaces|h2f_ARLEN [3] & 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~0_combout  & (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~0_combout  & !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]))) ) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [3]),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~0_combout ),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~0_combout ),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0 .lut_mask = 64'h0000000020000000;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y30_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~2 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~2_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] & ( (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~2 .lut_mask = 64'h00000000F000F000;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y30_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~3 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~3_combout  = ( !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] & ( (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~3 .lut_mask = 64'hF000F00000000000;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y30_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~13 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~13_sumout  = SUM(( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~3_combout  ) + ( VCC ) + ( !VCC ))
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~14  = CARRY(( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~3_combout  ) + ( VCC ) + ( !VCC ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~3_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~13_sumout ),
        .cout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~14 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~13 .lut_mask = 64'h0000000000000F0F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y30_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~9 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~9_sumout  = SUM(( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~2_combout  ) + ( VCC ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~14  ))
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~10  = CARRY(( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~2_combout  ) + ( VCC ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~14  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~2_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~14 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~9_sumout ),
        .cout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~10 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~9 .lut_mask = 64'h0000000000000F0F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y30_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~1 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~1_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~9_sumout  & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout  ) ) # ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~9_sumout  & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout  & ((\u0|hps_0|fpga_interfaces|h2f_ARBURST [0]) # (\u0|hps_0|fpga_interfaces|h2f_ARBURST [1]))) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARBURST [1]),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARBURST [0]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~9_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~1 .lut_mask = 64'h5F005F00FF00FF00;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y37_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_017|src_payload~17 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_017|src_payload~17_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~1_combout  & ( \u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_017|src_payload~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~17 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~17 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y37_N29
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_017|src_payload~17_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y37_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [1] & ( !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & ( 
// (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & \u0|mm_interconnect_0|cmd_mux_017|saved_grant [1])) ) ) )

        .dataa(gnd),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
        .datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [1]),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .lut_mask = 64'h0000000C00000000;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y37_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] 
// & ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  & ( (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # 
// (\u0|mm_interconnect_0|cmd_mux_017|src_payload~14_combout ) ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] & ( 
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  & ( (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// \u0|mm_interconnect_0|cmd_mux_017|src_payload~14_combout ) ) ) ) # ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] & ( 
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  ) ) # ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] & ( 
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_017|src_payload~14_combout ),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .lut_mask = 64'hFFFFFFFF1111BBBB;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y37_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout  = 
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout 

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .lut_mask = 64'hFF00FF00FF00FF00;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y37_N17
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y30_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~1 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~1_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARLEN [3] & ( \u0|hps_0|fpga_interfaces|h2f_ARLEN [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARLEN [3] & ( 
// \u0|hps_0|fpga_interfaces|h2f_ARLEN [1] & ( !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] $ (!\u0|hps_0|fpga_interfaces|h2f_ARLEN [2]) ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_ARLEN [3] & ( !\u0|hps_0|fpga_interfaces|h2f_ARLEN [1] & ( 
// \u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARLEN [3] & ( !\u0|hps_0|fpga_interfaces|h2f_ARLEN [1] & ( !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] $ (((!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0] & 
// !\u0|hps_0|fpga_interfaces|h2f_ARLEN [2]))) ) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [2]),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [3]),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~1 .lut_mask = 64'h5AAA555555AA5555;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y30_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~2 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~2_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~13_sumout  & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout  & 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~1_combout ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~13_sumout  & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout  & 
// (!\u0|hps_0|fpga_interfaces|h2f_ARBURST [0] & (!\u0|hps_0|fpga_interfaces|h2f_ARBURST [1]))) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout  & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~1_combout ) # 
// ((!\u0|hps_0|fpga_interfaces|h2f_ARBURST [0] & !\u0|hps_0|fpga_interfaces|h2f_ARBURST [1])))) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout ),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARBURST [0]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARBURST [1]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~13_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~2 .lut_mask = 64'hD5C0D5C055005500;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~2 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y37_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_017|src_payload~18 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_017|src_payload~18_combout  = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~2_combout  & ( \u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_017|src_payload~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~18 .lut_mask = 64'h3333333300000000;
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~18 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y37_N26
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_017|src_payload~18_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y37_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0] = ( \u0|mm_interconnect_0|cmd_mux_017|src_payload~18_combout  & ( 
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  & 
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0])) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_017|src_payload~18_combout  & ( 
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  & ((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]) # 
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_017|src_payload~18_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .lut_mask = 64'h3131313120202020;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y37_N20
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y37_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout  = SUM(( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) + ( 
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14  = CARRY(( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) + ( 
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
        .datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
        .cout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .lut_mask = 64'h0000CCCC00000F0F;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y37_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  = ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// (((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0] & (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout )))) # 
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]) ) ) # ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// ((\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] & (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  & ((\u0|hps_0|fpga_interfaces|h2f_ARADDR [0]))))) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
        .datae(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [0]),
        .datag(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .extended_lut = "on";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .lut_mask = 64'h555F0000555F3030;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y37_N7
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y37_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout  = SUM(( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + ( 
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14  ))
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10  = CARRY(( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + ( 
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14  ))

        .dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
        .cout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .lut_mask = 64'h0000AAAA000000FF;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y37_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1] = ( \u0|mm_interconnect_0|cmd_mux_017|src_payload~17_combout  & ( 
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout  & (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1])) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_017|src_payload~17_combout  & ( 
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout  & ((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]) # 
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_017|src_payload~17_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .lut_mask = 64'h5151515140404040;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y37_N13
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y37_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout  = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1] & ( 
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1] & ( ((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1] & 
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout  & !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) # 
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
        .datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .lut_mask = 64'h37333733FF33FF33;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y37_N23
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y37_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout  = SUM(( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + ( 
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10  ))
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6  = CARRY(( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + ( 
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10  ))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
        .cout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .lut_mask = 64'h0000FF0000003333;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y37_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2] = ( \u0|mm_interconnect_0|cmd_mux_017|src_payload~13_combout  & ( 
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout  & (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] & 
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_017|src_payload~13_combout  & ( 
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout  & ((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]) # 
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_017|src_payload~13_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .lut_mask = 64'h3033303330003000;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y37_N49
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y37_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout  = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( 
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [2] & \u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]) ) ) ) # ( 
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// (\u0|hps_0|fpga_interfaces|h2f_ARADDR [2] & \u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]) ) ) ) # ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( 
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  ) ) # ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( 
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] & 
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [2]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
        .datae(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .lut_mask = 64'h1111FFFF000F000F;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y37_N47
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y16_N21
cyclonev_lcell_comb \u0|data_info|read_mux_out[11] (
// Equation(s):
// \u0|data_info|read_mux_out [11] = ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & ( 
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & \m_x|info [11]) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datab(gnd),
        .datac(!\m_x|info [11]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|data_info|read_mux_out [11]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|data_info|read_mux_out[11] .extended_lut = "off";
defparam \u0|data_info|read_mux_out[11] .lut_mask = 64'h0A0A0A0A00000000;
defparam \u0|data_info|read_mux_out[11] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y16_N23
dffeas \u0|data_info|readdata[11] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|data_info|read_mux_out [11]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|data_info|readdata [11]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|data_info|readdata[11] .is_wysiwyg = "true";
defparam \u0|data_info|readdata[11] .power_up = "low";
// synopsys translate_on

// Location: FF_X30_Y16_N22
dffeas \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[11] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|data_info|readdata [11]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [11]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[11] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[11] .power_up = "low";
// synopsys translate_on

// Location: FF_X31_Y16_N8
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][11] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~11_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][11]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][11] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][11] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y16_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~11 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~11_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][11]~q  ) ) # ( 
// !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [11] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [11]),
        .datad(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][11]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~11 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~11 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y16_N37
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][11] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~11_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][11]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][11] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][11] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y16_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~31 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~31_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][11]~q  & ( (\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout  & 
// ((!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout ) # (\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [11]))) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][11]~q  & ( 
// (\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout  & (\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout  & \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [11])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout ),
        .datad(!\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [11]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][11]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~31_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~31 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~31 .lut_mask = 64'h0003000330333033;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~31 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y26_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|src_payload~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|src_payload~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_WDATA [0] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_WDATA [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_004|src_payload~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|src_payload~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|src_payload~0 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_004|src_payload~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y26_N47
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_004|src_payload~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y26_N12
cyclonev_lcell_comb \u0|data_read_en_rx|data_out~feeder (
// Equation(s):
// \u0|data_read_en_rx|data_out~feeder_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [0] )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|data_read_en_rx|data_out~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|data_read_en_rx|data_out~feeder .extended_lut = "off";
defparam \u0|data_read_en_rx|data_out~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|data_read_en_rx|data_out~feeder .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y28_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout  & ( 
// ((\u0|hps_0|fpga_interfaces|h2f_ARADDR [2] & \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1])) # (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout  & 
// ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [2] & \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [2]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 .lut_mask = 64'h005500550F5F0F5F;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y29_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~13 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~13_sumout  = SUM(( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~7_combout  ) + ( VCC ) + ( !VCC ))
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~14  = CARRY(( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~7_combout  ) + ( VCC ) + ( !VCC ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~7_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~13_sumout ),
        .cout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~14 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~13 .lut_mask = 64'h0000000000000F0F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y29_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~9 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~9_sumout  = SUM(( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~6_combout  ) + ( VCC ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~14  ))
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~10  = CARRY(( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~6_combout  ) + ( VCC ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~14  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~6_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~14 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~9_sumout ),
        .cout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~10 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~9 .lut_mask = 64'h0000000000000F0F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y29_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~5 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~5_sumout  = SUM(( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~5_combout  ) + ( VCC ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~10  ))
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~6  = CARRY(( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~5_combout  ) + ( VCC ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~10  ))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~5_combout ),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~10 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~5_sumout ),
        .cout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~6 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~5 .lut_mask = 64'h0000000000003333;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y29_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~5_sumout  & ( (\u0|hps_0|fpga_interfaces|h2f_AWBURST [1] & (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|LessThan12~0_combout )) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~5_sumout  & ( (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & ((!\u0|hps_0|fpga_interfaces|h2f_AWBURST [1]) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|LessThan12~0_combout ))) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [1]),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|LessThan12~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~5_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~0 .lut_mask = 64'h8C8C8C8C04040404;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y28_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|src_data[81] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|src_data [81] = ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~0_combout  & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout  ) ) 
// ) # ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~0_combout  & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout ) # 
// (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~0_combout  & ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout ),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
        .datae(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_004|src_data [81]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[81] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[81] .lut_mask = 64'h00FFCCFF0000CCCC;
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[81] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y28_N26
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_004|src_data [81]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .power_up = "low";
// synopsys translate_on

// Location: FF_X15_Y28_N19
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y28_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|src_data[86] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|src_data [86] = ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [0] & ( ((\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [0])) # (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0] & ( (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_004|src_data [86]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[86] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[86] .lut_mask = 64'h003300330F3F0F3F;
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[86] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y28_N20
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_004|src_data [86]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X17_Y28_N32
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_004|src_data [88]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .power_up = "low";
// synopsys translate_on

// Location: FF_X17_Y28_N2
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_004|src_data [87]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y28_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_004|src_data [88] & ( 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & 
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1])) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_004|src_data [88] & ( 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & 
// ((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1])))) # (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((\u0|mm_interconnect_0|cmd_mux_004|src_data [87])))) ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_004|src_data [87]),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_004|src_data [88]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .lut_mask = 64'h058D058D00880088;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y28_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  & ( 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) # 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|cmd_mux_004|src_data [86]))) ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_004|src_data [86]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .lut_mask = 64'h00000000AACCAACC;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y28_N59
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y28_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  = ( \u0|mm_interconnect_0|cmd_mux_004|src_data [87] & ( 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1])) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_004|src_data [87] & ( 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & 
// ((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1])))) # (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((!\u0|mm_interconnect_0|cmd_mux_004|src_data [88])))) ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_004|src_data [88]),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_004|src_data [87]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .lut_mask = 64'hD850D85088008800;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y28_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout  = (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  & 
// ((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) # 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((\u0|mm_interconnect_0|cmd_mux_004|src_data [86])))))

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_004|src_data [86]),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .lut_mask = 64'h0503050305030503;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y28_N29
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y28_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout  & ( 
// ((\u0|hps_0|fpga_interfaces|h2f_ARADDR [0] & \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1])) # (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout  & 
// ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [0] & \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [0]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .lut_mask = 64'h000F000F333F333F;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y29_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|LessThan10~0_combout  & ( (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & 
// ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~13_sumout ) # (\u0|hps_0|fpga_interfaces|h2f_AWBURST [1]))) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|LessThan10~0_combout  & ( (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [1] & 
// (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~13_sumout )) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [1]),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~13_sumout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|LessThan10~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0 .lut_mask = 64'hA000A000F050F050;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y28_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|src_data[79] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|src_data [79] = ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~2_combout ) # ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout  
// & \u0|mm_interconnect_0|cmd_mux_004|saved_grant [0])) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout  & \u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~2_combout ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_004|src_data [79]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[79] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[79] .lut_mask = 64'h2222F2F22222F2F2;
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[79] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y28_N47
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_004|src_data [79]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y28_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0] = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout  & ( 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]))) # 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|cmd_mux_004|src_data [79])) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_004|src_data [79]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .lut_mask = 64'h00000000F0AAF0AA;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y28_N5
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y28_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  = ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]))) # (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (!\u0|mm_interconnect_0|cmd_mux_004|src_data [86])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_004|src_data [86]),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .lut_mask = 64'h00000000F0CCF0CC;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y28_N26
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y28_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout  = SUM(( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) 
// + ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14  = CARRY(( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) + ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
        .cout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .lut_mask = 64'h0000F0F000003333;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y28_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  
// & ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  & ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  ) ) ) # ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  & ( 
// ((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0] & \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout )) # 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]) ) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  
// & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  & ( 
// ((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0] & \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout )) # 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]) ) ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
        .datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 .lut_mask = 64'h0F3F00000F3F5555;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y28_N8
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y28_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout  = SUM(( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] 
// ) + ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14  ))
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10  = CARRY(( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + 
// ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
        .cout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y29_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector28~0_combout  & ( (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & 
// ((!\u0|hps_0|fpga_interfaces|h2f_AWBURST [1] & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~9_sumout ))) # (\u0|hps_0|fpga_interfaces|h2f_AWBURST [1] & (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~1_combout )))) ) ) # ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector28~0_combout  & ( (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [1] & (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~9_sumout 
// )) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [1]),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~1_combout ),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~9_sumout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector28~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~0 .lut_mask = 64'hA000A000E040E040;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y28_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|src_data[80] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|src_data [80] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~0_combout  & ( (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~1_combout ) ) ) 
// # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~0_combout  & ( ((\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~1_combout )) # (\u0|mm_interconnect_0|cmd_mux_004|saved_grant 
// [0]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_004|src_data [80]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[80] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[80] .lut_mask = 64'h3377337700550055;
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[80] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y28_N53
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_004|src_data [80]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y28_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1] = ( \u0|mm_interconnect_0|cmd_mux_004|src_data [80] & ( 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1] & 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout  & !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q 
// )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_004|src_data [80] & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout  & 
// ((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]) # (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_004|src_data [80]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .lut_mask = 64'h2233223322002200;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y28_N41
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y28_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout  & ( 
// ((\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [1])) # (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout  & 
// ( (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [1]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .lut_mask = 64'h000F000F333F333F;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y28_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  
// & ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout  & ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  ) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout  & ( ((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout 
//  & \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1])) # (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]) 
// ) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout  & ( ((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout  
// & \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1])) # (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]) ) 
// ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
        .datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .lut_mask = 64'h05FF000005FF3333;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y28_N31
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y28_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout  = SUM(( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] 
// ) + ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10  ))
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6  = CARRY(( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
        .cout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y28_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2] = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// (!\u0|mm_interconnect_0|cmd_mux_004|src_data [81] & \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] & 
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_004|src_data [81]),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .lut_mask = 64'h00F000F000CC00CC;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y28_N13
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y28_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout  & ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ) ) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout  
// & ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ) ) ) ) # ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout  
// & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]))) # (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout )) ) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout 
//  & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 .lut_mask = 64'h11111B1BBBBBBBBB;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y28_N59
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y29_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~1 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~1_sumout  = SUM(( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~4_combout  ) + ( VCC ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~6  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~4_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~6 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~1_sumout ),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~1 .lut_mask = 64'h0000000000000F0F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y29_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~1_sumout  & ( (\u0|hps_0|fpga_interfaces|h2f_AWBURST [1] & 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector28~0_combout  & !\u0|hps_0|fpga_interfaces|h2f_AWBURST [0])) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~1_sumout  & ( 
// (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & ((!\u0|hps_0|fpga_interfaces|h2f_AWBURST [1]) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector28~0_combout ))) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [1]),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector28~0_combout ),
        .datac(gnd),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~1_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0 .lut_mask = 64'hBB00BB0011001100;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y28_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|src_data[82] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|src_data [82] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout  & ( (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ) ) ) 
// # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout  & ( ((\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout )) # (\u0|mm_interconnect_0|cmd_mux_004|saved_grant 
// [0]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_004|src_data [82]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[82] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[82] .lut_mask = 64'h5577557700330033;
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[82] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y28_N8
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_004|src_data [82]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y28_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3] = (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout  & 
// ((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3])) # 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|cmd_mux_004|src_data [82])))))

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_004|src_data [82]),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .lut_mask = 64'h00D800D800D800D8;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y28_N44
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y28_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & ( 
// ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout  & \u0|mm_interconnect_0|cmd_mux_004|saved_grant [0])) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [3]) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & 
// ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout  & \u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [3]),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .lut_mask = 64'h0303030357575757;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y28_N47
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y28_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  & ( 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) # 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((\u0|mm_interconnect_0|cmd_mux_004|src_data [86]))) ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_004|src_data [86]),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .lut_mask = 64'h0000000053535353;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y28_N56
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y28_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout  = SUM(( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3] 
// ) + ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3] ) + ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y28_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout  & ( 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3])) # 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]))) # (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout )))) ) ) # ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout  & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3])) # (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .lut_mask = 64'h0A5F0A5F2A7F2A7F;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y27_N16
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y27_N15
cyclonev_lcell_comb \u0|data_read_en_rx|always0~0 (
// Equation(s):
// \u0|data_read_en_rx|always0~0_combout  = ( !\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [1] & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [0] & 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_write~combout  & (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]))) ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [0]),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_write~combout ),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|data_read_en_rx|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|data_read_en_rx|always0~0 .extended_lut = "off";
defparam \u0|data_read_en_rx|always0~0 .lut_mask = 64'h2000200000000000;
defparam \u0|data_read_en_rx|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y26_N14
dffeas \u0|data_read_en_rx|data_out (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|data_read_en_rx|data_out~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|data_read_en_rx|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|data_read_en_rx|data_out~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|data_read_en_rx|data_out .is_wysiwyg = "true";
defparam \u0|data_read_en_rx|data_out .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X35_Y7_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Add9~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Add9~1_sumout  = SUM(( \u0|data_read_en_rx|data_out~q  ) + ( \A_SPW_TOP|rx_data|rd_ptr [0] ) + ( !VCC ))
// \A_SPW_TOP|rx_data|Add9~2  = CARRY(( \u0|data_read_en_rx|data_out~q  ) + ( \A_SPW_TOP|rx_data|rd_ptr [0] ) + ( !VCC ))

        .dataa(gnd),
        .datab(!\u0|data_read_en_rx|data_out~q ),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(),
        .sumout(\A_SPW_TOP|rx_data|Add9~1_sumout ),
        .cout(\A_SPW_TOP|rx_data|Add9~2 ),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Add9~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Add9~1 .lut_mask = 64'h0000F0F000003333;
defparam \A_SPW_TOP|rx_data|Add9~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X32_Y14_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|counter_writer[0]~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|counter_writer[0]~0_combout  = !\A_SPW_TOP|rx_data|counter_writer [0]

        .dataa(!\A_SPW_TOP|rx_data|counter_writer [0]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|counter_writer[0]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|counter_writer[0]~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|counter_writer[0]~0 .lut_mask = 64'hAAAAAAAAAAAAAAAA;
defparam \A_SPW_TOP|rx_data|counter_writer[0]~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y3_N12
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|rx_buffer_write~1 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|rx_buffer_write~1_combout  = ( !\A_SPW_TOP|SPW|RX|last_is_timec~q  & ( \A_SPW_TOP|SPW|RX|last_is_data~q  ) ) # ( !\A_SPW_TOP|SPW|RX|last_is_timec~q  & ( !\A_SPW_TOP|SPW|RX|last_is_data~q  & ( (\A_SPW_TOP|SPW|RX|control [2] & 
// (\A_SPW_TOP|SPW|RX|last_is_control~q  & (!\A_SPW_TOP|SPW|RX|control [0] $ (!\A_SPW_TOP|SPW|RX|control [1])))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|control [0]),
        .datab(!\A_SPW_TOP|SPW|RX|control [1]),
        .datac(!\A_SPW_TOP|SPW|RX|control [2]),
        .datad(!\A_SPW_TOP|SPW|RX|last_is_control~q ),
        .datae(!\A_SPW_TOP|SPW|RX|last_is_timec~q ),
        .dataf(!\A_SPW_TOP|SPW|RX|last_is_data~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|rx_buffer_write~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_buffer_write~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|rx_buffer_write~1 .lut_mask = 64'h00060000FFFF0000;
defparam \A_SPW_TOP|SPW|RX|rx_buffer_write~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y3_N36
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|rx_buffer_write~0 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|rx_buffer_write~0_combout  = ( !\A_SPW_TOP|SPW|RX|ready_data_p_r~q  & ( !\A_SPW_TOP|SPW|RX|always1~0_combout  & ( (!\A_SPW_TOP|SPW|RX|ready_control_p_r~q  & (!\A_SPW_TOP|SPW|RX|ready_data~combout  & ((\A_SPW_TOP|SPW|RX|rx_buffer_write~q 
// ) # (\A_SPW_TOP|SPW|RX|rx_buffer_write~1_combout )))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_buffer_write~1_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_buffer_write~q ),
        .datac(!\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),
        .datad(!\A_SPW_TOP|SPW|RX|ready_data~combout ),
        .datae(!\A_SPW_TOP|SPW|RX|ready_data_p_r~q ),
        .dataf(!\A_SPW_TOP|SPW|RX|always1~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|rx_buffer_write~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_buffer_write~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|rx_buffer_write~0 .lut_mask = 64'h7000000000000000;
defparam \A_SPW_TOP|SPW|RX|rx_buffer_write~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y3_N41
dffeas \A_SPW_TOP|SPW|RX|rx_buffer_write (
        .clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|RX|rx_buffer_write~0_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|rx_buffer_write~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_buffer_write .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|rx_buffer_write .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X32_Y14_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|counter_reader[0]~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|counter_reader[0]~0_combout  = !\A_SPW_TOP|rx_data|counter_reader [0]

        .dataa(gnd),
        .datab(!\A_SPW_TOP|rx_data|counter_reader [0]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|counter_reader[0]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|counter_reader[0]~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|counter_reader[0]~0 .lut_mask = 64'hCCCCCCCCCCCCCCCC;
defparam \A_SPW_TOP|rx_data|counter_reader[0]~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y13_N39
cyclonev_lcell_comb \A_SPW_TOP|rx_data|state_data_read~9 (
// Equation(s):
// \A_SPW_TOP|rx_data|state_data_read~9_combout  = ( \A_SPW_TOP|rx_data|state_data_read.00~q  & ( \A_SPW_TOP|rx_data|state_data_read.01~q  & ( (!\u0|data_read_en_rx|data_out~q  & !\A_SPW_TOP|rx_data|state_data_read.10~q ) ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|data_read_en_rx|data_out~q ),
        .datad(!\A_SPW_TOP|rx_data|state_data_read.10~q ),
        .datae(!\A_SPW_TOP|rx_data|state_data_read.00~q ),
        .dataf(!\A_SPW_TOP|rx_data|state_data_read.01~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|state_data_read~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|state_data_read~9 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|state_data_read~9 .lut_mask = 64'h000000000000F000;
defparam \A_SPW_TOP|rx_data|state_data_read~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y13_N33
cyclonev_lcell_comb \A_SPW_TOP|rx_data|state_data_read.10~feeder (
// Equation(s):
// \A_SPW_TOP|rx_data|state_data_read.10~feeder_combout  = ( \A_SPW_TOP|rx_data|state_data_read~9_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|state_data_read~9_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|state_data_read.10~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|state_data_read.10~feeder .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|state_data_read.10~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|rx_data|state_data_read.10~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y13_N35
dffeas \A_SPW_TOP|rx_data|state_data_read.10 (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|rx_data|state_data_read.10~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|state_data_read.10~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|state_data_read.10 .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|state_data_read.10 .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y13_N51
cyclonev_lcell_comb \A_SPW_TOP|rx_data|state_data_read~8 (
// Equation(s):
// \A_SPW_TOP|rx_data|state_data_read~8_combout  = ( \A_SPW_TOP|rx_data|state_data_read.00~q  & ( \A_SPW_TOP|rx_data|state_data_read.01~q  & ( (\u0|data_read_en_rx|data_out~q  & !\A_SPW_TOP|rx_data|state_data_read.10~q ) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|state_data_read.00~q  & ( !\A_SPW_TOP|rx_data|state_data_read.01~q  & ( (\u0|data_read_en_rx|data_out~q  & (!\A_SPW_TOP|rx_data|f_empty~q  & !\A_SPW_TOP|rx_data|state_data_read.10~q )) ) ) )

        .dataa(gnd),
        .datab(!\u0|data_read_en_rx|data_out~q ),
        .datac(!\A_SPW_TOP|rx_data|f_empty~q ),
        .datad(!\A_SPW_TOP|rx_data|state_data_read.10~q ),
        .datae(!\A_SPW_TOP|rx_data|state_data_read.00~q ),
        .dataf(!\A_SPW_TOP|rx_data|state_data_read.01~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|state_data_read~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|state_data_read~8 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|state_data_read~8 .lut_mask = 64'h3000000000003300;
defparam \A_SPW_TOP|rx_data|state_data_read~8 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y13_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|state_data_read.01~feeder (
// Equation(s):
// \A_SPW_TOP|rx_data|state_data_read.01~feeder_combout  = ( \A_SPW_TOP|rx_data|state_data_read~8_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|state_data_read~8_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|state_data_read.01~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|state_data_read.01~feeder .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|state_data_read.01~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|rx_data|state_data_read.01~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y13_N8
dffeas \A_SPW_TOP|rx_data|state_data_read.01 (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|rx_data|state_data_read.01~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|state_data_read.01~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|state_data_read.01 .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|state_data_read.01 .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y13_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|always5~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|always5~0_combout  = ( \A_SPW_TOP|rx_data|state_data_read.01~q  & ( !\u0|data_read_en_rx|data_out~q  ) )

        .dataa(gnd),
        .datab(!\u0|data_read_en_rx|data_out~q ),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|state_data_read.01~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|always5~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|always5~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|always5~0 .lut_mask = 64'h00000000CCCCCCCC;
defparam \A_SPW_TOP|rx_data|always5~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X32_Y14_N41
dffeas \A_SPW_TOP|rx_data|counter_reader[0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|counter_reader[0]~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|rx_data|always5~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|counter_reader [0]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|counter_reader[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|counter_reader[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X32_Y14_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Add8~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Add8~1_sumout  = SUM(( !\A_SPW_TOP|rx_data|counter_reader [0] $ (!\A_SPW_TOP|rx_data|counter_writer [0]) ) + ( !VCC ) + ( !VCC ))
// \A_SPW_TOP|rx_data|Add8~2  = CARRY(( !\A_SPW_TOP|rx_data|counter_reader [0] $ (!\A_SPW_TOP|rx_data|counter_writer [0]) ) + ( !VCC ) + ( !VCC ))
// \A_SPW_TOP|rx_data|Add8~3  = SHARE((!\A_SPW_TOP|rx_data|counter_reader [0]) # (\A_SPW_TOP|rx_data|counter_writer [0]))

        .dataa(gnd),
        .datab(!\A_SPW_TOP|rx_data|counter_reader [0]),
        .datac(!\A_SPW_TOP|rx_data|counter_writer [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(),
        .sumout(\A_SPW_TOP|rx_data|Add8~1_sumout ),
        .cout(\A_SPW_TOP|rx_data|Add8~2 ),
        .shareout(\A_SPW_TOP|rx_data|Add8~3 ));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Add8~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Add8~1 .lut_mask = 64'h0000CFCF00003C3C;
defparam \A_SPW_TOP|rx_data|Add8~1 .shared_arith = "on";
// synopsys translate_on

// Location: FF_X32_Y14_N2
dffeas \A_SPW_TOP|rx_data|counter[0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|rx_data|Add8~1_sumout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|counter [0]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|counter[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|counter[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X32_Y14_N39
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Add7~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Add7~0_combout  = !\A_SPW_TOP|rx_data|counter_reader [1] $ (!\A_SPW_TOP|rx_data|counter_reader [0])

        .dataa(!\A_SPW_TOP|rx_data|counter_reader [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\A_SPW_TOP|rx_data|counter_reader [0]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Add7~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Add7~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Add7~0 .lut_mask = 64'h55AA55AA55AA55AA;
defparam \A_SPW_TOP|rx_data|Add7~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X32_Y14_N38
dffeas \A_SPW_TOP|rx_data|counter_reader[1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Add7~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|rx_data|always5~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|counter_reader [1]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|counter_reader[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|counter_reader[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X32_Y14_N27
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Add6~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Add6~0_combout  = !\A_SPW_TOP|rx_data|counter_writer [0] $ (!\A_SPW_TOP|rx_data|counter_writer [1])

        .dataa(!\A_SPW_TOP|rx_data|counter_writer [0]),
        .datab(gnd),
        .datac(!\A_SPW_TOP|rx_data|counter_writer [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Add6~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Add6~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Add6~0 .lut_mask = 64'h5A5A5A5A5A5A5A5A;
defparam \A_SPW_TOP|rx_data|Add6~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X32_Y14_N59
dffeas \A_SPW_TOP|rx_data|counter_writer[1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Add6~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|rx_data|state_data_write.10~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|counter_writer [1]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|counter_writer[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|counter_writer[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X32_Y14_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Add8~5 (
// Equation(s):
// \A_SPW_TOP|rx_data|Add8~5_sumout  = SUM(( !\A_SPW_TOP|rx_data|counter_reader [1] $ (\A_SPW_TOP|rx_data|counter_writer [1]) ) + ( \A_SPW_TOP|rx_data|Add8~3  ) + ( \A_SPW_TOP|rx_data|Add8~2  ))
// \A_SPW_TOP|rx_data|Add8~6  = CARRY(( !\A_SPW_TOP|rx_data|counter_reader [1] $ (\A_SPW_TOP|rx_data|counter_writer [1]) ) + ( \A_SPW_TOP|rx_data|Add8~3  ) + ( \A_SPW_TOP|rx_data|Add8~2  ))
// \A_SPW_TOP|rx_data|Add8~7  = SHARE((!\A_SPW_TOP|rx_data|counter_reader [1] & \A_SPW_TOP|rx_data|counter_writer [1]))

        .dataa(!\A_SPW_TOP|rx_data|counter_reader [1]),
        .datab(gnd),
        .datac(!\A_SPW_TOP|rx_data|counter_writer [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\A_SPW_TOP|rx_data|Add8~2 ),
        .sharein(\A_SPW_TOP|rx_data|Add8~3 ),
        .combout(),
        .sumout(\A_SPW_TOP|rx_data|Add8~5_sumout ),
        .cout(\A_SPW_TOP|rx_data|Add8~6 ),
        .shareout(\A_SPW_TOP|rx_data|Add8~7 ));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Add8~5 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Add8~5 .lut_mask = 64'h00000A0A0000A5A5;
defparam \A_SPW_TOP|rx_data|Add8~5 .shared_arith = "on";
// synopsys translate_on

// Location: FF_X32_Y14_N5
dffeas \A_SPW_TOP|rx_data|counter[1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|rx_data|Add8~5_sumout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|counter [1]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|counter[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|counter[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X32_Y14_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Add7~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Add7~1_combout  = ( \A_SPW_TOP|rx_data|counter_reader [0] & ( !\A_SPW_TOP|rx_data|counter_reader [2] $ (!\A_SPW_TOP|rx_data|counter_reader [1]) ) ) # ( !\A_SPW_TOP|rx_data|counter_reader [0] & ( \A_SPW_TOP|rx_data|counter_reader [2] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|rx_data|counter_reader [2]),
        .datad(!\A_SPW_TOP|rx_data|counter_reader [1]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|counter_reader [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Add7~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Add7~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Add7~1 .lut_mask = 64'h0F0F0F0F0FF00FF0;
defparam \A_SPW_TOP|rx_data|Add7~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X32_Y14_N47
dffeas \A_SPW_TOP|rx_data|counter_reader[2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Add7~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|rx_data|always5~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|counter_reader [2]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|counter_reader[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|counter_reader[2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X32_Y14_N45
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Add7~2 (
// Equation(s):
// \A_SPW_TOP|rx_data|Add7~2_combout  = !\A_SPW_TOP|rx_data|counter_reader [3] $ (((!\A_SPW_TOP|rx_data|counter_reader [1]) # ((!\A_SPW_TOP|rx_data|counter_reader [0]) # (!\A_SPW_TOP|rx_data|counter_reader [2]))))

        .dataa(!\A_SPW_TOP|rx_data|counter_reader [1]),
        .datab(!\A_SPW_TOP|rx_data|counter_reader [0]),
        .datac(!\A_SPW_TOP|rx_data|counter_reader [3]),
        .datad(!\A_SPW_TOP|rx_data|counter_reader [2]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Add7~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Add7~2 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Add7~2 .lut_mask = 64'h0F1E0F1E0F1E0F1E;
defparam \A_SPW_TOP|rx_data|Add7~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X32_Y14_N44
dffeas \A_SPW_TOP|rx_data|counter_reader[3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Add7~2_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|rx_data|always5~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|counter_reader [3]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|counter_reader[3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|counter_reader[3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X32_Y14_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Add7~3 (
// Equation(s):
// \A_SPW_TOP|rx_data|Add7~3_combout  = ( \A_SPW_TOP|rx_data|counter_reader [4] & ( (!\A_SPW_TOP|rx_data|counter_reader [1]) # ((!\A_SPW_TOP|rx_data|counter_reader [0]) # ((!\A_SPW_TOP|rx_data|counter_reader [2]) # (!\A_SPW_TOP|rx_data|counter_reader [3]))) 
// ) ) # ( !\A_SPW_TOP|rx_data|counter_reader [4] & ( (\A_SPW_TOP|rx_data|counter_reader [1] & (\A_SPW_TOP|rx_data|counter_reader [0] & (\A_SPW_TOP|rx_data|counter_reader [2] & \A_SPW_TOP|rx_data|counter_reader [3]))) ) )

        .dataa(!\A_SPW_TOP|rx_data|counter_reader [1]),
        .datab(!\A_SPW_TOP|rx_data|counter_reader [0]),
        .datac(!\A_SPW_TOP|rx_data|counter_reader [2]),
        .datad(!\A_SPW_TOP|rx_data|counter_reader [3]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|counter_reader [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Add7~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Add7~3 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Add7~3 .lut_mask = 64'h00010001FFFEFFFE;
defparam \A_SPW_TOP|rx_data|Add7~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X32_Y14_N32
dffeas \A_SPW_TOP|rx_data|counter_reader[4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Add7~3_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|rx_data|always5~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|counter_reader [4]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|counter_reader[4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|counter_reader[4] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X32_Y14_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Add7~4 (
// Equation(s):
// \A_SPW_TOP|rx_data|Add7~4_combout  = ( \A_SPW_TOP|rx_data|counter_reader [4] & ( \A_SPW_TOP|rx_data|counter_reader [2] & ( !\A_SPW_TOP|rx_data|counter_reader [5] $ (((!\A_SPW_TOP|rx_data|counter_reader [3]) # ((!\A_SPW_TOP|rx_data|counter_reader [1]) # 
// (!\A_SPW_TOP|rx_data|counter_reader [0])))) ) ) ) # ( !\A_SPW_TOP|rx_data|counter_reader [4] & ( \A_SPW_TOP|rx_data|counter_reader [2] & ( \A_SPW_TOP|rx_data|counter_reader [5] ) ) ) # ( \A_SPW_TOP|rx_data|counter_reader [4] & ( 
// !\A_SPW_TOP|rx_data|counter_reader [2] & ( \A_SPW_TOP|rx_data|counter_reader [5] ) ) ) # ( !\A_SPW_TOP|rx_data|counter_reader [4] & ( !\A_SPW_TOP|rx_data|counter_reader [2] & ( \A_SPW_TOP|rx_data|counter_reader [5] ) ) )

        .dataa(!\A_SPW_TOP|rx_data|counter_reader [5]),
        .datab(!\A_SPW_TOP|rx_data|counter_reader [3]),
        .datac(!\A_SPW_TOP|rx_data|counter_reader [1]),
        .datad(!\A_SPW_TOP|rx_data|counter_reader [0]),
        .datae(!\A_SPW_TOP|rx_data|counter_reader [4]),
        .dataf(!\A_SPW_TOP|rx_data|counter_reader [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Add7~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Add7~4 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Add7~4 .lut_mask = 64'h5555555555555556;
defparam \A_SPW_TOP|rx_data|Add7~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X32_Y14_N35
dffeas \A_SPW_TOP|rx_data|counter_reader[5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Add7~4_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|rx_data|always5~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|counter_reader [5]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|counter_reader[5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|counter_reader[5] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X32_Y14_N57
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Add6~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Add6~1_combout  = ( \A_SPW_TOP|rx_data|counter_writer [2] & ( (!\A_SPW_TOP|rx_data|counter_writer [0]) # (!\A_SPW_TOP|rx_data|counter_writer [1]) ) ) # ( !\A_SPW_TOP|rx_data|counter_writer [2] & ( (\A_SPW_TOP|rx_data|counter_writer [0] 
// & \A_SPW_TOP|rx_data|counter_writer [1]) ) )

        .dataa(!\A_SPW_TOP|rx_data|counter_writer [0]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\A_SPW_TOP|rx_data|counter_writer [1]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|counter_writer [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Add6~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Add6~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Add6~1 .lut_mask = 64'h00550055FFAAFFAA;
defparam \A_SPW_TOP|rx_data|Add6~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X32_Y14_N53
dffeas \A_SPW_TOP|rx_data|counter_writer[2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Add6~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|rx_data|state_data_write.10~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|counter_writer [2]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|counter_writer[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|counter_writer[2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X32_Y14_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Add6~3 (
// Equation(s):
// \A_SPW_TOP|rx_data|Add6~3_combout  = ( \A_SPW_TOP|rx_data|counter_writer [4] & ( (!\A_SPW_TOP|rx_data|counter_writer [0]) # ((!\A_SPW_TOP|rx_data|counter_writer [1]) # ((!\A_SPW_TOP|rx_data|counter_writer [2]) # (!\A_SPW_TOP|rx_data|counter_writer [3]))) 
// ) ) # ( !\A_SPW_TOP|rx_data|counter_writer [4] & ( (\A_SPW_TOP|rx_data|counter_writer [0] & (\A_SPW_TOP|rx_data|counter_writer [1] & (\A_SPW_TOP|rx_data|counter_writer [2] & \A_SPW_TOP|rx_data|counter_writer [3]))) ) )

        .dataa(!\A_SPW_TOP|rx_data|counter_writer [0]),
        .datab(!\A_SPW_TOP|rx_data|counter_writer [1]),
        .datac(!\A_SPW_TOP|rx_data|counter_writer [2]),
        .datad(!\A_SPW_TOP|rx_data|counter_writer [3]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|counter_writer [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Add6~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Add6~3 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Add6~3 .lut_mask = 64'h00010001FFFEFFFE;
defparam \A_SPW_TOP|rx_data|Add6~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X32_Y14_N20
dffeas \A_SPW_TOP|rx_data|counter_writer[4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Add6~3_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|rx_data|state_data_write.10~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|counter_writer [4]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|counter_writer[4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|counter_writer[4] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X32_Y14_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Add6~4 (
// Equation(s):
// \A_SPW_TOP|rx_data|Add6~4_combout  = ( \A_SPW_TOP|rx_data|counter_writer [4] & ( \A_SPW_TOP|rx_data|counter_writer [2] & ( !\A_SPW_TOP|rx_data|counter_writer [5] $ (((!\A_SPW_TOP|rx_data|counter_writer [0]) # ((!\A_SPW_TOP|rx_data|counter_writer [1]) # 
// (!\A_SPW_TOP|rx_data|counter_writer [3])))) ) ) ) # ( !\A_SPW_TOP|rx_data|counter_writer [4] & ( \A_SPW_TOP|rx_data|counter_writer [2] & ( \A_SPW_TOP|rx_data|counter_writer [5] ) ) ) # ( \A_SPW_TOP|rx_data|counter_writer [4] & ( 
// !\A_SPW_TOP|rx_data|counter_writer [2] & ( \A_SPW_TOP|rx_data|counter_writer [5] ) ) ) # ( !\A_SPW_TOP|rx_data|counter_writer [4] & ( !\A_SPW_TOP|rx_data|counter_writer [2] & ( \A_SPW_TOP|rx_data|counter_writer [5] ) ) )

        .dataa(!\A_SPW_TOP|rx_data|counter_writer [0]),
        .datab(!\A_SPW_TOP|rx_data|counter_writer [1]),
        .datac(!\A_SPW_TOP|rx_data|counter_writer [3]),
        .datad(!\A_SPW_TOP|rx_data|counter_writer [5]),
        .datae(!\A_SPW_TOP|rx_data|counter_writer [4]),
        .dataf(!\A_SPW_TOP|rx_data|counter_writer [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Add6~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Add6~4 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Add6~4 .lut_mask = 64'h00FF00FF00FF01FE;
defparam \A_SPW_TOP|rx_data|Add6~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X32_Y14_N23
dffeas \A_SPW_TOP|rx_data|counter_writer[5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Add6~4_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|rx_data|state_data_write.10~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|counter_writer [5]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|counter_writer[5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|counter_writer[5] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X32_Y14_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Add8~9 (
// Equation(s):
// \A_SPW_TOP|rx_data|Add8~9_sumout  = SUM(( !\A_SPW_TOP|rx_data|counter_writer [2] $ (\A_SPW_TOP|rx_data|counter_reader [2]) ) + ( \A_SPW_TOP|rx_data|Add8~7  ) + ( \A_SPW_TOP|rx_data|Add8~6  ))
// \A_SPW_TOP|rx_data|Add8~10  = CARRY(( !\A_SPW_TOP|rx_data|counter_writer [2] $ (\A_SPW_TOP|rx_data|counter_reader [2]) ) + ( \A_SPW_TOP|rx_data|Add8~7  ) + ( \A_SPW_TOP|rx_data|Add8~6  ))
// \A_SPW_TOP|rx_data|Add8~11  = SHARE((\A_SPW_TOP|rx_data|counter_writer [2] & !\A_SPW_TOP|rx_data|counter_reader [2]))

        .dataa(gnd),
        .datab(!\A_SPW_TOP|rx_data|counter_writer [2]),
        .datac(!\A_SPW_TOP|rx_data|counter_reader [2]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\A_SPW_TOP|rx_data|Add8~6 ),
        .sharein(\A_SPW_TOP|rx_data|Add8~7 ),
        .combout(),
        .sumout(\A_SPW_TOP|rx_data|Add8~9_sumout ),
        .cout(\A_SPW_TOP|rx_data|Add8~10 ),
        .shareout(\A_SPW_TOP|rx_data|Add8~11 ));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Add8~9 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Add8~9 .lut_mask = 64'h000030300000C3C3;
defparam \A_SPW_TOP|rx_data|Add8~9 .shared_arith = "on";
// synopsys translate_on

// Location: MLABCELL_X32_Y14_N9
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Add8~13 (
// Equation(s):
// \A_SPW_TOP|rx_data|Add8~13_sumout  = SUM(( !\A_SPW_TOP|rx_data|counter_writer [3] $ (\A_SPW_TOP|rx_data|counter_reader [3]) ) + ( \A_SPW_TOP|rx_data|Add8~11  ) + ( \A_SPW_TOP|rx_data|Add8~10  ))
// \A_SPW_TOP|rx_data|Add8~14  = CARRY(( !\A_SPW_TOP|rx_data|counter_writer [3] $ (\A_SPW_TOP|rx_data|counter_reader [3]) ) + ( \A_SPW_TOP|rx_data|Add8~11  ) + ( \A_SPW_TOP|rx_data|Add8~10  ))
// \A_SPW_TOP|rx_data|Add8~15  = SHARE((\A_SPW_TOP|rx_data|counter_writer [3] & !\A_SPW_TOP|rx_data|counter_reader [3]))

        .dataa(!\A_SPW_TOP|rx_data|counter_writer [3]),
        .datab(gnd),
        .datac(!\A_SPW_TOP|rx_data|counter_reader [3]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\A_SPW_TOP|rx_data|Add8~10 ),
        .sharein(\A_SPW_TOP|rx_data|Add8~11 ),
        .combout(),
        .sumout(\A_SPW_TOP|rx_data|Add8~13_sumout ),
        .cout(\A_SPW_TOP|rx_data|Add8~14 ),
        .shareout(\A_SPW_TOP|rx_data|Add8~15 ));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Add8~13 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Add8~13 .lut_mask = 64'h000050500000A5A5;
defparam \A_SPW_TOP|rx_data|Add8~13 .shared_arith = "on";
// synopsys translate_on

// Location: MLABCELL_X32_Y14_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Add8~17 (
// Equation(s):
// \A_SPW_TOP|rx_data|Add8~17_sumout  = SUM(( !\A_SPW_TOP|rx_data|counter_reader [4] $ (\A_SPW_TOP|rx_data|counter_writer [4]) ) + ( \A_SPW_TOP|rx_data|Add8~15  ) + ( \A_SPW_TOP|rx_data|Add8~14  ))
// \A_SPW_TOP|rx_data|Add8~18  = CARRY(( !\A_SPW_TOP|rx_data|counter_reader [4] $ (\A_SPW_TOP|rx_data|counter_writer [4]) ) + ( \A_SPW_TOP|rx_data|Add8~15  ) + ( \A_SPW_TOP|rx_data|Add8~14  ))
// \A_SPW_TOP|rx_data|Add8~19  = SHARE((!\A_SPW_TOP|rx_data|counter_reader [4] & \A_SPW_TOP|rx_data|counter_writer [4]))

        .dataa(gnd),
        .datab(!\A_SPW_TOP|rx_data|counter_reader [4]),
        .datac(!\A_SPW_TOP|rx_data|counter_writer [4]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\A_SPW_TOP|rx_data|Add8~14 ),
        .sharein(\A_SPW_TOP|rx_data|Add8~15 ),
        .combout(),
        .sumout(\A_SPW_TOP|rx_data|Add8~17_sumout ),
        .cout(\A_SPW_TOP|rx_data|Add8~18 ),
        .shareout(\A_SPW_TOP|rx_data|Add8~19 ));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Add8~17 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Add8~17 .lut_mask = 64'h00000C0C0000C3C3;
defparam \A_SPW_TOP|rx_data|Add8~17 .shared_arith = "on";
// synopsys translate_on

// Location: MLABCELL_X32_Y14_N15
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Add8~21 (
// Equation(s):
// \A_SPW_TOP|rx_data|Add8~21_sumout  = SUM(( !\A_SPW_TOP|rx_data|counter_reader [5] $ (\A_SPW_TOP|rx_data|counter_writer [5]) ) + ( \A_SPW_TOP|rx_data|Add8~19  ) + ( \A_SPW_TOP|rx_data|Add8~18  ))

        .dataa(!\A_SPW_TOP|rx_data|counter_reader [5]),
        .datab(gnd),
        .datac(!\A_SPW_TOP|rx_data|counter_writer [5]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\A_SPW_TOP|rx_data|Add8~18 ),
        .sharein(\A_SPW_TOP|rx_data|Add8~19 ),
        .combout(),
        .sumout(\A_SPW_TOP|rx_data|Add8~21_sumout ),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Add8~21 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Add8~21 .lut_mask = 64'h000000000000A5A5;
defparam \A_SPW_TOP|rx_data|Add8~21 .shared_arith = "on";
// synopsys translate_on

// Location: FF_X32_Y14_N17
dffeas \A_SPW_TOP|rx_data|counter[5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|rx_data|Add8~21_sumout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|counter [5]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|counter[5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|counter[5] .power_up = "low";
// synopsys translate_on

// Location: FF_X32_Y14_N14
dffeas \A_SPW_TOP|rx_data|counter[4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|rx_data|Add8~17_sumout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|counter [4]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|counter[4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|counter[4] .power_up = "low";
// synopsys translate_on

// Location: FF_X32_Y14_N8
dffeas \A_SPW_TOP|rx_data|counter[2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|rx_data|Add8~9_sumout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|counter [2]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|counter[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|counter[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y14_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Equal9~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Equal9~0_combout  = ( \A_SPW_TOP|rx_data|counter [4] & ( \A_SPW_TOP|rx_data|counter [2] & ( (\A_SPW_TOP|rx_data|counter [3] & (\A_SPW_TOP|rx_data|counter [0] & (\A_SPW_TOP|rx_data|counter [1] & \A_SPW_TOP|rx_data|counter [5]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|counter [3]),
        .datab(!\A_SPW_TOP|rx_data|counter [0]),
        .datac(!\A_SPW_TOP|rx_data|counter [1]),
        .datad(!\A_SPW_TOP|rx_data|counter [5]),
        .datae(!\A_SPW_TOP|rx_data|counter [4]),
        .dataf(!\A_SPW_TOP|rx_data|counter [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Equal9~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Equal9~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Equal9~0 .lut_mask = 64'h0000000000000001;
defparam \A_SPW_TOP|rx_data|Equal9~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y14_N32
dffeas \A_SPW_TOP|rx_data|f_full (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|rx_data|Equal9~0_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|f_full~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|f_full .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|f_full .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X36_Y9_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|state_data_write~8 (
// Equation(s):
// \A_SPW_TOP|rx_data|state_data_write~8_combout  = ( \A_SPW_TOP|rx_data|f_full~q  & ( (!\A_SPW_TOP|rx_data|state_data_write.10~q  & (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_buffer_write~q  & \A_SPW_TOP|rx_data|state_data_write.01~q 
// ))) ) ) # ( !\A_SPW_TOP|rx_data|f_full~q  & ( (!\A_SPW_TOP|rx_data|state_data_write.10~q  & (\A_SPW_TOP|SPW|RX|rx_buffer_write~q  & (!\A_SPW_TOP|rx_data|state_data_write.00~q  $ (\A_SPW_TOP|rx_data|state_data_write.01~q )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.10~q ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|SPW|RX|rx_buffer_write~q ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|f_full~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|state_data_write~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|state_data_write~8 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|state_data_write~8 .lut_mask = 64'h0802080200020002;
defparam \A_SPW_TOP|rx_data|state_data_write~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y9_N53
dffeas \A_SPW_TOP|rx_data|state_data_write.01 (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|state_data_write~8_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|state_data_write.01 .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|state_data_write.01 .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X36_Y9_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|state_data_write~7 (
// Equation(s):
// \A_SPW_TOP|rx_data|state_data_write~7_combout  = ( \A_SPW_TOP|rx_data|f_full~q  & ( (!\A_SPW_TOP|rx_data|state_data_write.10~q  & (\A_SPW_TOP|rx_data|state_data_write.00~q  & \A_SPW_TOP|rx_data|state_data_write.01~q )) ) ) # ( !\A_SPW_TOP|rx_data|f_full~q 
//  & ( (!\A_SPW_TOP|rx_data|state_data_write.10~q  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_buffer_write~q  & !\A_SPW_TOP|rx_data|state_data_write.01~q )) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|state_data_write.01~q ))))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.10~q ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|SPW|RX|rx_buffer_write~q ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|f_full~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|state_data_write~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|state_data_write~7 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|state_data_write~7 .lut_mask = 64'h0822082200220022;
defparam \A_SPW_TOP|rx_data|state_data_write~7 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y9_N23
dffeas \A_SPW_TOP|rx_data|state_data_write.00 (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|state_data_write~7_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|state_data_write.00 .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|state_data_write.00 .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X36_Y9_N33
cyclonev_lcell_comb \A_SPW_TOP|rx_data|state_data_write~9 (
// Equation(s):
// \A_SPW_TOP|rx_data|state_data_write~9_combout  = ( !\A_SPW_TOP|SPW|RX|rx_buffer_write~q  & ( (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|state_data_write.01~q  & !\A_SPW_TOP|rx_data|state_data_write.10~q )) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.10~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|rx_buffer_write~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|state_data_write~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|state_data_write~9 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|state_data_write~9 .lut_mask = 64'h0300030000000000;
defparam \A_SPW_TOP|rx_data|state_data_write~9 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y9_N17
dffeas \A_SPW_TOP|rx_data|state_data_write.10 (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|state_data_write~9_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|state_data_write.10~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|state_data_write.10 .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|state_data_write.10 .power_up = "low";
// synopsys translate_on

// Location: FF_X32_Y14_N56
dffeas \A_SPW_TOP|rx_data|counter_writer[0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|counter_writer[0]~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|rx_data|state_data_write.10~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|counter_writer [0]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|counter_writer[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|counter_writer[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X32_Y14_N51
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Add6~2 (
// Equation(s):
// \A_SPW_TOP|rx_data|Add6~2_combout  = ( \A_SPW_TOP|rx_data|counter_writer [3] & ( (!\A_SPW_TOP|rx_data|counter_writer [0]) # ((!\A_SPW_TOP|rx_data|counter_writer [1]) # (!\A_SPW_TOP|rx_data|counter_writer [2])) ) ) # ( !\A_SPW_TOP|rx_data|counter_writer 
// [3] & ( (\A_SPW_TOP|rx_data|counter_writer [0] & (\A_SPW_TOP|rx_data|counter_writer [1] & \A_SPW_TOP|rx_data|counter_writer [2])) ) )

        .dataa(!\A_SPW_TOP|rx_data|counter_writer [0]),
        .datab(!\A_SPW_TOP|rx_data|counter_writer [1]),
        .datac(gnd),
        .datad(!\A_SPW_TOP|rx_data|counter_writer [2]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|counter_writer [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Add6~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Add6~2 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Add6~2 .lut_mask = 64'h00110011FFEEFFEE;
defparam \A_SPW_TOP|rx_data|Add6~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X32_Y14_N50
dffeas \A_SPW_TOP|rx_data|counter_writer[3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Add6~2_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|rx_data|state_data_write.10~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|counter_writer [3]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|counter_writer[3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|counter_writer[3] .power_up = "low";
// synopsys translate_on

// Location: FF_X32_Y14_N11
dffeas \A_SPW_TOP|rx_data|counter[3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|rx_data|Add8~13_sumout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|counter [3]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|counter[3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|counter[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y14_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Equal10~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Equal10~0_combout  = ( !\A_SPW_TOP|rx_data|counter [4] & ( !\A_SPW_TOP|rx_data|counter [2] & ( (!\A_SPW_TOP|rx_data|counter [3] & (!\A_SPW_TOP|rx_data|counter [0] & (!\A_SPW_TOP|rx_data|counter [1] & !\A_SPW_TOP|rx_data|counter [5]))) ) 
// ) )

        .dataa(!\A_SPW_TOP|rx_data|counter [3]),
        .datab(!\A_SPW_TOP|rx_data|counter [0]),
        .datac(!\A_SPW_TOP|rx_data|counter [1]),
        .datad(!\A_SPW_TOP|rx_data|counter [5]),
        .datae(!\A_SPW_TOP|rx_data|counter [4]),
        .dataf(!\A_SPW_TOP|rx_data|counter [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Equal10~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Equal10~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Equal10~0 .lut_mask = 64'h8000000000000000;
defparam \A_SPW_TOP|rx_data|Equal10~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y14_N14
dffeas \A_SPW_TOP|rx_data|f_empty (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|rx_data|Equal10~0_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|f_empty~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|f_empty .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|f_empty .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y13_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|state_data_read~7 (
// Equation(s):
// \A_SPW_TOP|rx_data|state_data_read~7_combout  = ( \A_SPW_TOP|rx_data|state_data_read.01~q  & ( (\A_SPW_TOP|rx_data|state_data_read.00~q  & !\A_SPW_TOP|rx_data|state_data_read.10~q ) ) ) # ( !\A_SPW_TOP|rx_data|state_data_read.01~q  & ( 
// (!\A_SPW_TOP|rx_data|state_data_read.00~q  & (!\A_SPW_TOP|rx_data|f_empty~q  & (!\A_SPW_TOP|rx_data|state_data_read.10~q  & \u0|data_read_en_rx|data_out~q ))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_read.00~q ),
        .datab(!\A_SPW_TOP|rx_data|f_empty~q ),
        .datac(!\A_SPW_TOP|rx_data|state_data_read.10~q ),
        .datad(!\u0|data_read_en_rx|data_out~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|state_data_read.01~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|state_data_read~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|state_data_read~7 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|state_data_read~7 .lut_mask = 64'h0080008050505050;
defparam \A_SPW_TOP|rx_data|state_data_read~7 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y13_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|state_data_read.00~feeder (
// Equation(s):
// \A_SPW_TOP|rx_data|state_data_read.00~feeder_combout  = ( \A_SPW_TOP|rx_data|state_data_read~7_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|state_data_read~7_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|state_data_read.00~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|state_data_read.00~feeder .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|state_data_read.00~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|rx_data|state_data_read.00~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y13_N56
dffeas \A_SPW_TOP|rx_data|state_data_read.00 (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|rx_data|state_data_read.00~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|state_data_read.00~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|state_data_read.00 .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|state_data_read.00 .power_up = "low";
// synopsys translate_on

// Location: FF_X35_Y7_N20
dffeas \A_SPW_TOP|rx_data|rd_ptr[0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Add9~1_sumout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(!\A_SPW_TOP|rx_data|state_data_read.00~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|rd_ptr [0]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|rd_ptr[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|rd_ptr[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X35_Y7_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Add9~13 (
// Equation(s):
// \A_SPW_TOP|rx_data|Add9~13_sumout  = SUM(( \A_SPW_TOP|rx_data|rd_ptr [1] ) + ( GND ) + ( \A_SPW_TOP|rx_data|Add9~2  ))
// \A_SPW_TOP|rx_data|Add9~14  = CARRY(( \A_SPW_TOP|rx_data|rd_ptr [1] ) + ( GND ) + ( \A_SPW_TOP|rx_data|Add9~2  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\A_SPW_TOP|rx_data|Add9~2 ),
        .sharein(gnd),
        .combout(),
        .sumout(\A_SPW_TOP|rx_data|Add9~13_sumout ),
        .cout(\A_SPW_TOP|rx_data|Add9~14 ),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Add9~13 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Add9~13 .lut_mask = 64'h0000FFFF00000F0F;
defparam \A_SPW_TOP|rx_data|Add9~13 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X35_Y7_N47
dffeas \A_SPW_TOP|rx_data|rd_ptr[1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Add9~13_sumout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(!\A_SPW_TOP|rx_data|state_data_read.00~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|rd_ptr [1]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|rd_ptr[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|rd_ptr[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X35_Y7_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Add9~9 (
// Equation(s):
// \A_SPW_TOP|rx_data|Add9~9_sumout  = SUM(( \A_SPW_TOP|rx_data|rd_ptr [2] ) + ( GND ) + ( \A_SPW_TOP|rx_data|Add9~14  ))
// \A_SPW_TOP|rx_data|Add9~10  = CARRY(( \A_SPW_TOP|rx_data|rd_ptr [2] ) + ( GND ) + ( \A_SPW_TOP|rx_data|Add9~14  ))

        .dataa(gnd),
        .datab(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\A_SPW_TOP|rx_data|Add9~14 ),
        .sharein(gnd),
        .combout(),
        .sumout(\A_SPW_TOP|rx_data|Add9~9_sumout ),
        .cout(\A_SPW_TOP|rx_data|Add9~10 ),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Add9~9 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Add9~9 .lut_mask = 64'h0000FFFF00003333;
defparam \A_SPW_TOP|rx_data|Add9~9 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X35_Y7_N32
dffeas \A_SPW_TOP|rx_data|rd_ptr[2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Add9~9_sumout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(!\A_SPW_TOP|rx_data|state_data_read.00~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|rd_ptr [2]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|rd_ptr[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|rd_ptr[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y5_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|always3~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|always3~0_combout  = ( \A_SPW_TOP|rx_data|rd_ptr [2] & ( (\A_SPW_TOP|rx_data|rd_ptr [0] & \A_SPW_TOP|rx_data|rd_ptr [1]) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|always3~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|always3~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|always3~0 .lut_mask = 64'h0000000003030303;
defparam \A_SPW_TOP|rx_data|always3~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y5_N21
cyclonev_lcell_comb \A_SPW_TOP|rx_data|state_open_slot~8 (
// Equation(s):
// \A_SPW_TOP|rx_data|state_open_slot~8_combout  = ( \A_SPW_TOP|rx_data|always3~0_combout  & ( (!\A_SPW_TOP|rx_data|state_open_slot.01~q  & (!\A_SPW_TOP|rx_data|state_open_slot.00~q  $ (\A_SPW_TOP|rx_data|state_open_slot.10~q ))) # 
// (\A_SPW_TOP|rx_data|state_open_slot.01~q  & (\A_SPW_TOP|rx_data|state_open_slot.00~q  & !\A_SPW_TOP|rx_data|state_open_slot.10~q )) ) ) # ( !\A_SPW_TOP|rx_data|always3~0_combout  & ( (\A_SPW_TOP|rx_data|state_open_slot.01~q  & 
// (\A_SPW_TOP|rx_data|state_open_slot.00~q  & !\A_SPW_TOP|rx_data|state_open_slot.10~q )) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_open_slot.01~q ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|rx_data|state_open_slot.00~q ),
        .datad(!\A_SPW_TOP|rx_data|state_open_slot.10~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|always3~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|state_open_slot~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|state_open_slot~8 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|state_open_slot~8 .lut_mask = 64'h05000500A50AA50A;
defparam \A_SPW_TOP|rx_data|state_open_slot~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y5_N11
dffeas \A_SPW_TOP|rx_data|state_open_slot.00 (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|state_open_slot~8_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|state_open_slot.00~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|state_open_slot.00 .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|state_open_slot.00 .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y5_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector8~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector8~1_combout  = ( \A_SPW_TOP|rx_data|rd_ptr [1] & ( (!\A_SPW_TOP|rx_data|state_open_slot.00~q  & ((!\A_SPW_TOP|rx_data|rd_ptr [2]) # (!\A_SPW_TOP|rx_data|rd_ptr [0]))) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [1] & ( 
// !\A_SPW_TOP|rx_data|state_open_slot.00~q  ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|rx_data|state_open_slot.00~q ),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector8~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector8~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector8~1 .lut_mask = 64'hCCCCCCCCCCC0CCC0;
defparam \A_SPW_TOP|rx_data|Selector8~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y5_N33
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector1~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector1~0_combout  = ( \A_SPW_TOP|rx_data|rd_ptr [0] & ( (\A_SPW_TOP|rx_data|rd_ptr [2] & (!\A_SPW_TOP|rx_data|state_open_slot.00~q  & \A_SPW_TOP|rx_data|rd_ptr [1])) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datab(gnd),
        .datac(!\A_SPW_TOP|rx_data|state_open_slot.00~q ),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector1~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector1~0 .lut_mask = 64'h0000000000500050;
defparam \A_SPW_TOP|rx_data|Selector1~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y5_N9
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Add0~29 (
// Equation(s):
// \A_SPW_TOP|rx_data|Add0~29_sumout  = SUM(( \A_SPW_TOP|rx_data|counter_wait [3] ) + ( GND ) + ( \A_SPW_TOP|rx_data|Add0~34  ))
// \A_SPW_TOP|rx_data|Add0~30  = CARRY(( \A_SPW_TOP|rx_data|counter_wait [3] ) + ( GND ) + ( \A_SPW_TOP|rx_data|Add0~34  ))

        .dataa(!\A_SPW_TOP|rx_data|counter_wait [3]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\A_SPW_TOP|rx_data|Add0~34 ),
        .sharein(gnd),
        .combout(),
        .sumout(\A_SPW_TOP|rx_data|Add0~29_sumout ),
        .cout(\A_SPW_TOP|rx_data|Add0~30 ),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Add0~29 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Add0~29 .lut_mask = 64'h0000FFFF00005555;
defparam \A_SPW_TOP|rx_data|Add0~29 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y5_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Add0~25 (
// Equation(s):
// \A_SPW_TOP|rx_data|Add0~25_sumout  = SUM(( \A_SPW_TOP|rx_data|counter_wait [4] ) + ( GND ) + ( \A_SPW_TOP|rx_data|Add0~30  ))
// \A_SPW_TOP|rx_data|Add0~26  = CARRY(( \A_SPW_TOP|rx_data|counter_wait [4] ) + ( GND ) + ( \A_SPW_TOP|rx_data|Add0~30  ))

        .dataa(gnd),
        .datab(!\A_SPW_TOP|rx_data|counter_wait [4]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\A_SPW_TOP|rx_data|Add0~30 ),
        .sharein(gnd),
        .combout(),
        .sumout(\A_SPW_TOP|rx_data|Add0~25_sumout ),
        .cout(\A_SPW_TOP|rx_data|Add0~26 ),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Add0~25 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Add0~25 .lut_mask = 64'h0000FFFF00003333;
defparam \A_SPW_TOP|rx_data|Add0~25 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y5_N57
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector14~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector14~0_combout  = ( \A_SPW_TOP|rx_data|counter_wait [4] & ( ((\A_SPW_TOP|rx_data|Selector8~0_combout  & \A_SPW_TOP|rx_data|Add0~25_sumout )) # (\A_SPW_TOP|rx_data|Selector8~1_combout ) ) ) # ( !\A_SPW_TOP|rx_data|counter_wait [4] 
// & ( (\A_SPW_TOP|rx_data|Selector8~0_combout  & \A_SPW_TOP|rx_data|Add0~25_sumout ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Selector8~1_combout ),
        .datab(!\A_SPW_TOP|rx_data|Selector8~0_combout ),
        .datac(gnd),
        .datad(!\A_SPW_TOP|rx_data|Add0~25_sumout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|counter_wait [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector14~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector14~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector14~0 .lut_mask = 64'h0033003355775577;
defparam \A_SPW_TOP|rx_data|Selector14~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y5_N14
dffeas \A_SPW_TOP|rx_data|counter_wait[4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector14~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|counter_wait [4]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|counter_wait[4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|counter_wait[4] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y5_N15
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Add0~21 (
// Equation(s):
// \A_SPW_TOP|rx_data|Add0~21_sumout  = SUM(( \A_SPW_TOP|rx_data|counter_wait [5] ) + ( GND ) + ( \A_SPW_TOP|rx_data|Add0~26  ))
// \A_SPW_TOP|rx_data|Add0~22  = CARRY(( \A_SPW_TOP|rx_data|counter_wait [5] ) + ( GND ) + ( \A_SPW_TOP|rx_data|Add0~26  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|rx_data|counter_wait [5]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\A_SPW_TOP|rx_data|Add0~26 ),
        .sharein(gnd),
        .combout(),
        .sumout(\A_SPW_TOP|rx_data|Add0~21_sumout ),
        .cout(\A_SPW_TOP|rx_data|Add0~22 ),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Add0~21 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Add0~21 .lut_mask = 64'h0000FFFF00000F0F;
defparam \A_SPW_TOP|rx_data|Add0~21 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y5_N33
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector13~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector13~0_combout  = ( \A_SPW_TOP|rx_data|Selector8~0_combout  & ( \A_SPW_TOP|rx_data|Add0~21_sumout  ) ) # ( !\A_SPW_TOP|rx_data|Selector8~0_combout  & ( \A_SPW_TOP|rx_data|Add0~21_sumout  & ( (\A_SPW_TOP|rx_data|counter_wait [5] & 
// \A_SPW_TOP|rx_data|Selector8~1_combout ) ) ) ) # ( \A_SPW_TOP|rx_data|Selector8~0_combout  & ( !\A_SPW_TOP|rx_data|Add0~21_sumout  & ( (\A_SPW_TOP|rx_data|counter_wait [5] & \A_SPW_TOP|rx_data|Selector8~1_combout ) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|Selector8~0_combout  & ( !\A_SPW_TOP|rx_data|Add0~21_sumout  & ( (\A_SPW_TOP|rx_data|counter_wait [5] & \A_SPW_TOP|rx_data|Selector8~1_combout ) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|counter_wait [5]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\A_SPW_TOP|rx_data|Selector8~1_combout ),
        .datae(!\A_SPW_TOP|rx_data|Selector8~0_combout ),
        .dataf(!\A_SPW_TOP|rx_data|Add0~21_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector13~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector13~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector13~0 .lut_mask = 64'h005500550055FFFF;
defparam \A_SPW_TOP|rx_data|Selector13~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y5_N20
dffeas \A_SPW_TOP|rx_data|counter_wait[5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector13~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|counter_wait [5]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|counter_wait[5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|counter_wait[5] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y5_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Add0~17 (
// Equation(s):
// \A_SPW_TOP|rx_data|Add0~17_sumout  = SUM(( \A_SPW_TOP|rx_data|counter_wait [6] ) + ( GND ) + ( \A_SPW_TOP|rx_data|Add0~22  ))
// \A_SPW_TOP|rx_data|Add0~18  = CARRY(( \A_SPW_TOP|rx_data|counter_wait [6] ) + ( GND ) + ( \A_SPW_TOP|rx_data|Add0~22  ))

        .dataa(gnd),
        .datab(!\A_SPW_TOP|rx_data|counter_wait [6]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\A_SPW_TOP|rx_data|Add0~22 ),
        .sharein(gnd),
        .combout(),
        .sumout(\A_SPW_TOP|rx_data|Add0~17_sumout ),
        .cout(\A_SPW_TOP|rx_data|Add0~18 ),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Add0~17 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Add0~17 .lut_mask = 64'h0000FFFF00003333;
defparam \A_SPW_TOP|rx_data|Add0~17 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y5_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector12~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector12~0_combout  = ( \A_SPW_TOP|rx_data|counter_wait [6] & ( ((\A_SPW_TOP|rx_data|Selector8~0_combout  & \A_SPW_TOP|rx_data|Add0~17_sumout )) # (\A_SPW_TOP|rx_data|Selector8~1_combout ) ) ) # ( !\A_SPW_TOP|rx_data|counter_wait [6] 
// & ( (\A_SPW_TOP|rx_data|Selector8~0_combout  & \A_SPW_TOP|rx_data|Add0~17_sumout ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Selector8~1_combout ),
        .datab(!\A_SPW_TOP|rx_data|Selector8~0_combout ),
        .datac(!\A_SPW_TOP|rx_data|Add0~17_sumout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|counter_wait [6]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector12~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector12~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector12~0 .lut_mask = 64'h0303030357575757;
defparam \A_SPW_TOP|rx_data|Selector12~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y5_N44
dffeas \A_SPW_TOP|rx_data|counter_wait[6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector12~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|counter_wait [6]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|counter_wait[6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|counter_wait[6] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y5_N21
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Add0~13 (
// Equation(s):
// \A_SPW_TOP|rx_data|Add0~13_sumout  = SUM(( \A_SPW_TOP|rx_data|counter_wait [7] ) + ( GND ) + ( \A_SPW_TOP|rx_data|Add0~18  ))
// \A_SPW_TOP|rx_data|Add0~14  = CARRY(( \A_SPW_TOP|rx_data|counter_wait [7] ) + ( GND ) + ( \A_SPW_TOP|rx_data|Add0~18  ))

        .dataa(!\A_SPW_TOP|rx_data|counter_wait [7]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\A_SPW_TOP|rx_data|Add0~18 ),
        .sharein(gnd),
        .combout(),
        .sumout(\A_SPW_TOP|rx_data|Add0~13_sumout ),
        .cout(\A_SPW_TOP|rx_data|Add0~14 ),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Add0~13 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Add0~13 .lut_mask = 64'h0000FFFF00005555;
defparam \A_SPW_TOP|rx_data|Add0~13 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y5_N51
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector11~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector11~0_combout  = ( \A_SPW_TOP|rx_data|Add0~13_sumout  & ( ((\A_SPW_TOP|rx_data|Selector8~1_combout  & \A_SPW_TOP|rx_data|counter_wait [7])) # (\A_SPW_TOP|rx_data|Selector8~0_combout ) ) ) # ( !\A_SPW_TOP|rx_data|Add0~13_sumout  & 
// ( (\A_SPW_TOP|rx_data|Selector8~1_combout  & \A_SPW_TOP|rx_data|counter_wait [7]) ) )

        .dataa(!\A_SPW_TOP|rx_data|Selector8~1_combout ),
        .datab(!\A_SPW_TOP|rx_data|Selector8~0_combout ),
        .datac(gnd),
        .datad(!\A_SPW_TOP|rx_data|counter_wait [7]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Add0~13_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector11~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector11~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector11~0 .lut_mask = 64'h0055005533773377;
defparam \A_SPW_TOP|rx_data|Selector11~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y5_N23
dffeas \A_SPW_TOP|rx_data|counter_wait[7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector11~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|counter_wait [7]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|counter_wait[7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|counter_wait[7] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y5_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Add0~9 (
// Equation(s):
// \A_SPW_TOP|rx_data|Add0~9_sumout  = SUM(( \A_SPW_TOP|rx_data|counter_wait [8] ) + ( GND ) + ( \A_SPW_TOP|rx_data|Add0~14  ))
// \A_SPW_TOP|rx_data|Add0~10  = CARRY(( \A_SPW_TOP|rx_data|counter_wait [8] ) + ( GND ) + ( \A_SPW_TOP|rx_data|Add0~14  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|rx_data|counter_wait [8]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\A_SPW_TOP|rx_data|Add0~14 ),
        .sharein(gnd),
        .combout(),
        .sumout(\A_SPW_TOP|rx_data|Add0~9_sumout ),
        .cout(\A_SPW_TOP|rx_data|Add0~10 ),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Add0~9 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Add0~9 .lut_mask = 64'h0000FFFF00000F0F;
defparam \A_SPW_TOP|rx_data|Add0~9 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y5_N45
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector10~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector10~0_combout  = (!\A_SPW_TOP|rx_data|Selector8~1_combout  & (\A_SPW_TOP|rx_data|Selector8~0_combout  & (\A_SPW_TOP|rx_data|Add0~9_sumout ))) # (\A_SPW_TOP|rx_data|Selector8~1_combout  & (((\A_SPW_TOP|rx_data|Selector8~0_combout  
// & \A_SPW_TOP|rx_data|Add0~9_sumout )) # (\A_SPW_TOP|rx_data|counter_wait [8])))

        .dataa(!\A_SPW_TOP|rx_data|Selector8~1_combout ),
        .datab(!\A_SPW_TOP|rx_data|Selector8~0_combout ),
        .datac(!\A_SPW_TOP|rx_data|Add0~9_sumout ),
        .datad(!\A_SPW_TOP|rx_data|counter_wait [8]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector10~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector10~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector10~0 .lut_mask = 64'h0357035703570357;
defparam \A_SPW_TOP|rx_data|Selector10~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y5_N26
dffeas \A_SPW_TOP|rx_data|counter_wait[8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector10~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|counter_wait [8]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|counter_wait[8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|counter_wait[8] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y5_N27
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Add0~5 (
// Equation(s):
// \A_SPW_TOP|rx_data|Add0~5_sumout  = SUM(( \A_SPW_TOP|rx_data|counter_wait [9] ) + ( GND ) + ( \A_SPW_TOP|rx_data|Add0~10  ))
// \A_SPW_TOP|rx_data|Add0~6  = CARRY(( \A_SPW_TOP|rx_data|counter_wait [9] ) + ( GND ) + ( \A_SPW_TOP|rx_data|Add0~10  ))

        .dataa(!\A_SPW_TOP|rx_data|counter_wait [9]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\A_SPW_TOP|rx_data|Add0~10 ),
        .sharein(gnd),
        .combout(),
        .sumout(\A_SPW_TOP|rx_data|Add0~5_sumout ),
        .cout(\A_SPW_TOP|rx_data|Add0~6 ),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Add0~5 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Add0~5 .lut_mask = 64'h0000FFFF00005555;
defparam \A_SPW_TOP|rx_data|Add0~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y5_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector9~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector9~0_combout  = ( \A_SPW_TOP|rx_data|counter_wait [9] & ( \A_SPW_TOP|rx_data|Selector8~1_combout  ) ) # ( !\A_SPW_TOP|rx_data|counter_wait [9] & ( \A_SPW_TOP|rx_data|Selector8~1_combout  & ( 
// (\A_SPW_TOP|rx_data|Selector8~0_combout  & \A_SPW_TOP|rx_data|Add0~5_sumout ) ) ) ) # ( \A_SPW_TOP|rx_data|counter_wait [9] & ( !\A_SPW_TOP|rx_data|Selector8~1_combout  & ( (\A_SPW_TOP|rx_data|Selector8~0_combout  & \A_SPW_TOP|rx_data|Add0~5_sumout ) ) ) 
// ) # ( !\A_SPW_TOP|rx_data|counter_wait [9] & ( !\A_SPW_TOP|rx_data|Selector8~1_combout  & ( (\A_SPW_TOP|rx_data|Selector8~0_combout  & \A_SPW_TOP|rx_data|Add0~5_sumout ) ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|rx_data|Selector8~0_combout ),
        .datac(!\A_SPW_TOP|rx_data|Add0~5_sumout ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|rx_data|counter_wait [9]),
        .dataf(!\A_SPW_TOP|rx_data|Selector8~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector9~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector9~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector9~0 .lut_mask = 64'h030303030303FFFF;
defparam \A_SPW_TOP|rx_data|Selector9~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y5_N29
dffeas \A_SPW_TOP|rx_data|counter_wait[9] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector9~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|counter_wait [9]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|counter_wait[9] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|counter_wait[9] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y5_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Add0~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Add0~1_sumout  = SUM(( \A_SPW_TOP|rx_data|counter_wait [10] ) + ( GND ) + ( \A_SPW_TOP|rx_data|Add0~6  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|rx_data|counter_wait [10]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\A_SPW_TOP|rx_data|Add0~6 ),
        .sharein(gnd),
        .combout(),
        .sumout(\A_SPW_TOP|rx_data|Add0~1_sumout ),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Add0~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Add0~1 .lut_mask = 64'h0000FFFF00000F0F;
defparam \A_SPW_TOP|rx_data|Add0~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y5_N39
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector8~2 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector8~2_combout  = ( \A_SPW_TOP|rx_data|Selector8~0_combout  & ( \A_SPW_TOP|rx_data|Add0~1_sumout  ) ) # ( !\A_SPW_TOP|rx_data|Selector8~0_combout  & ( \A_SPW_TOP|rx_data|Add0~1_sumout  & ( (\A_SPW_TOP|rx_data|counter_wait [10] & 
// \A_SPW_TOP|rx_data|Selector8~1_combout ) ) ) ) # ( \A_SPW_TOP|rx_data|Selector8~0_combout  & ( !\A_SPW_TOP|rx_data|Add0~1_sumout  & ( (\A_SPW_TOP|rx_data|counter_wait [10] & \A_SPW_TOP|rx_data|Selector8~1_combout ) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|Selector8~0_combout  & ( !\A_SPW_TOP|rx_data|Add0~1_sumout  & ( (\A_SPW_TOP|rx_data|counter_wait [10] & \A_SPW_TOP|rx_data|Selector8~1_combout ) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|counter_wait [10]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\A_SPW_TOP|rx_data|Selector8~1_combout ),
        .datae(!\A_SPW_TOP|rx_data|Selector8~0_combout ),
        .dataf(!\A_SPW_TOP|rx_data|Add0~1_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector8~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector8~2 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector8~2 .lut_mask = 64'h005500550055FFFF;
defparam \A_SPW_TOP|rx_data|Selector8~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y5_N32
dffeas \A_SPW_TOP|rx_data|counter_wait[10] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector8~2_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|counter_wait [10]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|counter_wait[10] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|counter_wait[10] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y5_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Equal0~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Equal0~0_combout  = ( !\A_SPW_TOP|rx_data|counter_wait [7] & ( \A_SPW_TOP|rx_data|counter_wait [8] & ( (\A_SPW_TOP|rx_data|counter_wait [5] & (!\A_SPW_TOP|rx_data|counter_wait [6] & (!\A_SPW_TOP|rx_data|counter_wait [10] & 
// !\A_SPW_TOP|rx_data|counter_wait [9]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|counter_wait [5]),
        .datab(!\A_SPW_TOP|rx_data|counter_wait [6]),
        .datac(!\A_SPW_TOP|rx_data|counter_wait [10]),
        .datad(!\A_SPW_TOP|rx_data|counter_wait [9]),
        .datae(!\A_SPW_TOP|rx_data|counter_wait [7]),
        .dataf(!\A_SPW_TOP|rx_data|counter_wait [8]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Equal0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Equal0~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Equal0~0 .lut_mask = 64'h0000000040000000;
defparam \A_SPW_TOP|rx_data|Equal0~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y5_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Add0~41 (
// Equation(s):
// \A_SPW_TOP|rx_data|Add0~41_sumout  = SUM(( \A_SPW_TOP|rx_data|counter_wait [0] ) + ( VCC ) + ( !VCC ))
// \A_SPW_TOP|rx_data|Add0~42  = CARRY(( \A_SPW_TOP|rx_data|counter_wait [0] ) + ( VCC ) + ( !VCC ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|rx_data|counter_wait [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(),
        .sumout(\A_SPW_TOP|rx_data|Add0~41_sumout ),
        .cout(\A_SPW_TOP|rx_data|Add0~42 ),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Add0~41 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Add0~41 .lut_mask = 64'h0000000000000F0F;
defparam \A_SPW_TOP|rx_data|Add0~41 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y5_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector18~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector18~0_combout  = ( \A_SPW_TOP|rx_data|rd_ptr [0] & ( (!\A_SPW_TOP|rx_data|state_open_slot.00~q  & (\A_SPW_TOP|rx_data|counter_wait [0] & ((!\A_SPW_TOP|rx_data|rd_ptr [2]) # (!\A_SPW_TOP|rx_data|rd_ptr [1])))) ) ) # ( 
// !\A_SPW_TOP|rx_data|rd_ptr [0] & ( (!\A_SPW_TOP|rx_data|state_open_slot.00~q  & \A_SPW_TOP|rx_data|counter_wait [0]) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datab(!\A_SPW_TOP|rx_data|state_open_slot.00~q ),
        .datac(!\A_SPW_TOP|rx_data|counter_wait [0]),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector18~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector18~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector18~0 .lut_mask = 64'h0C0C0C0C0C080C08;
defparam \A_SPW_TOP|rx_data|Selector18~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y5_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector18~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector18~1_combout  = ( \A_SPW_TOP|rx_data|state_open_slot.01~q  & ( \A_SPW_TOP|rx_data|Selector18~0_combout  ) ) # ( !\A_SPW_TOP|rx_data|state_open_slot.01~q  & ( \A_SPW_TOP|rx_data|Selector18~0_combout  ) ) # ( 
// \A_SPW_TOP|rx_data|state_open_slot.01~q  & ( !\A_SPW_TOP|rx_data|Selector18~0_combout  & ( (\A_SPW_TOP|rx_data|Add0~41_sumout  & (((!\A_SPW_TOP|rx_data|Equal0~0_combout ) # (!\A_SPW_TOP|rx_data|Equal0~1_combout )) # (\A_SPW_TOP|rx_data|Selector1~0_combout 
// ))) ) ) ) # ( !\A_SPW_TOP|rx_data|state_open_slot.01~q  & ( !\A_SPW_TOP|rx_data|Selector18~0_combout  & ( (\A_SPW_TOP|rx_data|Selector1~0_combout  & \A_SPW_TOP|rx_data|Add0~41_sumout ) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Selector1~0_combout ),
        .datab(!\A_SPW_TOP|rx_data|Equal0~0_combout ),
        .datac(!\A_SPW_TOP|rx_data|Add0~41_sumout ),
        .datad(!\A_SPW_TOP|rx_data|Equal0~1_combout ),
        .datae(!\A_SPW_TOP|rx_data|state_open_slot.01~q ),
        .dataf(!\A_SPW_TOP|rx_data|Selector18~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector18~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector18~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector18~1 .lut_mask = 64'h05050F0DFFFFFFFF;
defparam \A_SPW_TOP|rx_data|Selector18~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y5_N56
dffeas \A_SPW_TOP|rx_data|counter_wait[0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector18~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|counter_wait [0]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|counter_wait[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|counter_wait[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y5_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Add0~37 (
// Equation(s):
// \A_SPW_TOP|rx_data|Add0~37_sumout  = SUM(( \A_SPW_TOP|rx_data|counter_wait [1] ) + ( GND ) + ( \A_SPW_TOP|rx_data|Add0~42  ))
// \A_SPW_TOP|rx_data|Add0~38  = CARRY(( \A_SPW_TOP|rx_data|counter_wait [1] ) + ( GND ) + ( \A_SPW_TOP|rx_data|Add0~42  ))

        .dataa(!\A_SPW_TOP|rx_data|counter_wait [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\A_SPW_TOP|rx_data|Add0~42 ),
        .sharein(gnd),
        .combout(),
        .sumout(\A_SPW_TOP|rx_data|Add0~37_sumout ),
        .cout(\A_SPW_TOP|rx_data|Add0~38 ),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Add0~37 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Add0~37 .lut_mask = 64'h0000FFFF00005555;
defparam \A_SPW_TOP|rx_data|Add0~37 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y5_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector17~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector17~0_combout  = ( \A_SPW_TOP|rx_data|Selector8~1_combout  & ( ((\A_SPW_TOP|rx_data|Selector8~0_combout  & \A_SPW_TOP|rx_data|Add0~37_sumout )) # (\A_SPW_TOP|rx_data|counter_wait [1]) ) ) # ( 
// !\A_SPW_TOP|rx_data|Selector8~1_combout  & ( (\A_SPW_TOP|rx_data|Selector8~0_combout  & \A_SPW_TOP|rx_data|Add0~37_sumout ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|rx_data|Selector8~0_combout ),
        .datac(!\A_SPW_TOP|rx_data|counter_wait [1]),
        .datad(!\A_SPW_TOP|rx_data|Add0~37_sumout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector8~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector17~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector17~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector17~0 .lut_mask = 64'h003300330F3F0F3F;
defparam \A_SPW_TOP|rx_data|Selector17~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y5_N38
dffeas \A_SPW_TOP|rx_data|counter_wait[1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector17~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|counter_wait [1]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|counter_wait[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|counter_wait[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y5_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Add0~33 (
// Equation(s):
// \A_SPW_TOP|rx_data|Add0~33_sumout  = SUM(( \A_SPW_TOP|rx_data|counter_wait [2] ) + ( GND ) + ( \A_SPW_TOP|rx_data|Add0~38  ))
// \A_SPW_TOP|rx_data|Add0~34  = CARRY(( \A_SPW_TOP|rx_data|counter_wait [2] ) + ( GND ) + ( \A_SPW_TOP|rx_data|Add0~38  ))

        .dataa(gnd),
        .datab(!\A_SPW_TOP|rx_data|counter_wait [2]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\A_SPW_TOP|rx_data|Add0~38 ),
        .sharein(gnd),
        .combout(),
        .sumout(\A_SPW_TOP|rx_data|Add0~33_sumout ),
        .cout(\A_SPW_TOP|rx_data|Add0~34 ),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Add0~33 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Add0~33 .lut_mask = 64'h0000FFFF00003333;
defparam \A_SPW_TOP|rx_data|Add0~33 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y5_N39
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector16~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector16~0_combout  = ( \A_SPW_TOP|rx_data|Selector8~1_combout  & ( ((\A_SPW_TOP|rx_data|Add0~33_sumout  & \A_SPW_TOP|rx_data|Selector8~0_combout )) # (\A_SPW_TOP|rx_data|counter_wait [2]) ) ) # ( 
// !\A_SPW_TOP|rx_data|Selector8~1_combout  & ( (\A_SPW_TOP|rx_data|Add0~33_sumout  & \A_SPW_TOP|rx_data|Selector8~0_combout ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|rx_data|counter_wait [2]),
        .datac(!\A_SPW_TOP|rx_data|Add0~33_sumout ),
        .datad(!\A_SPW_TOP|rx_data|Selector8~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector8~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector16~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector16~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector16~0 .lut_mask = 64'h000F000F333F333F;
defparam \A_SPW_TOP|rx_data|Selector16~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y5_N41
dffeas \A_SPW_TOP|rx_data|counter_wait[2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|rx_data|Selector16~0_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|counter_wait [2]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|counter_wait[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|counter_wait[2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y5_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector15~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector15~0_combout  = ( \A_SPW_TOP|rx_data|Add0~29_sumout  & ( ((\A_SPW_TOP|rx_data|Selector8~1_combout  & \A_SPW_TOP|rx_data|counter_wait [3])) # (\A_SPW_TOP|rx_data|Selector8~0_combout ) ) ) # ( !\A_SPW_TOP|rx_data|Add0~29_sumout  & 
// ( (\A_SPW_TOP|rx_data|Selector8~1_combout  & \A_SPW_TOP|rx_data|counter_wait [3]) ) )

        .dataa(!\A_SPW_TOP|rx_data|Selector8~1_combout ),
        .datab(!\A_SPW_TOP|rx_data|Selector8~0_combout ),
        .datac(!\A_SPW_TOP|rx_data|counter_wait [3]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Add0~29_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector15~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector15~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector15~0 .lut_mask = 64'h0505050537373737;
defparam \A_SPW_TOP|rx_data|Selector15~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y5_N35
dffeas \A_SPW_TOP|rx_data|counter_wait[3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector15~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|counter_wait [3]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|counter_wait[3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|counter_wait[3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y5_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Equal0~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Equal0~1_combout  = ( !\A_SPW_TOP|rx_data|counter_wait [4] & ( (\A_SPW_TOP|rx_data|counter_wait [3] & (\A_SPW_TOP|rx_data|counter_wait [2] & (!\A_SPW_TOP|rx_data|counter_wait [0] & !\A_SPW_TOP|rx_data|counter_wait [1]))) ) )

        .dataa(!\A_SPW_TOP|rx_data|counter_wait [3]),
        .datab(!\A_SPW_TOP|rx_data|counter_wait [2]),
        .datac(!\A_SPW_TOP|rx_data|counter_wait [0]),
        .datad(!\A_SPW_TOP|rx_data|counter_wait [1]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|counter_wait [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Equal0~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Equal0~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Equal0~1 .lut_mask = 64'h1000100000000000;
defparam \A_SPW_TOP|rx_data|Equal0~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y5_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|state_open_slot~9 (
// Equation(s):
// \A_SPW_TOP|rx_data|state_open_slot~9_combout  = ( \A_SPW_TOP|rx_data|Equal0~1_combout  & ( \A_SPW_TOP|rx_data|Equal0~0_combout  & ( (\A_SPW_TOP|rx_data|state_open_slot.00~q  & ((!\A_SPW_TOP|rx_data|state_open_slot.01~q  & 
// (\A_SPW_TOP|rx_data|state_open_slot.10~q  & \A_SPW_TOP|rx_data|always3~0_combout )) # (\A_SPW_TOP|rx_data|state_open_slot.01~q  & (!\A_SPW_TOP|rx_data|state_open_slot.10~q )))) ) ) ) # ( !\A_SPW_TOP|rx_data|Equal0~1_combout  & ( 
// \A_SPW_TOP|rx_data|Equal0~0_combout  & ( (!\A_SPW_TOP|rx_data|state_open_slot.01~q  & (\A_SPW_TOP|rx_data|state_open_slot.10~q  & (\A_SPW_TOP|rx_data|always3~0_combout  & \A_SPW_TOP|rx_data|state_open_slot.00~q ))) ) ) ) # ( 
// \A_SPW_TOP|rx_data|Equal0~1_combout  & ( !\A_SPW_TOP|rx_data|Equal0~0_combout  & ( (!\A_SPW_TOP|rx_data|state_open_slot.01~q  & (\A_SPW_TOP|rx_data|state_open_slot.10~q  & (\A_SPW_TOP|rx_data|always3~0_combout  & \A_SPW_TOP|rx_data|state_open_slot.00~q 
// ))) ) ) ) # ( !\A_SPW_TOP|rx_data|Equal0~1_combout  & ( !\A_SPW_TOP|rx_data|Equal0~0_combout  & ( (!\A_SPW_TOP|rx_data|state_open_slot.01~q  & (\A_SPW_TOP|rx_data|state_open_slot.10~q  & (\A_SPW_TOP|rx_data|always3~0_combout  & 
// \A_SPW_TOP|rx_data|state_open_slot.00~q ))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_open_slot.01~q ),
        .datab(!\A_SPW_TOP|rx_data|state_open_slot.10~q ),
        .datac(!\A_SPW_TOP|rx_data|always3~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_open_slot.00~q ),
        .datae(!\A_SPW_TOP|rx_data|Equal0~1_combout ),
        .dataf(!\A_SPW_TOP|rx_data|Equal0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|state_open_slot~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|state_open_slot~9 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|state_open_slot~9 .lut_mask = 64'h0002000200020046;
defparam \A_SPW_TOP|rx_data|state_open_slot~9 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y5_N50
dffeas \A_SPW_TOP|rx_data|state_open_slot.10 (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|state_open_slot~9_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|state_open_slot.10~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|state_open_slot.10 .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|state_open_slot.10 .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y5_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|state_open_slot~7 (
// Equation(s):
// \A_SPW_TOP|rx_data|state_open_slot~7_combout  = ( \A_SPW_TOP|rx_data|Equal0~1_combout  & ( \A_SPW_TOP|rx_data|Equal0~0_combout  & ( (!\A_SPW_TOP|rx_data|state_open_slot.01~q  & (!\A_SPW_TOP|rx_data|state_open_slot.10~q  & 
// (\A_SPW_TOP|rx_data|always3~0_combout  & !\A_SPW_TOP|rx_data|state_open_slot.00~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|Equal0~1_combout  & ( \A_SPW_TOP|rx_data|Equal0~0_combout  & ( (!\A_SPW_TOP|rx_data|state_open_slot.10~q  & 
// ((!\A_SPW_TOP|rx_data|state_open_slot.01~q  & (\A_SPW_TOP|rx_data|always3~0_combout  & !\A_SPW_TOP|rx_data|state_open_slot.00~q )) # (\A_SPW_TOP|rx_data|state_open_slot.01~q  & ((\A_SPW_TOP|rx_data|state_open_slot.00~q ))))) ) ) ) # ( 
// \A_SPW_TOP|rx_data|Equal0~1_combout  & ( !\A_SPW_TOP|rx_data|Equal0~0_combout  & ( (!\A_SPW_TOP|rx_data|state_open_slot.10~q  & ((!\A_SPW_TOP|rx_data|state_open_slot.01~q  & (\A_SPW_TOP|rx_data|always3~0_combout  & !\A_SPW_TOP|rx_data|state_open_slot.00~q 
// )) # (\A_SPW_TOP|rx_data|state_open_slot.01~q  & ((\A_SPW_TOP|rx_data|state_open_slot.00~q ))))) ) ) ) # ( !\A_SPW_TOP|rx_data|Equal0~1_combout  & ( !\A_SPW_TOP|rx_data|Equal0~0_combout  & ( (!\A_SPW_TOP|rx_data|state_open_slot.10~q  & 
// ((!\A_SPW_TOP|rx_data|state_open_slot.01~q  & (\A_SPW_TOP|rx_data|always3~0_combout  & !\A_SPW_TOP|rx_data|state_open_slot.00~q )) # (\A_SPW_TOP|rx_data|state_open_slot.01~q  & ((\A_SPW_TOP|rx_data|state_open_slot.00~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_open_slot.01~q ),
        .datab(!\A_SPW_TOP|rx_data|state_open_slot.10~q ),
        .datac(!\A_SPW_TOP|rx_data|always3~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_open_slot.00~q ),
        .datae(!\A_SPW_TOP|rx_data|Equal0~1_combout ),
        .dataf(!\A_SPW_TOP|rx_data|Equal0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|state_open_slot~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|state_open_slot~7 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|state_open_slot~7 .lut_mask = 64'h0844084408440800;
defparam \A_SPW_TOP|rx_data|state_open_slot~7 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X45_Y5_N56
dffeas \A_SPW_TOP|rx_data|state_open_slot.01 (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|state_open_slot~7_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|state_open_slot.01~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|state_open_slot.01 .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|state_open_slot.01 .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y5_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector8~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector8~0_combout  = ( \A_SPW_TOP|rx_data|state_open_slot.01~q  & ( \A_SPW_TOP|rx_data|state_open_slot.00~q  ) ) # ( \A_SPW_TOP|rx_data|state_open_slot.01~q  & ( !\A_SPW_TOP|rx_data|state_open_slot.00~q  ) ) # ( 
// !\A_SPW_TOP|rx_data|state_open_slot.01~q  & ( !\A_SPW_TOP|rx_data|state_open_slot.00~q  & ( (\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|rd_ptr [1] & \A_SPW_TOP|rx_data|rd_ptr [0])) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datab(gnd),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .datae(!\A_SPW_TOP|rx_data|state_open_slot.01~q ),
        .dataf(!\A_SPW_TOP|rx_data|state_open_slot.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector8~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector8~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector8~0 .lut_mask = 64'h0005FFFF0000FFFF;
defparam \A_SPW_TOP|rx_data|Selector8~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y5_N8
dffeas \A_SPW_TOP|rx_data|open_slot_fct (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector8~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|open_slot_fct~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|open_slot_fct .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|open_slot_fct .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X56_Y4_N6
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|fct_flag~2 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|fct_flag~2_combout  = ( \A_SPW_TOP|SPW|TX|fct_flag [0] & ( (!\A_SPW_TOP|SPW|TX|clear_reg_fct_flag~q  & ((!\A_SPW_TOP|rx_data|open_slot_fct~q ) # ((\A_SPW_TOP|SPW|TX|fct_flag [2] & \A_SPW_TOP|SPW|TX|fct_flag [1])))) ) ) # ( 
// !\A_SPW_TOP|SPW|TX|fct_flag [0] & ( (!\A_SPW_TOP|SPW|TX|clear_reg_fct_flag~q  & \A_SPW_TOP|rx_data|open_slot_fct~q ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|clear_reg_fct_flag~q ),
        .datab(!\A_SPW_TOP|SPW|TX|fct_flag [2]),
        .datac(!\A_SPW_TOP|rx_data|open_slot_fct~q ),
        .datad(!\A_SPW_TOP|SPW|TX|fct_flag [1]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|fct_flag [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|fct_flag~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|fct_flag~2 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|fct_flag~2 .lut_mask = 64'h0A0A0A0AA0A2A0A2;
defparam \A_SPW_TOP|SPW|TX|fct_flag~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X56_Y4_N47
dffeas \A_SPW_TOP|SPW|TX|state_fct_send.001 (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|open_slot_fct~q ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|state_fct_send.001~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_fct_send.001 .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|state_fct_send.001 .power_up = "low";
// synopsys translate_on

// Location: FF_X56_Y4_N11
dffeas \A_SPW_TOP|SPW|TX|fct_flag[0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|fct_flag~2_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(!\A_SPW_TOP|SPW|TX|state_fct_send.001~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|fct_flag [0]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|fct_flag[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|fct_flag[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X56_Y4_N21
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|fct_flag~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|fct_flag~0_combout  = ( \A_SPW_TOP|SPW|TX|fct_flag [2] & ( !\A_SPW_TOP|SPW|TX|clear_reg_fct_flag~q  ) ) # ( !\A_SPW_TOP|SPW|TX|fct_flag [2] & ( (!\A_SPW_TOP|SPW|TX|clear_reg_fct_flag~q  & (\A_SPW_TOP|SPW|TX|fct_flag [1] & 
// (\A_SPW_TOP|SPW|TX|fct_flag [0] & \A_SPW_TOP|rx_data|open_slot_fct~q ))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|clear_reg_fct_flag~q ),
        .datab(!\A_SPW_TOP|SPW|TX|fct_flag [1]),
        .datac(!\A_SPW_TOP|SPW|TX|fct_flag [0]),
        .datad(!\A_SPW_TOP|rx_data|open_slot_fct~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|fct_flag [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|fct_flag~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|fct_flag~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|fct_flag~0 .lut_mask = 64'h00020002AAAAAAAA;
defparam \A_SPW_TOP|SPW|TX|fct_flag~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X56_Y4_N20
dffeas \A_SPW_TOP|SPW|TX|fct_flag[2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|fct_flag~0_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(!\A_SPW_TOP|SPW|TX|state_fct_send.001~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|fct_flag [2]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|fct_flag[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|fct_flag[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y3_N57
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|rx_got_fct_fsm~feeder (
// Equation(s):
// \A_SPW_TOP|SPW|RX|rx_got_fct_fsm~feeder_combout  = VCC

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|rx_got_fct_fsm~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_got_fct_fsm~feeder .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|rx_got_fct_fsm~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \A_SPW_TOP|SPW|RX|rx_got_fct_fsm~feeder .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y3_N27
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|control_l_r~0 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|control_l_r~0_combout  = (!\A_SPW_TOP|SPW|RX|ready_control_p_r~q  & (\A_SPW_TOP|SPW|RX|control_l_r [2])) # (\A_SPW_TOP|SPW|RX|ready_control_p_r~q  & ((\A_SPW_TOP|SPW|RX|control [2])))

        .dataa(!\A_SPW_TOP|SPW|RX|control_l_r [2]),
        .datab(!\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),
        .datac(gnd),
        .datad(!\A_SPW_TOP|SPW|RX|control [2]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|control_l_r~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|control_l_r~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|control_l_r~0 .lut_mask = 64'h4477447744774477;
defparam \A_SPW_TOP|SPW|RX|control_l_r~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y3_N2
dffeas \A_SPW_TOP|SPW|RX|control_l_r[2] (
        .clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|RX|control_l_r~0_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(!\A_SPW_TOP|SPW|RX|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|control_l_r [2]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|control_l_r[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|control_l_r[2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y3_N9
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|control_l_r~2 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|control_l_r~2_combout  = (!\A_SPW_TOP|SPW|RX|ready_control_p_r~q  & ((\A_SPW_TOP|SPW|RX|control_l_r [0]))) # (\A_SPW_TOP|SPW|RX|ready_control_p_r~q  & (\A_SPW_TOP|SPW|RX|control [0]))

        .dataa(gnd),
        .datab(!\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),
        .datac(!\A_SPW_TOP|SPW|RX|control [0]),
        .datad(!\A_SPW_TOP|SPW|RX|control_l_r [0]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|control_l_r~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|control_l_r~2 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|control_l_r~2 .lut_mask = 64'h03CF03CF03CF03CF;
defparam \A_SPW_TOP|SPW|RX|control_l_r~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y3_N38
dffeas \A_SPW_TOP|SPW|RX|control_l_r[0] (
        .clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|RX|control_l_r~2_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(!\A_SPW_TOP|SPW|RX|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|control_l_r [0]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|control_l_r[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|control_l_r[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y3_N18
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|control_l_r~1 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|control_l_r~1_combout  = ( \A_SPW_TOP|SPW|RX|control_l_r [1] & ( (!\A_SPW_TOP|SPW|RX|ready_control_p_r~q ) # (\A_SPW_TOP|SPW|RX|control [1]) ) ) # ( !\A_SPW_TOP|SPW|RX|control_l_r [1] & ( (\A_SPW_TOP|SPW|RX|control [1] & 
// \A_SPW_TOP|SPW|RX|ready_control_p_r~q ) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|control [1]),
        .datab(!\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|control_l_r [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|control_l_r~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|control_l_r~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|control_l_r~1 .lut_mask = 64'h11111111DDDDDDDD;
defparam \A_SPW_TOP|SPW|RX|control_l_r~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y3_N41
dffeas \A_SPW_TOP|SPW|RX|control_l_r[1] (
        .clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|RX|control_l_r~1_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(!\A_SPW_TOP|SPW|RX|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|control_l_r [1]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|control_l_r[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|control_l_r[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y3_N36
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|always8~0 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|always8~0_combout  = ( \A_SPW_TOP|SPW|RX|control_l_r [0] & ( \A_SPW_TOP|SPW|RX|control_l_r [1] & ( (\A_SPW_TOP|SPW|RX|control [2] & (!\A_SPW_TOP|SPW|RX|control [1] & (!\A_SPW_TOP|SPW|RX|control_l_r [2] & !\A_SPW_TOP|SPW|RX|control [0]))) 
// ) ) ) # ( !\A_SPW_TOP|SPW|RX|control_l_r [0] & ( \A_SPW_TOP|SPW|RX|control_l_r [1] & ( (\A_SPW_TOP|SPW|RX|control [2] & (!\A_SPW_TOP|SPW|RX|control [1] & !\A_SPW_TOP|SPW|RX|control [0])) ) ) ) # ( \A_SPW_TOP|SPW|RX|control_l_r [0] & ( 
// !\A_SPW_TOP|SPW|RX|control_l_r [1] & ( (\A_SPW_TOP|SPW|RX|control [2] & (!\A_SPW_TOP|SPW|RX|control [1] & !\A_SPW_TOP|SPW|RX|control [0])) ) ) ) # ( !\A_SPW_TOP|SPW|RX|control_l_r [0] & ( !\A_SPW_TOP|SPW|RX|control_l_r [1] & ( (\A_SPW_TOP|SPW|RX|control 
// [2] & (!\A_SPW_TOP|SPW|RX|control [1] & !\A_SPW_TOP|SPW|RX|control [0])) ) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|control [2]),
        .datab(!\A_SPW_TOP|SPW|RX|control [1]),
        .datac(!\A_SPW_TOP|SPW|RX|control_l_r [2]),
        .datad(!\A_SPW_TOP|SPW|RX|control [0]),
        .datae(!\A_SPW_TOP|SPW|RX|control_l_r [0]),
        .dataf(!\A_SPW_TOP|SPW|RX|control_l_r [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|always8~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|always8~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|always8~0 .lut_mask = 64'h4400440044004000;
defparam \A_SPW_TOP|SPW|RX|always8~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y3_N54
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|always10~0 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|always10~0_combout  = ( \A_SPW_TOP|SPW|RX|always8~0_combout  & ( \A_SPW_TOP|SPW|RX|last_is_control~q  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|RX|last_is_control~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|always8~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|always10~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|always10~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|always10~0 .lut_mask = 64'h000000000F0F0F0F;
defparam \A_SPW_TOP|SPW|RX|always10~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y3_N59
dffeas \A_SPW_TOP|SPW|RX|rx_got_fct_fsm (
        .clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(\A_SPW_TOP|SPW|RX|rx_got_fct_fsm~feeder_combout ),
        .asdata(vcc),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\A_SPW_TOP|SPW|RX|always10~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|rx_got_fct_fsm~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_got_fct_fsm .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|rx_got_fct_fsm .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y3_N30
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|rx_got_time_code~0 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|rx_got_time_code~0_combout  = ((\A_SPW_TOP|SPW|RX|last_is_control~q  & \A_SPW_TOP|SPW|RX|rx_got_time_code~q )) # (\A_SPW_TOP|SPW|RX|last_is_timec~q )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|SPW|RX|last_is_control~q ),
        .datac(!\A_SPW_TOP|SPW|RX|rx_got_time_code~q ),
        .datad(!\A_SPW_TOP|SPW|RX|last_is_timec~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|rx_got_time_code~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_got_time_code~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|rx_got_time_code~0 .lut_mask = 64'h03FF03FF03FF03FF;
defparam \A_SPW_TOP|SPW|RX|rx_got_time_code~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y3_N26
dffeas \A_SPW_TOP|SPW|RX|rx_got_time_code (
        .clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|RX|rx_got_time_code~0_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(!\A_SPW_TOP|SPW|RX|last_is_data~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|rx_got_time_code~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_got_time_code .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|rx_got_time_code .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X51_Y4_N12
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|state_fsm~21 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|state_fsm~21_combout  = ( !\A_SPW_TOP|SPW|RX|rx_got_time_code~q  & ( \A_SPW_TOP|SPW|FSM|state_fsm.connecting~q  & ( (!\A_SPW_TOP|SPW|RX|rx_got_fct_fsm~q  & (!\A_SPW_TOP|SPW|RX|rx_error_c~q  & (!\A_SPW_TOP|SPW|RX|rx_got_nchar~q  & 
// !\A_SPW_TOP|SPW|RX|rx_error_d~q ))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_got_fct_fsm~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_error_c~q ),
        .datac(!\A_SPW_TOP|SPW|RX|rx_got_nchar~q ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_error_d~q ),
        .datae(!\A_SPW_TOP|SPW|RX|rx_got_time_code~q ),
        .dataf(!\A_SPW_TOP|SPW|FSM|state_fsm.connecting~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|state_fsm~21_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|state_fsm~21 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|state_fsm~21 .lut_mask = 64'h0000000080000000;
defparam \A_SPW_TOP|SPW|FSM|state_fsm~21 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y4_N30
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|always0~1 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|always0~1_combout  = ( \din_a~input_o  & ( \A_SPW_TOP|SPW|RX|rx_got_null~q  ) ) # ( !\din_a~input_o  & ( (\A_SPW_TOP|SPW|RX|rx_got_null~q  & \sin_a~input_o ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|RX|rx_got_null~q ),
        .datad(!\sin_a~input_o ),
        .datae(gnd),
        .dataf(!\din_a~input_o ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|always0~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|always0~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|always0~1 .lut_mask = 64'h000F000F0F0F0F0F;
defparam \A_SPW_TOP|SPW|FSM|always0~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y4_N57
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|always0~0 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|always0~0_combout  = ( !\A_SPW_TOP|SPW|RX|rx_got_time_code~q  & ( (!\A_SPW_TOP|SPW|RX|rx_got_nchar~q  & (!\A_SPW_TOP|SPW|RX|rx_error_d~q  & (!\A_SPW_TOP|SPW|RX|rx_error_c~q  & !\A_SPW_TOP|SPW|RX|rx_got_fct_fsm~q ))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_got_nchar~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_error_d~q ),
        .datac(!\A_SPW_TOP|SPW|RX|rx_error_c~q ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_got_fct_fsm~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|rx_got_time_code~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|always0~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|always0~0 .lut_mask = 64'h8000800000000000;
defparam \A_SPW_TOP|SPW|FSM|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y4_N54
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|state_fsm~18 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|state_fsm~18_combout  = ( \A_SPW_TOP|SPW|FSM|always0~0_combout  & ( \A_SPW_TOP|SPW|FSM|state_fsm.error_reset~0_combout  & ( (!\A_SPW_TOP|SPW|FSM|state_fsm~21_combout  & (\A_SPW_TOP|SPW|FSM|Selector4~0_combout  & 
// (\A_SPW_TOP|SPW|FSM|always0~1_combout ))) # (\A_SPW_TOP|SPW|FSM|state_fsm~21_combout  & ((!\A_SPW_TOP|SPW|FSM|Equal0~3_combout ) # ((\A_SPW_TOP|SPW|FSM|Selector4~0_combout  & \A_SPW_TOP|SPW|FSM|always0~1_combout )))) ) ) ) # ( 
// !\A_SPW_TOP|SPW|FSM|always0~0_combout  & ( \A_SPW_TOP|SPW|FSM|state_fsm.error_reset~0_combout  & ( (\A_SPW_TOP|SPW|FSM|state_fsm~21_combout  & !\A_SPW_TOP|SPW|FSM|Equal0~3_combout ) ) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|state_fsm~21_combout ),
        .datab(!\A_SPW_TOP|SPW|FSM|Selector4~0_combout ),
        .datac(!\A_SPW_TOP|SPW|FSM|always0~1_combout ),
        .datad(!\A_SPW_TOP|SPW|FSM|Equal0~3_combout ),
        .datae(!\A_SPW_TOP|SPW|FSM|always0~0_combout ),
        .dataf(!\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|state_fsm~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|state_fsm~18 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|state_fsm~18 .lut_mask = 64'h0000000055005703;
defparam \A_SPW_TOP|SPW|FSM|state_fsm~18 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y4_N11
dffeas \A_SPW_TOP|SPW|FSM|state_fsm.connecting (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|FSM|state_fsm~18_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|FSM|state_fsm.connecting~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|state_fsm.connecting .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|state_fsm.connecting .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y4_N21
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|send_fct_tx~0 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|send_fct_tx~0_combout  = ( \A_SPW_TOP|SPW|FSM|state_fsm.run~q  ) # ( !\A_SPW_TOP|SPW|FSM|state_fsm.run~q  & ( \A_SPW_TOP|SPW|FSM|state_fsm.connecting~q  ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|SPW|FSM|state_fsm.connecting~q ),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|FSM|state_fsm.run~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|send_fct_tx~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|send_fct_tx~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|send_fct_tx~0 .lut_mask = 64'h33333333FFFFFFFF;
defparam \A_SPW_TOP|SPW|FSM|send_fct_tx~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y4_N23
dffeas \A_SPW_TOP|SPW|FSM|send_fct_tx (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|SPW|FSM|send_fct_tx~0_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|FSM|send_fct_tx~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|send_fct_tx .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|send_fct_tx .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y21_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_payload~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|src_payload~0_combout  = (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_WDATA [0])

        .dataa(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_WDATA [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_015|src_payload~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|src_payload~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_015|src_payload~0 .lut_mask = 64'h0505050505050505;
defparam \u0|mm_interconnect_0|cmd_mux_015|src_payload~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y21_N38
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_015|src_payload~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y21_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [2] & ( ((\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout )) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [2] & ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] 
// & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 .lut_mask = 64'h0505050537373737;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y21_N5
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y21_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_data[86] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|src_data [86] = ( \u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & ( \u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]) # (\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0]) ) ) ) # 
// ( !\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & ( \u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & ( 
// !\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [0] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]),
        .datae(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_015|src_data [86]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[86] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[86] .lut_mask = 64'h00000F0F00FF0FFF;
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[86] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y21_N59
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_015|src_data [86]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X23_Y21_N50
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_015|src_data [88]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .power_up = "low";
// synopsys translate_on

// Location: FF_X23_Y21_N56
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_015|src_data [87]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y21_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_015|src_data [88] & ( 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1])) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_015|src_data [88] & ( 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & 
// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1])))) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((\u0|mm_interconnect_0|cmd_mux_015|src_data [87])))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_015|src_data [87]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_015|src_data [88]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .lut_mask = 64'h03A303A300A000A0;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y21_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout  = ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  
// & ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]))) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (!\u0|mm_interconnect_0|cmd_mux_015|src_data [86])) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_015|src_data [86]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .lut_mask = 64'h00000000F0AAF0AA;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y21_N47
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y21_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ( (!\u0|mm_interconnect_0|cmd_mux_015|src_data [87] & !\u0|mm_interconnect_0|cmd_mux_015|src_data [88]) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_015|src_data [87]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_015|src_data [88]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .lut_mask = 64'hAA00AA00C0C0C0C0;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y21_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ( (\u0|mm_interconnect_0|cmd_mux_015|src_data [86] & \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] & 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_015|src_data [86]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .lut_mask = 64'h000F000F00550055;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y21_N28
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y21_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  = ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( (!\u0|mm_interconnect_0|cmd_mux_015|src_data [86] & 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] & 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_015|src_data [86]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .lut_mask = 64'h00CC00CC00F000F0;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y21_N26
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y21_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_data[79] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|src_data [79] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~2_combout  & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout  & \u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]) ) ) 
// # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~2_combout  & ( ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout  & \u0|mm_interconnect_0|cmd_mux_015|saved_grant [0])) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant 
// [1]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_015|src_data [79]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[79] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[79] .lut_mask = 64'h33F333F300F000F0;
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[79] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y21_N47
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_015|src_data [79]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y21_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0] = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout 
//  & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg 
// [0])) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|cmd_mux_015|src_data [79]))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_015|src_data [79]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .lut_mask = 64'h00000000CCF0CCF0;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y21_N50
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y21_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout  = SUM(( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly 
// [0] ) + ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14  = CARRY(( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) 
// + ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
        .cout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y21_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout  & ( 
// ((\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [0])) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout  & 
// ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [0]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .lut_mask = 64'h0303030357575757;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y21_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout  = ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  & ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  & ( 
// (((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout  & \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0])) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]) 
// ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  & ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout  & 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0])) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg 
// [0]))) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  & ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout  & 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0])) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg 
// [0]))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  & ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout  & 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0])) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg 
// [0]))) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 .lut_mask = 64'h444C444C444C777F;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y21_N37
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y21_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout  = SUM(( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly 
// [1] ) + ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14  ))
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10  = CARRY(( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) 
// + ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 
//  ))

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
        .cout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .lut_mask = 64'h0000F0F000005555;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y21_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_data[80] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|src_data [80] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~0_combout  & ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~1_combout ) ) ) 
// # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~0_combout  & ( ((\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~1_combout )) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant 
// [0]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_015|src_data [80]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[80] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[80] .lut_mask = 64'h555F555F000F000F;
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[80] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y21_N2
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_015|src_data [80]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y21_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1] = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout 
//  & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg 
// [1]))) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|cmd_mux_015|src_data [80])) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_015|src_data [80]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .lut_mask = 64'h00000000F0AAF0AA;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y21_N8
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y21_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout  & ( 
// ((\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [1])) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout  & 
// ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [1]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
        .datac(gnd),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .lut_mask = 64'h0033003355775577;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y21_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout  = ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout  & ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  ) 
// ) ) # ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout  & ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout  & 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1])) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg 
// [1]) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout  & ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout  & 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1])) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg 
// [1]) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
        .datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .lut_mask = 64'h05FF05FF00003333;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y21_N2
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y21_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout  = SUM(( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10  ))
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6  = CARRY(( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] 
// ) + ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10  
// ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
        .cout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y21_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_data[81] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|src_data [81] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout  & ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~0_combout ) ) ) 
// # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout  & ( ((\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~0_combout )) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant 
// [1]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_015|src_data [81]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[81] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[81] .lut_mask = 64'h3F333F330F000F00;
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[81] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y21_N14
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_015|src_data [81]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y21_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2] = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2])) 
// # (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|cmd_mux_015|src_data [81]))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_015|src_data [81]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .lut_mask = 64'h00000000F5A0F5A0;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y21_N58
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y21_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg 
// [2] & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  
// & (((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout  & \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg 
// [2])))) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 .lut_mask = 64'h111D111DDDDDDDDD;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y21_N23
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y21_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_write (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_write~combout  = ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|WideOr0~0_combout  & 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write~0_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|WideOr0~0_combout ),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_write~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_write .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_write .lut_mask = 64'h00AA00AA00000000;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_write .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y21_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_data[82] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|src_data [82] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout  & ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ) ) ) 
// # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout  & ( ((\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout )) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant 
// [0]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_015|src_data [82]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[82] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[82] .lut_mask = 64'h05FF05FF05050505;
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[82] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y21_N23
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_015|src_data [82]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y21_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3] = ( \u0|mm_interconnect_0|cmd_mux_015|src_data [82] & ( 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3] & 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_015|src_data [82] & ( 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout  & 
// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q 
// ))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_015|src_data [82]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .lut_mask = 64'h00F300F300C000C0;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y21_N14
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y21_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [3] & ( 
// ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout  & \u0|mm_interconnect_0|cmd_mux_015|saved_grant [0])) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [3] & 
// ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout  & \u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
        .datad(gnd),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [3]),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .lut_mask = 64'h0303575703035757;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y21_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout  = ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  
// & ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]))) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|cmd_mux_015|src_data [86])) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_015|src_data [86]),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .lut_mask = 64'h0000000035353535;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y21_N44
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .power_up = "low";
// synopsys translate_on

// Location: FF_X23_Y21_N17
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y21_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout  = SUM(( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly 
// [3] ) + ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3] ) + ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6  ))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .lut_mask = 64'h0000CCCC00000F0F;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y21_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout  & 
// ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg 
// [3])) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]))) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout 
// )))) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3])) 
// # (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .lut_mask = 64'h0C3F0C3F4C7F4C7F;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y21_N25
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y21_N24
cyclonev_lcell_comb \u0|timecode_tx_enable|always0~0 (
// Equation(s):
// \u0|timecode_tx_enable|always0~0_combout  = ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [1] & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [0] & 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_write~combout  & 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [0]),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_write~combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|timecode_tx_enable|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|timecode_tx_enable|always0~0 .extended_lut = "off";
defparam \u0|timecode_tx_enable|always0~0 .lut_mask = 64'h0800080000000000;
defparam \u0|timecode_tx_enable|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y21_N29
dffeas \u0|timecode_tx_enable|data_out (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [0]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|timecode_tx_enable|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|timecode_tx_enable|data_out~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|timecode_tx_enable|data_out .is_wysiwyg = "true";
defparam \u0|timecode_tx_enable|data_out .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y6_N33
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Equal0~5 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Equal0~5_combout  = ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & ( (\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & (!\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & \A_SPW_TOP|SPW|TX|global_counter_transfer [3])) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
        .datab(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
        .datac(gnd),
        .datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Equal0~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Equal0~5 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Equal0~5 .lut_mask = 64'h0044004400000000;
defparam \A_SPW_TOP|SPW|TX|Equal0~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X56_Y6_N48
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Equal0~6 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Equal0~6_combout  = ( \A_SPW_TOP|SPW|TX|global_counter_transfer [2] & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & (\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & !\A_SPW_TOP|SPW|TX|global_counter_transfer [1])) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
        .datab(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
        .datac(gnd),
        .datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Equal0~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Equal0~6 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Equal0~6 .lut_mask = 64'h0000000022002200;
defparam \A_SPW_TOP|SPW|TX|Equal0~6 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X59_Y6_N12
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector42~1 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector42~1_combout  = ( \A_SPW_TOP|SPW|TX|tx_data_in [8] & ( \A_SPW_TOP|SPW|TX|Equal0~6_combout  & ( !\A_SPW_TOP|SPW|TX|Equal0~5_combout  ) ) ) # ( !\A_SPW_TOP|SPW|TX|tx_data_in [8] & ( \A_SPW_TOP|SPW|TX|Equal0~6_combout  & ( 
// !\A_SPW_TOP|SPW|TX|Equal0~5_combout  ) ) ) # ( \A_SPW_TOP|SPW|TX|tx_data_in [8] & ( !\A_SPW_TOP|SPW|TX|Equal0~6_combout  & ( !\A_SPW_TOP|SPW|TX|Equal0~5_combout  ) ) ) # ( !\A_SPW_TOP|SPW|TX|tx_data_in [8] & ( !\A_SPW_TOP|SPW|TX|Equal0~6_combout  & ( 
// (!\A_SPW_TOP|SPW|TX|Equal0~5_combout  & ((!\A_SPW_TOP|tx_data|write_tx~q ) # ((\A_SPW_TOP|SPW|TX|LessThan3~0_combout ) # (\A_SPW_TOP|SPW|TX|char_sent~q )))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|write_tx~q ),
        .datab(!\A_SPW_TOP|SPW|TX|char_sent~q ),
        .datac(!\A_SPW_TOP|SPW|TX|Equal0~5_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|LessThan3~0_combout ),
        .datae(!\A_SPW_TOP|SPW|TX|tx_data_in [8]),
        .dataf(!\A_SPW_TOP|SPW|TX|Equal0~6_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector42~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector42~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector42~1 .lut_mask = 64'hB0F0F0F0F0F0F0F0;
defparam \A_SPW_TOP|SPW|TX|Selector42~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X54_Y6_N6
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_tcode_in~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_tcode_in~0_combout  = (\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & (!\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & (!\A_SPW_TOP|SPW|TX|global_counter_transfer [2] $ (!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]))))

        .dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
        .datab(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
        .datac(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
        .datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|tx_tcode_in~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_tcode_in~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_tcode_in~0 .lut_mask = 64'h1040104010401040;
defparam \A_SPW_TOP|SPW|TX|tx_tcode_in~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y10_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|rd_ptr~5 (
// Equation(s):
// \A_SPW_TOP|tx_data|rd_ptr~5_combout  = ( \A_SPW_TOP|SPW|TX|ready_tx_data~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [0] $ (\A_SPW_TOP|tx_data|f_empty~q ) ) ) # ( !\A_SPW_TOP|SPW|TX|ready_tx_data~q  & ( \A_SPW_TOP|tx_data|rd_ptr [0] ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .datac(!\A_SPW_TOP|tx_data|f_empty~q ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|SPW|TX|ready_tx_data~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|rd_ptr~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|rd_ptr~5 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|rd_ptr~5 .lut_mask = 64'h3333C3C33333C3C3;
defparam \A_SPW_TOP|tx_data|rd_ptr~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y10_N41
dffeas \A_SPW_TOP|tx_data|rd_ptr[0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|rd_ptr~5_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|tx_data|state_data_read.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|rd_ptr [0]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|rd_ptr[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|rd_ptr[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y10_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|rd_ptr~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|rd_ptr~1_combout  = ( \A_SPW_TOP|tx_data|rd_ptr [0] & ( !\A_SPW_TOP|tx_data|rd_ptr [1] $ (((!\A_SPW_TOP|SPW|TX|ready_tx_data~q ) # (\A_SPW_TOP|tx_data|f_empty~q ))) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [0] & ( \A_SPW_TOP|tx_data|rd_ptr 
// [1] ) )

        .dataa(!\A_SPW_TOP|SPW|TX|ready_tx_data~q ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .datad(!\A_SPW_TOP|tx_data|f_empty~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|rd_ptr~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|rd_ptr~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|rd_ptr~1 .lut_mask = 64'h0F0F0F0F5A0F5A0F;
defparam \A_SPW_TOP|tx_data|rd_ptr~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y10_N32
dffeas \A_SPW_TOP|tx_data|rd_ptr[1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|rd_ptr~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|tx_data|state_data_read.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|rd_ptr [1]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|rd_ptr[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|rd_ptr[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y10_N27
cyclonev_lcell_comb \A_SPW_TOP|tx_data|rd_ptr~3 (
// Equation(s):
// \A_SPW_TOP|tx_data|rd_ptr~3_combout  = ( \A_SPW_TOP|SPW|TX|ready_tx_data~q  & ( \A_SPW_TOP|tx_data|rd_ptr [0] & ( !\A_SPW_TOP|tx_data|rd_ptr [2] $ (((!\A_SPW_TOP|tx_data|rd_ptr [1]) # (\A_SPW_TOP|tx_data|f_empty~q ))) ) ) ) # ( 
// !\A_SPW_TOP|SPW|TX|ready_tx_data~q  & ( \A_SPW_TOP|tx_data|rd_ptr [0] & ( \A_SPW_TOP|tx_data|rd_ptr [2] ) ) ) # ( \A_SPW_TOP|SPW|TX|ready_tx_data~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [0] & ( \A_SPW_TOP|tx_data|rd_ptr [2] ) ) ) # ( 
// !\A_SPW_TOP|SPW|TX|ready_tx_data~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [0] & ( \A_SPW_TOP|tx_data|rd_ptr [2] ) ) )

        .dataa(!\A_SPW_TOP|tx_data|f_empty~q ),
        .datab(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .datad(gnd),
        .datae(!\A_SPW_TOP|SPW|TX|ready_tx_data~q ),
        .dataf(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|rd_ptr~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|rd_ptr~3 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|rd_ptr~3 .lut_mask = 64'h0F0F0F0F0F0F2D2D;
defparam \A_SPW_TOP|tx_data|rd_ptr~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y10_N44
dffeas \A_SPW_TOP|tx_data|rd_ptr[2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|rd_ptr~3_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|tx_data|state_data_read.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|rd_ptr [2]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|rd_ptr[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|rd_ptr[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y10_N45
cyclonev_lcell_comb \A_SPW_TOP|tx_data|rd_ptr~2 (
// Equation(s):
// \A_SPW_TOP|tx_data|rd_ptr~2_combout  = ( \A_SPW_TOP|SPW|TX|ready_tx_data~q  & ( \A_SPW_TOP|tx_data|f_empty~q  & ( \A_SPW_TOP|tx_data|rd_ptr [3] ) ) ) # ( !\A_SPW_TOP|SPW|TX|ready_tx_data~q  & ( \A_SPW_TOP|tx_data|f_empty~q  & ( \A_SPW_TOP|tx_data|rd_ptr 
// [3] ) ) ) # ( \A_SPW_TOP|SPW|TX|ready_tx_data~q  & ( !\A_SPW_TOP|tx_data|f_empty~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [3] $ (((!\A_SPW_TOP|tx_data|rd_ptr [1]) # ((!\A_SPW_TOP|tx_data|rd_ptr [0]) # (!\A_SPW_TOP|tx_data|rd_ptr [2])))) ) ) ) # ( 
// !\A_SPW_TOP|SPW|TX|ready_tx_data~q  & ( !\A_SPW_TOP|tx_data|f_empty~q  & ( \A_SPW_TOP|tx_data|rd_ptr [3] ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [3]),
        .datab(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .datae(!\A_SPW_TOP|SPW|TX|ready_tx_data~q ),
        .dataf(!\A_SPW_TOP|tx_data|f_empty~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|rd_ptr~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|rd_ptr~2 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|rd_ptr~2 .lut_mask = 64'h5555555655555555;
defparam \A_SPW_TOP|tx_data|rd_ptr~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y10_N26
dffeas \A_SPW_TOP|tx_data|rd_ptr[3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|rd_ptr~2_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|tx_data|state_data_read.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|rd_ptr [3]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|rd_ptr[3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|rd_ptr[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y10_N57
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Add4~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Add4~0_combout  = (\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|rd_ptr [0] & \A_SPW_TOP|tx_data|rd_ptr [3])))

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .datab(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [3]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Add4~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Add4~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Add4~0 .lut_mask = 64'h0001000100010001;
defparam \A_SPW_TOP|tx_data|Add4~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y10_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|rd_ptr~4 (
// Equation(s):
// \A_SPW_TOP|tx_data|rd_ptr~4_combout  = ( \A_SPW_TOP|tx_data|rd_ptr [4] & ( (!\A_SPW_TOP|SPW|TX|ready_tx_data~q ) # ((!\A_SPW_TOP|tx_data|Add4~0_combout ) # (\A_SPW_TOP|tx_data|f_empty~q )) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [4] & ( 
// (\A_SPW_TOP|SPW|TX|ready_tx_data~q  & (!\A_SPW_TOP|tx_data|f_empty~q  & \A_SPW_TOP|tx_data|Add4~0_combout )) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|ready_tx_data~q ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|tx_data|f_empty~q ),
        .datad(!\A_SPW_TOP|tx_data|Add4~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|rd_ptr~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|rd_ptr~4 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|rd_ptr~4 .lut_mask = 64'h00500050FFAFFFAF;
defparam \A_SPW_TOP|tx_data|rd_ptr~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y10_N17
dffeas \A_SPW_TOP|tx_data|rd_ptr[4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|rd_ptr~4_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|tx_data|state_data_read.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|rd_ptr [4]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|rd_ptr[4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|rd_ptr[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y10_N33
cyclonev_lcell_comb \A_SPW_TOP|tx_data|rd_ptr~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|rd_ptr~0_combout  = ( \A_SPW_TOP|tx_data|f_empty~q  & ( \A_SPW_TOP|tx_data|rd_ptr [5] ) ) # ( !\A_SPW_TOP|tx_data|f_empty~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [5] $ (((!\A_SPW_TOP|SPW|TX|ready_tx_data~q ) # ((!\A_SPW_TOP|tx_data|rd_ptr 
// [4]) # (!\A_SPW_TOP|tx_data|Add4~0_combout )))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|ready_tx_data~q ),
        .datab(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .datac(!\A_SPW_TOP|tx_data|Add4~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [5]),
        .datae(!\A_SPW_TOP|tx_data|f_empty~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|rd_ptr~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|rd_ptr~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|rd_ptr~0 .lut_mask = 64'h01FE00FF01FE00FF;
defparam \A_SPW_TOP|tx_data|rd_ptr~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y10_N56
dffeas \A_SPW_TOP|tx_data|rd_ptr[5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|rd_ptr~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|tx_data|state_data_read.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|rd_ptr [5]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|rd_ptr[5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|rd_ptr[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y14_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_payload~8 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_payload~8_combout  = ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_WDATA [8] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_WDATA [8]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_010|src_payload~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_payload~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_payload~8 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_payload~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y14_N59
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[8] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_010|src_payload~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [8]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[8] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y14_N0
cyclonev_lcell_comb \u0|write_data_fifo_tx|always0~0 (
// Equation(s):
// \u0|write_data_fifo_tx|always0~0_combout  = ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & ( 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [0] & 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [1] & \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_write~combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [0]),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [1]),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_write~combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|write_data_fifo_tx|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|write_data_fifo_tx|always0~0 .extended_lut = "off";
defparam \u0|write_data_fifo_tx|always0~0 .lut_mask = 64'h0080008000000000;
defparam \u0|write_data_fifo_tx|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y14_N23
dffeas \u0|write_data_fifo_tx|data_out[8] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [8]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|write_data_fifo_tx|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|write_data_fifo_tx|data_out [8]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|write_data_fifo_tx|data_out[8] .is_wysiwyg = "true";
defparam \u0|write_data_fifo_tx|data_out[8] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y10_N51
cyclonev_lcell_comb \A_SPW_TOP|tx_data|wr_ptr[0]~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|wr_ptr[0]~0_combout  = !\A_SPW_TOP|tx_data|wr_ptr [0]

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|wr_ptr[0]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|wr_ptr[0]~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|wr_ptr[0]~0 .lut_mask = 64'hF0F0F0F0F0F0F0F0;
defparam \A_SPW_TOP|tx_data|wr_ptr[0]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y10_N59
dffeas \A_SPW_TOP|tx_data|wr_ptr[0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|wr_ptr[0]~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|tx_data|state_data_write.10~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|wr_ptr [0]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|wr_ptr[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|wr_ptr[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y10_N57
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Add0~4 (
// Equation(s):
// \A_SPW_TOP|tx_data|Add0~4_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [1] & ( !\A_SPW_TOP|tx_data|wr_ptr [0] ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( \A_SPW_TOP|tx_data|wr_ptr [0] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Add0~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Add0~4 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Add0~4 .lut_mask = 64'h00FF00FFFF00FF00;
defparam \A_SPW_TOP|tx_data|Add0~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y10_N50
dffeas \A_SPW_TOP|tx_data|wr_ptr[1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Add0~4_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|tx_data|state_data_write.10~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|wr_ptr [1]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|wr_ptr[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|wr_ptr[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y10_N9
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Add0~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Add0~1_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [2] & ( (!\A_SPW_TOP|tx_data|wr_ptr [1]) # (!\A_SPW_TOP|tx_data|wr_ptr [0]) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [2] & ( (\A_SPW_TOP|tx_data|wr_ptr [1] & \A_SPW_TOP|tx_data|wr_ptr [0]) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datab(gnd),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Add0~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Add0~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Add0~1 .lut_mask = 64'h05050505FAFAFAFA;
defparam \A_SPW_TOP|tx_data|Add0~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y10_N41
dffeas \A_SPW_TOP|tx_data|wr_ptr[2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Add0~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|tx_data|state_data_write.10~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|wr_ptr [2]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|wr_ptr[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|wr_ptr[2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y10_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Add0~2 (
// Equation(s):
// \A_SPW_TOP|tx_data|Add0~2_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [3] & ( (!\A_SPW_TOP|tx_data|wr_ptr [1]) # ((!\A_SPW_TOP|tx_data|wr_ptr [2]) # (!\A_SPW_TOP|tx_data|wr_ptr [0])) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [3] & ( (\A_SPW_TOP|tx_data|wr_ptr [1] & 
// (\A_SPW_TOP|tx_data|wr_ptr [2] & \A_SPW_TOP|tx_data|wr_ptr [0])) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datac(gnd),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Add0~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Add0~2 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Add0~2 .lut_mask = 64'h00110011FFEEFFEE;
defparam \A_SPW_TOP|tx_data|Add0~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y10_N32
dffeas \A_SPW_TOP|tx_data|wr_ptr[3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Add0~2_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|tx_data|state_data_write.10~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|wr_ptr [3]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|wr_ptr[3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|wr_ptr[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y12_N51
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Add0~3 (
// Equation(s):
// \A_SPW_TOP|tx_data|Add0~3_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [2] & ( \A_SPW_TOP|tx_data|wr_ptr [4] & ( (!\A_SPW_TOP|tx_data|wr_ptr [3]) # ((!\A_SPW_TOP|tx_data|wr_ptr [0]) # (!\A_SPW_TOP|tx_data|wr_ptr [1])) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [2] & 
// ( \A_SPW_TOP|tx_data|wr_ptr [4] ) ) # ( \A_SPW_TOP|tx_data|wr_ptr [2] & ( !\A_SPW_TOP|tx_data|wr_ptr [4] & ( (\A_SPW_TOP|tx_data|wr_ptr [3] & (\A_SPW_TOP|tx_data|wr_ptr [0] & \A_SPW_TOP|tx_data|wr_ptr [1])) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datad(gnd),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Add0~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Add0~3 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Add0~3 .lut_mask = 64'h00000101FFFFFEFE;
defparam \A_SPW_TOP|tx_data|Add0~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y12_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|wr_ptr[4]~feeder (
// Equation(s):
// \A_SPW_TOP|tx_data|wr_ptr[4]~feeder_combout  = ( \A_SPW_TOP|tx_data|Add0~3_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Add0~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|wr_ptr[4]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|wr_ptr[4]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|wr_ptr[4]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|tx_data|wr_ptr[4]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X45_Y12_N20
dffeas \A_SPW_TOP|tx_data|wr_ptr[4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|tx_data|wr_ptr[4]~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\A_SPW_TOP|tx_data|state_data_write.10~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|wr_ptr [4]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|wr_ptr[4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|wr_ptr[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y12_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Add0~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Add0~0_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [2] & ( \A_SPW_TOP|tx_data|wr_ptr [4] & ( !\A_SPW_TOP|tx_data|wr_ptr [5] $ (((!\A_SPW_TOP|tx_data|wr_ptr [0]) # ((!\A_SPW_TOP|tx_data|wr_ptr [3]) # (!\A_SPW_TOP|tx_data|wr_ptr [1])))) ) ) ) 
// # ( !\A_SPW_TOP|tx_data|wr_ptr [2] & ( \A_SPW_TOP|tx_data|wr_ptr [4] & ( \A_SPW_TOP|tx_data|wr_ptr [5] ) ) ) # ( \A_SPW_TOP|tx_data|wr_ptr [2] & ( !\A_SPW_TOP|tx_data|wr_ptr [4] & ( \A_SPW_TOP|tx_data|wr_ptr [5] ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [2] & 
// ( !\A_SPW_TOP|tx_data|wr_ptr [4] & ( \A_SPW_TOP|tx_data|wr_ptr [5] ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Add0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Add0~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Add0~0 .lut_mask = 64'h5555555555555556;
defparam \A_SPW_TOP|tx_data|Add0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y12_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|wr_ptr[5]~feeder (
// Equation(s):
// \A_SPW_TOP|tx_data|wr_ptr[5]~feeder_combout  = ( \A_SPW_TOP|tx_data|Add0~0_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Add0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|wr_ptr[5]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|wr_ptr[5]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|wr_ptr[5]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|tx_data|wr_ptr[5]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X45_Y12_N56
dffeas \A_SPW_TOP|tx_data|wr_ptr[5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|tx_data|wr_ptr[5]~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\A_SPW_TOP|tx_data|state_data_write.10~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|wr_ptr [5]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|wr_ptr[5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|wr_ptr[5] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y13_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Decoder0~13 (
// Equation(s):
// \A_SPW_TOP|tx_data|Decoder0~13_combout  = ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( !\A_SPW_TOP|tx_data|wr_ptr [4] & ( (\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|wr_ptr [2] & (!\A_SPW_TOP|tx_data|wr_ptr [0] & \A_SPW_TOP|tx_data|wr_ptr [3]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Decoder0~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Decoder0~13 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Decoder0~13 .lut_mask = 64'h0010000000000000;
defparam \A_SPW_TOP|tx_data|Decoder0~13 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y13_N21
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector401~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector401~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( \A_SPW_TOP|tx_data|Decoder0~13_combout  & ( \A_SPW_TOP|tx_data|state_data_write.01~q  ) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( 
// \A_SPW_TOP|tx_data|Decoder0~13_combout  ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .dataf(!\A_SPW_TOP|tx_data|Decoder0~13_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector401~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector401~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector401~0 .lut_mask = 64'h00000000FFFF5555;
defparam \A_SPW_TOP|tx_data|Selector401~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y15_N33
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Decoder0~20 (
// Equation(s):
// \A_SPW_TOP|tx_data|Decoder0~20_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [4] & ( !\A_SPW_TOP|tx_data|wr_ptr [3] & ( (\A_SPW_TOP|tx_data|wr_ptr [5] & (!\A_SPW_TOP|tx_data|wr_ptr [1] & (!\A_SPW_TOP|tx_data|wr_ptr [0] & !\A_SPW_TOP|tx_data|wr_ptr [2]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Decoder0~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Decoder0~20 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Decoder0~20 .lut_mask = 64'h0000400000000000;
defparam \A_SPW_TOP|tx_data|Decoder0~20 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y15_N27
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector437~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector437~0_combout  = ( \A_SPW_TOP|tx_data|Decoder0~20_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q ) # (\A_SPW_TOP|tx_data|state_data_write.01~q ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Decoder0~20_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector437~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector437~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector437~0 .lut_mask = 64'h00000000CFCFCFCF;
defparam \A_SPW_TOP|tx_data|Selector437~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y13_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector437~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector437~1_combout  = ( \A_SPW_TOP|tx_data|mem[48][8]~q  & ( (!\A_SPW_TOP|tx_data|Selector437~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux0~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [8])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[48][8]~q  & ( (\A_SPW_TOP|tx_data|Selector437~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux0~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [8]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector437~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [8]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[48][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector437~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector437~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector437~1 .lut_mask = 64'h04070407F4F7F4F7;
defparam \A_SPW_TOP|tx_data|Selector437~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y13_N53
dffeas \A_SPW_TOP|tx_data|mem[48][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector437~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[48][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[48][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[48][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y11_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Decoder0~18 (
// Equation(s):
// \A_SPW_TOP|tx_data|Decoder0~18_combout  = ( !\A_SPW_TOP|tx_data|wr_ptr [0] & ( \A_SPW_TOP|tx_data|wr_ptr [4] & ( (\A_SPW_TOP|tx_data|wr_ptr [2] & (!\A_SPW_TOP|tx_data|wr_ptr [1] & (!\A_SPW_TOP|tx_data|wr_ptr [5] & !\A_SPW_TOP|tx_data|wr_ptr [3]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Decoder0~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Decoder0~18 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Decoder0~18 .lut_mask = 64'h0000000040000000;
defparam \A_SPW_TOP|tx_data|Decoder0~18 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y11_N57
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector185~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector185~0_combout  = ( \A_SPW_TOP|tx_data|Decoder0~18_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q ) # (\A_SPW_TOP|tx_data|state_data_write.01~q ) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Decoder0~18_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector185~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector185~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector185~0 .lut_mask = 64'h00000000BBBBBBBB;
defparam \A_SPW_TOP|tx_data|Selector185~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y14_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector185~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector185~1_combout  = ( \A_SPW_TOP|tx_data|mem[20][8]~q  & ( (!\A_SPW_TOP|tx_data|Selector185~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux0~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [8]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[20][8]~q  & ( (\A_SPW_TOP|tx_data|Selector185~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux0~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [8])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [8]),
        .datab(!\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|tx_data|Selector185~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[20][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector185~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector185~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector185~1 .lut_mask = 64'h00350035FF35FF35;
defparam \A_SPW_TOP|tx_data|Selector185~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y14_N11
dffeas \A_SPW_TOP|tx_data|mem[20][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector185~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[20][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[20][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[20][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y11_N15
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Decoder0~16 (
// Equation(s):
// \A_SPW_TOP|tx_data|Decoder0~16_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [4] & ( !\A_SPW_TOP|tx_data|wr_ptr [2] & ( (!\A_SPW_TOP|tx_data|wr_ptr [3] & (!\A_SPW_TOP|tx_data|wr_ptr [0] & (!\A_SPW_TOP|tx_data|wr_ptr [5] & !\A_SPW_TOP|tx_data|wr_ptr [1]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Decoder0~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Decoder0~16 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Decoder0~16 .lut_mask = 64'h0000800000000000;
defparam \A_SPW_TOP|tx_data|Decoder0~16 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y11_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector149~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector149~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (\A_SPW_TOP|tx_data|Decoder0~16_combout  & \A_SPW_TOP|tx_data|state_data_write.01~q ) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( 
// \A_SPW_TOP|tx_data|Decoder0~16_combout  ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|tx_data|Decoder0~16_combout ),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector149~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector149~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector149~0 .lut_mask = 64'h3333030333330303;
defparam \A_SPW_TOP|tx_data|Selector149~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y12_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector149~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector149~1_combout  = ( \A_SPW_TOP|tx_data|Selector149~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux0~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [8]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector149~0_combout  & ( \A_SPW_TOP|tx_data|mem[16][8]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [8]),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[16][8]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector149~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector149~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector149~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector149~1 .lut_mask = 64'h00FF00FF53535353;
defparam \A_SPW_TOP|tx_data|Selector149~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y12_N59
dffeas \A_SPW_TOP|tx_data|mem[16][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector149~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[16][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[16][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[16][8] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y14_N9
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Decoder0~22 (
// Equation(s):
// \A_SPW_TOP|tx_data|Decoder0~22_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [4] & ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( (\A_SPW_TOP|tx_data|wr_ptr [2] & (!\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|wr_ptr [5] & !\A_SPW_TOP|tx_data|wr_ptr [3]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Decoder0~22_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Decoder0~22 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Decoder0~22 .lut_mask = 64'h0000040000000000;
defparam \A_SPW_TOP|tx_data|Decoder0~22 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y14_N21
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector473~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector473~0_combout  = ( \A_SPW_TOP|tx_data|Decoder0~22_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q ) # (\A_SPW_TOP|tx_data|state_data_write.01~q ) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Decoder0~22_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector473~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector473~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector473~0 .lut_mask = 64'h00000000DDDDDDDD;
defparam \A_SPW_TOP|tx_data|Selector473~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y13_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector473~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector473~1_combout  = ( \A_SPW_TOP|tx_data|mem[52][8]~q  & ( (!\A_SPW_TOP|tx_data|Selector473~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux0~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [8])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[52][8]~q  & ( (\A_SPW_TOP|tx_data|Selector473~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux0~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [8]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector473~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [8]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[52][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector473~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector473~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector473~1 .lut_mask = 64'h04070407F4F7F4F7;
defparam \A_SPW_TOP|tx_data|Selector473~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y13_N50
dffeas \A_SPW_TOP|tx_data|mem[52][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector473~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[52][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[52][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[52][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y13_N9
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux0~2 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux0~2_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [5] & ( \A_SPW_TOP|tx_data|mem[52][8]~q  & ( (\A_SPW_TOP|tx_data|wr_ptr [2]) # (\A_SPW_TOP|tx_data|mem[48][8]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [5] & ( \A_SPW_TOP|tx_data|mem[52][8]~q 
//  & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & ((\A_SPW_TOP|tx_data|mem[16][8]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|mem[20][8]~q )) ) ) ) # ( \A_SPW_TOP|tx_data|wr_ptr [5] & ( !\A_SPW_TOP|tx_data|mem[52][8]~q  & ( 
// (\A_SPW_TOP|tx_data|mem[48][8]~q  & !\A_SPW_TOP|tx_data|wr_ptr [2]) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [5] & ( !\A_SPW_TOP|tx_data|mem[52][8]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & ((\A_SPW_TOP|tx_data|mem[16][8]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [2] 
// & (\A_SPW_TOP|tx_data|mem[20][8]~q )) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[48][8]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[20][8]~q ),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datad(!\A_SPW_TOP|tx_data|mem[16][8]~q ),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .dataf(!\A_SPW_TOP|tx_data|mem[52][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux0~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux0~2 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux0~2 .lut_mask = 64'h03F3505003F35F5F;
defparam \A_SPW_TOP|tx_data|Mux0~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y15_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Decoder0~17 (
// Equation(s):
// \A_SPW_TOP|tx_data|Decoder0~17_combout  = ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( \A_SPW_TOP|tx_data|wr_ptr [4] & ( (!\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|wr_ptr [3] & (!\A_SPW_TOP|tx_data|wr_ptr [2] & !\A_SPW_TOP|tx_data|wr_ptr [0]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Decoder0~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Decoder0~17 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Decoder0~17 .lut_mask = 64'h0000000020000000;
defparam \A_SPW_TOP|tx_data|Decoder0~17 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y15_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector221~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector221~0_combout  = ( \A_SPW_TOP|tx_data|Decoder0~17_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q ) # (\A_SPW_TOP|tx_data|state_data_write.01~q ) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Decoder0~17_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector221~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector221~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector221~0 .lut_mask = 64'h00000000F5F5F5F5;
defparam \A_SPW_TOP|tx_data|Selector221~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y14_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector221~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector221~1_combout  = ( \A_SPW_TOP|tx_data|Selector221~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux0~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\u0|write_data_fifo_tx|data_out [8])) ) ) # ( !\A_SPW_TOP|tx_data|Selector221~0_combout  & ( \A_SPW_TOP|tx_data|mem[24][8]~q  ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [8]),
        .datab(!\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|mem[24][8]~q ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector221~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector221~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector221~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector221~1 .lut_mask = 64'h0F0F0F0F33553355;
defparam \A_SPW_TOP|tx_data|Selector221~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y14_N29
dffeas \A_SPW_TOP|tx_data|mem[24][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector221~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[24][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[24][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[24][8] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y14_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Decoder0~21 (
// Equation(s):
// \A_SPW_TOP|tx_data|Decoder0~21_combout  = ( !\A_SPW_TOP|tx_data|wr_ptr [0] & ( \A_SPW_TOP|tx_data|wr_ptr [5] & ( (!\A_SPW_TOP|tx_data|wr_ptr [1] & (!\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|wr_ptr [3] & \A_SPW_TOP|tx_data|wr_ptr [4]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Decoder0~21_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Decoder0~21 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Decoder0~21 .lut_mask = 64'h0000000000080000;
defparam \A_SPW_TOP|tx_data|Decoder0~21 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y14_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector509~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector509~0_combout  = ( \A_SPW_TOP|tx_data|Decoder0~21_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q ) # (\A_SPW_TOP|tx_data|state_data_write.01~q ) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Decoder0~21_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector509~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector509~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector509~0 .lut_mask = 64'h00000000AFAFAFAF;
defparam \A_SPW_TOP|tx_data|Selector509~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y13_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector509~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector509~1_combout  = ( \A_SPW_TOP|tx_data|mem[56][8]~q  & ( (!\A_SPW_TOP|tx_data|Selector509~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux0~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [8])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[56][8]~q  & ( (\A_SPW_TOP|tx_data|Selector509~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux0~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [8]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector509~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [8]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[56][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector509~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector509~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector509~1 .lut_mask = 64'h04070407F4F7F4F7;
defparam \A_SPW_TOP|tx_data|Selector509~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y13_N8
dffeas \A_SPW_TOP|tx_data|mem[56][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector509~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[56][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[56][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[56][8] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y14_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Decoder0~23 (
// Equation(s):
// \A_SPW_TOP|tx_data|Decoder0~23_combout  = ( !\A_SPW_TOP|tx_data|wr_ptr [0] & ( \A_SPW_TOP|tx_data|wr_ptr [4] & ( (\A_SPW_TOP|tx_data|wr_ptr [3] & (\A_SPW_TOP|tx_data|wr_ptr [2] & (!\A_SPW_TOP|tx_data|wr_ptr [1] & \A_SPW_TOP|tx_data|wr_ptr [5]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Decoder0~23_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Decoder0~23 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Decoder0~23 .lut_mask = 64'h0000000000100000;
defparam \A_SPW_TOP|tx_data|Decoder0~23 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y14_N51
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector545~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector545~0_combout  = ( \A_SPW_TOP|tx_data|Decoder0~23_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q ) # (\A_SPW_TOP|tx_data|state_data_write.01~q ) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(gnd),
        .datac(gnd),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Decoder0~23_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector545~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector545~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector545~0 .lut_mask = 64'h00000000AAFFAAFF;
defparam \A_SPW_TOP|tx_data|Selector545~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y13_N45
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector545~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector545~1_combout  = ( \A_SPW_TOP|tx_data|Selector545~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux0~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [8]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector545~0_combout  & ( \A_SPW_TOP|tx_data|mem[60][8]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\u0|write_data_fifo_tx|data_out [8]),
        .datad(!\A_SPW_TOP|tx_data|mem[60][8]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector545~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector545~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector545~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector545~1 .lut_mask = 64'h00FF00FF47474747;
defparam \A_SPW_TOP|tx_data|Selector545~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y13_N38
dffeas \A_SPW_TOP|tx_data|mem[60][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector545~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[60][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[60][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[60][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y11_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Decoder0~19 (
// Equation(s):
// \A_SPW_TOP|tx_data|Decoder0~19_combout  = ( !\A_SPW_TOP|tx_data|wr_ptr [5] & ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( (\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|wr_ptr [3] & !\A_SPW_TOP|tx_data|wr_ptr [0]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Decoder0~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Decoder0~19 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Decoder0~19 .lut_mask = 64'h0100000000000000;
defparam \A_SPW_TOP|tx_data|Decoder0~19 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y11_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector257~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector257~0_combout  = (\A_SPW_TOP|tx_data|Decoder0~19_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q ) # (\A_SPW_TOP|tx_data|state_data_write.01~q )))

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .datac(!\A_SPW_TOP|tx_data|Decoder0~19_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector257~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector257~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector257~0 .lut_mask = 64'h0B0B0B0B0B0B0B0B;
defparam \A_SPW_TOP|tx_data|Selector257~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y13_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector257~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector257~1_combout  = ( \u0|write_data_fifo_tx|data_out [8] & ( \A_SPW_TOP|tx_data|mem[28][8]~q  & ( (!\A_SPW_TOP|tx_data|Selector257~0_combout ) # ((\A_SPW_TOP|tx_data|Mux0~20_combout ) # (\A_SPW_TOP|tx_data|state_data_write.00~q )) 
// ) ) ) # ( !\u0|write_data_fifo_tx|data_out [8] & ( \A_SPW_TOP|tx_data|mem[28][8]~q  & ( (!\A_SPW_TOP|tx_data|Selector257~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & \A_SPW_TOP|tx_data|Mux0~20_combout )) ) ) ) # ( 
// \u0|write_data_fifo_tx|data_out [8] & ( !\A_SPW_TOP|tx_data|mem[28][8]~q  & ( (\A_SPW_TOP|tx_data|Selector257~0_combout  & ((\A_SPW_TOP|tx_data|Mux0~20_combout ) # (\A_SPW_TOP|tx_data|state_data_write.00~q ))) ) ) ) # ( !\u0|write_data_fifo_tx|data_out 
// [8] & ( !\A_SPW_TOP|tx_data|mem[28][8]~q  & ( (\A_SPW_TOP|tx_data|Selector257~0_combout  & (!\A_SPW_TOP|tx_data|state_data_write.00~q  & \A_SPW_TOP|tx_data|Mux0~20_combout )) ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|tx_data|Selector257~0_combout ),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .datae(!\u0|write_data_fifo_tx|data_out [8]),
        .dataf(!\A_SPW_TOP|tx_data|mem[28][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector257~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector257~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector257~1 .lut_mask = 64'h00300333CCFCCFFF;
defparam \A_SPW_TOP|tx_data|Selector257~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y13_N26
dffeas \A_SPW_TOP|tx_data|mem[28][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector257~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[28][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[28][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[28][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y13_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux0~3 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux0~3_combout  = ( \A_SPW_TOP|tx_data|mem[60][8]~q  & ( \A_SPW_TOP|tx_data|mem[28][8]~q  & ( ((!\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|mem[24][8]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [5] & ((\A_SPW_TOP|tx_data|mem[56][8]~q 
// )))) # (\A_SPW_TOP|tx_data|wr_ptr [2]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[60][8]~q  & ( \A_SPW_TOP|tx_data|mem[28][8]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [5] & (((\A_SPW_TOP|tx_data|wr_ptr [2])) # (\A_SPW_TOP|tx_data|mem[24][8]~q ))) # 
// (\A_SPW_TOP|tx_data|wr_ptr [5] & (((\A_SPW_TOP|tx_data|mem[56][8]~q  & !\A_SPW_TOP|tx_data|wr_ptr [2])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[60][8]~q  & ( !\A_SPW_TOP|tx_data|mem[28][8]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [5] & 
// (\A_SPW_TOP|tx_data|mem[24][8]~q  & ((!\A_SPW_TOP|tx_data|wr_ptr [2])))) # (\A_SPW_TOP|tx_data|wr_ptr [5] & (((\A_SPW_TOP|tx_data|wr_ptr [2]) # (\A_SPW_TOP|tx_data|mem[56][8]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[60][8]~q  & ( 
// !\A_SPW_TOP|tx_data|mem[28][8]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & ((!\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|mem[24][8]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [5] & ((\A_SPW_TOP|tx_data|mem[56][8]~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[24][8]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[56][8]~q ),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datae(!\A_SPW_TOP|tx_data|mem[60][8]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[28][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux0~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux0~3 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux0~3 .lut_mask = 64'h5300530F53F053FF;
defparam \A_SPW_TOP|tx_data|Mux0~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y11_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Decoder0~4 (
// Equation(s):
// \A_SPW_TOP|tx_data|Decoder0~4_combout  = ( !\A_SPW_TOP|tx_data|wr_ptr [4] & ( !\A_SPW_TOP|tx_data|wr_ptr [0] & ( (!\A_SPW_TOP|tx_data|wr_ptr [1] & (!\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|wr_ptr [3] & !\A_SPW_TOP|tx_data|wr_ptr [5]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Decoder0~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Decoder0~4 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Decoder0~4 .lut_mask = 64'h0800000000000000;
defparam \A_SPW_TOP|tx_data|Decoder0~4 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y11_N51
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector77~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector77~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.01~q  & ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( \A_SPW_TOP|tx_data|Decoder0~4_combout  ) ) ) # ( \A_SPW_TOP|tx_data|state_data_write.01~q  & ( 
// !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( \A_SPW_TOP|tx_data|Decoder0~4_combout  ) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.01~q  & ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( \A_SPW_TOP|tx_data|Decoder0~4_combout  ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|tx_data|Decoder0~4_combout ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector77~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector77~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector77~0 .lut_mask = 64'h0F0F0F0F00000F0F;
defparam \A_SPW_TOP|tx_data|Selector77~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y13_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector77~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector77~1_combout  = ( \u0|write_data_fifo_tx|data_out [8] & ( (!\A_SPW_TOP|tx_data|Selector77~0_combout  & (((\A_SPW_TOP|tx_data|mem[8][8]~q )))) # (\A_SPW_TOP|tx_data|Selector77~0_combout  & 
// (((\A_SPW_TOP|tx_data|state_data_write.00~q )) # (\A_SPW_TOP|tx_data|Mux0~20_combout ))) ) ) # ( !\u0|write_data_fifo_tx|data_out [8] & ( (!\A_SPW_TOP|tx_data|Selector77~0_combout  & (((\A_SPW_TOP|tx_data|mem[8][8]~q )))) # 
// (\A_SPW_TOP|tx_data|Selector77~0_combout  & (\A_SPW_TOP|tx_data|Mux0~20_combout  & (!\A_SPW_TOP|tx_data|state_data_write.00~q ))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[8][8]~q ),
        .datad(!\A_SPW_TOP|tx_data|Selector77~0_combout ),
        .datae(gnd),
        .dataf(!\u0|write_data_fifo_tx|data_out [8]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector77~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector77~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector77~1 .lut_mask = 64'h0F440F440F770F77;
defparam \A_SPW_TOP|tx_data|Selector77~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y13_N56
dffeas \A_SPW_TOP|tx_data|mem[8][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector77~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[8][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[8][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[8][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y11_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Decoder0~12 (
// Equation(s):
// \A_SPW_TOP|tx_data|Decoder0~12_combout  = ( !\A_SPW_TOP|tx_data|wr_ptr [0] & ( \A_SPW_TOP|tx_data|wr_ptr [2] & ( (\A_SPW_TOP|tx_data|wr_ptr [3] & (!\A_SPW_TOP|tx_data|wr_ptr [5] & (!\A_SPW_TOP|tx_data|wr_ptr [1] & !\A_SPW_TOP|tx_data|wr_ptr [4]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Decoder0~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Decoder0~12 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Decoder0~12 .lut_mask = 64'h0000000040000000;
defparam \A_SPW_TOP|tx_data|Decoder0~12 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y11_N57
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector113~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector113~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.01~q  & ( \A_SPW_TOP|tx_data|Decoder0~12_combout  ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.01~q  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// \A_SPW_TOP|tx_data|Decoder0~12_combout ) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|tx_data|Decoder0~12_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector113~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector113~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector113~0 .lut_mask = 64'h0A0A0A0A0F0F0F0F;
defparam \A_SPW_TOP|tx_data|Selector113~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y13_N21
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector113~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector113~1_combout  = ( \A_SPW_TOP|tx_data|mem[12][8]~q  & ( (!\A_SPW_TOP|tx_data|Selector113~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux0~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [8]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[12][8]~q  & ( (\A_SPW_TOP|tx_data|Selector113~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux0~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [8])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [8]),
        .datab(!\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|tx_data|Selector113~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[12][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector113~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector113~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector113~1 .lut_mask = 64'h00350035FF35FF35;
defparam \A_SPW_TOP|tx_data|Selector113~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y13_N41
dffeas \A_SPW_TOP|tx_data|mem[12][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector113~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[12][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[12][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[12][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y15_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Decoder0~5 (
// Equation(s):
// \A_SPW_TOP|tx_data|Decoder0~5_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [3] & ( !\A_SPW_TOP|tx_data|wr_ptr [4] & ( (\A_SPW_TOP|tx_data|wr_ptr [5] & (!\A_SPW_TOP|tx_data|wr_ptr [1] & (!\A_SPW_TOP|tx_data|wr_ptr [2] & !\A_SPW_TOP|tx_data|wr_ptr [0]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Decoder0~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Decoder0~5 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Decoder0~5 .lut_mask = 64'h0000400000000000;
defparam \A_SPW_TOP|tx_data|Decoder0~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y15_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector365~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector365~0_combout  = ( \A_SPW_TOP|tx_data|Decoder0~5_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q ) # (\A_SPW_TOP|tx_data|state_data_write.01~q ) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Decoder0~5_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector365~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector365~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector365~0 .lut_mask = 64'h00000000BBBBBBBB;
defparam \A_SPW_TOP|tx_data|Selector365~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y13_N27
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector365~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector365~1_combout  = ( \A_SPW_TOP|tx_data|mem[40][8]~q  & ( (!\A_SPW_TOP|tx_data|Selector365~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux0~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [8])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[40][8]~q  & ( (\A_SPW_TOP|tx_data|Selector365~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux0~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [8]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector365~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [8]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[40][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector365~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector365~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector365~1 .lut_mask = 64'h04070407F4F7F4F7;
defparam \A_SPW_TOP|tx_data|Selector365~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y13_N53
dffeas \A_SPW_TOP|tx_data|mem[40][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector365~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[40][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[40][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[40][8] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y13_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux0~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux0~1_combout  = ( \A_SPW_TOP|tx_data|mem[44][8]~q  & ( \A_SPW_TOP|tx_data|mem[40][8]~q  & ( ((!\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|mem[8][8]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [2] & ((\A_SPW_TOP|tx_data|mem[12][8]~q 
// )))) # (\A_SPW_TOP|tx_data|wr_ptr [5]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[44][8]~q  & ( \A_SPW_TOP|tx_data|mem[40][8]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & (((\A_SPW_TOP|tx_data|wr_ptr [5])) # (\A_SPW_TOP|tx_data|mem[8][8]~q ))) # 
// (\A_SPW_TOP|tx_data|wr_ptr [2] & (((\A_SPW_TOP|tx_data|mem[12][8]~q  & !\A_SPW_TOP|tx_data|wr_ptr [5])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[44][8]~q  & ( !\A_SPW_TOP|tx_data|mem[40][8]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & 
// (\A_SPW_TOP|tx_data|mem[8][8]~q  & ((!\A_SPW_TOP|tx_data|wr_ptr [5])))) # (\A_SPW_TOP|tx_data|wr_ptr [2] & (((\A_SPW_TOP|tx_data|wr_ptr [5]) # (\A_SPW_TOP|tx_data|mem[12][8]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[44][8]~q  & ( 
// !\A_SPW_TOP|tx_data|mem[40][8]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [5] & ((!\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|mem[8][8]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [2] & ((\A_SPW_TOP|tx_data|mem[12][8]~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[8][8]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[12][8]~q ),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datae(!\A_SPW_TOP|tx_data|mem[44][8]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[40][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux0~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux0~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux0~1 .lut_mask = 64'h5300530F53F053FF;
defparam \A_SPW_TOP|tx_data|Mux0~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y11_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Decoder0~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Decoder0~1_combout  = ( !\A_SPW_TOP|tx_data|wr_ptr [4] & ( \A_SPW_TOP|tx_data|wr_ptr [5] & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & (!\A_SPW_TOP|tx_data|wr_ptr [0] & (!\A_SPW_TOP|tx_data|wr_ptr [1] & !\A_SPW_TOP|tx_data|wr_ptr [3]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Decoder0~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Decoder0~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Decoder0~1 .lut_mask = 64'h0000000080000000;
defparam \A_SPW_TOP|tx_data|Decoder0~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y11_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector293~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector293~0_combout  = ( \A_SPW_TOP|tx_data|Decoder0~1_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q ) # (\A_SPW_TOP|tx_data|state_data_write.01~q ) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Decoder0~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector293~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector293~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector293~0 .lut_mask = 64'h00000000BBBBBBBB;
defparam \A_SPW_TOP|tx_data|Selector293~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y13_N57
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector293~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector293~1_combout  = ( \A_SPW_TOP|tx_data|Mux0~20_combout  & ( (!\A_SPW_TOP|tx_data|Selector293~0_combout  & (((\A_SPW_TOP|tx_data|mem[32][8]~q )))) # (\A_SPW_TOP|tx_data|Selector293~0_combout  & 
// ((!\A_SPW_TOP|tx_data|state_data_write.00~q ) # ((\u0|write_data_fifo_tx|data_out [8])))) ) ) # ( !\A_SPW_TOP|tx_data|Mux0~20_combout  & ( (!\A_SPW_TOP|tx_data|Selector293~0_combout  & (((\A_SPW_TOP|tx_data|mem[32][8]~q )))) # 
// (\A_SPW_TOP|tx_data|Selector293~0_combout  & (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [8])))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Selector293~0_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[32][8]~q ),
        .datad(!\u0|write_data_fifo_tx|data_out [8]),
        .datae(!\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector293~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector293~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector293~1 .lut_mask = 64'h0A1B4E5F0A1B4E5F;
defparam \A_SPW_TOP|tx_data|Selector293~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y13_N11
dffeas \A_SPW_TOP|tx_data|mem[32][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector293~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[32][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[32][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[32][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y11_N9
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Decoder0~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Decoder0~0_combout  = ( !\A_SPW_TOP|tx_data|wr_ptr [2] & ( !\A_SPW_TOP|tx_data|wr_ptr [0] & ( (!\A_SPW_TOP|tx_data|wr_ptr [3] & (!\A_SPW_TOP|tx_data|wr_ptr [4] & (!\A_SPW_TOP|tx_data|wr_ptr [5] & !\A_SPW_TOP|tx_data|wr_ptr [1]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Decoder0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Decoder0~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Decoder0~0 .lut_mask = 64'h8000000000000000;
defparam \A_SPW_TOP|tx_data|Decoder0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y11_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector5~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector5~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( \A_SPW_TOP|tx_data|state_data_write.01~q  & ( \A_SPW_TOP|tx_data|Decoder0~0_combout  ) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( 
// \A_SPW_TOP|tx_data|state_data_write.01~q  & ( \A_SPW_TOP|tx_data|Decoder0~0_combout  ) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( !\A_SPW_TOP|tx_data|state_data_write.01~q  & ( \A_SPW_TOP|tx_data|Decoder0~0_combout  ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|tx_data|Decoder0~0_combout ),
        .datac(gnd),
        .datad(gnd),
        .datae(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector5~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector5~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector5~0 .lut_mask = 64'h3333000033333333;
defparam \A_SPW_TOP|tx_data|Selector5~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y13_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector5~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector5~1_combout  = ( \A_SPW_TOP|tx_data|Selector5~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux0~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out 
// [8]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector5~0_combout  & ( \A_SPW_TOP|tx_data|mem[0][8]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[0][8]~q ),
        .datad(!\u0|write_data_fifo_tx|data_out [8]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector5~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector5~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector5~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector5~1 .lut_mask = 64'h0F0F0F0F44774477;
defparam \A_SPW_TOP|tx_data|Selector5~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y13_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|mem[0][8]~feeder (
// Equation(s):
// \A_SPW_TOP|tx_data|mem[0][8]~feeder_combout  = ( \A_SPW_TOP|tx_data|Selector5~1_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector5~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|mem[0][8]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[0][8]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|mem[0][8]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|tx_data|mem[0][8]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y13_N5
dffeas \A_SPW_TOP|tx_data|mem[0][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|tx_data|mem[0][8]~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[0][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[0][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[0][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y15_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Decoder0~9 (
// Equation(s):
// \A_SPW_TOP|tx_data|Decoder0~9_combout  = ( !\A_SPW_TOP|tx_data|wr_ptr [4] & ( !\A_SPW_TOP|tx_data|wr_ptr [3] & ( (\A_SPW_TOP|tx_data|wr_ptr [2] & (!\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|wr_ptr [5] & !\A_SPW_TOP|tx_data|wr_ptr [0]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Decoder0~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Decoder0~9 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Decoder0~9 .lut_mask = 64'h0400000000000000;
defparam \A_SPW_TOP|tx_data|Decoder0~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y15_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector329~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector329~0_combout  = (\A_SPW_TOP|tx_data|Decoder0~9_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q ) # (\A_SPW_TOP|tx_data|state_data_write.01~q )))

        .dataa(gnd),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Decoder0~9_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector329~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector329~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector329~0 .lut_mask = 64'h0C0F0C0F0C0F0C0F;
defparam \A_SPW_TOP|tx_data|Selector329~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y13_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector329~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector329~1_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector329~0_combout  & ((\A_SPW_TOP|tx_data|mem[36][8]~q ))) # (\A_SPW_TOP|tx_data|Selector329~0_combout  & (\u0|write_data_fifo_tx|data_out 
// [8])) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector329~0_combout  & ((\A_SPW_TOP|tx_data|mem[36][8]~q ))) # (\A_SPW_TOP|tx_data|Selector329~0_combout  & (\A_SPW_TOP|tx_data|Mux0~20_combout )) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [8]),
        .datab(!\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector329~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|mem[36][8]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector329~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector329~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector329~1 .lut_mask = 64'h03F303F305F505F5;
defparam \A_SPW_TOP|tx_data|Selector329~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y13_N59
dffeas \A_SPW_TOP|tx_data|mem[36][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector329~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[36][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[36][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[36][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y11_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Decoder0~8 (
// Equation(s):
// \A_SPW_TOP|tx_data|Decoder0~8_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [2] & ( !\A_SPW_TOP|tx_data|wr_ptr [4] & ( (!\A_SPW_TOP|tx_data|wr_ptr [3] & (!\A_SPW_TOP|tx_data|wr_ptr [0] & (!\A_SPW_TOP|tx_data|wr_ptr [1] & !\A_SPW_TOP|tx_data|wr_ptr [5]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Decoder0~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Decoder0~8 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Decoder0~8 .lut_mask = 64'h0000800000000000;
defparam \A_SPW_TOP|tx_data|Decoder0~8 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y11_N39
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector41~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector41~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.01~q  & ( \A_SPW_TOP|tx_data|Decoder0~8_combout  ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.01~q  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// \A_SPW_TOP|tx_data|Decoder0~8_combout ) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|tx_data|Decoder0~8_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector41~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector41~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector41~0 .lut_mask = 64'h0A0A0A0A0F0F0F0F;
defparam \A_SPW_TOP|tx_data|Selector41~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y13_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector41~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector41~1_combout  = ( \A_SPW_TOP|tx_data|Selector41~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux0~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\u0|write_data_fifo_tx|data_out [8])) ) ) # ( !\A_SPW_TOP|tx_data|Selector41~0_combout  & ( \A_SPW_TOP|tx_data|mem[4][8]~q  ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [8]),
        .datab(!\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|mem[4][8]~q ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector41~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector41~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector41~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector41~1 .lut_mask = 64'h0F0F0F0F33553355;
defparam \A_SPW_TOP|tx_data|Selector41~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y13_N8
dffeas \A_SPW_TOP|tx_data|mem[4][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector41~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[4][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[4][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[4][8] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y13_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux0~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux0~0_combout  = ( \A_SPW_TOP|tx_data|mem[36][8]~q  & ( \A_SPW_TOP|tx_data|mem[4][8]~q  & ( ((!\A_SPW_TOP|tx_data|wr_ptr [5] & ((\A_SPW_TOP|tx_data|mem[0][8]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|mem[32][8]~q ))) 
// # (\A_SPW_TOP|tx_data|wr_ptr [2]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[36][8]~q  & ( \A_SPW_TOP|tx_data|mem[4][8]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & ((!\A_SPW_TOP|tx_data|wr_ptr [5] & ((\A_SPW_TOP|tx_data|mem[0][8]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr 
// [5] & (\A_SPW_TOP|tx_data|mem[32][8]~q )))) # (\A_SPW_TOP|tx_data|wr_ptr [2] & (((!\A_SPW_TOP|tx_data|wr_ptr [5])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[36][8]~q  & ( !\A_SPW_TOP|tx_data|mem[4][8]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & 
// ((!\A_SPW_TOP|tx_data|wr_ptr [5] & ((\A_SPW_TOP|tx_data|mem[0][8]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|mem[32][8]~q )))) # (\A_SPW_TOP|tx_data|wr_ptr [2] & (((\A_SPW_TOP|tx_data|wr_ptr [5])))) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|mem[36][8]~q  & ( !\A_SPW_TOP|tx_data|mem[4][8]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & ((!\A_SPW_TOP|tx_data|wr_ptr [5] & ((\A_SPW_TOP|tx_data|mem[0][8]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|mem[32][8]~q )))) ) 
// ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datab(!\A_SPW_TOP|tx_data|mem[32][8]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[0][8]~q ),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datae(!\A_SPW_TOP|tx_data|mem[36][8]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[4][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux0~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux0~0 .lut_mask = 64'h0A220A775F225F77;
defparam \A_SPW_TOP|tx_data|Mux0~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y13_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux0~4 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux0~4_combout  = ( \A_SPW_TOP|tx_data|Mux0~0_combout  & ( \A_SPW_TOP|tx_data|wr_ptr [4] & ( (!\A_SPW_TOP|tx_data|wr_ptr [3] & (\A_SPW_TOP|tx_data|Mux0~2_combout )) # (\A_SPW_TOP|tx_data|wr_ptr [3] & ((\A_SPW_TOP|tx_data|Mux0~3_combout 
// ))) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux0~0_combout  & ( \A_SPW_TOP|tx_data|wr_ptr [4] & ( (!\A_SPW_TOP|tx_data|wr_ptr [3] & (\A_SPW_TOP|tx_data|Mux0~2_combout )) # (\A_SPW_TOP|tx_data|wr_ptr [3] & ((\A_SPW_TOP|tx_data|Mux0~3_combout ))) ) ) ) # ( 
// \A_SPW_TOP|tx_data|Mux0~0_combout  & ( !\A_SPW_TOP|tx_data|wr_ptr [4] & ( (!\A_SPW_TOP|tx_data|wr_ptr [3]) # (\A_SPW_TOP|tx_data|Mux0~1_combout ) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux0~0_combout  & ( !\A_SPW_TOP|tx_data|wr_ptr [4] & ( 
// (\A_SPW_TOP|tx_data|Mux0~1_combout  & \A_SPW_TOP|tx_data|wr_ptr [3]) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux0~2_combout ),
        .datab(!\A_SPW_TOP|tx_data|Mux0~3_combout ),
        .datac(!\A_SPW_TOP|tx_data|Mux0~1_combout ),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datae(!\A_SPW_TOP|tx_data|Mux0~0_combout ),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux0~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux0~4 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux0~4 .lut_mask = 64'h000FFF0F55335533;
defparam \A_SPW_TOP|tx_data|Mux0~4 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y13_N39
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Decoder0~58 (
// Equation(s):
// \A_SPW_TOP|tx_data|Decoder0~58_combout  = ( !\A_SPW_TOP|tx_data|wr_ptr [5] & ( \A_SPW_TOP|tx_data|wr_ptr [1] & ( (\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|wr_ptr [4] & (!\A_SPW_TOP|tx_data|wr_ptr [3] & \A_SPW_TOP|tx_data|wr_ptr [0]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Decoder0~58_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Decoder0~58 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Decoder0~58 .lut_mask = 64'h0000000000100000;
defparam \A_SPW_TOP|tx_data|Decoder0~58 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y13_N57
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector212~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector212~0_combout  = ( \A_SPW_TOP|tx_data|Decoder0~58_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q ) # (\A_SPW_TOP|tx_data|state_data_write.01~q ) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .datab(gnd),
        .datac(gnd),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Decoder0~58_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector212~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector212~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector212~0 .lut_mask = 64'h00000000FF55FF55;
defparam \A_SPW_TOP|tx_data|Selector212~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y12_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector212~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector212~1_combout  = ( \u0|write_data_fifo_tx|data_out [8] & ( (!\A_SPW_TOP|tx_data|Selector212~0_combout  & (((\A_SPW_TOP|tx_data|mem[23][8]~q )))) # (\A_SPW_TOP|tx_data|Selector212~0_combout  & 
// (((\A_SPW_TOP|tx_data|Mux0~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q ))) ) ) # ( !\u0|write_data_fifo_tx|data_out [8] & ( (!\A_SPW_TOP|tx_data|Selector212~0_combout  & (((\A_SPW_TOP|tx_data|mem[23][8]~q )))) # 
// (\A_SPW_TOP|tx_data|Selector212~0_combout  & (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux0~20_combout ))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector212~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|mem[23][8]~q ),
        .datae(gnd),
        .dataf(!\u0|write_data_fifo_tx|data_out [8]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector212~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector212~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector212~1 .lut_mask = 64'h02F202F207F707F7;
defparam \A_SPW_TOP|tx_data|Selector212~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y12_N41
dffeas \A_SPW_TOP|tx_data|mem[23][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector212~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[23][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[23][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[23][8] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y14_N33
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Decoder0~42 (
// Equation(s):
// \A_SPW_TOP|tx_data|Decoder0~42_combout  = ( !\A_SPW_TOP|tx_data|wr_ptr [5] & ( \A_SPW_TOP|tx_data|wr_ptr [1] & ( (!\A_SPW_TOP|tx_data|wr_ptr [3] & (!\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|wr_ptr [2] & \A_SPW_TOP|tx_data|wr_ptr [0]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Decoder0~42_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Decoder0~42 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Decoder0~42 .lut_mask = 64'h0000000000080000;
defparam \A_SPW_TOP|tx_data|Decoder0~42 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y14_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector68~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector68~0_combout  = ( \A_SPW_TOP|tx_data|Decoder0~42_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q ) # (\A_SPW_TOP|tx_data|state_data_write.01~q ) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(gnd),
        .datac(gnd),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Decoder0~42_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector68~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector68~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector68~0 .lut_mask = 64'h00000000AAFFAAFF;
defparam \A_SPW_TOP|tx_data|Selector68~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y12_N57
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector68~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector68~1_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector68~0_combout  & ((\A_SPW_TOP|tx_data|mem[7][8]~q ))) # (\A_SPW_TOP|tx_data|Selector68~0_combout  & (\u0|write_data_fifo_tx|data_out 
// [8])) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector68~0_combout  & ((\A_SPW_TOP|tx_data|mem[7][8]~q ))) # (\A_SPW_TOP|tx_data|Selector68~0_combout  & (\A_SPW_TOP|tx_data|Mux0~20_combout )) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [8]),
        .datac(!\A_SPW_TOP|tx_data|mem[7][8]~q ),
        .datad(!\A_SPW_TOP|tx_data|Selector68~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector68~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector68~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector68~1 .lut_mask = 64'h0F550F550F330F33;
defparam \A_SPW_TOP|tx_data|Selector68~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y12_N47
dffeas \A_SPW_TOP|tx_data|mem[7][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector68~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[7][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[7][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[7][8] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y13_N15
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Decoder0~59 (
// Equation(s):
// \A_SPW_TOP|tx_data|Decoder0~59_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [2] & ( \A_SPW_TOP|tx_data|wr_ptr [3] & ( (\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|wr_ptr [4] & !\A_SPW_TOP|tx_data|wr_ptr [5]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Decoder0~59_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Decoder0~59 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Decoder0~59 .lut_mask = 64'h0000000000000100;
defparam \A_SPW_TOP|tx_data|Decoder0~59 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y13_N57
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector284~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector284~0_combout  = ( \A_SPW_TOP|tx_data|Decoder0~59_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q ) # (\A_SPW_TOP|tx_data|state_data_write.01~q ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Decoder0~59_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector284~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector284~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector284~0 .lut_mask = 64'h00000000CFCFCFCF;
defparam \A_SPW_TOP|tx_data|Selector284~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y12_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector284~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector284~1_combout  = ( \A_SPW_TOP|tx_data|mem[31][8]~q  & ( (!\A_SPW_TOP|tx_data|Selector284~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux0~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [8])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[31][8]~q  & ( (\A_SPW_TOP|tx_data|Selector284~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux0~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [8]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .datac(!\u0|write_data_fifo_tx|data_out [8]),
        .datad(!\A_SPW_TOP|tx_data|Selector284~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[31][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector284~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector284~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector284~1 .lut_mask = 64'h00270027FF27FF27;
defparam \A_SPW_TOP|tx_data|Selector284~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y12_N11
dffeas \A_SPW_TOP|tx_data|mem[31][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector284~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[31][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[31][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[31][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y13_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Decoder0~46 (
// Equation(s):
// \A_SPW_TOP|tx_data|Decoder0~46_combout  = ( !\A_SPW_TOP|tx_data|wr_ptr [5] & ( \A_SPW_TOP|tx_data|wr_ptr [1] & ( (\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|wr_ptr [3] & (!\A_SPW_TOP|tx_data|wr_ptr [4] & \A_SPW_TOP|tx_data|wr_ptr [0]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Decoder0~46_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Decoder0~46 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Decoder0~46 .lut_mask = 64'h0000000000100000;
defparam \A_SPW_TOP|tx_data|Decoder0~46 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y13_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector140~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector140~0_combout  = (\A_SPW_TOP|tx_data|Decoder0~46_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q ) # (\A_SPW_TOP|tx_data|state_data_write.01~q )))

        .dataa(gnd),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .datad(!\A_SPW_TOP|tx_data|Decoder0~46_combout ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector140~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector140~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector140~0 .lut_mask = 64'h00CF00CF00CF00CF;
defparam \A_SPW_TOP|tx_data|Selector140~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y12_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector140~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector140~1_combout  = ( \A_SPW_TOP|tx_data|mem[15][8]~q  & ( (!\A_SPW_TOP|tx_data|Selector140~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux0~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [8]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[15][8]~q  & ( (\A_SPW_TOP|tx_data|Selector140~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux0~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [8])))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\u0|write_data_fifo_tx|data_out [8]),
        .datac(!\A_SPW_TOP|tx_data|Selector140~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[15][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector140~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector140~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector140~1 .lut_mask = 64'h010B010BF1FBF1FB;
defparam \A_SPW_TOP|tx_data|Selector140~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y12_N41
dffeas \A_SPW_TOP|tx_data|mem[15][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector140~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[15][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[15][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[15][8] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y12_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux0~17 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux0~17_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [4] & ( \A_SPW_TOP|tx_data|mem[15][8]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [3] & (\A_SPW_TOP|tx_data|mem[23][8]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [3] & ((\A_SPW_TOP|tx_data|mem[31][8]~q ))) ) 
// ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [4] & ( \A_SPW_TOP|tx_data|mem[15][8]~q  & ( (\A_SPW_TOP|tx_data|mem[7][8]~q ) # (\A_SPW_TOP|tx_data|wr_ptr [3]) ) ) ) # ( \A_SPW_TOP|tx_data|wr_ptr [4] & ( !\A_SPW_TOP|tx_data|mem[15][8]~q  & ( 
// (!\A_SPW_TOP|tx_data|wr_ptr [3] & (\A_SPW_TOP|tx_data|mem[23][8]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [3] & ((\A_SPW_TOP|tx_data|mem[31][8]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [4] & ( !\A_SPW_TOP|tx_data|mem[15][8]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr 
// [3] & \A_SPW_TOP|tx_data|mem[7][8]~q ) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datab(!\A_SPW_TOP|tx_data|mem[23][8]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[7][8]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[31][8]~q ),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .dataf(!\A_SPW_TOP|tx_data|mem[15][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux0~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux0~17 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux0~17 .lut_mask = 64'h0A0A22775F5F2277;
defparam \A_SPW_TOP|tx_data|Mux0~17 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y11_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Decoder0~47 (
// Equation(s):
// \A_SPW_TOP|tx_data|Decoder0~47_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [5] & ( \A_SPW_TOP|tx_data|wr_ptr [1] & ( (\A_SPW_TOP|tx_data|wr_ptr [3] & (\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|wr_ptr [2] & !\A_SPW_TOP|tx_data|wr_ptr [4]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Decoder0~47_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Decoder0~47 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Decoder0~47 .lut_mask = 64'h0000000000000100;
defparam \A_SPW_TOP|tx_data|Decoder0~47 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y11_N9
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector428~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector428~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( \A_SPW_TOP|tx_data|state_data_write.01~q  & ( \A_SPW_TOP|tx_data|Decoder0~47_combout  ) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( 
// \A_SPW_TOP|tx_data|state_data_write.01~q  & ( \A_SPW_TOP|tx_data|Decoder0~47_combout  ) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( !\A_SPW_TOP|tx_data|state_data_write.01~q  & ( \A_SPW_TOP|tx_data|Decoder0~47_combout  ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Decoder0~47_combout ),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector428~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector428~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector428~0 .lut_mask = 64'h5555000055555555;
defparam \A_SPW_TOP|tx_data|Selector428~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y12_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector428~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector428~1_combout  = ( \A_SPW_TOP|tx_data|Selector428~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux0~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [8]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector428~0_combout  & ( \A_SPW_TOP|tx_data|mem[47][8]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|mem[47][8]~q ),
        .datad(!\u0|write_data_fifo_tx|data_out [8]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector428~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector428~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector428~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector428~1 .lut_mask = 64'h0F0F0F0F22772277;
defparam \A_SPW_TOP|tx_data|Selector428~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y12_N50
dffeas \A_SPW_TOP|tx_data|mem[47][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector428~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[47][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[47][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[47][8] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y13_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Decoder0~62 (
// Equation(s):
// \A_SPW_TOP|tx_data|Decoder0~62_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [1] & ( \A_SPW_TOP|tx_data|wr_ptr [4] & ( (\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|wr_ptr [0] & !\A_SPW_TOP|tx_data|wr_ptr [3]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Decoder0~62_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Decoder0~62 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Decoder0~62 .lut_mask = 64'h0000000000000100;
defparam \A_SPW_TOP|tx_data|Decoder0~62 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y13_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector500~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector500~0_combout  = ( \A_SPW_TOP|tx_data|Decoder0~62_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q ) # (\A_SPW_TOP|tx_data|state_data_write.01~q ) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Decoder0~62_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector500~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector500~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector500~0 .lut_mask = 64'h00000000F5F5F5F5;
defparam \A_SPW_TOP|tx_data|Selector500~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y12_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector500~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector500~1_combout  = ( \A_SPW_TOP|tx_data|mem[55][8]~q  & ( (!\A_SPW_TOP|tx_data|Selector500~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux0~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [8]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[55][8]~q  & ( (\A_SPW_TOP|tx_data|Selector500~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux0~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [8])))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\u0|write_data_fifo_tx|data_out [8]),
        .datac(!\A_SPW_TOP|tx_data|Selector500~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[55][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector500~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector500~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector500~1 .lut_mask = 64'h010B010BF1FBF1FB;
defparam \A_SPW_TOP|tx_data|Selector500~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y12_N17
dffeas \A_SPW_TOP|tx_data|mem[55][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector500~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[55][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[55][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[55][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y15_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Decoder0~63 (
// Equation(s):
// \A_SPW_TOP|tx_data|Decoder0~63_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [0] & ( \A_SPW_TOP|tx_data|wr_ptr [4] & ( (\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|wr_ptr [3] & (\A_SPW_TOP|tx_data|wr_ptr [2] & \A_SPW_TOP|tx_data|wr_ptr [1]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Decoder0~63_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Decoder0~63 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Decoder0~63 .lut_mask = 64'h0000000000000001;
defparam \A_SPW_TOP|tx_data|Decoder0~63 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y15_N27
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector572~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector572~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.01~q  & ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( \A_SPW_TOP|tx_data|Decoder0~63_combout  ) ) ) # ( \A_SPW_TOP|tx_data|state_data_write.01~q  & ( 
// !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( \A_SPW_TOP|tx_data|Decoder0~63_combout  ) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.01~q  & ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( \A_SPW_TOP|tx_data|Decoder0~63_combout  ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Decoder0~63_combout ),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector572~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector572~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector572~0 .lut_mask = 64'h5555555500005555;
defparam \A_SPW_TOP|tx_data|Selector572~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y12_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector572~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector572~1_combout  = ( \A_SPW_TOP|tx_data|Selector572~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux0~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [8]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector572~0_combout  & ( \A_SPW_TOP|tx_data|mem[63][8]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|mem[63][8]~q ),
        .datad(!\u0|write_data_fifo_tx|data_out [8]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector572~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector572~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector572~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector572~1 .lut_mask = 64'h0F0F0F0F22772277;
defparam \A_SPW_TOP|tx_data|Selector572~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y12_N38
dffeas \A_SPW_TOP|tx_data|mem[63][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector572~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[63][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[63][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[63][8] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y15_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Decoder0~43 (
// Equation(s):
// \A_SPW_TOP|tx_data|Decoder0~43_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [5] & ( \A_SPW_TOP|tx_data|wr_ptr [1] & ( (\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|wr_ptr [0] & (!\A_SPW_TOP|tx_data|wr_ptr [3] & !\A_SPW_TOP|tx_data|wr_ptr [4]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Decoder0~43_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Decoder0~43 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Decoder0~43 .lut_mask = 64'h0000000000001000;
defparam \A_SPW_TOP|tx_data|Decoder0~43 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y15_N57
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector356~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector356~0_combout  = (\A_SPW_TOP|tx_data|Decoder0~43_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q ) # (\A_SPW_TOP|tx_data|state_data_write.01~q )))

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|tx_data|Decoder0~43_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector356~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector356~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector356~0 .lut_mask = 64'h0A0F0A0F0A0F0A0F;
defparam \A_SPW_TOP|tx_data|Selector356~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y12_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector356~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector356~1_combout  = ( \A_SPW_TOP|tx_data|mem[39][8]~q  & ( (!\A_SPW_TOP|tx_data|Selector356~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux0~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [8]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[39][8]~q  & ( (\A_SPW_TOP|tx_data|Selector356~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux0~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [8])))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\u0|write_data_fifo_tx|data_out [8]),
        .datac(!\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .datad(!\A_SPW_TOP|tx_data|Selector356~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[39][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector356~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector356~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector356~1 .lut_mask = 64'h001B001BFF1BFF1B;
defparam \A_SPW_TOP|tx_data|Selector356~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y12_N35
dffeas \A_SPW_TOP|tx_data|mem[39][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector356~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[39][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[39][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[39][8] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y12_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux0~18 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux0~18_combout  = ( \A_SPW_TOP|tx_data|mem[63][8]~q  & ( \A_SPW_TOP|tx_data|mem[39][8]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & (((!\A_SPW_TOP|tx_data|wr_ptr [3])) # (\A_SPW_TOP|tx_data|mem[47][8]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [4] 
// & (((\A_SPW_TOP|tx_data|mem[55][8]~q ) # (\A_SPW_TOP|tx_data|wr_ptr [3])))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[63][8]~q  & ( \A_SPW_TOP|tx_data|mem[39][8]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & (((!\A_SPW_TOP|tx_data|wr_ptr [3])) # 
// (\A_SPW_TOP|tx_data|mem[47][8]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [4] & (((!\A_SPW_TOP|tx_data|wr_ptr [3] & \A_SPW_TOP|tx_data|mem[55][8]~q )))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[63][8]~q  & ( !\A_SPW_TOP|tx_data|mem[39][8]~q  & ( 
// (!\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|mem[47][8]~q  & (\A_SPW_TOP|tx_data|wr_ptr [3]))) # (\A_SPW_TOP|tx_data|wr_ptr [4] & (((\A_SPW_TOP|tx_data|mem[55][8]~q ) # (\A_SPW_TOP|tx_data|wr_ptr [3])))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[63][8]~q 
//  & ( !\A_SPW_TOP|tx_data|mem[39][8]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|mem[47][8]~q  & (\A_SPW_TOP|tx_data|wr_ptr [3]))) # (\A_SPW_TOP|tx_data|wr_ptr [4] & (((!\A_SPW_TOP|tx_data|wr_ptr [3] & \A_SPW_TOP|tx_data|mem[55][8]~q )))) 
// ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datab(!\A_SPW_TOP|tx_data|mem[47][8]~q ),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datad(!\A_SPW_TOP|tx_data|mem[55][8]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[63][8]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[39][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux0~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux0~18 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux0~18 .lut_mask = 64'h02520757A2F2A7F7;
defparam \A_SPW_TOP|tx_data|Mux0~18 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y14_N39
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Decoder0~34 (
// Equation(s):
// \A_SPW_TOP|tx_data|Decoder0~34_combout  = ( !\A_SPW_TOP|tx_data|wr_ptr [5] & ( !\A_SPW_TOP|tx_data|wr_ptr [2] & ( (!\A_SPW_TOP|tx_data|wr_ptr [3] & (\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|wr_ptr [1] & !\A_SPW_TOP|tx_data|wr_ptr [4]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Decoder0~34_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Decoder0~34 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Decoder0~34 .lut_mask = 64'h0200000000000000;
defparam \A_SPW_TOP|tx_data|Decoder0~34 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y14_N51
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector32~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector32~0_combout  = (\A_SPW_TOP|tx_data|Decoder0~34_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q ) # (\A_SPW_TOP|tx_data|state_data_write.01~q )))

        .dataa(gnd),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Decoder0~34_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector32~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector32~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector32~0 .lut_mask = 64'h0C0F0C0F0C0F0C0F;
defparam \A_SPW_TOP|tx_data|Selector32~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y12_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector32~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector32~1_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( \A_SPW_TOP|tx_data|mem[3][8]~q  & ( (!\A_SPW_TOP|tx_data|Selector32~0_combout ) # (\u0|write_data_fifo_tx|data_out [8]) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( \A_SPW_TOP|tx_data|mem[3][8]~q  & ( (!\A_SPW_TOP|tx_data|Selector32~0_combout ) # (\A_SPW_TOP|tx_data|Mux0~20_combout ) ) ) ) # ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( !\A_SPW_TOP|tx_data|mem[3][8]~q  
// & ( (\A_SPW_TOP|tx_data|Selector32~0_combout  & \u0|write_data_fifo_tx|data_out [8]) ) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( !\A_SPW_TOP|tx_data|mem[3][8]~q  & ( (\A_SPW_TOP|tx_data|Mux0~20_combout  & 
// \A_SPW_TOP|tx_data|Selector32~0_combout ) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|Selector32~0_combout ),
        .datac(gnd),
        .datad(!\u0|write_data_fifo_tx|data_out [8]),
        .datae(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[3][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector32~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector32~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector32~1 .lut_mask = 64'h11110033DDDDCCFF;
defparam \A_SPW_TOP|tx_data|Selector32~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y12_N17
dffeas \A_SPW_TOP|tx_data|mem[3][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector32~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[3][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[3][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[3][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y11_N51
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Decoder0~38 (
// Equation(s):
// \A_SPW_TOP|tx_data|Decoder0~38_combout  = ( !\A_SPW_TOP|tx_data|wr_ptr [5] & ( \A_SPW_TOP|tx_data|wr_ptr [1] & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|wr_ptr [3] & (!\A_SPW_TOP|tx_data|wr_ptr [4] & \A_SPW_TOP|tx_data|wr_ptr [0]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Decoder0~38_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Decoder0~38 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Decoder0~38 .lut_mask = 64'h0000000000200000;
defparam \A_SPW_TOP|tx_data|Decoder0~38 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y11_N15
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector104~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector104~0_combout  = ( \A_SPW_TOP|tx_data|Decoder0~38_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q ) # (\A_SPW_TOP|tx_data|state_data_write.01~q ) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Decoder0~38_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector104~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector104~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector104~0 .lut_mask = 64'h00000000BBBBBBBB;
defparam \A_SPW_TOP|tx_data|Selector104~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y14_N45
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector104~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector104~1_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector104~0_combout  & (\A_SPW_TOP|tx_data|mem[11][8]~q )) # (\A_SPW_TOP|tx_data|Selector104~0_combout  & ((\u0|write_data_fifo_tx|data_out 
// [8]))) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector104~0_combout  & (\A_SPW_TOP|tx_data|mem[11][8]~q )) # (\A_SPW_TOP|tx_data|Selector104~0_combout  & ((\A_SPW_TOP|tx_data|Mux0~20_combout ))) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[11][8]~q ),
        .datab(!\A_SPW_TOP|tx_data|Selector104~0_combout ),
        .datac(!\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [8]),
        .datae(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector104~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector104~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector104~1 .lut_mask = 64'h4747447747474477;
defparam \A_SPW_TOP|tx_data|Selector104~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y14_N53
dffeas \A_SPW_TOP|tx_data|mem[11][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector104~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[11][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[11][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[11][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y15_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Decoder0~56 (
// Equation(s):
// \A_SPW_TOP|tx_data|Decoder0~56_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [0] & ( \A_SPW_TOP|tx_data|wr_ptr [4] & ( (!\A_SPW_TOP|tx_data|wr_ptr [5] & (!\A_SPW_TOP|tx_data|wr_ptr [3] & (!\A_SPW_TOP|tx_data|wr_ptr [2] & \A_SPW_TOP|tx_data|wr_ptr [1]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Decoder0~56_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Decoder0~56 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Decoder0~56 .lut_mask = 64'h0000000000000080;
defparam \A_SPW_TOP|tx_data|Decoder0~56 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y15_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector176~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector176~0_combout  = ( \A_SPW_TOP|tx_data|Decoder0~56_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q ) # (\A_SPW_TOP|tx_data|state_data_write.01~q ) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Decoder0~56_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector176~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector176~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector176~0 .lut_mask = 64'h00000000F5F5F5F5;
defparam \A_SPW_TOP|tx_data|Selector176~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y12_N57
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector176~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector176~1_combout  = ( \A_SPW_TOP|tx_data|Selector176~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux0~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [8]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector176~0_combout  & ( \A_SPW_TOP|tx_data|mem[19][8]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .datac(!\u0|write_data_fifo_tx|data_out [8]),
        .datad(!\A_SPW_TOP|tx_data|mem[19][8]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector176~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector176~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector176~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector176~1 .lut_mask = 64'h00FF00FF27272727;
defparam \A_SPW_TOP|tx_data|Selector176~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y12_N20
dffeas \A_SPW_TOP|tx_data|mem[19][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector176~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[19][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[19][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[19][8] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y13_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Decoder0~57 (
// Equation(s):
// \A_SPW_TOP|tx_data|Decoder0~57_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [3] & ( \A_SPW_TOP|tx_data|wr_ptr [0] & ( (!\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|wr_ptr [1] & (!\A_SPW_TOP|tx_data|wr_ptr [2] & \A_SPW_TOP|tx_data|wr_ptr [4]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Decoder0~57_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Decoder0~57 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Decoder0~57 .lut_mask = 64'h0000000000000020;
defparam \A_SPW_TOP|tx_data|Decoder0~57 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y13_N45
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector248~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector248~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.01~q  & ( \A_SPW_TOP|tx_data|Decoder0~57_combout  ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.01~q  & ( \A_SPW_TOP|tx_data|Decoder0~57_combout  & ( 
// !\A_SPW_TOP|tx_data|state_data_write.00~q  ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .dataf(!\A_SPW_TOP|tx_data|Decoder0~57_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector248~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector248~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector248~0 .lut_mask = 64'h00000000F0F0FFFF;
defparam \A_SPW_TOP|tx_data|Selector248~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y12_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector248~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector248~1_combout  = ( \A_SPW_TOP|tx_data|Selector248~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux0~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [8]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector248~0_combout  & ( \A_SPW_TOP|tx_data|mem[27][8]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|mem[27][8]~q ),
        .datad(!\u0|write_data_fifo_tx|data_out [8]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector248~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector248~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector248~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector248~1 .lut_mask = 64'h0F0F0F0F22772277;
defparam \A_SPW_TOP|tx_data|Selector248~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y12_N35
dffeas \A_SPW_TOP|tx_data|mem[27][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector248~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[27][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[27][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[27][8] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y12_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux0~15 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux0~15_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [4] & ( \A_SPW_TOP|tx_data|wr_ptr [3] & ( \A_SPW_TOP|tx_data|mem[27][8]~q  ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [4] & ( \A_SPW_TOP|tx_data|wr_ptr [3] & ( \A_SPW_TOP|tx_data|mem[11][8]~q  ) 
// ) ) # ( \A_SPW_TOP|tx_data|wr_ptr [4] & ( !\A_SPW_TOP|tx_data|wr_ptr [3] & ( \A_SPW_TOP|tx_data|mem[19][8]~q  ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [4] & ( !\A_SPW_TOP|tx_data|wr_ptr [3] & ( \A_SPW_TOP|tx_data|mem[3][8]~q  ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[3][8]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[11][8]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[19][8]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[27][8]~q ),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux0~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux0~15 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux0~15 .lut_mask = 64'h55550F0F333300FF;
defparam \A_SPW_TOP|tx_data|Mux0~15 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y14_N39
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Decoder0~39 (
// Equation(s):
// \A_SPW_TOP|tx_data|Decoder0~39_combout  = ( !\A_SPW_TOP|tx_data|wr_ptr [4] & ( \A_SPW_TOP|tx_data|wr_ptr [3] & ( (\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|wr_ptr [5] & (!\A_SPW_TOP|tx_data|wr_ptr [2] & \A_SPW_TOP|tx_data|wr_ptr [0]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Decoder0~39_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Decoder0~39 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Decoder0~39 .lut_mask = 64'h0000000000100000;
defparam \A_SPW_TOP|tx_data|Decoder0~39 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y14_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector392~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector392~0_combout  = ( \A_SPW_TOP|tx_data|Decoder0~39_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q ) # (\A_SPW_TOP|tx_data|state_data_write.01~q ) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Decoder0~39_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector392~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector392~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector392~0 .lut_mask = 64'h00000000F5F5F5F5;
defparam \A_SPW_TOP|tx_data|Selector392~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y12_N45
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector392~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector392~1_combout  = ( \A_SPW_TOP|tx_data|Selector392~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux0~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [8]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector392~0_combout  & ( \A_SPW_TOP|tx_data|mem[43][8]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .datac(!\u0|write_data_fifo_tx|data_out [8]),
        .datad(!\A_SPW_TOP|tx_data|mem[43][8]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector392~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector392~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector392~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector392~1 .lut_mask = 64'h00FF00FF27272727;
defparam \A_SPW_TOP|tx_data|Selector392~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y12_N56
dffeas \A_SPW_TOP|tx_data|mem[43][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector392~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[43][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[43][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[43][8] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y14_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Decoder0~35 (
// Equation(s):
// \A_SPW_TOP|tx_data|Decoder0~35_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [1] & ( !\A_SPW_TOP|tx_data|wr_ptr [4] & ( (\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|wr_ptr [5] & (!\A_SPW_TOP|tx_data|wr_ptr [3] & !\A_SPW_TOP|tx_data|wr_ptr [2]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Decoder0~35_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Decoder0~35 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Decoder0~35 .lut_mask = 64'h0000100000000000;
defparam \A_SPW_TOP|tx_data|Decoder0~35 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y14_N27
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector320~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector320~0_combout  = ( \A_SPW_TOP|tx_data|Decoder0~35_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q ) # (\A_SPW_TOP|tx_data|state_data_write.01~q ) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(gnd),
        .datac(gnd),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Decoder0~35_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector320~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector320~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector320~0 .lut_mask = 64'h00000000AAFFAAFF;
defparam \A_SPW_TOP|tx_data|Selector320~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y12_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector320~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector320~1_combout  = ( \u0|write_data_fifo_tx|data_out [8] & ( (!\A_SPW_TOP|tx_data|Selector320~0_combout  & (((\A_SPW_TOP|tx_data|mem[35][8]~q )))) # (\A_SPW_TOP|tx_data|Selector320~0_combout  & 
// (((\A_SPW_TOP|tx_data|state_data_write.00~q )) # (\A_SPW_TOP|tx_data|Mux0~20_combout ))) ) ) # ( !\u0|write_data_fifo_tx|data_out [8] & ( (!\A_SPW_TOP|tx_data|Selector320~0_combout  & (((\A_SPW_TOP|tx_data|mem[35][8]~q )))) # 
// (\A_SPW_TOP|tx_data|Selector320~0_combout  & (\A_SPW_TOP|tx_data|Mux0~20_combout  & (!\A_SPW_TOP|tx_data|state_data_write.00~q ))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Selector320~0_combout ),
        .datab(!\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[35][8]~q ),
        .datae(gnd),
        .dataf(!\u0|write_data_fifo_tx|data_out [8]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector320~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector320~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector320~1 .lut_mask = 64'h10BA10BA15BF15BF;
defparam \A_SPW_TOP|tx_data|Selector320~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y12_N14
dffeas \A_SPW_TOP|tx_data|mem[35][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector320~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[35][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[35][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[35][8] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y14_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Decoder0~60 (
// Equation(s):
// \A_SPW_TOP|tx_data|Decoder0~60_combout  = ( !\A_SPW_TOP|tx_data|wr_ptr [3] & ( \A_SPW_TOP|tx_data|wr_ptr [4] & ( (\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|wr_ptr [0] & !\A_SPW_TOP|tx_data|wr_ptr [2]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Decoder0~60_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Decoder0~60 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Decoder0~60 .lut_mask = 64'h0000000001000000;
defparam \A_SPW_TOP|tx_data|Decoder0~60 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y14_N57
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector464~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector464~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (\A_SPW_TOP|tx_data|state_data_write.01~q  & \A_SPW_TOP|tx_data|Decoder0~60_combout ) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( 
// \A_SPW_TOP|tx_data|Decoder0~60_combout  ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .datab(gnd),
        .datac(gnd),
        .datad(!\A_SPW_TOP|tx_data|Decoder0~60_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector464~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector464~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector464~0 .lut_mask = 64'h00FF00FF00550055;
defparam \A_SPW_TOP|tx_data|Selector464~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y12_N27
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector464~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector464~1_combout  = ( \A_SPW_TOP|tx_data|Selector464~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux0~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [8]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector464~0_combout  & ( \A_SPW_TOP|tx_data|mem[51][8]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .datac(!\u0|write_data_fifo_tx|data_out [8]),
        .datad(!\A_SPW_TOP|tx_data|mem[51][8]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector464~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector464~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector464~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector464~1 .lut_mask = 64'h00FF00FF27272727;
defparam \A_SPW_TOP|tx_data|Selector464~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y12_N23
dffeas \A_SPW_TOP|tx_data|mem[51][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector464~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[51][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[51][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[51][8] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y10_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Decoder0~61 (
// Equation(s):
// \A_SPW_TOP|tx_data|Decoder0~61_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [0] & ( !\A_SPW_TOP|tx_data|wr_ptr [2] & ( (\A_SPW_TOP|tx_data|wr_ptr [3] & (\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|wr_ptr [1] & \A_SPW_TOP|tx_data|wr_ptr [4]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Decoder0~61_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Decoder0~61 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Decoder0~61 .lut_mask = 64'h0000000100000000;
defparam \A_SPW_TOP|tx_data|Decoder0~61 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y10_N15
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector536~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector536~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.01~q  & ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( \A_SPW_TOP|tx_data|Decoder0~61_combout  ) ) ) # ( \A_SPW_TOP|tx_data|state_data_write.01~q  & ( 
// !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( \A_SPW_TOP|tx_data|Decoder0~61_combout  ) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.01~q  & ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( \A_SPW_TOP|tx_data|Decoder0~61_combout  ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Decoder0~61_combout ),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector536~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector536~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector536~0 .lut_mask = 64'h5555555500005555;
defparam \A_SPW_TOP|tx_data|Selector536~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y12_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector536~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector536~1_combout  = ( \A_SPW_TOP|tx_data|Selector536~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux0~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [8]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector536~0_combout  & ( \A_SPW_TOP|tx_data|mem[59][8]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .datac(!\u0|write_data_fifo_tx|data_out [8]),
        .datad(!\A_SPW_TOP|tx_data|mem[59][8]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector536~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector536~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector536~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector536~1 .lut_mask = 64'h00FF00FF27272727;
defparam \A_SPW_TOP|tx_data|Selector536~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y12_N59
dffeas \A_SPW_TOP|tx_data|mem[59][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector536~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[59][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[59][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[59][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y12_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux0~16 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux0~16_combout  = ( \A_SPW_TOP|tx_data|mem[59][8]~q  & ( \A_SPW_TOP|tx_data|wr_ptr [3] & ( (\A_SPW_TOP|tx_data|wr_ptr [4]) # (\A_SPW_TOP|tx_data|mem[43][8]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[59][8]~q  & ( \A_SPW_TOP|tx_data|wr_ptr 
// [3] & ( (\A_SPW_TOP|tx_data|mem[43][8]~q  & !\A_SPW_TOP|tx_data|wr_ptr [4]) ) ) ) # ( \A_SPW_TOP|tx_data|mem[59][8]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [3] & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|mem[35][8]~q )) # 
// (\A_SPW_TOP|tx_data|wr_ptr [4] & ((\A_SPW_TOP|tx_data|mem[51][8]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[59][8]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [3] & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|mem[35][8]~q )) # (\A_SPW_TOP|tx_data|wr_ptr 
// [4] & ((\A_SPW_TOP|tx_data|mem[51][8]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[43][8]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[35][8]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[51][8]~q ),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datae(!\A_SPW_TOP|tx_data|mem[59][8]~q ),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux0~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux0~16 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux0~16 .lut_mask = 64'h330F330F550055FF;
defparam \A_SPW_TOP|tx_data|Mux0~16 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y12_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux0~19 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux0~19_combout  = ( \A_SPW_TOP|tx_data|Mux0~16_combout  & ( \A_SPW_TOP|tx_data|wr_ptr [5] & ( (!\A_SPW_TOP|tx_data|wr_ptr [2]) # (\A_SPW_TOP|tx_data|Mux0~18_combout ) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux0~16_combout  & ( 
// \A_SPW_TOP|tx_data|wr_ptr [5] & ( (\A_SPW_TOP|tx_data|Mux0~18_combout  & \A_SPW_TOP|tx_data|wr_ptr [2]) ) ) ) # ( \A_SPW_TOP|tx_data|Mux0~16_combout  & ( !\A_SPW_TOP|tx_data|wr_ptr [5] & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & 
// ((\A_SPW_TOP|tx_data|Mux0~15_combout ))) # (\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|Mux0~17_combout )) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux0~16_combout  & ( !\A_SPW_TOP|tx_data|wr_ptr [5] & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & 
// ((\A_SPW_TOP|tx_data|Mux0~15_combout ))) # (\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|Mux0~17_combout )) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux0~17_combout ),
        .datab(!\A_SPW_TOP|tx_data|Mux0~18_combout ),
        .datac(!\A_SPW_TOP|tx_data|Mux0~15_combout ),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datae(!\A_SPW_TOP|tx_data|Mux0~16_combout ),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux0~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux0~19 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux0~19 .lut_mask = 64'h0F550F550033FF33;
defparam \A_SPW_TOP|tx_data|Mux0~19 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y15_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Decoder0~27 (
// Equation(s):
// \A_SPW_TOP|tx_data|Decoder0~27_combout  = ( !\A_SPW_TOP|tx_data|wr_ptr [0] & ( \A_SPW_TOP|tx_data|wr_ptr [1] & ( (!\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|wr_ptr [2] & \A_SPW_TOP|tx_data|wr_ptr [3]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Decoder0~27_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Decoder0~27 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Decoder0~27 .lut_mask = 64'h0000000000020000;
defparam \A_SPW_TOP|tx_data|Decoder0~27 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y15_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector275~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector275~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.01~q  & ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( \A_SPW_TOP|tx_data|Decoder0~27_combout  ) ) ) # ( \A_SPW_TOP|tx_data|state_data_write.01~q  & ( 
// !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( \A_SPW_TOP|tx_data|Decoder0~27_combout  ) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.01~q  & ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( \A_SPW_TOP|tx_data|Decoder0~27_combout  ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|tx_data|Decoder0~27_combout ),
        .datac(gnd),
        .datad(gnd),
        .datae(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector275~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector275~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector275~0 .lut_mask = 64'h3333333300003333;
defparam \A_SPW_TOP|tx_data|Selector275~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y13_N57
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector275~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector275~1_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector275~0_combout  & ((\A_SPW_TOP|tx_data|mem[30][8]~q ))) # (\A_SPW_TOP|tx_data|Selector275~0_combout  & (\u0|write_data_fifo_tx|data_out 
// [8])) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector275~0_combout  & ((\A_SPW_TOP|tx_data|mem[30][8]~q ))) # (\A_SPW_TOP|tx_data|Selector275~0_combout  & (\A_SPW_TOP|tx_data|Mux0~20_combout )) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [8]),
        .datab(!\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|mem[30][8]~q ),
        .datad(!\A_SPW_TOP|tx_data|Selector275~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector275~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector275~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector275~1 .lut_mask = 64'h0F330F330F550F55;
defparam \A_SPW_TOP|tx_data|Selector275~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X45_Y13_N29
dffeas \A_SPW_TOP|tx_data|mem[30][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector275~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[30][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[30][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[30][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y11_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Decoder0~26 (
// Equation(s):
// \A_SPW_TOP|tx_data|Decoder0~26_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [4] & ( !\A_SPW_TOP|tx_data|wr_ptr [5] & ( (\A_SPW_TOP|tx_data|wr_ptr [2] & (!\A_SPW_TOP|tx_data|wr_ptr [3] & (\A_SPW_TOP|tx_data|wr_ptr [1] & !\A_SPW_TOP|tx_data|wr_ptr [0]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Decoder0~26_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Decoder0~26 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Decoder0~26 .lut_mask = 64'h0000040000000000;
defparam \A_SPW_TOP|tx_data|Decoder0~26 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y11_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector203~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector203~0_combout  = ( \A_SPW_TOP|tx_data|Decoder0~26_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q ) # (\A_SPW_TOP|tx_data|state_data_write.01~q ) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Decoder0~26_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector203~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector203~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector203~0 .lut_mask = 64'h00000000BBBBBBBB;
defparam \A_SPW_TOP|tx_data|Selector203~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y13_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector203~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector203~1_combout  = ( \A_SPW_TOP|tx_data|Selector203~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux0~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [8]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector203~0_combout  & ( \A_SPW_TOP|tx_data|mem[22][8]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[22][8]~q ),
        .datad(!\u0|write_data_fifo_tx|data_out [8]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector203~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector203~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector203~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector203~1 .lut_mask = 64'h0F0F0F0F44774477;
defparam \A_SPW_TOP|tx_data|Selector203~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y13_N59
dffeas \A_SPW_TOP|tx_data|mem[22][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector203~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[22][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[22][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[22][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y9_N45
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Decoder0~14 (
// Equation(s):
// \A_SPW_TOP|tx_data|Decoder0~14_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [1] & ( !\A_SPW_TOP|tx_data|wr_ptr [0] & ( (\A_SPW_TOP|tx_data|wr_ptr [2] & (!\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|wr_ptr [3] & !\A_SPW_TOP|tx_data|wr_ptr [4]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Decoder0~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Decoder0~14 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Decoder0~14 .lut_mask = 64'h0000040000000000;
defparam \A_SPW_TOP|tx_data|Decoder0~14 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y9_N9
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector131~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector131~0_combout  = ( \A_SPW_TOP|tx_data|Decoder0~14_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q ) # (\A_SPW_TOP|tx_data|state_data_write.01~q ) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Decoder0~14_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector131~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector131~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector131~0 .lut_mask = 64'h00000000AFAFAFAF;
defparam \A_SPW_TOP|tx_data|Selector131~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y13_N39
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector131~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector131~1_combout  = ( \A_SPW_TOP|tx_data|mem[14][8]~q  & ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector131~0_combout ) # (\u0|write_data_fifo_tx|data_out [8]) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|mem[14][8]~q  & ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (\A_SPW_TOP|tx_data|Selector131~0_combout  & \u0|write_data_fifo_tx|data_out [8]) ) ) ) # ( \A_SPW_TOP|tx_data|mem[14][8]~q  & ( !\A_SPW_TOP|tx_data|state_data_write.00~q  
// & ( (!\A_SPW_TOP|tx_data|Selector131~0_combout ) # (\A_SPW_TOP|tx_data|Mux0~20_combout ) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[14][8]~q  & ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( (\A_SPW_TOP|tx_data|Selector131~0_combout  & 
// \A_SPW_TOP|tx_data|Mux0~20_combout ) ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|tx_data|Selector131~0_combout ),
        .datac(!\u0|write_data_fifo_tx|data_out [8]),
        .datad(!\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .datae(!\A_SPW_TOP|tx_data|mem[14][8]~q ),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector131~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector131~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector131~1 .lut_mask = 64'h0033CCFF0303CFCF;
defparam \A_SPW_TOP|tx_data|Selector131~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y13_N29
dffeas \A_SPW_TOP|tx_data|mem[14][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector131~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[14][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[14][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[14][8] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y14_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Decoder0~10 (
// Equation(s):
// \A_SPW_TOP|tx_data|Decoder0~10_combout  = ( !\A_SPW_TOP|tx_data|wr_ptr [5] & ( !\A_SPW_TOP|tx_data|wr_ptr [3] & ( (\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|wr_ptr [1] & (!\A_SPW_TOP|tx_data|wr_ptr [0] & !\A_SPW_TOP|tx_data|wr_ptr [4]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Decoder0~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Decoder0~10 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Decoder0~10 .lut_mask = 64'h1000000000000000;
defparam \A_SPW_TOP|tx_data|Decoder0~10 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y14_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector59~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector59~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.01~q  & ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( \A_SPW_TOP|tx_data|Decoder0~10_combout  ) ) ) # ( \A_SPW_TOP|tx_data|state_data_write.01~q  & ( 
// !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( \A_SPW_TOP|tx_data|Decoder0~10_combout  ) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.01~q  & ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( \A_SPW_TOP|tx_data|Decoder0~10_combout  ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|tx_data|Decoder0~10_combout ),
        .datac(gnd),
        .datad(gnd),
        .datae(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector59~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector59~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector59~0 .lut_mask = 64'h3333333300003333;
defparam \A_SPW_TOP|tx_data|Selector59~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y13_N33
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector59~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector59~1_combout  = ( \A_SPW_TOP|tx_data|Selector59~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux0~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out 
// [8]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector59~0_combout  & ( \A_SPW_TOP|tx_data|mem[6][8]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[6][8]~q ),
        .datad(!\u0|write_data_fifo_tx|data_out [8]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector59~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector59~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector59~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector59~1 .lut_mask = 64'h0F0F0F0F44774477;
defparam \A_SPW_TOP|tx_data|Selector59~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y13_N23
dffeas \A_SPW_TOP|tx_data|mem[6][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector59~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[6][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[6][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[6][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y13_N15
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux0~7 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux0~7_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [4] & ( \A_SPW_TOP|tx_data|wr_ptr [3] & ( \A_SPW_TOP|tx_data|mem[30][8]~q  ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [4] & ( \A_SPW_TOP|tx_data|wr_ptr [3] & ( \A_SPW_TOP|tx_data|mem[14][8]~q  ) ) 
// ) # ( \A_SPW_TOP|tx_data|wr_ptr [4] & ( !\A_SPW_TOP|tx_data|wr_ptr [3] & ( \A_SPW_TOP|tx_data|mem[22][8]~q  ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [4] & ( !\A_SPW_TOP|tx_data|wr_ptr [3] & ( \A_SPW_TOP|tx_data|mem[6][8]~q  ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[30][8]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[22][8]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[14][8]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[6][8]~q ),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux0~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux0~7 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux0~7 .lut_mask = 64'h00FF33330F0F5555;
defparam \A_SPW_TOP|tx_data|Mux0~7 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y15_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Decoder0~24 (
// Equation(s):
// \A_SPW_TOP|tx_data|Decoder0~24_combout  = ( !\A_SPW_TOP|tx_data|wr_ptr [0] & ( \A_SPW_TOP|tx_data|wr_ptr [1] & ( (!\A_SPW_TOP|tx_data|wr_ptr [5] & (!\A_SPW_TOP|tx_data|wr_ptr [3] & (!\A_SPW_TOP|tx_data|wr_ptr [2] & \A_SPW_TOP|tx_data|wr_ptr [4]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Decoder0~24_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Decoder0~24 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Decoder0~24 .lut_mask = 64'h0000000000800000;
defparam \A_SPW_TOP|tx_data|Decoder0~24 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y15_N57
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector167~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector167~0_combout  = (\A_SPW_TOP|tx_data|Decoder0~24_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q ) # (\A_SPW_TOP|tx_data|state_data_write.01~q )))

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .datac(gnd),
        .datad(!\A_SPW_TOP|tx_data|Decoder0~24_combout ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector167~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector167~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector167~0 .lut_mask = 64'h00BB00BB00BB00BB;
defparam \A_SPW_TOP|tx_data|Selector167~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y13_N15
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector167~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector167~1_combout  = ( \A_SPW_TOP|tx_data|Selector167~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux0~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [8]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector167~0_combout  & ( \A_SPW_TOP|tx_data|mem[18][8]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[18][8]~q ),
        .datad(!\u0|write_data_fifo_tx|data_out [8]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector167~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector167~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector167~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector167~1 .lut_mask = 64'h0F0F0F0F44774477;
defparam \A_SPW_TOP|tx_data|Selector167~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y13_N23
dffeas \A_SPW_TOP|tx_data|mem[18][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector167~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[18][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[18][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[18][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y15_N9
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Decoder0~2 (
// Equation(s):
// \A_SPW_TOP|tx_data|Decoder0~2_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [1] & ( !\A_SPW_TOP|tx_data|wr_ptr [0] & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & (!\A_SPW_TOP|tx_data|wr_ptr [4] & (!\A_SPW_TOP|tx_data|wr_ptr [3] & !\A_SPW_TOP|tx_data|wr_ptr [5]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Decoder0~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Decoder0~2 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Decoder0~2 .lut_mask = 64'h0000800000000000;
defparam \A_SPW_TOP|tx_data|Decoder0~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y15_N21
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector23~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector23~0_combout  = ( \A_SPW_TOP|tx_data|Decoder0~2_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q ) # (\A_SPW_TOP|tx_data|state_data_write.01~q ) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .datab(gnd),
        .datac(gnd),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Decoder0~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector23~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector23~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector23~0 .lut_mask = 64'h00000000FF55FF55;
defparam \A_SPW_TOP|tx_data|Selector23~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y13_N45
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector23~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector23~1_combout  = ( \A_SPW_TOP|tx_data|Selector23~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux0~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out 
// [8]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector23~0_combout  & ( \A_SPW_TOP|tx_data|mem[2][8]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\u0|write_data_fifo_tx|data_out [8]),
        .datad(!\A_SPW_TOP|tx_data|mem[2][8]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector23~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector23~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector23~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector23~1 .lut_mask = 64'h00FF00FF47474747;
defparam \A_SPW_TOP|tx_data|Selector23~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X45_Y13_N23
dffeas \A_SPW_TOP|tx_data|mem[2][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector23~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[2][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[2][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[2][8] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y10_N21
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Decoder0~25 (
// Equation(s):
// \A_SPW_TOP|tx_data|Decoder0~25_combout  = ( !\A_SPW_TOP|tx_data|wr_ptr [5] & ( \A_SPW_TOP|tx_data|wr_ptr [3] & ( (\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|wr_ptr [4] & (!\A_SPW_TOP|tx_data|wr_ptr [2] & !\A_SPW_TOP|tx_data|wr_ptr [0]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Decoder0~25_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Decoder0~25 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Decoder0~25 .lut_mask = 64'h0000000010000000;
defparam \A_SPW_TOP|tx_data|Decoder0~25 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y10_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector239~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector239~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (\A_SPW_TOP|tx_data|state_data_write.01~q  & \A_SPW_TOP|tx_data|Decoder0~25_combout ) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( 
// \A_SPW_TOP|tx_data|Decoder0~25_combout  ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|tx_data|Decoder0~25_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector239~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector239~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector239~0 .lut_mask = 64'h0F0F0F0F05050505;
defparam \A_SPW_TOP|tx_data|Selector239~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y13_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector239~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector239~1_combout  = ( \A_SPW_TOP|tx_data|mem[26][8]~q  & ( (!\A_SPW_TOP|tx_data|Selector239~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux0~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [8])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[26][8]~q  & ( (\A_SPW_TOP|tx_data|Selector239~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux0~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [8]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\u0|write_data_fifo_tx|data_out [8]),
        .datad(!\A_SPW_TOP|tx_data|Selector239~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[26][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector239~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector239~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector239~1 .lut_mask = 64'h00470047FF47FF47;
defparam \A_SPW_TOP|tx_data|Selector239~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X45_Y13_N11
dffeas \A_SPW_TOP|tx_data|mem[26][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector239~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[26][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[26][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[26][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y15_N51
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Decoder0~6 (
// Equation(s):
// \A_SPW_TOP|tx_data|Decoder0~6_combout  = ( !\A_SPW_TOP|tx_data|wr_ptr [4] & ( \A_SPW_TOP|tx_data|wr_ptr [1] & ( (!\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|wr_ptr [3] & (!\A_SPW_TOP|tx_data|wr_ptr [0] & !\A_SPW_TOP|tx_data|wr_ptr [2]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Decoder0~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Decoder0~6 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Decoder0~6 .lut_mask = 64'h0000000020000000;
defparam \A_SPW_TOP|tx_data|Decoder0~6 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y15_N57
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector95~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector95~0_combout  = ( \A_SPW_TOP|tx_data|Decoder0~6_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q ) # (\A_SPW_TOP|tx_data|state_data_write.01~q ) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .datab(gnd),
        .datac(gnd),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Decoder0~6_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector95~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector95~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector95~0 .lut_mask = 64'h00000000FF55FF55;
defparam \A_SPW_TOP|tx_data|Selector95~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y13_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector95~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector95~1_combout  = ( \A_SPW_TOP|tx_data|Selector95~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux0~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out 
// [8]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector95~0_combout  & ( \A_SPW_TOP|tx_data|mem[10][8]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[10][8]~q ),
        .datad(!\u0|write_data_fifo_tx|data_out [8]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector95~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector95~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector95~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector95~1 .lut_mask = 64'h0F0F0F0F44774477;
defparam \A_SPW_TOP|tx_data|Selector95~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X45_Y13_N59
dffeas \A_SPW_TOP|tx_data|mem[10][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector95~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[10][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[10][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[10][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y13_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux0~5 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux0~5_combout  = ( \A_SPW_TOP|tx_data|mem[10][8]~q  & ( \A_SPW_TOP|tx_data|wr_ptr [3] & ( (!\A_SPW_TOP|tx_data|wr_ptr [4]) # (\A_SPW_TOP|tx_data|mem[26][8]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[10][8]~q  & ( \A_SPW_TOP|tx_data|wr_ptr 
// [3] & ( (\A_SPW_TOP|tx_data|wr_ptr [4] & \A_SPW_TOP|tx_data|mem[26][8]~q ) ) ) ) # ( \A_SPW_TOP|tx_data|mem[10][8]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [3] & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & ((\A_SPW_TOP|tx_data|mem[2][8]~q ))) # 
// (\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|mem[18][8]~q )) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[10][8]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [3] & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & ((\A_SPW_TOP|tx_data|mem[2][8]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [4] 
// & (\A_SPW_TOP|tx_data|mem[18][8]~q )) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[18][8]~q ),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datac(!\A_SPW_TOP|tx_data|mem[2][8]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[26][8]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[10][8]~q ),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux0~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux0~5 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux0~5 .lut_mask = 64'h1D1D1D1D0033CCFF;
defparam \A_SPW_TOP|tx_data|Mux0~5 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y13_N27
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Decoder0~7 (
// Equation(s):
// \A_SPW_TOP|tx_data|Decoder0~7_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [3] & ( !\A_SPW_TOP|tx_data|wr_ptr [0] & ( (\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|wr_ptr [1] & (!\A_SPW_TOP|tx_data|wr_ptr [4] & !\A_SPW_TOP|tx_data|wr_ptr [2]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Decoder0~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Decoder0~7 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Decoder0~7 .lut_mask = 64'h0000100000000000;
defparam \A_SPW_TOP|tx_data|Decoder0~7 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y13_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector383~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector383~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.01~q  & ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( \A_SPW_TOP|tx_data|Decoder0~7_combout  ) ) ) # ( \A_SPW_TOP|tx_data|state_data_write.01~q  & ( 
// !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( \A_SPW_TOP|tx_data|Decoder0~7_combout  ) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.01~q  & ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( \A_SPW_TOP|tx_data|Decoder0~7_combout  ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|tx_data|Decoder0~7_combout ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector383~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector383~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector383~0 .lut_mask = 64'h0F0F0F0F00000F0F;
defparam \A_SPW_TOP|tx_data|Selector383~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y13_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector383~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector383~1_combout  = ( \A_SPW_TOP|tx_data|Selector383~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux0~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\u0|write_data_fifo_tx|data_out [8])) ) ) # ( !\A_SPW_TOP|tx_data|Selector383~0_combout  & ( \A_SPW_TOP|tx_data|mem[42][8]~q  ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [8]),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[42][8]~q ),
        .datad(!\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector383~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector383~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector383~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector383~1 .lut_mask = 64'h0F0F0F0F11DD11DD;
defparam \A_SPW_TOP|tx_data|Selector383~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y13_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|mem[42][8]~feeder (
// Equation(s):
// \A_SPW_TOP|tx_data|mem[42][8]~feeder_combout  = ( \A_SPW_TOP|tx_data|Selector383~1_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector383~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|mem[42][8]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[42][8]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|mem[42][8]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|tx_data|mem[42][8]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y13_N2
dffeas \A_SPW_TOP|tx_data|mem[42][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|tx_data|mem[42][8]~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[42][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[42][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[42][8] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y10_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Decoder0~28 (
// Equation(s):
// \A_SPW_TOP|tx_data|Decoder0~28_combout  = ( !\A_SPW_TOP|tx_data|wr_ptr [3] & ( \A_SPW_TOP|tx_data|wr_ptr [5] & ( (\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|wr_ptr [4] & (!\A_SPW_TOP|tx_data|wr_ptr [0] & !\A_SPW_TOP|tx_data|wr_ptr [2]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Decoder0~28_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Decoder0~28 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Decoder0~28 .lut_mask = 64'h0000000010000000;
defparam \A_SPW_TOP|tx_data|Decoder0~28 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y10_N15
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector455~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector455~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.01~q  & ( \A_SPW_TOP|tx_data|Decoder0~28_combout  ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.01~q  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// \A_SPW_TOP|tx_data|Decoder0~28_combout ) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|tx_data|Decoder0~28_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector455~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector455~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector455~0 .lut_mask = 64'h0A0A0A0A0F0F0F0F;
defparam \A_SPW_TOP|tx_data|Selector455~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y13_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector455~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector455~1_combout  = ( \A_SPW_TOP|tx_data|mem[50][8]~q  & ( (!\A_SPW_TOP|tx_data|Selector455~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux0~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [8])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[50][8]~q  & ( (\A_SPW_TOP|tx_data|Selector455~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux0~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [8]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector455~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [8]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[50][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector455~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector455~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector455~1 .lut_mask = 64'h04070407F4F7F4F7;
defparam \A_SPW_TOP|tx_data|Selector455~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X45_Y13_N50
dffeas \A_SPW_TOP|tx_data|mem[50][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector455~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[50][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[50][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[50][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y11_N9
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Decoder0~29 (
// Equation(s):
// \A_SPW_TOP|tx_data|Decoder0~29_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [1] & ( !\A_SPW_TOP|tx_data|wr_ptr [0] & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|wr_ptr [3] & \A_SPW_TOP|tx_data|wr_ptr [5]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Decoder0~29_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Decoder0~29 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Decoder0~29 .lut_mask = 64'h0000000200000000;
defparam \A_SPW_TOP|tx_data|Decoder0~29 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y11_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector527~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector527~0_combout  = ( \A_SPW_TOP|tx_data|Decoder0~29_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q ) # (\A_SPW_TOP|tx_data|state_data_write.01~q ) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Decoder0~29_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector527~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector527~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector527~0 .lut_mask = 64'h00000000BBBBBBBB;
defparam \A_SPW_TOP|tx_data|Selector527~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y13_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector527~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector527~1_combout  = ( \A_SPW_TOP|tx_data|Selector527~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux0~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [8]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector527~0_combout  & ( \A_SPW_TOP|tx_data|mem[58][8]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\u0|write_data_fifo_tx|data_out [8]),
        .datad(!\A_SPW_TOP|tx_data|mem[58][8]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector527~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector527~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector527~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector527~1 .lut_mask = 64'h00FF00FF47474747;
defparam \A_SPW_TOP|tx_data|Selector527~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X45_Y13_N38
dffeas \A_SPW_TOP|tx_data|mem[58][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector527~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[58][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[58][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[58][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y15_N45
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Decoder0~3 (
// Equation(s):
// \A_SPW_TOP|tx_data|Decoder0~3_combout  = ( !\A_SPW_TOP|tx_data|wr_ptr [2] & ( !\A_SPW_TOP|tx_data|wr_ptr [4] & ( (\A_SPW_TOP|tx_data|wr_ptr [5] & (!\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|wr_ptr [1] & !\A_SPW_TOP|tx_data|wr_ptr [3]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Decoder0~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Decoder0~3 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Decoder0~3 .lut_mask = 64'h0400000000000000;
defparam \A_SPW_TOP|tx_data|Decoder0~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y15_N21
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector311~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector311~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (\A_SPW_TOP|tx_data|state_data_write.01~q  & \A_SPW_TOP|tx_data|Decoder0~3_combout ) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( 
// \A_SPW_TOP|tx_data|Decoder0~3_combout  ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .datac(!\A_SPW_TOP|tx_data|Decoder0~3_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector311~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector311~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector311~0 .lut_mask = 64'h0F0F0F0F03030303;
defparam \A_SPW_TOP|tx_data|Selector311~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y13_N39
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector311~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector311~1_combout  = ( \A_SPW_TOP|tx_data|mem[34][8]~q  & ( (!\A_SPW_TOP|tx_data|Selector311~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux0~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [8]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[34][8]~q  & ( (\A_SPW_TOP|tx_data|Selector311~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux0~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [8])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [8]),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector311~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[34][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector311~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector311~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector311~1 .lut_mask = 64'h010D010DF1FDF1FD;
defparam \A_SPW_TOP|tx_data|Selector311~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y13_N20
dffeas \A_SPW_TOP|tx_data|mem[34][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector311~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[34][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[34][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[34][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y13_N45
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux0~6 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux0~6_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [3] & ( \A_SPW_TOP|tx_data|mem[34][8]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|mem[42][8]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [4] & ((\A_SPW_TOP|tx_data|mem[58][8]~q ))) ) 
// ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [3] & ( \A_SPW_TOP|tx_data|mem[34][8]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [4]) # (\A_SPW_TOP|tx_data|mem[50][8]~q ) ) ) ) # ( \A_SPW_TOP|tx_data|wr_ptr [3] & ( !\A_SPW_TOP|tx_data|mem[34][8]~q  & ( 
// (!\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|mem[42][8]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [4] & ((\A_SPW_TOP|tx_data|mem[58][8]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [3] & ( !\A_SPW_TOP|tx_data|mem[34][8]~q  & ( 
// (\A_SPW_TOP|tx_data|mem[50][8]~q  & \A_SPW_TOP|tx_data|wr_ptr [4]) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[42][8]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[50][8]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[58][8]~q ),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .dataf(!\A_SPW_TOP|tx_data|mem[34][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux0~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux0~6 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux0~6 .lut_mask = 64'h0033550FFF33550F;
defparam \A_SPW_TOP|tx_data|Mux0~6 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y9_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Decoder0~15 (
// Equation(s):
// \A_SPW_TOP|tx_data|Decoder0~15_combout  = ( !\A_SPW_TOP|tx_data|wr_ptr [4] & ( \A_SPW_TOP|tx_data|wr_ptr [5] & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|wr_ptr [1] & \A_SPW_TOP|tx_data|wr_ptr [3]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Decoder0~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Decoder0~15 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Decoder0~15 .lut_mask = 64'h0000000000020000;
defparam \A_SPW_TOP|tx_data|Decoder0~15 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y9_N33
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector419~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector419~0_combout  = ( \A_SPW_TOP|tx_data|Decoder0~15_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q ) # (\A_SPW_TOP|tx_data|state_data_write.01~q ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Decoder0~15_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector419~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector419~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector419~0 .lut_mask = 64'h00000000FF0FFF0F;
defparam \A_SPW_TOP|tx_data|Selector419~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y13_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector419~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector419~1_combout  = ( \A_SPW_TOP|tx_data|mem[46][8]~q  & ( (!\A_SPW_TOP|tx_data|Selector419~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux0~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [8]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[46][8]~q  & ( (\A_SPW_TOP|tx_data|Selector419~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux0~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [8])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [8]),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector419~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[46][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector419~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector419~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector419~1 .lut_mask = 64'h010D010DF1FDF1FD;
defparam \A_SPW_TOP|tx_data|Selector419~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y13_N17
dffeas \A_SPW_TOP|tx_data|mem[46][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector419~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[46][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[46][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[46][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y15_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Decoder0~30 (
// Equation(s):
// \A_SPW_TOP|tx_data|Decoder0~30_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [2] & ( \A_SPW_TOP|tx_data|wr_ptr [4] & ( (\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|wr_ptr [1] & (!\A_SPW_TOP|tx_data|wr_ptr [3] & !\A_SPW_TOP|tx_data|wr_ptr [0]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Decoder0~30_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Decoder0~30 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Decoder0~30 .lut_mask = 64'h0000000000001000;
defparam \A_SPW_TOP|tx_data|Decoder0~30 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y15_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector491~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector491~0_combout  = ( \A_SPW_TOP|tx_data|Decoder0~30_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q ) # (\A_SPW_TOP|tx_data|state_data_write.01~q ) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Decoder0~30_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector491~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector491~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector491~0 .lut_mask = 64'h00000000F5F5F5F5;
defparam \A_SPW_TOP|tx_data|Selector491~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y13_N33
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector491~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector491~1_combout  = ( \A_SPW_TOP|tx_data|Selector491~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux0~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [8]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector491~0_combout  & ( \A_SPW_TOP|tx_data|mem[54][8]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[54][8]~q ),
        .datad(!\u0|write_data_fifo_tx|data_out [8]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector491~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector491~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector491~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector491~1 .lut_mask = 64'h0F0F0F0F44774477;
defparam \A_SPW_TOP|tx_data|Selector491~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X45_Y13_N41
dffeas \A_SPW_TOP|tx_data|mem[54][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector491~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[54][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[54][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[54][8] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y14_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Decoder0~11 (
// Equation(s):
// \A_SPW_TOP|tx_data|Decoder0~11_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [1] & ( !\A_SPW_TOP|tx_data|wr_ptr [4] & ( (\A_SPW_TOP|tx_data|wr_ptr [2] & (!\A_SPW_TOP|tx_data|wr_ptr [0] & (!\A_SPW_TOP|tx_data|wr_ptr [3] & \A_SPW_TOP|tx_data|wr_ptr [5]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Decoder0~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Decoder0~11 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Decoder0~11 .lut_mask = 64'h0000004000000000;
defparam \A_SPW_TOP|tx_data|Decoder0~11 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y14_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector347~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector347~0_combout  = ( \A_SPW_TOP|tx_data|Decoder0~11_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q ) # (\A_SPW_TOP|tx_data|state_data_write.01~q ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Decoder0~11_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector347~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector347~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector347~0 .lut_mask = 64'h00000000CFCFCFCF;
defparam \A_SPW_TOP|tx_data|Selector347~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y13_N27
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector347~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector347~1_combout  = ( \A_SPW_TOP|tx_data|Selector347~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux0~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\u0|write_data_fifo_tx|data_out [8])) ) ) # ( !\A_SPW_TOP|tx_data|Selector347~0_combout  & ( \A_SPW_TOP|tx_data|mem[38][8]~q  ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [8]),
        .datab(!\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|mem[38][8]~q ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector347~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector347~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector347~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector347~1 .lut_mask = 64'h0F0F0F0F33553355;
defparam \A_SPW_TOP|tx_data|Selector347~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y13_N44
dffeas \A_SPW_TOP|tx_data|mem[38][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector347~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[38][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[38][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[38][8] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y10_N27
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Decoder0~31 (
// Equation(s):
// \A_SPW_TOP|tx_data|Decoder0~31_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [2] & ( !\A_SPW_TOP|tx_data|wr_ptr [0] & ( (\A_SPW_TOP|tx_data|wr_ptr [3] & (\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|wr_ptr [4] & \A_SPW_TOP|tx_data|wr_ptr [1]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Decoder0~31_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Decoder0~31 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Decoder0~31 .lut_mask = 64'h0000000100000000;
defparam \A_SPW_TOP|tx_data|Decoder0~31 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y10_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector563~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector563~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (\A_SPW_TOP|tx_data|Decoder0~31_combout  & \A_SPW_TOP|tx_data|state_data_write.01~q ) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( 
// \A_SPW_TOP|tx_data|Decoder0~31_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|tx_data|Decoder0~31_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector563~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector563~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector563~0 .lut_mask = 64'h0F0F0F0F000F000F;
defparam \A_SPW_TOP|tx_data|Selector563~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y13_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector563~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector563~1_combout  = ( \A_SPW_TOP|tx_data|mem[62][8]~q  & ( (!\A_SPW_TOP|tx_data|Selector563~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux0~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [8]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[62][8]~q  & ( (\A_SPW_TOP|tx_data|Selector563~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux0~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [8])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [8]),
        .datab(!\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector563~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[62][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector563~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector563~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector563~1 .lut_mask = 64'h03050305F3F5F3F5;
defparam \A_SPW_TOP|tx_data|Selector563~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y13_N14
dffeas \A_SPW_TOP|tx_data|mem[62][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector563~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[62][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[62][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[62][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y13_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux0~8 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux0~8_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [4] & ( \A_SPW_TOP|tx_data|mem[62][8]~q  & ( (\A_SPW_TOP|tx_data|mem[54][8]~q ) # (\A_SPW_TOP|tx_data|wr_ptr [3]) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [4] & ( \A_SPW_TOP|tx_data|mem[62][8]~q 
//  & ( (!\A_SPW_TOP|tx_data|wr_ptr [3] & ((\A_SPW_TOP|tx_data|mem[38][8]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [3] & (\A_SPW_TOP|tx_data|mem[46][8]~q )) ) ) ) # ( \A_SPW_TOP|tx_data|wr_ptr [4] & ( !\A_SPW_TOP|tx_data|mem[62][8]~q  & ( 
// (!\A_SPW_TOP|tx_data|wr_ptr [3] & \A_SPW_TOP|tx_data|mem[54][8]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [4] & ( !\A_SPW_TOP|tx_data|mem[62][8]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [3] & ((\A_SPW_TOP|tx_data|mem[38][8]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [3] 
// & (\A_SPW_TOP|tx_data|mem[46][8]~q )) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[46][8]~q ),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datac(!\A_SPW_TOP|tx_data|mem[54][8]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[38][8]~q ),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .dataf(!\A_SPW_TOP|tx_data|mem[62][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux0~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux0~8 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux0~8 .lut_mask = 64'h11DD0C0C11DD3F3F;
defparam \A_SPW_TOP|tx_data|Mux0~8 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y13_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux0~9 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux0~9_combout  = ( \A_SPW_TOP|tx_data|Mux0~8_combout  & ( \A_SPW_TOP|tx_data|wr_ptr [2] & ( (\A_SPW_TOP|tx_data|Mux0~7_combout ) # (\A_SPW_TOP|tx_data|wr_ptr [5]) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux0~8_combout  & ( 
// \A_SPW_TOP|tx_data|wr_ptr [2] & ( (!\A_SPW_TOP|tx_data|wr_ptr [5] & \A_SPW_TOP|tx_data|Mux0~7_combout ) ) ) ) # ( \A_SPW_TOP|tx_data|Mux0~8_combout  & ( !\A_SPW_TOP|tx_data|wr_ptr [2] & ( (!\A_SPW_TOP|tx_data|wr_ptr [5] & 
// (\A_SPW_TOP|tx_data|Mux0~5_combout )) # (\A_SPW_TOP|tx_data|wr_ptr [5] & ((\A_SPW_TOP|tx_data|Mux0~6_combout ))) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux0~8_combout  & ( !\A_SPW_TOP|tx_data|wr_ptr [2] & ( (!\A_SPW_TOP|tx_data|wr_ptr [5] & 
// (\A_SPW_TOP|tx_data|Mux0~5_combout )) # (\A_SPW_TOP|tx_data|wr_ptr [5] & ((\A_SPW_TOP|tx_data|Mux0~6_combout ))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datab(!\A_SPW_TOP|tx_data|Mux0~7_combout ),
        .datac(!\A_SPW_TOP|tx_data|Mux0~5_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux0~6_combout ),
        .datae(!\A_SPW_TOP|tx_data|Mux0~8_combout ),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux0~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux0~9 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux0~9 .lut_mask = 64'h0A5F0A5F22227777;
defparam \A_SPW_TOP|tx_data|Mux0~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y11_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Decoder0~37 (
// Equation(s):
// \A_SPW_TOP|tx_data|Decoder0~37_combout  = ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( \A_SPW_TOP|tx_data|wr_ptr [5] & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|wr_ptr [3] & (\A_SPW_TOP|tx_data|wr_ptr [0] & !\A_SPW_TOP|tx_data|wr_ptr [4]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Decoder0~37_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Decoder0~37 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Decoder0~37 .lut_mask = 64'h0000000002000000;
defparam \A_SPW_TOP|tx_data|Decoder0~37 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y11_N33
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector374~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector374~0_combout  = ( \A_SPW_TOP|tx_data|Decoder0~37_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q ) # (\A_SPW_TOP|tx_data|state_data_write.01~q ) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Decoder0~37_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector374~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector374~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector374~0 .lut_mask = 64'h00000000BBBBBBBB;
defparam \A_SPW_TOP|tx_data|Selector374~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y12_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector374~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector374~1_combout  = ( \A_SPW_TOP|tx_data|Selector374~0_combout  & ( \A_SPW_TOP|tx_data|mem[41][8]~q  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux0~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [8])) ) ) ) # ( !\A_SPW_TOP|tx_data|Selector374~0_combout  & ( \A_SPW_TOP|tx_data|mem[41][8]~q  ) ) # ( \A_SPW_TOP|tx_data|Selector374~0_combout  & ( 
// !\A_SPW_TOP|tx_data|mem[41][8]~q  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux0~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [8])) ) ) )

        .dataa(gnd),
        .datab(!\u0|write_data_fifo_tx|data_out [8]),
        .datac(!\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(!\A_SPW_TOP|tx_data|Selector374~0_combout ),
        .dataf(!\A_SPW_TOP|tx_data|mem[41][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector374~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector374~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector374~1 .lut_mask = 64'h00000F33FFFF0F33;
defparam \A_SPW_TOP|tx_data|Selector374~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y12_N32
dffeas \A_SPW_TOP|tx_data|mem[41][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector374~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[41][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[41][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[41][8] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y14_N9
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Decoder0~45 (
// Equation(s):
// \A_SPW_TOP|tx_data|Decoder0~45_combout  = ( !\A_SPW_TOP|tx_data|wr_ptr [4] & ( \A_SPW_TOP|tx_data|wr_ptr [0] & ( (\A_SPW_TOP|tx_data|wr_ptr [3] & (\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|wr_ptr [5] & !\A_SPW_TOP|tx_data|wr_ptr [1]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Decoder0~45_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Decoder0~45 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Decoder0~45 .lut_mask = 64'h0000000001000000;
defparam \A_SPW_TOP|tx_data|Decoder0~45 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y14_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector410~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector410~0_combout  = ( \A_SPW_TOP|tx_data|Decoder0~45_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q ) # (\A_SPW_TOP|tx_data|state_data_write.01~q ) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Decoder0~45_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector410~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector410~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector410~0 .lut_mask = 64'h00000000F5F5F5F5;
defparam \A_SPW_TOP|tx_data|Selector410~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y12_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector410~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector410~1_combout  = ( \u0|write_data_fifo_tx|data_out [8] & ( (!\A_SPW_TOP|tx_data|Selector410~0_combout  & (((\A_SPW_TOP|tx_data|mem[45][8]~q )))) # (\A_SPW_TOP|tx_data|Selector410~0_combout  & 
// (((\A_SPW_TOP|tx_data|Mux0~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q ))) ) ) # ( !\u0|write_data_fifo_tx|data_out [8] & ( (!\A_SPW_TOP|tx_data|Selector410~0_combout  & (((\A_SPW_TOP|tx_data|mem[45][8]~q )))) # 
// (\A_SPW_TOP|tx_data|Selector410~0_combout  & (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux0~20_combout ))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector410~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|mem[45][8]~q ),
        .datae(gnd),
        .dataf(!\u0|write_data_fifo_tx|data_out [8]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector410~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector410~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector410~1 .lut_mask = 64'h02F202F207F707F7;
defparam \A_SPW_TOP|tx_data|Selector410~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y12_N47
dffeas \A_SPW_TOP|tx_data|mem[45][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector410~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[45][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[45][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[45][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y11_N33
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Decoder0~36 (
// Equation(s):
// \A_SPW_TOP|tx_data|Decoder0~36_combout  = ( !\A_SPW_TOP|tx_data|wr_ptr [2] & ( \A_SPW_TOP|tx_data|wr_ptr [0] & ( (\A_SPW_TOP|tx_data|wr_ptr [3] & (!\A_SPW_TOP|tx_data|wr_ptr [5] & (!\A_SPW_TOP|tx_data|wr_ptr [4] & !\A_SPW_TOP|tx_data|wr_ptr [1]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Decoder0~36_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Decoder0~36 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Decoder0~36 .lut_mask = 64'h0000000040000000;
defparam \A_SPW_TOP|tx_data|Decoder0~36 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y11_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector86~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector86~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.01~q  & ( \A_SPW_TOP|tx_data|Decoder0~36_combout  ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.01~q  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// \A_SPW_TOP|tx_data|Decoder0~36_combout ) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|tx_data|Decoder0~36_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector86~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector86~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector86~0 .lut_mask = 64'h0A0A0A0A0F0F0F0F;
defparam \A_SPW_TOP|tx_data|Selector86~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y13_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector86~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector86~1_combout  = ( \A_SPW_TOP|tx_data|Mux0~20_combout  & ( \A_SPW_TOP|tx_data|Selector86~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q ) # (\u0|write_data_fifo_tx|data_out [8]) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|Mux0~20_combout  & ( \A_SPW_TOP|tx_data|Selector86~0_combout  & ( (\u0|write_data_fifo_tx|data_out [8] & \A_SPW_TOP|tx_data|state_data_write.00~q ) ) ) ) # ( \A_SPW_TOP|tx_data|Mux0~20_combout  & ( 
// !\A_SPW_TOP|tx_data|Selector86~0_combout  & ( \A_SPW_TOP|tx_data|mem[9][8]~q  ) ) ) # ( !\A_SPW_TOP|tx_data|Mux0~20_combout  & ( !\A_SPW_TOP|tx_data|Selector86~0_combout  & ( \A_SPW_TOP|tx_data|mem[9][8]~q  ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[9][8]~q ),
        .datab(!\u0|write_data_fifo_tx|data_out [8]),
        .datac(gnd),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(!\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .dataf(!\A_SPW_TOP|tx_data|Selector86~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector86~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector86~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector86~1 .lut_mask = 64'h555555550033FF33;
defparam \A_SPW_TOP|tx_data|Selector86~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y13_N35
dffeas \A_SPW_TOP|tx_data|mem[9][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector86~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[9][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[9][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[9][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y15_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Decoder0~44 (
// Equation(s):
// \A_SPW_TOP|tx_data|Decoder0~44_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [3] & ( !\A_SPW_TOP|tx_data|wr_ptr [4] & ( (\A_SPW_TOP|tx_data|wr_ptr [2] & (!\A_SPW_TOP|tx_data|wr_ptr [1] & (!\A_SPW_TOP|tx_data|wr_ptr [5] & \A_SPW_TOP|tx_data|wr_ptr [0]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Decoder0~44_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Decoder0~44 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Decoder0~44 .lut_mask = 64'h0000004000000000;
defparam \A_SPW_TOP|tx_data|Decoder0~44 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y15_N27
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector122~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector122~0_combout  = ( \A_SPW_TOP|tx_data|Decoder0~44_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q ) # (\A_SPW_TOP|tx_data|state_data_write.01~q ) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .datab(gnd),
        .datac(gnd),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Decoder0~44_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector122~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector122~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector122~0 .lut_mask = 64'h00000000FF55FF55;
defparam \A_SPW_TOP|tx_data|Selector122~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y12_N9
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector122~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector122~1_combout  = ( \A_SPW_TOP|tx_data|Selector122~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux0~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [8]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector122~0_combout  & ( \A_SPW_TOP|tx_data|mem[13][8]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .datac(!\u0|write_data_fifo_tx|data_out [8]),
        .datad(!\A_SPW_TOP|tx_data|mem[13][8]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector122~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector122~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector122~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector122~1 .lut_mask = 64'h00FF00FF27272727;
defparam \A_SPW_TOP|tx_data|Selector122~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y12_N8
dffeas \A_SPW_TOP|tx_data|mem[13][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector122~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[13][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[13][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[13][8] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y12_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux0~11 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux0~11_combout  = ( \A_SPW_TOP|tx_data|mem[13][8]~q  & ( \A_SPW_TOP|tx_data|wr_ptr [5] & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|mem[41][8]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [2] & ((\A_SPW_TOP|tx_data|mem[45][8]~q ))) ) 
// ) ) # ( !\A_SPW_TOP|tx_data|mem[13][8]~q  & ( \A_SPW_TOP|tx_data|wr_ptr [5] & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|mem[41][8]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [2] & ((\A_SPW_TOP|tx_data|mem[45][8]~q ))) ) ) ) # ( 
// \A_SPW_TOP|tx_data|mem[13][8]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [5] & ( (\A_SPW_TOP|tx_data|wr_ptr [2]) # (\A_SPW_TOP|tx_data|mem[9][8]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[13][8]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [5] & ( (\A_SPW_TOP|tx_data|mem[9][8]~q  
// & !\A_SPW_TOP|tx_data|wr_ptr [2]) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[41][8]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[45][8]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[9][8]~q ),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datae(!\A_SPW_TOP|tx_data|mem[13][8]~q ),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux0~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux0~11 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux0~11 .lut_mask = 64'h0F000FFF55335533;
defparam \A_SPW_TOP|tx_data|Mux0~11 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y15_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Decoder0~32 (
// Equation(s):
// \A_SPW_TOP|tx_data|Decoder0~32_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [0] & ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & (!\A_SPW_TOP|tx_data|wr_ptr [4] & (!\A_SPW_TOP|tx_data|wr_ptr [5] & !\A_SPW_TOP|tx_data|wr_ptr [3]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Decoder0~32_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Decoder0~32 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Decoder0~32 .lut_mask = 64'h0000800000000000;
defparam \A_SPW_TOP|tx_data|Decoder0~32 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y15_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector14~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector14~0_combout  = ( \A_SPW_TOP|tx_data|Decoder0~32_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q ) # (\A_SPW_TOP|tx_data|state_data_write.01~q ) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .datab(gnd),
        .datac(gnd),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Decoder0~32_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector14~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector14~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector14~0 .lut_mask = 64'h00000000FF55FF55;
defparam \A_SPW_TOP|tx_data|Selector14~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y12_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector14~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector14~1_combout  = ( \A_SPW_TOP|tx_data|mem[1][8]~q  & ( (!\A_SPW_TOP|tx_data|Selector14~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux0~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [8])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[1][8]~q  & ( (\A_SPW_TOP|tx_data|Selector14~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux0~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [8]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [8]),
        .datac(!\A_SPW_TOP|tx_data|Selector14~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[1][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector14~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector14~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector14~1 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|tx_data|Selector14~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y12_N53
dffeas \A_SPW_TOP|tx_data|mem[1][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector14~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[1][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[1][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[1][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y11_N27
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Decoder0~40 (
// Equation(s):
// \A_SPW_TOP|tx_data|Decoder0~40_combout  = ( !\A_SPW_TOP|tx_data|wr_ptr [4] & ( \A_SPW_TOP|tx_data|wr_ptr [0] & ( (\A_SPW_TOP|tx_data|wr_ptr [2] & (!\A_SPW_TOP|tx_data|wr_ptr [1] & (!\A_SPW_TOP|tx_data|wr_ptr [3] & !\A_SPW_TOP|tx_data|wr_ptr [5]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Decoder0~40_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Decoder0~40 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Decoder0~40 .lut_mask = 64'h0000000040000000;
defparam \A_SPW_TOP|tx_data|Decoder0~40 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y11_N27
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector50~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector50~0_combout  = ( \A_SPW_TOP|tx_data|Decoder0~40_combout  & ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( \A_SPW_TOP|tx_data|state_data_write.01~q  ) ) ) # ( \A_SPW_TOP|tx_data|Decoder0~40_combout  & ( 
// !\A_SPW_TOP|tx_data|state_data_write.00~q  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|tx_data|Decoder0~40_combout ),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector50~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector50~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector50~0 .lut_mask = 64'h0000FFFF00000F0F;
defparam \A_SPW_TOP|tx_data|Selector50~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y12_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector50~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector50~1_combout  = ( \A_SPW_TOP|tx_data|mem[5][8]~q  & ( (!\A_SPW_TOP|tx_data|Selector50~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux0~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [8])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[5][8]~q  & ( (\A_SPW_TOP|tx_data|Selector50~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux0~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [8]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [8]),
        .datac(!\A_SPW_TOP|tx_data|Selector50~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[5][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector50~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector50~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector50~1 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|tx_data|Selector50~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y12_N11
dffeas \A_SPW_TOP|tx_data|mem[5][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector50~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[5][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[5][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[5][8] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y13_N45
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Decoder0~33 (
// Equation(s):
// \A_SPW_TOP|tx_data|Decoder0~33_combout  = ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( !\A_SPW_TOP|tx_data|wr_ptr [3] & ( (\A_SPW_TOP|tx_data|wr_ptr [0] & (!\A_SPW_TOP|tx_data|wr_ptr [4] & (!\A_SPW_TOP|tx_data|wr_ptr [2] & \A_SPW_TOP|tx_data|wr_ptr [5]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Decoder0~33_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Decoder0~33 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Decoder0~33 .lut_mask = 64'h0040000000000000;
defparam \A_SPW_TOP|tx_data|Decoder0~33 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y13_N39
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector302~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector302~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (\A_SPW_TOP|tx_data|state_data_write.01~q  & \A_SPW_TOP|tx_data|Decoder0~33_combout ) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( 
// \A_SPW_TOP|tx_data|Decoder0~33_combout  ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|tx_data|Decoder0~33_combout ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector302~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector302~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector302~0 .lut_mask = 64'h0F0F05050F0F0505;
defparam \A_SPW_TOP|tx_data|Selector302~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y12_N39
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector302~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector302~1_combout  = ( \A_SPW_TOP|tx_data|mem[33][8]~q  & ( (!\A_SPW_TOP|tx_data|Selector302~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux0~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [8])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[33][8]~q  & ( (\A_SPW_TOP|tx_data|Selector302~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux0~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [8]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [8]),
        .datac(!\A_SPW_TOP|tx_data|Selector302~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[33][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector302~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector302~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector302~1 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|tx_data|Selector302~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y12_N26
dffeas \A_SPW_TOP|tx_data|mem[33][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector302~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[33][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[33][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[33][8] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y14_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Decoder0~41 (
// Equation(s):
// \A_SPW_TOP|tx_data|Decoder0~41_combout  = ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( \A_SPW_TOP|tx_data|wr_ptr [5] & ( (!\A_SPW_TOP|tx_data|wr_ptr [3] & (!\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|wr_ptr [0] & \A_SPW_TOP|tx_data|wr_ptr [2]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Decoder0~41_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Decoder0~41 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Decoder0~41 .lut_mask = 64'h0000000000080000;
defparam \A_SPW_TOP|tx_data|Decoder0~41 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y14_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector338~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector338~0_combout  = ( \A_SPW_TOP|tx_data|Decoder0~41_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q ) # (\A_SPW_TOP|tx_data|state_data_write.01~q ) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Decoder0~41_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector338~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector338~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector338~0 .lut_mask = 64'h00000000AFAFAFAF;
defparam \A_SPW_TOP|tx_data|Selector338~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y12_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector338~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector338~1_combout  = ( \A_SPW_TOP|tx_data|Mux0~20_combout  & ( (!\A_SPW_TOP|tx_data|Selector338~0_combout  & (((\A_SPW_TOP|tx_data|mem[37][8]~q )))) # (\A_SPW_TOP|tx_data|Selector338~0_combout  & 
// ((!\A_SPW_TOP|tx_data|state_data_write.00~q ) # ((\u0|write_data_fifo_tx|data_out [8])))) ) ) # ( !\A_SPW_TOP|tx_data|Mux0~20_combout  & ( (!\A_SPW_TOP|tx_data|Selector338~0_combout  & (((\A_SPW_TOP|tx_data|mem[37][8]~q )))) # 
// (\A_SPW_TOP|tx_data|Selector338~0_combout  & (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [8]))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\u0|write_data_fifo_tx|data_out [8]),
        .datac(!\A_SPW_TOP|tx_data|Selector338~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|mem[37][8]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector338~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector338~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector338~1 .lut_mask = 64'h01F101F10BFB0BFB;
defparam \A_SPW_TOP|tx_data|Selector338~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y12_N23
dffeas \A_SPW_TOP|tx_data|mem[37][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector338~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[37][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[37][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[37][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y12_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux0~10 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux0~10_combout  = ( \A_SPW_TOP|tx_data|mem[37][8]~q  & ( \A_SPW_TOP|tx_data|wr_ptr [2] & ( (\A_SPW_TOP|tx_data|wr_ptr [5]) # (\A_SPW_TOP|tx_data|mem[5][8]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[37][8]~q  & ( \A_SPW_TOP|tx_data|wr_ptr 
// [2] & ( (\A_SPW_TOP|tx_data|mem[5][8]~q  & !\A_SPW_TOP|tx_data|wr_ptr [5]) ) ) ) # ( \A_SPW_TOP|tx_data|mem[37][8]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [2] & ( (!\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|mem[1][8]~q )) # (\A_SPW_TOP|tx_data|wr_ptr 
// [5] & ((\A_SPW_TOP|tx_data|mem[33][8]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[37][8]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [2] & ( (!\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|mem[1][8]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [5] & 
// ((\A_SPW_TOP|tx_data|mem[33][8]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[1][8]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[5][8]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[33][8]~q ),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datae(!\A_SPW_TOP|tx_data|mem[37][8]~q ),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux0~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux0~10 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux0~10 .lut_mask = 64'h550F550F330033FF;
defparam \A_SPW_TOP|tx_data|Mux0~10 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y14_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Decoder0~55 (
// Equation(s):
// \A_SPW_TOP|tx_data|Decoder0~55_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [4] & ( \A_SPW_TOP|tx_data|wr_ptr [3] & ( (\A_SPW_TOP|tx_data|wr_ptr [0] & (!\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|wr_ptr [2] & \A_SPW_TOP|tx_data|wr_ptr [5]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Decoder0~55_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Decoder0~55 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Decoder0~55 .lut_mask = 64'h0000000000000004;
defparam \A_SPW_TOP|tx_data|Decoder0~55 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y14_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector554~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector554~0_combout  = ( \A_SPW_TOP|tx_data|Decoder0~55_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q ) # (\A_SPW_TOP|tx_data|state_data_write.01~q ) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Decoder0~55_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector554~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector554~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector554~0 .lut_mask = 64'h00000000DDDDDDDD;
defparam \A_SPW_TOP|tx_data|Selector554~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y12_N21
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector554~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector554~1_combout  = ( \A_SPW_TOP|tx_data|mem[61][8]~q  & ( (!\A_SPW_TOP|tx_data|Selector554~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux0~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [8])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[61][8]~q  & ( (\A_SPW_TOP|tx_data|Selector554~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux0~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [8]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [8]),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|tx_data|Selector554~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[61][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector554~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector554~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector554~1 .lut_mask = 64'h00530053FF53FF53;
defparam \A_SPW_TOP|tx_data|Selector554~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y12_N32
dffeas \A_SPW_TOP|tx_data|mem[61][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector554~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[61][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[61][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[61][8] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y14_N21
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Decoder0~49 (
// Equation(s):
// \A_SPW_TOP|tx_data|Decoder0~49_combout  = ( !\A_SPW_TOP|tx_data|wr_ptr [5] & ( \A_SPW_TOP|tx_data|wr_ptr [0] & ( (!\A_SPW_TOP|tx_data|wr_ptr [1] & (!\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|wr_ptr [4] & \A_SPW_TOP|tx_data|wr_ptr [3]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Decoder0~49_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Decoder0~49 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Decoder0~49 .lut_mask = 64'h0000000000080000;
defparam \A_SPW_TOP|tx_data|Decoder0~49 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y14_N45
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector230~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector230~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (\A_SPW_TOP|tx_data|state_data_write.01~q  & \A_SPW_TOP|tx_data|Decoder0~49_combout ) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( 
// \A_SPW_TOP|tx_data|Decoder0~49_combout  ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .datab(gnd),
        .datac(gnd),
        .datad(!\A_SPW_TOP|tx_data|Decoder0~49_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector230~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector230~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector230~0 .lut_mask = 64'h00FF00FF00550055;
defparam \A_SPW_TOP|tx_data|Selector230~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y12_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector230~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector230~1_combout  = ( \u0|write_data_fifo_tx|data_out [8] & ( \A_SPW_TOP|tx_data|mem[25][8]~q  & ( ((!\A_SPW_TOP|tx_data|Selector230~0_combout ) # (\A_SPW_TOP|tx_data|state_data_write.00~q )) # (\A_SPW_TOP|tx_data|Mux0~20_combout ) 
// ) ) ) # ( !\u0|write_data_fifo_tx|data_out [8] & ( \A_SPW_TOP|tx_data|mem[25][8]~q  & ( (!\A_SPW_TOP|tx_data|Selector230~0_combout ) # ((\A_SPW_TOP|tx_data|Mux0~20_combout  & !\A_SPW_TOP|tx_data|state_data_write.00~q )) ) ) ) # ( 
// \u0|write_data_fifo_tx|data_out [8] & ( !\A_SPW_TOP|tx_data|mem[25][8]~q  & ( (\A_SPW_TOP|tx_data|Selector230~0_combout  & ((\A_SPW_TOP|tx_data|state_data_write.00~q ) # (\A_SPW_TOP|tx_data|Mux0~20_combout ))) ) ) ) # ( !\u0|write_data_fifo_tx|data_out 
// [8] & ( !\A_SPW_TOP|tx_data|mem[25][8]~q  & ( (\A_SPW_TOP|tx_data|Mux0~20_combout  & (!\A_SPW_TOP|tx_data|state_data_write.00~q  & \A_SPW_TOP|tx_data|Selector230~0_combout )) ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|tx_data|Selector230~0_combout ),
        .datae(!\u0|write_data_fifo_tx|data_out [8]),
        .dataf(!\A_SPW_TOP|tx_data|mem[25][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector230~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector230~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector230~1 .lut_mask = 64'h0030003FFF30FF3F;
defparam \A_SPW_TOP|tx_data|Selector230~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y12_N53
dffeas \A_SPW_TOP|tx_data|mem[25][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector230~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[25][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[25][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[25][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y11_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Decoder0~53 (
// Equation(s):
// \A_SPW_TOP|tx_data|Decoder0~53_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [0] & ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|wr_ptr [5] & \A_SPW_TOP|tx_data|wr_ptr [3]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Decoder0~53_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Decoder0~53 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Decoder0~53 .lut_mask = 64'h0000000200000000;
defparam \A_SPW_TOP|tx_data|Decoder0~53 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y11_N39
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector518~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector518~0_combout  = ( \A_SPW_TOP|tx_data|Decoder0~53_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q ) # (\A_SPW_TOP|tx_data|state_data_write.01~q ) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Decoder0~53_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector518~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector518~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector518~0 .lut_mask = 64'h00000000BBBBBBBB;
defparam \A_SPW_TOP|tx_data|Selector518~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y12_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector518~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector518~1_combout  = ( \A_SPW_TOP|tx_data|mem[57][8]~q  & ( (!\A_SPW_TOP|tx_data|Selector518~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux0~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [8])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[57][8]~q  & ( (\A_SPW_TOP|tx_data|Selector518~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux0~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [8]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [8]),
        .datac(!\A_SPW_TOP|tx_data|Selector518~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[57][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector518~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector518~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector518~1 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|tx_data|Selector518~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y12_N53
dffeas \A_SPW_TOP|tx_data|mem[57][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector518~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[57][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[57][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[57][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y15_N15
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Decoder0~51 (
// Equation(s):
// \A_SPW_TOP|tx_data|Decoder0~51_combout  = ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( \A_SPW_TOP|tx_data|wr_ptr [0] & ( (!\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|wr_ptr [3] & \A_SPW_TOP|tx_data|wr_ptr [2]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Decoder0~51_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Decoder0~51 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Decoder0~51 .lut_mask = 64'h0000000000020000;
defparam \A_SPW_TOP|tx_data|Decoder0~51 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y15_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector266~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector266~0_combout  = ( \A_SPW_TOP|tx_data|Decoder0~51_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q ) # (\A_SPW_TOP|tx_data|state_data_write.01~q ) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Decoder0~51_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector266~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector266~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector266~0 .lut_mask = 64'h00000000BBBBBBBB;
defparam \A_SPW_TOP|tx_data|Selector266~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y12_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector266~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector266~1_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector266~0_combout  & ((\A_SPW_TOP|tx_data|mem[29][8]~q ))) # (\A_SPW_TOP|tx_data|Selector266~0_combout  & (\u0|write_data_fifo_tx|data_out 
// [8])) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector266~0_combout  & ((\A_SPW_TOP|tx_data|mem[29][8]~q ))) # (\A_SPW_TOP|tx_data|Selector266~0_combout  & (\A_SPW_TOP|tx_data|Mux0~20_combout )) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [8]),
        .datac(!\A_SPW_TOP|tx_data|Selector266~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|mem[29][8]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector266~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector266~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector266~1 .lut_mask = 64'h05F505F503F303F3;
defparam \A_SPW_TOP|tx_data|Selector266~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y12_N2
dffeas \A_SPW_TOP|tx_data|mem[29][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector266~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[29][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[29][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[29][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y12_N45
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux0~13 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux0~13_combout  = ( \A_SPW_TOP|tx_data|mem[29][8]~q  & ( \A_SPW_TOP|tx_data|wr_ptr [5] & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & ((\A_SPW_TOP|tx_data|mem[57][8]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|mem[61][8]~q )) ) 
// ) ) # ( !\A_SPW_TOP|tx_data|mem[29][8]~q  & ( \A_SPW_TOP|tx_data|wr_ptr [5] & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & ((\A_SPW_TOP|tx_data|mem[57][8]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|mem[61][8]~q )) ) ) ) # ( 
// \A_SPW_TOP|tx_data|mem[29][8]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [5] & ( (\A_SPW_TOP|tx_data|mem[25][8]~q ) # (\A_SPW_TOP|tx_data|wr_ptr [2]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[29][8]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [5] & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] 
// & \A_SPW_TOP|tx_data|mem[25][8]~q ) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datab(!\A_SPW_TOP|tx_data|mem[61][8]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[25][8]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[57][8]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[29][8]~q ),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux0~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux0~13 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux0~13 .lut_mask = 64'h0A0A5F5F11BB11BB;
defparam \A_SPW_TOP|tx_data|Mux0~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y15_N39
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Decoder0~48 (
// Equation(s):
// \A_SPW_TOP|tx_data|Decoder0~48_combout  = ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( \A_SPW_TOP|tx_data|wr_ptr [0] & ( (!\A_SPW_TOP|tx_data|wr_ptr [5] & (!\A_SPW_TOP|tx_data|wr_ptr [3] & (\A_SPW_TOP|tx_data|wr_ptr [4] & !\A_SPW_TOP|tx_data|wr_ptr [2]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Decoder0~48_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Decoder0~48 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Decoder0~48 .lut_mask = 64'h0000000008000000;
defparam \A_SPW_TOP|tx_data|Decoder0~48 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y15_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector158~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector158~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.01~q  & ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( \A_SPW_TOP|tx_data|Decoder0~48_combout  ) ) ) # ( \A_SPW_TOP|tx_data|state_data_write.01~q  & ( 
// !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( \A_SPW_TOP|tx_data|Decoder0~48_combout  ) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.01~q  & ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( \A_SPW_TOP|tx_data|Decoder0~48_combout  ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|tx_data|Decoder0~48_combout ),
        .datac(gnd),
        .datad(gnd),
        .datae(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector158~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector158~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector158~0 .lut_mask = 64'h3333333300003333;
defparam \A_SPW_TOP|tx_data|Selector158~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y12_N27
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector158~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector158~1_combout  = ( \A_SPW_TOP|tx_data|Selector158~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux0~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [8]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector158~0_combout  & ( \A_SPW_TOP|tx_data|mem[17][8]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [8]),
        .datac(!\A_SPW_TOP|tx_data|mem[17][8]~q ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector158~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector158~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector158~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector158~1 .lut_mask = 64'h0F0F0F0F55335533;
defparam \A_SPW_TOP|tx_data|Selector158~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y12_N44
dffeas \A_SPW_TOP|tx_data|mem[17][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector158~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[17][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[17][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[17][8] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y14_N15
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Decoder0~52 (
// Equation(s):
// \A_SPW_TOP|tx_data|Decoder0~52_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [4] & ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( (\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|wr_ptr [5] & (!\A_SPW_TOP|tx_data|wr_ptr [2] & !\A_SPW_TOP|tx_data|wr_ptr [3]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Decoder0~52_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Decoder0~52 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Decoder0~52 .lut_mask = 64'h0000100000000000;
defparam \A_SPW_TOP|tx_data|Decoder0~52 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y14_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector446~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector446~0_combout  = ( \A_SPW_TOP|tx_data|Decoder0~52_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q ) # (\A_SPW_TOP|tx_data|state_data_write.01~q ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Decoder0~52_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector446~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector446~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector446~0 .lut_mask = 64'h00000000F0FFF0FF;
defparam \A_SPW_TOP|tx_data|Selector446~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y12_N9
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector446~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector446~1_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector446~0_combout  & ((\A_SPW_TOP|tx_data|mem[49][8]~q ))) # (\A_SPW_TOP|tx_data|Selector446~0_combout  & (\u0|write_data_fifo_tx|data_out 
// [8])) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector446~0_combout  & (\A_SPW_TOP|tx_data|mem[49][8]~q )) # (\A_SPW_TOP|tx_data|Selector446~0_combout  & ((\A_SPW_TOP|tx_data|Mux0~20_combout ))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Selector446~0_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [8]),
        .datac(!\A_SPW_TOP|tx_data|mem[49][8]~q ),
        .datad(!\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .datae(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector446~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector446~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector446~1 .lut_mask = 64'h0A5F1B1B0A5F1B1B;
defparam \A_SPW_TOP|tx_data|Selector446~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y12_N8
dffeas \A_SPW_TOP|tx_data|mem[49][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector446~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[49][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[49][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[49][8] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y13_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Decoder0~54 (
// Equation(s):
// \A_SPW_TOP|tx_data|Decoder0~54_combout  = ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( \A_SPW_TOP|tx_data|wr_ptr [5] & ( (\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|wr_ptr [0] & !\A_SPW_TOP|tx_data|wr_ptr [3]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Decoder0~54_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Decoder0~54 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Decoder0~54 .lut_mask = 64'h0000000001000000;
defparam \A_SPW_TOP|tx_data|Decoder0~54 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y13_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector482~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector482~0_combout  = (\A_SPW_TOP|tx_data|Decoder0~54_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q ) # (\A_SPW_TOP|tx_data|state_data_write.01~q )))

        .dataa(gnd),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Decoder0~54_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector482~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector482~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector482~0 .lut_mask = 64'h0C0F0C0F0C0F0C0F;
defparam \A_SPW_TOP|tx_data|Selector482~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y12_N39
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector482~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector482~1_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector482~0_combout  & ((\A_SPW_TOP|tx_data|mem[53][8]~q ))) # (\A_SPW_TOP|tx_data|Selector482~0_combout  & (\u0|write_data_fifo_tx|data_out 
// [8])) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector482~0_combout  & ((\A_SPW_TOP|tx_data|mem[53][8]~q ))) # (\A_SPW_TOP|tx_data|Selector482~0_combout  & (\A_SPW_TOP|tx_data|Mux0~20_combout )) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [8]),
        .datac(!\A_SPW_TOP|tx_data|Selector482~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|mem[53][8]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector482~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector482~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector482~1 .lut_mask = 64'h05F505F503F303F3;
defparam \A_SPW_TOP|tx_data|Selector482~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y12_N5
dffeas \A_SPW_TOP|tx_data|mem[53][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector482~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[53][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[53][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[53][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y15_N15
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Decoder0~50 (
// Equation(s):
// \A_SPW_TOP|tx_data|Decoder0~50_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [4] & ( !\A_SPW_TOP|tx_data|wr_ptr [3] & ( (\A_SPW_TOP|tx_data|wr_ptr [2] & (!\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|wr_ptr [0] & !\A_SPW_TOP|tx_data|wr_ptr [5]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Decoder0~50_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Decoder0~50 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Decoder0~50 .lut_mask = 64'h0000040000000000;
defparam \A_SPW_TOP|tx_data|Decoder0~50 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y15_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector194~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector194~0_combout  = ( \A_SPW_TOP|tx_data|Decoder0~50_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q ) # (\A_SPW_TOP|tx_data|state_data_write.01~q ) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Decoder0~50_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector194~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector194~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector194~0 .lut_mask = 64'h00000000F5F5F5F5;
defparam \A_SPW_TOP|tx_data|Selector194~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y12_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector194~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector194~1_combout  = ( \A_SPW_TOP|tx_data|mem[21][8]~q  & ( (!\A_SPW_TOP|tx_data|Selector194~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux0~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [8])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[21][8]~q  & ( (\A_SPW_TOP|tx_data|Selector194~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux0~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [8]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [8]),
        .datac(!\A_SPW_TOP|tx_data|Selector194~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[21][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector194~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector194~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector194~1 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|tx_data|Selector194~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y12_N17
dffeas \A_SPW_TOP|tx_data|mem[21][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector194~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[21][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[21][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[21][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y12_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux0~12 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux0~12_combout  = ( \A_SPW_TOP|tx_data|mem[53][8]~q  & ( \A_SPW_TOP|tx_data|mem[21][8]~q  & ( ((!\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|mem[17][8]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [5] & ((\A_SPW_TOP|tx_data|mem[49][8]~q 
// )))) # (\A_SPW_TOP|tx_data|wr_ptr [2]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[53][8]~q  & ( \A_SPW_TOP|tx_data|mem[21][8]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [5] & (((\A_SPW_TOP|tx_data|wr_ptr [2])) # (\A_SPW_TOP|tx_data|mem[17][8]~q ))) # 
// (\A_SPW_TOP|tx_data|wr_ptr [5] & (((!\A_SPW_TOP|tx_data|wr_ptr [2] & \A_SPW_TOP|tx_data|mem[49][8]~q )))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[53][8]~q  & ( !\A_SPW_TOP|tx_data|mem[21][8]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [5] & 
// (\A_SPW_TOP|tx_data|mem[17][8]~q  & (!\A_SPW_TOP|tx_data|wr_ptr [2]))) # (\A_SPW_TOP|tx_data|wr_ptr [5] & (((\A_SPW_TOP|tx_data|mem[49][8]~q ) # (\A_SPW_TOP|tx_data|wr_ptr [2])))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[53][8]~q  & ( 
// !\A_SPW_TOP|tx_data|mem[21][8]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & ((!\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|mem[17][8]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [5] & ((\A_SPW_TOP|tx_data|mem[49][8]~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datab(!\A_SPW_TOP|tx_data|mem[17][8]~q ),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datad(!\A_SPW_TOP|tx_data|mem[49][8]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[53][8]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[21][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux0~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux0~12 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux0~12 .lut_mask = 64'h207025752A7A2F7F;
defparam \A_SPW_TOP|tx_data|Mux0~12 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y12_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux0~14 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux0~14_combout  = ( \A_SPW_TOP|tx_data|Mux0~12_combout  & ( \A_SPW_TOP|tx_data|wr_ptr [4] & ( (!\A_SPW_TOP|tx_data|wr_ptr [3]) # (\A_SPW_TOP|tx_data|Mux0~13_combout ) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux0~12_combout  & ( 
// \A_SPW_TOP|tx_data|wr_ptr [4] & ( (\A_SPW_TOP|tx_data|wr_ptr [3] & \A_SPW_TOP|tx_data|Mux0~13_combout ) ) ) ) # ( \A_SPW_TOP|tx_data|Mux0~12_combout  & ( !\A_SPW_TOP|tx_data|wr_ptr [4] & ( (!\A_SPW_TOP|tx_data|wr_ptr [3] & 
// ((\A_SPW_TOP|tx_data|Mux0~10_combout ))) # (\A_SPW_TOP|tx_data|wr_ptr [3] & (\A_SPW_TOP|tx_data|Mux0~11_combout )) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux0~12_combout  & ( !\A_SPW_TOP|tx_data|wr_ptr [4] & ( (!\A_SPW_TOP|tx_data|wr_ptr [3] & 
// ((\A_SPW_TOP|tx_data|Mux0~10_combout ))) # (\A_SPW_TOP|tx_data|wr_ptr [3] & (\A_SPW_TOP|tx_data|Mux0~11_combout )) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datab(!\A_SPW_TOP|tx_data|Mux0~11_combout ),
        .datac(!\A_SPW_TOP|tx_data|Mux0~10_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux0~13_combout ),
        .datae(!\A_SPW_TOP|tx_data|Mux0~12_combout ),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux0~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux0~14 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux0~14 .lut_mask = 64'h1B1B1B1B0055AAFF;
defparam \A_SPW_TOP|tx_data|Mux0~14 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y13_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux0~20 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux0~20_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [1] & ( \A_SPW_TOP|tx_data|Mux0~14_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|Mux0~9_combout ))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & 
// (\A_SPW_TOP|tx_data|Mux0~19_combout )) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( \A_SPW_TOP|tx_data|Mux0~14_combout  & ( (\A_SPW_TOP|tx_data|wr_ptr [0]) # (\A_SPW_TOP|tx_data|Mux0~4_combout ) ) ) ) # ( \A_SPW_TOP|tx_data|wr_ptr [1] & ( 
// !\A_SPW_TOP|tx_data|Mux0~14_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|Mux0~9_combout ))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|Mux0~19_combout )) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( 
// !\A_SPW_TOP|tx_data|Mux0~14_combout  & ( (\A_SPW_TOP|tx_data|Mux0~4_combout  & !\A_SPW_TOP|tx_data|wr_ptr [0]) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux0~4_combout ),
        .datab(!\A_SPW_TOP|tx_data|Mux0~19_combout ),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datad(!\A_SPW_TOP|tx_data|Mux0~9_combout ),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .dataf(!\A_SPW_TOP|tx_data|Mux0~14_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux0~20 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux0~20 .lut_mask = 64'h505003F35F5F03F3;
defparam \A_SPW_TOP|tx_data|Mux0~20 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y13_N45
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector401~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector401~1_combout  = ( \A_SPW_TOP|tx_data|mem[44][8]~q  & ( (!\A_SPW_TOP|tx_data|Selector401~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux0~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [8]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[44][8]~q  & ( (\A_SPW_TOP|tx_data|Selector401~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux0~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [8])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [8]),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector401~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux0~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[44][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector401~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector401~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector401~1 .lut_mask = 64'h010D010DF1FDF1FD;
defparam \A_SPW_TOP|tx_data|Selector401~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y13_N50
dffeas \A_SPW_TOP|tx_data|mem[44][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector401~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[44][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[44][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[44][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y13_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux9~3 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux9~3_combout  = ( \A_SPW_TOP|tx_data|rd_ptr [1] & ( \A_SPW_TOP|tx_data|mem[14][8]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5]) # (\A_SPW_TOP|tx_data|mem[46][8]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [1] & ( 
// \A_SPW_TOP|tx_data|mem[14][8]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & ((\A_SPW_TOP|tx_data|mem[12][8]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|mem[44][8]~q )) ) ) ) # ( \A_SPW_TOP|tx_data|rd_ptr [1] & ( 
// !\A_SPW_TOP|tx_data|mem[14][8]~q  & ( (\A_SPW_TOP|tx_data|rd_ptr [5] & \A_SPW_TOP|tx_data|mem[46][8]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [1] & ( !\A_SPW_TOP|tx_data|mem[14][8]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & ((\A_SPW_TOP|tx_data|mem[12][8]~q 
// ))) # (\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|mem[44][8]~q )) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [5]),
        .datab(!\A_SPW_TOP|tx_data|mem[44][8]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[46][8]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[12][8]~q ),
        .datae(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .dataf(!\A_SPW_TOP|tx_data|mem[14][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux9~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux9~3 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux9~3 .lut_mask = 64'h11BB050511BBAFAF;
defparam \A_SPW_TOP|tx_data|Mux9~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y13_N15
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux9~2 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux9~2_combout  = ( \A_SPW_TOP|tx_data|rd_ptr [1] & ( \A_SPW_TOP|tx_data|rd_ptr [5] & ( \A_SPW_TOP|tx_data|mem[38][8]~q  ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [1] & ( \A_SPW_TOP|tx_data|rd_ptr [5] & ( \A_SPW_TOP|tx_data|mem[36][8]~q  ) ) 
// ) # ( \A_SPW_TOP|tx_data|rd_ptr [1] & ( !\A_SPW_TOP|tx_data|rd_ptr [5] & ( \A_SPW_TOP|tx_data|mem[6][8]~q  ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [1] & ( !\A_SPW_TOP|tx_data|rd_ptr [5] & ( \A_SPW_TOP|tx_data|mem[4][8]~q  ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[6][8]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[36][8]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[38][8]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[4][8]~q ),
        .datae(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .dataf(!\A_SPW_TOP|tx_data|rd_ptr [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux9~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux9~2 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux9~2 .lut_mask = 64'h00FF555533330F0F;
defparam \A_SPW_TOP|tx_data|Mux9~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y13_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux9~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux9~0_combout  = ( \A_SPW_TOP|tx_data|rd_ptr [1] & ( \A_SPW_TOP|tx_data|mem[0][8]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & ((\A_SPW_TOP|tx_data|mem[2][8]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|mem[34][8]~q )) ) ) 
// ) # ( !\A_SPW_TOP|tx_data|rd_ptr [1] & ( \A_SPW_TOP|tx_data|mem[0][8]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5]) # (\A_SPW_TOP|tx_data|mem[32][8]~q ) ) ) ) # ( \A_SPW_TOP|tx_data|rd_ptr [1] & ( !\A_SPW_TOP|tx_data|mem[0][8]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr 
// [5] & ((\A_SPW_TOP|tx_data|mem[2][8]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|mem[34][8]~q )) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [1] & ( !\A_SPW_TOP|tx_data|mem[0][8]~q  & ( (\A_SPW_TOP|tx_data|rd_ptr [5] & 
// \A_SPW_TOP|tx_data|mem[32][8]~q ) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [5]),
        .datab(!\A_SPW_TOP|tx_data|mem[34][8]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[32][8]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[2][8]~q ),
        .datae(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .dataf(!\A_SPW_TOP|tx_data|mem[0][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux9~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux9~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux9~0 .lut_mask = 64'h050511BBAFAF11BB;
defparam \A_SPW_TOP|tx_data|Mux9~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y13_N9
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux9~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux9~1_combout  = ( \A_SPW_TOP|tx_data|mem[42][8]~q  & ( \A_SPW_TOP|tx_data|mem[10][8]~q  & ( ((!\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|mem[8][8]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [5] & ((\A_SPW_TOP|tx_data|mem[40][8]~q 
// )))) # (\A_SPW_TOP|tx_data|rd_ptr [1]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[42][8]~q  & ( \A_SPW_TOP|tx_data|mem[10][8]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & (((\A_SPW_TOP|tx_data|rd_ptr [1])) # (\A_SPW_TOP|tx_data|mem[8][8]~q ))) # 
// (\A_SPW_TOP|tx_data|rd_ptr [5] & (((!\A_SPW_TOP|tx_data|rd_ptr [1] & \A_SPW_TOP|tx_data|mem[40][8]~q )))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[42][8]~q  & ( !\A_SPW_TOP|tx_data|mem[10][8]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & 
// (\A_SPW_TOP|tx_data|mem[8][8]~q  & (!\A_SPW_TOP|tx_data|rd_ptr [1]))) # (\A_SPW_TOP|tx_data|rd_ptr [5] & (((\A_SPW_TOP|tx_data|mem[40][8]~q ) # (\A_SPW_TOP|tx_data|rd_ptr [1])))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[42][8]~q  & ( 
// !\A_SPW_TOP|tx_data|mem[10][8]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [1] & ((!\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|mem[8][8]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [5] & ((\A_SPW_TOP|tx_data|mem[40][8]~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [5]),
        .datab(!\A_SPW_TOP|tx_data|mem[8][8]~q ),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .datad(!\A_SPW_TOP|tx_data|mem[40][8]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[42][8]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[10][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux9~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux9~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux9~1 .lut_mask = 64'h207025752A7A2F7F;
defparam \A_SPW_TOP|tx_data|Mux9~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y13_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux9~4 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux9~4_combout  = ( \A_SPW_TOP|tx_data|Mux9~0_combout  & ( \A_SPW_TOP|tx_data|Mux9~1_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [2]) # ((!\A_SPW_TOP|tx_data|rd_ptr [3] & ((\A_SPW_TOP|tx_data|Mux9~2_combout ))) # (\A_SPW_TOP|tx_data|rd_ptr 
// [3] & (\A_SPW_TOP|tx_data|Mux9~3_combout ))) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux9~0_combout  & ( \A_SPW_TOP|tx_data|Mux9~1_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [3] & (((\A_SPW_TOP|tx_data|rd_ptr [2] & \A_SPW_TOP|tx_data|Mux9~2_combout )))) # 
// (\A_SPW_TOP|tx_data|rd_ptr [3] & (((!\A_SPW_TOP|tx_data|rd_ptr [2])) # (\A_SPW_TOP|tx_data|Mux9~3_combout ))) ) ) ) # ( \A_SPW_TOP|tx_data|Mux9~0_combout  & ( !\A_SPW_TOP|tx_data|Mux9~1_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [3] & 
// (((!\A_SPW_TOP|tx_data|rd_ptr [2]) # (\A_SPW_TOP|tx_data|Mux9~2_combout )))) # (\A_SPW_TOP|tx_data|rd_ptr [3] & (\A_SPW_TOP|tx_data|Mux9~3_combout  & (\A_SPW_TOP|tx_data|rd_ptr [2]))) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux9~0_combout  & ( 
// !\A_SPW_TOP|tx_data|Mux9~1_combout  & ( (\A_SPW_TOP|tx_data|rd_ptr [2] & ((!\A_SPW_TOP|tx_data|rd_ptr [3] & ((\A_SPW_TOP|tx_data|Mux9~2_combout ))) # (\A_SPW_TOP|tx_data|rd_ptr [3] & (\A_SPW_TOP|tx_data|Mux9~3_combout )))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [3]),
        .datab(!\A_SPW_TOP|tx_data|Mux9~3_combout ),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .datad(!\A_SPW_TOP|tx_data|Mux9~2_combout ),
        .datae(!\A_SPW_TOP|tx_data|Mux9~0_combout ),
        .dataf(!\A_SPW_TOP|tx_data|Mux9~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux9~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux9~4 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux9~4 .lut_mask = 64'h010BA1AB515BF1FB;
defparam \A_SPW_TOP|tx_data|Mux9~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y12_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux9~17 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux9~17_combout  = ( \A_SPW_TOP|tx_data|mem[19][8]~q  & ( \A_SPW_TOP|tx_data|mem[27][8]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [2]) # ((!\A_SPW_TOP|tx_data|rd_ptr [3] & (\A_SPW_TOP|tx_data|mem[23][8]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [3] & 
// ((\A_SPW_TOP|tx_data|mem[31][8]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[19][8]~q  & ( \A_SPW_TOP|tx_data|mem[27][8]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & (((\A_SPW_TOP|tx_data|rd_ptr [3])))) # (\A_SPW_TOP|tx_data|rd_ptr [2] & 
// ((!\A_SPW_TOP|tx_data|rd_ptr [3] & (\A_SPW_TOP|tx_data|mem[23][8]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [3] & ((\A_SPW_TOP|tx_data|mem[31][8]~q ))))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[19][8]~q  & ( !\A_SPW_TOP|tx_data|mem[27][8]~q  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [2] & (((!\A_SPW_TOP|tx_data|rd_ptr [3])))) # (\A_SPW_TOP|tx_data|rd_ptr [2] & ((!\A_SPW_TOP|tx_data|rd_ptr [3] & (\A_SPW_TOP|tx_data|mem[23][8]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [3] & ((\A_SPW_TOP|tx_data|mem[31][8]~q ))))) ) 
// ) ) # ( !\A_SPW_TOP|tx_data|mem[19][8]~q  & ( !\A_SPW_TOP|tx_data|mem[27][8]~q  & ( (\A_SPW_TOP|tx_data|rd_ptr [2] & ((!\A_SPW_TOP|tx_data|rd_ptr [3] & (\A_SPW_TOP|tx_data|mem[23][8]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [3] & 
// ((\A_SPW_TOP|tx_data|mem[31][8]~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .datab(!\A_SPW_TOP|tx_data|mem[23][8]~q ),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [3]),
        .datad(!\A_SPW_TOP|tx_data|mem[31][8]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[19][8]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[27][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux9~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux9~17 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux9~17 .lut_mask = 64'h1015B0B51A1FBABF;
defparam \A_SPW_TOP|tx_data|Mux9~17 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y12_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux9~18 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux9~18_combout  = ( \A_SPW_TOP|tx_data|rd_ptr [2] & ( \A_SPW_TOP|tx_data|mem[55][8]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [3]) # (\A_SPW_TOP|tx_data|mem[63][8]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [2] & ( 
// \A_SPW_TOP|tx_data|mem[55][8]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [3] & (\A_SPW_TOP|tx_data|mem[51][8]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [3] & ((\A_SPW_TOP|tx_data|mem[59][8]~q ))) ) ) ) # ( \A_SPW_TOP|tx_data|rd_ptr [2] & ( 
// !\A_SPW_TOP|tx_data|mem[55][8]~q  & ( (\A_SPW_TOP|tx_data|mem[63][8]~q  & \A_SPW_TOP|tx_data|rd_ptr [3]) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [2] & ( !\A_SPW_TOP|tx_data|mem[55][8]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [3] & (\A_SPW_TOP|tx_data|mem[51][8]~q 
// )) # (\A_SPW_TOP|tx_data|rd_ptr [3] & ((\A_SPW_TOP|tx_data|mem[59][8]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[51][8]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[63][8]~q ),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [3]),
        .datad(!\A_SPW_TOP|tx_data|mem[59][8]~q ),
        .datae(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .dataf(!\A_SPW_TOP|tx_data|mem[55][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux9~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux9~18 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux9~18 .lut_mask = 64'h505F0303505FF3F3;
defparam \A_SPW_TOP|tx_data|Mux9~18 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y12_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux9~16 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux9~16_combout  = ( \A_SPW_TOP|tx_data|rd_ptr [3] & ( \A_SPW_TOP|tx_data|mem[61][8]~q  & ( (\A_SPW_TOP|tx_data|mem[57][8]~q ) # (\A_SPW_TOP|tx_data|rd_ptr [2]) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [3] & ( 
// \A_SPW_TOP|tx_data|mem[61][8]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & ((\A_SPW_TOP|tx_data|mem[49][8]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[53][8]~q )) ) ) ) # ( \A_SPW_TOP|tx_data|rd_ptr [3] & ( 
// !\A_SPW_TOP|tx_data|mem[61][8]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & \A_SPW_TOP|tx_data|mem[57][8]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [3] & ( !\A_SPW_TOP|tx_data|mem[61][8]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & 
// ((\A_SPW_TOP|tx_data|mem[49][8]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[53][8]~q )) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[53][8]~q ),
        .datab(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .datac(!\A_SPW_TOP|tx_data|mem[57][8]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[49][8]~q ),
        .datae(!\A_SPW_TOP|tx_data|rd_ptr [3]),
        .dataf(!\A_SPW_TOP|tx_data|mem[61][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux9~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux9~16 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux9~16 .lut_mask = 64'h11DD0C0C11DD3F3F;
defparam \A_SPW_TOP|tx_data|Mux9~16 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y12_N33
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux9~15 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux9~15_combout  = ( \A_SPW_TOP|tx_data|rd_ptr [3] & ( \A_SPW_TOP|tx_data|mem[21][8]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & ((\A_SPW_TOP|tx_data|mem[25][8]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[29][8]~q )) ) 
// ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [3] & ( \A_SPW_TOP|tx_data|mem[21][8]~q  & ( (\A_SPW_TOP|tx_data|mem[17][8]~q ) # (\A_SPW_TOP|tx_data|rd_ptr [2]) ) ) ) # ( \A_SPW_TOP|tx_data|rd_ptr [3] & ( !\A_SPW_TOP|tx_data|mem[21][8]~q  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [2] & ((\A_SPW_TOP|tx_data|mem[25][8]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[29][8]~q )) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [3] & ( !\A_SPW_TOP|tx_data|mem[21][8]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr 
// [2] & \A_SPW_TOP|tx_data|mem[17][8]~q ) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[29][8]~q ),
        .datab(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .datac(!\A_SPW_TOP|tx_data|mem[17][8]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[25][8]~q ),
        .datae(!\A_SPW_TOP|tx_data|rd_ptr [3]),
        .dataf(!\A_SPW_TOP|tx_data|mem[21][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux9~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux9~15 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux9~15 .lut_mask = 64'h0C0C11DD3F3F11DD;
defparam \A_SPW_TOP|tx_data|Mux9~15 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y12_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux9~19 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux9~19_combout  = ( \A_SPW_TOP|tx_data|Mux9~16_combout  & ( \A_SPW_TOP|tx_data|Mux9~15_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [1]) # ((!\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|Mux9~17_combout )) # 
// (\A_SPW_TOP|tx_data|rd_ptr [5] & ((\A_SPW_TOP|tx_data|Mux9~18_combout )))) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux9~16_combout  & ( \A_SPW_TOP|tx_data|Mux9~15_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [1] & (((!\A_SPW_TOP|tx_data|rd_ptr [5])))) # 
// (\A_SPW_TOP|tx_data|rd_ptr [1] & ((!\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|Mux9~17_combout )) # (\A_SPW_TOP|tx_data|rd_ptr [5] & ((\A_SPW_TOP|tx_data|Mux9~18_combout ))))) ) ) ) # ( \A_SPW_TOP|tx_data|Mux9~16_combout  & ( 
// !\A_SPW_TOP|tx_data|Mux9~15_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [1] & (((\A_SPW_TOP|tx_data|rd_ptr [5])))) # (\A_SPW_TOP|tx_data|rd_ptr [1] & ((!\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|Mux9~17_combout )) # (\A_SPW_TOP|tx_data|rd_ptr [5] & 
// ((\A_SPW_TOP|tx_data|Mux9~18_combout ))))) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux9~16_combout  & ( !\A_SPW_TOP|tx_data|Mux9~15_combout  & ( (\A_SPW_TOP|tx_data|rd_ptr [1] & ((!\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|Mux9~17_combout )) # 
// (\A_SPW_TOP|tx_data|rd_ptr [5] & ((\A_SPW_TOP|tx_data|Mux9~18_combout ))))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux9~17_combout ),
        .datab(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [5]),
        .datad(!\A_SPW_TOP|tx_data|Mux9~18_combout ),
        .datae(!\A_SPW_TOP|tx_data|Mux9~16_combout ),
        .dataf(!\A_SPW_TOP|tx_data|Mux9~15_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux9~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux9~19 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux9~19 .lut_mask = 64'h10131C1FD0D3DCDF;
defparam \A_SPW_TOP|tx_data|Mux9~19 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y12_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux9~10 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux9~10_combout  = ( \A_SPW_TOP|tx_data|mem[35][8]~q  & ( \A_SPW_TOP|tx_data|rd_ptr [1] & ( (\A_SPW_TOP|tx_data|rd_ptr [5]) # (\A_SPW_TOP|tx_data|mem[3][8]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[35][8]~q  & ( \A_SPW_TOP|tx_data|rd_ptr 
// [1] & ( (\A_SPW_TOP|tx_data|mem[3][8]~q  & !\A_SPW_TOP|tx_data|rd_ptr [5]) ) ) ) # ( \A_SPW_TOP|tx_data|mem[35][8]~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [1] & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|mem[1][8]~q )) # (\A_SPW_TOP|tx_data|rd_ptr 
// [5] & ((\A_SPW_TOP|tx_data|mem[33][8]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[35][8]~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [1] & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|mem[1][8]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [5] & 
// ((\A_SPW_TOP|tx_data|mem[33][8]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[1][8]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[3][8]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[33][8]~q ),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [5]),
        .datae(!\A_SPW_TOP|tx_data|mem[35][8]~q ),
        .dataf(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux9~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux9~10 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux9~10 .lut_mask = 64'h550F550F330033FF;
defparam \A_SPW_TOP|tx_data|Mux9~10 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y12_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux9~11 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux9~11_combout  = ( \A_SPW_TOP|tx_data|mem[9][8]~q  & ( \A_SPW_TOP|tx_data|rd_ptr [1] & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & ((\A_SPW_TOP|tx_data|mem[11][8]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|mem[43][8]~q )) ) 
// ) ) # ( !\A_SPW_TOP|tx_data|mem[9][8]~q  & ( \A_SPW_TOP|tx_data|rd_ptr [1] & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & ((\A_SPW_TOP|tx_data|mem[11][8]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|mem[43][8]~q )) ) ) ) # ( 
// \A_SPW_TOP|tx_data|mem[9][8]~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [1] & ( (!\A_SPW_TOP|tx_data|rd_ptr [5]) # (\A_SPW_TOP|tx_data|mem[41][8]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[9][8]~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [1] & ( (\A_SPW_TOP|tx_data|rd_ptr [5] & 
// \A_SPW_TOP|tx_data|mem[41][8]~q ) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [5]),
        .datab(!\A_SPW_TOP|tx_data|mem[43][8]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[41][8]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[11][8]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[9][8]~q ),
        .dataf(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux9~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux9~11 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux9~11 .lut_mask = 64'h0505AFAF11BB11BB;
defparam \A_SPW_TOP|tx_data|Mux9~11 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y12_N27
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux9~12 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux9~12_combout  = ( \A_SPW_TOP|tx_data|mem[37][8]~q  & ( \A_SPW_TOP|tx_data|mem[5][8]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [1]) # ((!\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|mem[7][8]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [5] & 
// ((\A_SPW_TOP|tx_data|mem[39][8]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[37][8]~q  & ( \A_SPW_TOP|tx_data|mem[5][8]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [1] & (((!\A_SPW_TOP|tx_data|rd_ptr [5])))) # (\A_SPW_TOP|tx_data|rd_ptr [1] & 
// ((!\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|mem[7][8]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [5] & ((\A_SPW_TOP|tx_data|mem[39][8]~q ))))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[37][8]~q  & ( !\A_SPW_TOP|tx_data|mem[5][8]~q  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [1] & (((\A_SPW_TOP|tx_data|rd_ptr [5])))) # (\A_SPW_TOP|tx_data|rd_ptr [1] & ((!\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|mem[7][8]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [5] & ((\A_SPW_TOP|tx_data|mem[39][8]~q ))))) ) ) 
// ) # ( !\A_SPW_TOP|tx_data|mem[37][8]~q  & ( !\A_SPW_TOP|tx_data|mem[5][8]~q  & ( (\A_SPW_TOP|tx_data|rd_ptr [1] & ((!\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|mem[7][8]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [5] & ((\A_SPW_TOP|tx_data|mem[39][8]~q 
// ))))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .datab(!\A_SPW_TOP|tx_data|mem[7][8]~q ),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [5]),
        .datad(!\A_SPW_TOP|tx_data|mem[39][8]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[37][8]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[5][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux9~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux9~12 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux9~12 .lut_mask = 64'h10151A1FB0B5BABF;
defparam \A_SPW_TOP|tx_data|Mux9~12 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y12_N33
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux9~13 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux9~13_combout  = ( \A_SPW_TOP|tx_data|mem[47][8]~q  & ( \A_SPW_TOP|tx_data|rd_ptr [5] & ( (\A_SPW_TOP|tx_data|rd_ptr [1]) # (\A_SPW_TOP|tx_data|mem[45][8]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[47][8]~q  & ( \A_SPW_TOP|tx_data|rd_ptr 
// [5] & ( (\A_SPW_TOP|tx_data|mem[45][8]~q  & !\A_SPW_TOP|tx_data|rd_ptr [1]) ) ) ) # ( \A_SPW_TOP|tx_data|mem[47][8]~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [5] & ( (!\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|mem[13][8]~q )) # 
// (\A_SPW_TOP|tx_data|rd_ptr [1] & ((\A_SPW_TOP|tx_data|mem[15][8]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[47][8]~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [5] & ( (!\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|mem[13][8]~q )) # (\A_SPW_TOP|tx_data|rd_ptr 
// [1] & ((\A_SPW_TOP|tx_data|mem[15][8]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[13][8]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[15][8]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[45][8]~q ),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .datae(!\A_SPW_TOP|tx_data|mem[47][8]~q ),
        .dataf(!\A_SPW_TOP|tx_data|rd_ptr [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux9~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux9~13 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux9~13 .lut_mask = 64'h553355330F000FFF;
defparam \A_SPW_TOP|tx_data|Mux9~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y12_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux9~14 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux9~14_combout  = ( \A_SPW_TOP|tx_data|rd_ptr [3] & ( \A_SPW_TOP|tx_data|rd_ptr [2] & ( \A_SPW_TOP|tx_data|Mux9~13_combout  ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [3] & ( \A_SPW_TOP|tx_data|rd_ptr [2] & ( 
// \A_SPW_TOP|tx_data|Mux9~12_combout  ) ) ) # ( \A_SPW_TOP|tx_data|rd_ptr [3] & ( !\A_SPW_TOP|tx_data|rd_ptr [2] & ( \A_SPW_TOP|tx_data|Mux9~11_combout  ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [3] & ( !\A_SPW_TOP|tx_data|rd_ptr [2] & ( 
// \A_SPW_TOP|tx_data|Mux9~10_combout  ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux9~10_combout ),
        .datab(!\A_SPW_TOP|tx_data|Mux9~11_combout ),
        .datac(!\A_SPW_TOP|tx_data|Mux9~12_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux9~13_combout ),
        .datae(!\A_SPW_TOP|tx_data|rd_ptr [3]),
        .dataf(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux9~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux9~14 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux9~14 .lut_mask = 64'h555533330F0F00FF;
defparam \A_SPW_TOP|tx_data|Mux9~14 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y13_N51
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux9~8 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux9~8_combout  = ( \A_SPW_TOP|tx_data|rd_ptr [3] & ( \A_SPW_TOP|tx_data|mem[54][8]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[58][8]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [2] & ((\A_SPW_TOP|tx_data|mem[62][8]~q ))) ) 
// ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [3] & ( \A_SPW_TOP|tx_data|mem[54][8]~q  & ( (\A_SPW_TOP|tx_data|mem[50][8]~q ) # (\A_SPW_TOP|tx_data|rd_ptr [2]) ) ) ) # ( \A_SPW_TOP|tx_data|rd_ptr [3] & ( !\A_SPW_TOP|tx_data|mem[54][8]~q  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[58][8]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [2] & ((\A_SPW_TOP|tx_data|mem[62][8]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [3] & ( !\A_SPW_TOP|tx_data|mem[54][8]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr 
// [2] & \A_SPW_TOP|tx_data|mem[50][8]~q ) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .datab(!\A_SPW_TOP|tx_data|mem[58][8]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[62][8]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[50][8]~q ),
        .datae(!\A_SPW_TOP|tx_data|rd_ptr [3]),
        .dataf(!\A_SPW_TOP|tx_data|mem[54][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux9~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux9~8 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux9~8 .lut_mask = 64'h00AA272755FF2727;
defparam \A_SPW_TOP|tx_data|Mux9~8 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y13_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux9~7 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux9~7_combout  = ( \A_SPW_TOP|tx_data|mem[30][8]~q  & ( \A_SPW_TOP|tx_data|mem[26][8]~q  & ( ((!\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[18][8]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [2] & ((\A_SPW_TOP|tx_data|mem[22][8]~q 
// )))) # (\A_SPW_TOP|tx_data|rd_ptr [3]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[30][8]~q  & ( \A_SPW_TOP|tx_data|mem[26][8]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & (((\A_SPW_TOP|tx_data|mem[18][8]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [3]))) # 
// (\A_SPW_TOP|tx_data|rd_ptr [2] & (!\A_SPW_TOP|tx_data|rd_ptr [3] & ((\A_SPW_TOP|tx_data|mem[22][8]~q )))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[30][8]~q  & ( !\A_SPW_TOP|tx_data|mem[26][8]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & (!\A_SPW_TOP|tx_data|rd_ptr 
// [3] & (\A_SPW_TOP|tx_data|mem[18][8]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [2] & (((\A_SPW_TOP|tx_data|mem[22][8]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [3]))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[30][8]~q  & ( !\A_SPW_TOP|tx_data|mem[26][8]~q  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [3] & ((!\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[18][8]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [2] & ((\A_SPW_TOP|tx_data|mem[22][8]~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .datab(!\A_SPW_TOP|tx_data|rd_ptr [3]),
        .datac(!\A_SPW_TOP|tx_data|mem[18][8]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[22][8]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[30][8]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[26][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux9~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux9~7 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux9~7 .lut_mask = 64'h084C195D2A6E3B7F;
defparam \A_SPW_TOP|tx_data|Mux9~7 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y13_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux9~6 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux9~6_combout  = ( \A_SPW_TOP|tx_data|mem[60][8]~q  & ( \A_SPW_TOP|tx_data|rd_ptr [3] & ( (\A_SPW_TOP|tx_data|rd_ptr [2]) # (\A_SPW_TOP|tx_data|mem[56][8]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[60][8]~q  & ( \A_SPW_TOP|tx_data|rd_ptr 
// [3] & ( (\A_SPW_TOP|tx_data|mem[56][8]~q  & !\A_SPW_TOP|tx_data|rd_ptr [2]) ) ) ) # ( \A_SPW_TOP|tx_data|mem[60][8]~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [3] & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & ((\A_SPW_TOP|tx_data|mem[48][8]~q ))) # 
// (\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[52][8]~q )) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[60][8]~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [3] & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & ((\A_SPW_TOP|tx_data|mem[48][8]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr 
// [2] & (\A_SPW_TOP|tx_data|mem[52][8]~q )) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[52][8]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[56][8]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[48][8]~q ),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .datae(!\A_SPW_TOP|tx_data|mem[60][8]~q ),
        .dataf(!\A_SPW_TOP|tx_data|rd_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux9~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux9~6 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux9~6 .lut_mask = 64'h0F550F55330033FF;
defparam \A_SPW_TOP|tx_data|Mux9~6 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y13_N27
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux9~5 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux9~5_combout  = ( \A_SPW_TOP|tx_data|mem[24][8]~q  & ( \A_SPW_TOP|tx_data|rd_ptr [3] & ( (!\A_SPW_TOP|tx_data|rd_ptr [2]) # (\A_SPW_TOP|tx_data|mem[28][8]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[24][8]~q  & ( \A_SPW_TOP|tx_data|rd_ptr 
// [3] & ( (\A_SPW_TOP|tx_data|rd_ptr [2] & \A_SPW_TOP|tx_data|mem[28][8]~q ) ) ) ) # ( \A_SPW_TOP|tx_data|mem[24][8]~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [3] & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[16][8]~q )) # (\A_SPW_TOP|tx_data|rd_ptr 
// [2] & ((\A_SPW_TOP|tx_data|mem[20][8]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[24][8]~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [3] & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[16][8]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [2] & 
// ((\A_SPW_TOP|tx_data|mem[20][8]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[16][8]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[20][8]~q ),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .datad(!\A_SPW_TOP|tx_data|mem[28][8]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[24][8]~q ),
        .dataf(!\A_SPW_TOP|tx_data|rd_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux9~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux9~5 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux9~5 .lut_mask = 64'h53535353000FF0FF;
defparam \A_SPW_TOP|tx_data|Mux9~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y13_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux9~9 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux9~9_combout  = ( \A_SPW_TOP|tx_data|Mux9~6_combout  & ( \A_SPW_TOP|tx_data|Mux9~5_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [1]) # ((!\A_SPW_TOP|tx_data|rd_ptr [5] & ((\A_SPW_TOP|tx_data|Mux9~7_combout ))) # (\A_SPW_TOP|tx_data|rd_ptr 
// [5] & (\A_SPW_TOP|tx_data|Mux9~8_combout ))) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux9~6_combout  & ( \A_SPW_TOP|tx_data|Mux9~5_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & (((!\A_SPW_TOP|tx_data|rd_ptr [1]) # (\A_SPW_TOP|tx_data|Mux9~7_combout )))) # 
// (\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|Mux9~8_combout  & ((\A_SPW_TOP|tx_data|rd_ptr [1])))) ) ) ) # ( \A_SPW_TOP|tx_data|Mux9~6_combout  & ( !\A_SPW_TOP|tx_data|Mux9~5_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & 
// (((\A_SPW_TOP|tx_data|Mux9~7_combout  & \A_SPW_TOP|tx_data|rd_ptr [1])))) # (\A_SPW_TOP|tx_data|rd_ptr [5] & (((!\A_SPW_TOP|tx_data|rd_ptr [1])) # (\A_SPW_TOP|tx_data|Mux9~8_combout ))) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux9~6_combout  & ( 
// !\A_SPW_TOP|tx_data|Mux9~5_combout  & ( (\A_SPW_TOP|tx_data|rd_ptr [1] & ((!\A_SPW_TOP|tx_data|rd_ptr [5] & ((\A_SPW_TOP|tx_data|Mux9~7_combout ))) # (\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|Mux9~8_combout )))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux9~8_combout ),
        .datab(!\A_SPW_TOP|tx_data|Mux9~7_combout ),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [5]),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .datae(!\A_SPW_TOP|tx_data|Mux9~6_combout ),
        .dataf(!\A_SPW_TOP|tx_data|Mux9~5_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux9~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux9~9 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux9~9 .lut_mask = 64'h00350F35F035FF35;
defparam \A_SPW_TOP|tx_data|Mux9~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y12_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux9~20 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux9~20_combout  = ( \A_SPW_TOP|tx_data|Mux9~9_combout  & ( \A_SPW_TOP|tx_data|rd_ptr [0] & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & ((\A_SPW_TOP|tx_data|Mux9~14_combout ))) # (\A_SPW_TOP|tx_data|rd_ptr [4] & 
// (\A_SPW_TOP|tx_data|Mux9~19_combout )) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux9~9_combout  & ( \A_SPW_TOP|tx_data|rd_ptr [0] & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & ((\A_SPW_TOP|tx_data|Mux9~14_combout ))) # (\A_SPW_TOP|tx_data|rd_ptr [4] & 
// (\A_SPW_TOP|tx_data|Mux9~19_combout )) ) ) ) # ( \A_SPW_TOP|tx_data|Mux9~9_combout  & ( !\A_SPW_TOP|tx_data|rd_ptr [0] & ( (\A_SPW_TOP|tx_data|rd_ptr [4]) # (\A_SPW_TOP|tx_data|Mux9~4_combout ) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux9~9_combout  & ( 
// !\A_SPW_TOP|tx_data|rd_ptr [0] & ( (\A_SPW_TOP|tx_data|Mux9~4_combout  & !\A_SPW_TOP|tx_data|rd_ptr [4]) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux9~4_combout ),
        .datab(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .datac(!\A_SPW_TOP|tx_data|Mux9~19_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux9~14_combout ),
        .datae(!\A_SPW_TOP|tx_data|Mux9~9_combout ),
        .dataf(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux9~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux9~20 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux9~20 .lut_mask = 64'h4444777703CF03CF;
defparam \A_SPW_TOP|tx_data|Mux9~20 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y12_N20
dffeas \A_SPW_TOP|tx_data|data_out[8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|tx_data|Mux9~20_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|data_out [8]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|data_out[8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|data_out[8] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X55_Y5_N57
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tcode_rdy_trnsp~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tcode_rdy_trnsp~0_combout  = ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & ( (\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & (!\A_SPW_TOP|SPW|TX|global_counter_transfer [3] $ (!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
        .datab(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
        .datac(gnd),
        .datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|tcode_rdy_trnsp~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tcode_rdy_trnsp~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tcode_rdy_trnsp~0 .lut_mask = 64'h1144114400000000;
defparam \A_SPW_TOP|SPW|TX|tcode_rdy_trnsp~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X54_Y7_N51
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector32~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector32~0_combout  = ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q  & ( !\A_SPW_TOP|SPW|TX|tcode_rdy_trnsp~0_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|TX|tcode_rdy_trnsp~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector32~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector32~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector32~0 .lut_mask = 64'h00000000F0F0F0F0;
defparam \A_SPW_TOP|SPW|TX|Selector32~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X58_Y6_N24
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|next_state_tx~1 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|next_state_tx~1_combout  = ( \A_SPW_TOP|SPW|TX|global_counter_transfer [0] & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & ((!\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & (\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & 
// !\A_SPW_TOP|SPW|TX|tx_data_in [8])) # (\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & (!\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & \A_SPW_TOP|SPW|TX|tx_data_in [8])))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
        .datab(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
        .datac(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
        .datad(!\A_SPW_TOP|SPW|TX|tx_data_in [8]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|next_state_tx~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|next_state_tx~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|next_state_tx~1 .lut_mask = 64'h0000000020402040;
defparam \A_SPW_TOP|SPW|TX|next_state_tx~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X56_Y6_N3
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|state_tx~15 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|state_tx~15_combout  = ( \A_SPW_TOP|SPW|TX|global_counter_transfer [1] & ( (\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & (\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_c~q  & 
// !\A_SPW_TOP|SPW|TX|global_counter_transfer [3]))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
        .datab(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
        .datac(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_c~q ),
        .datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|state_tx~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_tx~15 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|state_tx~15 .lut_mask = 64'h0000000001000100;
defparam \A_SPW_TOP|SPW|TX|state_tx~15 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X58_Y6_N15
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|next_state_tx~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|next_state_tx~0_combout  = ( \A_SPW_TOP|SPW|TX|tx_data_in_0 [8] & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & (!\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & (\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & 
// \A_SPW_TOP|SPW|TX|global_counter_transfer [1]))) ) ) # ( !\A_SPW_TOP|SPW|TX|tx_data_in_0 [8] & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & (\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & (\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & 
// !\A_SPW_TOP|SPW|TX|global_counter_transfer [1]))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
        .datab(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
        .datac(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
        .datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|tx_data_in_0 [8]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|next_state_tx~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|next_state_tx~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|next_state_tx~0 .lut_mask = 64'h0200020000080008;
defparam \A_SPW_TOP|SPW|TX|next_state_tx~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X59_Y6_N9
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|state_tx~13 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|state_tx~13_combout  = ( \A_SPW_TOP|SPW|TX|process_data_0~q  & ( (\A_SPW_TOP|SPW|TX|Equal0~5_combout  & (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q  & (!\A_SPW_TOP|SPW|TX|tcode_rdy_trnsp~q  & !\A_SPW_TOP|SPW|TX|tx_data_in [8]))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|Equal0~5_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q ),
        .datac(!\A_SPW_TOP|SPW|TX|tcode_rdy_trnsp~q ),
        .datad(!\A_SPW_TOP|SPW|TX|tx_data_in [8]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|process_data_0~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|state_tx~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_tx~13 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|state_tx~13 .lut_mask = 64'h0000000010001000;
defparam \A_SPW_TOP|SPW|TX|state_tx~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X59_Y6_N21
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|state_tx~14 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|state_tx~14_combout  = (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~4_combout  & (((\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q  & !\A_SPW_TOP|SPW|TX|next_state_tx~0_combout )) # (\A_SPW_TOP|SPW|TX|state_tx~13_combout )))

        .dataa(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~4_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q ),
        .datac(!\A_SPW_TOP|SPW|TX|state_tx~13_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|next_state_tx~0_combout ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|state_tx~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_tx~14 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|state_tx~14 .lut_mask = 64'h1505150515051505;
defparam \A_SPW_TOP|SPW|TX|state_tx~14 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X58_Y6_N50
dffeas \A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0 (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|state_tx~14_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0 .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0 .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X60_Y6_N12
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|state_tx~30 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|state_tx~30_combout  = ( !\A_SPW_TOP|SPW|TX|next_state_tx~0_combout  & ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q  & ( (!\A_SPW_TOP|SPW|TX|state_tx~15_combout  & ((!\A_SPW_TOP|SPW|TX|next_state_tx~1_combout ) # 
// (!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q ))) ) ) ) # ( \A_SPW_TOP|SPW|TX|next_state_tx~0_combout  & ( !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q  & ( (!\A_SPW_TOP|SPW|TX|state_tx~15_combout  & ((!\A_SPW_TOP|SPW|TX|next_state_tx~1_combout ) # 
// (!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q ))) ) ) ) # ( !\A_SPW_TOP|SPW|TX|next_state_tx~0_combout  & ( !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q  & ( (!\A_SPW_TOP|SPW|TX|state_tx~15_combout  & ((!\A_SPW_TOP|SPW|TX|next_state_tx~1_combout ) # 
// (!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q ))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|next_state_tx~1_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q ),
        .datac(!\A_SPW_TOP|SPW|TX|state_tx~15_combout ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|SPW|TX|next_state_tx~0_combout ),
        .dataf(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|state_tx~30_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_tx~30 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|state_tx~30 .lut_mask = 64'hE0E0E0E0E0E00000;
defparam \A_SPW_TOP|SPW|TX|state_tx~30 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X54_Y6_N51
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|state_tx~29 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|state_tx~29_combout  = ( \A_SPW_TOP|SPW|TX|Equal0~4_combout  & ( ((\A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct~q  & \A_SPW_TOP|SPW|FSM|send_fct_tx~q )) # (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct_c~q ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct~q ),
        .datab(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct_c~q ),
        .datac(!\A_SPW_TOP|SPW|FSM|send_fct_tx~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|Equal0~4_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|state_tx~29_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_tx~29 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|state_tx~29 .lut_mask = 64'h0000000037373737;
defparam \A_SPW_TOP|SPW|TX|state_tx~29 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X54_Y6_N24
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|state_tx~31 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|state_tx~31_combout  = ( \A_SPW_TOP|SPW|TX|Selector62~0_combout  & ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~4_combout  ) ) # ( !\A_SPW_TOP|SPW|TX|Selector62~0_combout  & ( (\A_SPW_TOP|SPW|TX|tcode_rdy_trnsp~q  & 
// (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~4_combout  & ((!\A_SPW_TOP|SPW|TX|state_tx~30_combout ) # (\A_SPW_TOP|SPW|TX|state_tx~29_combout )))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|tcode_rdy_trnsp~q ),
        .datab(!\A_SPW_TOP|SPW|TX|state_tx~30_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|state_tx~29_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~4_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|Selector62~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|state_tx~31_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_tx~31 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|state_tx~31 .lut_mask = 64'h0045004500FF00FF;
defparam \A_SPW_TOP|SPW|TX|state_tx~31 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X54_Y6_N26
dffeas \A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(\A_SPW_TOP|SPW|TX|state_tx~31_combout ),
        .asdata(vcc),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X55_Y5_N18
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector39~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector39~0_combout  = ( \A_SPW_TOP|SPW|TX|global_counter_transfer [2] & ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_c~q  & ( (\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & ((!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]) # 
// ((!\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & \A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c~q )))) ) ) ) # ( \A_SPW_TOP|SPW|TX|global_counter_transfer [2] & ( !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_c~q  & ( 
// (!\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c~q  & \A_SPW_TOP|SPW|TX|global_counter_transfer [0])) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
        .datab(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c~q ),
        .datac(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
        .datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
        .datae(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
        .dataf(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_c~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector39~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector39~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector39~0 .lut_mask = 64'h0000020200000F02;
defparam \A_SPW_TOP|SPW|TX|Selector39~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X55_Y5_N6
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector40~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector40~0_combout  = ( \A_SPW_TOP|SPW|TX|tcode_rdy_trnsp~0_combout  & ( !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q  & ( (!\A_SPW_TOP|SPW|TX|Selector39~0_combout  & (!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q  & 
// !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct_c~q )) ) ) ) # ( !\A_SPW_TOP|SPW|TX|tcode_rdy_trnsp~0_combout  & ( !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q  & ( (!\A_SPW_TOP|SPW|TX|Selector39~0_combout  & !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct_c~q ) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|Selector39~0_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q ),
        .datac(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct_c~q ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|SPW|TX|tcode_rdy_trnsp~0_combout ),
        .dataf(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector40~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector40~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector40~0 .lut_mask = 64'hA0A0808000000000;
defparam \A_SPW_TOP|SPW|TX|Selector40~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X53_Y7_N45
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector32~1 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector32~1_combout  = ( \A_SPW_TOP|SPW|TX|tx_data_in_0 [8] & ( (!\A_SPW_TOP|SPW|TX|Selector40~0_combout ) # ((\A_SPW_TOP|tx_data|data_out [8] & \A_SPW_TOP|SPW|TX|Selector32~0_combout )) ) ) # ( !\A_SPW_TOP|SPW|TX|tx_data_in_0 [8] & ( 
// (\A_SPW_TOP|tx_data|data_out [8] & \A_SPW_TOP|SPW|TX|Selector32~0_combout ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|tx_data|data_out [8]),
        .datac(!\A_SPW_TOP|SPW|TX|Selector32~0_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|Selector40~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|tx_data_in_0 [8]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector32~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector32~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector32~1 .lut_mask = 64'h03030303FF03FF03;
defparam \A_SPW_TOP|SPW|TX|Selector32~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X53_Y7_N50
dffeas \A_SPW_TOP|SPW|TX|tx_data_in_0[8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|Selector32~1_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|tx_data_in_0 [8]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_data_in_0[8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|tx_data_in_0[8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X59_Y6_N48
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector42~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector42~0_combout  = ( \A_SPW_TOP|SPW|TX|tx_data_in_0 [8] & ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q  & ( \A_SPW_TOP|SPW|TX|tx_tcode_in~0_combout  ) ) ) # ( !\A_SPW_TOP|SPW|TX|tx_data_in_0 [8] & ( 
// \A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q  & ( ((!\A_SPW_TOP|SPW|TX|char_sent~q  & (\A_SPW_TOP|tx_data|write_tx~q  & !\A_SPW_TOP|SPW|TX|LessThan3~0_combout ))) # (\A_SPW_TOP|SPW|TX|tx_tcode_in~0_combout ) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|char_sent~q ),
        .datab(!\A_SPW_TOP|SPW|TX|tx_tcode_in~0_combout ),
        .datac(!\A_SPW_TOP|tx_data|write_tx~q ),
        .datad(!\A_SPW_TOP|SPW|TX|LessThan3~0_combout ),
        .datae(!\A_SPW_TOP|SPW|TX|tx_data_in_0 [8]),
        .dataf(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector42~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector42~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector42~0 .lut_mask = 64'h000000003B333333;
defparam \A_SPW_TOP|SPW|TX|Selector42~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X58_Y5_N3
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|state_fct_p~16 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|state_fct_p~16_combout  = (\A_SPW_TOP|SPW|TX|state_fct_p.011~q  & (\A_SPW_TOP|SPW|TX|state_fct_p.000~0_combout  & !\A_SPW_TOP|SPW|TX|char_sent~q ))

        .dataa(gnd),
        .datab(!\A_SPW_TOP|SPW|TX|state_fct_p.011~q ),
        .datac(!\A_SPW_TOP|SPW|TX|state_fct_p.000~0_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|char_sent~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|state_fct_p~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_fct_p~16 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|state_fct_p~16 .lut_mask = 64'h0300030003000300;
defparam \A_SPW_TOP|SPW|TX|state_fct_p~16 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X58_Y5_N5
dffeas \A_SPW_TOP|SPW|TX|state_fct_p.100 (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(\A_SPW_TOP|SPW|TX|state_fct_p~16_combout ),
        .asdata(vcc),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|state_fct_p.100~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_fct_p.100 .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|state_fct_p.100 .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y3_N15
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|always8~1 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|always8~1_combout  = ( \A_SPW_TOP|SPW|RX|ready_control_p_r~q  & ( \A_SPW_TOP|SPW|RX|always8~0_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),
        .dataf(!\A_SPW_TOP|SPW|RX|always8~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|always8~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|always8~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|always8~1 .lut_mask = 64'h000000000000FFFF;
defparam \A_SPW_TOP|SPW|RX|always8~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y3_N17
dffeas \A_SPW_TOP|SPW|RX|rx_got_fct (
        .clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(\A_SPW_TOP|SPW|RX|always8~1_combout ),
        .asdata(vcc),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|rx_got_fct~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_got_fct .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|rx_got_fct .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X56_Y7_N24
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|state_fct_receive.000~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|state_fct_receive.000~0_combout  = ( \A_SPW_TOP|SPW|TX|state_fct_receive.000~q  & ( (!\A_SPW_TOP|SPW|TX|state_fct_receive.011~q  & ((!\A_SPW_TOP|SPW|TX|state_fct_receive.100~q  & (!\A_SPW_TOP|SPW|TX|state_fct_receive.001~q  $ 
// (!\A_SPW_TOP|SPW|TX|state_fct_receive.010~q ))) # (\A_SPW_TOP|SPW|TX|state_fct_receive.100~q  & (!\A_SPW_TOP|SPW|TX|state_fct_receive.001~q  & !\A_SPW_TOP|SPW|TX|state_fct_receive.010~q )))) # (\A_SPW_TOP|SPW|TX|state_fct_receive.011~q  & 
// (!\A_SPW_TOP|SPW|TX|state_fct_receive.100~q  & (!\A_SPW_TOP|SPW|TX|state_fct_receive.001~q  & !\A_SPW_TOP|SPW|TX|state_fct_receive.010~q ))) ) ) # ( !\A_SPW_TOP|SPW|TX|state_fct_receive.000~q  & ( (!\A_SPW_TOP|SPW|TX|state_fct_receive.011~q  & 
// (!\A_SPW_TOP|SPW|TX|state_fct_receive.100~q  & (!\A_SPW_TOP|SPW|TX|state_fct_receive.001~q  & !\A_SPW_TOP|SPW|TX|state_fct_receive.010~q ))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|state_fct_receive.011~q ),
        .datab(!\A_SPW_TOP|SPW|TX|state_fct_receive.100~q ),
        .datac(!\A_SPW_TOP|SPW|TX|state_fct_receive.001~q ),
        .datad(!\A_SPW_TOP|SPW|TX|state_fct_receive.010~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|state_fct_receive.000~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|state_fct_receive.000~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_fct_receive.000~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|state_fct_receive.000~0 .lut_mask = 64'h8000800068806880;
defparam \A_SPW_TOP|SPW|TX|state_fct_receive.000~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X56_Y7_N48
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|state_fct_receive~13 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|state_fct_receive~13_combout  = ( \A_SPW_TOP|SPW|TX|state_fct_receive.100~q  & ( \A_SPW_TOP|SPW|RX|rx_got_fct~q  & ( (\A_SPW_TOP|SPW|TX|clear_reg~q  & \A_SPW_TOP|SPW|TX|state_fct_receive.000~0_combout ) ) ) ) # ( 
// !\A_SPW_TOP|SPW|TX|state_fct_receive.100~q  & ( \A_SPW_TOP|SPW|RX|rx_got_fct~q  & ( \A_SPW_TOP|SPW|TX|state_fct_receive.000~0_combout  ) ) ) # ( \A_SPW_TOP|SPW|TX|state_fct_receive.100~q  & ( !\A_SPW_TOP|SPW|RX|rx_got_fct~q  & ( 
// (!\A_SPW_TOP|SPW|TX|state_fct_receive.010~q  & (\A_SPW_TOP|SPW|TX|clear_reg~q  & \A_SPW_TOP|SPW|TX|state_fct_receive.000~0_combout )) ) ) ) # ( !\A_SPW_TOP|SPW|TX|state_fct_receive.100~q  & ( !\A_SPW_TOP|SPW|RX|rx_got_fct~q  & ( 
// (!\A_SPW_TOP|SPW|TX|state_fct_receive.010~q  & (\A_SPW_TOP|SPW|TX|state_fct_receive.000~0_combout  & ((\A_SPW_TOP|SPW|TX|clear_reg~q ) # (\A_SPW_TOP|SPW|TX|state_fct_receive.000~q )))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|state_fct_receive.010~q ),
        .datab(!\A_SPW_TOP|SPW|TX|state_fct_receive.000~q ),
        .datac(!\A_SPW_TOP|SPW|TX|clear_reg~q ),
        .datad(!\A_SPW_TOP|SPW|TX|state_fct_receive.000~0_combout ),
        .datae(!\A_SPW_TOP|SPW|TX|state_fct_receive.100~q ),
        .dataf(!\A_SPW_TOP|SPW|RX|rx_got_fct~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|state_fct_receive~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_fct_receive~13 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|state_fct_receive~13 .lut_mask = 64'h002A000A00FF000F;
defparam \A_SPW_TOP|SPW|TX|state_fct_receive~13 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X56_Y7_N14
dffeas \A_SPW_TOP|SPW|TX|state_fct_receive.000 (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|state_fct_receive~13_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|state_fct_receive.000~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_fct_receive.000 .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|state_fct_receive.000 .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X56_Y7_N12
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|state_fct_receive~14 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|state_fct_receive~14_combout  = ( \A_SPW_TOP|SPW|TX|state_fct_receive.000~q  & ( \A_SPW_TOP|SPW|TX|state_fct_receive.001~q  & ( (!\A_SPW_TOP|SPW|TX|state_fct_receive.011~q  & (!\A_SPW_TOP|SPW|TX|state_fct_receive.100~q  & 
// !\A_SPW_TOP|SPW|TX|state_fct_receive.010~q )) ) ) ) # ( \A_SPW_TOP|SPW|TX|state_fct_receive.000~q  & ( !\A_SPW_TOP|SPW|TX|state_fct_receive.001~q  & ( (!\A_SPW_TOP|SPW|TX|state_fct_receive.011~q  & (!\A_SPW_TOP|SPW|TX|state_fct_receive.100~q  & 
// (\A_SPW_TOP|SPW|TX|state_fct_receive.010~q  & \A_SPW_TOP|SPW|RX|rx_got_fct~q ))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|state_fct_receive.011~q ),
        .datab(!\A_SPW_TOP|SPW|TX|state_fct_receive.100~q ),
        .datac(!\A_SPW_TOP|SPW|TX|state_fct_receive.010~q ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_got_fct~q ),
        .datae(!\A_SPW_TOP|SPW|TX|state_fct_receive.000~q ),
        .dataf(!\A_SPW_TOP|SPW|TX|state_fct_receive.001~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|state_fct_receive~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_fct_receive~14 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|state_fct_receive~14 .lut_mask = 64'h0000000800008080;
defparam \A_SPW_TOP|SPW|TX|state_fct_receive~14 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X56_Y7_N26
dffeas \A_SPW_TOP|SPW|TX|state_fct_receive.010 (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|state_fct_receive~14_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|state_fct_receive.010~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_fct_receive.010 .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|state_fct_receive.010 .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X56_Y7_N30
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|state_fct_receive~11 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|state_fct_receive~11_combout  = ( !\A_SPW_TOP|SPW|TX|state_fct_receive.100~q  & ( !\A_SPW_TOP|SPW|TX|state_fct_receive.001~q  & ( (!\A_SPW_TOP|SPW|TX|state_fct_receive.010~q  & (!\A_SPW_TOP|SPW|TX|state_fct_receive.000~q  & 
// (!\A_SPW_TOP|SPW|TX|state_fct_receive.011~q  & \A_SPW_TOP|SPW|RX|rx_got_fct~q ))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|state_fct_receive.010~q ),
        .datab(!\A_SPW_TOP|SPW|TX|state_fct_receive.000~q ),
        .datac(!\A_SPW_TOP|SPW|TX|state_fct_receive.011~q ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_got_fct~q ),
        .datae(!\A_SPW_TOP|SPW|TX|state_fct_receive.100~q ),
        .dataf(!\A_SPW_TOP|SPW|TX|state_fct_receive.001~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|state_fct_receive~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_fct_receive~11 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|state_fct_receive~11 .lut_mask = 64'h0080000000000000;
defparam \A_SPW_TOP|SPW|TX|state_fct_receive~11 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X56_Y7_N50
dffeas \A_SPW_TOP|SPW|TX|state_fct_receive.001 (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|state_fct_receive~11_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|state_fct_receive.001~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_fct_receive.001 .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|state_fct_receive.001 .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X58_Y5_N15
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector11~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector11~0_combout  = ( \A_SPW_TOP|SPW|TX|fct_counter_receive [3] & ( (!\A_SPW_TOP|SPW|TX|fct_counter_receive [4] & ((\A_SPW_TOP|SPW|TX|state_fct_receive.001~q ))) # (\A_SPW_TOP|SPW|TX|fct_counter_receive [4] & 
// (!\A_SPW_TOP|SPW|TX|state_fct_receive.100~q  & !\A_SPW_TOP|SPW|TX|state_fct_receive.001~q )) ) ) # ( !\A_SPW_TOP|SPW|TX|fct_counter_receive [3] & ( (\A_SPW_TOP|SPW|TX|fct_counter_receive [4] & ((!\A_SPW_TOP|SPW|TX|state_fct_receive.100~q ) # 
// (\A_SPW_TOP|SPW|TX|state_fct_receive.001~q ))) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|SPW|TX|fct_counter_receive [4]),
        .datac(!\A_SPW_TOP|SPW|TX|state_fct_receive.100~q ),
        .datad(!\A_SPW_TOP|SPW|TX|state_fct_receive.001~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|fct_counter_receive [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector11~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector11~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector11~0 .lut_mask = 64'h3033303330CC30CC;
defparam \A_SPW_TOP|SPW|TX|Selector11~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X58_Y5_N17
dffeas \A_SPW_TOP|SPW|TX|fct_counter_receive[4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(\A_SPW_TOP|SPW|TX|Selector11~0_combout ),
        .asdata(vcc),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|fct_counter_receive [4]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|fct_counter_receive[4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|fct_counter_receive[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X58_Y5_N51
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|state_fct_p~12 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|state_fct_p~12_combout  = ( \A_SPW_TOP|SPW|TX|fct_counter_receive [3] & ( (\A_SPW_TOP|SPW|TX|fct_counter_receive [5] & (!\A_SPW_TOP|SPW|TX|state_fct_p.000~q  & (\A_SPW_TOP|SPW|TX|fct_counter_receive [4] & 
// \A_SPW_TOP|SPW|TX|state_fct_p.000~0_combout ))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|fct_counter_receive [5]),
        .datab(!\A_SPW_TOP|SPW|TX|state_fct_p.000~q ),
        .datac(!\A_SPW_TOP|SPW|TX|fct_counter_receive [4]),
        .datad(!\A_SPW_TOP|SPW|TX|state_fct_p.000~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|fct_counter_receive [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|state_fct_p~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_fct_p~12 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|state_fct_p~12 .lut_mask = 64'h0000000000040004;
defparam \A_SPW_TOP|SPW|TX|state_fct_p~12 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X58_Y5_N53
dffeas \A_SPW_TOP|SPW|TX|state_fct_p.001 (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(\A_SPW_TOP|SPW|TX|state_fct_p~12_combout ),
        .asdata(vcc),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|state_fct_p.001~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_fct_p.001 .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|state_fct_p.001 .power_up = "low";
// synopsys translate_on

// Location: FF_X58_Y5_N26
dffeas \A_SPW_TOP|SPW|TX|clear_reg (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|state_fct_p.001~q ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|clear_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|clear_reg .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|clear_reg .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X56_Y7_N54
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|state_fct_receive~15 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|state_fct_receive~15_combout  = ( !\A_SPW_TOP|SPW|TX|state_fct_receive.000~q  & ( (!\A_SPW_TOP|SPW|RX|rx_got_fct~q  & (\A_SPW_TOP|SPW|TX|clear_reg~q  & \A_SPW_TOP|SPW|TX|state_fct_receive.000~0_combout )) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|SPW|RX|rx_got_fct~q ),
        .datac(!\A_SPW_TOP|SPW|TX|clear_reg~q ),
        .datad(!\A_SPW_TOP|SPW|TX|state_fct_receive.000~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|state_fct_receive.000~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|state_fct_receive~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_fct_receive~15 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|state_fct_receive~15 .lut_mask = 64'h000C000C00000000;
defparam \A_SPW_TOP|SPW|TX|state_fct_receive~15 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X56_Y7_N56
dffeas \A_SPW_TOP|SPW|TX|state_fct_receive.011 (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(\A_SPW_TOP|SPW|TX|state_fct_receive~15_combout ),
        .asdata(vcc),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|state_fct_receive.011~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_fct_receive.011 .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|state_fct_receive.011 .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X56_Y7_N27
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|state_fct_receive~12 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|state_fct_receive~12_combout  = ( \A_SPW_TOP|SPW|TX|clear_reg~q  & ( (\A_SPW_TOP|SPW|TX|state_fct_receive.000~0_combout  & ((\A_SPW_TOP|SPW|TX|state_fct_receive.100~q ) # (\A_SPW_TOP|SPW|TX|state_fct_receive.011~q ))) ) ) # ( 
// !\A_SPW_TOP|SPW|TX|clear_reg~q  & ( (\A_SPW_TOP|SPW|TX|state_fct_receive.011~q  & \A_SPW_TOP|SPW|TX|state_fct_receive.000~0_combout ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|state_fct_receive.011~q ),
        .datab(!\A_SPW_TOP|SPW|TX|state_fct_receive.100~q ),
        .datac(!\A_SPW_TOP|SPW|TX|state_fct_receive.000~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|clear_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|state_fct_receive~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_fct_receive~12 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|state_fct_receive~12 .lut_mask = 64'h0505050507070707;
defparam \A_SPW_TOP|SPW|TX|state_fct_receive~12 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X56_Y7_N47
dffeas \A_SPW_TOP|SPW|TX|state_fct_receive.100 (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|state_fct_receive~12_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|state_fct_receive.100~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_fct_receive.100 .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|state_fct_receive.100 .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X58_Y5_N45
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector12~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector12~0_combout  = ( \A_SPW_TOP|SPW|TX|fct_counter_receive [3] & ( (!\A_SPW_TOP|SPW|TX|state_fct_receive.100~q  & !\A_SPW_TOP|SPW|TX|state_fct_receive.001~q ) ) ) # ( !\A_SPW_TOP|SPW|TX|fct_counter_receive [3] & ( 
// \A_SPW_TOP|SPW|TX|state_fct_receive.001~q  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|TX|state_fct_receive.100~q ),
        .datad(!\A_SPW_TOP|SPW|TX|state_fct_receive.001~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|fct_counter_receive [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector12~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector12~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector12~0 .lut_mask = 64'h00FF00FFF000F000;
defparam \A_SPW_TOP|SPW|TX|Selector12~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X58_Y5_N50
dffeas \A_SPW_TOP|SPW|TX|fct_counter_receive[3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|Selector12~0_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|fct_counter_receive [3]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|fct_counter_receive[3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|fct_counter_receive[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X58_Y5_N18
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector10~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector10~0_combout  = ( \A_SPW_TOP|SPW|TX|fct_counter_receive [5] & ( (!\A_SPW_TOP|SPW|TX|state_fct_receive.001~q  & (((!\A_SPW_TOP|SPW|TX|state_fct_receive.100~q )))) # (\A_SPW_TOP|SPW|TX|state_fct_receive.001~q  & 
// ((!\A_SPW_TOP|SPW|TX|fct_counter_receive [3]) # ((!\A_SPW_TOP|SPW|TX|fct_counter_receive [4])))) ) ) # ( !\A_SPW_TOP|SPW|TX|fct_counter_receive [5] & ( (\A_SPW_TOP|SPW|TX|fct_counter_receive [3] & (\A_SPW_TOP|SPW|TX|fct_counter_receive [4] & 
// \A_SPW_TOP|SPW|TX|state_fct_receive.001~q )) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|fct_counter_receive [3]),
        .datab(!\A_SPW_TOP|SPW|TX|fct_counter_receive [4]),
        .datac(!\A_SPW_TOP|SPW|TX|state_fct_receive.001~q ),
        .datad(!\A_SPW_TOP|SPW|TX|state_fct_receive.100~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|fct_counter_receive [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector10~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector10~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector10~0 .lut_mask = 64'h01010101FE0EFE0E;
defparam \A_SPW_TOP|SPW|TX|Selector10~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X58_Y5_N41
dffeas \A_SPW_TOP|SPW|TX|fct_counter_receive[5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|Selector10~0_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|fct_counter_receive [5]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|fct_counter_receive[5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|fct_counter_receive[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X58_Y5_N48
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|state_fct_p~14 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|state_fct_p~14_combout  = ( \A_SPW_TOP|SPW|TX|fct_counter_receive [4] & ( (!\A_SPW_TOP|SPW|TX|state_fct_p.000~q  & ((!\A_SPW_TOP|SPW|TX|fct_counter_receive [5]) # (!\A_SPW_TOP|SPW|TX|fct_counter_receive [3]))) ) ) # ( 
// !\A_SPW_TOP|SPW|TX|fct_counter_receive [4] & ( !\A_SPW_TOP|SPW|TX|state_fct_p.000~q  ) )

        .dataa(!\A_SPW_TOP|SPW|TX|fct_counter_receive [5]),
        .datab(!\A_SPW_TOP|SPW|TX|state_fct_p.000~q ),
        .datac(gnd),
        .datad(!\A_SPW_TOP|SPW|TX|fct_counter_receive [3]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|fct_counter_receive [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|state_fct_p~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_fct_p~14 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|state_fct_p~14 .lut_mask = 64'hCCCCCCCCCC88CC88;
defparam \A_SPW_TOP|SPW|TX|state_fct_p~14 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X58_Y5_N9
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|state_fct_p~15 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|state_fct_p~15_combout  = ( !\A_SPW_TOP|SPW|TX|state_fct_p~14_combout  & ( (\A_SPW_TOP|SPW|TX|state_fct_p.000~0_combout  & ((!\A_SPW_TOP|SPW|TX|state_fct_p.100~q ) # (!\A_SPW_TOP|SPW|TX|LessThan2~0_combout ))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|state_fct_p.100~q ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|TX|LessThan2~0_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|state_fct_p.000~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|state_fct_p~14_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|state_fct_p~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_fct_p~15 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|state_fct_p~15 .lut_mask = 64'h00FA00FA00000000;
defparam \A_SPW_TOP|SPW|TX|state_fct_p~15 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X58_Y5_N11
dffeas \A_SPW_TOP|SPW|TX|state_fct_p.000 (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(\A_SPW_TOP|SPW|TX|state_fct_p~15_combout ),
        .asdata(vcc),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|state_fct_p.000~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_fct_p.000 .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|state_fct_p.000 .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X59_Y5_N45
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|state_fct_p~13 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|state_fct_p~13_combout  = ( \A_SPW_TOP|SPW|TX|state_fct_p.010~q  & ( \A_SPW_TOP|SPW|TX|state_fct_p.001~q  & ( \A_SPW_TOP|SPW|TX|state_fct_p.000~0_combout  ) ) ) # ( !\A_SPW_TOP|SPW|TX|state_fct_p.010~q  & ( 
// \A_SPW_TOP|SPW|TX|state_fct_p.001~q  & ( \A_SPW_TOP|SPW|TX|state_fct_p.000~0_combout  ) ) ) # ( \A_SPW_TOP|SPW|TX|state_fct_p.010~q  & ( !\A_SPW_TOP|SPW|TX|state_fct_p.001~q  & ( (\A_SPW_TOP|SPW|TX|state_fct_p.000~0_combout  & 
// ((!\A_SPW_TOP|SPW|TX|char_sent~q ) # ((!\A_SPW_TOP|SPW|TX|LessThan2~0_combout  & \A_SPW_TOP|SPW|TX|state_fct_p.100~q )))) ) ) ) # ( !\A_SPW_TOP|SPW|TX|state_fct_p.010~q  & ( !\A_SPW_TOP|SPW|TX|state_fct_p.001~q  & ( (!\A_SPW_TOP|SPW|TX|LessThan2~0_combout 
//  & (\A_SPW_TOP|SPW|TX|state_fct_p.100~q  & \A_SPW_TOP|SPW|TX|state_fct_p.000~0_combout )) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|LessThan2~0_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|state_fct_p.100~q ),
        .datac(!\A_SPW_TOP|SPW|TX|char_sent~q ),
        .datad(!\A_SPW_TOP|SPW|TX|state_fct_p.000~0_combout ),
        .datae(!\A_SPW_TOP|SPW|TX|state_fct_p.010~q ),
        .dataf(!\A_SPW_TOP|SPW|TX|state_fct_p.001~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|state_fct_p~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_fct_p~13 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|state_fct_p~13 .lut_mask = 64'h002200F200FF00FF;
defparam \A_SPW_TOP|SPW|TX|state_fct_p~13 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X58_Y5_N35
dffeas \A_SPW_TOP|SPW|TX|state_fct_p.010 (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|state_fct_p~13_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|state_fct_p.010~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_fct_p.010 .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|state_fct_p.010 .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X58_Y5_N6
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|state_fct_p.000~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|state_fct_p.000~0_combout  = ( \A_SPW_TOP|SPW|TX|state_fct_p.010~q  & ( (!\A_SPW_TOP|SPW|TX|state_fct_p.100~q  & (\A_SPW_TOP|SPW|TX|state_fct_p.000~q  & (!\A_SPW_TOP|SPW|TX|state_fct_p.001~q  & !\A_SPW_TOP|SPW|TX|state_fct_p.011~q ))) ) 
// ) # ( !\A_SPW_TOP|SPW|TX|state_fct_p.010~q  & ( (!\A_SPW_TOP|SPW|TX|state_fct_p.100~q  & ((!\A_SPW_TOP|SPW|TX|state_fct_p.000~q  & (!\A_SPW_TOP|SPW|TX|state_fct_p.001~q  & !\A_SPW_TOP|SPW|TX|state_fct_p.011~q )) # (\A_SPW_TOP|SPW|TX|state_fct_p.000~q  & 
// (!\A_SPW_TOP|SPW|TX|state_fct_p.001~q  $ (!\A_SPW_TOP|SPW|TX|state_fct_p.011~q ))))) # (\A_SPW_TOP|SPW|TX|state_fct_p.100~q  & (\A_SPW_TOP|SPW|TX|state_fct_p.000~q  & (!\A_SPW_TOP|SPW|TX|state_fct_p.001~q  & !\A_SPW_TOP|SPW|TX|state_fct_p.011~q ))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|state_fct_p.100~q ),
        .datab(!\A_SPW_TOP|SPW|TX|state_fct_p.000~q ),
        .datac(!\A_SPW_TOP|SPW|TX|state_fct_p.001~q ),
        .datad(!\A_SPW_TOP|SPW|TX|state_fct_p.011~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|state_fct_p.010~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|state_fct_p.000~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_fct_p.000~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|state_fct_p.000~0 .lut_mask = 64'h9220922020002000;
defparam \A_SPW_TOP|SPW|TX|state_fct_p.000~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X59_Y5_N21
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|state_fct_p~11 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|state_fct_p~11_combout  = ( \A_SPW_TOP|SPW|TX|state_fct_p.011~q  & ( \A_SPW_TOP|SPW|TX|char_sent~q  & ( \A_SPW_TOP|SPW|TX|state_fct_p.000~0_combout  ) ) ) # ( !\A_SPW_TOP|SPW|TX|state_fct_p.011~q  & ( \A_SPW_TOP|SPW|TX|char_sent~q  & ( 
// (\A_SPW_TOP|SPW|TX|state_fct_p.000~0_combout  & \A_SPW_TOP|SPW|TX|state_fct_p.010~q ) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|state_fct_p.000~0_combout ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|TX|state_fct_p.010~q ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|SPW|TX|state_fct_p.011~q ),
        .dataf(!\A_SPW_TOP|SPW|TX|char_sent~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|state_fct_p~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_fct_p~11 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|state_fct_p~11 .lut_mask = 64'h0000000005055555;
defparam \A_SPW_TOP|SPW|TX|state_fct_p~11 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X58_Y5_N8
dffeas \A_SPW_TOP|SPW|TX|state_fct_p.011 (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|state_fct_p~11_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|state_fct_p.011~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_fct_p.011 .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|state_fct_p.011 .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X59_Y5_N30
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector17~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector17~0_combout  = ( \A_SPW_TOP|SPW|TX|state_fct_p.011~q  & ( \A_SPW_TOP|SPW|TX|state_fct_p.001~q  & ( (!\A_SPW_TOP|SPW|TX|LessThan2~0_combout  & !\A_SPW_TOP|SPW|TX|char_sent~q ) ) ) ) # ( !\A_SPW_TOP|SPW|TX|state_fct_p.011~q  & ( 
// \A_SPW_TOP|SPW|TX|state_fct_p.001~q  ) ) # ( \A_SPW_TOP|SPW|TX|state_fct_p.011~q  & ( !\A_SPW_TOP|SPW|TX|state_fct_p.001~q  & ( (!\A_SPW_TOP|SPW|TX|LessThan2~0_combout  & !\A_SPW_TOP|SPW|TX|char_sent~q ) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|LessThan2~0_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|char_sent~q ),
        .datac(gnd),
        .datad(gnd),
        .datae(!\A_SPW_TOP|SPW|TX|state_fct_p.011~q ),
        .dataf(!\A_SPW_TOP|SPW|TX|state_fct_p.001~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector17~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector17~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector17~0 .lut_mask = 64'h00008888FFFF8888;
defparam \A_SPW_TOP|SPW|TX|Selector17~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X59_Y5_N0
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector17~2 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector17~2_combout  = ( \A_SPW_TOP|SPW|TX|state_fct_p.011~q  & ( !\A_SPW_TOP|SPW|TX|char_sent~q  & ( !\A_SPW_TOP|SPW|TX|LessThan2~0_combout  ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|TX|LessThan2~0_combout ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|SPW|TX|state_fct_p.011~q ),
        .dataf(!\A_SPW_TOP|SPW|TX|char_sent~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector17~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector17~2 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector17~2 .lut_mask = 64'h0000F0F000000000;
defparam \A_SPW_TOP|SPW|TX|Selector17~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X58_Y5_N27
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector21~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector21~0_combout  = ( \A_SPW_TOP|SPW|TX|state_fct_p.001~q  & ( (\A_SPW_TOP|SPW|TX|char_sent~q  & \A_SPW_TOP|SPW|TX|state_fct_p.011~q ) ) ) # ( !\A_SPW_TOP|SPW|TX|state_fct_p.001~q  & ( (!\A_SPW_TOP|SPW|TX|state_fct_p.011~q ) # 
// (\A_SPW_TOP|SPW|TX|char_sent~q ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|char_sent~q ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|TX|state_fct_p.011~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|state_fct_p.001~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector21~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector21~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector21~0 .lut_mask = 64'hF5F5F5F505050505;
defparam \A_SPW_TOP|SPW|TX|Selector21~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X58_Y5_N42
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector22~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector22~0_combout  = ( \A_SPW_TOP|SPW|TX|state_fct_p.011~q  & ( !\A_SPW_TOP|SPW|TX|fct_counter_p [0] $ (((\A_SPW_TOP|SPW|TX|LessThan2~0_combout ) # (\A_SPW_TOP|SPW|TX|char_sent~q ))) ) ) # ( !\A_SPW_TOP|SPW|TX|state_fct_p.011~q  & ( 
// (!\A_SPW_TOP|SPW|TX|state_fct_p.001~q  & \A_SPW_TOP|SPW|TX|fct_counter_p [0]) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|char_sent~q ),
        .datab(!\A_SPW_TOP|SPW|TX|LessThan2~0_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|state_fct_p.001~q ),
        .datad(!\A_SPW_TOP|SPW|TX|fct_counter_p [0]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|state_fct_p.011~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector22~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector22~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector22~0 .lut_mask = 64'h00F000F088778877;
defparam \A_SPW_TOP|SPW|TX|Selector22~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X58_Y5_N59
dffeas \A_SPW_TOP|SPW|TX|fct_counter_p[0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|Selector22~0_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|fct_counter_p [0]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|fct_counter_p[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|fct_counter_p[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X58_Y5_N57
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector21~1 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector21~1_combout  = (!\A_SPW_TOP|SPW|TX|fct_counter_p [1] & (\A_SPW_TOP|SPW|TX|Selector17~2_combout  & ((!\A_SPW_TOP|SPW|TX|fct_counter_p [0])))) # (\A_SPW_TOP|SPW|TX|fct_counter_p [1] & (((\A_SPW_TOP|SPW|TX|Selector17~2_combout  & 
// \A_SPW_TOP|SPW|TX|fct_counter_p [0])) # (\A_SPW_TOP|SPW|TX|Selector21~0_combout )))

        .dataa(!\A_SPW_TOP|SPW|TX|Selector17~2_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|Selector21~0_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|fct_counter_p [1]),
        .datad(!\A_SPW_TOP|SPW|TX|fct_counter_p [0]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector21~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector21~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector21~1 .lut_mask = 64'h5307530753075307;
defparam \A_SPW_TOP|SPW|TX|Selector21~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X58_Y5_N56
dffeas \A_SPW_TOP|SPW|TX|fct_counter_p[1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|Selector21~1_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|fct_counter_p [1]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|fct_counter_p[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|fct_counter_p[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X58_Y5_N54
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector20~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector20~0_combout  = ( \A_SPW_TOP|SPW|TX|fct_counter_p [0] & ( (\A_SPW_TOP|SPW|TX|fct_counter_p [2] & ((\A_SPW_TOP|SPW|TX|Selector21~0_combout ) # (\A_SPW_TOP|SPW|TX|Selector17~2_combout ))) ) ) # ( !\A_SPW_TOP|SPW|TX|fct_counter_p 
// [0] & ( (!\A_SPW_TOP|SPW|TX|fct_counter_p [2] & (\A_SPW_TOP|SPW|TX|Selector17~2_combout  & ((!\A_SPW_TOP|SPW|TX|fct_counter_p [1])))) # (\A_SPW_TOP|SPW|TX|fct_counter_p [2] & (((\A_SPW_TOP|SPW|TX|Selector17~2_combout  & \A_SPW_TOP|SPW|TX|fct_counter_p 
// [1])) # (\A_SPW_TOP|SPW|TX|Selector21~0_combout ))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|Selector17~2_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|Selector21~0_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|fct_counter_p [2]),
        .datad(!\A_SPW_TOP|SPW|TX|fct_counter_p [1]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|fct_counter_p [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector20~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector20~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector20~0 .lut_mask = 64'h5307530707070707;
defparam \A_SPW_TOP|SPW|TX|Selector20~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X58_Y5_N23
dffeas \A_SPW_TOP|SPW|TX|fct_counter_p[2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|Selector20~0_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|fct_counter_p [2]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|fct_counter_p[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|fct_counter_p[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X58_Y5_N21
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|LessThan2~1 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|LessThan2~1_combout  = ( !\A_SPW_TOP|SPW|TX|fct_counter_p [0] & ( (!\A_SPW_TOP|SPW|TX|fct_counter_p [1] & !\A_SPW_TOP|SPW|TX|fct_counter_p [2]) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|TX|fct_counter_p [1]),
        .datad(!\A_SPW_TOP|SPW|TX|fct_counter_p [2]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|fct_counter_p [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|LessThan2~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|LessThan2~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|LessThan2~1 .lut_mask = 64'hF000F00000000000;
defparam \A_SPW_TOP|SPW|TX|LessThan2~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X58_Y5_N0
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector19~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector19~0_combout  = ( \A_SPW_TOP|SPW|TX|LessThan2~1_combout  & ( (!\A_SPW_TOP|SPW|TX|Selector17~0_combout  & (((\A_SPW_TOP|SPW|TX|fct_counter_p [3])))) # (\A_SPW_TOP|SPW|TX|Selector17~0_combout  & 
// ((!\A_SPW_TOP|SPW|TX|state_fct_p.011~q  & (\A_SPW_TOP|SPW|TX|fct_counter_receive [3])) # (\A_SPW_TOP|SPW|TX|state_fct_p.011~q  & ((!\A_SPW_TOP|SPW|TX|fct_counter_p [3]))))) ) ) # ( !\A_SPW_TOP|SPW|TX|LessThan2~1_combout  & ( 
// (!\A_SPW_TOP|SPW|TX|Selector17~0_combout  & (((\A_SPW_TOP|SPW|TX|fct_counter_p [3])))) # (\A_SPW_TOP|SPW|TX|Selector17~0_combout  & ((!\A_SPW_TOP|SPW|TX|state_fct_p.011~q  & (\A_SPW_TOP|SPW|TX|fct_counter_receive [3])) # 
// (\A_SPW_TOP|SPW|TX|state_fct_p.011~q  & ((\A_SPW_TOP|SPW|TX|fct_counter_p [3]))))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|Selector17~0_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|state_fct_p.011~q ),
        .datac(!\A_SPW_TOP|SPW|TX|fct_counter_receive [3]),
        .datad(!\A_SPW_TOP|SPW|TX|fct_counter_p [3]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|LessThan2~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector19~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector19~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector19~0 .lut_mask = 64'h04BF04BF15AE15AE;
defparam \A_SPW_TOP|SPW|TX|Selector19~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X58_Y5_N29
dffeas \A_SPW_TOP|SPW|TX|fct_counter_p[3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|Selector19~0_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|fct_counter_p [3]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|fct_counter_p[3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|fct_counter_p[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X58_Y5_N24
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|LessThan2~2 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|LessThan2~2_combout  = ( \A_SPW_TOP|SPW|TX|LessThan2~1_combout  & ( !\A_SPW_TOP|SPW|TX|fct_counter_p [3] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\A_SPW_TOP|SPW|TX|fct_counter_p [3]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|LessThan2~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|LessThan2~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|LessThan2~2 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|LessThan2~2 .lut_mask = 64'h00000000FF00FF00;
defparam \A_SPW_TOP|SPW|TX|LessThan2~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X58_Y5_N12
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector18~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector18~0_combout  = ( \A_SPW_TOP|SPW|TX|state_fct_p.011~q  & ( !\A_SPW_TOP|SPW|TX|fct_counter_p [4] $ (((!\A_SPW_TOP|SPW|TX|LessThan2~2_combout ) # (!\A_SPW_TOP|SPW|TX|Selector17~0_combout ))) ) ) # ( 
// !\A_SPW_TOP|SPW|TX|state_fct_p.011~q  & ( (!\A_SPW_TOP|SPW|TX|Selector17~0_combout  & ((\A_SPW_TOP|SPW|TX|fct_counter_p [4]))) # (\A_SPW_TOP|SPW|TX|Selector17~0_combout  & (\A_SPW_TOP|SPW|TX|fct_counter_receive [4])) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|LessThan2~2_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|fct_counter_receive [4]),
        .datac(!\A_SPW_TOP|SPW|TX|Selector17~0_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|fct_counter_p [4]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|state_fct_p.011~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector18~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector18~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector18~0 .lut_mask = 64'h03F303F305FA05FA;
defparam \A_SPW_TOP|SPW|TX|Selector18~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X58_Y5_N32
dffeas \A_SPW_TOP|SPW|TX|fct_counter_p[4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|Selector18~0_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|fct_counter_p [4]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|fct_counter_p[4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|fct_counter_p[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X58_Y5_N33
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector17~1 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector17~1_combout  = ( \A_SPW_TOP|SPW|TX|fct_counter_p [5] & ( \A_SPW_TOP|SPW|TX|fct_counter_receive [5] & ( (!\A_SPW_TOP|SPW|TX|LessThan2~2_combout ) # (((!\A_SPW_TOP|SPW|TX|state_fct_p.011~q ) # 
// (!\A_SPW_TOP|SPW|TX|Selector17~0_combout )) # (\A_SPW_TOP|SPW|TX|fct_counter_p [4])) ) ) ) # ( !\A_SPW_TOP|SPW|TX|fct_counter_p [5] & ( \A_SPW_TOP|SPW|TX|fct_counter_receive [5] & ( (\A_SPW_TOP|SPW|TX|Selector17~0_combout  & 
// ((!\A_SPW_TOP|SPW|TX|state_fct_p.011~q ) # ((\A_SPW_TOP|SPW|TX|LessThan2~2_combout  & !\A_SPW_TOP|SPW|TX|fct_counter_p [4])))) ) ) ) # ( \A_SPW_TOP|SPW|TX|fct_counter_p [5] & ( !\A_SPW_TOP|SPW|TX|fct_counter_receive [5] & ( 
// (!\A_SPW_TOP|SPW|TX|Selector17~0_combout ) # ((\A_SPW_TOP|SPW|TX|state_fct_p.011~q  & ((!\A_SPW_TOP|SPW|TX|LessThan2~2_combout ) # (\A_SPW_TOP|SPW|TX|fct_counter_p [4])))) ) ) ) # ( !\A_SPW_TOP|SPW|TX|fct_counter_p [5] & ( 
// !\A_SPW_TOP|SPW|TX|fct_counter_receive [5] & ( (\A_SPW_TOP|SPW|TX|LessThan2~2_combout  & (!\A_SPW_TOP|SPW|TX|fct_counter_p [4] & (\A_SPW_TOP|SPW|TX|state_fct_p.011~q  & \A_SPW_TOP|SPW|TX|Selector17~0_combout ))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|LessThan2~2_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|fct_counter_p [4]),
        .datac(!\A_SPW_TOP|SPW|TX|state_fct_p.011~q ),
        .datad(!\A_SPW_TOP|SPW|TX|Selector17~0_combout ),
        .datae(!\A_SPW_TOP|SPW|TX|fct_counter_p [5]),
        .dataf(!\A_SPW_TOP|SPW|TX|fct_counter_receive [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector17~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector17~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector17~1 .lut_mask = 64'h0004FF0B00F4FFFB;
defparam \A_SPW_TOP|SPW|TX|Selector17~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X58_Y5_N2
dffeas \A_SPW_TOP|SPW|TX|fct_counter_p[5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|Selector17~1_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|fct_counter_p [5]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|fct_counter_p[5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|fct_counter_p[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X58_Y5_N36
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|LessThan2~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|LessThan2~0_combout  = ( !\A_SPW_TOP|SPW|TX|fct_counter_p [3] & ( !\A_SPW_TOP|SPW|TX|fct_counter_p [0] & ( (!\A_SPW_TOP|SPW|TX|fct_counter_p [5] & (!\A_SPW_TOP|SPW|TX|fct_counter_p [4] & (!\A_SPW_TOP|SPW|TX|fct_counter_p [2] & 
// !\A_SPW_TOP|SPW|TX|fct_counter_p [1]))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|fct_counter_p [5]),
        .datab(!\A_SPW_TOP|SPW|TX|fct_counter_p [4]),
        .datac(!\A_SPW_TOP|SPW|TX|fct_counter_p [2]),
        .datad(!\A_SPW_TOP|SPW|TX|fct_counter_p [1]),
        .datae(!\A_SPW_TOP|SPW|TX|fct_counter_p [3]),
        .dataf(!\A_SPW_TOP|SPW|TX|fct_counter_p [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|LessThan2~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|LessThan2~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|LessThan2~0 .lut_mask = 64'h8000000000000000;
defparam \A_SPW_TOP|SPW|TX|LessThan2~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X59_Y6_N6
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector42~2 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector42~2_combout  = ( \A_SPW_TOP|SPW|TX|Equal0~6_combout  & ( (!\A_SPW_TOP|SPW|TX|Equal0~5_combout  & (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q  & (!\A_SPW_TOP|SPW|TX|LessThan2~0_combout  & \A_SPW_TOP|tx_data|write_tx~q ))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|Equal0~5_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q ),
        .datac(!\A_SPW_TOP|SPW|TX|LessThan2~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|write_tx~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|Equal0~6_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector42~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector42~2 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector42~2 .lut_mask = 64'h0000000000200020;
defparam \A_SPW_TOP|SPW|TX|Selector42~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X58_Y6_N33
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector40~2 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector40~2_combout  = (!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct_c~q  & !\A_SPW_TOP|SPW|TX|Selector39~0_combout )

        .dataa(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct_c~q ),
        .datab(gnd),
        .datac(gnd),
        .datad(!\A_SPW_TOP|SPW|TX|Selector39~0_combout ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector40~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector40~2 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector40~2 .lut_mask = 64'hAA00AA00AA00AA00;
defparam \A_SPW_TOP|SPW|TX|Selector40~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X59_Y6_N54
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector42~3 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector42~3_combout  = ( \A_SPW_TOP|SPW|TX|Selector40~2_combout  & ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q  & ( ((\A_SPW_TOP|SPW|TX|process_data_0~q  & ((!\A_SPW_TOP|SPW|TX|Selector42~1_combout ) # 
// (\A_SPW_TOP|SPW|TX|Selector42~0_combout )))) # (\A_SPW_TOP|SPW|TX|Selector42~2_combout ) ) ) ) # ( !\A_SPW_TOP|SPW|TX|Selector40~2_combout  & ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q  & ( (\A_SPW_TOP|SPW|TX|Selector42~2_combout ) # 
// (\A_SPW_TOP|SPW|TX|process_data_0~q ) ) ) ) # ( \A_SPW_TOP|SPW|TX|Selector40~2_combout  & ( !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q  & ( ((\A_SPW_TOP|SPW|TX|process_data_0~q  & \A_SPW_TOP|SPW|TX|Selector42~0_combout )) # 
// (\A_SPW_TOP|SPW|TX|Selector42~2_combout ) ) ) ) # ( !\A_SPW_TOP|SPW|TX|Selector40~2_combout  & ( !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q  & ( (\A_SPW_TOP|SPW|TX|Selector42~2_combout ) # (\A_SPW_TOP|SPW|TX|process_data_0~q ) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|process_data_0~q ),
        .datab(!\A_SPW_TOP|SPW|TX|Selector42~1_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|Selector42~0_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|Selector42~2_combout ),
        .datae(!\A_SPW_TOP|SPW|TX|Selector40~2_combout ),
        .dataf(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector42~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector42~3 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector42~3 .lut_mask = 64'h55FF05FF55FF45FF;
defparam \A_SPW_TOP|SPW|TX|Selector42~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X58_Y6_N53
dffeas \A_SPW_TOP|SPW|TX|process_data_0 (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|Selector42~3_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|process_data_0~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|process_data_0 .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|process_data_0 .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X59_Y6_N24
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|state_tx~21 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|state_tx~21_combout  = ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q  & ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q  & ( (!\A_SPW_TOP|SPW|TX|tx_data_in [8] & ((!\A_SPW_TOP|SPW|TX|process_data_0~q ) # ((!\A_SPW_TOP|SPW|TX|process_data~q 
//  & !\A_SPW_TOP|SPW|TX|tx_data_in_0 [8])))) # (\A_SPW_TOP|SPW|TX|tx_data_in [8] & (!\A_SPW_TOP|SPW|TX|process_data~q  & ((!\A_SPW_TOP|SPW|TX|tx_data_in_0 [8])))) ) ) ) # ( !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q  & ( 
// \A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q  & ( (!\A_SPW_TOP|SPW|TX|tx_data_in [8] & !\A_SPW_TOP|SPW|TX|process_data_0~q ) ) ) ) # ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q  & ( !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q  & ( 
// (!\A_SPW_TOP|SPW|TX|process_data~q  & !\A_SPW_TOP|SPW|TX|tx_data_in_0 [8]) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|tx_data_in [8]),
        .datab(!\A_SPW_TOP|SPW|TX|process_data~q ),
        .datac(!\A_SPW_TOP|SPW|TX|process_data_0~q ),
        .datad(!\A_SPW_TOP|SPW|TX|tx_data_in_0 [8]),
        .datae(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q ),
        .dataf(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|state_tx~21_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_tx~21 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|state_tx~21 .lut_mask = 64'h0000CC00A0A0ECA0;
defparam \A_SPW_TOP|SPW|TX|state_tx~21 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X58_Y6_N6
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|state_tx~22 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|state_tx~22_combout  = ( \A_SPW_TOP|SPW|TX|state_tx~21_combout  & ( ((\A_SPW_TOP|SPW|TX|state_fct_send_p~8_combout  & (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_c~q  & !\A_SPW_TOP|SPW|TX|process_data~q ))) # 
// (\A_SPW_TOP|SPW|TX|Equal0~5_combout ) ) ) # ( !\A_SPW_TOP|SPW|TX|state_tx~21_combout  & ( (\A_SPW_TOP|SPW|TX|state_fct_send_p~8_combout  & (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_c~q  & !\A_SPW_TOP|SPW|TX|process_data~q )) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|state_fct_send_p~8_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_c~q ),
        .datac(!\A_SPW_TOP|SPW|TX|Equal0~5_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|process_data~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|state_tx~21_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|state_tx~22_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_tx~22 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|state_tx~22 .lut_mask = 64'h110011001F0F1F0F;
defparam \A_SPW_TOP|SPW|TX|state_tx~22 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X56_Y6_N6
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector23~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector23~0_combout  = ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & ( (\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c~q  & (\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & 
// \A_SPW_TOP|SPW|TX|global_counter_transfer [0]))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
        .datab(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c~q ),
        .datac(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
        .datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector23~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector23~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector23~0 .lut_mask = 64'h0001000100000000;
defparam \A_SPW_TOP|SPW|TX|Selector23~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X58_Y6_N9
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|state_tx~23 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|state_tx~23_combout  = ( \A_SPW_TOP|SPW|TX|Equal0~1_combout  & ( (\A_SPW_TOP|SPW|TX|state_fct_send_p~8_combout  & (\A_SPW_TOP|SPW|TX|Selector23~0_combout  & !\A_SPW_TOP|SPW|TX|process_data~q )) ) ) # ( !\A_SPW_TOP|SPW|TX|Equal0~1_combout 
//  & ( ((\A_SPW_TOP|SPW|TX|state_fct_send_p~8_combout  & (\A_SPW_TOP|SPW|TX|Selector23~0_combout  & !\A_SPW_TOP|SPW|TX|process_data~q ))) # (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_c~q ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|state_fct_send_p~8_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_c~q ),
        .datac(!\A_SPW_TOP|SPW|TX|Selector23~0_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|process_data~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|Equal0~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|state_tx~23_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_tx~23 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|state_tx~23 .lut_mask = 64'h3733373305000500;
defparam \A_SPW_TOP|SPW|TX|state_tx~23 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X54_Y6_N15
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|state_tx~19 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|state_tx~19_combout  = ( \A_SPW_TOP|SPW|TX|tx_data_in_0 [8] & ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q  & ( (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q ) # (\A_SPW_TOP|SPW|TX|tx_data_in [8]) ) ) ) # ( 
// !\A_SPW_TOP|SPW|TX|tx_data_in_0 [8] & ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q  & ( \A_SPW_TOP|SPW|TX|tx_data_in [8] ) ) ) # ( \A_SPW_TOP|SPW|TX|tx_data_in_0 [8] & ( !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q  & ( 
// \A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q  ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|tx_data_in [8]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q ),
        .datae(!\A_SPW_TOP|SPW|TX|tx_data_in_0 [8]),
        .dataf(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|state_tx~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_tx~19 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|state_tx~19 .lut_mask = 64'h000000FF555555FF;
defparam \A_SPW_TOP|SPW|TX|state_tx~19 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X54_Y6_N48
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|state_tx~20 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|state_tx~20_combout  = ( !\A_SPW_TOP|SPW|TX|state_tx~19_combout  & ( (!\A_SPW_TOP|SPW|TX|state_fct_send_p~8_combout ) # ((!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct_c~q  & ((!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct~q ) # 
// (!\A_SPW_TOP|SPW|FSM|send_fct_tx~q )))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct~q ),
        .datab(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct_c~q ),
        .datac(!\A_SPW_TOP|SPW|FSM|send_fct_tx~q ),
        .datad(!\A_SPW_TOP|SPW|TX|state_fct_send_p~8_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|state_tx~19_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|state_tx~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_tx~20 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|state_tx~20 .lut_mask = 64'hFFC8FFC800000000;
defparam \A_SPW_TOP|SPW|TX|state_tx~20 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X54_Y6_N18
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|state_tx~24 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|state_tx~24_combout  = ( \A_SPW_TOP|SPW|TX|state_tx~23_combout  & ( \A_SPW_TOP|SPW|TX|state_tx~20_combout  & ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~4_combout  ) ) ) # ( !\A_SPW_TOP|SPW|TX|state_tx~23_combout  & ( 
// \A_SPW_TOP|SPW|TX|state_tx~20_combout  & ( (!\A_SPW_TOP|SPW|TX|tcode_rdy_trnsp~q  & (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~4_combout  & \A_SPW_TOP|SPW|TX|state_tx~22_combout )) ) ) ) # ( \A_SPW_TOP|SPW|TX|state_tx~23_combout  & ( 
// !\A_SPW_TOP|SPW|TX|state_tx~20_combout  & ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~4_combout  ) ) ) # ( !\A_SPW_TOP|SPW|TX|state_tx~23_combout  & ( !\A_SPW_TOP|SPW|TX|state_tx~20_combout  & ( (!\A_SPW_TOP|SPW|TX|tcode_rdy_trnsp~q  & 
// (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~4_combout  & ((\A_SPW_TOP|SPW|TX|state_tx~22_combout ) # (\A_SPW_TOP|SPW|TX|Equal0~4_combout )))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|tcode_rdy_trnsp~q ),
        .datab(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~4_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|Equal0~4_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|state_tx~22_combout ),
        .datae(!\A_SPW_TOP|SPW|TX|state_tx~23_combout ),
        .dataf(!\A_SPW_TOP|SPW|TX|state_tx~20_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|state_tx~24_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_tx~24 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|state_tx~24 .lut_mask = 64'h0222333300223333;
defparam \A_SPW_TOP|SPW|TX|state_tx~24 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X54_Y6_N20
dffeas \A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_c (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(\A_SPW_TOP|SPW|TX|state_tx~24_combout ),
        .asdata(vcc),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_c~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_c .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_c .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X55_Y5_N54
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector51~1 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector51~1_combout  = ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_c~q  & ( (\u0|timecode_tx_enable|data_out~q  & ((!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]) # ((!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]) # 
// (\A_SPW_TOP|SPW|TX|global_counter_transfer [3])))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
        .datab(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
        .datac(!\u0|timecode_tx_enable|data_out~q ),
        .datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_c~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector51~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector51~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector51~1 .lut_mask = 64'h000000000F0B0F0B;
defparam \A_SPW_TOP|SPW|TX|Selector51~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X55_Y5_N51
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector51~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector51~0_combout  = ( \A_SPW_TOP|SPW|TX|global_counter_transfer [2] & ( \A_SPW_TOP|SPW|TX|global_counter_transfer [1] & ( \u0|timecode_tx_enable|data_out~q  ) ) ) # ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & ( 
// \A_SPW_TOP|SPW|TX|global_counter_transfer [1] & ( (\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & \u0|timecode_tx_enable|data_out~q ) ) ) ) # ( \A_SPW_TOP|SPW|TX|global_counter_transfer [2] & ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & ( 
// (\u0|timecode_tx_enable|data_out~q  & ((\A_SPW_TOP|SPW|TX|global_counter_transfer [3]) # (\A_SPW_TOP|SPW|TX|global_counter_transfer [0]))) ) ) ) # ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & ( 
// (\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & \u0|timecode_tx_enable|data_out~q ) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
        .datad(!\u0|timecode_tx_enable|data_out~q ),
        .datae(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
        .dataf(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector51~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector51~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector51~0 .lut_mask = 64'h000F005F000F00FF;
defparam \A_SPW_TOP|SPW|TX|Selector51~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X60_Y6_N33
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~5 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~5_combout  = ( !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q  & ( !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~5 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~5 .lut_mask = 64'hF0F0F0F000000000;
defparam \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~5 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X55_Y5_N15
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector50~1 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector50~1_combout  = ( \A_SPW_TOP|SPW|TX|global_counter_transfer [0] & ( !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct_c~q  & ( (!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c~q  & ((!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_c~q ) # 
// ((!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]) # (\A_SPW_TOP|SPW|TX|global_counter_transfer [3])))) ) ) ) # ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & ( !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct_c~q  & ( 
// !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c~q  ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_c~q ),
        .datab(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c~q ),
        .datac(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
        .datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
        .datae(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
        .dataf(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct_c~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector50~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector50~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector50~1 .lut_mask = 64'hCCCCCC8C00000000;
defparam \A_SPW_TOP|SPW|TX|Selector50~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X55_Y6_N30
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector51~2 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector51~2_combout  = ( \A_SPW_TOP|SPW|TX|tcode_rdy_trnsp~q  & ( \A_SPW_TOP|SPW|TX|Selector50~1_combout  & ( ((!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~5_combout  & ((\A_SPW_TOP|SPW|TX|Selector51~0_combout ) # 
// (\A_SPW_TOP|SPW|TX|tcode_rdy_trnsp~0_combout )))) # (\A_SPW_TOP|SPW|TX|Selector51~1_combout ) ) ) ) # ( !\A_SPW_TOP|SPW|TX|tcode_rdy_trnsp~q  & ( \A_SPW_TOP|SPW|TX|Selector50~1_combout  & ( ((!\A_SPW_TOP|SPW|TX|tcode_rdy_trnsp~0_combout  & 
// (\A_SPW_TOP|SPW|TX|Selector51~0_combout  & !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~5_combout ))) # (\A_SPW_TOP|SPW|TX|Selector51~1_combout ) ) ) ) # ( \A_SPW_TOP|SPW|TX|tcode_rdy_trnsp~q  & ( !\A_SPW_TOP|SPW|TX|Selector50~1_combout  ) ) # ( 
// !\A_SPW_TOP|SPW|TX|tcode_rdy_trnsp~q  & ( !\A_SPW_TOP|SPW|TX|Selector50~1_combout  & ( ((!\A_SPW_TOP|SPW|TX|tcode_rdy_trnsp~0_combout  & (\A_SPW_TOP|SPW|TX|Selector51~0_combout  & !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~5_combout ))) # 
// (\A_SPW_TOP|SPW|TX|Selector51~1_combout ) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|Selector51~1_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|tcode_rdy_trnsp~0_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|Selector51~0_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~5_combout ),
        .datae(!\A_SPW_TOP|SPW|TX|tcode_rdy_trnsp~q ),
        .dataf(!\A_SPW_TOP|SPW|TX|Selector50~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector51~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector51~2 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector51~2 .lut_mask = 64'h5D55FFFF5D557F55;
defparam \A_SPW_TOP|SPW|TX|Selector51~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X54_Y6_N11
dffeas \A_SPW_TOP|SPW|TX|tcode_rdy_trnsp (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|Selector51~2_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|tcode_rdy_trnsp~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tcode_rdy_trnsp .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|tcode_rdy_trnsp .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X54_Y6_N39
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|state_tx~27 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|state_tx~27_combout  = ( \A_SPW_TOP|SPW|TX|tcode_rdy_trnsp~q  & ( (\A_SPW_TOP|SPW|TX|Equal0~4_combout  & \A_SPW_TOP|SPW|FSM|send_fct_tx~q ) ) ) # ( !\A_SPW_TOP|SPW|TX|tcode_rdy_trnsp~q  & ( (\A_SPW_TOP|SPW|TX|Equal0~4_combout  & 
// (\A_SPW_TOP|SPW|FSM|send_fct_tx~q  & \A_SPW_TOP|SPW|TX|state_fct_send_p~8_combout )) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|Equal0~4_combout ),
        .datab(!\A_SPW_TOP|SPW|FSM|send_fct_tx~q ),
        .datac(!\A_SPW_TOP|SPW|TX|state_fct_send_p~8_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|tcode_rdy_trnsp~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|state_tx~27_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_tx~27 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|state_tx~27 .lut_mask = 64'h0101010111111111;
defparam \A_SPW_TOP|SPW|TX|state_tx~27 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X53_Y6_N42
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|state_tx~28 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|state_tx~28_combout  = ( \A_SPW_TOP|SPW|TX|state_tx~25_combout  & ( (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~4_combout  & (((!\A_SPW_TOP|SPW|TX|state_tx~27_combout  & \A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct~q )) # 
// (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null~q ))) ) ) # ( !\A_SPW_TOP|SPW|TX|state_tx~25_combout  & ( (!\A_SPW_TOP|SPW|TX|state_tx~27_combout  & (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~4_combout  & \A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct~q )) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|state_tx~27_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null~q ),
        .datac(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~4_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|state_tx~25_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|state_tx~28_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_tx~28 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|state_tx~28 .lut_mask = 64'h000A000A030B030B;
defparam \A_SPW_TOP|SPW|TX|state_tx~28 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X53_Y6_N47
dffeas \A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|state_tx~28_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X58_Y6_N27
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~1 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~1_combout  = (!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct~q  & !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct_c~q )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct~q ),
        .datad(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct_c~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~1 .lut_mask = 64'hF000F000F000F000;
defparam \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y6_N30
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|LessThan6~1 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|LessThan6~1_combout  = ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & ((!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]) # (!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]))) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
        .datac(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
        .datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|LessThan6~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|LessThan6~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|LessThan6~1 .lut_mask = 64'hFC00FC0000000000;
defparam \A_SPW_TOP|SPW|TX|LessThan6~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X53_Y6_N15
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector72~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector72~0_combout  = ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q  & ( (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~q  & (!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null~q  & ((!\A_SPW_TOP|SPW|TX|LessThan6~1_combout ) # 
// (\A_SPW_TOP|SPW|TX|tx_data_in [8])))) ) ) # ( !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q  & ( (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~q  & !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null~q ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|LessThan6~1_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~q ),
        .datac(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null~q ),
        .datad(!\A_SPW_TOP|SPW|TX|tx_data_in [8]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector72~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector72~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector72~0 .lut_mask = 64'h3030303020302030;
defparam \A_SPW_TOP|SPW|TX|Selector72~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X58_Y7_N18
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Equal0~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Equal0~0_combout  = ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & (!\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & !\A_SPW_TOP|SPW|TX|global_counter_transfer [0])) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
        .datac(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
        .datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Equal0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Equal0~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Equal0~0 .lut_mask = 64'hC000C00000000000;
defparam \A_SPW_TOP|SPW|TX|Equal0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X58_Y6_N39
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector72~1 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector72~1_combout  = ( \A_SPW_TOP|SPW|TX|fct_sent~q  & ( (!\A_SPW_TOP|SPW|TX|Selector72~0_combout ) # ((!\A_SPW_TOP|SPW|TX|state_fct_send_p~8_combout  & (!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~1_combout  & 
// \A_SPW_TOP|SPW|TX|Equal0~0_combout ))) ) ) # ( !\A_SPW_TOP|SPW|TX|fct_sent~q  & ( (!\A_SPW_TOP|SPW|TX|state_fct_send_p~8_combout  & (!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~1_combout  & \A_SPW_TOP|SPW|TX|Equal0~0_combout )) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|state_fct_send_p~8_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~1_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|Selector72~0_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|Equal0~0_combout ),
        .datae(!\A_SPW_TOP|SPW|TX|fct_sent~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector72~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector72~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector72~1 .lut_mask = 64'h0088F0F80088F0F8;
defparam \A_SPW_TOP|SPW|TX|Selector72~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X58_Y6_N38
dffeas \A_SPW_TOP|SPW|TX|fct_sent (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|Selector72~1_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|fct_sent~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|fct_sent .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|fct_sent .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X56_Y4_N36
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|state_fct_send_p~12 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|state_fct_send_p~12_combout  = ( \A_SPW_TOP|rx_data|open_slot_fct~q  & ( \A_SPW_TOP|SPW|TX|state_fct_send_p.001~0_combout  & ( ((\A_SPW_TOP|SPW|TX|state_fct_send_p~9_combout ) # (\A_SPW_TOP|SPW|TX|fct_sent~q )) # 
// (\A_SPW_TOP|SPW|TX|state_fct_send_p.000~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|open_slot_fct~q  & ( \A_SPW_TOP|SPW|TX|state_fct_send_p.001~0_combout  & ( (!\A_SPW_TOP|SPW|TX|state_fct_send_p.000~q  & (((\A_SPW_TOP|SPW|TX|state_fct_send_p~9_combout ) # 
// (\A_SPW_TOP|SPW|TX|fct_sent~q )))) # (\A_SPW_TOP|SPW|TX|state_fct_send_p.000~q  & (!\A_SPW_TOP|SPW|TX|Selector2~0_combout )) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|Selector2~0_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|state_fct_send_p.000~q ),
        .datac(!\A_SPW_TOP|SPW|TX|fct_sent~q ),
        .datad(!\A_SPW_TOP|SPW|TX|state_fct_send_p~9_combout ),
        .datae(!\A_SPW_TOP|rx_data|open_slot_fct~q ),
        .dataf(!\A_SPW_TOP|SPW|TX|state_fct_send_p.001~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|state_fct_send_p~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_fct_send_p~12 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|state_fct_send_p~12 .lut_mask = 64'h000000002EEE3FFF;
defparam \A_SPW_TOP|SPW|TX|state_fct_send_p~12 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X56_Y4_N38
dffeas \A_SPW_TOP|SPW|TX|state_fct_send_p.001 (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(\A_SPW_TOP|SPW|TX|state_fct_send_p~12_combout ),
        .asdata(vcc),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|state_fct_send_p.001~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_fct_send_p.001 .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|state_fct_send_p.001 .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X56_Y4_N24
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|state_fct_send_p.001~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|state_fct_send_p.001~0_combout  = ( \A_SPW_TOP|SPW|TX|state_fct_send_p.000~q  & ( (!\A_SPW_TOP|SPW|TX|state_fct_send_p.010~q  & \A_SPW_TOP|SPW|TX|state_fct_send_p.001~q ) ) ) # ( !\A_SPW_TOP|SPW|TX|state_fct_send_p.000~q  & ( 
// !\A_SPW_TOP|SPW|TX|state_fct_send_p.010~q  $ (\A_SPW_TOP|SPW|TX|state_fct_send_p.001~q ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|state_fct_send_p.010~q ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|TX|state_fct_send_p.001~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|state_fct_send_p.000~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|state_fct_send_p.001~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_fct_send_p.001~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|state_fct_send_p.001~0 .lut_mask = 64'hA5A5A5A50A0A0A0A;
defparam \A_SPW_TOP|SPW|TX|state_fct_send_p.001~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X56_Y4_N3
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|state_fct_send_p~11 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|state_fct_send_p~11_combout  = ( \A_SPW_TOP|SPW|TX|state_fct_send_p.001~0_combout  & ( (\A_SPW_TOP|SPW|TX|fct_sent~q  & !\A_SPW_TOP|SPW|TX|state_fct_send_p.000~q ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|fct_sent~q ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|TX|state_fct_send_p.000~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|state_fct_send_p.001~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|state_fct_send_p~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_fct_send_p~11 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|state_fct_send_p~11 .lut_mask = 64'h0000000050505050;
defparam \A_SPW_TOP|SPW|TX|state_fct_send_p~11 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X56_Y4_N5
dffeas \A_SPW_TOP|SPW|TX|state_fct_send_p.010 (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(\A_SPW_TOP|SPW|TX|state_fct_send_p~11_combout ),
        .asdata(vcc),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|state_fct_send_p.010~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_fct_send_p.010 .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|state_fct_send_p.010 .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X56_Y4_N30
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|state_fct_send_p~9 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|state_fct_send_p~9_combout  = ( \A_SPW_TOP|SPW|TX|state_fct_send_p~8_combout  & ( \A_SPW_TOP|SPW|TX|state_fct_send_p.010~q  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\A_SPW_TOP|SPW|TX|state_fct_send_p.010~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|state_fct_send_p~8_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|state_fct_send_p~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_fct_send_p~9 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|state_fct_send_p~9 .lut_mask = 64'h0000000000FF00FF;
defparam \A_SPW_TOP|SPW|TX|state_fct_send_p~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X56_Y4_N42
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|state_fct_send_p~10 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|state_fct_send_p~10_combout  = ( \A_SPW_TOP|rx_data|open_slot_fct~q  & ( \A_SPW_TOP|SPW|TX|state_fct_send_p.001~0_combout  & ( ((!\A_SPW_TOP|SPW|TX|fct_sent~q  & \A_SPW_TOP|SPW|TX|state_fct_send_p~9_combout )) # 
// (\A_SPW_TOP|SPW|TX|state_fct_send_p.000~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|open_slot_fct~q  & ( \A_SPW_TOP|SPW|TX|state_fct_send_p.001~0_combout  & ( (!\A_SPW_TOP|SPW|TX|fct_sent~q  & (((\A_SPW_TOP|SPW|TX|state_fct_send_p.000~q  & 
// !\A_SPW_TOP|SPW|TX|Selector2~0_combout )) # (\A_SPW_TOP|SPW|TX|state_fct_send_p~9_combout ))) # (\A_SPW_TOP|SPW|TX|fct_sent~q  & (\A_SPW_TOP|SPW|TX|state_fct_send_p.000~q  & (!\A_SPW_TOP|SPW|TX|Selector2~0_combout ))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|fct_sent~q ),
        .datab(!\A_SPW_TOP|SPW|TX|state_fct_send_p.000~q ),
        .datac(!\A_SPW_TOP|SPW|TX|Selector2~0_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|state_fct_send_p~9_combout ),
        .datae(!\A_SPW_TOP|rx_data|open_slot_fct~q ),
        .dataf(!\A_SPW_TOP|SPW|TX|state_fct_send_p.001~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|state_fct_send_p~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_fct_send_p~10 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|state_fct_send_p~10 .lut_mask = 64'h0000000030BA33BB;
defparam \A_SPW_TOP|SPW|TX|state_fct_send_p~10 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X56_Y4_N41
dffeas \A_SPW_TOP|SPW|TX|state_fct_send_p.000 (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|state_fct_send_p~10_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|state_fct_send_p.000~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_fct_send_p.000 .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|state_fct_send_p.000 .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X56_Y4_N33
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector2~1 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector2~1_combout  = ( \A_SPW_TOP|SPW|TX|fct_flag [0] & ( (\A_SPW_TOP|SPW|TX|fct_flag [2] & (\A_SPW_TOP|SPW|TX|state_fct_send_p.000~q  & (\A_SPW_TOP|SPW|TX|fct_flag [1] & !\A_SPW_TOP|rx_data|open_slot_fct~q ))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|fct_flag [2]),
        .datab(!\A_SPW_TOP|SPW|TX|state_fct_send_p.000~q ),
        .datac(!\A_SPW_TOP|SPW|TX|fct_flag [1]),
        .datad(!\A_SPW_TOP|rx_data|open_slot_fct~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|fct_flag [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector2~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector2~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector2~1 .lut_mask = 64'h0000000001000100;
defparam \A_SPW_TOP|SPW|TX|Selector2~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X56_Y4_N35
dffeas \A_SPW_TOP|SPW|TX|clear_reg_fct_flag (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(\A_SPW_TOP|SPW|TX|Selector2~1_combout ),
        .asdata(vcc),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|clear_reg_fct_flag~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|clear_reg_fct_flag .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|clear_reg_fct_flag .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X56_Y4_N9
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|fct_flag~1 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|fct_flag~1_combout  = ( \A_SPW_TOP|rx_data|open_slot_fct~q  & ( (!\A_SPW_TOP|SPW|TX|clear_reg_fct_flag~q  & ((!\A_SPW_TOP|SPW|TX|fct_flag [1] & ((\A_SPW_TOP|SPW|TX|fct_flag [0]))) # (\A_SPW_TOP|SPW|TX|fct_flag [1] & 
// ((!\A_SPW_TOP|SPW|TX|fct_flag [0]) # (\A_SPW_TOP|SPW|TX|fct_flag [2]))))) ) ) # ( !\A_SPW_TOP|rx_data|open_slot_fct~q  & ( (!\A_SPW_TOP|SPW|TX|clear_reg_fct_flag~q  & \A_SPW_TOP|SPW|TX|fct_flag [1]) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|clear_reg_fct_flag~q ),
        .datab(!\A_SPW_TOP|SPW|TX|fct_flag [2]),
        .datac(!\A_SPW_TOP|SPW|TX|fct_flag [1]),
        .datad(!\A_SPW_TOP|SPW|TX|fct_flag [0]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|open_slot_fct~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|fct_flag~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|fct_flag~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|fct_flag~1 .lut_mask = 64'h0A0A0A0A0AA20AA2;
defparam \A_SPW_TOP|SPW|TX|fct_flag~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X56_Y4_N8
dffeas \A_SPW_TOP|SPW|TX|fct_flag[1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|fct_flag~1_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(!\A_SPW_TOP|SPW|TX|state_fct_send.001~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|fct_flag [1]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|fct_flag[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|fct_flag[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X56_Y4_N18
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector2~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector2~0_combout  = ( \A_SPW_TOP|SPW|TX|fct_flag [0] & ( (\A_SPW_TOP|SPW|TX|fct_flag [1] & \A_SPW_TOP|SPW|TX|fct_flag [2]) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|SPW|TX|fct_flag [1]),
        .datac(gnd),
        .datad(!\A_SPW_TOP|SPW|TX|fct_flag [2]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|fct_flag [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector2~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector2~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector2~0 .lut_mask = 64'h0000000000330033;
defparam \A_SPW_TOP|SPW|TX|Selector2~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X56_Y4_N27
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector6~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector6~0_combout  = ( \A_SPW_TOP|SPW|TX|fct_sent~q  & ( (!\A_SPW_TOP|SPW|TX|state_fct_send_p.010~q  & (\A_SPW_TOP|SPW|TX|fct_flag_p [0] & ((!\A_SPW_TOP|SPW|TX|fct_flag_p [2]) # (!\A_SPW_TOP|SPW|TX|fct_flag_p [1])))) ) ) # ( 
// !\A_SPW_TOP|SPW|TX|fct_sent~q  & ( (!\A_SPW_TOP|SPW|TX|state_fct_send_p.010~q  & !\A_SPW_TOP|SPW|TX|fct_flag_p [0]) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|state_fct_send_p.010~q ),
        .datab(!\A_SPW_TOP|SPW|TX|fct_flag_p [0]),
        .datac(!\A_SPW_TOP|SPW|TX|fct_flag_p [2]),
        .datad(!\A_SPW_TOP|SPW|TX|fct_flag_p [1]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|fct_sent~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector6~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector6~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector6~0 .lut_mask = 64'h8888888822202220;
defparam \A_SPW_TOP|SPW|TX|Selector6~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X56_Y4_N12
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector6~1 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector6~1_combout  = ( \A_SPW_TOP|SPW|TX|state_fct_send_p.010~q  & ( \A_SPW_TOP|SPW|TX|fct_flag_p [0] & ( (!\A_SPW_TOP|SPW|TX|state_fct_send_p.000~q  & (!\A_SPW_TOP|SPW|TX|Selector6~0_combout )) # 
// (\A_SPW_TOP|SPW|TX|state_fct_send_p.000~q  & (((!\A_SPW_TOP|SPW|TX|Selector2~0_combout ) # (\A_SPW_TOP|rx_data|open_slot_fct~q )))) ) ) ) # ( !\A_SPW_TOP|SPW|TX|state_fct_send_p.010~q  & ( \A_SPW_TOP|SPW|TX|fct_flag_p [0] & ( 
// (!\A_SPW_TOP|SPW|TX|state_fct_send_p.000~q  & (!\A_SPW_TOP|SPW|TX|Selector6~0_combout )) # (\A_SPW_TOP|SPW|TX|state_fct_send_p.000~q  & (((!\A_SPW_TOP|SPW|TX|Selector2~0_combout ) # (\A_SPW_TOP|rx_data|open_slot_fct~q )))) ) ) ) # ( 
// \A_SPW_TOP|SPW|TX|state_fct_send_p.010~q  & ( !\A_SPW_TOP|SPW|TX|fct_flag_p [0] & ( (\A_SPW_TOP|SPW|TX|state_fct_send_p.000~q  & ((!\A_SPW_TOP|SPW|TX|Selector2~0_combout ) # (\A_SPW_TOP|rx_data|open_slot_fct~q ))) ) ) ) # ( 
// !\A_SPW_TOP|SPW|TX|state_fct_send_p.010~q  & ( !\A_SPW_TOP|SPW|TX|fct_flag_p [0] & ( (!\A_SPW_TOP|SPW|TX|state_fct_send_p.000~q  & (!\A_SPW_TOP|SPW|TX|Selector6~0_combout )) # (\A_SPW_TOP|SPW|TX|state_fct_send_p.000~q  & 
// (((!\A_SPW_TOP|SPW|TX|Selector2~0_combout ) # (\A_SPW_TOP|rx_data|open_slot_fct~q )))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|Selector6~0_combout ),
        .datab(!\A_SPW_TOP|rx_data|open_slot_fct~q ),
        .datac(!\A_SPW_TOP|SPW|TX|Selector2~0_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|state_fct_send_p.000~q ),
        .datae(!\A_SPW_TOP|SPW|TX|state_fct_send_p.010~q ),
        .dataf(!\A_SPW_TOP|SPW|TX|fct_flag_p [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector6~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector6~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector6~1 .lut_mask = 64'hAAF300F3AAF3AAF3;
defparam \A_SPW_TOP|SPW|TX|Selector6~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X56_Y4_N17
dffeas \A_SPW_TOP|SPW|TX|fct_flag_p[0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|Selector6~1_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|fct_flag_p [0]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|fct_flag_p[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|fct_flag_p[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X56_Y4_N51
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector5~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector5~0_combout  = ( !\A_SPW_TOP|SPW|TX|fct_flag_p [1] & ( \A_SPW_TOP|SPW|TX|fct_flag_p [2] & ( (!\A_SPW_TOP|SPW|TX|state_fct_send_p.000~q  & ((!\A_SPW_TOP|SPW|TX|fct_sent~q ) # ((!\A_SPW_TOP|SPW|TX|fct_flag_p [0]) # 
// (\A_SPW_TOP|SPW|TX|state_fct_send_p.010~q )))) ) ) ) # ( \A_SPW_TOP|SPW|TX|fct_flag_p [1] & ( !\A_SPW_TOP|SPW|TX|fct_flag_p [2] & ( (\A_SPW_TOP|SPW|TX|fct_sent~q  & (!\A_SPW_TOP|SPW|TX|state_fct_send_p.000~q  & (\A_SPW_TOP|SPW|TX|fct_flag_p [0] & 
// !\A_SPW_TOP|SPW|TX|state_fct_send_p.010~q ))) ) ) ) # ( !\A_SPW_TOP|SPW|TX|fct_flag_p [1] & ( !\A_SPW_TOP|SPW|TX|fct_flag_p [2] & ( (!\A_SPW_TOP|SPW|TX|state_fct_send_p.000~q  & ((!\A_SPW_TOP|SPW|TX|fct_sent~q ) # ((!\A_SPW_TOP|SPW|TX|fct_flag_p [0]) # 
// (\A_SPW_TOP|SPW|TX|state_fct_send_p.010~q )))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|fct_sent~q ),
        .datab(!\A_SPW_TOP|SPW|TX|state_fct_send_p.000~q ),
        .datac(!\A_SPW_TOP|SPW|TX|fct_flag_p [0]),
        .datad(!\A_SPW_TOP|SPW|TX|state_fct_send_p.010~q ),
        .datae(!\A_SPW_TOP|SPW|TX|fct_flag_p [1]),
        .dataf(!\A_SPW_TOP|SPW|TX|fct_flag_p [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector5~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector5~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector5~0 .lut_mask = 64'hC8CC0400C8CC0000;
defparam \A_SPW_TOP|SPW|TX|Selector5~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X56_Y4_N57
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector5~1 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector5~1_combout  = ( !\A_SPW_TOP|SPW|TX|Selector5~0_combout  & ( (!\A_SPW_TOP|SPW|TX|Selector2~0_combout ) # ((!\A_SPW_TOP|SPW|TX|state_fct_send_p.000~q ) # (\A_SPW_TOP|rx_data|open_slot_fct~q )) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|Selector2~0_combout ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|TX|state_fct_send_p.000~q ),
        .datad(!\A_SPW_TOP|rx_data|open_slot_fct~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|Selector5~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector5~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector5~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector5~1 .lut_mask = 64'hFAFFFAFF00000000;
defparam \A_SPW_TOP|SPW|TX|Selector5~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X56_Y4_N59
dffeas \A_SPW_TOP|SPW|TX|fct_flag_p[1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(\A_SPW_TOP|SPW|TX|Selector5~1_combout ),
        .asdata(vcc),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|fct_flag_p [1]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|fct_flag_p[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|fct_flag_p[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X56_Y4_N0
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector4~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector4~0_combout  = ( \A_SPW_TOP|SPW|TX|fct_flag_p [0] & ( (\A_SPW_TOP|SPW|TX|fct_sent~q  & (!\A_SPW_TOP|SPW|TX|state_fct_send_p.010~q  & \A_SPW_TOP|SPW|TX|fct_flag_p [1])) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|fct_sent~q ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|TX|state_fct_send_p.010~q ),
        .datad(!\A_SPW_TOP|SPW|TX|fct_flag_p [1]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|fct_flag_p [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector4~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector4~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector4~0 .lut_mask = 64'h0000000000500050;
defparam \A_SPW_TOP|SPW|TX|Selector4~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X56_Y4_N54
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector4~1 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector4~1_combout  = ( \A_SPW_TOP|SPW|TX|fct_flag_p [2] & ( (!\A_SPW_TOP|SPW|TX|Selector2~0_combout ) # ((!\A_SPW_TOP|SPW|TX|state_fct_send_p.000~q ) # (\A_SPW_TOP|rx_data|open_slot_fct~q )) ) ) # ( !\A_SPW_TOP|SPW|TX|fct_flag_p [2] & 
// ( (!\A_SPW_TOP|SPW|TX|state_fct_send_p.000~q  & (((\A_SPW_TOP|SPW|TX|Selector4~0_combout )))) # (\A_SPW_TOP|SPW|TX|state_fct_send_p.000~q  & ((!\A_SPW_TOP|SPW|TX|Selector2~0_combout ) # ((\A_SPW_TOP|rx_data|open_slot_fct~q )))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|Selector2~0_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|state_fct_send_p.000~q ),
        .datac(!\A_SPW_TOP|SPW|TX|Selector4~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|open_slot_fct~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|fct_flag_p [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector4~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector4~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector4~1 .lut_mask = 64'h2E3F2E3FEEFFEEFF;
defparam \A_SPW_TOP|SPW|TX|Selector4~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X56_Y4_N50
dffeas \A_SPW_TOP|SPW|TX|fct_flag_p[2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|Selector4~1_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|fct_flag_p [2]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|fct_flag_p[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|fct_flag_p[2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X55_Y4_N33
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|state_fct_send_p~8 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|state_fct_send_p~8_combout  = ( \A_SPW_TOP|SPW|TX|fct_flag_p [0] & ( (\A_SPW_TOP|SPW|TX|fct_flag_p [2] & \A_SPW_TOP|SPW|TX|fct_flag_p [1]) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|SPW|TX|fct_flag_p [2]),
        .datac(!\A_SPW_TOP|SPW|TX|fct_flag_p [1]),
        .datad(gnd),
        .datae(!\A_SPW_TOP|SPW|TX|fct_flag_p [0]),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|state_fct_send_p~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_fct_send_p~8 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|state_fct_send_p~8 .lut_mask = 64'h0000030300000303;
defparam \A_SPW_TOP|SPW|TX|state_fct_send_p~8 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X58_Y6_N0
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|state_tx~32 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|state_tx~32_combout  = ( !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct_c~q  & ( (!\A_SPW_TOP|SPW|TX|state_fct_send_p~8_combout  & (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~4_combout  & (((\A_SPW_TOP|SPW|TX|state_tx~15_combout  & 
// !\A_SPW_TOP|SPW|TX|tcode_rdy_trnsp~q )) # (\A_SPW_TOP|SPW|TX|Selector23~0_combout )))) ) ) # ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct_c~q  & ( (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~4_combout  & ((!\A_SPW_TOP|SPW|TX|Equal0~4_combout ) # 
// ((!\A_SPW_TOP|SPW|TX|state_fct_send_p~8_combout  & ((!\A_SPW_TOP|SPW|TX|tcode_rdy_trnsp~q ) # (\A_SPW_TOP|SPW|TX|Selector23~0_combout )))))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|state_fct_send_p~8_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~4_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|Equal0~4_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|Selector23~0_combout ),
        .datae(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct_c~q ),
        .dataf(!\A_SPW_TOP|SPW|TX|tcode_rdy_trnsp~q ),
        .datag(!\A_SPW_TOP|SPW|TX|state_tx~15_combout ),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|state_tx~32_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_tx~32 .extended_lut = "on";
defparam \A_SPW_TOP|SPW|TX|state_tx~32 .lut_mask = 64'h0222323200223032;
defparam \A_SPW_TOP|SPW|TX|state_tx~32 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X58_Y6_N2
dffeas \A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct_c (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(\A_SPW_TOP|SPW|TX|state_tx~32_combout ),
        .asdata(vcc),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct_c~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct_c .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct_c .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X58_Y6_N48
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector30~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector30~0_combout  = ( !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q  & ( \A_SPW_TOP|SPW|TX|Equal0~5_combout  & ( (!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct_c~q  & (!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q  & 
// (!\A_SPW_TOP|SPW|TX|state_tx~15_combout  & !\A_SPW_TOP|SPW|TX|Selector23~0_combout ))) ) ) ) # ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q  & ( !\A_SPW_TOP|SPW|TX|Equal0~5_combout  & ( (!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct_c~q  & 
// (!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q  & (!\A_SPW_TOP|SPW|TX|state_tx~15_combout  & !\A_SPW_TOP|SPW|TX|Selector23~0_combout ))) ) ) ) # ( !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q  & ( !\A_SPW_TOP|SPW|TX|Equal0~5_combout  & ( 
// (!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct_c~q  & (!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q  & (!\A_SPW_TOP|SPW|TX|state_tx~15_combout  & !\A_SPW_TOP|SPW|TX|Selector23~0_combout ))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct_c~q ),
        .datab(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q ),
        .datac(!\A_SPW_TOP|SPW|TX|state_tx~15_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|Selector23~0_combout ),
        .datae(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q ),
        .dataf(!\A_SPW_TOP|SPW|TX|Equal0~5_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector30~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector30~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector30~0 .lut_mask = 64'h8000800080000000;
defparam \A_SPW_TOP|SPW|TX|Selector30~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X54_Y6_N54
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector30~1 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector30~1_combout  = ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c~q  & ( (\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & (\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & 
// (!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q  & \A_SPW_TOP|SPW|TX|global_counter_transfer [3]))) ) ) ) # ( \A_SPW_TOP|SPW|TX|global_counter_transfer [1] & ( !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c~q  & ( 
// !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q  ) ) ) # ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & ( !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c~q  & ( (!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q ) # 
// ((\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & (!\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & \A_SPW_TOP|SPW|TX|global_counter_transfer [3]))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
        .datab(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
        .datac(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q ),
        .datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
        .datae(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
        .dataf(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector30~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector30~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector30~1 .lut_mask = 64'hF0F4F0F000100000;
defparam \A_SPW_TOP|SPW|TX|Selector30~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X51_Y6_N18
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector30~2 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector30~2_combout  = ( \A_SPW_TOP|SPW|TX|Equal0~1_combout  & ( \A_SPW_TOP|SPW|TX|Selector30~1_combout  ) ) # ( !\A_SPW_TOP|SPW|TX|Equal0~1_combout  & ( (!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_c~q  & 
// \A_SPW_TOP|SPW|TX|Selector30~1_combout ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_c~q ),
        .datad(!\A_SPW_TOP|SPW|TX|Selector30~1_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|Equal0~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector30~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector30~2 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector30~2 .lut_mask = 64'h00F000F000FF00FF;
defparam \A_SPW_TOP|SPW|TX|Selector30~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X53_Y7_N42
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector23~1 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector23~1_combout  = ( \A_SPW_TOP|SPW|TX|Selector30~2_combout  & ( (!\A_SPW_TOP|SPW|TX|Selector30~0_combout  & \A_SPW_TOP|SPW|TX|tx_data_in [8]) ) ) # ( !\A_SPW_TOP|SPW|TX|Selector30~2_combout  & ( (!\A_SPW_TOP|SPW|TX|Equal0~6_combout 
//  & (((!\A_SPW_TOP|SPW|TX|Selector30~0_combout  & \A_SPW_TOP|SPW|TX|tx_data_in [8])) # (\A_SPW_TOP|tx_data|data_out [8]))) # (\A_SPW_TOP|SPW|TX|Equal0~6_combout  & (((\A_SPW_TOP|SPW|TX|tx_data_in [8])))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|Selector30~0_combout ),
        .datab(!\A_SPW_TOP|tx_data|data_out [8]),
        .datac(!\A_SPW_TOP|SPW|TX|tx_data_in [8]),
        .datad(!\A_SPW_TOP|SPW|TX|Equal0~6_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|Selector30~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector23~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector23~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector23~1 .lut_mask = 64'h3B0F3B0F0A0A0A0A;
defparam \A_SPW_TOP|SPW|TX|Selector23~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X54_Y7_N53
dffeas \A_SPW_TOP|SPW|TX|tx_data_in[8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|Selector23~1_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|tx_data_in [8]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_data_in[8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|tx_data_in[8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X59_Y7_N9
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector63~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector63~0_combout  = ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q  & ( (!\A_SPW_TOP|SPW|TX|tx_data_in_0 [8]) # ((\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q  & !\A_SPW_TOP|SPW|TX|tx_data_in [8])) ) ) # ( 
// !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q  & ( (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q  & !\A_SPW_TOP|SPW|TX|tx_data_in [8]) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|TX|tx_data_in [8]),
        .datad(!\A_SPW_TOP|SPW|TX|tx_data_in_0 [8]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector63~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector63~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector63~0 .lut_mask = 64'h50505050FF50FF50;
defparam \A_SPW_TOP|SPW|TX|Selector63~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X53_Y6_N45
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|WideOr12 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|WideOr12~combout  = ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~q  & ( (!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null~q  & !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct~q ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null~q ),
        .datac(gnd),
        .datad(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|WideOr12~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|WideOr12 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|WideOr12 .lut_mask = 64'h00000000CC00CC00;
defparam \A_SPW_TOP|SPW|TX|WideOr12 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X51_Y6_N30
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector73~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector73~0_combout  = ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_c~q  & ( (!\A_SPW_TOP|SPW|TX|Equal0~1_combout  & (\A_SPW_TOP|SPW|TX|WideOr12~combout  & ((!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c~q ) # 
// (!\A_SPW_TOP|SPW|TX|Equal0~3_combout )))) ) ) # ( !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_c~q  & ( (\A_SPW_TOP|SPW|TX|WideOr12~combout  & ((!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c~q ) # (!\A_SPW_TOP|SPW|TX|Equal0~3_combout ))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|Equal0~1_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c~q ),
        .datac(!\A_SPW_TOP|SPW|TX|Equal0~3_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|WideOr12~combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_c~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector73~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector73~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector73~0 .lut_mask = 64'h00FC00FC00A800A8;
defparam \A_SPW_TOP|SPW|TX|Selector73~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X51_Y6_N6
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector73~2 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector73~2_combout  = ( \A_SPW_TOP|SPW|TX|Equal0~5_combout  & ( \A_SPW_TOP|SPW|TX|LessThan6~1_combout  & ( ((\A_SPW_TOP|SPW|TX|char_sent~q  & ((!\A_SPW_TOP|SPW|TX|Selector73~0_combout ) # (\A_SPW_TOP|SPW|TX|Selector63~0_combout )))) # 
// (\A_SPW_TOP|SPW|TX|Selector73~1_combout ) ) ) ) # ( !\A_SPW_TOP|SPW|TX|Equal0~5_combout  & ( \A_SPW_TOP|SPW|TX|LessThan6~1_combout  & ( (((\A_SPW_TOP|SPW|TX|char_sent~q  & !\A_SPW_TOP|SPW|TX|Selector73~0_combout )) # 
// (\A_SPW_TOP|SPW|TX|Selector63~0_combout )) # (\A_SPW_TOP|SPW|TX|Selector73~1_combout ) ) ) ) # ( \A_SPW_TOP|SPW|TX|Equal0~5_combout  & ( !\A_SPW_TOP|SPW|TX|LessThan6~1_combout  & ( ((\A_SPW_TOP|SPW|TX|char_sent~q  & 
// ((!\A_SPW_TOP|SPW|TX|Selector73~0_combout ) # (\A_SPW_TOP|SPW|TX|Selector63~0_combout )))) # (\A_SPW_TOP|SPW|TX|Selector73~1_combout ) ) ) ) # ( !\A_SPW_TOP|SPW|TX|Equal0~5_combout  & ( !\A_SPW_TOP|SPW|TX|LessThan6~1_combout  & ( 
// ((\A_SPW_TOP|SPW|TX|char_sent~q  & !\A_SPW_TOP|SPW|TX|Selector73~0_combout )) # (\A_SPW_TOP|SPW|TX|Selector73~1_combout ) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|Selector73~1_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|Selector63~0_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|char_sent~q ),
        .datad(!\A_SPW_TOP|SPW|TX|Selector73~0_combout ),
        .datae(!\A_SPW_TOP|SPW|TX|Equal0~5_combout ),
        .dataf(!\A_SPW_TOP|SPW|TX|LessThan6~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector73~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector73~2 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector73~2 .lut_mask = 64'h5F555F577F775F57;
defparam \A_SPW_TOP|SPW|TX|Selector73~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X54_Y6_N35
dffeas \A_SPW_TOP|SPW|TX|char_sent (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|Selector73~2_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|char_sent~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|char_sent .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|char_sent .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X56_Y6_N27
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector41~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector41~0_combout  = ( !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c~q  & ( !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_c~q  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_c~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector41~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector41~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector41~0 .lut_mask = 64'hF0F0F0F000000000;
defparam \A_SPW_TOP|SPW|TX|Selector41~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X59_Y6_N33
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector41~1 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector41~1_combout  = ( \A_SPW_TOP|SPW|TX|tx_data_in_0 [8] & ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q  & ( \A_SPW_TOP|SPW|TX|Selector41~0_combout  ) ) ) # ( !\A_SPW_TOP|SPW|TX|tx_data_in_0 [8] & ( 
// \A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q  & ( (\A_SPW_TOP|SPW|TX|Selector41~0_combout  & ((!\A_SPW_TOP|tx_data|write_tx~q ) # ((\A_SPW_TOP|SPW|TX|char_sent~q ) # (\A_SPW_TOP|SPW|TX|LessThan3~0_combout )))) ) ) ) # ( \A_SPW_TOP|SPW|TX|tx_data_in_0 [8] 
// & ( !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q  & ( \A_SPW_TOP|SPW|TX|Selector41~0_combout  ) ) ) # ( !\A_SPW_TOP|SPW|TX|tx_data_in_0 [8] & ( !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q  & ( \A_SPW_TOP|SPW|TX|Selector41~0_combout  ) ) )

        .dataa(!\A_SPW_TOP|tx_data|write_tx~q ),
        .datab(!\A_SPW_TOP|SPW|TX|LessThan3~0_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|char_sent~q ),
        .datad(!\A_SPW_TOP|SPW|TX|Selector41~0_combout ),
        .datae(!\A_SPW_TOP|SPW|TX|tx_data_in_0 [8]),
        .dataf(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector41~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector41~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector41~1 .lut_mask = 64'h00FF00FF00BF00FF;
defparam \A_SPW_TOP|SPW|TX|Selector41~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X59_Y6_N0
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector41~3 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector41~3_combout  = ( \A_SPW_TOP|SPW|TX|Selector30~1_combout  & ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_c~q  & ( (\A_SPW_TOP|tx_data|write_tx~q  & (\A_SPW_TOP|SPW|TX|Equal0~6_combout  & (!\A_SPW_TOP|SPW|TX|LessThan2~0_combout  & 
// !\A_SPW_TOP|SPW|TX|Equal0~1_combout ))) ) ) ) # ( !\A_SPW_TOP|SPW|TX|Selector30~1_combout  & ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_c~q  & ( (\A_SPW_TOP|tx_data|write_tx~q  & (\A_SPW_TOP|SPW|TX|Equal0~6_combout  & !\A_SPW_TOP|SPW|TX|LessThan2~0_combout 
// )) ) ) ) # ( !\A_SPW_TOP|SPW|TX|Selector30~1_combout  & ( !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_c~q  & ( (\A_SPW_TOP|tx_data|write_tx~q  & (\A_SPW_TOP|SPW|TX|Equal0~6_combout  & !\A_SPW_TOP|SPW|TX|LessThan2~0_combout )) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|write_tx~q ),
        .datab(!\A_SPW_TOP|SPW|TX|Equal0~6_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|LessThan2~0_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|Equal0~1_combout ),
        .datae(!\A_SPW_TOP|SPW|TX|Selector30~1_combout ),
        .dataf(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_c~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector41~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector41~3 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector41~3 .lut_mask = 64'h1010000010101000;
defparam \A_SPW_TOP|SPW|TX|Selector41~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X58_Y6_N42
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector30~4 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector30~4_combout  = ( \A_SPW_TOP|SPW|TX|Equal0~5_combout  & ( (!\A_SPW_TOP|SPW|TX|state_tx~15_combout  & (!\A_SPW_TOP|SPW|TX|Selector23~0_combout  & (!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q  & 
// !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct_c~q ))) ) ) # ( !\A_SPW_TOP|SPW|TX|Equal0~5_combout  & ( (!\A_SPW_TOP|SPW|TX|state_tx~15_combout  & (!\A_SPW_TOP|SPW|TX|Selector23~0_combout  & !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct_c~q )) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|state_tx~15_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|Selector23~0_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q ),
        .datad(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct_c~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|Equal0~5_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector30~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector30~4 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector30~4 .lut_mask = 64'h8800880080008000;
defparam \A_SPW_TOP|SPW|TX|Selector30~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X59_Y6_N51
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector41~2 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector41~2_combout  = ( \A_SPW_TOP|SPW|TX|tx_data_in [8] & ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q  & ( \A_SPW_TOP|SPW|TX|tx_tcode_in~0_combout  ) ) ) # ( !\A_SPW_TOP|SPW|TX|tx_data_in [8] & ( 
// \A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q  & ( ((!\A_SPW_TOP|SPW|TX|char_sent~q  & (!\A_SPW_TOP|SPW|TX|LessThan3~0_combout  & \A_SPW_TOP|tx_data|write_tx~q ))) # (\A_SPW_TOP|SPW|TX|tx_tcode_in~0_combout ) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|char_sent~q ),
        .datab(!\A_SPW_TOP|SPW|TX|tx_tcode_in~0_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|LessThan3~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|write_tx~q ),
        .datae(!\A_SPW_TOP|SPW|TX|tx_data_in [8]),
        .dataf(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector41~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector41~2 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector41~2 .lut_mask = 64'h0000000033B33333;
defparam \A_SPW_TOP|SPW|TX|Selector41~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X59_Y6_N36
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector41~4 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector41~4_combout  = ( \A_SPW_TOP|SPW|TX|Selector30~4_combout  & ( \A_SPW_TOP|SPW|TX|Selector41~2_combout  & ( (\A_SPW_TOP|SPW|TX|process_data~q ) # (\A_SPW_TOP|SPW|TX|Selector41~3_combout ) ) ) ) # ( 
// !\A_SPW_TOP|SPW|TX|Selector30~4_combout  & ( \A_SPW_TOP|SPW|TX|Selector41~2_combout  & ( (\A_SPW_TOP|SPW|TX|process_data~q ) # (\A_SPW_TOP|SPW|TX|Selector41~3_combout ) ) ) ) # ( \A_SPW_TOP|SPW|TX|Selector30~4_combout  & ( 
// !\A_SPW_TOP|SPW|TX|Selector41~2_combout  & ( ((!\A_SPW_TOP|SPW|TX|Selector41~1_combout  & (!\A_SPW_TOP|SPW|TX|Equal0~6_combout  & \A_SPW_TOP|SPW|TX|process_data~q ))) # (\A_SPW_TOP|SPW|TX|Selector41~3_combout ) ) ) ) # ( 
// !\A_SPW_TOP|SPW|TX|Selector30~4_combout  & ( !\A_SPW_TOP|SPW|TX|Selector41~2_combout  & ( (\A_SPW_TOP|SPW|TX|process_data~q ) # (\A_SPW_TOP|SPW|TX|Selector41~3_combout ) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|Selector41~1_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|Equal0~6_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|Selector41~3_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|process_data~q ),
        .datae(!\A_SPW_TOP|SPW|TX|Selector30~4_combout ),
        .dataf(!\A_SPW_TOP|SPW|TX|Selector41~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector41~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector41~4 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector41~4 .lut_mask = 64'h0FFF0F8F0FFF0FFF;
defparam \A_SPW_TOP|SPW|TX|Selector41~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X58_Y6_N59
dffeas \A_SPW_TOP|SPW|TX|process_data (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|Selector41~4_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|process_data~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|process_data .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|process_data .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X58_Y6_N45
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|state_tx~17 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|state_tx~17_combout  = ( \A_SPW_TOP|SPW|TX|state_fct_send_p~8_combout  & ( ((\A_SPW_TOP|SPW|TX|state_tx~15_combout  & !\A_SPW_TOP|SPW|TX|tcode_rdy_trnsp~q )) # (\A_SPW_TOP|SPW|TX|Selector23~0_combout ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|state_tx~15_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|Selector23~0_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|tcode_rdy_trnsp~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|state_fct_send_p~8_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|state_tx~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_tx~17 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|state_tx~17 .lut_mask = 64'h0000000073737373;
defparam \A_SPW_TOP|SPW|TX|state_tx~17 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X59_Y6_N18
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|state_tx~16 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|state_tx~16_combout  = ( !\A_SPW_TOP|SPW|TX|tcode_rdy_trnsp~q  & ( (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q  & (\A_SPW_TOP|SPW|TX|Equal0~5_combout  & !\A_SPW_TOP|SPW|TX|tx_data_in_0 [8])) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q ),
        .datac(!\A_SPW_TOP|SPW|TX|Equal0~5_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|tx_data_in_0 [8]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|tcode_rdy_trnsp~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|state_tx~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_tx~16 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|state_tx~16 .lut_mask = 64'h0300030000000000;
defparam \A_SPW_TOP|SPW|TX|state_tx~16 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X59_Y6_N42
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|state_tx~18 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|state_tx~18_combout  = ( \A_SPW_TOP|SPW|TX|next_state_tx~1_combout  & ( \A_SPW_TOP|SPW|TX|state_tx~16_combout  & ( (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~4_combout  & \A_SPW_TOP|SPW|TX|process_data~q ) ) ) ) # ( 
// !\A_SPW_TOP|SPW|TX|next_state_tx~1_combout  & ( \A_SPW_TOP|SPW|TX|state_tx~16_combout  & ( (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~4_combout  & ((\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q ) # (\A_SPW_TOP|SPW|TX|process_data~q ))) ) ) ) # ( 
// \A_SPW_TOP|SPW|TX|next_state_tx~1_combout  & ( !\A_SPW_TOP|SPW|TX|state_tx~16_combout  & ( (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~4_combout  & (\A_SPW_TOP|SPW|TX|process_data~q  & \A_SPW_TOP|SPW|TX|state_tx~17_combout )) ) ) ) # ( 
// !\A_SPW_TOP|SPW|TX|next_state_tx~1_combout  & ( !\A_SPW_TOP|SPW|TX|state_tx~16_combout  & ( (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~4_combout  & (((\A_SPW_TOP|SPW|TX|process_data~q  & \A_SPW_TOP|SPW|TX|state_tx~17_combout )) # 
// (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q ))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~4_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|process_data~q ),
        .datac(!\A_SPW_TOP|SPW|TX|state_tx~17_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q ),
        .datae(!\A_SPW_TOP|SPW|TX|next_state_tx~1_combout ),
        .dataf(!\A_SPW_TOP|SPW|TX|state_tx~16_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|state_tx~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_tx~18 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|state_tx~18 .lut_mask = 64'h0155010111551111;
defparam \A_SPW_TOP|SPW|TX|state_tx~18 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X54_Y6_N8
dffeas \A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|state_tx~18_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X53_Y6_N18
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~2 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~2_combout  = ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q  & ( (!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q  & (!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c~q  & \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~q )) ) ) 
// # ( !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q  & ( (!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q  & (!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c~q  $ (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~q ))) # (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q  & 
// (!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c~q  & \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~q )) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q ),
        .datab(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c~q ),
        .datac(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~2 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~2 .lut_mask = 64'h8686868608080808;
defparam \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X53_Y6_N21
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~3 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~3_combout  = ( !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q  & ( (!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q  & (!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c~q  & \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~q )) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c~q ),
        .datad(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~3 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~3 .lut_mask = 64'h00A000A000000000;
defparam \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X53_Y6_N48
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~4 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~4_combout  = ( !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct~q  & ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_c~q  & ( (!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct_c~q  & (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~3_combout  & 
// !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null~q )) ) ) ) # ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct~q  & ( !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_c~q  & ( (!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct_c~q  & (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~3_combout  & 
// !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null~q )) ) ) ) # ( !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct~q  & ( !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_c~q  & ( (!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct_c~q  & ((!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null~q  & 
// (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~2_combout )) # (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null~q  & ((\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~3_combout ))))) # (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct_c~q  & 
// (((\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~3_combout  & !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null~q )))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~2_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct_c~q ),
        .datac(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~3_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null~q ),
        .datae(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct~q ),
        .dataf(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_c~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~4 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~4 .lut_mask = 64'h470C0C000C000000;
defparam \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X53_Y6_N12
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|state_tx~12 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|state_tx~12_combout  = ( \A_SPW_TOP|SPW|FSM|enable_tx~q  & ( (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~4_combout  & ((\A_SPW_TOP|SPW|FSM|send_null_tx~q ) # (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~q ))) ) ) # ( 
// !\A_SPW_TOP|SPW|FSM|enable_tx~q  & ( (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~q  & \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~4_combout ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~q ),
        .datac(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~4_combout ),
        .datad(!\A_SPW_TOP|SPW|FSM|send_null_tx~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|state_tx~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_tx~12 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|state_tx~12 .lut_mask = 64'h03030303030F030F;
defparam \A_SPW_TOP|SPW|TX|state_tx~12 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X53_Y6_N14
dffeas \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(\A_SPW_TOP|SPW|TX|state_tx~12_combout ),
        .asdata(vcc),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X53_Y6_N54
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector65~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector65~0_combout  = ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~q  & ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [0] ) ) # ( !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~q  & ( (\A_SPW_TOP|SPW|FSM|enable_tx~q  & 
// (!\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & \A_SPW_TOP|SPW|FSM|send_null_tx~q )) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
        .datad(!\A_SPW_TOP|SPW|FSM|send_null_tx~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector65~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector65~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector65~0 .lut_mask = 64'h00500050F0F0F0F0;
defparam \A_SPW_TOP|SPW|TX|Selector65~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X53_Y6_N35
dffeas \A_SPW_TOP|SPW|TX|global_counter_transfer[0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|Selector65~0_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|global_counter_transfer[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|global_counter_transfer[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X59_Y7_N48
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Equal0~1 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Equal0~1_combout  = ( \A_SPW_TOP|SPW|TX|global_counter_transfer [1] & ( (\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & (!\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & \A_SPW_TOP|SPW|TX|global_counter_transfer [2])) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
        .datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Equal0~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Equal0~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Equal0~1 .lut_mask = 64'h0000000000500050;
defparam \A_SPW_TOP|SPW|TX|Equal0~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X53_Y6_N24
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|state_tx~25 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|state_tx~25_combout  = ( \A_SPW_TOP|SPW|FSM|send_fct_tx~q  & ( (\A_SPW_TOP|SPW|FSM|send_null_tx~q  & (\A_SPW_TOP|SPW|FSM|enable_tx~q  & \A_SPW_TOP|SPW|TX|Equal0~1_combout )) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|send_null_tx~q ),
        .datab(!\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .datac(!\A_SPW_TOP|SPW|TX|Equal0~1_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|FSM|send_fct_tx~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|state_tx~25_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_tx~25 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|state_tx~25 .lut_mask = 64'h0000000001010101;
defparam \A_SPW_TOP|SPW|TX|state_tx~25 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X53_Y6_N30
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|state_tx~26 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|state_tx~26_combout  = ( \A_SPW_TOP|SPW|FSM|send_null_tx~q  & ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_null~q  & ( (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~4_combout  & ((!\A_SPW_TOP|SPW|TX|state_tx~25_combout ) # 
// ((!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~q  & \A_SPW_TOP|SPW|FSM|enable_tx~q )))) ) ) ) # ( !\A_SPW_TOP|SPW|FSM|send_null_tx~q  & ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_null~q  & ( (!\A_SPW_TOP|SPW|TX|state_tx~25_combout  & 
// \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~4_combout ) ) ) ) # ( \A_SPW_TOP|SPW|FSM|send_null_tx~q  & ( !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null~q  & ( (!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~q  & (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~4_combout  & 
// \A_SPW_TOP|SPW|FSM|enable_tx~q )) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|state_tx~25_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~q ),
        .datac(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~4_combout ),
        .datad(!\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .datae(!\A_SPW_TOP|SPW|FSM|send_null_tx~q ),
        .dataf(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|state_tx~26_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_tx~26 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|state_tx~26 .lut_mask = 64'h0000000C0A0A0A0E;
defparam \A_SPW_TOP|SPW|TX|state_tx~26 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X53_Y6_N11
dffeas \A_SPW_TOP|SPW|TX|state_tx.tx_spw_null (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|state_tx~26_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_tx.tx_spw_null .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|state_tx.tx_spw_null .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X53_Y6_N57
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~0_combout  = ( !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_c~q  & ( !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null~q  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_c~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~0 .lut_mask = 64'hF0F0F0F000000000;
defparam \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X54_Y6_N9
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Add4~1 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Add4~1_combout  = !\A_SPW_TOP|SPW|TX|global_counter_transfer [3] $ (((!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]) # ((!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]) # (!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]))))

        .dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
        .datab(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
        .datac(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
        .datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Add4~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Add4~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Add4~1 .lut_mask = 64'h0F1E0F1E0F1E0F1E;
defparam \A_SPW_TOP|SPW|TX|Add4~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X58_Y6_N54
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector62~1 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector62~1_combout  = ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~1_combout  & ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q  & ( (\A_SPW_TOP|SPW|TX|Equal0~5_combout  & (!\A_SPW_TOP|SPW|TX|tx_data_in_0 [8] & 
// ((!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q ) # (!\A_SPW_TOP|SPW|TX|tx_data_in [8])))) ) ) ) # ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~1_combout  & ( !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q  & ( (!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q ) # 
// ((\A_SPW_TOP|SPW|TX|Equal0~5_combout  & !\A_SPW_TOP|SPW|TX|tx_data_in [8])) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|Equal0~5_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q ),
        .datac(!\A_SPW_TOP|SPW|TX|tx_data_in_0 [8]),
        .datad(!\A_SPW_TOP|SPW|TX|tx_data_in [8]),
        .datae(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~1_combout ),
        .dataf(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector62~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector62~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector62~1 .lut_mask = 64'h0000DDCC00005040;
defparam \A_SPW_TOP|SPW|TX|Selector62~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X54_Y6_N0
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector62~2 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector62~2_combout  = ( \A_SPW_TOP|SPW|TX|Equal0~1_combout  & ( (\A_SPW_TOP|SPW|TX|Add4~1_combout  & ((!\A_SPW_TOP|SPW|TX|Selector62~1_combout ) # (\A_SPW_TOP|SPW|TX|Selector63~3_combout ))) ) ) # ( !\A_SPW_TOP|SPW|TX|Equal0~1_combout  
// & ( (\A_SPW_TOP|SPW|TX|Add4~1_combout  & (((!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~0_combout ) # (!\A_SPW_TOP|SPW|TX|Selector62~1_combout )) # (\A_SPW_TOP|SPW|TX|Selector63~3_combout ))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|Selector63~3_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~0_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|Add4~1_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|Selector62~1_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|Equal0~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector62~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector62~2 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector62~2 .lut_mask = 64'h0F0D0F0D0F050F05;
defparam \A_SPW_TOP|SPW|TX|Selector62~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X54_Y6_N2
dffeas \A_SPW_TOP|SPW|TX|global_counter_transfer[3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(\A_SPW_TOP|SPW|TX|Selector62~2_combout ),
        .asdata(vcc),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|global_counter_transfer[3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|global_counter_transfer[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X54_Y6_N30
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Equal0~3 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Equal0~3_combout  = ( \A_SPW_TOP|SPW|TX|global_counter_transfer [0] & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & (\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & \A_SPW_TOP|SPW|TX|global_counter_transfer [3])) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
        .datab(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
        .datac(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Equal0~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Equal0~3 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Equal0~3 .lut_mask = 64'h0000000002020202;
defparam \A_SPW_TOP|SPW|TX|Equal0~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X53_Y6_N3
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector62~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector62~0_combout  = ( !\A_SPW_TOP|SPW|TX|Equal0~3_combout  & ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c~q  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\A_SPW_TOP|SPW|TX|Equal0~3_combout ),
        .dataf(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector62~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector62~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector62~0 .lut_mask = 64'h00000000FFFF0000;
defparam \A_SPW_TOP|SPW|TX|Selector62~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y6_N21
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Add4~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Add4~0_combout  = ( \A_SPW_TOP|SPW|TX|global_counter_transfer [2] & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]) # (!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]) ) ) # ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & ( 
// (\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & \A_SPW_TOP|SPW|TX|global_counter_transfer [0]) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
        .datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Add4~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Add4~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Add4~0 .lut_mask = 64'h000F000FFFF0FFF0;
defparam \A_SPW_TOP|SPW|TX|Add4~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X56_Y6_N30
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector63~1 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector63~1_combout  = ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~1_combout  & ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~5_combout  & ( (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~0_combout  & !\A_SPW_TOP|SPW|TX|Selector63~0_combout ) ) ) ) 
// # ( !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~1_combout  & ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~5_combout  & ( (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~0_combout  & (\A_SPW_TOP|SPW|TX|Equal0~4_combout  & !\A_SPW_TOP|SPW|TX|Selector63~0_combout )) ) ) 
// ) # ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~1_combout  & ( !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~5_combout  & ( (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~0_combout  & (\A_SPW_TOP|SPW|TX|Equal0~4_combout  & !\A_SPW_TOP|SPW|TX|Selector63~0_combout )) ) 
// ) ) # ( !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~1_combout  & ( !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~5_combout  & ( (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~0_combout  & (\A_SPW_TOP|SPW|TX|Equal0~4_combout  & !\A_SPW_TOP|SPW|TX|Selector63~0_combout )) 
// ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~0_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|Equal0~4_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|Selector63~0_combout ),
        .datae(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~1_combout ),
        .dataf(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~5_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector63~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector63~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector63~1 .lut_mask = 64'h0300030003003300;
defparam \A_SPW_TOP|SPW|TX|Selector63~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X53_Y6_N6
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector63~2 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector63~2_combout  = ( \A_SPW_TOP|SPW|FSM|send_null_tx~q  & ( \A_SPW_TOP|SPW|FSM|enable_tx~q  & ( (\A_SPW_TOP|SPW|TX|Add4~0_combout  & (((!\A_SPW_TOP|SPW|TX|Selector63~1_combout ) # (!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~q )) # 
// (\A_SPW_TOP|SPW|TX|Selector62~0_combout ))) ) ) ) # ( !\A_SPW_TOP|SPW|FSM|send_null_tx~q  & ( \A_SPW_TOP|SPW|FSM|enable_tx~q  & ( (\A_SPW_TOP|SPW|TX|Add4~0_combout  & ((!\A_SPW_TOP|SPW|TX|Selector63~1_combout ) # (\A_SPW_TOP|SPW|TX|Selector62~0_combout 
// ))) ) ) ) # ( \A_SPW_TOP|SPW|FSM|send_null_tx~q  & ( !\A_SPW_TOP|SPW|FSM|enable_tx~q  & ( (\A_SPW_TOP|SPW|TX|Add4~0_combout  & ((!\A_SPW_TOP|SPW|TX|Selector63~1_combout ) # (\A_SPW_TOP|SPW|TX|Selector62~0_combout ))) ) ) ) # ( 
// !\A_SPW_TOP|SPW|FSM|send_null_tx~q  & ( !\A_SPW_TOP|SPW|FSM|enable_tx~q  & ( (\A_SPW_TOP|SPW|TX|Add4~0_combout  & ((!\A_SPW_TOP|SPW|TX|Selector63~1_combout ) # (\A_SPW_TOP|SPW|TX|Selector62~0_combout ))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|Selector62~0_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|Add4~0_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|Selector63~1_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~q ),
        .datae(!\A_SPW_TOP|SPW|FSM|send_null_tx~q ),
        .dataf(!\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector63~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector63~2 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector63~2 .lut_mask = 64'h3131313131313331;
defparam \A_SPW_TOP|SPW|TX|Selector63~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X54_Y6_N44
dffeas \A_SPW_TOP|SPW|TX|global_counter_transfer[2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|Selector63~2_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|global_counter_transfer[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|global_counter_transfer[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y17_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_payload~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_payload~1_combout  = ( \u0|hps_0|fpga_interfaces|h2f_WDATA [1] & ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_WDATA [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_010|src_payload~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_payload~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_payload~1 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_payload~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y17_N50
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_010|src_payload~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X30_Y15_N41
dffeas \u0|write_data_fifo_tx|data_out[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|write_data_fifo_tx|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|write_data_fifo_tx|data_out [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|write_data_fifo_tx|data_out[1] .is_wysiwyg = "true";
defparam \u0|write_data_fifo_tx|data_out[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y13_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector300~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector300~0_combout  = ( \A_SPW_TOP|tx_data|Selector293~0_combout  & ( \A_SPW_TOP|tx_data|mem[32][1]~q  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux7~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [1]))) ) ) ) # ( !\A_SPW_TOP|tx_data|Selector293~0_combout  & ( \A_SPW_TOP|tx_data|mem[32][1]~q  ) ) # ( \A_SPW_TOP|tx_data|Selector293~0_combout  & ( 
// !\A_SPW_TOP|tx_data|mem[32][1]~q  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux7~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [1]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\u0|write_data_fifo_tx|data_out [1]),
        .datad(gnd),
        .datae(!\A_SPW_TOP|tx_data|Selector293~0_combout ),
        .dataf(!\A_SPW_TOP|tx_data|mem[32][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector300~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector300~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector300~0 .lut_mask = 64'h00004747FFFF4747;
defparam \A_SPW_TOP|tx_data|Selector300~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y13_N20
dffeas \A_SPW_TOP|tx_data|mem[32][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector300~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[32][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[32][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[32][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y13_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector309~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector309~0_combout  = ( \A_SPW_TOP|tx_data|mem[33][1]~q  & ( (!\A_SPW_TOP|tx_data|Selector302~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux7~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [1]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[33][1]~q  & ( (\A_SPW_TOP|tx_data|Selector302~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux7~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [1])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [1]),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector302~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[33][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector309~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector309~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector309~0 .lut_mask = 64'h010D010DF1FDF1FD;
defparam \A_SPW_TOP|tx_data|Selector309~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y13_N17
dffeas \A_SPW_TOP|tx_data|mem[33][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector309~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[33][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[33][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[33][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y13_N45
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector327~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector327~0_combout  = ( \A_SPW_TOP|tx_data|mem[35][1]~q  & ( (!\A_SPW_TOP|tx_data|Selector320~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux7~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [1]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[35][1]~q  & ( (\A_SPW_TOP|tx_data|Selector320~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux7~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [1])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [1]),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector320~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[35][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector327~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector327~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector327~0 .lut_mask = 64'h010D010DF1FDF1FD;
defparam \A_SPW_TOP|tx_data|Selector327~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y13_N14
dffeas \A_SPW_TOP|tx_data|mem[35][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector327~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[35][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[35][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[35][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y13_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector318~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector318~0_combout  = ( \A_SPW_TOP|tx_data|mem[34][1]~q  & ( (!\A_SPW_TOP|tx_data|Selector311~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux7~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [1]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[34][1]~q  & ( (\A_SPW_TOP|tx_data|Selector311~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux7~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [1])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [1]),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector311~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[34][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector318~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector318~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector318~0 .lut_mask = 64'h010D010DF1FDF1FD;
defparam \A_SPW_TOP|tx_data|Selector318~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y13_N11
dffeas \A_SPW_TOP|tx_data|mem[34][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector318~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[34][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[34][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[34][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y13_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux7~2 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux7~2_combout  = ( \A_SPW_TOP|tx_data|mem[35][1]~q  & ( \A_SPW_TOP|tx_data|mem[34][1]~q  & ( ((!\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|mem[32][1]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|mem[33][1]~q 
// )))) # (\A_SPW_TOP|tx_data|wr_ptr [1]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[35][1]~q  & ( \A_SPW_TOP|tx_data|mem[34][1]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [1] & ((!\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|mem[32][1]~q )) # 
// (\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|mem[33][1]~q ))))) # (\A_SPW_TOP|tx_data|wr_ptr [1] & (((!\A_SPW_TOP|tx_data|wr_ptr [0])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[35][1]~q  & ( !\A_SPW_TOP|tx_data|mem[34][1]~q  & ( 
// (!\A_SPW_TOP|tx_data|wr_ptr [1] & ((!\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|mem[32][1]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|mem[33][1]~q ))))) # (\A_SPW_TOP|tx_data|wr_ptr [1] & (((\A_SPW_TOP|tx_data|wr_ptr [0])))) ) ) 
// ) # ( !\A_SPW_TOP|tx_data|mem[35][1]~q  & ( !\A_SPW_TOP|tx_data|mem[34][1]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [1] & ((!\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|mem[32][1]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|mem[33][1]~q 
// ))))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[32][1]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[33][1]~q ),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datae(!\A_SPW_TOP|tx_data|mem[35][1]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[34][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux7~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux7~2 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux7~2 .lut_mask = 64'h5030503F5F305F3F;
defparam \A_SPW_TOP|tx_data|Mux7~2 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y13_N45
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector21~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector21~0_combout  = ( \A_SPW_TOP|tx_data|Selector14~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux7~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out 
// [1]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector14~0_combout  & ( \A_SPW_TOP|tx_data|mem[1][1]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\u0|write_data_fifo_tx|data_out [1]),
        .datad(!\A_SPW_TOP|tx_data|mem[1][1]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector14~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector21~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector21~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector21~0 .lut_mask = 64'h00FF00FF47474747;
defparam \A_SPW_TOP|tx_data|Selector21~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y13_N29
dffeas \A_SPW_TOP|tx_data|mem[1][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector21~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[1][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[1][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[1][1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y13_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector30~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector30~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector23~0_combout  & ((\A_SPW_TOP|tx_data|mem[2][1]~q ))) # (\A_SPW_TOP|tx_data|Selector23~0_combout  & (\u0|write_data_fifo_tx|data_out 
// [1])) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector23~0_combout  & ((\A_SPW_TOP|tx_data|mem[2][1]~q ))) # (\A_SPW_TOP|tx_data|Selector23~0_combout  & (\A_SPW_TOP|tx_data|Mux7~20_combout )) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [1]),
        .datac(!\A_SPW_TOP|tx_data|Selector23~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|mem[2][1]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector30~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector30~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector30~0 .lut_mask = 64'h05F505F503F303F3;
defparam \A_SPW_TOP|tx_data|Selector30~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y13_N23
dffeas \A_SPW_TOP|tx_data|mem[2][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector30~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[2][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[2][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[2][1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y13_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector12~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector12~0_combout  = ( \u0|write_data_fifo_tx|data_out [1] & ( \A_SPW_TOP|tx_data|mem[0][1]~q  & ( ((!\A_SPW_TOP|tx_data|Selector5~0_combout ) # (\A_SPW_TOP|tx_data|state_data_write.00~q )) # (\A_SPW_TOP|tx_data|Mux7~20_combout ) ) ) 
// ) # ( !\u0|write_data_fifo_tx|data_out [1] & ( \A_SPW_TOP|tx_data|mem[0][1]~q  & ( (!\A_SPW_TOP|tx_data|Selector5~0_combout ) # ((\A_SPW_TOP|tx_data|Mux7~20_combout  & !\A_SPW_TOP|tx_data|state_data_write.00~q )) ) ) ) # ( \u0|write_data_fifo_tx|data_out 
// [1] & ( !\A_SPW_TOP|tx_data|mem[0][1]~q  & ( (\A_SPW_TOP|tx_data|Selector5~0_combout  & ((\A_SPW_TOP|tx_data|state_data_write.00~q ) # (\A_SPW_TOP|tx_data|Mux7~20_combout ))) ) ) ) # ( !\u0|write_data_fifo_tx|data_out [1] & ( 
// !\A_SPW_TOP|tx_data|mem[0][1]~q  & ( (\A_SPW_TOP|tx_data|Mux7~20_combout  & (!\A_SPW_TOP|tx_data|state_data_write.00~q  & \A_SPW_TOP|tx_data|Selector5~0_combout )) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector5~0_combout ),
        .datad(gnd),
        .datae(!\u0|write_data_fifo_tx|data_out [1]),
        .dataf(!\A_SPW_TOP|tx_data|mem[0][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector12~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector12~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector12~0 .lut_mask = 64'h04040707F4F4F7F7;
defparam \A_SPW_TOP|tx_data|Selector12~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y13_N8
dffeas \A_SPW_TOP|tx_data|mem[0][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector12~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[0][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[0][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[0][1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y13_N51
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector39~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector39~0_combout  = ( \A_SPW_TOP|tx_data|mem[3][1]~q  & ( (!\A_SPW_TOP|tx_data|Selector32~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux7~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [1])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[3][1]~q  & ( (\A_SPW_TOP|tx_data|Selector32~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux7~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [1]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector32~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [1]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[3][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector39~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector39~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector39~0 .lut_mask = 64'h04070407F4F7F4F7;
defparam \A_SPW_TOP|tx_data|Selector39~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y13_N26
dffeas \A_SPW_TOP|tx_data|mem[3][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector39~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[3][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[3][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[3][1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y13_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux7~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux7~0_combout  = ( \A_SPW_TOP|tx_data|mem[3][1]~q  & ( \A_SPW_TOP|tx_data|wr_ptr [0] & ( (\A_SPW_TOP|tx_data|wr_ptr [1]) # (\A_SPW_TOP|tx_data|mem[1][1]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[3][1]~q  & ( \A_SPW_TOP|tx_data|wr_ptr [0] & 
// ( (\A_SPW_TOP|tx_data|mem[1][1]~q  & !\A_SPW_TOP|tx_data|wr_ptr [1]) ) ) ) # ( \A_SPW_TOP|tx_data|mem[3][1]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [0] & ( (!\A_SPW_TOP|tx_data|wr_ptr [1] & ((\A_SPW_TOP|tx_data|mem[0][1]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [1] & 
// (\A_SPW_TOP|tx_data|mem[2][1]~q )) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[3][1]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [0] & ( (!\A_SPW_TOP|tx_data|wr_ptr [1] & ((\A_SPW_TOP|tx_data|mem[0][1]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|mem[2][1]~q 
// )) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[1][1]~q ),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datac(!\A_SPW_TOP|tx_data|mem[2][1]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[0][1]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[3][1]~q ),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux7~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux7~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux7~0 .lut_mask = 64'h03CF03CF44447777;
defparam \A_SPW_TOP|tx_data|Mux7~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X51_Y13_N21
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector102~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector102~0_combout  = ( \A_SPW_TOP|tx_data|mem[10][1]~q  & ( (!\A_SPW_TOP|tx_data|Selector95~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux7~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [1])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[10][1]~q  & ( (\A_SPW_TOP|tx_data|Selector95~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux7~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [1]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .datac(!\u0|write_data_fifo_tx|data_out [1]),
        .datad(!\A_SPW_TOP|tx_data|Selector95~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[10][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector102~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector102~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector102~0 .lut_mask = 64'h00270027FF27FF27;
defparam \A_SPW_TOP|tx_data|Selector102~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X51_Y13_N53
dffeas \A_SPW_TOP|tx_data|mem[10][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector102~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[10][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[10][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[10][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X51_Y13_N45
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector111~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector111~0_combout  = ( \A_SPW_TOP|tx_data|mem[11][1]~q  & ( (!\A_SPW_TOP|tx_data|Selector104~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux7~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [1])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[11][1]~q  & ( (\A_SPW_TOP|tx_data|Selector104~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux7~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [1]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .datac(!\u0|write_data_fifo_tx|data_out [1]),
        .datad(!\A_SPW_TOP|tx_data|Selector104~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[11][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector111~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector111~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector111~0 .lut_mask = 64'h00270027FF27FF27;
defparam \A_SPW_TOP|tx_data|Selector111~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X51_Y13_N11
dffeas \A_SPW_TOP|tx_data|mem[11][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector111~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[11][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[11][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[11][1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y13_N39
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector84~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector84~0_combout  = ( \A_SPW_TOP|tx_data|mem[8][1]~q  & ( (!\A_SPW_TOP|tx_data|Selector77~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux7~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [1])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[8][1]~q  & ( (\A_SPW_TOP|tx_data|Selector77~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux7~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [1]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [1]),
        .datac(!\A_SPW_TOP|tx_data|Selector77~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[8][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector84~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector84~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector84~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|tx_data|Selector84~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y13_N35
dffeas \A_SPW_TOP|tx_data|mem[8][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector84~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[8][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[8][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[8][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X51_Y13_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector93~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector93~0_combout  = ( \A_SPW_TOP|tx_data|mem[9][1]~q  & ( (!\A_SPW_TOP|tx_data|Selector86~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux7~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [1])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[9][1]~q  & ( (\A_SPW_TOP|tx_data|Selector86~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux7~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [1]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector86~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [1]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[9][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector93~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector93~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector93~0 .lut_mask = 64'h02070207F2F7F2F7;
defparam \A_SPW_TOP|tx_data|Selector93~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X51_Y13_N39
cyclonev_lcell_comb \A_SPW_TOP|tx_data|mem[9][1]~feeder (
// Equation(s):
// \A_SPW_TOP|tx_data|mem[9][1]~feeder_combout  = ( \A_SPW_TOP|tx_data|Selector93~0_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector93~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|mem[9][1]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[9][1]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|mem[9][1]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|tx_data|mem[9][1]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X51_Y13_N41
dffeas \A_SPW_TOP|tx_data|mem[9][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|tx_data|mem[9][1]~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[9][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[9][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[9][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X51_Y13_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux7~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux7~1_combout  = ( \A_SPW_TOP|tx_data|mem[8][1]~q  & ( \A_SPW_TOP|tx_data|mem[9][1]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [1]) # ((!\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|mem[10][1]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [0] & 
// ((\A_SPW_TOP|tx_data|mem[11][1]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[8][1]~q  & ( \A_SPW_TOP|tx_data|mem[9][1]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [1] & (((\A_SPW_TOP|tx_data|wr_ptr [0])))) # (\A_SPW_TOP|tx_data|wr_ptr [1] & 
// ((!\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|mem[10][1]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|mem[11][1]~q ))))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[8][1]~q  & ( !\A_SPW_TOP|tx_data|mem[9][1]~q  & ( 
// (!\A_SPW_TOP|tx_data|wr_ptr [1] & (((!\A_SPW_TOP|tx_data|wr_ptr [0])))) # (\A_SPW_TOP|tx_data|wr_ptr [1] & ((!\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|mem[10][1]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|mem[11][1]~q ))))) ) 
// ) ) # ( !\A_SPW_TOP|tx_data|mem[8][1]~q  & ( !\A_SPW_TOP|tx_data|mem[9][1]~q  & ( (\A_SPW_TOP|tx_data|wr_ptr [1] & ((!\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|mem[10][1]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|mem[11][1]~q 
// ))))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[10][1]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[11][1]~q ),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datae(!\A_SPW_TOP|tx_data|mem[8][1]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[9][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux7~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux7~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux7~1 .lut_mask = 64'h0503F50305F3F5F3;
defparam \A_SPW_TOP|tx_data|Mux7~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y13_N51
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector399~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector399~0_combout  = ( \u0|write_data_fifo_tx|data_out [1] & ( (!\A_SPW_TOP|tx_data|Selector392~0_combout  & (((\A_SPW_TOP|tx_data|mem[43][1]~q )))) # (\A_SPW_TOP|tx_data|Selector392~0_combout  & 
// (((\A_SPW_TOP|tx_data|Mux7~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q ))) ) ) # ( !\u0|write_data_fifo_tx|data_out [1] & ( (!\A_SPW_TOP|tx_data|Selector392~0_combout  & (((\A_SPW_TOP|tx_data|mem[43][1]~q )))) # 
// (\A_SPW_TOP|tx_data|Selector392~0_combout  & (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux7~20_combout ))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector392~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|mem[43][1]~q ),
        .datae(gnd),
        .dataf(!\u0|write_data_fifo_tx|data_out [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector399~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector399~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector399~0 .lut_mask = 64'h02F202F207F707F7;
defparam \A_SPW_TOP|tx_data|Selector399~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y13_N56
dffeas \A_SPW_TOP|tx_data|mem[43][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector399~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[43][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[43][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[43][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y13_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector381~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector381~0_combout  = ( \A_SPW_TOP|tx_data|Selector374~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux7~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\u0|write_data_fifo_tx|data_out [1])) ) ) # ( !\A_SPW_TOP|tx_data|Selector374~0_combout  & ( \A_SPW_TOP|tx_data|mem[41][1]~q  ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [1]),
        .datab(!\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[41][1]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector374~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector381~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector381~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector381~0 .lut_mask = 64'h00FF00FF35353535;
defparam \A_SPW_TOP|tx_data|Selector381~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y13_N59
dffeas \A_SPW_TOP|tx_data|mem[41][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector381~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[41][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[41][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[41][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y13_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector372~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector372~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector365~0_combout  & ((\A_SPW_TOP|tx_data|mem[40][1]~q ))) # (\A_SPW_TOP|tx_data|Selector365~0_combout  & (\u0|write_data_fifo_tx|data_out 
// [1])) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector365~0_combout  & (\A_SPW_TOP|tx_data|mem[40][1]~q )) # (\A_SPW_TOP|tx_data|Selector365~0_combout  & ((\A_SPW_TOP|tx_data|Mux7~20_combout ))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Selector365~0_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [1]),
        .datac(!\A_SPW_TOP|tx_data|mem[40][1]~q ),
        .datad(!\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .datae(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector372~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector372~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector372~0 .lut_mask = 64'h0A5F1B1B0A5F1B1B;
defparam \A_SPW_TOP|tx_data|Selector372~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y13_N44
dffeas \A_SPW_TOP|tx_data|mem[40][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector372~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[40][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[40][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[40][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y13_N27
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector390~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector390~0_combout  = ( \A_SPW_TOP|tx_data|mem[42][1]~q  & ( (!\A_SPW_TOP|tx_data|Selector383~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux7~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [1]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[42][1]~q  & ( (\A_SPW_TOP|tx_data|Selector383~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux7~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [1])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [1]),
        .datab(!\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector383~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[42][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector390~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector390~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector390~0 .lut_mask = 64'h03050305F3F5F3F5;
defparam \A_SPW_TOP|tx_data|Selector390~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y13_N17
dffeas \A_SPW_TOP|tx_data|mem[42][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector390~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[42][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[42][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[42][1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y13_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux7~3 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux7~3_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [1] & ( \A_SPW_TOP|tx_data|wr_ptr [0] & ( \A_SPW_TOP|tx_data|mem[43][1]~q  ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( \A_SPW_TOP|tx_data|wr_ptr [0] & ( \A_SPW_TOP|tx_data|mem[41][1]~q  ) ) 
// ) # ( \A_SPW_TOP|tx_data|wr_ptr [1] & ( !\A_SPW_TOP|tx_data|wr_ptr [0] & ( \A_SPW_TOP|tx_data|mem[42][1]~q  ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( !\A_SPW_TOP|tx_data|wr_ptr [0] & ( \A_SPW_TOP|tx_data|mem[40][1]~q  ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[43][1]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[41][1]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[40][1]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[42][1]~q ),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux7~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux7~3 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux7~3 .lut_mask = 64'h0F0F00FF33335555;
defparam \A_SPW_TOP|tx_data|Mux7~3 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y13_N21
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux7~4 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux7~4_combout  = ( \A_SPW_TOP|tx_data|Mux7~1_combout  & ( \A_SPW_TOP|tx_data|Mux7~3_combout  & ( ((!\A_SPW_TOP|tx_data|wr_ptr [5] & ((\A_SPW_TOP|tx_data|Mux7~0_combout ))) # (\A_SPW_TOP|tx_data|wr_ptr [5] & 
// (\A_SPW_TOP|tx_data|Mux7~2_combout ))) # (\A_SPW_TOP|tx_data|wr_ptr [3]) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux7~1_combout  & ( \A_SPW_TOP|tx_data|Mux7~3_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [3] & ((!\A_SPW_TOP|tx_data|wr_ptr [5] & 
// ((\A_SPW_TOP|tx_data|Mux7~0_combout ))) # (\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|Mux7~2_combout )))) # (\A_SPW_TOP|tx_data|wr_ptr [3] & (\A_SPW_TOP|tx_data|wr_ptr [5])) ) ) ) # ( \A_SPW_TOP|tx_data|Mux7~1_combout  & ( 
// !\A_SPW_TOP|tx_data|Mux7~3_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [3] & ((!\A_SPW_TOP|tx_data|wr_ptr [5] & ((\A_SPW_TOP|tx_data|Mux7~0_combout ))) # (\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|Mux7~2_combout )))) # (\A_SPW_TOP|tx_data|wr_ptr 
// [3] & (!\A_SPW_TOP|tx_data|wr_ptr [5])) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux7~1_combout  & ( !\A_SPW_TOP|tx_data|Mux7~3_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [3] & ((!\A_SPW_TOP|tx_data|wr_ptr [5] & ((\A_SPW_TOP|tx_data|Mux7~0_combout ))) # 
// (\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|Mux7~2_combout )))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datac(!\A_SPW_TOP|tx_data|Mux7~2_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux7~0_combout ),
        .datae(!\A_SPW_TOP|tx_data|Mux7~1_combout ),
        .dataf(!\A_SPW_TOP|tx_data|Mux7~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux7~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux7~4 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux7~4 .lut_mask = 64'h028A46CE139B57DF;
defparam \A_SPW_TOP|tx_data|Mux7~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y10_N9
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector210~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector210~0_combout  = ( \A_SPW_TOP|tx_data|mem[22][1]~q  & ( (!\A_SPW_TOP|tx_data|Selector203~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux7~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [1]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[22][1]~q  & ( (\A_SPW_TOP|tx_data|Selector203~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux7~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [1])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [1]),
        .datab(!\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector203~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[22][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector210~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector210~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector210~0 .lut_mask = 64'h03050305F3F5F3F5;
defparam \A_SPW_TOP|tx_data|Selector210~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X45_Y10_N14
dffeas \A_SPW_TOP|tx_data|mem[22][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector210~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[22][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[22][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[22][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y9_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector507~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector507~0_combout  = ( \A_SPW_TOP|tx_data|Selector500~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux7~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [1]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector500~0_combout  & ( \A_SPW_TOP|tx_data|mem[55][1]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[55][1]~q ),
        .datad(!\u0|write_data_fifo_tx|data_out [1]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector500~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector507~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector507~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector507~0 .lut_mask = 64'h0F0F0F0F44774477;
defparam \A_SPW_TOP|tx_data|Selector507~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y9_N56
dffeas \A_SPW_TOP|tx_data|mem[55][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector507~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[55][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[55][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[55][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y9_N27
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector498~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector498~0_combout  = ( \A_SPW_TOP|tx_data|Selector491~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux7~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [1]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector491~0_combout  & ( \A_SPW_TOP|tx_data|mem[54][1]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\u0|write_data_fifo_tx|data_out [1]),
        .datad(!\A_SPW_TOP|tx_data|mem[54][1]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector491~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector498~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector498~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector498~0 .lut_mask = 64'h00FF00FF47474747;
defparam \A_SPW_TOP|tx_data|Selector498~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y9_N47
dffeas \A_SPW_TOP|tx_data|mem[54][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector498~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[54][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[54][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[54][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y10_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector219~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector219~0_combout  = ( \A_SPW_TOP|tx_data|mem[23][1]~q  & ( (!\A_SPW_TOP|tx_data|Selector212~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux7~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [1]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[23][1]~q  & ( (\A_SPW_TOP|tx_data|Selector212~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux7~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [1])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [1]),
        .datab(!\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector212~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[23][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector219~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector219~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector219~0 .lut_mask = 64'h03050305F3F5F3F5;
defparam \A_SPW_TOP|tx_data|Selector219~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X45_Y10_N11
dffeas \A_SPW_TOP|tx_data|mem[23][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector219~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[23][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[23][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[23][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y9_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux7~17 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux7~17_combout  = ( \A_SPW_TOP|tx_data|mem[23][1]~q  & ( \A_SPW_TOP|tx_data|wr_ptr [5] & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|mem[54][1]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|mem[55][1]~q )) ) 
// ) ) # ( !\A_SPW_TOP|tx_data|mem[23][1]~q  & ( \A_SPW_TOP|tx_data|wr_ptr [5] & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|mem[54][1]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|mem[55][1]~q )) ) ) ) # ( 
// \A_SPW_TOP|tx_data|mem[23][1]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [5] & ( (\A_SPW_TOP|tx_data|mem[22][1]~q ) # (\A_SPW_TOP|tx_data|wr_ptr [0]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[23][1]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [5] & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] 
// & \A_SPW_TOP|tx_data|mem[22][1]~q ) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datab(!\A_SPW_TOP|tx_data|mem[22][1]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[55][1]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[54][1]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[23][1]~q ),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux7~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux7~17 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux7~17 .lut_mask = 64'h2222777705AF05AF;
defparam \A_SPW_TOP|tx_data|Mux7~17 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y9_N57
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector291~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector291~0_combout  = ( \A_SPW_TOP|tx_data|Selector284~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux7~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [1]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector284~0_combout  & ( \A_SPW_TOP|tx_data|mem[31][1]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .datac(!\u0|write_data_fifo_tx|data_out [1]),
        .datad(!\A_SPW_TOP|tx_data|mem[31][1]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector284~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector291~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector291~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector291~0 .lut_mask = 64'h00FF00FF27272727;
defparam \A_SPW_TOP|tx_data|Selector291~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y9_N2
dffeas \A_SPW_TOP|tx_data|mem[31][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector291~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[31][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[31][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[31][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y9_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector282~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector282~0_combout  = ( \A_SPW_TOP|tx_data|mem[30][1]~q  & ( (!\A_SPW_TOP|tx_data|Selector275~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux7~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [1])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[30][1]~q  & ( (\A_SPW_TOP|tx_data|Selector275~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux7~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [1]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .datac(!\u0|write_data_fifo_tx|data_out [1]),
        .datad(!\A_SPW_TOP|tx_data|Selector275~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[30][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector282~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector282~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector282~0 .lut_mask = 64'h00270027FF27FF27;
defparam \A_SPW_TOP|tx_data|Selector282~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y9_N17
dffeas \A_SPW_TOP|tx_data|mem[30][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector282~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[30][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[30][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[30][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y9_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector579~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector579~0_combout  = ( \A_SPW_TOP|tx_data|mem[63][1]~q  & ( (!\A_SPW_TOP|tx_data|Selector572~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux7~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [1])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[63][1]~q  & ( (\A_SPW_TOP|tx_data|Selector572~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux7~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [1]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [1]),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|tx_data|Selector572~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[63][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector579~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector579~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector579~0 .lut_mask = 64'h00530053FF53FF53;
defparam \A_SPW_TOP|tx_data|Selector579~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y9_N44
dffeas \A_SPW_TOP|tx_data|mem[63][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector579~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[63][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[63][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[63][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y9_N51
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector570~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector570~0_combout  = ( \A_SPW_TOP|tx_data|Selector563~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux7~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [1]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector563~0_combout  & ( \A_SPW_TOP|tx_data|mem[62][1]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [1]),
        .datac(!\A_SPW_TOP|tx_data|mem[62][1]~q ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector563~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector570~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector570~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector570~0 .lut_mask = 64'h0F0F0F0F55335533;
defparam \A_SPW_TOP|tx_data|Selector570~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y9_N47
dffeas \A_SPW_TOP|tx_data|mem[62][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector570~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[62][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[62][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[62][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y9_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux7~18 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux7~18_combout  = ( \A_SPW_TOP|tx_data|mem[63][1]~q  & ( \A_SPW_TOP|tx_data|mem[62][1]~q  & ( ((!\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|mem[30][1]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|mem[31][1]~q 
// ))) # (\A_SPW_TOP|tx_data|wr_ptr [5]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[63][1]~q  & ( \A_SPW_TOP|tx_data|mem[62][1]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & (((\A_SPW_TOP|tx_data|wr_ptr [5]) # (\A_SPW_TOP|tx_data|mem[30][1]~q )))) # 
// (\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|mem[31][1]~q  & ((!\A_SPW_TOP|tx_data|wr_ptr [5])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[63][1]~q  & ( !\A_SPW_TOP|tx_data|mem[62][1]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & 
// (((\A_SPW_TOP|tx_data|mem[30][1]~q  & !\A_SPW_TOP|tx_data|wr_ptr [5])))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & (((\A_SPW_TOP|tx_data|wr_ptr [5])) # (\A_SPW_TOP|tx_data|mem[31][1]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[63][1]~q  & ( 
// !\A_SPW_TOP|tx_data|mem[62][1]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [5] & ((!\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|mem[30][1]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|mem[31][1]~q )))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datab(!\A_SPW_TOP|tx_data|mem[31][1]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[30][1]~q ),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datae(!\A_SPW_TOP|tx_data|mem[63][1]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[62][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux7~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux7~18 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux7~18 .lut_mask = 64'h1B001B551BAA1BFF;
defparam \A_SPW_TOP|tx_data|Mux7~18 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y9_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector552~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector552~0_combout  = ( \A_SPW_TOP|tx_data|mem[60][1]~q  & ( (!\A_SPW_TOP|tx_data|Selector545~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux7~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [1])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[60][1]~q  & ( (\A_SPW_TOP|tx_data|Selector545~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux7~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [1]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [1]),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|tx_data|Selector545~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[60][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector552~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector552~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector552~0 .lut_mask = 64'h00530053FF53FF53;
defparam \A_SPW_TOP|tx_data|Selector552~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y9_N17
dffeas \A_SPW_TOP|tx_data|mem[60][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector552~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[60][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[60][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[60][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y9_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector264~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector264~0_combout  = ( \A_SPW_TOP|tx_data|mem[28][1]~q  & ( (!\A_SPW_TOP|tx_data|Selector257~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux7~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [1]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[28][1]~q  & ( (\A_SPW_TOP|tx_data|Selector257~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux7~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [1])))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\u0|write_data_fifo_tx|data_out [1]),
        .datac(!\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .datad(!\A_SPW_TOP|tx_data|Selector257~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[28][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector264~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector264~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector264~0 .lut_mask = 64'h001B001BFF1BFF1B;
defparam \A_SPW_TOP|tx_data|Selector264~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y9_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|mem[28][1]~feeder (
// Equation(s):
// \A_SPW_TOP|tx_data|mem[28][1]~feeder_combout  = ( \A_SPW_TOP|tx_data|Selector264~0_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector264~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|mem[28][1]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[28][1]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|mem[28][1]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|tx_data|mem[28][1]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y9_N32
dffeas \A_SPW_TOP|tx_data|mem[28][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|tx_data|mem[28][1]~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[28][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[28][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[28][1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y9_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector273~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector273~0_combout  = ( \A_SPW_TOP|tx_data|mem[29][1]~q  & ( (!\A_SPW_TOP|tx_data|Selector266~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux7~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [1]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[29][1]~q  & ( (\A_SPW_TOP|tx_data|Selector266~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux7~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [1])))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\u0|write_data_fifo_tx|data_out [1]),
        .datac(!\A_SPW_TOP|tx_data|Selector266~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[29][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector273~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector273~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector273~0 .lut_mask = 64'h010B010BF1FBF1FB;
defparam \A_SPW_TOP|tx_data|Selector273~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y9_N20
dffeas \A_SPW_TOP|tx_data|mem[29][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector273~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[29][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[29][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[29][1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y9_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector561~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector561~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector554~0_combout  & ((\A_SPW_TOP|tx_data|mem[61][1]~q ))) # (\A_SPW_TOP|tx_data|Selector554~0_combout  & (\u0|write_data_fifo_tx|data_out 
// [1])) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector554~0_combout  & ((\A_SPW_TOP|tx_data|mem[61][1]~q ))) # (\A_SPW_TOP|tx_data|Selector554~0_combout  & (\A_SPW_TOP|tx_data|Mux7~20_combout )) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [1]),
        .datac(!\A_SPW_TOP|tx_data|Selector554~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|mem[61][1]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector561~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector561~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector561~0 .lut_mask = 64'h05F505F503F303F3;
defparam \A_SPW_TOP|tx_data|Selector561~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y9_N38
dffeas \A_SPW_TOP|tx_data|mem[61][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector561~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[61][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[61][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[61][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y9_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux7~16 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux7~16_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [0] & ( \A_SPW_TOP|tx_data|mem[61][1]~q  & ( (\A_SPW_TOP|tx_data|mem[29][1]~q ) # (\A_SPW_TOP|tx_data|wr_ptr [5]) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [0] & ( 
// \A_SPW_TOP|tx_data|mem[61][1]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [5] & ((\A_SPW_TOP|tx_data|mem[28][1]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|mem[60][1]~q )) ) ) ) # ( \A_SPW_TOP|tx_data|wr_ptr [0] & ( 
// !\A_SPW_TOP|tx_data|mem[61][1]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [5] & \A_SPW_TOP|tx_data|mem[29][1]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [0] & ( !\A_SPW_TOP|tx_data|mem[61][1]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [5] & 
// ((\A_SPW_TOP|tx_data|mem[28][1]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|mem[60][1]~q )) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[60][1]~q ),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datac(!\A_SPW_TOP|tx_data|mem[28][1]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[29][1]~q ),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .dataf(!\A_SPW_TOP|tx_data|mem[61][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux7~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux7~16 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux7~16 .lut_mask = 64'h1D1D00CC1D1D33FF;
defparam \A_SPW_TOP|tx_data|Mux7~16 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y9_N57
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector201~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector201~0_combout  = ( \A_SPW_TOP|tx_data|Mux7~20_combout  & ( (!\A_SPW_TOP|tx_data|Selector194~0_combout  & (\A_SPW_TOP|tx_data|mem[21][1]~q )) # (\A_SPW_TOP|tx_data|Selector194~0_combout  & 
// (((!\A_SPW_TOP|tx_data|state_data_write.00~q ) # (\u0|write_data_fifo_tx|data_out [1])))) ) ) # ( !\A_SPW_TOP|tx_data|Mux7~20_combout  & ( (!\A_SPW_TOP|tx_data|Selector194~0_combout  & (\A_SPW_TOP|tx_data|mem[21][1]~q )) # 
// (\A_SPW_TOP|tx_data|Selector194~0_combout  & (((\u0|write_data_fifo_tx|data_out [1] & \A_SPW_TOP|tx_data|state_data_write.00~q )))) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[21][1]~q ),
        .datab(!\u0|write_data_fifo_tx|data_out [1]),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|tx_data|Selector194~0_combout ),
        .datae(!\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector201~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector201~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector201~0 .lut_mask = 64'h550355F3550355F3;
defparam \A_SPW_TOP|tx_data|Selector201~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y9_N53
dffeas \A_SPW_TOP|tx_data|mem[21][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector201~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[21][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[21][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[21][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y9_N21
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector192~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector192~0_combout  = ( \A_SPW_TOP|tx_data|Selector185~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux7~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\u0|write_data_fifo_tx|data_out [1])) ) ) # ( !\A_SPW_TOP|tx_data|Selector185~0_combout  & ( \A_SPW_TOP|tx_data|mem[20][1]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\u0|write_data_fifo_tx|data_out [1]),
        .datac(!\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .datad(!\A_SPW_TOP|tx_data|mem[20][1]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector185~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector192~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector192~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector192~0 .lut_mask = 64'h00FF00FF1B1B1B1B;
defparam \A_SPW_TOP|tx_data|Selector192~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y9_N5
dffeas \A_SPW_TOP|tx_data|mem[20][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector192~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[20][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[20][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[20][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y9_N15
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector480~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector480~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( \A_SPW_TOP|tx_data|Selector473~0_combout  & ( \u0|write_data_fifo_tx|data_out [1] ) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( 
// \A_SPW_TOP|tx_data|Selector473~0_combout  & ( \A_SPW_TOP|tx_data|Mux7~20_combout  ) ) ) # ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( !\A_SPW_TOP|tx_data|Selector473~0_combout  & ( \A_SPW_TOP|tx_data|mem[52][1]~q  ) ) ) # ( 
// !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( !\A_SPW_TOP|tx_data|Selector473~0_combout  & ( \A_SPW_TOP|tx_data|mem[52][1]~q  ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|mem[52][1]~q ),
        .datac(!\u0|write_data_fifo_tx|data_out [1]),
        .datad(gnd),
        .datae(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .dataf(!\A_SPW_TOP|tx_data|Selector473~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector480~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector480~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector480~0 .lut_mask = 64'h3333333355550F0F;
defparam \A_SPW_TOP|tx_data|Selector480~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y9_N41
dffeas \A_SPW_TOP|tx_data|mem[52][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector480~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[52][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[52][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[52][1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y9_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector489~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector489~0_combout  = ( \A_SPW_TOP|tx_data|Mux7~20_combout  & ( \A_SPW_TOP|tx_data|mem[53][1]~q  & ( ((!\A_SPW_TOP|tx_data|Selector482~0_combout ) # (!\A_SPW_TOP|tx_data|state_data_write.00~q )) # (\u0|write_data_fifo_tx|data_out 
// [1]) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux7~20_combout  & ( \A_SPW_TOP|tx_data|mem[53][1]~q  & ( (!\A_SPW_TOP|tx_data|Selector482~0_combout ) # ((\u0|write_data_fifo_tx|data_out [1] & \A_SPW_TOP|tx_data|state_data_write.00~q )) ) ) ) # ( 
// \A_SPW_TOP|tx_data|Mux7~20_combout  & ( !\A_SPW_TOP|tx_data|mem[53][1]~q  & ( (\A_SPW_TOP|tx_data|Selector482~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q ) # (\u0|write_data_fifo_tx|data_out [1]))) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|Mux7~20_combout  & ( !\A_SPW_TOP|tx_data|mem[53][1]~q  & ( (\u0|write_data_fifo_tx|data_out [1] & (\A_SPW_TOP|tx_data|Selector482~0_combout  & \A_SPW_TOP|tx_data|state_data_write.00~q )) ) ) )

        .dataa(gnd),
        .datab(!\u0|write_data_fifo_tx|data_out [1]),
        .datac(!\A_SPW_TOP|tx_data|Selector482~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(!\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .dataf(!\A_SPW_TOP|tx_data|mem[53][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector489~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector489~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector489~0 .lut_mask = 64'h00030F03F0F3FFF3;
defparam \A_SPW_TOP|tx_data|Selector489~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y9_N50
dffeas \A_SPW_TOP|tx_data|mem[53][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector489~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[53][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[53][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[53][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y9_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux7~15 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux7~15_combout  = ( \A_SPW_TOP|tx_data|mem[53][1]~q  & ( \A_SPW_TOP|tx_data|wr_ptr [5] & ( (\A_SPW_TOP|tx_data|mem[52][1]~q ) # (\A_SPW_TOP|tx_data|wr_ptr [0]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[53][1]~q  & ( \A_SPW_TOP|tx_data|wr_ptr 
// [5] & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & \A_SPW_TOP|tx_data|mem[52][1]~q ) ) ) ) # ( \A_SPW_TOP|tx_data|mem[53][1]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [5] & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|mem[20][1]~q ))) # 
// (\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|mem[21][1]~q )) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[53][1]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [5] & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|mem[20][1]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr 
// [0] & (\A_SPW_TOP|tx_data|mem[21][1]~q )) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[21][1]~q ),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datac(!\A_SPW_TOP|tx_data|mem[20][1]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[52][1]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[53][1]~q ),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux7~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux7~15 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux7~15 .lut_mask = 64'h1D1D1D1D00CC33FF;
defparam \A_SPW_TOP|tx_data|Mux7~15 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y9_N9
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux7~19 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux7~19_combout  = ( \A_SPW_TOP|tx_data|Mux7~16_combout  & ( \A_SPW_TOP|tx_data|Mux7~15_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [1]) # ((!\A_SPW_TOP|tx_data|wr_ptr [3] & (\A_SPW_TOP|tx_data|Mux7~17_combout )) # 
// (\A_SPW_TOP|tx_data|wr_ptr [3] & ((\A_SPW_TOP|tx_data|Mux7~18_combout )))) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux7~16_combout  & ( \A_SPW_TOP|tx_data|Mux7~15_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [1] & (((!\A_SPW_TOP|tx_data|wr_ptr [3])))) # 
// (\A_SPW_TOP|tx_data|wr_ptr [1] & ((!\A_SPW_TOP|tx_data|wr_ptr [3] & (\A_SPW_TOP|tx_data|Mux7~17_combout )) # (\A_SPW_TOP|tx_data|wr_ptr [3] & ((\A_SPW_TOP|tx_data|Mux7~18_combout ))))) ) ) ) # ( \A_SPW_TOP|tx_data|Mux7~16_combout  & ( 
// !\A_SPW_TOP|tx_data|Mux7~15_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [1] & (((\A_SPW_TOP|tx_data|wr_ptr [3])))) # (\A_SPW_TOP|tx_data|wr_ptr [1] & ((!\A_SPW_TOP|tx_data|wr_ptr [3] & (\A_SPW_TOP|tx_data|Mux7~17_combout )) # (\A_SPW_TOP|tx_data|wr_ptr [3] & 
// ((\A_SPW_TOP|tx_data|Mux7~18_combout ))))) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux7~16_combout  & ( !\A_SPW_TOP|tx_data|Mux7~15_combout  & ( (\A_SPW_TOP|tx_data|wr_ptr [1] & ((!\A_SPW_TOP|tx_data|wr_ptr [3] & (\A_SPW_TOP|tx_data|Mux7~17_combout )) # 
// (\A_SPW_TOP|tx_data|wr_ptr [3] & ((\A_SPW_TOP|tx_data|Mux7~18_combout ))))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux7~17_combout ),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datad(!\A_SPW_TOP|tx_data|Mux7~18_combout ),
        .datae(!\A_SPW_TOP|tx_data|Mux7~16_combout ),
        .dataf(!\A_SPW_TOP|tx_data|Mux7~15_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux7~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux7~19 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux7~19 .lut_mask = 64'h10131C1FD0D3DCDF;
defparam \A_SPW_TOP|tx_data|Mux7~19 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y13_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector471~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector471~0_combout  = ( \A_SPW_TOP|tx_data|mem[51][1]~q  & ( (!\A_SPW_TOP|tx_data|Selector464~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux7~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [1])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[51][1]~q  & ( (\A_SPW_TOP|tx_data|Selector464~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux7~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [1]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector464~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [1]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[51][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector471~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector471~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector471~0 .lut_mask = 64'h04070407F4F7F4F7;
defparam \A_SPW_TOP|tx_data|Selector471~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y13_N35
dffeas \A_SPW_TOP|tx_data|mem[51][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector471~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[51][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[51][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[51][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y13_N39
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector462~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector462~0_combout  = ( \u0|write_data_fifo_tx|data_out [1] & ( (!\A_SPW_TOP|tx_data|Selector455~0_combout  & (((\A_SPW_TOP|tx_data|mem[50][1]~q )))) # (\A_SPW_TOP|tx_data|Selector455~0_combout  & 
// (((\A_SPW_TOP|tx_data|state_data_write.00~q )) # (\A_SPW_TOP|tx_data|Mux7~20_combout ))) ) ) # ( !\u0|write_data_fifo_tx|data_out [1] & ( (!\A_SPW_TOP|tx_data|Selector455~0_combout  & (((\A_SPW_TOP|tx_data|mem[50][1]~q )))) # 
// (\A_SPW_TOP|tx_data|Selector455~0_combout  & (\A_SPW_TOP|tx_data|Mux7~20_combout  & (!\A_SPW_TOP|tx_data|state_data_write.00~q ))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[50][1]~q ),
        .datad(!\A_SPW_TOP|tx_data|Selector455~0_combout ),
        .datae(gnd),
        .dataf(!\u0|write_data_fifo_tx|data_out [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector462~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector462~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector462~0 .lut_mask = 64'h0F440F440F770F77;
defparam \A_SPW_TOP|tx_data|Selector462~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y13_N8
dffeas \A_SPW_TOP|tx_data|mem[50][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector462~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[50][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[50][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[50][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y13_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector453~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector453~0_combout  = ( \A_SPW_TOP|tx_data|Selector446~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux7~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\u0|write_data_fifo_tx|data_out [1])) ) ) # ( !\A_SPW_TOP|tx_data|Selector446~0_combout  & ( \A_SPW_TOP|tx_data|mem[49][1]~q  ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [1]),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[49][1]~q ),
        .datad(!\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector446~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector453~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector453~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector453~0 .lut_mask = 64'h0F0F0F0F11DD11DD;
defparam \A_SPW_TOP|tx_data|Selector453~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y13_N56
dffeas \A_SPW_TOP|tx_data|mem[49][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector453~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[49][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[49][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[49][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y13_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector444~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector444~0_combout  = ( \A_SPW_TOP|tx_data|Selector437~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux7~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\u0|write_data_fifo_tx|data_out [1])) ) ) # ( !\A_SPW_TOP|tx_data|Selector437~0_combout  & ( \A_SPW_TOP|tx_data|mem[48][1]~q  ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [1]),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .datad(!\A_SPW_TOP|tx_data|mem[48][1]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector437~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector444~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector444~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector444~0 .lut_mask = 64'h00FF00FF1D1D1D1D;
defparam \A_SPW_TOP|tx_data|Selector444~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y13_N59
dffeas \A_SPW_TOP|tx_data|mem[48][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector444~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[48][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[48][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[48][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y13_N21
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux7~7 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux7~7_combout  = ( \A_SPW_TOP|tx_data|mem[48][1]~q  & ( \A_SPW_TOP|tx_data|wr_ptr [1] & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|mem[50][1]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|mem[51][1]~q )) ) 
// ) ) # ( !\A_SPW_TOP|tx_data|mem[48][1]~q  & ( \A_SPW_TOP|tx_data|wr_ptr [1] & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|mem[50][1]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|mem[51][1]~q )) ) ) ) # ( 
// \A_SPW_TOP|tx_data|mem[48][1]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( (!\A_SPW_TOP|tx_data|wr_ptr [0]) # (\A_SPW_TOP|tx_data|mem[49][1]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[48][1]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( (\A_SPW_TOP|tx_data|wr_ptr [0] 
// & \A_SPW_TOP|tx_data|mem[49][1]~q ) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[51][1]~q ),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datac(!\A_SPW_TOP|tx_data|mem[50][1]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[49][1]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[48][1]~q ),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux7~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux7~7 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux7~7 .lut_mask = 64'h0033CCFF1D1D1D1D;
defparam \A_SPW_TOP|tx_data|Mux7~7 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X51_Y13_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector246~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector246~0_combout  = ( \u0|write_data_fifo_tx|data_out [1] & ( (!\A_SPW_TOP|tx_data|Selector239~0_combout  & (((\A_SPW_TOP|tx_data|mem[26][1]~q )))) # (\A_SPW_TOP|tx_data|Selector239~0_combout  & 
// (((\A_SPW_TOP|tx_data|Mux7~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q ))) ) ) # ( !\u0|write_data_fifo_tx|data_out [1] & ( (!\A_SPW_TOP|tx_data|Selector239~0_combout  & (((\A_SPW_TOP|tx_data|mem[26][1]~q )))) # 
// (\A_SPW_TOP|tx_data|Selector239~0_combout  & (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux7~20_combout ))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|mem[26][1]~q ),
        .datad(!\A_SPW_TOP|tx_data|Selector239~0_combout ),
        .datae(gnd),
        .dataf(!\u0|write_data_fifo_tx|data_out [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector246~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector246~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector246~0 .lut_mask = 64'h0F220F220F770F77;
defparam \A_SPW_TOP|tx_data|Selector246~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X51_Y13_N2
dffeas \A_SPW_TOP|tx_data|mem[26][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector246~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[26][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[26][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[26][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X51_Y13_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector237~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector237~0_combout  = ( \A_SPW_TOP|tx_data|Mux7~20_combout  & ( (!\A_SPW_TOP|tx_data|Selector230~0_combout  & (((\A_SPW_TOP|tx_data|mem[25][1]~q )))) # (\A_SPW_TOP|tx_data|Selector230~0_combout  & 
// ((!\A_SPW_TOP|tx_data|state_data_write.00~q ) # ((\u0|write_data_fifo_tx|data_out [1])))) ) ) # ( !\A_SPW_TOP|tx_data|Mux7~20_combout  & ( (!\A_SPW_TOP|tx_data|Selector230~0_combout  & (((\A_SPW_TOP|tx_data|mem[25][1]~q )))) # 
// (\A_SPW_TOP|tx_data|Selector230~0_combout  & (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [1]))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\u0|write_data_fifo_tx|data_out [1]),
        .datac(!\A_SPW_TOP|tx_data|Selector230~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|mem[25][1]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector237~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector237~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector237~0 .lut_mask = 64'h01F101F10BFB0BFB;
defparam \A_SPW_TOP|tx_data|Selector237~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X51_Y13_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|mem[25][1]~feeder (
// Equation(s):
// \A_SPW_TOP|tx_data|mem[25][1]~feeder_combout  = ( \A_SPW_TOP|tx_data|Selector237~0_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector237~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|mem[25][1]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[25][1]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|mem[25][1]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|tx_data|mem[25][1]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X51_Y13_N38
dffeas \A_SPW_TOP|tx_data|mem[25][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|tx_data|mem[25][1]~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[25][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[25][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[25][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X51_Y13_N57
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector228~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector228~0_combout  = ( \A_SPW_TOP|tx_data|mem[24][1]~q  & ( \A_SPW_TOP|tx_data|Mux7~20_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q ) # ((!\A_SPW_TOP|tx_data|Selector221~0_combout ) # (\u0|write_data_fifo_tx|data_out 
// [1])) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[24][1]~q  & ( \A_SPW_TOP|tx_data|Mux7~20_combout  & ( (\A_SPW_TOP|tx_data|Selector221~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q ) # (\u0|write_data_fifo_tx|data_out [1]))) ) ) ) # ( 
// \A_SPW_TOP|tx_data|mem[24][1]~q  & ( !\A_SPW_TOP|tx_data|Mux7~20_combout  & ( (!\A_SPW_TOP|tx_data|Selector221~0_combout ) # ((\A_SPW_TOP|tx_data|state_data_write.00~q  & \u0|write_data_fifo_tx|data_out [1])) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[24][1]~q  & 
// ( !\A_SPW_TOP|tx_data|Mux7~20_combout  & ( (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Selector221~0_combout  & \u0|write_data_fifo_tx|data_out [1])) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Selector221~0_combout ),
        .datac(!\u0|write_data_fifo_tx|data_out [1]),
        .datad(gnd),
        .datae(!\A_SPW_TOP|tx_data|mem[24][1]~q ),
        .dataf(!\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector228~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector228~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector228~0 .lut_mask = 64'h0101CDCD2323EFEF;
defparam \A_SPW_TOP|tx_data|Selector228~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X51_Y13_N56
dffeas \A_SPW_TOP|tx_data|mem[24][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector228~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[24][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[24][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[24][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X51_Y13_N15
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector255~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector255~0_combout  = ( \A_SPW_TOP|tx_data|Mux7~20_combout  & ( (!\A_SPW_TOP|tx_data|Selector248~0_combout  & (((\A_SPW_TOP|tx_data|mem[27][1]~q )))) # (\A_SPW_TOP|tx_data|Selector248~0_combout  & 
// ((!\A_SPW_TOP|tx_data|state_data_write.00~q ) # ((\u0|write_data_fifo_tx|data_out [1])))) ) ) # ( !\A_SPW_TOP|tx_data|Mux7~20_combout  & ( (!\A_SPW_TOP|tx_data|Selector248~0_combout  & (((\A_SPW_TOP|tx_data|mem[27][1]~q )))) # 
// (\A_SPW_TOP|tx_data|Selector248~0_combout  & (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [1]))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\u0|write_data_fifo_tx|data_out [1]),
        .datac(!\A_SPW_TOP|tx_data|Selector248~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|mem[27][1]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector255~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector255~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector255~0 .lut_mask = 64'h01F101F10BFB0BFB;
defparam \A_SPW_TOP|tx_data|Selector255~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X51_Y13_N27
cyclonev_lcell_comb \A_SPW_TOP|tx_data|mem[27][1]~feeder (
// Equation(s):
// \A_SPW_TOP|tx_data|mem[27][1]~feeder_combout  = ( \A_SPW_TOP|tx_data|Selector255~0_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector255~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|mem[27][1]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[27][1]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|mem[27][1]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|tx_data|mem[27][1]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X51_Y13_N29
dffeas \A_SPW_TOP|tx_data|mem[27][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|tx_data|mem[27][1]~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[27][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[27][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[27][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X51_Y13_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux7~6 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux7~6_combout  = ( \A_SPW_TOP|tx_data|mem[27][1]~q  & ( \A_SPW_TOP|tx_data|wr_ptr [1] & ( (\A_SPW_TOP|tx_data|wr_ptr [0]) # (\A_SPW_TOP|tx_data|mem[26][1]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[27][1]~q  & ( \A_SPW_TOP|tx_data|wr_ptr 
// [1] & ( (\A_SPW_TOP|tx_data|mem[26][1]~q  & !\A_SPW_TOP|tx_data|wr_ptr [0]) ) ) ) # ( \A_SPW_TOP|tx_data|mem[27][1]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|mem[24][1]~q ))) # 
// (\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|mem[25][1]~q )) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[27][1]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|mem[24][1]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr 
// [0] & (\A_SPW_TOP|tx_data|mem[25][1]~q )) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[26][1]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[25][1]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[24][1]~q ),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datae(!\A_SPW_TOP|tx_data|mem[27][1]~q ),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux7~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux7~6 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux7~6 .lut_mask = 64'h0F330F33550055FF;
defparam \A_SPW_TOP|tx_data|Mux7~6 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y13_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector165~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector165~0_combout  = ( \A_SPW_TOP|tx_data|mem[17][1]~q  & ( (!\A_SPW_TOP|tx_data|Selector158~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux7~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [1])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[17][1]~q  & ( (\A_SPW_TOP|tx_data|Selector158~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux7~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [1]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector158~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [1]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[17][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector165~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector165~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector165~0 .lut_mask = 64'h04070407F4F7F4F7;
defparam \A_SPW_TOP|tx_data|Selector165~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y13_N14
dffeas \A_SPW_TOP|tx_data|mem[17][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector165~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[17][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[17][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[17][1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y13_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector174~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector174~0_combout  = ( \A_SPW_TOP|tx_data|mem[18][1]~q  & ( (!\A_SPW_TOP|tx_data|Selector167~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux7~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [1])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[18][1]~q  & ( (\A_SPW_TOP|tx_data|Selector167~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux7~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [1]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\u0|write_data_fifo_tx|data_out [1]),
        .datad(!\A_SPW_TOP|tx_data|Selector167~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[18][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector174~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector174~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector174~0 .lut_mask = 64'h00470047FF47FF47;
defparam \A_SPW_TOP|tx_data|Selector174~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y13_N20
dffeas \A_SPW_TOP|tx_data|mem[18][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector174~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[18][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[18][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[18][1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y13_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector183~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector183~0_combout  = ( \u0|write_data_fifo_tx|data_out [1] & ( (!\A_SPW_TOP|tx_data|Selector176~0_combout  & (((\A_SPW_TOP|tx_data|mem[19][1]~q )))) # (\A_SPW_TOP|tx_data|Selector176~0_combout  & 
// (((\A_SPW_TOP|tx_data|state_data_write.00~q )) # (\A_SPW_TOP|tx_data|Mux7~20_combout ))) ) ) # ( !\u0|write_data_fifo_tx|data_out [1] & ( (!\A_SPW_TOP|tx_data|Selector176~0_combout  & (((\A_SPW_TOP|tx_data|mem[19][1]~q )))) # 
// (\A_SPW_TOP|tx_data|Selector176~0_combout  & (\A_SPW_TOP|tx_data|Mux7~20_combout  & (!\A_SPW_TOP|tx_data|state_data_write.00~q ))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector176~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|mem[19][1]~q ),
        .datae(gnd),
        .dataf(!\u0|write_data_fifo_tx|data_out [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector183~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector183~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector183~0 .lut_mask = 64'h04F404F407F707F7;
defparam \A_SPW_TOP|tx_data|Selector183~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y13_N59
dffeas \A_SPW_TOP|tx_data|mem[19][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector183~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[19][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[19][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[19][1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y13_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector156~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector156~0_combout  = ( \A_SPW_TOP|tx_data|mem[16][1]~q  & ( (!\A_SPW_TOP|tx_data|Selector149~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux7~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [1])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[16][1]~q  & ( (\A_SPW_TOP|tx_data|Selector149~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux7~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [1]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector149~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [1]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[16][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector156~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector156~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector156~0 .lut_mask = 64'h04070407F4F7F4F7;
defparam \A_SPW_TOP|tx_data|Selector156~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y13_N17
dffeas \A_SPW_TOP|tx_data|mem[16][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector156~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[16][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[16][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[16][1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y13_N9
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux7~5 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux7~5_combout  = ( \A_SPW_TOP|tx_data|mem[19][1]~q  & ( \A_SPW_TOP|tx_data|mem[16][1]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & (((!\A_SPW_TOP|tx_data|wr_ptr [1]) # (\A_SPW_TOP|tx_data|mem[18][1]~q )))) # (\A_SPW_TOP|tx_data|wr_ptr [0] 
// & (((\A_SPW_TOP|tx_data|wr_ptr [1])) # (\A_SPW_TOP|tx_data|mem[17][1]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[19][1]~q  & ( \A_SPW_TOP|tx_data|mem[16][1]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & (((!\A_SPW_TOP|tx_data|wr_ptr [1]) # 
// (\A_SPW_TOP|tx_data|mem[18][1]~q )))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|mem[17][1]~q  & (!\A_SPW_TOP|tx_data|wr_ptr [1]))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[19][1]~q  & ( !\A_SPW_TOP|tx_data|mem[16][1]~q  & ( 
// (!\A_SPW_TOP|tx_data|wr_ptr [0] & (((\A_SPW_TOP|tx_data|wr_ptr [1] & \A_SPW_TOP|tx_data|mem[18][1]~q )))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & (((\A_SPW_TOP|tx_data|wr_ptr [1])) # (\A_SPW_TOP|tx_data|mem[17][1]~q ))) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|mem[19][1]~q  & ( !\A_SPW_TOP|tx_data|mem[16][1]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & (((\A_SPW_TOP|tx_data|wr_ptr [1] & \A_SPW_TOP|tx_data|mem[18][1]~q )))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|mem[17][1]~q  & 
// (!\A_SPW_TOP|tx_data|wr_ptr [1]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datab(!\A_SPW_TOP|tx_data|mem[17][1]~q ),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datad(!\A_SPW_TOP|tx_data|mem[18][1]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[19][1]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[16][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux7~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux7~5 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux7~5 .lut_mask = 64'h101A151FB0BAB5BF;
defparam \A_SPW_TOP|tx_data|Mux7~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y13_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector543~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector543~0_combout  = ( \A_SPW_TOP|tx_data|mem[59][1]~q  & ( (!\A_SPW_TOP|tx_data|Selector536~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux7~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [1]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[59][1]~q  & ( (\A_SPW_TOP|tx_data|Selector536~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux7~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [1])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [1]),
        .datab(!\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector536~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[59][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector543~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector543~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector543~0 .lut_mask = 64'h03050305F3F5F3F5;
defparam \A_SPW_TOP|tx_data|Selector543~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y13_N35
dffeas \A_SPW_TOP|tx_data|mem[59][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector543~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[59][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[59][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[59][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y13_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector525~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector525~0_combout  = ( \A_SPW_TOP|tx_data|mem[57][1]~q  & ( (!\A_SPW_TOP|tx_data|Selector518~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux7~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [1])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[57][1]~q  & ( (\A_SPW_TOP|tx_data|Selector518~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux7~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [1]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector518~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [1]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[57][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector525~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector525~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector525~0 .lut_mask = 64'h02070207F2F7F2F7;
defparam \A_SPW_TOP|tx_data|Selector525~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y13_N8
dffeas \A_SPW_TOP|tx_data|mem[57][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector525~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[57][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[57][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[57][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y13_N21
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector516~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector516~0_combout  = ( \A_SPW_TOP|tx_data|mem[56][1]~q  & ( (!\A_SPW_TOP|tx_data|Selector509~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux7~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [1]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[56][1]~q  & ( (\A_SPW_TOP|tx_data|Selector509~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux7~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [1])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [1]),
        .datab(!\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector509~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[56][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector516~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector516~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector516~0 .lut_mask = 64'h03050305F3F5F3F5;
defparam \A_SPW_TOP|tx_data|Selector516~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y13_N11
dffeas \A_SPW_TOP|tx_data|mem[56][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector516~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[56][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[56][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[56][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y13_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector534~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector534~0_combout  = ( \A_SPW_TOP|tx_data|Selector527~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux7~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [1]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector527~0_combout  & ( \A_SPW_TOP|tx_data|mem[58][1]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .datac(!\u0|write_data_fifo_tx|data_out [1]),
        .datad(!\A_SPW_TOP|tx_data|mem[58][1]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector527~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector534~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector534~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector534~0 .lut_mask = 64'h00FF00FF27272727;
defparam \A_SPW_TOP|tx_data|Selector534~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y13_N2
dffeas \A_SPW_TOP|tx_data|mem[58][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector534~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[58][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[58][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[58][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y13_N45
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux7~8 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux7~8_combout  = ( \A_SPW_TOP|tx_data|mem[58][1]~q  & ( \A_SPW_TOP|tx_data|wr_ptr [0] & ( (!\A_SPW_TOP|tx_data|wr_ptr [1] & ((\A_SPW_TOP|tx_data|mem[57][1]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|mem[59][1]~q )) ) 
// ) ) # ( !\A_SPW_TOP|tx_data|mem[58][1]~q  & ( \A_SPW_TOP|tx_data|wr_ptr [0] & ( (!\A_SPW_TOP|tx_data|wr_ptr [1] & ((\A_SPW_TOP|tx_data|mem[57][1]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|mem[59][1]~q )) ) ) ) # ( 
// \A_SPW_TOP|tx_data|mem[58][1]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [0] & ( (\A_SPW_TOP|tx_data|wr_ptr [1]) # (\A_SPW_TOP|tx_data|mem[56][1]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[58][1]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [0] & ( 
// (\A_SPW_TOP|tx_data|mem[56][1]~q  & !\A_SPW_TOP|tx_data|wr_ptr [1]) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[59][1]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[57][1]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[56][1]~q ),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datae(!\A_SPW_TOP|tx_data|mem[58][1]~q ),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux7~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux7~8 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux7~8 .lut_mask = 64'h0F000FFF33553355;
defparam \A_SPW_TOP|tx_data|Mux7~8 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y13_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux7~9 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux7~9_combout  = ( \A_SPW_TOP|tx_data|Mux7~5_combout  & ( \A_SPW_TOP|tx_data|Mux7~8_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [5] & (((!\A_SPW_TOP|tx_data|wr_ptr [3]) # (\A_SPW_TOP|tx_data|Mux7~6_combout )))) # 
// (\A_SPW_TOP|tx_data|wr_ptr [5] & (((\A_SPW_TOP|tx_data|wr_ptr [3])) # (\A_SPW_TOP|tx_data|Mux7~7_combout ))) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux7~5_combout  & ( \A_SPW_TOP|tx_data|Mux7~8_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [5] & 
// (((\A_SPW_TOP|tx_data|wr_ptr [3] & \A_SPW_TOP|tx_data|Mux7~6_combout )))) # (\A_SPW_TOP|tx_data|wr_ptr [5] & (((\A_SPW_TOP|tx_data|wr_ptr [3])) # (\A_SPW_TOP|tx_data|Mux7~7_combout ))) ) ) ) # ( \A_SPW_TOP|tx_data|Mux7~5_combout  & ( 
// !\A_SPW_TOP|tx_data|Mux7~8_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [5] & (((!\A_SPW_TOP|tx_data|wr_ptr [3]) # (\A_SPW_TOP|tx_data|Mux7~6_combout )))) # (\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|Mux7~7_combout  & (!\A_SPW_TOP|tx_data|wr_ptr 
// [3]))) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux7~5_combout  & ( !\A_SPW_TOP|tx_data|Mux7~8_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [5] & (((\A_SPW_TOP|tx_data|wr_ptr [3] & \A_SPW_TOP|tx_data|Mux7~6_combout )))) # (\A_SPW_TOP|tx_data|wr_ptr [5] & 
// (\A_SPW_TOP|tx_data|Mux7~7_combout  & (!\A_SPW_TOP|tx_data|wr_ptr [3]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux7~7_combout ),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datad(!\A_SPW_TOP|tx_data|Mux7~6_combout ),
        .datae(!\A_SPW_TOP|tx_data|Mux7~5_combout ),
        .dataf(!\A_SPW_TOP|tx_data|Mux7~8_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux7~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux7~9 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux7~9 .lut_mask = 64'h101CD0DC131FD3DF;
defparam \A_SPW_TOP|tx_data|Mux7~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y9_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector426~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector426~0_combout  = ( \u0|write_data_fifo_tx|data_out [1] & ( \A_SPW_TOP|tx_data|Selector419~0_combout  & ( (\A_SPW_TOP|tx_data|Mux7~20_combout ) # (\A_SPW_TOP|tx_data|state_data_write.00~q ) ) ) ) # ( 
// !\u0|write_data_fifo_tx|data_out [1] & ( \A_SPW_TOP|tx_data|Selector419~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & \A_SPW_TOP|tx_data|Mux7~20_combout ) ) ) ) # ( \u0|write_data_fifo_tx|data_out [1] & ( 
// !\A_SPW_TOP|tx_data|Selector419~0_combout  & ( \A_SPW_TOP|tx_data|mem[46][1]~q  ) ) ) # ( !\u0|write_data_fifo_tx|data_out [1] & ( !\A_SPW_TOP|tx_data|Selector419~0_combout  & ( \A_SPW_TOP|tx_data|mem[46][1]~q  ) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[46][1]~q ),
        .datac(!\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .datad(gnd),
        .datae(!\u0|write_data_fifo_tx|data_out [1]),
        .dataf(!\A_SPW_TOP|tx_data|Selector419~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector426~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector426~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector426~0 .lut_mask = 64'h333333330A0A5F5F;
defparam \A_SPW_TOP|tx_data|Selector426~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y9_N44
dffeas \A_SPW_TOP|tx_data|mem[46][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector426~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[46][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[46][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[46][1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y9_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector435~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector435~0_combout  = ( \A_SPW_TOP|tx_data|Selector428~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux7~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\u0|write_data_fifo_tx|data_out [1])) ) ) # ( !\A_SPW_TOP|tx_data|Selector428~0_combout  & ( \A_SPW_TOP|tx_data|mem[47][1]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\u0|write_data_fifo_tx|data_out [1]),
        .datac(!\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .datad(!\A_SPW_TOP|tx_data|mem[47][1]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector428~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector435~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector435~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector435~0 .lut_mask = 64'h00FF00FF1B1B1B1B;
defparam \A_SPW_TOP|tx_data|Selector435~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y9_N29
dffeas \A_SPW_TOP|tx_data|mem[47][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector435~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[47][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[47][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[47][1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y9_N33
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector417~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector417~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector410~0_combout  & ((\A_SPW_TOP|tx_data|mem[45][1]~q ))) # (\A_SPW_TOP|tx_data|Selector410~0_combout  & (\u0|write_data_fifo_tx|data_out 
// [1])) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector410~0_combout  & ((\A_SPW_TOP|tx_data|mem[45][1]~q ))) # (\A_SPW_TOP|tx_data|Selector410~0_combout  & (\A_SPW_TOP|tx_data|Mux7~20_combout )) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [1]),
        .datac(!\A_SPW_TOP|tx_data|Selector410~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|mem[45][1]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector417~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector417~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector417~0 .lut_mask = 64'h05F505F503F303F3;
defparam \A_SPW_TOP|tx_data|Selector417~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y9_N23
dffeas \A_SPW_TOP|tx_data|mem[45][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector417~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[45][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[45][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[45][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y9_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector408~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector408~0_combout  = ( \u0|write_data_fifo_tx|data_out [1] & ( (!\A_SPW_TOP|tx_data|Selector401~0_combout  & (((\A_SPW_TOP|tx_data|mem[44][1]~q )))) # (\A_SPW_TOP|tx_data|Selector401~0_combout  & 
// (((\A_SPW_TOP|tx_data|state_data_write.00~q )) # (\A_SPW_TOP|tx_data|Mux7~20_combout ))) ) ) # ( !\u0|write_data_fifo_tx|data_out [1] & ( (!\A_SPW_TOP|tx_data|Selector401~0_combout  & (((\A_SPW_TOP|tx_data|mem[44][1]~q )))) # 
// (\A_SPW_TOP|tx_data|Selector401~0_combout  & (\A_SPW_TOP|tx_data|Mux7~20_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q )))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|mem[44][1]~q ),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|tx_data|Selector401~0_combout ),
        .datae(!\u0|write_data_fifo_tx|data_out [1]),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector408~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector408~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector408~0 .lut_mask = 64'h3350335F3350335F;
defparam \A_SPW_TOP|tx_data|Selector408~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y9_N8
dffeas \A_SPW_TOP|tx_data|mem[44][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector408~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[44][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[44][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[44][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y9_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux7~13 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux7~13_combout  = ( \A_SPW_TOP|tx_data|mem[45][1]~q  & ( \A_SPW_TOP|tx_data|mem[44][1]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [1]) # ((!\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|mem[46][1]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [0] & 
// ((\A_SPW_TOP|tx_data|mem[47][1]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[45][1]~q  & ( \A_SPW_TOP|tx_data|mem[44][1]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & (((!\A_SPW_TOP|tx_data|wr_ptr [1])) # (\A_SPW_TOP|tx_data|mem[46][1]~q ))) # 
// (\A_SPW_TOP|tx_data|wr_ptr [0] & (((\A_SPW_TOP|tx_data|wr_ptr [1] & \A_SPW_TOP|tx_data|mem[47][1]~q )))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[45][1]~q  & ( !\A_SPW_TOP|tx_data|mem[44][1]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & 
// (\A_SPW_TOP|tx_data|mem[46][1]~q  & (\A_SPW_TOP|tx_data|wr_ptr [1]))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & (((!\A_SPW_TOP|tx_data|wr_ptr [1]) # (\A_SPW_TOP|tx_data|mem[47][1]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[45][1]~q  & ( 
// !\A_SPW_TOP|tx_data|mem[44][1]~q  & ( (\A_SPW_TOP|tx_data|wr_ptr [1] & ((!\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|mem[46][1]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|mem[47][1]~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datab(!\A_SPW_TOP|tx_data|mem[46][1]~q ),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datad(!\A_SPW_TOP|tx_data|mem[47][1]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[45][1]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[44][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux7~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux7~13 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux7~13 .lut_mask = 64'h02075257A2A7F2F7;
defparam \A_SPW_TOP|tx_data|Mux7~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y13_N27
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector66~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector66~0_combout  = ( \A_SPW_TOP|tx_data|mem[6][1]~q  & ( (!\A_SPW_TOP|tx_data|Selector59~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux7~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [1]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[6][1]~q  & ( (\A_SPW_TOP|tx_data|Selector59~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux7~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [1])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [1]),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector59~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[6][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector66~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector66~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector66~0 .lut_mask = 64'h010D010DF1FDF1FD;
defparam \A_SPW_TOP|tx_data|Selector66~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y13_N53
dffeas \A_SPW_TOP|tx_data|mem[6][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector66~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[6][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[6][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[6][1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y9_N45
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector57~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector57~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector50~0_combout  & ((\A_SPW_TOP|tx_data|mem[5][1]~q ))) # (\A_SPW_TOP|tx_data|Selector50~0_combout  & (\u0|write_data_fifo_tx|data_out 
// [1])) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector50~0_combout  & ((\A_SPW_TOP|tx_data|mem[5][1]~q ))) # (\A_SPW_TOP|tx_data|Selector50~0_combout  & (\A_SPW_TOP|tx_data|Mux7~20_combout )) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [1]),
        .datac(!\A_SPW_TOP|tx_data|mem[5][1]~q ),
        .datad(!\A_SPW_TOP|tx_data|Selector50~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector57~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector57~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector57~0 .lut_mask = 64'h0F550F550F330F33;
defparam \A_SPW_TOP|tx_data|Selector57~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y9_N41
dffeas \A_SPW_TOP|tx_data|mem[5][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector57~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[5][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[5][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[5][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y9_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector48~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector48~0_combout  = ( \A_SPW_TOP|tx_data|Selector41~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux7~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out 
// [1]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector41~0_combout  & ( \A_SPW_TOP|tx_data|mem[4][1]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|mem[4][1]~q ),
        .datad(!\u0|write_data_fifo_tx|data_out [1]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector41~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector48~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector48~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector48~0 .lut_mask = 64'h0F0F0F0F22772277;
defparam \A_SPW_TOP|tx_data|Selector48~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y9_N20
dffeas \A_SPW_TOP|tx_data|mem[4][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector48~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[4][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[4][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[4][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y9_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector75~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector75~0_combout  = ( \A_SPW_TOP|tx_data|mem[7][1]~q  & ( (!\A_SPW_TOP|tx_data|Selector68~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux7~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [1])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[7][1]~q  & ( (\A_SPW_TOP|tx_data|Selector68~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux7~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [1]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector68~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [1]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[7][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector75~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector75~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector75~0 .lut_mask = 64'h04070407F4F7F4F7;
defparam \A_SPW_TOP|tx_data|Selector75~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y9_N41
dffeas \A_SPW_TOP|tx_data|mem[7][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector75~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[7][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[7][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[7][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y9_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux7~10 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux7~10_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [1] & ( \A_SPW_TOP|tx_data|mem[7][1]~q  & ( (\A_SPW_TOP|tx_data|mem[6][1]~q ) # (\A_SPW_TOP|tx_data|wr_ptr [0]) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( \A_SPW_TOP|tx_data|mem[7][1]~q  
// & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|mem[4][1]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|mem[5][1]~q )) ) ) ) # ( \A_SPW_TOP|tx_data|wr_ptr [1] & ( !\A_SPW_TOP|tx_data|mem[7][1]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr 
// [0] & \A_SPW_TOP|tx_data|mem[6][1]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( !\A_SPW_TOP|tx_data|mem[7][1]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|mem[4][1]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & 
// (\A_SPW_TOP|tx_data|mem[5][1]~q )) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datab(!\A_SPW_TOP|tx_data|mem[6][1]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[5][1]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[4][1]~q ),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .dataf(!\A_SPW_TOP|tx_data|mem[7][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux7~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux7~10 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux7~10 .lut_mask = 64'h05AF222205AF7777;
defparam \A_SPW_TOP|tx_data|Mux7~10 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y9_N21
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector363~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector363~0_combout  = ( \A_SPW_TOP|tx_data|Selector356~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux7~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [1]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector356~0_combout  & ( \A_SPW_TOP|tx_data|mem[39][1]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[39][1]~q ),
        .datad(!\u0|write_data_fifo_tx|data_out [1]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector356~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector363~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector363~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector363~0 .lut_mask = 64'h0F0F0F0F44774477;
defparam \A_SPW_TOP|tx_data|Selector363~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y9_N11
dffeas \A_SPW_TOP|tx_data|mem[39][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector363~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[39][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[39][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[39][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y13_N39
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector354~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector354~0_combout  = ( \u0|write_data_fifo_tx|data_out [1] & ( (!\A_SPW_TOP|tx_data|Selector347~0_combout  & (((\A_SPW_TOP|tx_data|mem[38][1]~q )))) # (\A_SPW_TOP|tx_data|Selector347~0_combout  & 
// (((\A_SPW_TOP|tx_data|Mux7~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q ))) ) ) # ( !\u0|write_data_fifo_tx|data_out [1] & ( (!\A_SPW_TOP|tx_data|Selector347~0_combout  & (((\A_SPW_TOP|tx_data|mem[38][1]~q )))) # 
// (\A_SPW_TOP|tx_data|Selector347~0_combout  & (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux7~20_combout ))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector347~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|mem[38][1]~q ),
        .datae(gnd),
        .dataf(!\u0|write_data_fifo_tx|data_out [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector354~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector354~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector354~0 .lut_mask = 64'h02F202F207F707F7;
defparam \A_SPW_TOP|tx_data|Selector354~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y13_N5
dffeas \A_SPW_TOP|tx_data|mem[38][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector354~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[38][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[38][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[38][1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y9_N57
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector345~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector345~0_combout  = ( \A_SPW_TOP|tx_data|mem[37][1]~q  & ( (!\A_SPW_TOP|tx_data|Selector338~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux7~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [1])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[37][1]~q  & ( (\A_SPW_TOP|tx_data|Selector338~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux7~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [1]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\u0|write_data_fifo_tx|data_out [1]),
        .datad(!\A_SPW_TOP|tx_data|Selector338~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[37][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector345~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector345~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector345~0 .lut_mask = 64'h00470047FF47FF47;
defparam \A_SPW_TOP|tx_data|Selector345~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y9_N11
dffeas \A_SPW_TOP|tx_data|mem[37][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector345~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[37][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[37][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[37][1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y9_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector336~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector336~0_combout  = ( \u0|write_data_fifo_tx|data_out [1] & ( (!\A_SPW_TOP|tx_data|Selector329~0_combout  & (((\A_SPW_TOP|tx_data|mem[36][1]~q )))) # (\A_SPW_TOP|tx_data|Selector329~0_combout  & 
// (((\A_SPW_TOP|tx_data|state_data_write.00~q )) # (\A_SPW_TOP|tx_data|Mux7~20_combout ))) ) ) # ( !\u0|write_data_fifo_tx|data_out [1] & ( (!\A_SPW_TOP|tx_data|Selector329~0_combout  & (((\A_SPW_TOP|tx_data|mem[36][1]~q )))) # 
// (\A_SPW_TOP|tx_data|Selector329~0_combout  & (\A_SPW_TOP|tx_data|Mux7~20_combout  & (!\A_SPW_TOP|tx_data|state_data_write.00~q ))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[36][1]~q ),
        .datad(!\A_SPW_TOP|tx_data|Selector329~0_combout ),
        .datae(gnd),
        .dataf(!\u0|write_data_fifo_tx|data_out [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector336~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector336~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector336~0 .lut_mask = 64'h0F440F440F770F77;
defparam \A_SPW_TOP|tx_data|Selector336~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y9_N53
dffeas \A_SPW_TOP|tx_data|mem[36][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector336~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[36][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[36][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[36][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y9_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux7~12 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux7~12_combout  = ( \A_SPW_TOP|tx_data|mem[37][1]~q  & ( \A_SPW_TOP|tx_data|mem[36][1]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [1]) # ((!\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|mem[38][1]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [0] 
// & (\A_SPW_TOP|tx_data|mem[39][1]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[37][1]~q  & ( \A_SPW_TOP|tx_data|mem[36][1]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [1] & (((!\A_SPW_TOP|tx_data|wr_ptr [0])))) # (\A_SPW_TOP|tx_data|wr_ptr [1] & 
// ((!\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|mem[38][1]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|mem[39][1]~q )))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[37][1]~q  & ( !\A_SPW_TOP|tx_data|mem[36][1]~q  & ( 
// (!\A_SPW_TOP|tx_data|wr_ptr [1] & (((\A_SPW_TOP|tx_data|wr_ptr [0])))) # (\A_SPW_TOP|tx_data|wr_ptr [1] & ((!\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|mem[38][1]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|mem[39][1]~q )))) ) ) 
// ) # ( !\A_SPW_TOP|tx_data|mem[37][1]~q  & ( !\A_SPW_TOP|tx_data|mem[36][1]~q  & ( (\A_SPW_TOP|tx_data|wr_ptr [1] & ((!\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|mem[38][1]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|mem[39][1]~q 
// )))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datab(!\A_SPW_TOP|tx_data|mem[39][1]~q ),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datad(!\A_SPW_TOP|tx_data|mem[38][1]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[37][1]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[36][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux7~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux7~12 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux7~12 .lut_mask = 64'h01510B5BA1F1ABFB;
defparam \A_SPW_TOP|tx_data|Mux7~12 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y9_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector138~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector138~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( \A_SPW_TOP|tx_data|mem[14][1]~q  & ( (!\A_SPW_TOP|tx_data|Selector131~0_combout ) # (\u0|write_data_fifo_tx|data_out [1]) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( \A_SPW_TOP|tx_data|mem[14][1]~q  & ( (!\A_SPW_TOP|tx_data|Selector131~0_combout ) # (\A_SPW_TOP|tx_data|Mux7~20_combout ) ) ) ) # ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( 
// !\A_SPW_TOP|tx_data|mem[14][1]~q  & ( (\u0|write_data_fifo_tx|data_out [1] & \A_SPW_TOP|tx_data|Selector131~0_combout ) ) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( !\A_SPW_TOP|tx_data|mem[14][1]~q  & ( (\A_SPW_TOP|tx_data|Mux7~20_combout  & 
// \A_SPW_TOP|tx_data|Selector131~0_combout ) ) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [1]),
        .datab(!\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector131~0_combout ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[14][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector138~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector138~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector138~0 .lut_mask = 64'h03030505F3F3F5F5;
defparam \A_SPW_TOP|tx_data|Selector138~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y9_N26
dffeas \A_SPW_TOP|tx_data|mem[14][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector138~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[14][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[14][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[14][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y9_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector147~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector147~0_combout  = ( \A_SPW_TOP|tx_data|mem[15][1]~q  & ( (!\A_SPW_TOP|tx_data|Selector140~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux7~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [1]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[15][1]~q  & ( (\A_SPW_TOP|tx_data|Selector140~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux7~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [1])))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\u0|write_data_fifo_tx|data_out [1]),
        .datac(!\A_SPW_TOP|tx_data|Selector140~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[15][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector147~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector147~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector147~0 .lut_mask = 64'h010B010BF1FBF1FB;
defparam \A_SPW_TOP|tx_data|Selector147~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y9_N41
dffeas \A_SPW_TOP|tx_data|mem[15][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector147~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[15][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[15][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[15][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y9_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector120~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector120~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( \A_SPW_TOP|tx_data|mem[12][1]~q  & ( (!\A_SPW_TOP|tx_data|Selector113~0_combout ) # (\u0|write_data_fifo_tx|data_out [1]) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( \A_SPW_TOP|tx_data|mem[12][1]~q  & ( (!\A_SPW_TOP|tx_data|Selector113~0_combout ) # (\A_SPW_TOP|tx_data|Mux7~20_combout ) ) ) ) # ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( 
// !\A_SPW_TOP|tx_data|mem[12][1]~q  & ( (\A_SPW_TOP|tx_data|Selector113~0_combout  & \u0|write_data_fifo_tx|data_out [1]) ) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( !\A_SPW_TOP|tx_data|mem[12][1]~q  & ( (\A_SPW_TOP|tx_data|Mux7~20_combout  & 
// \A_SPW_TOP|tx_data|Selector113~0_combout ) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|Selector113~0_combout ),
        .datac(gnd),
        .datad(!\u0|write_data_fifo_tx|data_out [1]),
        .datae(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[12][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector120~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector120~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector120~0 .lut_mask = 64'h11110033DDDDCCFF;
defparam \A_SPW_TOP|tx_data|Selector120~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y9_N53
dffeas \A_SPW_TOP|tx_data|mem[12][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector120~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[12][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[12][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[12][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y9_N27
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux7~11 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux7~11_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [0] & ( \A_SPW_TOP|tx_data|mem[12][1]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [1] & ((\A_SPW_TOP|tx_data|mem[13][1]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|mem[15][1]~q )) ) 
// ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [0] & ( \A_SPW_TOP|tx_data|mem[12][1]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [1]) # (\A_SPW_TOP|tx_data|mem[14][1]~q ) ) ) ) # ( \A_SPW_TOP|tx_data|wr_ptr [0] & ( !\A_SPW_TOP|tx_data|mem[12][1]~q  & ( 
// (!\A_SPW_TOP|tx_data|wr_ptr [1] & ((\A_SPW_TOP|tx_data|mem[13][1]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|mem[15][1]~q )) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [0] & ( !\A_SPW_TOP|tx_data|mem[12][1]~q  & ( 
// (\A_SPW_TOP|tx_data|mem[14][1]~q  & \A_SPW_TOP|tx_data|wr_ptr [1]) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[14][1]~q ),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datac(!\A_SPW_TOP|tx_data|mem[15][1]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[13][1]~q ),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .dataf(!\A_SPW_TOP|tx_data|mem[12][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux7~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux7~11 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux7~11 .lut_mask = 64'h111103CFDDDD03CF;
defparam \A_SPW_TOP|tx_data|Mux7~11 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y9_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux7~14 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux7~14_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [3] & ( \A_SPW_TOP|tx_data|Mux7~11_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [5]) # (\A_SPW_TOP|tx_data|Mux7~13_combout ) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [3] & ( 
// \A_SPW_TOP|tx_data|Mux7~11_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|Mux7~10_combout )) # (\A_SPW_TOP|tx_data|wr_ptr [5] & ((\A_SPW_TOP|tx_data|Mux7~12_combout ))) ) ) ) # ( \A_SPW_TOP|tx_data|wr_ptr [3] & ( 
// !\A_SPW_TOP|tx_data|Mux7~11_combout  & ( (\A_SPW_TOP|tx_data|Mux7~13_combout  & \A_SPW_TOP|tx_data|wr_ptr [5]) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [3] & ( !\A_SPW_TOP|tx_data|Mux7~11_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [5] & 
// (\A_SPW_TOP|tx_data|Mux7~10_combout )) # (\A_SPW_TOP|tx_data|wr_ptr [5] & ((\A_SPW_TOP|tx_data|Mux7~12_combout ))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux7~13_combout ),
        .datab(!\A_SPW_TOP|tx_data|Mux7~10_combout ),
        .datac(!\A_SPW_TOP|tx_data|Mux7~12_combout ),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .dataf(!\A_SPW_TOP|tx_data|Mux7~11_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux7~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux7~14 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux7~14 .lut_mask = 64'h330F0055330FFF55;
defparam \A_SPW_TOP|tx_data|Mux7~14 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y13_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux7~20 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux7~20_combout  = ( \A_SPW_TOP|tx_data|Mux7~14_combout  & ( \A_SPW_TOP|tx_data|wr_ptr [2] & ( (!\A_SPW_TOP|tx_data|wr_ptr [4]) # (\A_SPW_TOP|tx_data|Mux7~19_combout ) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux7~14_combout  & ( 
// \A_SPW_TOP|tx_data|wr_ptr [2] & ( (\A_SPW_TOP|tx_data|wr_ptr [4] & \A_SPW_TOP|tx_data|Mux7~19_combout ) ) ) ) # ( \A_SPW_TOP|tx_data|Mux7~14_combout  & ( !\A_SPW_TOP|tx_data|wr_ptr [2] & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & 
// (\A_SPW_TOP|tx_data|Mux7~4_combout )) # (\A_SPW_TOP|tx_data|wr_ptr [4] & ((\A_SPW_TOP|tx_data|Mux7~9_combout ))) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux7~14_combout  & ( !\A_SPW_TOP|tx_data|wr_ptr [2] & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & 
// (\A_SPW_TOP|tx_data|Mux7~4_combout )) # (\A_SPW_TOP|tx_data|wr_ptr [4] & ((\A_SPW_TOP|tx_data|Mux7~9_combout ))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux7~4_combout ),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datac(!\A_SPW_TOP|tx_data|Mux7~19_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux7~9_combout ),
        .datae(!\A_SPW_TOP|tx_data|Mux7~14_combout ),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux7~20 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux7~20 .lut_mask = 64'h447744770303CFCF;
defparam \A_SPW_TOP|tx_data|Mux7~20 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y9_N33
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector129~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector129~0_combout  = ( \A_SPW_TOP|tx_data|Selector122~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux7~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [1]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector122~0_combout  & ( \A_SPW_TOP|tx_data|mem[13][1]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux7~20_combout ),
        .datac(!\u0|write_data_fifo_tx|data_out [1]),
        .datad(!\A_SPW_TOP|tx_data|mem[13][1]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector122~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector129~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector129~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector129~0 .lut_mask = 64'h00FF00FF27272727;
defparam \A_SPW_TOP|tx_data|Selector129~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y9_N23
dffeas \A_SPW_TOP|tx_data|mem[13][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector129~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[13][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[13][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[13][1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y9_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux16~12 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux16~12_combout  = ( \A_SPW_TOP|tx_data|mem[29][1]~q  & ( \A_SPW_TOP|tx_data|rd_ptr [3] & ( (\A_SPW_TOP|tx_data|rd_ptr [4]) # (\A_SPW_TOP|tx_data|mem[13][1]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[29][1]~q  & ( \A_SPW_TOP|tx_data|rd_ptr 
// [3] & ( (\A_SPW_TOP|tx_data|mem[13][1]~q  & !\A_SPW_TOP|tx_data|rd_ptr [4]) ) ) ) # ( \A_SPW_TOP|tx_data|mem[29][1]~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [3] & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & (\A_SPW_TOP|tx_data|mem[5][1]~q )) # (\A_SPW_TOP|tx_data|rd_ptr 
// [4] & ((\A_SPW_TOP|tx_data|mem[21][1]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[29][1]~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [3] & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & (\A_SPW_TOP|tx_data|mem[5][1]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [4] & 
// ((\A_SPW_TOP|tx_data|mem[21][1]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[13][1]~q ),
        .datab(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .datac(!\A_SPW_TOP|tx_data|mem[5][1]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[21][1]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[29][1]~q ),
        .dataf(!\A_SPW_TOP|tx_data|rd_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux16~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux16~12 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux16~12 .lut_mask = 64'h0C3F0C3F44447777;
defparam \A_SPW_TOP|tx_data|Mux16~12 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y9_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux16~13 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux16~13_combout  = ( \A_SPW_TOP|tx_data|mem[45][1]~q  & ( \A_SPW_TOP|tx_data|rd_ptr [3] & ( (!\A_SPW_TOP|tx_data|rd_ptr [4]) # (\A_SPW_TOP|tx_data|mem[61][1]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[45][1]~q  & ( \A_SPW_TOP|tx_data|rd_ptr 
// [3] & ( (\A_SPW_TOP|tx_data|mem[61][1]~q  & \A_SPW_TOP|tx_data|rd_ptr [4]) ) ) ) # ( \A_SPW_TOP|tx_data|mem[45][1]~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [3] & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & (\A_SPW_TOP|tx_data|mem[37][1]~q )) # (\A_SPW_TOP|tx_data|rd_ptr 
// [4] & ((\A_SPW_TOP|tx_data|mem[53][1]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[45][1]~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [3] & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & (\A_SPW_TOP|tx_data|mem[37][1]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [4] & 
// ((\A_SPW_TOP|tx_data|mem[53][1]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[61][1]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[37][1]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[53][1]~q ),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .datae(!\A_SPW_TOP|tx_data|mem[45][1]~q ),
        .dataf(!\A_SPW_TOP|tx_data|rd_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux16~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux16~13 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux16~13 .lut_mask = 64'h330F330F0055FF55;
defparam \A_SPW_TOP|tx_data|Mux16~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y9_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux16~10 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux16~10_combout  = ( \A_SPW_TOP|tx_data|rd_ptr [4] & ( \A_SPW_TOP|tx_data|mem[4][1]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [3] & ((\A_SPW_TOP|tx_data|mem[20][1]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [3] & (\A_SPW_TOP|tx_data|mem[28][1]~q )) ) 
// ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [4] & ( \A_SPW_TOP|tx_data|mem[4][1]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [3]) # (\A_SPW_TOP|tx_data|mem[12][1]~q ) ) ) ) # ( \A_SPW_TOP|tx_data|rd_ptr [4] & ( !\A_SPW_TOP|tx_data|mem[4][1]~q  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [3] & ((\A_SPW_TOP|tx_data|mem[20][1]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [3] & (\A_SPW_TOP|tx_data|mem[28][1]~q )) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [4] & ( !\A_SPW_TOP|tx_data|mem[4][1]~q  & ( (\A_SPW_TOP|tx_data|rd_ptr [3] 
// & \A_SPW_TOP|tx_data|mem[12][1]~q ) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[28][1]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[20][1]~q ),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [3]),
        .datad(!\A_SPW_TOP|tx_data|mem[12][1]~q ),
        .datae(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .dataf(!\A_SPW_TOP|tx_data|mem[4][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux16~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux16~10 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux16~10 .lut_mask = 64'h000F3535F0FF3535;
defparam \A_SPW_TOP|tx_data|Mux16~10 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y9_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux16~11 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux16~11_combout  = ( \A_SPW_TOP|tx_data|rd_ptr [4] & ( \A_SPW_TOP|tx_data|mem[52][1]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [3]) # (\A_SPW_TOP|tx_data|mem[60][1]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [4] & ( 
// \A_SPW_TOP|tx_data|mem[52][1]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [3] & (\A_SPW_TOP|tx_data|mem[36][1]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [3] & ((\A_SPW_TOP|tx_data|mem[44][1]~q ))) ) ) ) # ( \A_SPW_TOP|tx_data|rd_ptr [4] & ( 
// !\A_SPW_TOP|tx_data|mem[52][1]~q  & ( (\A_SPW_TOP|tx_data|rd_ptr [3] & \A_SPW_TOP|tx_data|mem[60][1]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [4] & ( !\A_SPW_TOP|tx_data|mem[52][1]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [3] & (\A_SPW_TOP|tx_data|mem[36][1]~q 
// )) # (\A_SPW_TOP|tx_data|rd_ptr [3] & ((\A_SPW_TOP|tx_data|mem[44][1]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[36][1]~q ),
        .datab(!\A_SPW_TOP|tx_data|rd_ptr [3]),
        .datac(!\A_SPW_TOP|tx_data|mem[44][1]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[60][1]~q ),
        .datae(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .dataf(!\A_SPW_TOP|tx_data|mem[52][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux16~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux16~11 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux16~11 .lut_mask = 64'h474700334747CCFF;
defparam \A_SPW_TOP|tx_data|Mux16~11 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y9_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux16~14 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux16~14_combout  = ( \A_SPW_TOP|tx_data|rd_ptr [5] & ( \A_SPW_TOP|tx_data|Mux16~11_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [0]) # (\A_SPW_TOP|tx_data|Mux16~13_combout ) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [5] & ( 
// \A_SPW_TOP|tx_data|Mux16~11_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [0] & ((\A_SPW_TOP|tx_data|Mux16~10_combout ))) # (\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|Mux16~12_combout )) ) ) ) # ( \A_SPW_TOP|tx_data|rd_ptr [5] & ( 
// !\A_SPW_TOP|tx_data|Mux16~11_combout  & ( (\A_SPW_TOP|tx_data|rd_ptr [0] & \A_SPW_TOP|tx_data|Mux16~13_combout ) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [5] & ( !\A_SPW_TOP|tx_data|Mux16~11_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [0] & 
// ((\A_SPW_TOP|tx_data|Mux16~10_combout ))) # (\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|Mux16~12_combout )) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .datab(!\A_SPW_TOP|tx_data|Mux16~12_combout ),
        .datac(!\A_SPW_TOP|tx_data|Mux16~13_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux16~10_combout ),
        .datae(!\A_SPW_TOP|tx_data|rd_ptr [5]),
        .dataf(!\A_SPW_TOP|tx_data|Mux16~11_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux16~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux16~14 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux16~14 .lut_mask = 64'h11BB050511BBAFAF;
defparam \A_SPW_TOP|tx_data|Mux16~14 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X51_Y13_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux16~7 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux16~7_combout  = ( \A_SPW_TOP|tx_data|mem[27][1]~q  & ( \A_SPW_TOP|tx_data|mem[10][1]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [0] & (((!\A_SPW_TOP|tx_data|rd_ptr [4]) # (\A_SPW_TOP|tx_data|mem[26][1]~q )))) # (\A_SPW_TOP|tx_data|rd_ptr [0] 
// & (((\A_SPW_TOP|tx_data|rd_ptr [4])) # (\A_SPW_TOP|tx_data|mem[11][1]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[27][1]~q  & ( \A_SPW_TOP|tx_data|mem[10][1]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [0] & (((!\A_SPW_TOP|tx_data|rd_ptr [4]) # 
// (\A_SPW_TOP|tx_data|mem[26][1]~q )))) # (\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|mem[11][1]~q  & ((!\A_SPW_TOP|tx_data|rd_ptr [4])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[27][1]~q  & ( !\A_SPW_TOP|tx_data|mem[10][1]~q  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [0] & (((\A_SPW_TOP|tx_data|mem[26][1]~q  & \A_SPW_TOP|tx_data|rd_ptr [4])))) # (\A_SPW_TOP|tx_data|rd_ptr [0] & (((\A_SPW_TOP|tx_data|rd_ptr [4])) # (\A_SPW_TOP|tx_data|mem[11][1]~q ))) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|mem[27][1]~q  & ( !\A_SPW_TOP|tx_data|mem[10][1]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [0] & (((\A_SPW_TOP|tx_data|mem[26][1]~q  & \A_SPW_TOP|tx_data|rd_ptr [4])))) # (\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|mem[11][1]~q  & 
// ((!\A_SPW_TOP|tx_data|rd_ptr [4])))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .datab(!\A_SPW_TOP|tx_data|mem[11][1]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[26][1]~q ),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .datae(!\A_SPW_TOP|tx_data|mem[27][1]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[10][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux16~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux16~7 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux16~7 .lut_mask = 64'h110A115FBB0ABB5F;
defparam \A_SPW_TOP|tx_data|Mux16~7 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y13_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux16~6 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux16~6_combout  = ( \A_SPW_TOP|tx_data|mem[50][1]~q  & ( \A_SPW_TOP|tx_data|rd_ptr [0] & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & ((\A_SPW_TOP|tx_data|mem[35][1]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [4] & (\A_SPW_TOP|tx_data|mem[51][1]~q )) ) 
// ) ) # ( !\A_SPW_TOP|tx_data|mem[50][1]~q  & ( \A_SPW_TOP|tx_data|rd_ptr [0] & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & ((\A_SPW_TOP|tx_data|mem[35][1]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [4] & (\A_SPW_TOP|tx_data|mem[51][1]~q )) ) ) ) # ( 
// \A_SPW_TOP|tx_data|mem[50][1]~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [0] & ( (\A_SPW_TOP|tx_data|mem[34][1]~q ) # (\A_SPW_TOP|tx_data|rd_ptr [4]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[50][1]~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [0] & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] 
// & \A_SPW_TOP|tx_data|mem[34][1]~q ) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .datab(!\A_SPW_TOP|tx_data|mem[34][1]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[51][1]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[35][1]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[50][1]~q ),
        .dataf(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux16~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux16~6 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux16~6 .lut_mask = 64'h2222777705AF05AF;
defparam \A_SPW_TOP|tx_data|Mux16~6 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y13_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux16~8 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux16~8_combout  = ( \A_SPW_TOP|tx_data|mem[58][1]~q  & ( \A_SPW_TOP|tx_data|mem[59][1]~q  & ( ((!\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|mem[42][1]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [0] & ((\A_SPW_TOP|tx_data|mem[43][1]~q 
// )))) # (\A_SPW_TOP|tx_data|rd_ptr [4]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[58][1]~q  & ( \A_SPW_TOP|tx_data|mem[59][1]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & ((!\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|mem[42][1]~q )) # 
// (\A_SPW_TOP|tx_data|rd_ptr [0] & ((\A_SPW_TOP|tx_data|mem[43][1]~q ))))) # (\A_SPW_TOP|tx_data|rd_ptr [4] & (((\A_SPW_TOP|tx_data|rd_ptr [0])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[58][1]~q  & ( !\A_SPW_TOP|tx_data|mem[59][1]~q  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [4] & ((!\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|mem[42][1]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [0] & ((\A_SPW_TOP|tx_data|mem[43][1]~q ))))) # (\A_SPW_TOP|tx_data|rd_ptr [4] & (((!\A_SPW_TOP|tx_data|rd_ptr [0])))) ) 
// ) ) # ( !\A_SPW_TOP|tx_data|mem[58][1]~q  & ( !\A_SPW_TOP|tx_data|mem[59][1]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & ((!\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|mem[42][1]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [0] & 
// ((\A_SPW_TOP|tx_data|mem[43][1]~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .datab(!\A_SPW_TOP|tx_data|mem[42][1]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[43][1]~q ),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .datae(!\A_SPW_TOP|tx_data|mem[58][1]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[59][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux16~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux16~8 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux16~8 .lut_mask = 64'h220A770A225F775F;
defparam \A_SPW_TOP|tx_data|Mux16~8 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y13_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux16~5 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux16~5_combout  = ( \A_SPW_TOP|tx_data|mem[18][1]~q  & ( \A_SPW_TOP|tx_data|mem[3][1]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & (((\A_SPW_TOP|tx_data|rd_ptr [0])) # (\A_SPW_TOP|tx_data|mem[2][1]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [4] & 
// (((!\A_SPW_TOP|tx_data|rd_ptr [0]) # (\A_SPW_TOP|tx_data|mem[19][1]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[18][1]~q  & ( \A_SPW_TOP|tx_data|mem[3][1]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & (((\A_SPW_TOP|tx_data|rd_ptr [0])) # 
// (\A_SPW_TOP|tx_data|mem[2][1]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [4] & (((\A_SPW_TOP|tx_data|mem[19][1]~q  & \A_SPW_TOP|tx_data|rd_ptr [0])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[18][1]~q  & ( !\A_SPW_TOP|tx_data|mem[3][1]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr 
// [4] & (\A_SPW_TOP|tx_data|mem[2][1]~q  & ((!\A_SPW_TOP|tx_data|rd_ptr [0])))) # (\A_SPW_TOP|tx_data|rd_ptr [4] & (((!\A_SPW_TOP|tx_data|rd_ptr [0]) # (\A_SPW_TOP|tx_data|mem[19][1]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[18][1]~q  & ( 
// !\A_SPW_TOP|tx_data|mem[3][1]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & (\A_SPW_TOP|tx_data|mem[2][1]~q  & ((!\A_SPW_TOP|tx_data|rd_ptr [0])))) # (\A_SPW_TOP|tx_data|rd_ptr [4] & (((\A_SPW_TOP|tx_data|mem[19][1]~q  & \A_SPW_TOP|tx_data|rd_ptr [0])))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[2][1]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[19][1]~q ),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .datae(!\A_SPW_TOP|tx_data|mem[18][1]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[3][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux16~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux16~5 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux16~5 .lut_mask = 64'h50035F0350F35FF3;
defparam \A_SPW_TOP|tx_data|Mux16~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y13_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux16~9 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux16~9_combout  = ( \A_SPW_TOP|tx_data|Mux16~8_combout  & ( \A_SPW_TOP|tx_data|Mux16~5_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & ((!\A_SPW_TOP|tx_data|rd_ptr [3]) # ((\A_SPW_TOP|tx_data|Mux16~7_combout )))) # 
// (\A_SPW_TOP|tx_data|rd_ptr [5] & (((\A_SPW_TOP|tx_data|Mux16~6_combout )) # (\A_SPW_TOP|tx_data|rd_ptr [3]))) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux16~8_combout  & ( \A_SPW_TOP|tx_data|Mux16~5_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & 
// ((!\A_SPW_TOP|tx_data|rd_ptr [3]) # ((\A_SPW_TOP|tx_data|Mux16~7_combout )))) # (\A_SPW_TOP|tx_data|rd_ptr [5] & (!\A_SPW_TOP|tx_data|rd_ptr [3] & ((\A_SPW_TOP|tx_data|Mux16~6_combout )))) ) ) ) # ( \A_SPW_TOP|tx_data|Mux16~8_combout  & ( 
// !\A_SPW_TOP|tx_data|Mux16~5_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|rd_ptr [3] & (\A_SPW_TOP|tx_data|Mux16~7_combout ))) # (\A_SPW_TOP|tx_data|rd_ptr [5] & (((\A_SPW_TOP|tx_data|Mux16~6_combout )) # (\A_SPW_TOP|tx_data|rd_ptr 
// [3]))) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux16~8_combout  & ( !\A_SPW_TOP|tx_data|Mux16~5_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|rd_ptr [3] & (\A_SPW_TOP|tx_data|Mux16~7_combout ))) # (\A_SPW_TOP|tx_data|rd_ptr [5] & 
// (!\A_SPW_TOP|tx_data|rd_ptr [3] & ((\A_SPW_TOP|tx_data|Mux16~6_combout )))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [5]),
        .datab(!\A_SPW_TOP|tx_data|rd_ptr [3]),
        .datac(!\A_SPW_TOP|tx_data|Mux16~7_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux16~6_combout ),
        .datae(!\A_SPW_TOP|tx_data|Mux16~8_combout ),
        .dataf(!\A_SPW_TOP|tx_data|Mux16~5_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux16~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux16~9 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux16~9 .lut_mask = 64'h024613578ACE9BDF;
defparam \A_SPW_TOP|tx_data|Mux16~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y13_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux16~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux16~1_combout  = ( \A_SPW_TOP|tx_data|mem[49][1]~q  & ( \A_SPW_TOP|tx_data|mem[33][1]~q  & ( ((!\A_SPW_TOP|tx_data|rd_ptr [4] & (\A_SPW_TOP|tx_data|mem[32][1]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [4] & ((\A_SPW_TOP|tx_data|mem[48][1]~q 
// )))) # (\A_SPW_TOP|tx_data|rd_ptr [0]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[49][1]~q  & ( \A_SPW_TOP|tx_data|mem[33][1]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & (((\A_SPW_TOP|tx_data|rd_ptr [0])) # (\A_SPW_TOP|tx_data|mem[32][1]~q ))) # 
// (\A_SPW_TOP|tx_data|rd_ptr [4] & (((\A_SPW_TOP|tx_data|mem[48][1]~q  & !\A_SPW_TOP|tx_data|rd_ptr [0])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[49][1]~q  & ( !\A_SPW_TOP|tx_data|mem[33][1]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & 
// (\A_SPW_TOP|tx_data|mem[32][1]~q  & ((!\A_SPW_TOP|tx_data|rd_ptr [0])))) # (\A_SPW_TOP|tx_data|rd_ptr [4] & (((\A_SPW_TOP|tx_data|rd_ptr [0]) # (\A_SPW_TOP|tx_data|mem[48][1]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[49][1]~q  & ( 
// !\A_SPW_TOP|tx_data|mem[33][1]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [0] & ((!\A_SPW_TOP|tx_data|rd_ptr [4] & (\A_SPW_TOP|tx_data|mem[32][1]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [4] & ((\A_SPW_TOP|tx_data|mem[48][1]~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[32][1]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[48][1]~q ),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .datae(!\A_SPW_TOP|tx_data|mem[49][1]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[33][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux16~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux16~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux16~1 .lut_mask = 64'h5300530F53F053FF;
defparam \A_SPW_TOP|tx_data|Mux16~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y13_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux16~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux16~0_combout  = ( \A_SPW_TOP|tx_data|mem[17][1]~q  & ( \A_SPW_TOP|tx_data|rd_ptr [0] & ( (\A_SPW_TOP|tx_data|rd_ptr [4]) # (\A_SPW_TOP|tx_data|mem[1][1]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[17][1]~q  & ( \A_SPW_TOP|tx_data|rd_ptr 
// [0] & ( (\A_SPW_TOP|tx_data|mem[1][1]~q  & !\A_SPW_TOP|tx_data|rd_ptr [4]) ) ) ) # ( \A_SPW_TOP|tx_data|mem[17][1]~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [0] & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & ((\A_SPW_TOP|tx_data|mem[0][1]~q ))) # 
// (\A_SPW_TOP|tx_data|rd_ptr [4] & (\A_SPW_TOP|tx_data|mem[16][1]~q )) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[17][1]~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [0] & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & ((\A_SPW_TOP|tx_data|mem[0][1]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [4] 
// & (\A_SPW_TOP|tx_data|mem[16][1]~q )) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[1][1]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[16][1]~q ),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .datad(!\A_SPW_TOP|tx_data|mem[0][1]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[17][1]~q ),
        .dataf(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux16~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux16~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux16~0 .lut_mask = 64'h03F303F350505F5F;
defparam \A_SPW_TOP|tx_data|Mux16~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X51_Y13_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux16~2 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux16~2_combout  = ( \A_SPW_TOP|tx_data|rd_ptr [0] & ( \A_SPW_TOP|tx_data|rd_ptr [4] & ( \A_SPW_TOP|tx_data|mem[25][1]~q  ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [0] & ( \A_SPW_TOP|tx_data|rd_ptr [4] & ( \A_SPW_TOP|tx_data|mem[24][1]~q  ) 
// ) ) # ( \A_SPW_TOP|tx_data|rd_ptr [0] & ( !\A_SPW_TOP|tx_data|rd_ptr [4] & ( \A_SPW_TOP|tx_data|mem[9][1]~q  ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [0] & ( !\A_SPW_TOP|tx_data|rd_ptr [4] & ( \A_SPW_TOP|tx_data|mem[8][1]~q  ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[24][1]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[9][1]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[8][1]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[25][1]~q ),
        .datae(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .dataf(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux16~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux16~2 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux16~2 .lut_mask = 64'h0F0F3333555500FF;
defparam \A_SPW_TOP|tx_data|Mux16~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y13_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux16~3 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux16~3_combout  = ( \A_SPW_TOP|tx_data|mem[57][1]~q  & ( \A_SPW_TOP|tx_data|mem[56][1]~q  & ( ((!\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|mem[40][1]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [0] & ((\A_SPW_TOP|tx_data|mem[41][1]~q 
// )))) # (\A_SPW_TOP|tx_data|rd_ptr [4]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[57][1]~q  & ( \A_SPW_TOP|tx_data|mem[56][1]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & ((!\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|mem[40][1]~q )) # 
// (\A_SPW_TOP|tx_data|rd_ptr [0] & ((\A_SPW_TOP|tx_data|mem[41][1]~q ))))) # (\A_SPW_TOP|tx_data|rd_ptr [4] & (((!\A_SPW_TOP|tx_data|rd_ptr [0])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[57][1]~q  & ( !\A_SPW_TOP|tx_data|mem[56][1]~q  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [4] & ((!\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|mem[40][1]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [0] & ((\A_SPW_TOP|tx_data|mem[41][1]~q ))))) # (\A_SPW_TOP|tx_data|rd_ptr [4] & (((\A_SPW_TOP|tx_data|rd_ptr [0])))) ) ) 
// ) # ( !\A_SPW_TOP|tx_data|mem[57][1]~q  & ( !\A_SPW_TOP|tx_data|mem[56][1]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & ((!\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|mem[40][1]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [0] & ((\A_SPW_TOP|tx_data|mem[41][1]~q 
// ))))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[40][1]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[41][1]~q ),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .datae(!\A_SPW_TOP|tx_data|mem[57][1]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[56][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux16~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux16~3 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux16~3 .lut_mask = 64'h5030503F5F305F3F;
defparam \A_SPW_TOP|tx_data|Mux16~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y13_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux16~4 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux16~4_combout  = ( \A_SPW_TOP|tx_data|Mux16~2_combout  & ( \A_SPW_TOP|tx_data|Mux16~3_combout  & ( ((!\A_SPW_TOP|tx_data|rd_ptr [5] & ((\A_SPW_TOP|tx_data|Mux16~0_combout ))) # (\A_SPW_TOP|tx_data|rd_ptr [5] & 
// (\A_SPW_TOP|tx_data|Mux16~1_combout ))) # (\A_SPW_TOP|tx_data|rd_ptr [3]) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux16~2_combout  & ( \A_SPW_TOP|tx_data|Mux16~3_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & (!\A_SPW_TOP|tx_data|rd_ptr [3] & 
// ((\A_SPW_TOP|tx_data|Mux16~0_combout )))) # (\A_SPW_TOP|tx_data|rd_ptr [5] & (((\A_SPW_TOP|tx_data|Mux16~1_combout )) # (\A_SPW_TOP|tx_data|rd_ptr [3]))) ) ) ) # ( \A_SPW_TOP|tx_data|Mux16~2_combout  & ( !\A_SPW_TOP|tx_data|Mux16~3_combout  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [5] & (((\A_SPW_TOP|tx_data|Mux16~0_combout )) # (\A_SPW_TOP|tx_data|rd_ptr [3]))) # (\A_SPW_TOP|tx_data|rd_ptr [5] & (!\A_SPW_TOP|tx_data|rd_ptr [3] & (\A_SPW_TOP|tx_data|Mux16~1_combout ))) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|Mux16~2_combout  & ( !\A_SPW_TOP|tx_data|Mux16~3_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [3] & ((!\A_SPW_TOP|tx_data|rd_ptr [5] & ((\A_SPW_TOP|tx_data|Mux16~0_combout ))) # (\A_SPW_TOP|tx_data|rd_ptr [5] & 
// (\A_SPW_TOP|tx_data|Mux16~1_combout )))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [5]),
        .datab(!\A_SPW_TOP|tx_data|rd_ptr [3]),
        .datac(!\A_SPW_TOP|tx_data|Mux16~1_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux16~0_combout ),
        .datae(!\A_SPW_TOP|tx_data|Mux16~2_combout ),
        .dataf(!\A_SPW_TOP|tx_data|Mux16~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux16~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux16~4 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux16~4 .lut_mask = 64'h048C26AE159D37BF;
defparam \A_SPW_TOP|tx_data|Mux16~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y9_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux16~18 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux16~18_combout  = ( \A_SPW_TOP|tx_data|mem[62][1]~q  & ( \A_SPW_TOP|tx_data|mem[63][1]~q  & ( ((!\A_SPW_TOP|tx_data|rd_ptr [0] & ((\A_SPW_TOP|tx_data|mem[46][1]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|mem[47][1]~q 
// ))) # (\A_SPW_TOP|tx_data|rd_ptr [4]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[62][1]~q  & ( \A_SPW_TOP|tx_data|mem[63][1]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & ((!\A_SPW_TOP|tx_data|rd_ptr [0] & ((\A_SPW_TOP|tx_data|mem[46][1]~q ))) # 
// (\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|mem[47][1]~q )))) # (\A_SPW_TOP|tx_data|rd_ptr [4] & (((\A_SPW_TOP|tx_data|rd_ptr [0])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[62][1]~q  & ( !\A_SPW_TOP|tx_data|mem[63][1]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr 
// [4] & ((!\A_SPW_TOP|tx_data|rd_ptr [0] & ((\A_SPW_TOP|tx_data|mem[46][1]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|mem[47][1]~q )))) # (\A_SPW_TOP|tx_data|rd_ptr [4] & (((!\A_SPW_TOP|tx_data|rd_ptr [0])))) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|mem[62][1]~q  & ( !\A_SPW_TOP|tx_data|mem[63][1]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & ((!\A_SPW_TOP|tx_data|rd_ptr [0] & ((\A_SPW_TOP|tx_data|mem[46][1]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|mem[47][1]~q )))) 
// ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[47][1]~q ),
        .datab(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .datac(!\A_SPW_TOP|tx_data|mem[46][1]~q ),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .datae(!\A_SPW_TOP|tx_data|mem[62][1]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[63][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux16~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux16~18 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux16~18 .lut_mask = 64'h0C443F440C773F77;
defparam \A_SPW_TOP|tx_data|Mux16~18 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y9_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux16~17 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux16~17_combout  = ( \A_SPW_TOP|tx_data|rd_ptr [0] & ( \A_SPW_TOP|tx_data|mem[15][1]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4]) # (\A_SPW_TOP|tx_data|mem[31][1]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [0] & ( 
// \A_SPW_TOP|tx_data|mem[15][1]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & ((\A_SPW_TOP|tx_data|mem[14][1]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [4] & (\A_SPW_TOP|tx_data|mem[30][1]~q )) ) ) ) # ( \A_SPW_TOP|tx_data|rd_ptr [0] & ( 
// !\A_SPW_TOP|tx_data|mem[15][1]~q  & ( (\A_SPW_TOP|tx_data|mem[31][1]~q  & \A_SPW_TOP|tx_data|rd_ptr [4]) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [0] & ( !\A_SPW_TOP|tx_data|mem[15][1]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & ((\A_SPW_TOP|tx_data|mem[14][1]~q 
// ))) # (\A_SPW_TOP|tx_data|rd_ptr [4] & (\A_SPW_TOP|tx_data|mem[30][1]~q )) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[31][1]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[30][1]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[14][1]~q ),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .datae(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .dataf(!\A_SPW_TOP|tx_data|mem[15][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux16~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux16~17 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux16~17 .lut_mask = 64'h0F3300550F33FF55;
defparam \A_SPW_TOP|tx_data|Mux16~17 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y9_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux16~16 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux16~16_combout  = ( \A_SPW_TOP|tx_data|mem[54][1]~q  & ( \A_SPW_TOP|tx_data|rd_ptr [4] & ( (!\A_SPW_TOP|tx_data|rd_ptr [0]) # (\A_SPW_TOP|tx_data|mem[55][1]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[54][1]~q  & ( \A_SPW_TOP|tx_data|rd_ptr 
// [4] & ( (\A_SPW_TOP|tx_data|mem[55][1]~q  & \A_SPW_TOP|tx_data|rd_ptr [0]) ) ) ) # ( \A_SPW_TOP|tx_data|mem[54][1]~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [4] & ( (!\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|mem[38][1]~q )) # (\A_SPW_TOP|tx_data|rd_ptr 
// [0] & ((\A_SPW_TOP|tx_data|mem[39][1]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[54][1]~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [4] & ( (!\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|mem[38][1]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [0] & 
// ((\A_SPW_TOP|tx_data|mem[39][1]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[55][1]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[38][1]~q ),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .datad(!\A_SPW_TOP|tx_data|mem[39][1]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[54][1]~q ),
        .dataf(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux16~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux16~16 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux16~16 .lut_mask = 64'h303F303F0505F5F5;
defparam \A_SPW_TOP|tx_data|Mux16~16 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y9_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux16~15 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux16~15_combout  = ( \A_SPW_TOP|tx_data|mem[22][1]~q  & ( \A_SPW_TOP|tx_data|mem[7][1]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [0] & (((\A_SPW_TOP|tx_data|rd_ptr [4])) # (\A_SPW_TOP|tx_data|mem[6][1]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [0] & 
// (((!\A_SPW_TOP|tx_data|rd_ptr [4]) # (\A_SPW_TOP|tx_data|mem[23][1]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[22][1]~q  & ( \A_SPW_TOP|tx_data|mem[7][1]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|mem[6][1]~q  & (!\A_SPW_TOP|tx_data|rd_ptr 
// [4]))) # (\A_SPW_TOP|tx_data|rd_ptr [0] & (((!\A_SPW_TOP|tx_data|rd_ptr [4]) # (\A_SPW_TOP|tx_data|mem[23][1]~q )))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[22][1]~q  & ( !\A_SPW_TOP|tx_data|mem[7][1]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [0] & 
// (((\A_SPW_TOP|tx_data|rd_ptr [4])) # (\A_SPW_TOP|tx_data|mem[6][1]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [0] & (((\A_SPW_TOP|tx_data|rd_ptr [4] & \A_SPW_TOP|tx_data|mem[23][1]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[22][1]~q  & ( 
// !\A_SPW_TOP|tx_data|mem[7][1]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|mem[6][1]~q  & (!\A_SPW_TOP|tx_data|rd_ptr [4]))) # (\A_SPW_TOP|tx_data|rd_ptr [0] & (((\A_SPW_TOP|tx_data|rd_ptr [4] & \A_SPW_TOP|tx_data|mem[23][1]~q )))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .datab(!\A_SPW_TOP|tx_data|mem[6][1]~q ),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .datad(!\A_SPW_TOP|tx_data|mem[23][1]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[22][1]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[7][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux16~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux16~15 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux16~15 .lut_mask = 64'h20252A2F70757A7F;
defparam \A_SPW_TOP|tx_data|Mux16~15 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y9_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux16~19 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux16~19_combout  = ( \A_SPW_TOP|tx_data|Mux16~15_combout  & ( \A_SPW_TOP|tx_data|rd_ptr [3] & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & ((\A_SPW_TOP|tx_data|Mux16~17_combout ))) # (\A_SPW_TOP|tx_data|rd_ptr [5] & 
// (\A_SPW_TOP|tx_data|Mux16~18_combout )) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux16~15_combout  & ( \A_SPW_TOP|tx_data|rd_ptr [3] & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & ((\A_SPW_TOP|tx_data|Mux16~17_combout ))) # (\A_SPW_TOP|tx_data|rd_ptr [5] & 
// (\A_SPW_TOP|tx_data|Mux16~18_combout )) ) ) ) # ( \A_SPW_TOP|tx_data|Mux16~15_combout  & ( !\A_SPW_TOP|tx_data|rd_ptr [3] & ( (!\A_SPW_TOP|tx_data|rd_ptr [5]) # (\A_SPW_TOP|tx_data|Mux16~16_combout ) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux16~15_combout  & ( 
// !\A_SPW_TOP|tx_data|rd_ptr [3] & ( (\A_SPW_TOP|tx_data|rd_ptr [5] & \A_SPW_TOP|tx_data|Mux16~16_combout ) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux16~18_combout ),
        .datab(!\A_SPW_TOP|tx_data|Mux16~17_combout ),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [5]),
        .datad(!\A_SPW_TOP|tx_data|Mux16~16_combout ),
        .datae(!\A_SPW_TOP|tx_data|Mux16~15_combout ),
        .dataf(!\A_SPW_TOP|tx_data|rd_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux16~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux16~19 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux16~19 .lut_mask = 64'h000FF0FF35353535;
defparam \A_SPW_TOP|tx_data|Mux16~19 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y11_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux16~20 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux16~20_combout  = ( \A_SPW_TOP|tx_data|Mux16~4_combout  & ( \A_SPW_TOP|tx_data|Mux16~19_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [1] & (((!\A_SPW_TOP|tx_data|rd_ptr [2])) # (\A_SPW_TOP|tx_data|Mux16~14_combout ))) # 
// (\A_SPW_TOP|tx_data|rd_ptr [1] & (((\A_SPW_TOP|tx_data|rd_ptr [2]) # (\A_SPW_TOP|tx_data|Mux16~9_combout )))) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux16~4_combout  & ( \A_SPW_TOP|tx_data|Mux16~19_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [1] & 
// (\A_SPW_TOP|tx_data|Mux16~14_combout  & ((\A_SPW_TOP|tx_data|rd_ptr [2])))) # (\A_SPW_TOP|tx_data|rd_ptr [1] & (((\A_SPW_TOP|tx_data|rd_ptr [2]) # (\A_SPW_TOP|tx_data|Mux16~9_combout )))) ) ) ) # ( \A_SPW_TOP|tx_data|Mux16~4_combout  & ( 
// !\A_SPW_TOP|tx_data|Mux16~19_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [1] & (((!\A_SPW_TOP|tx_data|rd_ptr [2])) # (\A_SPW_TOP|tx_data|Mux16~14_combout ))) # (\A_SPW_TOP|tx_data|rd_ptr [1] & (((\A_SPW_TOP|tx_data|Mux16~9_combout  & 
// !\A_SPW_TOP|tx_data|rd_ptr [2])))) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux16~4_combout  & ( !\A_SPW_TOP|tx_data|Mux16~19_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|Mux16~14_combout  & ((\A_SPW_TOP|tx_data|rd_ptr [2])))) # 
// (\A_SPW_TOP|tx_data|rd_ptr [1] & (((\A_SPW_TOP|tx_data|Mux16~9_combout  & !\A_SPW_TOP|tx_data|rd_ptr [2])))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .datab(!\A_SPW_TOP|tx_data|Mux16~14_combout ),
        .datac(!\A_SPW_TOP|tx_data|Mux16~9_combout ),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .datae(!\A_SPW_TOP|tx_data|Mux16~4_combout ),
        .dataf(!\A_SPW_TOP|tx_data|Mux16~19_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux16~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux16~20 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux16~20 .lut_mask = 64'h0522AF220577AF77;
defparam \A_SPW_TOP|tx_data|Mux16~20 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y11_N26
dffeas \A_SPW_TOP|tx_data|data_out[1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|tx_data|Mux16~20_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|data_out [1]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|data_out[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|data_out[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X54_Y7_N27
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector30~3 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector30~3_combout  = ( \A_SPW_TOP|SPW|TX|Selector30~2_combout  & ( (\A_SPW_TOP|SPW|TX|tx_data_in [1] & !\A_SPW_TOP|SPW|TX|Selector30~0_combout ) ) ) # ( !\A_SPW_TOP|SPW|TX|Selector30~2_combout  & ( (!\A_SPW_TOP|SPW|TX|Equal0~6_combout 
//  & (((\A_SPW_TOP|SPW|TX|tx_data_in [1] & !\A_SPW_TOP|SPW|TX|Selector30~0_combout )) # (\A_SPW_TOP|tx_data|data_out [1]))) # (\A_SPW_TOP|SPW|TX|Equal0~6_combout  & (\A_SPW_TOP|SPW|TX|tx_data_in [1])) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|tx_data_in [1]),
        .datab(!\A_SPW_TOP|tx_data|data_out [1]),
        .datac(!\A_SPW_TOP|SPW|TX|Selector30~0_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|Equal0~6_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|Selector30~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector30~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector30~3 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector30~3 .lut_mask = 64'h7355735550505050;
defparam \A_SPW_TOP|SPW|TX|Selector30~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X54_Y7_N29
dffeas \A_SPW_TOP|SPW|TX|tx_data_in[1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(\A_SPW_TOP|SPW|TX|Selector30~3_combout ),
        .asdata(vcc),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|tx_data_in [1]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_data_in[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|tx_data_in[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X59_Y7_N36
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|last_type~11 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|last_type~11_combout  = ( \A_SPW_TOP|SPW|TX|tx_data_in [8] & ( \A_SPW_TOP|SPW|TX|tx_data_in [1] ) ) # ( !\A_SPW_TOP|SPW|TX|tx_data_in [8] & ( \A_SPW_TOP|SPW|TX|tx_data_in [1] & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & 
// ((!\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & ((!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]))) # (\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & (!\A_SPW_TOP|SPW|TX|global_counter_transfer [1])))) ) ) ) # ( \A_SPW_TOP|SPW|TX|tx_data_in [8] & ( 
// !\A_SPW_TOP|SPW|TX|tx_data_in [1] & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & (!\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & ((!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]) # (\A_SPW_TOP|SPW|TX|global_counter_transfer [0])))) ) ) ) # ( 
// !\A_SPW_TOP|SPW|TX|tx_data_in [8] & ( !\A_SPW_TOP|SPW|TX|tx_data_in [1] & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & ((!\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & ((!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]))) # 
// (\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & (!\A_SPW_TOP|SPW|TX|global_counter_transfer [1])))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
        .datab(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
        .datac(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
        .datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
        .datae(!\A_SPW_TOP|SPW|TX|tx_data_in [8]),
        .dataf(!\A_SPW_TOP|SPW|TX|tx_data_in [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|last_type~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_type~11 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|last_type~11 .lut_mask = 64'hA08880A0A088FFFF;
defparam \A_SPW_TOP|SPW|TX|last_type~11 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y6_N15
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector67~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector67~0_combout  = ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & ( \A_SPW_TOP|SPW|TX|global_counter_transfer [2] & ( (\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & (\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & 
// ((\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_c~q ) # (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null~q )))) ) ) ) # ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [1] 
// & ((\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_c~q ) # (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null~q ))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
        .datab(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null~q ),
        .datac(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
        .datad(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_c~q ),
        .datae(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
        .dataf(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector67~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector67~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector67~0 .lut_mask = 64'h30F0000001050000;
defparam \A_SPW_TOP|SPW|TX|Selector67~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X51_Y7_N48
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector39~1 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector39~1_combout  = ( \A_SPW_TOP|tx_data|data_out [1] & ( ((\A_SPW_TOP|SPW|TX|tx_data_in_0 [1] & !\A_SPW_TOP|SPW|TX|Selector40~0_combout )) # (\A_SPW_TOP|SPW|TX|Selector32~0_combout ) ) ) # ( !\A_SPW_TOP|tx_data|data_out [1] & ( 
// (\A_SPW_TOP|SPW|TX|tx_data_in_0 [1] & !\A_SPW_TOP|SPW|TX|Selector40~0_combout ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|SPW|TX|tx_data_in_0 [1]),
        .datac(!\A_SPW_TOP|SPW|TX|Selector40~0_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|Selector32~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|data_out [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector39~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector39~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector39~1 .lut_mask = 64'h3030303030FF30FF;
defparam \A_SPW_TOP|SPW|TX|Selector39~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X56_Y7_N44
dffeas \A_SPW_TOP|SPW|TX|tx_data_in_0[1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|Selector39~1_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|tx_data_in_0 [1]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_data_in_0[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|tx_data_in_0[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X59_Y7_N39
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|last_type~10 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|last_type~10_combout  = ( \A_SPW_TOP|SPW|TX|tx_data_in_0 [8] & ( \A_SPW_TOP|SPW|TX|tx_data_in_0 [1] ) ) # ( !\A_SPW_TOP|SPW|TX|tx_data_in_0 [8] & ( \A_SPW_TOP|SPW|TX|tx_data_in_0 [1] & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & 
// ((!\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & ((!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]))) # (\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & (!\A_SPW_TOP|SPW|TX|global_counter_transfer [1])))) ) ) ) # ( \A_SPW_TOP|SPW|TX|tx_data_in_0 [8] & ( 
// !\A_SPW_TOP|SPW|TX|tx_data_in_0 [1] & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & (!\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & ((!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]) # (\A_SPW_TOP|SPW|TX|global_counter_transfer [0])))) ) ) ) # ( 
// !\A_SPW_TOP|SPW|TX|tx_data_in_0 [8] & ( !\A_SPW_TOP|SPW|TX|tx_data_in_0 [1] & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & ((!\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & ((!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]))) # 
// (\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & (!\A_SPW_TOP|SPW|TX|global_counter_transfer [1])))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
        .datab(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
        .datac(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
        .datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
        .datae(!\A_SPW_TOP|SPW|TX|tx_data_in_0 [8]),
        .dataf(!\A_SPW_TOP|SPW|TX|tx_data_in_0 [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|last_type~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_type~10 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|last_type~10 .lut_mask = 64'hA8088A00A808FFFF;
defparam \A_SPW_TOP|SPW|TX|last_type~10 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X59_Y7_N30
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector67~1 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector67~1_combout  = ( !\A_SPW_TOP|SPW|TX|Selector67~0_combout  & ( \A_SPW_TOP|SPW|TX|last_type~10_combout  & ( (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~q  & (!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q  & 
// ((!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q ) # (!\A_SPW_TOP|SPW|TX|last_type~11_combout )))) ) ) ) # ( !\A_SPW_TOP|SPW|TX|Selector67~0_combout  & ( !\A_SPW_TOP|SPW|TX|last_type~10_combout  & ( (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~q  & 
// ((!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q ) # (!\A_SPW_TOP|SPW|TX|last_type~11_combout ))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q ),
        .datab(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~q ),
        .datac(!\A_SPW_TOP|SPW|TX|last_type~11_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q ),
        .datae(!\A_SPW_TOP|SPW|TX|Selector67~0_combout ),
        .dataf(!\A_SPW_TOP|SPW|TX|last_type~10_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector67~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector67~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector67~1 .lut_mask = 64'h3232000032000000;
defparam \A_SPW_TOP|SPW|TX|Selector67~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X59_Y7_N57
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|LessThan5~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|LessThan5~0_combout  = ( \A_SPW_TOP|SPW|TX|global_counter_transfer [3] ) # ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & ( (\A_SPW_TOP|SPW|TX|global_counter_transfer [2]) # (\A_SPW_TOP|SPW|TX|global_counter_transfer [1]) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
        .datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|LessThan5~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|LessThan5~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|LessThan5~0 .lut_mask = 64'h0FFF0FFFFFFFFFFF;
defparam \A_SPW_TOP|SPW|TX|LessThan5~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X58_Y6_N21
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector67~3 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector67~3_combout  = ( !\A_SPW_TOP|SPW|TX|Equal0~4_combout  & ( ((\A_SPW_TOP|SPW|TX|LessThan5~0_combout  & \A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct_c~q )) # (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct~q ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|LessThan5~0_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct~q ),
        .datac(gnd),
        .datad(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct_c~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|Equal0~4_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector67~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector67~3 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector67~3 .lut_mask = 64'h3377337700000000;
defparam \A_SPW_TOP|SPW|TX|Selector67~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X58_Y7_N27
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector67~2 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector67~2_combout  = ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c~q  & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & ((!\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & ((!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]))) # 
// (\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & (\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & \A_SPW_TOP|SPW|TX|global_counter_transfer [2])))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
        .datab(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
        .datac(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
        .datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector67~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector67~2 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector67~2 .lut_mask = 64'h0000000088048804;
defparam \A_SPW_TOP|SPW|TX|Selector67~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X58_Y6_N18
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector71~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector71~0_combout  = ( \A_SPW_TOP|SPW|TX|Equal0~4_combout  & ( (!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct~q  & !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct_c~q ) ) ) # ( !\A_SPW_TOP|SPW|TX|Equal0~4_combout  & ( 
// (!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct_c~q ) # (\A_SPW_TOP|SPW|TX|LessThan5~0_combout ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct~q ),
        .datac(!\A_SPW_TOP|SPW|TX|LessThan5~0_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct_c~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|Equal0~4_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector71~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector71~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector71~0 .lut_mask = 64'hFF0FFF0FCC00CC00;
defparam \A_SPW_TOP|SPW|TX|Selector71~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X59_Y7_N18
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|last_type~15 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|last_type~15_combout  = ( \A_SPW_TOP|SPW|TX|global_counter_transfer [0] & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & !\A_SPW_TOP|SPW|TX|global_counter_transfer [2]) ) ) # ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & ( 
// (!\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & !\A_SPW_TOP|SPW|TX|global_counter_transfer [2]) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
        .datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|last_type~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_type~15 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|last_type~15 .lut_mask = 64'hAA00AA00F000F000;
defparam \A_SPW_TOP|SPW|TX|last_type~15 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X59_Y7_N54
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector68~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector68~0_combout  = ( \A_SPW_TOP|SPW|TX|Selector63~0_combout  & ( (!\A_SPW_TOP|SPW|TX|Selector67~2_combout  & (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~q  & (!\A_SPW_TOP|SPW|TX|last_type~15_combout  & 
// !\A_SPW_TOP|SPW|TX|Selector67~0_combout ))) ) ) # ( !\A_SPW_TOP|SPW|TX|Selector63~0_combout  & ( (!\A_SPW_TOP|SPW|TX|Selector67~2_combout  & (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~q  & !\A_SPW_TOP|SPW|TX|Selector67~0_combout )) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|Selector67~2_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~q ),
        .datac(!\A_SPW_TOP|SPW|TX|last_type~15_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|Selector67~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|Selector63~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector68~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector68~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector68~0 .lut_mask = 64'h2200220020002000;
defparam \A_SPW_TOP|SPW|TX|Selector68~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y17_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_payload~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_payload~0_combout  = ( \u0|hps_0|fpga_interfaces|h2f_WDATA [0] & ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_WDATA [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_010|src_payload~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_payload~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_payload~0 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_payload~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y17_N37
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_010|src_payload~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y15_N54
cyclonev_lcell_comb \u0|write_data_fifo_tx|data_out[0]~feeder (
// Equation(s):
// \u0|write_data_fifo_tx|data_out[0]~feeder_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [0] )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|write_data_fifo_tx|data_out[0]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|write_data_fifo_tx|data_out[0]~feeder .extended_lut = "off";
defparam \u0|write_data_fifo_tx|data_out[0]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|write_data_fifo_tx|data_out[0]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y15_N56
dffeas \u0|write_data_fifo_tx|data_out[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|write_data_fifo_tx|data_out[0]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|write_data_fifo_tx|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|write_data_fifo_tx|data_out [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|write_data_fifo_tx|data_out[0] .is_wysiwyg = "true";
defparam \u0|write_data_fifo_tx|data_out[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y13_N57
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector481~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector481~0_combout  = ( \A_SPW_TOP|tx_data|mem[52][0]~q  & ( (!\A_SPW_TOP|tx_data|Selector473~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux8~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [0]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[52][0]~q  & ( (\A_SPW_TOP|tx_data|Selector473~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux8~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [0])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [0]),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector473~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[52][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector481~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector481~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector481~0 .lut_mask = 64'h010D010DF1FDF1FD;
defparam \A_SPW_TOP|tx_data|Selector481~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y13_N35
dffeas \A_SPW_TOP|tx_data|mem[52][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector481~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[52][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[52][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[52][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y13_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector301~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector301~0_combout  = ( \A_SPW_TOP|tx_data|mem[32][0]~q  & ( (!\A_SPW_TOP|tx_data|Selector293~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux8~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [0]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[32][0]~q  & ( (\A_SPW_TOP|tx_data|Selector293~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux8~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [0])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [0]),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector293~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[32][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector301~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector301~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector301~0 .lut_mask = 64'h010D010DF1FDF1FD;
defparam \A_SPW_TOP|tx_data|Selector301~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y13_N41
dffeas \A_SPW_TOP|tx_data|mem[32][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector301~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[32][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[32][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[32][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y13_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector445~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector445~0_combout  = ( \A_SPW_TOP|tx_data|mem[48][0]~q  & ( (!\A_SPW_TOP|tx_data|Selector437~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux8~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [0]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[48][0]~q  & ( (\A_SPW_TOP|tx_data|Selector437~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux8~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [0])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [0]),
        .datab(!\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector437~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[48][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector445~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector445~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector445~0 .lut_mask = 64'h03050305F3F5F3F5;
defparam \A_SPW_TOP|tx_data|Selector445~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y13_N53
dffeas \A_SPW_TOP|tx_data|mem[48][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector445~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[48][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[48][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[48][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y13_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector337~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector337~0_combout  = ( \A_SPW_TOP|tx_data|mem[36][0]~q  & ( (!\A_SPW_TOP|tx_data|Selector329~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux8~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [0]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[36][0]~q  & ( (\A_SPW_TOP|tx_data|Selector329~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux8~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [0])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [0]),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector329~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[36][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector337~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector337~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector337~0 .lut_mask = 64'h010D010DF1FDF1FD;
defparam \A_SPW_TOP|tx_data|Selector337~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y13_N53
dffeas \A_SPW_TOP|tx_data|mem[36][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector337~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[36][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[36][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[36][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y13_N27
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux8~10 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux8~10_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [4] & ( \A_SPW_TOP|tx_data|mem[36][0]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & ((\A_SPW_TOP|tx_data|mem[48][0]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|mem[52][0]~q )) ) 
// ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [4] & ( \A_SPW_TOP|tx_data|mem[36][0]~q  & ( (\A_SPW_TOP|tx_data|wr_ptr [2]) # (\A_SPW_TOP|tx_data|mem[32][0]~q ) ) ) ) # ( \A_SPW_TOP|tx_data|wr_ptr [4] & ( !\A_SPW_TOP|tx_data|mem[36][0]~q  & ( 
// (!\A_SPW_TOP|tx_data|wr_ptr [2] & ((\A_SPW_TOP|tx_data|mem[48][0]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|mem[52][0]~q )) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [4] & ( !\A_SPW_TOP|tx_data|mem[36][0]~q  & ( 
// (\A_SPW_TOP|tx_data|mem[32][0]~q  & !\A_SPW_TOP|tx_data|wr_ptr [2]) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[52][0]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[32][0]~q ),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datad(!\A_SPW_TOP|tx_data|mem[48][0]~q ),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .dataf(!\A_SPW_TOP|tx_data|mem[36][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux8~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux8~10 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux8~10 .lut_mask = 64'h303005F53F3F05F5;
defparam \A_SPW_TOP|tx_data|Mux8~10 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y15_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector490~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector490~0_combout  = ( \A_SPW_TOP|tx_data|Selector482~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux8~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [0]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector482~0_combout  & ( \A_SPW_TOP|tx_data|mem[53][0]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[53][0]~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(!\u0|write_data_fifo_tx|data_out [0]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector482~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector490~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector490~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector490~0 .lut_mask = 64'h55555555303F303F;
defparam \A_SPW_TOP|tx_data|Selector490~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y15_N29
dffeas \A_SPW_TOP|tx_data|mem[53][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector490~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[53][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[53][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[53][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y15_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector346~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector346~0_combout  = ( \A_SPW_TOP|tx_data|Selector338~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux8~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [0]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector338~0_combout  & ( \A_SPW_TOP|tx_data|mem[37][0]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .datac(!\u0|write_data_fifo_tx|data_out [0]),
        .datad(!\A_SPW_TOP|tx_data|mem[37][0]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector338~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector346~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector346~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector346~0 .lut_mask = 64'h00FF00FF27272727;
defparam \A_SPW_TOP|tx_data|Selector346~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y15_N47
dffeas \A_SPW_TOP|tx_data|mem[37][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector346~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[37][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[37][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[37][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y15_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector454~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector454~0_combout  = ( \A_SPW_TOP|tx_data|Selector446~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux8~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\u0|write_data_fifo_tx|data_out [0])) ) ) # ( !\A_SPW_TOP|tx_data|Selector446~0_combout  & ( \A_SPW_TOP|tx_data|mem[49][0]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[49][0]~q ),
        .datab(!\u0|write_data_fifo_tx|data_out [0]),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .datae(!\A_SPW_TOP|tx_data|Selector446~0_combout ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector454~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector454~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector454~0 .lut_mask = 64'h555503F3555503F3;
defparam \A_SPW_TOP|tx_data|Selector454~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y15_N56
dffeas \A_SPW_TOP|tx_data|mem[49][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector454~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[49][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[49][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[49][0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y11_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector310~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector310~0_combout  = ( \A_SPW_TOP|tx_data|mem[33][0]~q  & ( (!\A_SPW_TOP|tx_data|Selector302~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux8~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [0]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[33][0]~q  & ( (\A_SPW_TOP|tx_data|Selector302~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux8~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [0])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [0]),
        .datab(!\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector302~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[33][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector310~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector310~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector310~0 .lut_mask = 64'h03050305F3F5F3F5;
defparam \A_SPW_TOP|tx_data|Selector310~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y11_N41
dffeas \A_SPW_TOP|tx_data|mem[33][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector310~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[33][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[33][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[33][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y15_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux8~11 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux8~11_combout  = ( \A_SPW_TOP|tx_data|mem[49][0]~q  & ( \A_SPW_TOP|tx_data|mem[33][0]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [2]) # ((!\A_SPW_TOP|tx_data|wr_ptr [4] & ((\A_SPW_TOP|tx_data|mem[37][0]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [4] 
// & (\A_SPW_TOP|tx_data|mem[53][0]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[49][0]~q  & ( \A_SPW_TOP|tx_data|mem[33][0]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & (((!\A_SPW_TOP|tx_data|wr_ptr [4])))) # (\A_SPW_TOP|tx_data|wr_ptr [2] & 
// ((!\A_SPW_TOP|tx_data|wr_ptr [4] & ((\A_SPW_TOP|tx_data|mem[37][0]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|mem[53][0]~q )))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[49][0]~q  & ( !\A_SPW_TOP|tx_data|mem[33][0]~q  & ( 
// (!\A_SPW_TOP|tx_data|wr_ptr [2] & (((\A_SPW_TOP|tx_data|wr_ptr [4])))) # (\A_SPW_TOP|tx_data|wr_ptr [2] & ((!\A_SPW_TOP|tx_data|wr_ptr [4] & ((\A_SPW_TOP|tx_data|mem[37][0]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|mem[53][0]~q )))) ) ) 
// ) # ( !\A_SPW_TOP|tx_data|mem[49][0]~q  & ( !\A_SPW_TOP|tx_data|mem[33][0]~q  & ( (\A_SPW_TOP|tx_data|wr_ptr [2] & ((!\A_SPW_TOP|tx_data|wr_ptr [4] & ((\A_SPW_TOP|tx_data|mem[37][0]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|mem[53][0]~q 
// )))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[53][0]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[37][0]~q ),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datae(!\A_SPW_TOP|tx_data|mem[49][0]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[33][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux8~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux8~11 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux8~11 .lut_mask = 64'h030503F5F305F3F5;
defparam \A_SPW_TOP|tx_data|Mux8~11 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y13_N21
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector499~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector499~0_combout  = ( \A_SPW_TOP|tx_data|Selector491~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux8~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\u0|write_data_fifo_tx|data_out [0])) ) ) # ( !\A_SPW_TOP|tx_data|Selector491~0_combout  & ( \A_SPW_TOP|tx_data|mem[54][0]~q  ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [0]),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[54][0]~q ),
        .datad(!\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector491~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector499~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector499~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector499~0 .lut_mask = 64'h0F0F0F0F11DD11DD;
defparam \A_SPW_TOP|tx_data|Selector499~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y13_N11
dffeas \A_SPW_TOP|tx_data|mem[54][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector499~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[54][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[54][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[54][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y13_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector319~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector319~0_combout  = ( \A_SPW_TOP|tx_data|mem[34][0]~q  & ( (!\A_SPW_TOP|tx_data|Selector311~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux8~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [0]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[34][0]~q  & ( (\A_SPW_TOP|tx_data|Selector311~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux8~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [0])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [0]),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector311~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[34][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector319~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector319~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector319~0 .lut_mask = 64'h010D010DF1FDF1FD;
defparam \A_SPW_TOP|tx_data|Selector319~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y13_N26
dffeas \A_SPW_TOP|tx_data|mem[34][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector319~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[34][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[34][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[34][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y13_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector355~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector355~0_combout  = ( \A_SPW_TOP|tx_data|mem[38][0]~q  & ( (!\A_SPW_TOP|tx_data|Selector347~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux8~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [0]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[38][0]~q  & ( (\A_SPW_TOP|tx_data|Selector347~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux8~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [0])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [0]),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .datad(!\A_SPW_TOP|tx_data|Selector347~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[38][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector355~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector355~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector355~0 .lut_mask = 64'h001D001DFF1DFF1D;
defparam \A_SPW_TOP|tx_data|Selector355~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y13_N50
dffeas \A_SPW_TOP|tx_data|mem[38][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector355~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[38][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[38][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[38][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y13_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector463~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector463~0_combout  = ( \A_SPW_TOP|tx_data|mem[50][0]~q  & ( \A_SPW_TOP|tx_data|Selector455~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux8~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [0])) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[50][0]~q  & ( \A_SPW_TOP|tx_data|Selector455~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux8~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [0])) ) ) ) # ( \A_SPW_TOP|tx_data|mem[50][0]~q  & ( !\A_SPW_TOP|tx_data|Selector455~0_combout  ) )

        .dataa(gnd),
        .datab(!\u0|write_data_fifo_tx|data_out [0]),
        .datac(!\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[50][0]~q ),
        .dataf(!\A_SPW_TOP|tx_data|Selector455~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector463~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector463~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector463~0 .lut_mask = 64'h0000FFFF0F330F33;
defparam \A_SPW_TOP|tx_data|Selector463~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y13_N47
dffeas \A_SPW_TOP|tx_data|mem[50][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector463~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[50][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[50][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[50][0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y13_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux8~12 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux8~12_combout  = ( \A_SPW_TOP|tx_data|mem[38][0]~q  & ( \A_SPW_TOP|tx_data|mem[50][0]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & (((\A_SPW_TOP|tx_data|mem[34][0]~q ) # (\A_SPW_TOP|tx_data|wr_ptr [2])))) # (\A_SPW_TOP|tx_data|wr_ptr [4] 
// & (((!\A_SPW_TOP|tx_data|wr_ptr [2])) # (\A_SPW_TOP|tx_data|mem[54][0]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[38][0]~q  & ( \A_SPW_TOP|tx_data|mem[50][0]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & (((!\A_SPW_TOP|tx_data|wr_ptr [2] & 
// \A_SPW_TOP|tx_data|mem[34][0]~q )))) # (\A_SPW_TOP|tx_data|wr_ptr [4] & (((!\A_SPW_TOP|tx_data|wr_ptr [2])) # (\A_SPW_TOP|tx_data|mem[54][0]~q ))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[38][0]~q  & ( !\A_SPW_TOP|tx_data|mem[50][0]~q  & ( 
// (!\A_SPW_TOP|tx_data|wr_ptr [4] & (((\A_SPW_TOP|tx_data|mem[34][0]~q ) # (\A_SPW_TOP|tx_data|wr_ptr [2])))) # (\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|mem[54][0]~q  & (\A_SPW_TOP|tx_data|wr_ptr [2]))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[38][0]~q 
//  & ( !\A_SPW_TOP|tx_data|mem[50][0]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & (((!\A_SPW_TOP|tx_data|wr_ptr [2] & \A_SPW_TOP|tx_data|mem[34][0]~q )))) # (\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|mem[54][0]~q  & (\A_SPW_TOP|tx_data|wr_ptr [2]))) 
// ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[54][0]~q ),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datad(!\A_SPW_TOP|tx_data|mem[34][0]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[38][0]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[50][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux8~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux8~12 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux8~12 .lut_mask = 64'h01C10DCD31F13DFD;
defparam \A_SPW_TOP|tx_data|Mux8~12 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y15_N21
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector508~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector508~0_combout  = ( \A_SPW_TOP|tx_data|mem[55][0]~q  & ( (!\A_SPW_TOP|tx_data|Selector500~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux8~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [0])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[55][0]~q  & ( (\A_SPW_TOP|tx_data|Selector500~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux8~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [0]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .datac(!\u0|write_data_fifo_tx|data_out [0]),
        .datad(!\A_SPW_TOP|tx_data|Selector500~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[55][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector508~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector508~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector508~0 .lut_mask = 64'h00270027FF27FF27;
defparam \A_SPW_TOP|tx_data|Selector508~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y15_N50
dffeas \A_SPW_TOP|tx_data|mem[55][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector508~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[55][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[55][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[55][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y15_N33
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector328~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector328~0_combout  = ( \A_SPW_TOP|tx_data|mem[35][0]~q  & ( (!\A_SPW_TOP|tx_data|Selector320~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux8~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [0])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[35][0]~q  & ( (\A_SPW_TOP|tx_data|Selector320~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux8~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [0]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .datac(!\u0|write_data_fifo_tx|data_out [0]),
        .datad(!\A_SPW_TOP|tx_data|Selector320~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[35][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector328~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector328~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector328~0 .lut_mask = 64'h00270027FF27FF27;
defparam \A_SPW_TOP|tx_data|Selector328~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y15_N11
dffeas \A_SPW_TOP|tx_data|mem[35][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector328~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[35][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[35][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[35][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y15_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector472~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector472~0_combout  = ( \u0|write_data_fifo_tx|data_out [0] & ( (!\A_SPW_TOP|tx_data|Selector464~0_combout  & (((\A_SPW_TOP|tx_data|mem[51][0]~q )))) # (\A_SPW_TOP|tx_data|Selector464~0_combout  & 
// (((\A_SPW_TOP|tx_data|Mux8~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q ))) ) ) # ( !\u0|write_data_fifo_tx|data_out [0] & ( (!\A_SPW_TOP|tx_data|Selector464~0_combout  & (((\A_SPW_TOP|tx_data|mem[51][0]~q )))) # 
// (\A_SPW_TOP|tx_data|Selector464~0_combout  & (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux8~20_combout ))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector464~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|mem[51][0]~q ),
        .datae(gnd),
        .dataf(!\u0|write_data_fifo_tx|data_out [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector472~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector472~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector472~0 .lut_mask = 64'h02F202F207F707F7;
defparam \A_SPW_TOP|tx_data|Selector472~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y15_N38
dffeas \A_SPW_TOP|tx_data|mem[51][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector472~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[51][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[51][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[51][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y15_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector364~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector364~0_combout  = ( \A_SPW_TOP|tx_data|mem[39][0]~q  & ( (!\A_SPW_TOP|tx_data|Selector356~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux8~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [0])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[39][0]~q  & ( (\A_SPW_TOP|tx_data|Selector356~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux8~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [0]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .datac(!\u0|write_data_fifo_tx|data_out [0]),
        .datad(!\A_SPW_TOP|tx_data|Selector356~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[39][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector364~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector364~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector364~0 .lut_mask = 64'h00270027FF27FF27;
defparam \A_SPW_TOP|tx_data|Selector364~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y15_N14
dffeas \A_SPW_TOP|tx_data|mem[39][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector364~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[39][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[39][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[39][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y15_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux8~13 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux8~13_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [2] & ( \A_SPW_TOP|tx_data|mem[39][0]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [4]) # (\A_SPW_TOP|tx_data|mem[55][0]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [2] & ( 
// \A_SPW_TOP|tx_data|mem[39][0]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|mem[35][0]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [4] & ((\A_SPW_TOP|tx_data|mem[51][0]~q ))) ) ) ) # ( \A_SPW_TOP|tx_data|wr_ptr [2] & ( 
// !\A_SPW_TOP|tx_data|mem[39][0]~q  & ( (\A_SPW_TOP|tx_data|mem[55][0]~q  & \A_SPW_TOP|tx_data|wr_ptr [4]) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [2] & ( !\A_SPW_TOP|tx_data|mem[39][0]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|mem[35][0]~q 
// )) # (\A_SPW_TOP|tx_data|wr_ptr [4] & ((\A_SPW_TOP|tx_data|mem[51][0]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[55][0]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[35][0]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[51][0]~q ),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .dataf(!\A_SPW_TOP|tx_data|mem[39][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux8~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux8~13 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux8~13 .lut_mask = 64'h330F0055330FFF55;
defparam \A_SPW_TOP|tx_data|Mux8~13 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y13_N51
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux8~14 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux8~14_combout  = ( \A_SPW_TOP|tx_data|Mux8~13_combout  & ( \A_SPW_TOP|tx_data|wr_ptr [0] & ( (\A_SPW_TOP|tx_data|wr_ptr [1]) # (\A_SPW_TOP|tx_data|Mux8~11_combout ) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux8~13_combout  & ( 
// \A_SPW_TOP|tx_data|wr_ptr [0] & ( (\A_SPW_TOP|tx_data|Mux8~11_combout  & !\A_SPW_TOP|tx_data|wr_ptr [1]) ) ) ) # ( \A_SPW_TOP|tx_data|Mux8~13_combout  & ( !\A_SPW_TOP|tx_data|wr_ptr [0] & ( (!\A_SPW_TOP|tx_data|wr_ptr [1] & 
// (\A_SPW_TOP|tx_data|Mux8~10_combout )) # (\A_SPW_TOP|tx_data|wr_ptr [1] & ((\A_SPW_TOP|tx_data|Mux8~12_combout ))) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux8~13_combout  & ( !\A_SPW_TOP|tx_data|wr_ptr [0] & ( (!\A_SPW_TOP|tx_data|wr_ptr [1] & 
// (\A_SPW_TOP|tx_data|Mux8~10_combout )) # (\A_SPW_TOP|tx_data|wr_ptr [1] & ((\A_SPW_TOP|tx_data|Mux8~12_combout ))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux8~10_combout ),
        .datab(!\A_SPW_TOP|tx_data|Mux8~11_combout ),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datad(!\A_SPW_TOP|tx_data|Mux8~12_combout ),
        .datae(!\A_SPW_TOP|tx_data|Mux8~13_combout ),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux8~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux8~14 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux8~14 .lut_mask = 64'h505F505F30303F3F;
defparam \A_SPW_TOP|tx_data|Mux8~14 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y13_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector139~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector139~0_combout  = ( \A_SPW_TOP|tx_data|mem[14][0]~q  & ( \u0|write_data_fifo_tx|data_out [0] & ( (!\A_SPW_TOP|tx_data|Selector131~0_combout ) # ((\A_SPW_TOP|tx_data|state_data_write.00~q ) # (\A_SPW_TOP|tx_data|Mux8~20_combout )) 
// ) ) ) # ( !\A_SPW_TOP|tx_data|mem[14][0]~q  & ( \u0|write_data_fifo_tx|data_out [0] & ( (\A_SPW_TOP|tx_data|Selector131~0_combout  & ((\A_SPW_TOP|tx_data|state_data_write.00~q ) # (\A_SPW_TOP|tx_data|Mux8~20_combout ))) ) ) ) # ( 
// \A_SPW_TOP|tx_data|mem[14][0]~q  & ( !\u0|write_data_fifo_tx|data_out [0] & ( (!\A_SPW_TOP|tx_data|Selector131~0_combout ) # ((\A_SPW_TOP|tx_data|Mux8~20_combout  & !\A_SPW_TOP|tx_data|state_data_write.00~q )) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[14][0]~q  & 
// ( !\u0|write_data_fifo_tx|data_out [0] & ( (\A_SPW_TOP|tx_data|Selector131~0_combout  & (\A_SPW_TOP|tx_data|Mux8~20_combout  & !\A_SPW_TOP|tx_data|state_data_write.00~q )) ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|tx_data|Selector131~0_combout ),
        .datac(!\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[14][0]~q ),
        .dataf(!\u0|write_data_fifo_tx|data_out [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector139~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector139~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector139~0 .lut_mask = 64'h0300CFCC0333CFFF;
defparam \A_SPW_TOP|tx_data|Selector139~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y13_N29
dffeas \A_SPW_TOP|tx_data|mem[14][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector139~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[14][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[14][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[14][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y12_N21
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector283~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector283~0_combout  = ( \A_SPW_TOP|tx_data|Selector275~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux8~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [0]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector275~0_combout  & ( \A_SPW_TOP|tx_data|mem[30][0]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [0]),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[30][0]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector275~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector283~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector283~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector283~0 .lut_mask = 64'h00FF00FF53535353;
defparam \A_SPW_TOP|tx_data|Selector283~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y12_N5
dffeas \A_SPW_TOP|tx_data|mem[30][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector283~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[30][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[30][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[30][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y12_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector103~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector103~0_combout  = ( \A_SPW_TOP|tx_data|mem[10][0]~q  & ( (!\A_SPW_TOP|tx_data|Selector95~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux8~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [0])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[10][0]~q  & ( (\A_SPW_TOP|tx_data|Selector95~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux8~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [0]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [0]),
        .datac(!\A_SPW_TOP|tx_data|Selector95~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[10][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector103~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector103~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector103~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|tx_data|Selector103~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y12_N41
dffeas \A_SPW_TOP|tx_data|mem[10][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector103~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[10][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[10][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[10][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y12_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector247~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector247~0_combout  = ( \A_SPW_TOP|tx_data|mem[26][0]~q  & ( (!\A_SPW_TOP|tx_data|Selector239~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux8~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [0])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[26][0]~q  & ( (\A_SPW_TOP|tx_data|Selector239~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux8~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [0]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [0]),
        .datac(!\A_SPW_TOP|tx_data|Selector239~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[26][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector247~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector247~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector247~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|tx_data|Selector247~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y12_N17
dffeas \A_SPW_TOP|tx_data|mem[26][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector247~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[26][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[26][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[26][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y12_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux8~7 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux8~7_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [4] & ( \A_SPW_TOP|tx_data|mem[26][0]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [2]) # (\A_SPW_TOP|tx_data|mem[30][0]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [4] & ( 
// \A_SPW_TOP|tx_data|mem[26][0]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & ((\A_SPW_TOP|tx_data|mem[10][0]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|mem[14][0]~q )) ) ) ) # ( \A_SPW_TOP|tx_data|wr_ptr [4] & ( 
// !\A_SPW_TOP|tx_data|mem[26][0]~q  & ( (\A_SPW_TOP|tx_data|wr_ptr [2] & \A_SPW_TOP|tx_data|mem[30][0]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [4] & ( !\A_SPW_TOP|tx_data|mem[26][0]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & ((\A_SPW_TOP|tx_data|mem[10][0]~q 
// ))) # (\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|mem[14][0]~q )) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[14][0]~q ),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datac(!\A_SPW_TOP|tx_data|mem[30][0]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[10][0]~q ),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .dataf(!\A_SPW_TOP|tx_data|mem[26][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux8~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux8~7 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux8~7 .lut_mask = 64'h11DD030311DDCFCF;
defparam \A_SPW_TOP|tx_data|Mux8~7 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y12_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector256~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector256~0_combout  = ( \A_SPW_TOP|tx_data|mem[27][0]~q  & ( (!\A_SPW_TOP|tx_data|Selector248~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux8~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [0]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[27][0]~q  & ( (\A_SPW_TOP|tx_data|Selector248~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux8~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [0])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [0]),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector248~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[27][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector256~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector256~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector256~0 .lut_mask = 64'h010D010DF1FDF1FD;
defparam \A_SPW_TOP|tx_data|Selector256~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y12_N35
dffeas \A_SPW_TOP|tx_data|mem[27][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector256~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[27][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[27][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[27][0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y12_N15
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector292~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector292~0_combout  = ( \A_SPW_TOP|tx_data|mem[31][0]~q  & ( (!\A_SPW_TOP|tx_data|Selector284~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux8~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [0]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[31][0]~q  & ( (\A_SPW_TOP|tx_data|Selector284~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux8~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [0])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [0]),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector284~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[31][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector292~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector292~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector292~0 .lut_mask = 64'h010D010DF1FDF1FD;
defparam \A_SPW_TOP|tx_data|Selector292~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y12_N44
dffeas \A_SPW_TOP|tx_data|mem[31][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector292~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[31][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[31][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[31][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y12_N45
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector112~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector112~0_combout  = ( \A_SPW_TOP|tx_data|mem[11][0]~q  & ( (!\A_SPW_TOP|tx_data|Selector104~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux8~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [0])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[11][0]~q  & ( (\A_SPW_TOP|tx_data|Selector104~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux8~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [0]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [0]),
        .datac(!\A_SPW_TOP|tx_data|Selector104~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[11][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector112~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector112~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector112~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|tx_data|Selector112~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y12_N35
dffeas \A_SPW_TOP|tx_data|mem[11][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector112~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[11][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[11][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[11][0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y12_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector148~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector148~0_combout  = ( \A_SPW_TOP|tx_data|Selector140~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux8~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\u0|write_data_fifo_tx|data_out [0])) ) ) # ( !\A_SPW_TOP|tx_data|Selector140~0_combout  & ( \A_SPW_TOP|tx_data|mem[15][0]~q  ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [0]),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[15][0]~q ),
        .datad(!\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector140~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector148~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector148~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector148~0 .lut_mask = 64'h0F0F0F0F11DD11DD;
defparam \A_SPW_TOP|tx_data|Selector148~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y12_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|mem[15][0]~feeder (
// Equation(s):
// \A_SPW_TOP|tx_data|mem[15][0]~feeder_combout  = ( \A_SPW_TOP|tx_data|Selector148~0_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector148~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|mem[15][0]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[15][0]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|mem[15][0]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|tx_data|mem[15][0]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y12_N20
dffeas \A_SPW_TOP|tx_data|mem[15][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|tx_data|mem[15][0]~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[15][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[15][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[15][0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y12_N57
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux8~8 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux8~8_combout  = ( \A_SPW_TOP|tx_data|mem[11][0]~q  & ( \A_SPW_TOP|tx_data|mem[15][0]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [4]) # ((!\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|mem[27][0]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [2] & 
// ((\A_SPW_TOP|tx_data|mem[31][0]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[11][0]~q  & ( \A_SPW_TOP|tx_data|mem[15][0]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & (((\A_SPW_TOP|tx_data|wr_ptr [2])))) # (\A_SPW_TOP|tx_data|wr_ptr [4] & 
// ((!\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|mem[27][0]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [2] & ((\A_SPW_TOP|tx_data|mem[31][0]~q ))))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[11][0]~q  & ( !\A_SPW_TOP|tx_data|mem[15][0]~q  & ( 
// (!\A_SPW_TOP|tx_data|wr_ptr [4] & (((!\A_SPW_TOP|tx_data|wr_ptr [2])))) # (\A_SPW_TOP|tx_data|wr_ptr [4] & ((!\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|mem[27][0]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [2] & ((\A_SPW_TOP|tx_data|mem[31][0]~q ))))) ) 
// ) ) # ( !\A_SPW_TOP|tx_data|mem[11][0]~q  & ( !\A_SPW_TOP|tx_data|mem[15][0]~q  & ( (\A_SPW_TOP|tx_data|wr_ptr [4] & ((!\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|mem[27][0]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [2] & 
// ((\A_SPW_TOP|tx_data|mem[31][0]~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[27][0]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[31][0]~q ),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datae(!\A_SPW_TOP|tx_data|mem[11][0]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[15][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux8~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux8~8 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux8~8 .lut_mask = 64'h0503F50305F3F5F3;
defparam \A_SPW_TOP|tx_data|Mux8~8 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y12_N27
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector229~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector229~0_combout  = ( \A_SPW_TOP|tx_data|mem[24][0]~q  & ( (!\A_SPW_TOP|tx_data|Selector221~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux8~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [0])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[24][0]~q  & ( (\A_SPW_TOP|tx_data|Selector221~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux8~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [0]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [0]),
        .datac(!\A_SPW_TOP|tx_data|Selector221~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[24][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector229~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector229~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector229~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|tx_data|Selector229~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y12_N50
dffeas \A_SPW_TOP|tx_data|mem[24][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector229~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[24][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[24][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[24][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y12_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector265~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector265~0_combout  = ( \A_SPW_TOP|tx_data|mem[28][0]~q  & ( (!\A_SPW_TOP|tx_data|Selector257~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux8~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [0])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[28][0]~q  & ( (\A_SPW_TOP|tx_data|Selector257~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux8~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [0]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [0]),
        .datac(!\A_SPW_TOP|tx_data|Selector257~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[28][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector265~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector265~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector265~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|tx_data|Selector265~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y12_N11
dffeas \A_SPW_TOP|tx_data|mem[28][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector265~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[28][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[28][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[28][0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y12_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector85~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector85~0_combout  = ( \A_SPW_TOP|tx_data|Mux8~20_combout  & ( (!\A_SPW_TOP|tx_data|Selector77~0_combout  & (((\A_SPW_TOP|tx_data|mem[8][0]~q )))) # (\A_SPW_TOP|tx_data|Selector77~0_combout  & 
// (((!\A_SPW_TOP|tx_data|state_data_write.00~q )) # (\u0|write_data_fifo_tx|data_out [0]))) ) ) # ( !\A_SPW_TOP|tx_data|Mux8~20_combout  & ( (!\A_SPW_TOP|tx_data|Selector77~0_combout  & (((\A_SPW_TOP|tx_data|mem[8][0]~q )))) # 
// (\A_SPW_TOP|tx_data|Selector77~0_combout  & (\u0|write_data_fifo_tx|data_out [0] & ((\A_SPW_TOP|tx_data|state_data_write.00~q )))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [0]),
        .datab(!\A_SPW_TOP|tx_data|mem[8][0]~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector77~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(!\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector85~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector85~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector85~0 .lut_mask = 64'h30353F3530353F35;
defparam \A_SPW_TOP|tx_data|Selector85~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y12_N11
dffeas \A_SPW_TOP|tx_data|mem[8][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector85~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[8][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[8][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[8][0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y12_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector121~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector121~0_combout  = ( \A_SPW_TOP|tx_data|mem[12][0]~q  & ( \A_SPW_TOP|tx_data|Selector113~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux8~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [0])) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[12][0]~q  & ( \A_SPW_TOP|tx_data|Selector113~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux8~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [0])) ) ) ) # ( \A_SPW_TOP|tx_data|mem[12][0]~q  & ( !\A_SPW_TOP|tx_data|Selector113~0_combout  ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [0]),
        .datab(gnd),
        .datac(!\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[12][0]~q ),
        .dataf(!\A_SPW_TOP|tx_data|Selector113~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector121~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector121~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector121~0 .lut_mask = 64'h0000FFFF0F550F55;
defparam \A_SPW_TOP|tx_data|Selector121~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y12_N47
dffeas \A_SPW_TOP|tx_data|mem[12][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector121~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[12][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[12][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[12][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y12_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux8~5 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux8~5_combout  = ( \A_SPW_TOP|tx_data|mem[8][0]~q  & ( \A_SPW_TOP|tx_data|mem[12][0]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [4]) # ((!\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|mem[24][0]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [2] & 
// ((\A_SPW_TOP|tx_data|mem[28][0]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[8][0]~q  & ( \A_SPW_TOP|tx_data|mem[12][0]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|mem[24][0]~q  & (\A_SPW_TOP|tx_data|wr_ptr [4]))) # (\A_SPW_TOP|tx_data|wr_ptr 
// [2] & (((!\A_SPW_TOP|tx_data|wr_ptr [4]) # (\A_SPW_TOP|tx_data|mem[28][0]~q )))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[8][0]~q  & ( !\A_SPW_TOP|tx_data|mem[12][0]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & (((!\A_SPW_TOP|tx_data|wr_ptr [4])) # 
// (\A_SPW_TOP|tx_data|mem[24][0]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [2] & (((\A_SPW_TOP|tx_data|wr_ptr [4] & \A_SPW_TOP|tx_data|mem[28][0]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[8][0]~q  & ( !\A_SPW_TOP|tx_data|mem[12][0]~q  & ( (\A_SPW_TOP|tx_data|wr_ptr 
// [4] & ((!\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|mem[24][0]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [2] & ((\A_SPW_TOP|tx_data|mem[28][0]~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[24][0]~q ),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datad(!\A_SPW_TOP|tx_data|mem[28][0]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[8][0]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[12][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux8~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux8~5 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux8~5 .lut_mask = 64'h0407C4C73437F4F7;
defparam \A_SPW_TOP|tx_data|Mux8~5 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y12_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector94~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector94~0_combout  = ( \A_SPW_TOP|tx_data|mem[9][0]~q  & ( (!\A_SPW_TOP|tx_data|Selector86~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux8~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [0]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[9][0]~q  & ( (\A_SPW_TOP|tx_data|Selector86~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux8~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [0])))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Selector86~0_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [0]),
        .datac(!\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[9][0]~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector94~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector94~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector94~0 .lut_mask = 64'h0511AFBB0511AFBB;
defparam \A_SPW_TOP|tx_data|Selector94~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y12_N56
dffeas \A_SPW_TOP|tx_data|mem[9][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector94~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[9][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[9][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[9][0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y12_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector274~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector274~0_combout  = ( \A_SPW_TOP|tx_data|mem[29][0]~q  & ( (!\A_SPW_TOP|tx_data|Selector266~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux8~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [0])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[29][0]~q  & ( (\A_SPW_TOP|tx_data|Selector266~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux8~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [0]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [0]),
        .datac(!\A_SPW_TOP|tx_data|Selector266~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[29][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector274~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector274~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector274~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|tx_data|Selector274~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y12_N41
dffeas \A_SPW_TOP|tx_data|mem[29][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector274~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[29][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[29][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[29][0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y12_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector238~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector238~0_combout  = ( \A_SPW_TOP|tx_data|Selector230~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux8~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\u0|write_data_fifo_tx|data_out [0])) ) ) # ( !\A_SPW_TOP|tx_data|Selector230~0_combout  & ( \A_SPW_TOP|tx_data|mem[25][0]~q  ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [0]),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[25][0]~q ),
        .datad(!\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector230~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector238~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector238~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector238~0 .lut_mask = 64'h0F0F0F0F11DD11DD;
defparam \A_SPW_TOP|tx_data|Selector238~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y12_N53
dffeas \A_SPW_TOP|tx_data|mem[25][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector238~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[25][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[25][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[25][0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y12_N27
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector130~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector130~0_combout  = ( \A_SPW_TOP|tx_data|Selector122~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux8~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [0]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector122~0_combout  & ( \A_SPW_TOP|tx_data|mem[13][0]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [0]),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[13][0]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector122~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector130~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector130~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector130~0 .lut_mask = 64'h00FF00FF53535353;
defparam \A_SPW_TOP|tx_data|Selector130~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y12_N23
dffeas \A_SPW_TOP|tx_data|mem[13][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector130~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[13][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[13][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[13][0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y12_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux8~6 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux8~6_combout  = ( \A_SPW_TOP|tx_data|mem[13][0]~q  & ( \A_SPW_TOP|tx_data|wr_ptr [2] & ( (!\A_SPW_TOP|tx_data|wr_ptr [4]) # (\A_SPW_TOP|tx_data|mem[29][0]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[13][0]~q  & ( \A_SPW_TOP|tx_data|wr_ptr 
// [2] & ( (\A_SPW_TOP|tx_data|mem[29][0]~q  & \A_SPW_TOP|tx_data|wr_ptr [4]) ) ) ) # ( \A_SPW_TOP|tx_data|mem[13][0]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [2] & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|mem[9][0]~q )) # (\A_SPW_TOP|tx_data|wr_ptr 
// [4] & ((\A_SPW_TOP|tx_data|mem[25][0]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[13][0]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [2] & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|mem[9][0]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [4] & 
// ((\A_SPW_TOP|tx_data|mem[25][0]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[9][0]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[29][0]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[25][0]~q ),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datae(!\A_SPW_TOP|tx_data|mem[13][0]~q ),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux8~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux8~6 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux8~6 .lut_mask = 64'h550F550F0033FF33;
defparam \A_SPW_TOP|tx_data|Mux8~6 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y12_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux8~9 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux8~9_combout  = ( \A_SPW_TOP|tx_data|Mux8~5_combout  & ( \A_SPW_TOP|tx_data|Mux8~6_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [1]) # ((!\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|Mux8~7_combout )) # (\A_SPW_TOP|tx_data|wr_ptr 
// [0] & ((\A_SPW_TOP|tx_data|Mux8~8_combout )))) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux8~5_combout  & ( \A_SPW_TOP|tx_data|Mux8~6_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [1] & (((\A_SPW_TOP|tx_data|wr_ptr [0])))) # (\A_SPW_TOP|tx_data|wr_ptr [1] & 
// ((!\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|Mux8~7_combout )) # (\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|Mux8~8_combout ))))) ) ) ) # ( \A_SPW_TOP|tx_data|Mux8~5_combout  & ( !\A_SPW_TOP|tx_data|Mux8~6_combout  & ( 
// (!\A_SPW_TOP|tx_data|wr_ptr [1] & (((!\A_SPW_TOP|tx_data|wr_ptr [0])))) # (\A_SPW_TOP|tx_data|wr_ptr [1] & ((!\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|Mux8~7_combout )) # (\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|Mux8~8_combout 
// ))))) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux8~5_combout  & ( !\A_SPW_TOP|tx_data|Mux8~6_combout  & ( (\A_SPW_TOP|tx_data|wr_ptr [1] & ((!\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|Mux8~7_combout )) # (\A_SPW_TOP|tx_data|wr_ptr [0] & 
// ((\A_SPW_TOP|tx_data|Mux8~8_combout ))))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datab(!\A_SPW_TOP|tx_data|Mux8~7_combout ),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datad(!\A_SPW_TOP|tx_data|Mux8~8_combout ),
        .datae(!\A_SPW_TOP|tx_data|Mux8~5_combout ),
        .dataf(!\A_SPW_TOP|tx_data|Mux8~6_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux8~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux8~9 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux8~9 .lut_mask = 64'h1015B0B51A1FBABF;
defparam \A_SPW_TOP|tx_data|Mux8~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y13_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector418~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector418~0_combout  = ( \A_SPW_TOP|tx_data|mem[45][0]~q  & ( (!\A_SPW_TOP|tx_data|Selector410~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux8~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [0])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[45][0]~q  & ( (\A_SPW_TOP|tx_data|Selector410~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux8~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [0]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [0]),
        .datac(!\A_SPW_TOP|tx_data|Selector410~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[45][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector418~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector418~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector418~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|tx_data|Selector418~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y13_N35
dffeas \A_SPW_TOP|tx_data|mem[45][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector418~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[45][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[45][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[45][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y13_N27
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector436~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector436~0_combout  = ( \A_SPW_TOP|tx_data|Selector428~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux8~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\u0|write_data_fifo_tx|data_out [0])) ) ) # ( !\A_SPW_TOP|tx_data|Selector428~0_combout  & ( \A_SPW_TOP|tx_data|mem[47][0]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\u0|write_data_fifo_tx|data_out [0]),
        .datac(!\A_SPW_TOP|tx_data|mem[47][0]~q ),
        .datad(!\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector428~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector436~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector436~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector436~0 .lut_mask = 64'h0F0F0F0F11BB11BB;
defparam \A_SPW_TOP|tx_data|Selector436~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y13_N44
dffeas \A_SPW_TOP|tx_data|mem[47][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector436~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[47][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[47][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[47][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y13_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector562~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector562~0_combout  = ( \A_SPW_TOP|tx_data|Selector554~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux8~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\u0|write_data_fifo_tx|data_out [0])) ) ) # ( !\A_SPW_TOP|tx_data|Selector554~0_combout  & ( \A_SPW_TOP|tx_data|mem[61][0]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\u0|write_data_fifo_tx|data_out [0]),
        .datac(!\A_SPW_TOP|tx_data|mem[61][0]~q ),
        .datad(!\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector554~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector562~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector562~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector562~0 .lut_mask = 64'h0F0F0F0F11BB11BB;
defparam \A_SPW_TOP|tx_data|Selector562~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y13_N20
dffeas \A_SPW_TOP|tx_data|mem[61][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector562~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[61][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[61][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[61][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y13_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector580~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector580~0_combout  = ( \A_SPW_TOP|tx_data|Selector572~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux8~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\u0|write_data_fifo_tx|data_out [0])) ) ) # ( !\A_SPW_TOP|tx_data|Selector572~0_combout  & ( \A_SPW_TOP|tx_data|mem[63][0]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\u0|write_data_fifo_tx|data_out [0]),
        .datac(!\A_SPW_TOP|tx_data|mem[63][0]~q ),
        .datad(!\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector572~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector580~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector580~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector580~0 .lut_mask = 64'h0F0F0F0F11BB11BB;
defparam \A_SPW_TOP|tx_data|Selector580~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y13_N2
dffeas \A_SPW_TOP|tx_data|mem[63][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector580~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[63][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[63][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[63][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y13_N21
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux8~18 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux8~18_combout  = ( \A_SPW_TOP|tx_data|mem[63][0]~q  & ( \A_SPW_TOP|tx_data|wr_ptr [1] & ( (\A_SPW_TOP|tx_data|mem[47][0]~q ) # (\A_SPW_TOP|tx_data|wr_ptr [4]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[63][0]~q  & ( \A_SPW_TOP|tx_data|wr_ptr 
// [1] & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & \A_SPW_TOP|tx_data|mem[47][0]~q ) ) ) ) # ( \A_SPW_TOP|tx_data|mem[63][0]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|mem[45][0]~q )) # 
// (\A_SPW_TOP|tx_data|wr_ptr [4] & ((\A_SPW_TOP|tx_data|mem[61][0]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[63][0]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|mem[45][0]~q )) # (\A_SPW_TOP|tx_data|wr_ptr 
// [4] & ((\A_SPW_TOP|tx_data|mem[61][0]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[45][0]~q ),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datac(!\A_SPW_TOP|tx_data|mem[47][0]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[61][0]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[63][0]~q ),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux8~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux8~18 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux8~18 .lut_mask = 64'h447744770C0C3F3F;
defparam \A_SPW_TOP|tx_data|Mux8~18 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y13_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector373~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector373~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( \A_SPW_TOP|tx_data|mem[40][0]~q  & ( (!\A_SPW_TOP|tx_data|Selector365~0_combout ) # (\u0|write_data_fifo_tx|data_out [0]) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( \A_SPW_TOP|tx_data|mem[40][0]~q  & ( (!\A_SPW_TOP|tx_data|Selector365~0_combout ) # (\A_SPW_TOP|tx_data|Mux8~20_combout ) ) ) ) # ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( 
// !\A_SPW_TOP|tx_data|mem[40][0]~q  & ( (\u0|write_data_fifo_tx|data_out [0] & \A_SPW_TOP|tx_data|Selector365~0_combout ) ) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( !\A_SPW_TOP|tx_data|mem[40][0]~q  & ( 
// (\A_SPW_TOP|tx_data|Selector365~0_combout  & \A_SPW_TOP|tx_data|Mux8~20_combout ) ) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [0]),
        .datab(gnd),
        .datac(!\A_SPW_TOP|tx_data|Selector365~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .datae(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[40][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector373~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector373~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector373~0 .lut_mask = 64'h000F0505F0FFF5F5;
defparam \A_SPW_TOP|tx_data|Selector373~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y13_N11
dffeas \A_SPW_TOP|tx_data|mem[40][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector373~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[40][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[40][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[40][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y13_N57
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector391~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector391~0_combout  = ( \A_SPW_TOP|tx_data|Selector383~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux8~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\u0|write_data_fifo_tx|data_out [0])) ) ) # ( !\A_SPW_TOP|tx_data|Selector383~0_combout  & ( \A_SPW_TOP|tx_data|mem[42][0]~q  ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [0]),
        .datab(!\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|mem[42][0]~q ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector383~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector391~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector391~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector391~0 .lut_mask = 64'h0F0F0F0F33553355;
defparam \A_SPW_TOP|tx_data|Selector391~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y13_N47
dffeas \A_SPW_TOP|tx_data|mem[42][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector391~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[42][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[42][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[42][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y13_N15
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector535~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector535~0_combout  = ( \A_SPW_TOP|tx_data|Selector527~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux8~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [0]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector527~0_combout  & ( \A_SPW_TOP|tx_data|mem[58][0]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|mem[58][0]~q ),
        .datad(!\u0|write_data_fifo_tx|data_out [0]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector527~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector535~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector535~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector535~0 .lut_mask = 64'h0F0F0F0F22772277;
defparam \A_SPW_TOP|tx_data|Selector535~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y13_N8
dffeas \A_SPW_TOP|tx_data|mem[58][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector535~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[58][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[58][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[58][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y13_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector517~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector517~0_combout  = ( \A_SPW_TOP|tx_data|mem[56][0]~q  & ( (!\A_SPW_TOP|tx_data|Selector509~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux8~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [0]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[56][0]~q  & ( (\A_SPW_TOP|tx_data|Selector509~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux8~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [0])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [0]),
        .datab(!\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector509~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[56][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector517~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector517~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector517~0 .lut_mask = 64'h03050305F3F5F3F5;
defparam \A_SPW_TOP|tx_data|Selector517~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y13_N41
dffeas \A_SPW_TOP|tx_data|mem[56][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector517~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[56][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[56][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[56][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y13_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux8~15 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux8~15_combout  = ( \A_SPW_TOP|tx_data|mem[58][0]~q  & ( \A_SPW_TOP|tx_data|mem[56][0]~q  & ( ((!\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|mem[40][0]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [1] & ((\A_SPW_TOP|tx_data|mem[42][0]~q 
// )))) # (\A_SPW_TOP|tx_data|wr_ptr [4]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[58][0]~q  & ( \A_SPW_TOP|tx_data|mem[56][0]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & ((!\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|mem[40][0]~q )) # 
// (\A_SPW_TOP|tx_data|wr_ptr [1] & ((\A_SPW_TOP|tx_data|mem[42][0]~q ))))) # (\A_SPW_TOP|tx_data|wr_ptr [4] & (((!\A_SPW_TOP|tx_data|wr_ptr [1])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[58][0]~q  & ( !\A_SPW_TOP|tx_data|mem[56][0]~q  & ( 
// (!\A_SPW_TOP|tx_data|wr_ptr [4] & ((!\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|mem[40][0]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [1] & ((\A_SPW_TOP|tx_data|mem[42][0]~q ))))) # (\A_SPW_TOP|tx_data|wr_ptr [4] & (((\A_SPW_TOP|tx_data|wr_ptr [1])))) ) ) 
// ) # ( !\A_SPW_TOP|tx_data|mem[58][0]~q  & ( !\A_SPW_TOP|tx_data|mem[56][0]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & ((!\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|mem[40][0]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [1] & ((\A_SPW_TOP|tx_data|mem[42][0]~q 
// ))))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datab(!\A_SPW_TOP|tx_data|mem[40][0]~q ),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datad(!\A_SPW_TOP|tx_data|mem[42][0]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[58][0]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[56][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux8~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux8~15 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux8~15 .lut_mask = 64'h202A252F707A757F;
defparam \A_SPW_TOP|tx_data|Mux8~15 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y13_N57
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector526~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector526~0_combout  = ( \A_SPW_TOP|tx_data|mem[57][0]~q  & ( (!\A_SPW_TOP|tx_data|Selector518~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux8~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [0])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[57][0]~q  & ( (\A_SPW_TOP|tx_data|Selector518~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux8~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [0]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [0]),
        .datac(!\A_SPW_TOP|tx_data|Selector518~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[57][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector526~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector526~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector526~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|tx_data|Selector526~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y13_N53
dffeas \A_SPW_TOP|tx_data|mem[57][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector526~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[57][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[57][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[57][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y13_N39
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector544~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector544~0_combout  = ( \A_SPW_TOP|tx_data|mem[59][0]~q  & ( (!\A_SPW_TOP|tx_data|Selector536~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux8~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [0]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[59][0]~q  & ( (\A_SPW_TOP|tx_data|Selector536~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux8~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [0])))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\u0|write_data_fifo_tx|data_out [0]),
        .datac(!\A_SPW_TOP|tx_data|Selector536~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[59][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector544~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector544~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector544~0 .lut_mask = 64'h010B010BF1FBF1FB;
defparam \A_SPW_TOP|tx_data|Selector544~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y13_N17
dffeas \A_SPW_TOP|tx_data|mem[59][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector544~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[59][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[59][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[59][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y13_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector382~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector382~0_combout  = ( \A_SPW_TOP|tx_data|mem[41][0]~q  & ( (!\A_SPW_TOP|tx_data|Selector374~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux8~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [0]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[41][0]~q  & ( (\A_SPW_TOP|tx_data|Selector374~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux8~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [0])))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\u0|write_data_fifo_tx|data_out [0]),
        .datac(!\A_SPW_TOP|tx_data|Selector374~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .datae(!\A_SPW_TOP|tx_data|mem[41][0]~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector382~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector382~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector382~0 .lut_mask = 64'h010BF1FB010BF1FB;
defparam \A_SPW_TOP|tx_data|Selector382~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y13_N47
dffeas \A_SPW_TOP|tx_data|mem[41][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector382~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[41][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[41][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[41][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y13_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector400~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector400~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector392~0_combout  & (\A_SPW_TOP|tx_data|mem[43][0]~q )) # (\A_SPW_TOP|tx_data|Selector392~0_combout  & ((\u0|write_data_fifo_tx|data_out 
// [0]))) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector392~0_combout  & ((\A_SPW_TOP|tx_data|mem[43][0]~q ))) # (\A_SPW_TOP|tx_data|Selector392~0_combout  & (\A_SPW_TOP|tx_data|Mux8~20_combout )) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|mem[43][0]~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector392~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [0]),
        .datae(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector400~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector400~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector400~0 .lut_mask = 64'h3535303F3535303F;
defparam \A_SPW_TOP|tx_data|Selector400~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y13_N8
dffeas \A_SPW_TOP|tx_data|mem[43][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector400~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[43][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[43][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[43][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y13_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux8~16 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux8~16_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [4] & ( \A_SPW_TOP|tx_data|mem[43][0]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|mem[57][0]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [1] & ((\A_SPW_TOP|tx_data|mem[59][0]~q ))) ) 
// ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [4] & ( \A_SPW_TOP|tx_data|mem[43][0]~q  & ( (\A_SPW_TOP|tx_data|mem[41][0]~q ) # (\A_SPW_TOP|tx_data|wr_ptr [1]) ) ) ) # ( \A_SPW_TOP|tx_data|wr_ptr [4] & ( !\A_SPW_TOP|tx_data|mem[43][0]~q  & ( 
// (!\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|mem[57][0]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [1] & ((\A_SPW_TOP|tx_data|mem[59][0]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [4] & ( !\A_SPW_TOP|tx_data|mem[43][0]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr 
// [1] & \A_SPW_TOP|tx_data|mem[41][0]~q ) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[57][0]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[59][0]~q ),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datad(!\A_SPW_TOP|tx_data|mem[41][0]~q ),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .dataf(!\A_SPW_TOP|tx_data|mem[43][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux8~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux8~16 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux8~16 .lut_mask = 64'h00F053530FFF5353;
defparam \A_SPW_TOP|tx_data|Mux8~16 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y13_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector553~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector553~0_combout  = ( \A_SPW_TOP|tx_data|Selector545~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux8~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [0]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector545~0_combout  & ( \A_SPW_TOP|tx_data|mem[60][0]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|mem[60][0]~q ),
        .datad(!\u0|write_data_fifo_tx|data_out [0]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector545~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector553~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector553~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector553~0 .lut_mask = 64'h0F0F0F0F22772277;
defparam \A_SPW_TOP|tx_data|Selector553~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y13_N23
dffeas \A_SPW_TOP|tx_data|mem[60][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector553~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[60][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[60][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[60][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y13_N27
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector427~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector427~0_combout  = ( \A_SPW_TOP|tx_data|Selector419~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux8~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\u0|write_data_fifo_tx|data_out [0])) ) ) # ( !\A_SPW_TOP|tx_data|Selector419~0_combout  & ( \A_SPW_TOP|tx_data|mem[46][0]~q  ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [0]),
        .datab(!\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|mem[46][0]~q ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector419~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector427~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector427~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector427~0 .lut_mask = 64'h0F0F0F0F33553355;
defparam \A_SPW_TOP|tx_data|Selector427~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y13_N44
dffeas \A_SPW_TOP|tx_data|mem[46][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector427~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[46][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[46][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[46][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y13_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector409~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector409~0_combout  = ( \A_SPW_TOP|tx_data|mem[44][0]~q  & ( (!\A_SPW_TOP|tx_data|Selector401~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux8~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [0]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[44][0]~q  & ( (\A_SPW_TOP|tx_data|Selector401~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux8~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [0])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [0]),
        .datab(!\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|tx_data|Selector401~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[44][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector409~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector409~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector409~0 .lut_mask = 64'h00350035FF35FF35;
defparam \A_SPW_TOP|tx_data|Selector409~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y13_N35
dffeas \A_SPW_TOP|tx_data|mem[44][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector409~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[44][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[44][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[44][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y13_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector571~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector571~0_combout  = ( \A_SPW_TOP|tx_data|mem[62][0]~q  & ( (!\A_SPW_TOP|tx_data|Selector563~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux8~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [0]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[62][0]~q  & ( (\A_SPW_TOP|tx_data|Selector563~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux8~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [0])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [0]),
        .datab(!\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector563~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[62][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector571~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector571~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector571~0 .lut_mask = 64'h03050305F3F5F3F5;
defparam \A_SPW_TOP|tx_data|Selector571~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y13_N20
dffeas \A_SPW_TOP|tx_data|mem[62][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector571~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[62][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[62][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[62][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y13_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux8~17 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux8~17_combout  = ( \A_SPW_TOP|tx_data|mem[62][0]~q  & ( \A_SPW_TOP|tx_data|wr_ptr [1] & ( (\A_SPW_TOP|tx_data|wr_ptr [4]) # (\A_SPW_TOP|tx_data|mem[46][0]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[62][0]~q  & ( \A_SPW_TOP|tx_data|wr_ptr 
// [1] & ( (\A_SPW_TOP|tx_data|mem[46][0]~q  & !\A_SPW_TOP|tx_data|wr_ptr [4]) ) ) ) # ( \A_SPW_TOP|tx_data|mem[62][0]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & ((\A_SPW_TOP|tx_data|mem[44][0]~q ))) # 
// (\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|mem[60][0]~q )) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[62][0]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & ((\A_SPW_TOP|tx_data|mem[44][0]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr 
// [4] & (\A_SPW_TOP|tx_data|mem[60][0]~q )) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[60][0]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[46][0]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[44][0]~q ),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datae(!\A_SPW_TOP|tx_data|mem[62][0]~q ),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux8~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux8~17 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux8~17 .lut_mask = 64'h0F550F55330033FF;
defparam \A_SPW_TOP|tx_data|Mux8~17 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y13_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux8~19 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux8~19_combout  = ( \A_SPW_TOP|tx_data|Mux8~16_combout  & ( \A_SPW_TOP|tx_data|Mux8~17_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & (((\A_SPW_TOP|tx_data|wr_ptr [2]) # (\A_SPW_TOP|tx_data|Mux8~15_combout )))) # 
// (\A_SPW_TOP|tx_data|wr_ptr [0] & (((!\A_SPW_TOP|tx_data|wr_ptr [2])) # (\A_SPW_TOP|tx_data|Mux8~18_combout ))) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux8~16_combout  & ( \A_SPW_TOP|tx_data|Mux8~17_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & 
// (((\A_SPW_TOP|tx_data|wr_ptr [2]) # (\A_SPW_TOP|tx_data|Mux8~15_combout )))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|Mux8~18_combout  & ((\A_SPW_TOP|tx_data|wr_ptr [2])))) ) ) ) # ( \A_SPW_TOP|tx_data|Mux8~16_combout  & ( 
// !\A_SPW_TOP|tx_data|Mux8~17_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & (((\A_SPW_TOP|tx_data|Mux8~15_combout  & !\A_SPW_TOP|tx_data|wr_ptr [2])))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & (((!\A_SPW_TOP|tx_data|wr_ptr [2])) # 
// (\A_SPW_TOP|tx_data|Mux8~18_combout ))) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux8~16_combout  & ( !\A_SPW_TOP|tx_data|Mux8~17_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & (((\A_SPW_TOP|tx_data|Mux8~15_combout  & !\A_SPW_TOP|tx_data|wr_ptr [2])))) # 
// (\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|Mux8~18_combout  & ((\A_SPW_TOP|tx_data|wr_ptr [2])))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux8~18_combout ),
        .datab(!\A_SPW_TOP|tx_data|Mux8~15_combout ),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datae(!\A_SPW_TOP|tx_data|Mux8~16_combout ),
        .dataf(!\A_SPW_TOP|tx_data|Mux8~17_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux8~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux8~19 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux8~19 .lut_mask = 64'h30053F0530F53FF5;
defparam \A_SPW_TOP|tx_data|Mux8~19 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y11_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector166~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector166~0_combout  = ( \A_SPW_TOP|tx_data|Selector158~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux8~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\u0|write_data_fifo_tx|data_out [0])) ) ) # ( !\A_SPW_TOP|tx_data|Selector158~0_combout  & ( \A_SPW_TOP|tx_data|mem[17][0]~q  ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [0]),
        .datab(!\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[17][0]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector158~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector166~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector166~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector166~0 .lut_mask = 64'h00FF00FF35353535;
defparam \A_SPW_TOP|tx_data|Selector166~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y11_N47
dffeas \A_SPW_TOP|tx_data|mem[17][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector166~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[17][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[17][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[17][0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y11_N21
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector22~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector22~0_combout  = ( \A_SPW_TOP|tx_data|Selector14~0_combout  & ( \u0|write_data_fifo_tx|data_out [0] & ( (\A_SPW_TOP|tx_data|state_data_write.00~q ) # (\A_SPW_TOP|tx_data|Mux8~20_combout ) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|Selector14~0_combout  & ( \u0|write_data_fifo_tx|data_out [0] & ( \A_SPW_TOP|tx_data|mem[1][0]~q  ) ) ) # ( \A_SPW_TOP|tx_data|Selector14~0_combout  & ( !\u0|write_data_fifo_tx|data_out [0] & ( (\A_SPW_TOP|tx_data|Mux8~20_combout  & 
// !\A_SPW_TOP|tx_data|state_data_write.00~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|Selector14~0_combout  & ( !\u0|write_data_fifo_tx|data_out [0] & ( \A_SPW_TOP|tx_data|mem[1][0]~q  ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[1][0]~q ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(!\A_SPW_TOP|tx_data|Selector14~0_combout ),
        .dataf(!\u0|write_data_fifo_tx|data_out [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector22~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector22~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector22~0 .lut_mask = 64'h55550F0055550FFF;
defparam \A_SPW_TOP|tx_data|Selector22~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y11_N20
dffeas \A_SPW_TOP|tx_data|mem[1][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector22~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[1][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[1][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[1][0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y11_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector202~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector202~0_combout  = ( \A_SPW_TOP|tx_data|mem[21][0]~q  & ( (!\A_SPW_TOP|tx_data|Selector194~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux8~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [0]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[21][0]~q  & ( (\A_SPW_TOP|tx_data|Selector194~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux8~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [0])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [0]),
        .datab(!\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector194~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[21][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector202~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector202~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector202~0 .lut_mask = 64'h03050305F3F5F3F5;
defparam \A_SPW_TOP|tx_data|Selector202~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y11_N44
dffeas \A_SPW_TOP|tx_data|mem[21][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector202~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[21][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[21][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[21][0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y11_N57
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector58~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector58~0_combout  = ( \A_SPW_TOP|tx_data|mem[5][0]~q  & ( (!\A_SPW_TOP|tx_data|Selector50~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux8~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [0]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[5][0]~q  & ( (\A_SPW_TOP|tx_data|Selector50~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux8~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [0])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [0]),
        .datab(!\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector50~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[5][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector58~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector58~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector58~0 .lut_mask = 64'h03050305F3F5F3F5;
defparam \A_SPW_TOP|tx_data|Selector58~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y11_N17
dffeas \A_SPW_TOP|tx_data|mem[5][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector58~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[5][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[5][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[5][0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y11_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux8~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux8~1_combout  = ( \A_SPW_TOP|tx_data|mem[21][0]~q  & ( \A_SPW_TOP|tx_data|mem[5][0]~q  & ( ((!\A_SPW_TOP|tx_data|wr_ptr [4] & ((\A_SPW_TOP|tx_data|mem[1][0]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|mem[17][0]~q ))) 
// # (\A_SPW_TOP|tx_data|wr_ptr [2]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[21][0]~q  & ( \A_SPW_TOP|tx_data|mem[5][0]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & ((!\A_SPW_TOP|tx_data|wr_ptr [4] & ((\A_SPW_TOP|tx_data|mem[1][0]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr 
// [4] & (\A_SPW_TOP|tx_data|mem[17][0]~q )))) # (\A_SPW_TOP|tx_data|wr_ptr [2] & (((!\A_SPW_TOP|tx_data|wr_ptr [4])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[21][0]~q  & ( !\A_SPW_TOP|tx_data|mem[5][0]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & 
// ((!\A_SPW_TOP|tx_data|wr_ptr [4] & ((\A_SPW_TOP|tx_data|mem[1][0]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|mem[17][0]~q )))) # (\A_SPW_TOP|tx_data|wr_ptr [2] & (((\A_SPW_TOP|tx_data|wr_ptr [4])))) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|mem[21][0]~q  & ( !\A_SPW_TOP|tx_data|mem[5][0]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & ((!\A_SPW_TOP|tx_data|wr_ptr [4] & ((\A_SPW_TOP|tx_data|mem[1][0]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|mem[17][0]~q )))) ) 
// ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datab(!\A_SPW_TOP|tx_data|mem[17][0]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[1][0]~q ),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datae(!\A_SPW_TOP|tx_data|mem[21][0]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[5][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux8~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux8~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux8~1 .lut_mask = 64'h0A220A775F225F77;
defparam \A_SPW_TOP|tx_data|Mux8~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y11_N57
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector49~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector49~0_combout  = ( \A_SPW_TOP|tx_data|mem[4][0]~q  & ( (!\A_SPW_TOP|tx_data|Selector41~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux8~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [0]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[4][0]~q  & ( (\A_SPW_TOP|tx_data|Selector41~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux8~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [0])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [0]),
        .datab(!\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector41~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[4][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector49~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector49~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector49~0 .lut_mask = 64'h03050305F3F5F3F5;
defparam \A_SPW_TOP|tx_data|Selector49~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y11_N35
dffeas \A_SPW_TOP|tx_data|mem[4][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector49~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[4][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[4][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[4][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y11_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector157~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector157~0_combout  = ( \A_SPW_TOP|tx_data|mem[16][0]~q  & ( (!\A_SPW_TOP|tx_data|Selector149~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux8~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [0]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[16][0]~q  & ( (\A_SPW_TOP|tx_data|Selector149~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux8~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [0])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [0]),
        .datab(!\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|tx_data|Selector149~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[16][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector157~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector157~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector157~0 .lut_mask = 64'h00350035FF35FF35;
defparam \A_SPW_TOP|tx_data|Selector157~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y11_N11
dffeas \A_SPW_TOP|tx_data|mem[16][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector157~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[16][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[16][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[16][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y11_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector193~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector193~0_combout  = ( \A_SPW_TOP|tx_data|mem[20][0]~q  & ( (!\A_SPW_TOP|tx_data|Selector185~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux8~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [0])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[20][0]~q  & ( (\A_SPW_TOP|tx_data|Selector185~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux8~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [0]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .datac(!\u0|write_data_fifo_tx|data_out [0]),
        .datad(!\A_SPW_TOP|tx_data|Selector185~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[20][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector193~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector193~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector193~0 .lut_mask = 64'h00270027FF27FF27;
defparam \A_SPW_TOP|tx_data|Selector193~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y11_N8
dffeas \A_SPW_TOP|tx_data|mem[20][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector193~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[20][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[20][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[20][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y11_N27
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector13~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector13~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( \A_SPW_TOP|tx_data|mem[0][0]~q  & ( (!\A_SPW_TOP|tx_data|Selector5~0_combout ) # (\u0|write_data_fifo_tx|data_out [0]) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( \A_SPW_TOP|tx_data|mem[0][0]~q  & ( (!\A_SPW_TOP|tx_data|Selector5~0_combout ) # (\A_SPW_TOP|tx_data|Mux8~20_combout ) ) ) ) # ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( !\A_SPW_TOP|tx_data|mem[0][0]~q  
// & ( (\u0|write_data_fifo_tx|data_out [0] & \A_SPW_TOP|tx_data|Selector5~0_combout ) ) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( !\A_SPW_TOP|tx_data|mem[0][0]~q  & ( (\A_SPW_TOP|tx_data|Mux8~20_combout  & \A_SPW_TOP|tx_data|Selector5~0_combout 
// ) ) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [0]),
        .datab(gnd),
        .datac(!\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .datad(!\A_SPW_TOP|tx_data|Selector5~0_combout ),
        .datae(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[0][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector13~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector13~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector13~0 .lut_mask = 64'h000F0055FF0FFF55;
defparam \A_SPW_TOP|tx_data|Selector13~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y11_N26
dffeas \A_SPW_TOP|tx_data|mem[0][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector13~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[0][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[0][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[0][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y11_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux8~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux8~0_combout  = ( \A_SPW_TOP|tx_data|mem[20][0]~q  & ( \A_SPW_TOP|tx_data|mem[0][0]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & (((!\A_SPW_TOP|tx_data|wr_ptr [4]) # (\A_SPW_TOP|tx_data|mem[16][0]~q )))) # (\A_SPW_TOP|tx_data|wr_ptr [2] & 
// (((\A_SPW_TOP|tx_data|wr_ptr [4])) # (\A_SPW_TOP|tx_data|mem[4][0]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[20][0]~q  & ( \A_SPW_TOP|tx_data|mem[0][0]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & (((!\A_SPW_TOP|tx_data|wr_ptr [4]) # 
// (\A_SPW_TOP|tx_data|mem[16][0]~q )))) # (\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|mem[4][0]~q  & (!\A_SPW_TOP|tx_data|wr_ptr [4]))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[20][0]~q  & ( !\A_SPW_TOP|tx_data|mem[0][0]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr 
// [2] & (((\A_SPW_TOP|tx_data|wr_ptr [4] & \A_SPW_TOP|tx_data|mem[16][0]~q )))) # (\A_SPW_TOP|tx_data|wr_ptr [2] & (((\A_SPW_TOP|tx_data|wr_ptr [4])) # (\A_SPW_TOP|tx_data|mem[4][0]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[20][0]~q  & ( 
// !\A_SPW_TOP|tx_data|mem[0][0]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & (((\A_SPW_TOP|tx_data|wr_ptr [4] & \A_SPW_TOP|tx_data|mem[16][0]~q )))) # (\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|mem[4][0]~q  & (!\A_SPW_TOP|tx_data|wr_ptr [4]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[4][0]~q ),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datad(!\A_SPW_TOP|tx_data|mem[16][0]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[20][0]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[0][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux8~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux8~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux8~0 .lut_mask = 64'h101C131FD0DCD3DF;
defparam \A_SPW_TOP|tx_data|Mux8~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y11_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector40~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector40~0_combout  = ( \A_SPW_TOP|tx_data|mem[3][0]~q  & ( (!\A_SPW_TOP|tx_data|Selector32~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux8~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [0]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[3][0]~q  & ( (\A_SPW_TOP|tx_data|Selector32~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux8~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [0])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [0]),
        .datab(!\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector32~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[3][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector40~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector40~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector40~0 .lut_mask = 64'h03050305F3F5F3F5;
defparam \A_SPW_TOP|tx_data|Selector40~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y11_N35
dffeas \A_SPW_TOP|tx_data|mem[3][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector40~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[3][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[3][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[3][0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y11_N27
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector76~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector76~0_combout  = ( \A_SPW_TOP|tx_data|mem[7][0]~q  & ( (!\A_SPW_TOP|tx_data|Selector68~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux8~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [0]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[7][0]~q  & ( (\A_SPW_TOP|tx_data|Selector68~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux8~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [0])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [0]),
        .datab(!\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector68~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[7][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector76~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector76~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector76~0 .lut_mask = 64'h03050305F3F5F3F5;
defparam \A_SPW_TOP|tx_data|Selector76~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y11_N14
dffeas \A_SPW_TOP|tx_data|mem[7][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector76~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[7][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[7][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[7][0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y11_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector184~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector184~0_combout  = ( \A_SPW_TOP|tx_data|Selector176~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux8~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\u0|write_data_fifo_tx|data_out [0])) ) ) # ( !\A_SPW_TOP|tx_data|Selector176~0_combout  & ( \A_SPW_TOP|tx_data|mem[19][0]~q  ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [0]),
        .datab(!\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|mem[19][0]~q ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector176~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector184~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector184~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector184~0 .lut_mask = 64'h0F0F0F0F33553355;
defparam \A_SPW_TOP|tx_data|Selector184~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y11_N38
dffeas \A_SPW_TOP|tx_data|mem[19][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector184~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[19][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[19][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[19][0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y11_N51
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector220~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector220~0_combout  = ( \A_SPW_TOP|tx_data|mem[23][0]~q  & ( (!\A_SPW_TOP|tx_data|Selector212~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux8~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [0]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[23][0]~q  & ( (\A_SPW_TOP|tx_data|Selector212~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux8~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [0])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [0]),
        .datab(!\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector212~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[23][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector220~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector220~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector220~0 .lut_mask = 64'h03050305F3F5F3F5;
defparam \A_SPW_TOP|tx_data|Selector220~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y11_N11
dffeas \A_SPW_TOP|tx_data|mem[23][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector220~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[23][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[23][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[23][0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y11_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux8~3 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux8~3_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [4] & ( \A_SPW_TOP|tx_data|mem[23][0]~q  & ( (\A_SPW_TOP|tx_data|wr_ptr [2]) # (\A_SPW_TOP|tx_data|mem[19][0]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [4] & ( \A_SPW_TOP|tx_data|mem[23][0]~q 
//  & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|mem[3][0]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [2] & ((\A_SPW_TOP|tx_data|mem[7][0]~q ))) ) ) ) # ( \A_SPW_TOP|tx_data|wr_ptr [4] & ( !\A_SPW_TOP|tx_data|mem[23][0]~q  & ( 
// (\A_SPW_TOP|tx_data|mem[19][0]~q  & !\A_SPW_TOP|tx_data|wr_ptr [2]) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [4] & ( !\A_SPW_TOP|tx_data|mem[23][0]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|mem[3][0]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [2] & 
// ((\A_SPW_TOP|tx_data|mem[7][0]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[3][0]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[7][0]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[19][0]~q ),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .dataf(!\A_SPW_TOP|tx_data|mem[23][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux8~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux8~3 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux8~3 .lut_mask = 64'h55330F0055330FFF;
defparam \A_SPW_TOP|tx_data|Mux8~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y11_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector31~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector31~0_combout  = ( \A_SPW_TOP|tx_data|mem[2][0]~q  & ( (!\A_SPW_TOP|tx_data|Selector23~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux8~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [0])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[2][0]~q  & ( (\A_SPW_TOP|tx_data|Selector23~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux8~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [0]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .datac(!\u0|write_data_fifo_tx|data_out [0]),
        .datad(!\A_SPW_TOP|tx_data|Selector23~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[2][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector31~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector31~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector31~0 .lut_mask = 64'h00270027FF27FF27;
defparam \A_SPW_TOP|tx_data|Selector31~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y11_N53
dffeas \A_SPW_TOP|tx_data|mem[2][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector31~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[2][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[2][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[2][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y11_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector175~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector175~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector167~0_combout  & ((\A_SPW_TOP|tx_data|mem[18][0]~q ))) # (\A_SPW_TOP|tx_data|Selector167~0_combout  & (\u0|write_data_fifo_tx|data_out 
// [0])) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector167~0_combout  & (\A_SPW_TOP|tx_data|mem[18][0]~q )) # (\A_SPW_TOP|tx_data|Selector167~0_combout  & ((\A_SPW_TOP|tx_data|Mux8~20_combout ))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [0]),
        .datab(!\A_SPW_TOP|tx_data|mem[18][0]~q ),
        .datac(!\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .datad(!\A_SPW_TOP|tx_data|Selector167~0_combout ),
        .datae(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector175~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector175~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector175~0 .lut_mask = 64'h330F3355330F3355;
defparam \A_SPW_TOP|tx_data|Selector175~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y11_N17
dffeas \A_SPW_TOP|tx_data|mem[18][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector175~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[18][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[18][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[18][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y11_N45
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector67~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector67~0_combout  = ( \u0|write_data_fifo_tx|data_out [0] & ( (!\A_SPW_TOP|tx_data|Selector59~0_combout  & (((\A_SPW_TOP|tx_data|mem[6][0]~q )))) # (\A_SPW_TOP|tx_data|Selector59~0_combout  & (((\A_SPW_TOP|tx_data|Mux8~20_combout )) 
// # (\A_SPW_TOP|tx_data|state_data_write.00~q ))) ) ) # ( !\u0|write_data_fifo_tx|data_out [0] & ( (!\A_SPW_TOP|tx_data|Selector59~0_combout  & (((\A_SPW_TOP|tx_data|mem[6][0]~q )))) # (\A_SPW_TOP|tx_data|Selector59~0_combout  & 
// (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux8~20_combout ))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector59~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|mem[6][0]~q ),
        .datae(gnd),
        .dataf(!\u0|write_data_fifo_tx|data_out [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector67~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector67~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector67~0 .lut_mask = 64'h02F202F207F707F7;
defparam \A_SPW_TOP|tx_data|Selector67~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y11_N23
dffeas \A_SPW_TOP|tx_data|mem[6][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector67~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[6][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[6][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[6][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y11_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux8~2 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux8~2_combout  = ( \A_SPW_TOP|tx_data|mem[22][0]~q  & ( \A_SPW_TOP|tx_data|wr_ptr [4] & ( (\A_SPW_TOP|tx_data|wr_ptr [2]) # (\A_SPW_TOP|tx_data|mem[18][0]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[22][0]~q  & ( \A_SPW_TOP|tx_data|wr_ptr 
// [4] & ( (\A_SPW_TOP|tx_data|mem[18][0]~q  & !\A_SPW_TOP|tx_data|wr_ptr [2]) ) ) ) # ( \A_SPW_TOP|tx_data|mem[22][0]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [4] & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|mem[2][0]~q )) # (\A_SPW_TOP|tx_data|wr_ptr 
// [2] & ((\A_SPW_TOP|tx_data|mem[6][0]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[22][0]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [4] & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|mem[2][0]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [2] & 
// ((\A_SPW_TOP|tx_data|mem[6][0]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[2][0]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[18][0]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[6][0]~q ),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datae(!\A_SPW_TOP|tx_data|mem[22][0]~q ),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux8~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux8~2 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux8~2 .lut_mask = 64'h550F550F330033FF;
defparam \A_SPW_TOP|tx_data|Mux8~2 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y11_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux8~4 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux8~4_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [1] & ( \A_SPW_TOP|tx_data|Mux8~2_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [0]) # (\A_SPW_TOP|tx_data|Mux8~3_combout ) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( 
// \A_SPW_TOP|tx_data|Mux8~2_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|Mux8~0_combout ))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|Mux8~1_combout )) ) ) ) # ( \A_SPW_TOP|tx_data|wr_ptr [1] & ( 
// !\A_SPW_TOP|tx_data|Mux8~2_combout  & ( (\A_SPW_TOP|tx_data|wr_ptr [0] & \A_SPW_TOP|tx_data|Mux8~3_combout ) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( !\A_SPW_TOP|tx_data|Mux8~2_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & 
// ((\A_SPW_TOP|tx_data|Mux8~0_combout ))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|Mux8~1_combout )) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datab(!\A_SPW_TOP|tx_data|Mux8~1_combout ),
        .datac(!\A_SPW_TOP|tx_data|Mux8~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux8~3_combout ),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .dataf(!\A_SPW_TOP|tx_data|Mux8~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux8~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux8~4 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux8~4 .lut_mask = 64'h1B1B00551B1BAAFF;
defparam \A_SPW_TOP|tx_data|Mux8~4 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y13_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux8~20 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux8~20_combout  = ( \A_SPW_TOP|tx_data|Mux8~4_combout  & ( \A_SPW_TOP|tx_data|wr_ptr [3] & ( (!\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|Mux8~9_combout )) # (\A_SPW_TOP|tx_data|wr_ptr [5] & 
// ((\A_SPW_TOP|tx_data|Mux8~19_combout ))) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux8~4_combout  & ( \A_SPW_TOP|tx_data|wr_ptr [3] & ( (!\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|Mux8~9_combout )) # (\A_SPW_TOP|tx_data|wr_ptr [5] & 
// ((\A_SPW_TOP|tx_data|Mux8~19_combout ))) ) ) ) # ( \A_SPW_TOP|tx_data|Mux8~4_combout  & ( !\A_SPW_TOP|tx_data|wr_ptr [3] & ( (!\A_SPW_TOP|tx_data|wr_ptr [5]) # (\A_SPW_TOP|tx_data|Mux8~14_combout ) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux8~4_combout  & ( 
// !\A_SPW_TOP|tx_data|wr_ptr [3] & ( (\A_SPW_TOP|tx_data|Mux8~14_combout  & \A_SPW_TOP|tx_data|wr_ptr [5]) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux8~14_combout ),
        .datab(!\A_SPW_TOP|tx_data|Mux8~9_combout ),
        .datac(!\A_SPW_TOP|tx_data|Mux8~19_combout ),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datae(!\A_SPW_TOP|tx_data|Mux8~4_combout ),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux8~20 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux8~20 .lut_mask = 64'h0055FF55330F330F;
defparam \A_SPW_TOP|tx_data|Mux8~20 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y11_N39
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector211~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector211~0_combout  = ( \u0|write_data_fifo_tx|data_out [0] & ( (!\A_SPW_TOP|tx_data|Selector203~0_combout  & (((\A_SPW_TOP|tx_data|mem[22][0]~q )))) # (\A_SPW_TOP|tx_data|Selector203~0_combout  & 
// (((\A_SPW_TOP|tx_data|Mux8~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q ))) ) ) # ( !\u0|write_data_fifo_tx|data_out [0] & ( (!\A_SPW_TOP|tx_data|Selector203~0_combout  & (((\A_SPW_TOP|tx_data|mem[22][0]~q )))) # 
// (\A_SPW_TOP|tx_data|Selector203~0_combout  & (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux8~20_combout ))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux8~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector203~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|mem[22][0]~q ),
        .datae(gnd),
        .dataf(!\u0|write_data_fifo_tx|data_out [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector211~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector211~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector211~0 .lut_mask = 64'h02F202F207F707F7;
defparam \A_SPW_TOP|tx_data|Selector211~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y11_N2
dffeas \A_SPW_TOP|tx_data|mem[22][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector211~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[22][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[22][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[22][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y11_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux17~2 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux17~2_combout  = ( \A_SPW_TOP|tx_data|rd_ptr [1] & ( \A_SPW_TOP|tx_data|mem[16][0]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & ((\A_SPW_TOP|tx_data|mem[18][0]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[22][0]~q )) ) 
// ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [1] & ( \A_SPW_TOP|tx_data|mem[16][0]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [2]) # (\A_SPW_TOP|tx_data|mem[20][0]~q ) ) ) ) # ( \A_SPW_TOP|tx_data|rd_ptr [1] & ( !\A_SPW_TOP|tx_data|mem[16][0]~q  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [2] & ((\A_SPW_TOP|tx_data|mem[18][0]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[22][0]~q )) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [1] & ( !\A_SPW_TOP|tx_data|mem[16][0]~q  & ( 
// (\A_SPW_TOP|tx_data|mem[20][0]~q  & \A_SPW_TOP|tx_data|rd_ptr [2]) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[22][0]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[20][0]~q ),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .datad(!\A_SPW_TOP|tx_data|mem[18][0]~q ),
        .datae(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .dataf(!\A_SPW_TOP|tx_data|mem[16][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux17~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux17~2 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux17~2 .lut_mask = 64'h030305F5F3F305F5;
defparam \A_SPW_TOP|tx_data|Mux17~2 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y11_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux17~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux17~1_combout  = ( \A_SPW_TOP|tx_data|mem[7][0]~q  & ( \A_SPW_TOP|tx_data|mem[1][0]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [1] & (((!\A_SPW_TOP|tx_data|rd_ptr [2]) # (\A_SPW_TOP|tx_data|mem[5][0]~q )))) # (\A_SPW_TOP|tx_data|rd_ptr [1] & 
// (((\A_SPW_TOP|tx_data|rd_ptr [2])) # (\A_SPW_TOP|tx_data|mem[3][0]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[7][0]~q  & ( \A_SPW_TOP|tx_data|mem[1][0]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [1] & (((!\A_SPW_TOP|tx_data|rd_ptr [2]) # 
// (\A_SPW_TOP|tx_data|mem[5][0]~q )))) # (\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|mem[3][0]~q  & (!\A_SPW_TOP|tx_data|rd_ptr [2]))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[7][0]~q  & ( !\A_SPW_TOP|tx_data|mem[1][0]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr 
// [1] & (((\A_SPW_TOP|tx_data|rd_ptr [2] & \A_SPW_TOP|tx_data|mem[5][0]~q )))) # (\A_SPW_TOP|tx_data|rd_ptr [1] & (((\A_SPW_TOP|tx_data|rd_ptr [2])) # (\A_SPW_TOP|tx_data|mem[3][0]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[7][0]~q  & ( 
// !\A_SPW_TOP|tx_data|mem[1][0]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [1] & (((\A_SPW_TOP|tx_data|rd_ptr [2] & \A_SPW_TOP|tx_data|mem[5][0]~q )))) # (\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|mem[3][0]~q  & (!\A_SPW_TOP|tx_data|rd_ptr [2]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[3][0]~q ),
        .datab(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .datad(!\A_SPW_TOP|tx_data|mem[5][0]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[7][0]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[1][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux17~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux17~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux17~1 .lut_mask = 64'h101C131FD0DCD3DF;
defparam \A_SPW_TOP|tx_data|Mux17~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y11_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux17~3 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux17~3_combout  = ( \A_SPW_TOP|tx_data|mem[19][0]~q  & ( \A_SPW_TOP|tx_data|mem[21][0]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [1] & (((\A_SPW_TOP|tx_data|rd_ptr [2])) # (\A_SPW_TOP|tx_data|mem[17][0]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [1] 
// & (((!\A_SPW_TOP|tx_data|rd_ptr [2]) # (\A_SPW_TOP|tx_data|mem[23][0]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[19][0]~q  & ( \A_SPW_TOP|tx_data|mem[21][0]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [1] & (((\A_SPW_TOP|tx_data|rd_ptr [2])) # 
// (\A_SPW_TOP|tx_data|mem[17][0]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [1] & (((\A_SPW_TOP|tx_data|rd_ptr [2] & \A_SPW_TOP|tx_data|mem[23][0]~q )))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[19][0]~q  & ( !\A_SPW_TOP|tx_data|mem[21][0]~q  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|mem[17][0]~q  & (!\A_SPW_TOP|tx_data|rd_ptr [2]))) # (\A_SPW_TOP|tx_data|rd_ptr [1] & (((!\A_SPW_TOP|tx_data|rd_ptr [2]) # (\A_SPW_TOP|tx_data|mem[23][0]~q )))) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|mem[19][0]~q  & ( !\A_SPW_TOP|tx_data|mem[21][0]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|mem[17][0]~q  & (!\A_SPW_TOP|tx_data|rd_ptr [2]))) # (\A_SPW_TOP|tx_data|rd_ptr [1] & (((\A_SPW_TOP|tx_data|rd_ptr [2] & 
// \A_SPW_TOP|tx_data|mem[23][0]~q )))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .datab(!\A_SPW_TOP|tx_data|mem[17][0]~q ),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .datad(!\A_SPW_TOP|tx_data|mem[23][0]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[19][0]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[21][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux17~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux17~3 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux17~3 .lut_mask = 64'h202570752A2F7A7F;
defparam \A_SPW_TOP|tx_data|Mux17~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y11_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux17~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux17~0_combout  = ( \A_SPW_TOP|tx_data|mem[6][0]~q  & ( \A_SPW_TOP|tx_data|mem[4][0]~q  & ( ((!\A_SPW_TOP|tx_data|rd_ptr [1] & ((\A_SPW_TOP|tx_data|mem[0][0]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|mem[2][0]~q ))) 
// # (\A_SPW_TOP|tx_data|rd_ptr [2]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[6][0]~q  & ( \A_SPW_TOP|tx_data|mem[4][0]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [1] & (((\A_SPW_TOP|tx_data|rd_ptr [2]) # (\A_SPW_TOP|tx_data|mem[0][0]~q )))) # (\A_SPW_TOP|tx_data|rd_ptr 
// [1] & (\A_SPW_TOP|tx_data|mem[2][0]~q  & ((!\A_SPW_TOP|tx_data|rd_ptr [2])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[6][0]~q  & ( !\A_SPW_TOP|tx_data|mem[4][0]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [1] & (((\A_SPW_TOP|tx_data|mem[0][0]~q  & 
// !\A_SPW_TOP|tx_data|rd_ptr [2])))) # (\A_SPW_TOP|tx_data|rd_ptr [1] & (((\A_SPW_TOP|tx_data|rd_ptr [2])) # (\A_SPW_TOP|tx_data|mem[2][0]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[6][0]~q  & ( !\A_SPW_TOP|tx_data|mem[4][0]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr 
// [2] & ((!\A_SPW_TOP|tx_data|rd_ptr [1] & ((\A_SPW_TOP|tx_data|mem[0][0]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|mem[2][0]~q )))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[2][0]~q ),
        .datab(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .datac(!\A_SPW_TOP|tx_data|mem[0][0]~q ),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .datae(!\A_SPW_TOP|tx_data|mem[6][0]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[4][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux17~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux17~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux17~0 .lut_mask = 64'h1D001D331DCC1DFF;
defparam \A_SPW_TOP|tx_data|Mux17~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y11_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux17~4 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux17~4_combout  = ( \A_SPW_TOP|tx_data|rd_ptr [0] & ( \A_SPW_TOP|tx_data|Mux17~0_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & (\A_SPW_TOP|tx_data|Mux17~1_combout )) # (\A_SPW_TOP|tx_data|rd_ptr [4] & 
// ((\A_SPW_TOP|tx_data|Mux17~3_combout ))) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [0] & ( \A_SPW_TOP|tx_data|Mux17~0_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4]) # (\A_SPW_TOP|tx_data|Mux17~2_combout ) ) ) ) # ( \A_SPW_TOP|tx_data|rd_ptr [0] & ( 
// !\A_SPW_TOP|tx_data|Mux17~0_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & (\A_SPW_TOP|tx_data|Mux17~1_combout )) # (\A_SPW_TOP|tx_data|rd_ptr [4] & ((\A_SPW_TOP|tx_data|Mux17~3_combout ))) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [0] & ( 
// !\A_SPW_TOP|tx_data|Mux17~0_combout  & ( (\A_SPW_TOP|tx_data|Mux17~2_combout  & \A_SPW_TOP|tx_data|rd_ptr [4]) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux17~2_combout ),
        .datab(!\A_SPW_TOP|tx_data|Mux17~1_combout ),
        .datac(!\A_SPW_TOP|tx_data|Mux17~3_combout ),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .datae(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .dataf(!\A_SPW_TOP|tx_data|Mux17~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux17~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux17~4 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux17~4 .lut_mask = 64'h0055330FFF55330F;
defparam \A_SPW_TOP|tx_data|Mux17~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y12_N51
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux17~12 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux17~12_combout  = ( \A_SPW_TOP|tx_data|mem[25][0]~q  & ( \A_SPW_TOP|tx_data|mem[27][0]~q  & ( ((!\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|mem[24][0]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [1] & ((\A_SPW_TOP|tx_data|mem[26][0]~q 
// )))) # (\A_SPW_TOP|tx_data|rd_ptr [0]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[25][0]~q  & ( \A_SPW_TOP|tx_data|mem[27][0]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [0] & ((!\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|mem[24][0]~q )) # 
// (\A_SPW_TOP|tx_data|rd_ptr [1] & ((\A_SPW_TOP|tx_data|mem[26][0]~q ))))) # (\A_SPW_TOP|tx_data|rd_ptr [0] & (((\A_SPW_TOP|tx_data|rd_ptr [1])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[25][0]~q  & ( !\A_SPW_TOP|tx_data|mem[27][0]~q  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [0] & ((!\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|mem[24][0]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [1] & ((\A_SPW_TOP|tx_data|mem[26][0]~q ))))) # (\A_SPW_TOP|tx_data|rd_ptr [0] & (((!\A_SPW_TOP|tx_data|rd_ptr [1])))) ) 
// ) ) # ( !\A_SPW_TOP|tx_data|mem[25][0]~q  & ( !\A_SPW_TOP|tx_data|mem[27][0]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [0] & ((!\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|mem[24][0]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [1] & 
// ((\A_SPW_TOP|tx_data|mem[26][0]~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[24][0]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[26][0]~q ),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .datae(!\A_SPW_TOP|tx_data|mem[25][0]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[27][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux17~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux17~12 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux17~12 .lut_mask = 64'h50305F30503F5F3F;
defparam \A_SPW_TOP|tx_data|Mux17~12 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y12_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux17~13 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux17~13_combout  = ( \A_SPW_TOP|tx_data|mem[29][0]~q  & ( \A_SPW_TOP|tx_data|mem[31][0]~q  & ( ((!\A_SPW_TOP|tx_data|rd_ptr [1] & ((\A_SPW_TOP|tx_data|mem[28][0]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|mem[30][0]~q 
// ))) # (\A_SPW_TOP|tx_data|rd_ptr [0]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[29][0]~q  & ( \A_SPW_TOP|tx_data|mem[31][0]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [0] & ((!\A_SPW_TOP|tx_data|rd_ptr [1] & ((\A_SPW_TOP|tx_data|mem[28][0]~q ))) # 
// (\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|mem[30][0]~q )))) # (\A_SPW_TOP|tx_data|rd_ptr [0] & (((\A_SPW_TOP|tx_data|rd_ptr [1])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[29][0]~q  & ( !\A_SPW_TOP|tx_data|mem[31][0]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr 
// [0] & ((!\A_SPW_TOP|tx_data|rd_ptr [1] & ((\A_SPW_TOP|tx_data|mem[28][0]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|mem[30][0]~q )))) # (\A_SPW_TOP|tx_data|rd_ptr [0] & (((!\A_SPW_TOP|tx_data|rd_ptr [1])))) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|mem[29][0]~q  & ( !\A_SPW_TOP|tx_data|mem[31][0]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [0] & ((!\A_SPW_TOP|tx_data|rd_ptr [1] & ((\A_SPW_TOP|tx_data|mem[28][0]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|mem[30][0]~q )))) 
// ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[30][0]~q ),
        .datab(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .datad(!\A_SPW_TOP|tx_data|mem[28][0]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[29][0]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[31][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux17~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux17~13 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux17~13 .lut_mask = 64'h04C434F407C737F7;
defparam \A_SPW_TOP|tx_data|Mux17~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y12_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux17~10 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux17~10_combout  = ( \A_SPW_TOP|tx_data|mem[8][0]~q  & ( \A_SPW_TOP|tx_data|mem[9][0]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [1]) # ((!\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|mem[10][0]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [0] & 
// ((\A_SPW_TOP|tx_data|mem[11][0]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[8][0]~q  & ( \A_SPW_TOP|tx_data|mem[9][0]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [1] & (((\A_SPW_TOP|tx_data|rd_ptr [0])))) # (\A_SPW_TOP|tx_data|rd_ptr [1] & 
// ((!\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|mem[10][0]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [0] & ((\A_SPW_TOP|tx_data|mem[11][0]~q ))))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[8][0]~q  & ( !\A_SPW_TOP|tx_data|mem[9][0]~q  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [1] & (((!\A_SPW_TOP|tx_data|rd_ptr [0])))) # (\A_SPW_TOP|tx_data|rd_ptr [1] & ((!\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|mem[10][0]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [0] & ((\A_SPW_TOP|tx_data|mem[11][0]~q ))))) ) 
// ) ) # ( !\A_SPW_TOP|tx_data|mem[8][0]~q  & ( !\A_SPW_TOP|tx_data|mem[9][0]~q  & ( (\A_SPW_TOP|tx_data|rd_ptr [1] & ((!\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|mem[10][0]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [0] & ((\A_SPW_TOP|tx_data|mem[11][0]~q 
// ))))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .datab(!\A_SPW_TOP|tx_data|mem[10][0]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[11][0]~q ),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .datae(!\A_SPW_TOP|tx_data|mem[8][0]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[9][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux17~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux17~10 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux17~10 .lut_mask = 64'h1105BB0511AFBBAF;
defparam \A_SPW_TOP|tx_data|Mux17~10 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y12_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux17~11 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux17~11_combout  = ( \A_SPW_TOP|tx_data|rd_ptr [1] & ( \A_SPW_TOP|tx_data|mem[15][0]~q  & ( (\A_SPW_TOP|tx_data|mem[14][0]~q ) # (\A_SPW_TOP|tx_data|rd_ptr [0]) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [1] & ( 
// \A_SPW_TOP|tx_data|mem[15][0]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|mem[12][0]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [0] & ((\A_SPW_TOP|tx_data|mem[13][0]~q ))) ) ) ) # ( \A_SPW_TOP|tx_data|rd_ptr [1] & ( 
// !\A_SPW_TOP|tx_data|mem[15][0]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [0] & \A_SPW_TOP|tx_data|mem[14][0]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [1] & ( !\A_SPW_TOP|tx_data|mem[15][0]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|mem[12][0]~q 
// )) # (\A_SPW_TOP|tx_data|rd_ptr [0] & ((\A_SPW_TOP|tx_data|mem[13][0]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[12][0]~q ),
        .datab(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .datac(!\A_SPW_TOP|tx_data|mem[14][0]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[13][0]~q ),
        .datae(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .dataf(!\A_SPW_TOP|tx_data|mem[15][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux17~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux17~11 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux17~11 .lut_mask = 64'h44770C0C44773F3F;
defparam \A_SPW_TOP|tx_data|Mux17~11 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y12_N57
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux17~14 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux17~14_combout  = ( \A_SPW_TOP|tx_data|Mux17~10_combout  & ( \A_SPW_TOP|tx_data|Mux17~11_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4]) # ((!\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|Mux17~12_combout )) # 
// (\A_SPW_TOP|tx_data|rd_ptr [2] & ((\A_SPW_TOP|tx_data|Mux17~13_combout )))) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux17~10_combout  & ( \A_SPW_TOP|tx_data|Mux17~11_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & (((\A_SPW_TOP|tx_data|rd_ptr [2])))) # 
// (\A_SPW_TOP|tx_data|rd_ptr [4] & ((!\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|Mux17~12_combout )) # (\A_SPW_TOP|tx_data|rd_ptr [2] & ((\A_SPW_TOP|tx_data|Mux17~13_combout ))))) ) ) ) # ( \A_SPW_TOP|tx_data|Mux17~10_combout  & ( 
// !\A_SPW_TOP|tx_data|Mux17~11_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & (((!\A_SPW_TOP|tx_data|rd_ptr [2])))) # (\A_SPW_TOP|tx_data|rd_ptr [4] & ((!\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|Mux17~12_combout )) # (\A_SPW_TOP|tx_data|rd_ptr 
// [2] & ((\A_SPW_TOP|tx_data|Mux17~13_combout ))))) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux17~10_combout  & ( !\A_SPW_TOP|tx_data|Mux17~11_combout  & ( (\A_SPW_TOP|tx_data|rd_ptr [4] & ((!\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|Mux17~12_combout )) # 
// (\A_SPW_TOP|tx_data|rd_ptr [2] & ((\A_SPW_TOP|tx_data|Mux17~13_combout ))))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux17~12_combout ),
        .datab(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .datac(!\A_SPW_TOP|tx_data|Mux17~13_combout ),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .datae(!\A_SPW_TOP|tx_data|Mux17~10_combout ),
        .dataf(!\A_SPW_TOP|tx_data|Mux17~11_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux17~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux17~14 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux17~14 .lut_mask = 64'h1103DD0311CFDDCF;
defparam \A_SPW_TOP|tx_data|Mux17~14 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y13_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux17~17 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux17~17_combout  = ( \A_SPW_TOP|tx_data|mem[46][0]~q  & ( \A_SPW_TOP|tx_data|mem[58][0]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & (((\A_SPW_TOP|tx_data|rd_ptr [4])) # (\A_SPW_TOP|tx_data|mem[42][0]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [2] 
// & (((!\A_SPW_TOP|tx_data|rd_ptr [4]) # (\A_SPW_TOP|tx_data|mem[62][0]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[46][0]~q  & ( \A_SPW_TOP|tx_data|mem[58][0]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & (((\A_SPW_TOP|tx_data|rd_ptr [4])) # 
// (\A_SPW_TOP|tx_data|mem[42][0]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [2] & (((\A_SPW_TOP|tx_data|mem[62][0]~q  & \A_SPW_TOP|tx_data|rd_ptr [4])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[46][0]~q  & ( !\A_SPW_TOP|tx_data|mem[58][0]~q  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[42][0]~q  & ((!\A_SPW_TOP|tx_data|rd_ptr [4])))) # (\A_SPW_TOP|tx_data|rd_ptr [2] & (((!\A_SPW_TOP|tx_data|rd_ptr [4]) # (\A_SPW_TOP|tx_data|mem[62][0]~q )))) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|mem[46][0]~q  & ( !\A_SPW_TOP|tx_data|mem[58][0]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[42][0]~q  & ((!\A_SPW_TOP|tx_data|rd_ptr [4])))) # (\A_SPW_TOP|tx_data|rd_ptr [2] & (((\A_SPW_TOP|tx_data|mem[62][0]~q  & 
// \A_SPW_TOP|tx_data|rd_ptr [4])))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .datab(!\A_SPW_TOP|tx_data|mem[42][0]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[62][0]~q ),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .datae(!\A_SPW_TOP|tx_data|mem[46][0]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[58][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux17~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux17~17 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux17~17 .lut_mask = 64'h2205770522AF77AF;
defparam \A_SPW_TOP|tx_data|Mux17~17 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y13_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux17~16 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux17~16_combout  = ( \A_SPW_TOP|tx_data|rd_ptr [4] & ( \A_SPW_TOP|tx_data|mem[61][0]~q  & ( (\A_SPW_TOP|tx_data|rd_ptr [2]) # (\A_SPW_TOP|tx_data|mem[57][0]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [4] & ( 
// \A_SPW_TOP|tx_data|mem[61][0]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[41][0]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [2] & ((\A_SPW_TOP|tx_data|mem[45][0]~q ))) ) ) ) # ( \A_SPW_TOP|tx_data|rd_ptr [4] & ( 
// !\A_SPW_TOP|tx_data|mem[61][0]~q  & ( (\A_SPW_TOP|tx_data|mem[57][0]~q  & !\A_SPW_TOP|tx_data|rd_ptr [2]) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [4] & ( !\A_SPW_TOP|tx_data|mem[61][0]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[41][0]~q 
// )) # (\A_SPW_TOP|tx_data|rd_ptr [2] & ((\A_SPW_TOP|tx_data|mem[45][0]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[57][0]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[41][0]~q ),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .datad(!\A_SPW_TOP|tx_data|mem[45][0]~q ),
        .datae(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .dataf(!\A_SPW_TOP|tx_data|mem[61][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux17~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux17~16 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux17~16 .lut_mask = 64'h303F5050303F5F5F;
defparam \A_SPW_TOP|tx_data|Mux17~16 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y13_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux17~15 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux17~15_combout  = ( \A_SPW_TOP|tx_data|mem[60][0]~q  & ( \A_SPW_TOP|tx_data|mem[40][0]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & (((!\A_SPW_TOP|tx_data|rd_ptr [4]) # (\A_SPW_TOP|tx_data|mem[56][0]~q )))) # (\A_SPW_TOP|tx_data|rd_ptr 
// [2] & (((\A_SPW_TOP|tx_data|rd_ptr [4])) # (\A_SPW_TOP|tx_data|mem[44][0]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[60][0]~q  & ( \A_SPW_TOP|tx_data|mem[40][0]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & (((!\A_SPW_TOP|tx_data|rd_ptr [4]) # 
// (\A_SPW_TOP|tx_data|mem[56][0]~q )))) # (\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[44][0]~q  & ((!\A_SPW_TOP|tx_data|rd_ptr [4])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[60][0]~q  & ( !\A_SPW_TOP|tx_data|mem[40][0]~q  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [2] & (((\A_SPW_TOP|tx_data|mem[56][0]~q  & \A_SPW_TOP|tx_data|rd_ptr [4])))) # (\A_SPW_TOP|tx_data|rd_ptr [2] & (((\A_SPW_TOP|tx_data|rd_ptr [4])) # (\A_SPW_TOP|tx_data|mem[44][0]~q ))) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|mem[60][0]~q  & ( !\A_SPW_TOP|tx_data|mem[40][0]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & (((\A_SPW_TOP|tx_data|mem[56][0]~q  & \A_SPW_TOP|tx_data|rd_ptr [4])))) # (\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[44][0]~q  & 
// ((!\A_SPW_TOP|tx_data|rd_ptr [4])))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[44][0]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[56][0]~q ),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .datae(!\A_SPW_TOP|tx_data|mem[60][0]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[40][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux17~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux17~15 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux17~15 .lut_mask = 64'h0530053FF530F53F;
defparam \A_SPW_TOP|tx_data|Mux17~15 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y13_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux17~18 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux17~18_combout  = ( \A_SPW_TOP|tx_data|mem[47][0]~q  & ( \A_SPW_TOP|tx_data|mem[43][0]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4]) # ((!\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[59][0]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [2] & 
// ((\A_SPW_TOP|tx_data|mem[63][0]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[47][0]~q  & ( \A_SPW_TOP|tx_data|mem[43][0]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & (((!\A_SPW_TOP|tx_data|rd_ptr [4])) # (\A_SPW_TOP|tx_data|mem[59][0]~q ))) # 
// (\A_SPW_TOP|tx_data|rd_ptr [2] & (((\A_SPW_TOP|tx_data|mem[63][0]~q  & \A_SPW_TOP|tx_data|rd_ptr [4])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[47][0]~q  & ( !\A_SPW_TOP|tx_data|mem[43][0]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & 
// (\A_SPW_TOP|tx_data|mem[59][0]~q  & ((\A_SPW_TOP|tx_data|rd_ptr [4])))) # (\A_SPW_TOP|tx_data|rd_ptr [2] & (((!\A_SPW_TOP|tx_data|rd_ptr [4]) # (\A_SPW_TOP|tx_data|mem[63][0]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[47][0]~q  & ( 
// !\A_SPW_TOP|tx_data|mem[43][0]~q  & ( (\A_SPW_TOP|tx_data|rd_ptr [4] & ((!\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[59][0]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [2] & ((\A_SPW_TOP|tx_data|mem[63][0]~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .datab(!\A_SPW_TOP|tx_data|mem[59][0]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[63][0]~q ),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .datae(!\A_SPW_TOP|tx_data|mem[47][0]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[43][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux17~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux17~18 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux17~18 .lut_mask = 64'h00275527AA27FF27;
defparam \A_SPW_TOP|tx_data|Mux17~18 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y13_N9
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux17~19 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux17~19_combout  = ( \A_SPW_TOP|tx_data|Mux17~18_combout  & ( \A_SPW_TOP|tx_data|rd_ptr [0] & ( (\A_SPW_TOP|tx_data|rd_ptr [1]) # (\A_SPW_TOP|tx_data|Mux17~16_combout ) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux17~18_combout  & ( 
// \A_SPW_TOP|tx_data|rd_ptr [0] & ( (\A_SPW_TOP|tx_data|Mux17~16_combout  & !\A_SPW_TOP|tx_data|rd_ptr [1]) ) ) ) # ( \A_SPW_TOP|tx_data|Mux17~18_combout  & ( !\A_SPW_TOP|tx_data|rd_ptr [0] & ( (!\A_SPW_TOP|tx_data|rd_ptr [1] & 
// ((\A_SPW_TOP|tx_data|Mux17~15_combout ))) # (\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|Mux17~17_combout )) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux17~18_combout  & ( !\A_SPW_TOP|tx_data|rd_ptr [0] & ( (!\A_SPW_TOP|tx_data|rd_ptr [1] & 
// ((\A_SPW_TOP|tx_data|Mux17~15_combout ))) # (\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|Mux17~17_combout )) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux17~17_combout ),
        .datab(!\A_SPW_TOP|tx_data|Mux17~16_combout ),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .datad(!\A_SPW_TOP|tx_data|Mux17~15_combout ),
        .datae(!\A_SPW_TOP|tx_data|Mux17~18_combout ),
        .dataf(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux17~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux17~19 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux17~19 .lut_mask = 64'h05F505F530303F3F;
defparam \A_SPW_TOP|tx_data|Mux17~19 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y15_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux17~6 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux17~6_combout  = ( \A_SPW_TOP|tx_data|mem[39][0]~q  & ( \A_SPW_TOP|tx_data|mem[35][0]~q  & ( ((!\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[33][0]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [2] & ((\A_SPW_TOP|tx_data|mem[37][0]~q 
// )))) # (\A_SPW_TOP|tx_data|rd_ptr [1]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[39][0]~q  & ( \A_SPW_TOP|tx_data|mem[35][0]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [1] & ((!\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[33][0]~q )) # 
// (\A_SPW_TOP|tx_data|rd_ptr [2] & ((\A_SPW_TOP|tx_data|mem[37][0]~q ))))) # (\A_SPW_TOP|tx_data|rd_ptr [1] & (((!\A_SPW_TOP|tx_data|rd_ptr [2])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[39][0]~q  & ( !\A_SPW_TOP|tx_data|mem[35][0]~q  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [1] & ((!\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[33][0]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [2] & ((\A_SPW_TOP|tx_data|mem[37][0]~q ))))) # (\A_SPW_TOP|tx_data|rd_ptr [1] & (((\A_SPW_TOP|tx_data|rd_ptr [2])))) ) ) 
// ) # ( !\A_SPW_TOP|tx_data|mem[39][0]~q  & ( !\A_SPW_TOP|tx_data|mem[35][0]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [1] & ((!\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[33][0]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [2] & ((\A_SPW_TOP|tx_data|mem[37][0]~q 
// ))))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[33][0]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[37][0]~q ),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .datae(!\A_SPW_TOP|tx_data|mem[39][0]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[35][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux17~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux17~6 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux17~6 .lut_mask = 64'h5030503F5F305F3F;
defparam \A_SPW_TOP|tx_data|Mux17~6 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y13_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux17~5 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux17~5_combout  = ( \A_SPW_TOP|tx_data|mem[38][0]~q  & ( \A_SPW_TOP|tx_data|mem[34][0]~q  & ( ((!\A_SPW_TOP|tx_data|rd_ptr [2] & ((\A_SPW_TOP|tx_data|mem[32][0]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[36][0]~q 
// ))) # (\A_SPW_TOP|tx_data|rd_ptr [1]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[38][0]~q  & ( \A_SPW_TOP|tx_data|mem[34][0]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [1] & ((!\A_SPW_TOP|tx_data|rd_ptr [2] & ((\A_SPW_TOP|tx_data|mem[32][0]~q ))) # 
// (\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[36][0]~q )))) # (\A_SPW_TOP|tx_data|rd_ptr [1] & (((!\A_SPW_TOP|tx_data|rd_ptr [2])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[38][0]~q  & ( !\A_SPW_TOP|tx_data|mem[34][0]~q  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [1] & ((!\A_SPW_TOP|tx_data|rd_ptr [2] & ((\A_SPW_TOP|tx_data|mem[32][0]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[36][0]~q )))) # (\A_SPW_TOP|tx_data|rd_ptr [1] & (((\A_SPW_TOP|tx_data|rd_ptr [2])))) ) ) 
// ) # ( !\A_SPW_TOP|tx_data|mem[38][0]~q  & ( !\A_SPW_TOP|tx_data|mem[34][0]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [1] & ((!\A_SPW_TOP|tx_data|rd_ptr [2] & ((\A_SPW_TOP|tx_data|mem[32][0]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [2] & 
// (\A_SPW_TOP|tx_data|mem[36][0]~q )))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[36][0]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[32][0]~q ),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .datae(!\A_SPW_TOP|tx_data|mem[38][0]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[34][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux17~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux17~5 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux17~5 .lut_mask = 64'h3050305F3F503F5F;
defparam \A_SPW_TOP|tx_data|Mux17~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y15_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux17~8 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux17~8_combout  = ( \A_SPW_TOP|tx_data|mem[51][0]~q  & ( \A_SPW_TOP|tx_data|rd_ptr [1] & ( (!\A_SPW_TOP|tx_data|rd_ptr [2]) # (\A_SPW_TOP|tx_data|mem[55][0]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[51][0]~q  & ( \A_SPW_TOP|tx_data|rd_ptr 
// [1] & ( (\A_SPW_TOP|tx_data|mem[55][0]~q  & \A_SPW_TOP|tx_data|rd_ptr [2]) ) ) ) # ( \A_SPW_TOP|tx_data|mem[51][0]~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [1] & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[49][0]~q )) # (\A_SPW_TOP|tx_data|rd_ptr 
// [2] & ((\A_SPW_TOP|tx_data|mem[53][0]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[51][0]~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [1] & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[49][0]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [2] & 
// ((\A_SPW_TOP|tx_data|mem[53][0]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[55][0]~q ),
        .datab(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .datac(!\A_SPW_TOP|tx_data|mem[49][0]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[53][0]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[51][0]~q ),
        .dataf(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux17~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux17~8 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux17~8 .lut_mask = 64'h0C3F0C3F1111DDDD;
defparam \A_SPW_TOP|tx_data|Mux17~8 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y13_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux17~7 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux17~7_combout  = ( \A_SPW_TOP|tx_data|mem[50][0]~q  & ( \A_SPW_TOP|tx_data|mem[52][0]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [1] & (((\A_SPW_TOP|tx_data|rd_ptr [2])) # (\A_SPW_TOP|tx_data|mem[48][0]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [1] 
// & (((!\A_SPW_TOP|tx_data|rd_ptr [2]) # (\A_SPW_TOP|tx_data|mem[54][0]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[50][0]~q  & ( \A_SPW_TOP|tx_data|mem[52][0]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [1] & (((\A_SPW_TOP|tx_data|rd_ptr [2])) # 
// (\A_SPW_TOP|tx_data|mem[48][0]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [1] & (((\A_SPW_TOP|tx_data|mem[54][0]~q  & \A_SPW_TOP|tx_data|rd_ptr [2])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[50][0]~q  & ( !\A_SPW_TOP|tx_data|mem[52][0]~q  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|mem[48][0]~q  & ((!\A_SPW_TOP|tx_data|rd_ptr [2])))) # (\A_SPW_TOP|tx_data|rd_ptr [1] & (((!\A_SPW_TOP|tx_data|rd_ptr [2]) # (\A_SPW_TOP|tx_data|mem[54][0]~q )))) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|mem[50][0]~q  & ( !\A_SPW_TOP|tx_data|mem[52][0]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|mem[48][0]~q  & ((!\A_SPW_TOP|tx_data|rd_ptr [2])))) # (\A_SPW_TOP|tx_data|rd_ptr [1] & (((\A_SPW_TOP|tx_data|mem[54][0]~q  & 
// \A_SPW_TOP|tx_data|rd_ptr [2])))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[48][0]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[54][0]~q ),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .datae(!\A_SPW_TOP|tx_data|mem[50][0]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[52][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux17~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux17~7 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux17~7 .lut_mask = 64'h50035F0350F35FF3;
defparam \A_SPW_TOP|tx_data|Mux17~7 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y13_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux17~9 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux17~9_combout  = ( \A_SPW_TOP|tx_data|rd_ptr [0] & ( \A_SPW_TOP|tx_data|Mux17~7_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & (\A_SPW_TOP|tx_data|Mux17~6_combout )) # (\A_SPW_TOP|tx_data|rd_ptr [4] & 
// ((\A_SPW_TOP|tx_data|Mux17~8_combout ))) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [0] & ( \A_SPW_TOP|tx_data|Mux17~7_combout  & ( (\A_SPW_TOP|tx_data|Mux17~5_combout ) # (\A_SPW_TOP|tx_data|rd_ptr [4]) ) ) ) # ( \A_SPW_TOP|tx_data|rd_ptr [0] & ( 
// !\A_SPW_TOP|tx_data|Mux17~7_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & (\A_SPW_TOP|tx_data|Mux17~6_combout )) # (\A_SPW_TOP|tx_data|rd_ptr [4] & ((\A_SPW_TOP|tx_data|Mux17~8_combout ))) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [0] & ( 
// !\A_SPW_TOP|tx_data|Mux17~7_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & \A_SPW_TOP|tx_data|Mux17~5_combout ) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .datab(!\A_SPW_TOP|tx_data|Mux17~6_combout ),
        .datac(!\A_SPW_TOP|tx_data|Mux17~5_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux17~8_combout ),
        .datae(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .dataf(!\A_SPW_TOP|tx_data|Mux17~7_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux17~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux17~9 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux17~9 .lut_mask = 64'h0A0A22775F5F2277;
defparam \A_SPW_TOP|tx_data|Mux17~9 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y13_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux17~20 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux17~20_combout  = ( \A_SPW_TOP|tx_data|Mux17~9_combout  & ( \A_SPW_TOP|tx_data|rd_ptr [3] & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|Mux17~14_combout )) # (\A_SPW_TOP|tx_data|rd_ptr [5] & 
// ((\A_SPW_TOP|tx_data|Mux17~19_combout ))) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux17~9_combout  & ( \A_SPW_TOP|tx_data|rd_ptr [3] & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|Mux17~14_combout )) # (\A_SPW_TOP|tx_data|rd_ptr [5] & 
// ((\A_SPW_TOP|tx_data|Mux17~19_combout ))) ) ) ) # ( \A_SPW_TOP|tx_data|Mux17~9_combout  & ( !\A_SPW_TOP|tx_data|rd_ptr [3] & ( (\A_SPW_TOP|tx_data|rd_ptr [5]) # (\A_SPW_TOP|tx_data|Mux17~4_combout ) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux17~9_combout  & ( 
// !\A_SPW_TOP|tx_data|rd_ptr [3] & ( (\A_SPW_TOP|tx_data|Mux17~4_combout  & !\A_SPW_TOP|tx_data|rd_ptr [5]) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux17~4_combout ),
        .datab(!\A_SPW_TOP|tx_data|Mux17~14_combout ),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [5]),
        .datad(!\A_SPW_TOP|tx_data|Mux17~19_combout ),
        .datae(!\A_SPW_TOP|tx_data|Mux17~9_combout ),
        .dataf(!\A_SPW_TOP|tx_data|rd_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux17~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux17~20 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux17~20 .lut_mask = 64'h50505F5F303F303F;
defparam \A_SPW_TOP|tx_data|Mux17~20 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y11_N59
dffeas \A_SPW_TOP|tx_data|data_out[0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Mux17~20_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|data_out [0]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|data_out[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|data_out[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X56_Y7_N21
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector31~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector31~0_combout  = ( \A_SPW_TOP|SPW|TX|tx_data_in [0] & ( (!\A_SPW_TOP|SPW|TX|Selector30~0_combout ) # ((!\A_SPW_TOP|SPW|TX|Selector30~2_combout  & ((\A_SPW_TOP|SPW|TX|Equal0~6_combout ) # (\A_SPW_TOP|tx_data|data_out [0])))) ) ) # 
// ( !\A_SPW_TOP|SPW|TX|tx_data_in [0] & ( (\A_SPW_TOP|tx_data|data_out [0] & (!\A_SPW_TOP|SPW|TX|Selector30~2_combout  & !\A_SPW_TOP|SPW|TX|Equal0~6_combout )) ) )

        .dataa(!\A_SPW_TOP|tx_data|data_out [0]),
        .datab(!\A_SPW_TOP|SPW|TX|Selector30~2_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|Equal0~6_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|Selector30~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|tx_data_in [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector31~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector31~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector31~0 .lut_mask = 64'h40404040FF4CFF4C;
defparam \A_SPW_TOP|SPW|TX|Selector31~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X56_Y7_N53
dffeas \A_SPW_TOP|SPW|TX|tx_data_in[0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|Selector31~0_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|tx_data_in [0]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_data_in[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|tx_data_in[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X59_Y7_N24
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|last_type~12 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|last_type~12_combout  = ( !\A_SPW_TOP|SPW|TX|tx_data_in [1] & ( (((!\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & \A_SPW_TOP|SPW|TX|global_counter_transfer [1])) # (\A_SPW_TOP|SPW|TX|global_counter_transfer [2])) # 
// (\A_SPW_TOP|SPW|TX|global_counter_transfer [3]) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
        .datab(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
        .datac(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
        .datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|tx_data_in [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|last_type~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_type~12 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|last_type~12 .lut_mask = 64'h5DFF5DFF00000000;
defparam \A_SPW_TOP|SPW|TX|last_type~12 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X56_Y7_N3
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector68~1 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector68~1_combout  = ( \A_SPW_TOP|SPW|TX|tx_data_in [8] & ( (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q  & ((!\A_SPW_TOP|SPW|TX|last_type~12_combout  & ((\A_SPW_TOP|SPW|TX|last_type.EOP~q ))) # (\A_SPW_TOP|SPW|TX|last_type~12_combout  
// & (!\A_SPW_TOP|SPW|TX|tx_data_in [0])))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|tx_data_in [0]),
        .datab(!\A_SPW_TOP|SPW|TX|last_type~12_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|last_type.EOP~q ),
        .datad(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|tx_data_in [8]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector68~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector68~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector68~1 .lut_mask = 64'h00000000002E002E;
defparam \A_SPW_TOP|SPW|TX|Selector68~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X56_Y7_N57
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector40~1 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector40~1_combout  = ( \A_SPW_TOP|SPW|TX|tx_data_in_0 [0] & ( (!\A_SPW_TOP|SPW|TX|Selector40~0_combout ) # ((\A_SPW_TOP|tx_data|data_out [0] & \A_SPW_TOP|SPW|TX|Selector32~0_combout )) ) ) # ( !\A_SPW_TOP|SPW|TX|tx_data_in_0 [0] & ( 
// (\A_SPW_TOP|tx_data|data_out [0] & \A_SPW_TOP|SPW|TX|Selector32~0_combout ) ) )

        .dataa(!\A_SPW_TOP|tx_data|data_out [0]),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|TX|Selector32~0_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|Selector40~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|tx_data_in_0 [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector40~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector40~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector40~1 .lut_mask = 64'h05050505FF05FF05;
defparam \A_SPW_TOP|SPW|TX|Selector40~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X56_Y7_N35
dffeas \A_SPW_TOP|SPW|TX|tx_data_in_0[0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|Selector40~1_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|tx_data_in_0 [0]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_data_in_0[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|tx_data_in_0[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X51_Y7_N54
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|last_type~13 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|last_type~13_combout  = ( \A_SPW_TOP|SPW|TX|global_counter_transfer [0] & ( (!\A_SPW_TOP|SPW|TX|tx_data_in_0 [1] & ((\A_SPW_TOP|SPW|TX|global_counter_transfer [2]) # (\A_SPW_TOP|SPW|TX|global_counter_transfer [3]))) ) ) # ( 
// !\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & ( (!\A_SPW_TOP|SPW|TX|tx_data_in_0 [1] & (((\A_SPW_TOP|SPW|TX|global_counter_transfer [2]) # (\A_SPW_TOP|SPW|TX|global_counter_transfer [1])) # (\A_SPW_TOP|SPW|TX|global_counter_transfer [3]))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
        .datab(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
        .datac(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
        .datad(!\A_SPW_TOP|SPW|TX|tx_data_in_0 [1]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|last_type~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_type~13 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|last_type~13 .lut_mask = 64'h7F007F005F005F00;
defparam \A_SPW_TOP|SPW|TX|last_type~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X56_Y7_N9
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector68~2 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector68~2_combout  = ( \A_SPW_TOP|SPW|TX|last_type.EOP~q  & ( (\A_SPW_TOP|SPW|TX|tx_data_in_0 [8] & (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q  & ((!\A_SPW_TOP|SPW|TX|tx_data_in_0 [0]) # (!\A_SPW_TOP|SPW|TX|last_type~13_combout 
// )))) ) ) # ( !\A_SPW_TOP|SPW|TX|last_type.EOP~q  & ( (!\A_SPW_TOP|SPW|TX|tx_data_in_0 [0] & (\A_SPW_TOP|SPW|TX|last_type~13_combout  & (\A_SPW_TOP|SPW|TX|tx_data_in_0 [8] & \A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q ))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|tx_data_in_0 [0]),
        .datab(!\A_SPW_TOP|SPW|TX|last_type~13_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|tx_data_in_0 [8]),
        .datad(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|last_type.EOP~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector68~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector68~2 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector68~2 .lut_mask = 64'h00020002000E000E;
defparam \A_SPW_TOP|SPW|TX|Selector68~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X56_Y7_N42
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|last_type~17 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|last_type~17_combout  = ( \A_SPW_TOP|SPW|TX|Selector68~1_combout  & ( \A_SPW_TOP|SPW|TX|Selector68~2_combout  & ( \A_SPW_TOP|SPW|TX|last_type.NULL~0_combout  ) ) ) # ( !\A_SPW_TOP|SPW|TX|Selector68~1_combout  & ( 
// \A_SPW_TOP|SPW|TX|Selector68~2_combout  & ( \A_SPW_TOP|SPW|TX|last_type.NULL~0_combout  ) ) ) # ( \A_SPW_TOP|SPW|TX|Selector68~1_combout  & ( !\A_SPW_TOP|SPW|TX|Selector68~2_combout  & ( \A_SPW_TOP|SPW|TX|last_type.NULL~0_combout  ) ) ) # ( 
// !\A_SPW_TOP|SPW|TX|Selector68~1_combout  & ( !\A_SPW_TOP|SPW|TX|Selector68~2_combout  & ( (\A_SPW_TOP|SPW|TX|last_type.EOP~q  & (\A_SPW_TOP|SPW|TX|last_type.NULL~0_combout  & ((!\A_SPW_TOP|SPW|TX|Selector71~0_combout ) # 
// (!\A_SPW_TOP|SPW|TX|Selector68~0_combout )))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|Selector71~0_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|last_type.EOP~q ),
        .datac(!\A_SPW_TOP|SPW|TX|Selector68~0_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|last_type.NULL~0_combout ),
        .datae(!\A_SPW_TOP|SPW|TX|Selector68~1_combout ),
        .dataf(!\A_SPW_TOP|SPW|TX|Selector68~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|last_type~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_type~17 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|last_type~17 .lut_mask = 64'h003200FF00FF00FF;
defparam \A_SPW_TOP|SPW|TX|last_type~17 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X56_Y7_N17
dffeas \A_SPW_TOP|SPW|TX|last_type.EOP (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|last_type~17_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|last_type.EOP~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_type.EOP .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|last_type.EOP .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X58_Y7_N21
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector70~1 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector70~1_combout  = ( \A_SPW_TOP|SPW|TX|last_type~13_combout  & ( (!\A_SPW_TOP|SPW|TX|tx_data_in_0 [8] & \A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q ) ) ) # ( !\A_SPW_TOP|SPW|TX|last_type~13_combout  & ( 
// \A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|TX|tx_data_in_0 [8]),
        .datad(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|last_type~13_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector70~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector70~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector70~1 .lut_mask = 64'h00FF00FF00F000F0;
defparam \A_SPW_TOP|SPW|TX|Selector70~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X56_Y7_N18
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector70~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector70~0_combout  = ( \A_SPW_TOP|SPW|TX|tx_data_in [8] & ( (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q  & !\A_SPW_TOP|SPW|TX|last_type~12_combout ) ) ) # ( !\A_SPW_TOP|SPW|TX|tx_data_in [8] & ( 
// \A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q ),
        .datad(!\A_SPW_TOP|SPW|TX|last_type~12_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|tx_data_in [8]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector70~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector70~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector70~0 .lut_mask = 64'h0F0F0F0F0F000F00;
defparam \A_SPW_TOP|SPW|TX|Selector70~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X59_Y7_N0
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|last_type~14 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|last_type~14_combout  = ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct_c~q  & ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c~q  & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & ((!\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & 
// ((!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]))) # (\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & (\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & \A_SPW_TOP|SPW|TX|global_counter_transfer [2])))) ) ) ) # ( !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct_c~q  
// & ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c~q  & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & ((!\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & ((!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]))) # (\A_SPW_TOP|SPW|TX|global_counter_transfer 
// [3] & (\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & \A_SPW_TOP|SPW|TX|global_counter_transfer [2])))) ) ) ) # ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct_c~q  & ( !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c~q  & ( 
// (!\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & (!\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & !\A_SPW_TOP|SPW|TX|global_counter_transfer [2])) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
        .datab(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
        .datac(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
        .datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
        .datae(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct_c~q ),
        .dataf(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|last_type~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_type~14 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|last_type~14 .lut_mask = 64'h0000A000A010A010;
defparam \A_SPW_TOP|SPW|TX|last_type~14 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X59_Y7_N45
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector70~2 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector70~2_combout  = ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~q  & ( (!\A_SPW_TOP|SPW|TX|last_type~14_combout  & (!\A_SPW_TOP|SPW|TX|Selector67~0_combout  & ((!\A_SPW_TOP|SPW|TX|Equal0~4_combout ) # 
// (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~1_combout )))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|last_type~14_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|Selector67~0_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|Equal0~4_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~1_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector70~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector70~2 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector70~2 .lut_mask = 64'h0000000080888088;
defparam \A_SPW_TOP|SPW|TX|Selector70~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X59_Y7_N42
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector70~3 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector70~3_combout  = ( \A_SPW_TOP|SPW|TX|Selector63~0_combout  & ( !\A_SPW_TOP|SPW|TX|last_type~15_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|TX|last_type~15_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|Selector63~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector70~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector70~3 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector70~3 .lut_mask = 64'h00000000F0F0F0F0;
defparam \A_SPW_TOP|SPW|TX|Selector70~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X58_Y7_N0
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|last_type~16 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|last_type~16_combout  = ( \A_SPW_TOP|SPW|TX|last_type.DATA~q  & ( \A_SPW_TOP|SPW|TX|last_type.NULL~0_combout  & ( (((!\A_SPW_TOP|SPW|TX|Selector70~2_combout ) # (\A_SPW_TOP|SPW|TX|Selector70~3_combout )) # 
// (\A_SPW_TOP|SPW|TX|Selector70~0_combout )) # (\A_SPW_TOP|SPW|TX|Selector70~1_combout ) ) ) ) # ( !\A_SPW_TOP|SPW|TX|last_type.DATA~q  & ( \A_SPW_TOP|SPW|TX|last_type.NULL~0_combout  & ( \A_SPW_TOP|SPW|TX|Selector70~3_combout  ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|Selector70~1_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|Selector70~0_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|Selector70~2_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|Selector70~3_combout ),
        .datae(!\A_SPW_TOP|SPW|TX|last_type.DATA~q ),
        .dataf(!\A_SPW_TOP|SPW|TX|last_type.NULL~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|last_type~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_type~16 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|last_type~16 .lut_mask = 64'h0000000000FFF7FF;
defparam \A_SPW_TOP|SPW|TX|last_type~16 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X58_Y7_N5
dffeas \A_SPW_TOP|SPW|TX|last_type.DATA (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|last_type~16_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|last_type.DATA~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_type.DATA .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|last_type.DATA .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X56_Y7_N6
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector69~2 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector69~2_combout  = ( \A_SPW_TOP|SPW|TX|last_type.EEP~q  & ( (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q  & (\A_SPW_TOP|SPW|TX|tx_data_in_0 [8] & ((!\A_SPW_TOP|SPW|TX|last_type~13_combout ) # (\A_SPW_TOP|SPW|TX|tx_data_in_0 [0])))) 
// ) ) # ( !\A_SPW_TOP|SPW|TX|last_type.EEP~q  & ( (\A_SPW_TOP|SPW|TX|tx_data_in_0 [0] & (\A_SPW_TOP|SPW|TX|last_type~13_combout  & (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q  & \A_SPW_TOP|SPW|TX|tx_data_in_0 [8]))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|tx_data_in_0 [0]),
        .datab(!\A_SPW_TOP|SPW|TX|last_type~13_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q ),
        .datad(!\A_SPW_TOP|SPW|TX|tx_data_in_0 [8]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|last_type.EEP~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector69~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector69~2 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector69~2 .lut_mask = 64'h00010001000D000D;
defparam \A_SPW_TOP|SPW|TX|Selector69~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X58_Y6_N30
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector69~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector69~0_combout  = ( \A_SPW_TOP|SPW|TX|Equal0~4_combout  & ( (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct~q ) # (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct_c~q ) ) ) # ( !\A_SPW_TOP|SPW|TX|Equal0~4_combout  & ( 
// (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct_c~q  & !\A_SPW_TOP|SPW|TX|LessThan5~0_combout ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct_c~q ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|TX|LessThan5~0_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|Equal0~4_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector69~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector69~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector69~0 .lut_mask = 64'h5050505055FF55FF;
defparam \A_SPW_TOP|SPW|TX|Selector69~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X56_Y7_N0
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector69~1 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector69~1_combout  = ( \A_SPW_TOP|SPW|TX|last_type.EEP~q  & ( (\A_SPW_TOP|SPW|TX|tx_data_in [8] & (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q  & ((!\A_SPW_TOP|SPW|TX|last_type~12_combout ) # (\A_SPW_TOP|SPW|TX|tx_data_in [0])))) ) ) # 
// ( !\A_SPW_TOP|SPW|TX|last_type.EEP~q  & ( (\A_SPW_TOP|SPW|TX|tx_data_in [0] & (\A_SPW_TOP|SPW|TX|last_type~12_combout  & (\A_SPW_TOP|SPW|TX|tx_data_in [8] & \A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q ))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|tx_data_in [0]),
        .datab(!\A_SPW_TOP|SPW|TX|last_type~12_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|tx_data_in [8]),
        .datad(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|last_type.EEP~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector69~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector69~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector69~1 .lut_mask = 64'h00010001000D000D;
defparam \A_SPW_TOP|SPW|TX|Selector69~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X56_Y7_N36
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|last_type~18 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|last_type~18_combout  = ( \A_SPW_TOP|SPW|TX|Selector69~1_combout  & ( \A_SPW_TOP|SPW|TX|last_type.EEP~q  & ( \A_SPW_TOP|SPW|TX|last_type.NULL~0_combout  ) ) ) # ( !\A_SPW_TOP|SPW|TX|Selector69~1_combout  & ( 
// \A_SPW_TOP|SPW|TX|last_type.EEP~q  & ( (\A_SPW_TOP|SPW|TX|last_type.NULL~0_combout  & ((!\A_SPW_TOP|SPW|TX|Selector68~0_combout ) # ((\A_SPW_TOP|SPW|TX|Selector69~0_combout ) # (\A_SPW_TOP|SPW|TX|Selector69~2_combout )))) ) ) ) # ( 
// \A_SPW_TOP|SPW|TX|Selector69~1_combout  & ( !\A_SPW_TOP|SPW|TX|last_type.EEP~q  & ( \A_SPW_TOP|SPW|TX|last_type.NULL~0_combout  ) ) ) # ( !\A_SPW_TOP|SPW|TX|Selector69~1_combout  & ( !\A_SPW_TOP|SPW|TX|last_type.EEP~q  & ( 
// (\A_SPW_TOP|SPW|TX|Selector69~2_combout  & \A_SPW_TOP|SPW|TX|last_type.NULL~0_combout ) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|Selector68~0_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|Selector69~2_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|Selector69~0_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|last_type.NULL~0_combout ),
        .datae(!\A_SPW_TOP|SPW|TX|Selector69~1_combout ),
        .dataf(!\A_SPW_TOP|SPW|TX|last_type.EEP~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|last_type~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_type~18 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|last_type~18 .lut_mask = 64'h003300FF00BF00FF;
defparam \A_SPW_TOP|SPW|TX|last_type~18 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X56_Y7_N41
dffeas \A_SPW_TOP|SPW|TX|last_type.EEP (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|last_type~18_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|last_type.EEP~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_type.EEP .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|last_type.EEP .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X58_Y7_N54
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|last_type~24 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|last_type~24_combout  = ( !\A_SPW_TOP|SPW|TX|last_type.TIMEC~q  & ( (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c~q  & (\A_SPW_TOP|SPW|TX|last_type.NULL~0_combout  & (!\A_SPW_TOP|SPW|TX|Equal0~3_combout  & 
// (\A_SPW_TOP|SPW|TX|LessThan5~0_combout )))) ) ) # ( \A_SPW_TOP|SPW|TX|last_type.TIMEC~q  & ( (\A_SPW_TOP|SPW|TX|last_type.NULL~0_combout  & (((!\A_SPW_TOP|SPW|TX|Selector67~1_combout ) # ((!\A_SPW_TOP|SPW|TX|Selector71~0_combout ))) # 
// (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c~q ))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c~q ),
        .datab(!\A_SPW_TOP|SPW|TX|last_type.NULL~0_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|Selector67~1_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|LessThan5~0_combout ),
        .datae(!\A_SPW_TOP|SPW|TX|last_type.TIMEC~q ),
        .dataf(!\A_SPW_TOP|SPW|TX|Selector71~0_combout ),
        .datag(!\A_SPW_TOP|SPW|TX|Equal0~3_combout ),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|last_type~24_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_type~24 .extended_lut = "on";
defparam \A_SPW_TOP|SPW|TX|last_type~24 .lut_mask = 64'h0010333300103131;
defparam \A_SPW_TOP|SPW|TX|last_type~24 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X58_Y7_N56
dffeas \A_SPW_TOP|SPW|TX|last_type.TIMEC (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(\A_SPW_TOP|SPW|TX|last_type~24_combout ),
        .asdata(vcc),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|last_type.TIMEC~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_type.TIMEC .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|last_type.TIMEC .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X59_Y7_N6
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|last_type~19 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|last_type~19_combout  = ( \A_SPW_TOP|SPW|TX|last_type~10_combout  & ( (!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q  & (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~q  & ((!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q ) # 
// (!\A_SPW_TOP|SPW|TX|last_type~11_combout )))) ) ) # ( !\A_SPW_TOP|SPW|TX|last_type~10_combout  & ( (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~q  & ((!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q ) # (!\A_SPW_TOP|SPW|TX|last_type~11_combout ))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q ),
        .datab(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q ),
        .datac(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~q ),
        .datad(!\A_SPW_TOP|SPW|TX|last_type~11_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|last_type~10_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|last_type~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_type~19 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|last_type~19 .lut_mask = 64'h0F0A0F0A0C080C08;
defparam \A_SPW_TOP|SPW|TX|last_type~19 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X59_Y7_N51
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|last_type~21 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|last_type~21_combout  = ( \A_SPW_TOP|SPW|TX|Equal0~1_combout  & ( \A_SPW_TOP|SPW|TX|last_type.NULL~0_combout  ) ) # ( !\A_SPW_TOP|SPW|TX|Equal0~1_combout  & ( (\A_SPW_TOP|SPW|TX|last_type.NULL~0_combout  & 
// ((!\A_SPW_TOP|SPW|TX|LessThan5~0_combout ) # (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~0_combout ))) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~0_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|LessThan5~0_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|last_type.NULL~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|Equal0~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|last_type~21_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_type~21 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|last_type~21 .lut_mask = 64'h00F300F300FF00FF;
defparam \A_SPW_TOP|SPW|TX|last_type~21 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X59_Y7_N15
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|last_type~20 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|last_type~20_combout  = ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~0_combout  & ( (!\A_SPW_TOP|SPW|TX|last_type~14_combout  & ((!\A_SPW_TOP|SPW|TX|Equal0~4_combout ) # (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~1_combout ))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|last_type~14_combout ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|TX|Equal0~4_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~1_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|last_type~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_type~20 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|last_type~20 .lut_mask = 64'h00000000A0AAA0AA;
defparam \A_SPW_TOP|SPW|TX|last_type~20 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X59_Y7_N12
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|last_type~22 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|last_type~22_combout  = ( \A_SPW_TOP|SPW|TX|last_type~20_combout  & ( (\A_SPW_TOP|SPW|TX|last_type~21_combout  & ((\A_SPW_TOP|SPW|TX|last_type.NULL~q ) # (\A_SPW_TOP|SPW|TX|last_type~19_combout ))) ) ) # ( 
// !\A_SPW_TOP|SPW|TX|last_type~20_combout  & ( (\A_SPW_TOP|SPW|TX|last_type.NULL~q  & \A_SPW_TOP|SPW|TX|last_type~21_combout ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|SPW|TX|last_type~19_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|last_type.NULL~q ),
        .datad(!\A_SPW_TOP|SPW|TX|last_type~21_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|last_type~20_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|last_type~22_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_type~22 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|last_type~22 .lut_mask = 64'h000F000F003F003F;
defparam \A_SPW_TOP|SPW|TX|last_type~22 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X56_Y7_N32
dffeas \A_SPW_TOP|SPW|TX|last_type.NULL (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|last_type~22_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|last_type.NULL~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_type.NULL .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|last_type.NULL .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X58_Y7_N12
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|last_type.NULL~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|last_type.NULL~0_combout  = ( \A_SPW_TOP|SPW|TX|last_type.TIMEC~q  & ( \A_SPW_TOP|SPW|TX|last_type.NULL~q  & ( (!\A_SPW_TOP|SPW|TX|last_type.EOP~q  & (!\A_SPW_TOP|SPW|TX|last_type.FCT~q  & (!\A_SPW_TOP|SPW|TX|last_type.DATA~q  & 
// !\A_SPW_TOP|SPW|TX|last_type.EEP~q ))) ) ) ) # ( !\A_SPW_TOP|SPW|TX|last_type.TIMEC~q  & ( \A_SPW_TOP|SPW|TX|last_type.NULL~q  & ( (!\A_SPW_TOP|SPW|TX|last_type.EOP~q  & ((!\A_SPW_TOP|SPW|TX|last_type.FCT~q  & (!\A_SPW_TOP|SPW|TX|last_type.DATA~q  $ 
// (!\A_SPW_TOP|SPW|TX|last_type.EEP~q ))) # (\A_SPW_TOP|SPW|TX|last_type.FCT~q  & (!\A_SPW_TOP|SPW|TX|last_type.DATA~q  & !\A_SPW_TOP|SPW|TX|last_type.EEP~q )))) # (\A_SPW_TOP|SPW|TX|last_type.EOP~q  & (!\A_SPW_TOP|SPW|TX|last_type.FCT~q  & 
// (!\A_SPW_TOP|SPW|TX|last_type.DATA~q  & !\A_SPW_TOP|SPW|TX|last_type.EEP~q ))) ) ) ) # ( !\A_SPW_TOP|SPW|TX|last_type.TIMEC~q  & ( !\A_SPW_TOP|SPW|TX|last_type.NULL~q  & ( (!\A_SPW_TOP|SPW|TX|last_type.EOP~q  & (!\A_SPW_TOP|SPW|TX|last_type.FCT~q  & 
// (!\A_SPW_TOP|SPW|TX|last_type.DATA~q  & !\A_SPW_TOP|SPW|TX|last_type.EEP~q ))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|last_type.EOP~q ),
        .datab(!\A_SPW_TOP|SPW|TX|last_type.FCT~q ),
        .datac(!\A_SPW_TOP|SPW|TX|last_type.DATA~q ),
        .datad(!\A_SPW_TOP|SPW|TX|last_type.EEP~q ),
        .datae(!\A_SPW_TOP|SPW|TX|last_type.TIMEC~q ),
        .dataf(!\A_SPW_TOP|SPW|TX|last_type.NULL~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|last_type.NULL~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_type.NULL~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|last_type.NULL~0 .lut_mask = 64'h8000000068808000;
defparam \A_SPW_TOP|SPW|TX|last_type.NULL~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X58_Y7_N36
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|last_type~23 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|last_type~23_combout  = ( \A_SPW_TOP|SPW|TX|Selector67~2_combout  & ( \A_SPW_TOP|SPW|TX|last_type.NULL~0_combout  & ( (\A_SPW_TOP|SPW|TX|Selector67~3_combout ) # (\A_SPW_TOP|SPW|TX|last_type.FCT~q ) ) ) ) # ( 
// !\A_SPW_TOP|SPW|TX|Selector67~2_combout  & ( \A_SPW_TOP|SPW|TX|last_type.NULL~0_combout  & ( ((\A_SPW_TOP|SPW|TX|last_type.FCT~q  & ((!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~1_combout ) # (!\A_SPW_TOP|SPW|TX|Selector67~1_combout )))) # 
// (\A_SPW_TOP|SPW|TX|Selector67~3_combout ) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~1_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|last_type.FCT~q ),
        .datac(!\A_SPW_TOP|SPW|TX|Selector67~1_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|Selector67~3_combout ),
        .datae(!\A_SPW_TOP|SPW|TX|Selector67~2_combout ),
        .dataf(!\A_SPW_TOP|SPW|TX|last_type.NULL~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|last_type~23_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_type~23 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|last_type~23 .lut_mask = 64'h0000000032FF33FF;
defparam \A_SPW_TOP|SPW|TX|last_type~23 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X58_Y7_N11
dffeas \A_SPW_TOP|SPW|TX|last_type.FCT (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|last_type~23_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|last_type.FCT~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_type.FCT .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|last_type.FCT .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X58_Y7_N51
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|always0~11 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|always0~11_combout  = ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & (!\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & (\A_SPW_TOP|SPW|TX|last_type.FCT~q  & 
// !\A_SPW_TOP|SPW|TX|global_counter_transfer [0]))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
        .datab(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
        .datac(!\A_SPW_TOP|SPW|TX|last_type.FCT~q ),
        .datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|always0~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|always0~11 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|always0~11 .lut_mask = 64'h0800080000000000;
defparam \A_SPW_TOP|SPW|TX|always0~11 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X59_Y7_N21
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|always0~10 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|always0~10_combout  = ( !\A_SPW_TOP|SPW|TX|last_type.NULL~q  & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & (!\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & (!\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & 
// !\A_SPW_TOP|SPW|TX|global_counter_transfer [1]))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
        .datab(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
        .datac(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
        .datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|last_type.NULL~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|always0~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|always0~10 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|always0~10 .lut_mask = 64'h8000800000000000;
defparam \A_SPW_TOP|SPW|TX|always0~10 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X58_Y7_N24
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|always0~7 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|always0~7_combout  = ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & (!\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & (\A_SPW_TOP|SPW|TX|last_type.DATA~q  & 
// !\A_SPW_TOP|SPW|TX|global_counter_transfer [2]))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
        .datab(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
        .datac(!\A_SPW_TOP|SPW|TX|last_type.DATA~q ),
        .datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|always0~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|always0~7 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|always0~7 .lut_mask = 64'h0800080000000000;
defparam \A_SPW_TOP|SPW|TX|always0~7 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X58_Y7_N48
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|always0~6 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|always0~6_combout  = ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & (!\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & (\A_SPW_TOP|SPW|TX|last_type.TIMEC~q  & 
// !\A_SPW_TOP|SPW|TX|global_counter_transfer [0]))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
        .datab(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
        .datac(!\A_SPW_TOP|SPW|TX|last_type.TIMEC~q ),
        .datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|always0~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|always0~6 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|always0~6 .lut_mask = 64'h0800080000000000;
defparam \A_SPW_TOP|SPW|TX|always0~6 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X51_Y7_N51
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|always0~8 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|always0~8_combout  = ( !\A_SPW_TOP|SPW|TX|tx_data_in_0 [0] & ( (!\A_SPW_TOP|SPW|TX|tx_data_in_0 [1] & \A_SPW_TOP|SPW|TX|tx_data_in_0 [8]) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|SPW|TX|tx_data_in_0 [1]),
        .datac(!\A_SPW_TOP|SPW|TX|tx_data_in_0 [8]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|tx_data_in_0 [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|always0~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|always0~8 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|always0~8 .lut_mask = 64'h0C0C0C0C00000000;
defparam \A_SPW_TOP|SPW|TX|always0~8 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X51_Y7_N33
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|always0~9 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|always0~9_combout  = ( \A_SPW_TOP|SPW|TX|tx_data_in_0 [0] & ( (\A_SPW_TOP|SPW|TX|tx_data_in_0 [8] & !\A_SPW_TOP|SPW|TX|tx_data_in_0 [1]) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|SPW|TX|tx_data_in_0 [8]),
        .datac(!\A_SPW_TOP|SPW|TX|tx_data_in_0 [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|tx_data_in_0 [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|always0~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|always0~9 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|always0~9 .lut_mask = 64'h0000000030303030;
defparam \A_SPW_TOP|SPW|TX|always0~9 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X55_Y7_N48
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout~23 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout~23_combout  = ( \A_SPW_TOP|SPW|TX|always0~8_combout  & ( \A_SPW_TOP|SPW|TX|always0~9_combout  & ( (!\A_SPW_TOP|SPW|TX|always0~11_combout  & (!\A_SPW_TOP|SPW|TX|always0~10_combout  & (!\A_SPW_TOP|SPW|TX|always0~7_combout  & 
// !\A_SPW_TOP|SPW|TX|always0~6_combout ))) ) ) ) # ( !\A_SPW_TOP|SPW|TX|always0~8_combout  & ( \A_SPW_TOP|SPW|TX|always0~9_combout  & ( (!\A_SPW_TOP|SPW|TX|always0~11_combout  & !\A_SPW_TOP|SPW|TX|always0~10_combout ) ) ) ) # ( 
// \A_SPW_TOP|SPW|TX|always0~8_combout  & ( !\A_SPW_TOP|SPW|TX|always0~9_combout  & ( (!\A_SPW_TOP|SPW|TX|always0~7_combout  & !\A_SPW_TOP|SPW|TX|always0~6_combout ) ) ) ) # ( !\A_SPW_TOP|SPW|TX|always0~8_combout  & ( !\A_SPW_TOP|SPW|TX|always0~9_combout  ) 
// )

        .dataa(!\A_SPW_TOP|SPW|TX|always0~11_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|always0~10_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|always0~7_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|always0~6_combout ),
        .datae(!\A_SPW_TOP|SPW|TX|always0~8_combout ),
        .dataf(!\A_SPW_TOP|SPW|TX|always0~9_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|tx_dout~23_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout~23 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout~23 .lut_mask = 64'hFFFFF00088888000;
defparam \A_SPW_TOP|SPW|TX|tx_dout~23 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X51_Y7_N12
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Equal0~2 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Equal0~2_combout  = ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & (!\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & \A_SPW_TOP|SPW|TX|global_counter_transfer [0])) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
        .datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Equal0~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Equal0~2 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Equal0~2 .lut_mask = 64'h00A000A000000000;
defparam \A_SPW_TOP|SPW|TX|Equal0~2 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X55_Y7_N45
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout~21 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout~21_combout  = ( \A_SPW_TOP|SPW|TX|always0~9_combout  & ( (!\A_SPW_TOP|SPW|TX|always0~7_combout  & (!\A_SPW_TOP|SPW|TX|always0~6_combout  & ((!\A_SPW_TOP|SPW|TX|Equal0~2_combout ) # (\A_SPW_TOP|SPW|TX|tx_data_in_0 [8])))) ) ) # ( 
// !\A_SPW_TOP|SPW|TX|always0~9_combout  & ( (!\A_SPW_TOP|SPW|TX|Equal0~2_combout ) # (\A_SPW_TOP|SPW|TX|tx_data_in_0 [8]) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|always0~7_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|Equal0~2_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|tx_data_in_0 [8]),
        .datad(!\A_SPW_TOP|SPW|TX|always0~6_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|always0~9_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|tx_dout~21_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout~21 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout~21 .lut_mask = 64'hCFCFCFCF8A008A00;
defparam \A_SPW_TOP|SPW|TX|tx_dout~21 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X51_Y7_N6
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout~16 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout~16_combout  = ( \A_SPW_TOP|SPW|TX|global_counter_transfer [0] & ( (!\A_SPW_TOP|SPW|TX|tx_data_in_0 [8] & ((!\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & (\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & 
// !\A_SPW_TOP|SPW|TX|global_counter_transfer [2])) # (\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & (!\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & \A_SPW_TOP|SPW|TX|global_counter_transfer [2])))) ) ) # ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [0] 
// & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & (!\A_SPW_TOP|SPW|TX|tx_data_in_0 [8] & (\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & !\A_SPW_TOP|SPW|TX|global_counter_transfer [2]))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
        .datab(!\A_SPW_TOP|SPW|TX|tx_data_in_0 [8]),
        .datac(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
        .datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|tx_dout~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout~16 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout~16 .lut_mask = 64'h0800080008400840;
defparam \A_SPW_TOP|SPW|TX|tx_dout~16 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y17_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_payload~2 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_payload~2_combout  = ( \u0|hps_0|fpga_interfaces|h2f_WDATA [2] & ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_WDATA [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_010|src_payload~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_payload~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_payload~2 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_payload~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y17_N52
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_010|src_payload~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[2] .power_up = "low";
// synopsys translate_on

// Location: FF_X30_Y14_N53
dffeas \u0|write_data_fifo_tx|data_out[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [2]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|write_data_fifo_tx|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|write_data_fifo_tx|data_out [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|write_data_fifo_tx|data_out[2] .is_wysiwyg = "true";
defparam \u0|write_data_fifo_tx|data_out[2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y10_N57
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector479~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector479~0_combout  = ( \A_SPW_TOP|tx_data|mem[52][2]~q  & ( (!\A_SPW_TOP|tx_data|Selector473~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux6~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [2])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[52][2]~q  & ( (\A_SPW_TOP|tx_data|Selector473~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux6~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [2]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector473~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [2]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[52][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector479~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector479~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector479~0 .lut_mask = 64'h04070407F4F7F4F7;
defparam \A_SPW_TOP|tx_data|Selector479~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y10_N35
dffeas \A_SPW_TOP|tx_data|mem[52][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector479~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[52][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[52][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[52][2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y10_N21
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector263~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector263~0_combout  = ( \A_SPW_TOP|tx_data|mem[28][2]~q  & ( (!\A_SPW_TOP|tx_data|Selector257~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux6~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [2])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[28][2]~q  & ( (\A_SPW_TOP|tx_data|Selector257~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux6~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [2]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector257~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [2]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[28][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector263~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector263~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector263~0 .lut_mask = 64'h04070407F4F7F4F7;
defparam \A_SPW_TOP|tx_data|Selector263~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y10_N53
dffeas \A_SPW_TOP|tx_data|mem[28][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector263~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[28][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[28][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[28][2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y10_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector551~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector551~0_combout  = ( \A_SPW_TOP|tx_data|Selector545~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux6~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [2]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector545~0_combout  & ( \A_SPW_TOP|tx_data|mem[60][2]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [2]),
        .datac(!\A_SPW_TOP|tx_data|mem[60][2]~q ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector545~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector551~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector551~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector551~0 .lut_mask = 64'h0F0F0F0F55335533;
defparam \A_SPW_TOP|tx_data|Selector551~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y10_N2
dffeas \A_SPW_TOP|tx_data|mem[60][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector551~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[60][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[60][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[60][2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y10_N45
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector191~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector191~0_combout  = ( \A_SPW_TOP|tx_data|Selector185~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux6~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [2]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector185~0_combout  & ( \A_SPW_TOP|tx_data|mem[20][2]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [2]),
        .datac(!\A_SPW_TOP|tx_data|mem[20][2]~q ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector185~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector191~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector191~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector191~0 .lut_mask = 64'h0F0F0F0F55335533;
defparam \A_SPW_TOP|tx_data|Selector191~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y10_N14
dffeas \A_SPW_TOP|tx_data|mem[20][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector191~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[20][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[20][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[20][2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y10_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux6~3 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux6~3_combout  = ( \A_SPW_TOP|tx_data|mem[60][2]~q  & ( \A_SPW_TOP|tx_data|mem[20][2]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [3] & (((!\A_SPW_TOP|tx_data|wr_ptr [5])) # (\A_SPW_TOP|tx_data|mem[52][2]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [3] 
// & (((\A_SPW_TOP|tx_data|wr_ptr [5]) # (\A_SPW_TOP|tx_data|mem[28][2]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[60][2]~q  & ( \A_SPW_TOP|tx_data|mem[20][2]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [3] & (((!\A_SPW_TOP|tx_data|wr_ptr [5])) # 
// (\A_SPW_TOP|tx_data|mem[52][2]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [3] & (((\A_SPW_TOP|tx_data|mem[28][2]~q  & !\A_SPW_TOP|tx_data|wr_ptr [5])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[60][2]~q  & ( !\A_SPW_TOP|tx_data|mem[20][2]~q  & ( 
// (!\A_SPW_TOP|tx_data|wr_ptr [3] & (\A_SPW_TOP|tx_data|mem[52][2]~q  & ((\A_SPW_TOP|tx_data|wr_ptr [5])))) # (\A_SPW_TOP|tx_data|wr_ptr [3] & (((\A_SPW_TOP|tx_data|wr_ptr [5]) # (\A_SPW_TOP|tx_data|mem[28][2]~q )))) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|mem[60][2]~q  & ( !\A_SPW_TOP|tx_data|mem[20][2]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [3] & (\A_SPW_TOP|tx_data|mem[52][2]~q  & ((\A_SPW_TOP|tx_data|wr_ptr [5])))) # (\A_SPW_TOP|tx_data|wr_ptr [3] & (((\A_SPW_TOP|tx_data|mem[28][2]~q  & 
// !\A_SPW_TOP|tx_data|wr_ptr [5])))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[52][2]~q ),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datac(!\A_SPW_TOP|tx_data|mem[28][2]~q ),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datae(!\A_SPW_TOP|tx_data|mem[60][2]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[20][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux6~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux6~3 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux6~3 .lut_mask = 64'h03440377CF44CF77;
defparam \A_SPW_TOP|tx_data|Mux6~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y12_N21
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector83~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector83~0_combout  = ( \A_SPW_TOP|tx_data|Selector77~0_combout  & ( \A_SPW_TOP|tx_data|Mux6~20_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q ) # (\u0|write_data_fifo_tx|data_out [2]) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|Selector77~0_combout  & ( \A_SPW_TOP|tx_data|Mux6~20_combout  & ( \A_SPW_TOP|tx_data|mem[8][2]~q  ) ) ) # ( \A_SPW_TOP|tx_data|Selector77~0_combout  & ( !\A_SPW_TOP|tx_data|Mux6~20_combout  & ( (\A_SPW_TOP|tx_data|state_data_write.00~q 
//  & \u0|write_data_fifo_tx|data_out [2]) ) ) ) # ( !\A_SPW_TOP|tx_data|Selector77~0_combout  & ( !\A_SPW_TOP|tx_data|Mux6~20_combout  & ( \A_SPW_TOP|tx_data|mem[8][2]~q  ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[8][2]~q ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(!\u0|write_data_fifo_tx|data_out [2]),
        .datae(!\A_SPW_TOP|tx_data|Selector77~0_combout ),
        .dataf(!\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector83~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector83~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector83~0 .lut_mask = 64'h5555000F5555F0FF;
defparam \A_SPW_TOP|tx_data|Selector83~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y12_N20
dffeas \A_SPW_TOP|tx_data|mem[8][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector83~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[8][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[8][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[8][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y12_N57
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector299~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector299~0_combout  = ( \A_SPW_TOP|tx_data|mem[32][2]~q  & ( (!\A_SPW_TOP|tx_data|Selector293~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux6~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [2])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[32][2]~q  & ( (\A_SPW_TOP|tx_data|Selector293~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux6~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [2]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [2]),
        .datac(!\A_SPW_TOP|tx_data|Selector293~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[32][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector299~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector299~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector299~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|tx_data|Selector299~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y12_N17
dffeas \A_SPW_TOP|tx_data|mem[32][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector299~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[32][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[32][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[32][2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y12_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector11~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector11~0_combout  = ( \A_SPW_TOP|tx_data|mem[0][2]~q  & ( (!\A_SPW_TOP|tx_data|Selector5~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux6~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [2]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[0][2]~q  & ( (\A_SPW_TOP|tx_data|Selector5~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux6~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [2])))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\u0|write_data_fifo_tx|data_out [2]),
        .datac(!\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .datad(!\A_SPW_TOP|tx_data|Selector5~0_combout ),
        .datae(!\A_SPW_TOP|tx_data|mem[0][2]~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector11~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector11~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector11~0 .lut_mask = 64'h001BFF1B001BFF1B;
defparam \A_SPW_TOP|tx_data|Selector11~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y12_N5
dffeas \A_SPW_TOP|tx_data|mem[0][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector11~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[0][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[0][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[0][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y12_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector371~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector371~0_combout  = ( \A_SPW_TOP|tx_data|mem[40][2]~q  & ( (!\A_SPW_TOP|tx_data|Selector365~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux6~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [2])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[40][2]~q  & ( (\A_SPW_TOP|tx_data|Selector365~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux6~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [2]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [2]),
        .datac(!\A_SPW_TOP|tx_data|Selector365~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[40][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector371~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector371~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector371~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|tx_data|Selector371~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y12_N44
dffeas \A_SPW_TOP|tx_data|mem[40][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector371~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[40][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[40][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[40][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y12_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux6~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux6~0_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [3] & ( \A_SPW_TOP|tx_data|wr_ptr [5] & ( \A_SPW_TOP|tx_data|mem[40][2]~q  ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [3] & ( \A_SPW_TOP|tx_data|wr_ptr [5] & ( \A_SPW_TOP|tx_data|mem[32][2]~q  ) ) 
// ) # ( \A_SPW_TOP|tx_data|wr_ptr [3] & ( !\A_SPW_TOP|tx_data|wr_ptr [5] & ( \A_SPW_TOP|tx_data|mem[8][2]~q  ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [3] & ( !\A_SPW_TOP|tx_data|wr_ptr [5] & ( \A_SPW_TOP|tx_data|mem[0][2]~q  ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[8][2]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[32][2]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[0][2]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[40][2]~q ),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux6~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux6~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux6~0 .lut_mask = 64'h0F0F5555333300FF;
defparam \A_SPW_TOP|tx_data|Mux6~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y12_N33
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector119~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector119~0_combout  = ( \A_SPW_TOP|tx_data|Selector113~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux6~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [2]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector113~0_combout  & ( \A_SPW_TOP|tx_data|mem[12][2]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [2]),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[12][2]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector113~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector119~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector119~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector119~0 .lut_mask = 64'h00FF00FF53535353;
defparam \A_SPW_TOP|tx_data|Selector119~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y12_N5
dffeas \A_SPW_TOP|tx_data|mem[12][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector119~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[12][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[12][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[12][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y12_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector335~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector335~0_combout  = ( \A_SPW_TOP|tx_data|Selector329~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux6~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\u0|write_data_fifo_tx|data_out [2])) ) ) # ( !\A_SPW_TOP|tx_data|Selector329~0_combout  & ( \A_SPW_TOP|tx_data|mem[36][2]~q  ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [2]),
        .datab(!\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|mem[36][2]~q ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector329~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector335~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector335~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector335~0 .lut_mask = 64'h0F0F0F0F33553355;
defparam \A_SPW_TOP|tx_data|Selector335~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y12_N23
dffeas \A_SPW_TOP|tx_data|mem[36][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector335~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[36][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[36][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[36][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y12_N39
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector407~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector407~0_combout  = ( \A_SPW_TOP|tx_data|mem[44][2]~q  & ( (!\A_SPW_TOP|tx_data|Selector401~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux6~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [2])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[44][2]~q  & ( (\A_SPW_TOP|tx_data|Selector401~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux6~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [2]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [2]),
        .datac(!\A_SPW_TOP|tx_data|Selector401~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[44][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector407~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector407~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector407~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|tx_data|Selector407~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y12_N8
dffeas \A_SPW_TOP|tx_data|mem[44][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector407~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[44][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[44][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[44][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y12_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector47~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector47~0_combout  = ( \A_SPW_TOP|tx_data|mem[4][2]~q  & ( (!\A_SPW_TOP|tx_data|Selector41~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux6~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [2])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[4][2]~q  & ( (\A_SPW_TOP|tx_data|Selector41~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux6~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [2]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [2]),
        .datac(!\A_SPW_TOP|tx_data|Selector41~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[4][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector47~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector47~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector47~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|tx_data|Selector47~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y12_N53
dffeas \A_SPW_TOP|tx_data|mem[4][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector47~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[4][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[4][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[4][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y12_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux6~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux6~1_combout  = ( \A_SPW_TOP|tx_data|mem[44][2]~q  & ( \A_SPW_TOP|tx_data|mem[4][2]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [5] & (((!\A_SPW_TOP|tx_data|wr_ptr [3])) # (\A_SPW_TOP|tx_data|mem[12][2]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [5] & 
// (((\A_SPW_TOP|tx_data|wr_ptr [3]) # (\A_SPW_TOP|tx_data|mem[36][2]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[44][2]~q  & ( \A_SPW_TOP|tx_data|mem[4][2]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [5] & (((!\A_SPW_TOP|tx_data|wr_ptr [3])) # 
// (\A_SPW_TOP|tx_data|mem[12][2]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [5] & (((\A_SPW_TOP|tx_data|mem[36][2]~q  & !\A_SPW_TOP|tx_data|wr_ptr [3])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[44][2]~q  & ( !\A_SPW_TOP|tx_data|mem[4][2]~q  & ( 
// (!\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|mem[12][2]~q  & ((\A_SPW_TOP|tx_data|wr_ptr [3])))) # (\A_SPW_TOP|tx_data|wr_ptr [5] & (((\A_SPW_TOP|tx_data|wr_ptr [3]) # (\A_SPW_TOP|tx_data|mem[36][2]~q )))) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|mem[44][2]~q  & ( !\A_SPW_TOP|tx_data|mem[4][2]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|mem[12][2]~q  & ((\A_SPW_TOP|tx_data|wr_ptr [3])))) # (\A_SPW_TOP|tx_data|wr_ptr [5] & (((\A_SPW_TOP|tx_data|mem[36][2]~q  & 
// !\A_SPW_TOP|tx_data|wr_ptr [3])))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[12][2]~q ),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datac(!\A_SPW_TOP|tx_data|mem[36][2]~q ),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datae(!\A_SPW_TOP|tx_data|mem[44][2]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[4][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux6~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux6~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux6~1 .lut_mask = 64'h03440377CF44CF77;
defparam \A_SPW_TOP|tx_data|Mux6~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y10_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector515~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector515~0_combout  = ( \A_SPW_TOP|tx_data|Selector509~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux6~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [2]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector509~0_combout  & ( \A_SPW_TOP|tx_data|mem[56][2]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[56][2]~q ),
        .datad(!\u0|write_data_fifo_tx|data_out [2]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector509~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector515~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector515~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector515~0 .lut_mask = 64'h0F0F0F0F44774477;
defparam \A_SPW_TOP|tx_data|Selector515~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y10_N29
dffeas \A_SPW_TOP|tx_data|mem[56][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector515~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[56][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[56][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[56][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y12_N45
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector155~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector155~0_combout  = ( \A_SPW_TOP|tx_data|mem[16][2]~q  & ( (!\A_SPW_TOP|tx_data|Selector149~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux6~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [2]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[16][2]~q  & ( (\A_SPW_TOP|tx_data|Selector149~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux6~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [2])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [2]),
        .datab(!\A_SPW_TOP|tx_data|Selector149~0_combout ),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .datae(!\A_SPW_TOP|tx_data|mem[16][2]~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector155~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector155~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector155~0 .lut_mask = 64'h0131CDFD0131CDFD;
defparam \A_SPW_TOP|tx_data|Selector155~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y12_N29
dffeas \A_SPW_TOP|tx_data|mem[16][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector155~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[16][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[16][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[16][2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y10_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector443~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector443~0_combout  = ( \A_SPW_TOP|tx_data|Selector437~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux6~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [2]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector437~0_combout  & ( \A_SPW_TOP|tx_data|mem[48][2]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[48][2]~q ),
        .datad(!\u0|write_data_fifo_tx|data_out [2]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector437~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector443~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector443~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector443~0 .lut_mask = 64'h0F0F0F0F44774477;
defparam \A_SPW_TOP|tx_data|Selector443~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y10_N5
dffeas \A_SPW_TOP|tx_data|mem[48][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector443~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[48][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[48][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[48][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X51_Y10_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector227~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector227~0_combout  = ( \A_SPW_TOP|tx_data|Selector221~0_combout  & ( \A_SPW_TOP|tx_data|mem[24][2]~q  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux6~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [2])) ) ) ) # ( !\A_SPW_TOP|tx_data|Selector221~0_combout  & ( \A_SPW_TOP|tx_data|mem[24][2]~q  ) ) # ( \A_SPW_TOP|tx_data|Selector221~0_combout  & ( 
// !\A_SPW_TOP|tx_data|mem[24][2]~q  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux6~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [2])) ) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [2]),
        .datab(!\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .datac(gnd),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(!\A_SPW_TOP|tx_data|Selector221~0_combout ),
        .dataf(!\A_SPW_TOP|tx_data|mem[24][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector227~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector227~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector227~0 .lut_mask = 64'h00003355FFFF3355;
defparam \A_SPW_TOP|tx_data|Selector227~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y10_N11
dffeas \A_SPW_TOP|tx_data|mem[24][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector227~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[24][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[24][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[24][2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y10_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux6~2 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux6~2_combout  = ( \A_SPW_TOP|tx_data|mem[48][2]~q  & ( \A_SPW_TOP|tx_data|mem[24][2]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [5] & (((\A_SPW_TOP|tx_data|wr_ptr [3]) # (\A_SPW_TOP|tx_data|mem[16][2]~q )))) # (\A_SPW_TOP|tx_data|wr_ptr [5] & 
// (((!\A_SPW_TOP|tx_data|wr_ptr [3])) # (\A_SPW_TOP|tx_data|mem[56][2]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[48][2]~q  & ( \A_SPW_TOP|tx_data|mem[24][2]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [5] & (((\A_SPW_TOP|tx_data|wr_ptr [3]) # 
// (\A_SPW_TOP|tx_data|mem[16][2]~q )))) # (\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|mem[56][2]~q  & ((\A_SPW_TOP|tx_data|wr_ptr [3])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[48][2]~q  & ( !\A_SPW_TOP|tx_data|mem[24][2]~q  & ( 
// (!\A_SPW_TOP|tx_data|wr_ptr [5] & (((\A_SPW_TOP|tx_data|mem[16][2]~q  & !\A_SPW_TOP|tx_data|wr_ptr [3])))) # (\A_SPW_TOP|tx_data|wr_ptr [5] & (((!\A_SPW_TOP|tx_data|wr_ptr [3])) # (\A_SPW_TOP|tx_data|mem[56][2]~q ))) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|mem[48][2]~q  & ( !\A_SPW_TOP|tx_data|mem[24][2]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [5] & (((\A_SPW_TOP|tx_data|mem[16][2]~q  & !\A_SPW_TOP|tx_data|wr_ptr [3])))) # (\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|mem[56][2]~q  & 
// ((\A_SPW_TOP|tx_data|wr_ptr [3])))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[56][2]~q ),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datac(!\A_SPW_TOP|tx_data|mem[16][2]~q ),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datae(!\A_SPW_TOP|tx_data|mem[48][2]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[24][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux6~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux6~2 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux6~2 .lut_mask = 64'h0C113F110CDD3FDD;
defparam \A_SPW_TOP|tx_data|Mux6~2 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y12_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux6~4 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux6~4_combout  = ( \A_SPW_TOP|tx_data|Mux6~1_combout  & ( \A_SPW_TOP|tx_data|Mux6~2_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & (((\A_SPW_TOP|tx_data|wr_ptr [2]) # (\A_SPW_TOP|tx_data|Mux6~0_combout )))) # (\A_SPW_TOP|tx_data|wr_ptr 
// [4] & (((!\A_SPW_TOP|tx_data|wr_ptr [2])) # (\A_SPW_TOP|tx_data|Mux6~3_combout ))) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux6~1_combout  & ( \A_SPW_TOP|tx_data|Mux6~2_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & (((\A_SPW_TOP|tx_data|Mux6~0_combout  & 
// !\A_SPW_TOP|tx_data|wr_ptr [2])))) # (\A_SPW_TOP|tx_data|wr_ptr [4] & (((!\A_SPW_TOP|tx_data|wr_ptr [2])) # (\A_SPW_TOP|tx_data|Mux6~3_combout ))) ) ) ) # ( \A_SPW_TOP|tx_data|Mux6~1_combout  & ( !\A_SPW_TOP|tx_data|Mux6~2_combout  & ( 
// (!\A_SPW_TOP|tx_data|wr_ptr [4] & (((\A_SPW_TOP|tx_data|wr_ptr [2]) # (\A_SPW_TOP|tx_data|Mux6~0_combout )))) # (\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|Mux6~3_combout  & ((\A_SPW_TOP|tx_data|wr_ptr [2])))) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|Mux6~1_combout  & ( !\A_SPW_TOP|tx_data|Mux6~2_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & (((\A_SPW_TOP|tx_data|Mux6~0_combout  & !\A_SPW_TOP|tx_data|wr_ptr [2])))) # (\A_SPW_TOP|tx_data|wr_ptr [4] & 
// (\A_SPW_TOP|tx_data|Mux6~3_combout  & ((\A_SPW_TOP|tx_data|wr_ptr [2])))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux6~3_combout ),
        .datab(!\A_SPW_TOP|tx_data|Mux6~0_combout ),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datae(!\A_SPW_TOP|tx_data|Mux6~1_combout ),
        .dataf(!\A_SPW_TOP|tx_data|Mux6~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux6~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux6~4 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux6~4 .lut_mask = 64'h300530F53F053FF5;
defparam \A_SPW_TOP|tx_data|Mux6~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y10_N57
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector128~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector128~0_combout  = ( \A_SPW_TOP|tx_data|mem[13][2]~q  & ( (!\A_SPW_TOP|tx_data|Selector122~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux6~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [2])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[13][2]~q  & ( (\A_SPW_TOP|tx_data|Selector122~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux6~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [2]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\u0|write_data_fifo_tx|data_out [2]),
        .datad(!\A_SPW_TOP|tx_data|Selector122~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[13][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector128~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector128~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector128~0 .lut_mask = 64'h00470047FF47FF47;
defparam \A_SPW_TOP|tx_data|Selector128~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y10_N35
dffeas \A_SPW_TOP|tx_data|mem[13][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector128~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[13][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[13][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[13][2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y12_N57
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector56~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector56~0_combout  = ( \A_SPW_TOP|tx_data|mem[5][2]~q  & ( (!\A_SPW_TOP|tx_data|Selector50~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux6~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [2])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[5][2]~q  & ( (\A_SPW_TOP|tx_data|Selector50~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux6~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [2]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [2]),
        .datac(!\A_SPW_TOP|tx_data|Selector50~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[5][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector56~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector56~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector56~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|tx_data|Selector56~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y12_N11
dffeas \A_SPW_TOP|tx_data|mem[5][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector56~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[5][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[5][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[5][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y10_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector344~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector344~0_combout  = ( \A_SPW_TOP|tx_data|Selector338~0_combout  & ( \u0|write_data_fifo_tx|data_out [2] & ( (\A_SPW_TOP|tx_data|state_data_write.00~q ) # (\A_SPW_TOP|tx_data|Mux6~20_combout ) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|Selector338~0_combout  & ( \u0|write_data_fifo_tx|data_out [2] & ( \A_SPW_TOP|tx_data|mem[37][2]~q  ) ) ) # ( \A_SPW_TOP|tx_data|Selector338~0_combout  & ( !\u0|write_data_fifo_tx|data_out [2] & ( (\A_SPW_TOP|tx_data|Mux6~20_combout  & 
// !\A_SPW_TOP|tx_data|state_data_write.00~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|Selector338~0_combout  & ( !\u0|write_data_fifo_tx|data_out [2] & ( \A_SPW_TOP|tx_data|mem[37][2]~q  ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[37][2]~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .datac(gnd),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(!\A_SPW_TOP|tx_data|Selector338~0_combout ),
        .dataf(!\u0|write_data_fifo_tx|data_out [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector344~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector344~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector344~0 .lut_mask = 64'h55553300555533FF;
defparam \A_SPW_TOP|tx_data|Selector344~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X45_Y10_N53
dffeas \A_SPW_TOP|tx_data|mem[37][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector344~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[37][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[37][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[37][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y10_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector416~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector416~0_combout  = ( \A_SPW_TOP|tx_data|Selector410~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux6~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [2]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector410~0_combout  & ( \A_SPW_TOP|tx_data|mem[45][2]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[45][2]~q ),
        .datad(!\u0|write_data_fifo_tx|data_out [2]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector410~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector416~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector416~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector416~0 .lut_mask = 64'h0F0F0F0F44774477;
defparam \A_SPW_TOP|tx_data|Selector416~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y10_N29
dffeas \A_SPW_TOP|tx_data|mem[45][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector416~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[45][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[45][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[45][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y10_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux6~6 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux6~6_combout  = ( \A_SPW_TOP|tx_data|mem[45][2]~q  & ( \A_SPW_TOP|tx_data|wr_ptr [5] & ( (\A_SPW_TOP|tx_data|mem[37][2]~q ) # (\A_SPW_TOP|tx_data|wr_ptr [3]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[45][2]~q  & ( \A_SPW_TOP|tx_data|wr_ptr 
// [5] & ( (!\A_SPW_TOP|tx_data|wr_ptr [3] & \A_SPW_TOP|tx_data|mem[37][2]~q ) ) ) ) # ( \A_SPW_TOP|tx_data|mem[45][2]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [5] & ( (!\A_SPW_TOP|tx_data|wr_ptr [3] & ((\A_SPW_TOP|tx_data|mem[5][2]~q ))) # 
// (\A_SPW_TOP|tx_data|wr_ptr [3] & (\A_SPW_TOP|tx_data|mem[13][2]~q )) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[45][2]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [5] & ( (!\A_SPW_TOP|tx_data|wr_ptr [3] & ((\A_SPW_TOP|tx_data|mem[5][2]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [3] 
// & (\A_SPW_TOP|tx_data|mem[13][2]~q )) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[13][2]~q ),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datac(!\A_SPW_TOP|tx_data|mem[5][2]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[37][2]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[45][2]~q ),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux6~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux6~6 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux6~6 .lut_mask = 64'h1D1D1D1D00CC33FF;
defparam \A_SPW_TOP|tx_data|Mux6~6 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y12_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector308~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector308~0_combout  = ( \A_SPW_TOP|tx_data|mem[33][2]~q  & ( (!\A_SPW_TOP|tx_data|Selector302~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux6~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [2])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[33][2]~q  & ( (\A_SPW_TOP|tx_data|Selector302~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux6~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [2]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector302~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [2]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[33][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector308~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector308~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector308~0 .lut_mask = 64'h04070407F4F7F4F7;
defparam \A_SPW_TOP|tx_data|Selector308~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y12_N20
dffeas \A_SPW_TOP|tx_data|mem[33][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector308~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[33][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[33][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[33][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y12_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector380~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector380~0_combout  = ( \A_SPW_TOP|tx_data|mem[41][2]~q  & ( (!\A_SPW_TOP|tx_data|Selector374~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux6~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [2])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[41][2]~q  & ( (\A_SPW_TOP|tx_data|Selector374~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux6~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [2]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [2]),
        .datac(!\A_SPW_TOP|tx_data|Selector374~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[41][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector380~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector380~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector380~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|tx_data|Selector380~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y12_N14
dffeas \A_SPW_TOP|tx_data|mem[41][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector380~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[41][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[41][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[41][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y12_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector92~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector92~0_combout  = ( \A_SPW_TOP|tx_data|mem[9][2]~q  & ( (!\A_SPW_TOP|tx_data|Selector86~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux6~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [2])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[9][2]~q  & ( (\A_SPW_TOP|tx_data|Selector86~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux6~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [2]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [2]),
        .datac(!\A_SPW_TOP|tx_data|Selector86~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[9][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector92~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector92~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector92~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|tx_data|Selector92~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y12_N53
dffeas \A_SPW_TOP|tx_data|mem[9][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector92~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[9][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[9][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[9][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y12_N15
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux6~5 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux6~5_combout  = ( \A_SPW_TOP|tx_data|mem[1][2]~q  & ( \A_SPW_TOP|tx_data|wr_ptr [3] & ( (!\A_SPW_TOP|tx_data|wr_ptr [5] & ((\A_SPW_TOP|tx_data|mem[9][2]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|mem[41][2]~q )) ) ) 
// ) # ( !\A_SPW_TOP|tx_data|mem[1][2]~q  & ( \A_SPW_TOP|tx_data|wr_ptr [3] & ( (!\A_SPW_TOP|tx_data|wr_ptr [5] & ((\A_SPW_TOP|tx_data|mem[9][2]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|mem[41][2]~q )) ) ) ) # ( 
// \A_SPW_TOP|tx_data|mem[1][2]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [3] & ( (!\A_SPW_TOP|tx_data|wr_ptr [5]) # (\A_SPW_TOP|tx_data|mem[33][2]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[1][2]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [3] & ( (\A_SPW_TOP|tx_data|mem[33][2]~q 
//  & \A_SPW_TOP|tx_data|wr_ptr [5]) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[33][2]~q ),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datac(!\A_SPW_TOP|tx_data|mem[41][2]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[9][2]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[1][2]~q ),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux6~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux6~5 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux6~5 .lut_mask = 64'h1111DDDD03CF03CF;
defparam \A_SPW_TOP|tx_data|Mux6~5 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y10_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector272~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector272~0_combout  = ( \A_SPW_TOP|tx_data|mem[29][2]~q  & ( (!\A_SPW_TOP|tx_data|Selector266~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux6~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [2]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[29][2]~q  & ( (\A_SPW_TOP|tx_data|Selector266~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux6~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [2])))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\u0|write_data_fifo_tx|data_out [2]),
        .datac(!\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .datad(!\A_SPW_TOP|tx_data|Selector266~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[29][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector272~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector272~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector272~0 .lut_mask = 64'h001B001BFF1BFF1B;
defparam \A_SPW_TOP|tx_data|Selector272~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y10_N53
dffeas \A_SPW_TOP|tx_data|mem[29][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector272~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[29][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[29][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[29][2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y10_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector560~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector560~0_combout  = ( \A_SPW_TOP|tx_data|mem[61][2]~q  & ( (!\A_SPW_TOP|tx_data|Selector554~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux6~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [2])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[61][2]~q  & ( (\A_SPW_TOP|tx_data|Selector554~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux6~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [2]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector554~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [2]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[61][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector560~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector560~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector560~0 .lut_mask = 64'h04070407F4F7F4F7;
defparam \A_SPW_TOP|tx_data|Selector560~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y10_N11
dffeas \A_SPW_TOP|tx_data|mem[61][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector560~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[61][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[61][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[61][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X51_Y10_N15
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector200~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector200~0_combout  = ( \A_SPW_TOP|tx_data|mem[21][2]~q  & ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector194~0_combout ) # (\u0|write_data_fifo_tx|data_out [2]) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|mem[21][2]~q  & ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (\u0|write_data_fifo_tx|data_out [2] & \A_SPW_TOP|tx_data|Selector194~0_combout ) ) ) ) # ( \A_SPW_TOP|tx_data|mem[21][2]~q  & ( !\A_SPW_TOP|tx_data|state_data_write.00~q  
// & ( (!\A_SPW_TOP|tx_data|Selector194~0_combout ) # (\A_SPW_TOP|tx_data|Mux6~20_combout ) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[21][2]~q  & ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( (\A_SPW_TOP|tx_data|Mux6~20_combout  & 
// \A_SPW_TOP|tx_data|Selector194~0_combout ) ) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [2]),
        .datab(!\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector194~0_combout ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|tx_data|mem[21][2]~q ),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector200~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector200~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector200~0 .lut_mask = 64'h0303F3F30505F5F5;
defparam \A_SPW_TOP|tx_data|Selector200~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y10_N17
dffeas \A_SPW_TOP|tx_data|mem[21][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector200~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[21][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[21][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[21][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y10_N39
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector488~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector488~0_combout  = ( \A_SPW_TOP|tx_data|mem[53][2]~q  & ( (!\A_SPW_TOP|tx_data|Selector482~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux6~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [2])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[53][2]~q  & ( (\A_SPW_TOP|tx_data|Selector482~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux6~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [2]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\u0|write_data_fifo_tx|data_out [2]),
        .datad(!\A_SPW_TOP|tx_data|Selector482~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[53][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector488~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector488~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector488~0 .lut_mask = 64'h00470047FF47FF47;
defparam \A_SPW_TOP|tx_data|Selector488~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y10_N17
dffeas \A_SPW_TOP|tx_data|mem[53][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector488~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[53][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[53][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[53][2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y10_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux6~8 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux6~8_combout  = ( \A_SPW_TOP|tx_data|mem[53][2]~q  & ( \A_SPW_TOP|tx_data|wr_ptr [3] & ( (!\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|mem[29][2]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [5] & ((\A_SPW_TOP|tx_data|mem[61][2]~q ))) ) 
// ) ) # ( !\A_SPW_TOP|tx_data|mem[53][2]~q  & ( \A_SPW_TOP|tx_data|wr_ptr [3] & ( (!\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|mem[29][2]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [5] & ((\A_SPW_TOP|tx_data|mem[61][2]~q ))) ) ) ) # ( 
// \A_SPW_TOP|tx_data|mem[53][2]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [3] & ( (\A_SPW_TOP|tx_data|mem[21][2]~q ) # (\A_SPW_TOP|tx_data|wr_ptr [5]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[53][2]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [3] & ( (!\A_SPW_TOP|tx_data|wr_ptr [5] 
// & \A_SPW_TOP|tx_data|mem[21][2]~q ) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[29][2]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[61][2]~q ),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datad(!\A_SPW_TOP|tx_data|mem[21][2]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[53][2]~q ),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux6~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux6~8 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux6~8 .lut_mask = 64'h00F00FFF53535353;
defparam \A_SPW_TOP|tx_data|Mux6~8 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y10_N39
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector236~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector236~0_combout  = ( \A_SPW_TOP|tx_data|mem[25][2]~q  & ( (!\A_SPW_TOP|tx_data|Selector230~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux6~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [2])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[25][2]~q  & ( (\A_SPW_TOP|tx_data|Selector230~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux6~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [2]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [2]),
        .datac(!\A_SPW_TOP|tx_data|Selector230~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[25][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector236~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector236~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector236~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|tx_data|Selector236~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y10_N8
dffeas \A_SPW_TOP|tx_data|mem[25][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector236~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[25][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[25][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[25][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y10_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector524~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector524~0_combout  = ( \A_SPW_TOP|tx_data|Selector518~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux6~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [2]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector518~0_combout  & ( \A_SPW_TOP|tx_data|mem[57][2]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\u0|write_data_fifo_tx|data_out [2]),
        .datad(!\A_SPW_TOP|tx_data|mem[57][2]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector518~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector524~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector524~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector524~0 .lut_mask = 64'h00FF00FF47474747;
defparam \A_SPW_TOP|tx_data|Selector524~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y10_N47
dffeas \A_SPW_TOP|tx_data|mem[57][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector524~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[57][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[57][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[57][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y10_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector452~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector452~0_combout  = ( \A_SPW_TOP|tx_data|mem[49][2]~q  & ( (!\A_SPW_TOP|tx_data|Selector446~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux6~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [2]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[49][2]~q  & ( (\A_SPW_TOP|tx_data|Selector446~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux6~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [2])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [2]),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .datad(!\A_SPW_TOP|tx_data|Selector446~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[49][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector452~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector452~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector452~0 .lut_mask = 64'h001D001DFF1DFF1D;
defparam \A_SPW_TOP|tx_data|Selector452~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y10_N11
dffeas \A_SPW_TOP|tx_data|mem[49][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector452~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[49][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[49][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[49][2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y10_N39
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector164~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector164~0_combout  = ( \A_SPW_TOP|tx_data|Selector158~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux6~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [2]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector158~0_combout  & ( \A_SPW_TOP|tx_data|mem[17][2]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[17][2]~q ),
        .datad(!\u0|write_data_fifo_tx|data_out [2]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector158~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector164~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector164~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector164~0 .lut_mask = 64'h0F0F0F0F44774477;
defparam \A_SPW_TOP|tx_data|Selector164~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y10_N32
dffeas \A_SPW_TOP|tx_data|mem[17][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector164~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[17][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[17][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[17][2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y10_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux6~7 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux6~7_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [5] & ( \A_SPW_TOP|tx_data|mem[17][2]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [3] & ((\A_SPW_TOP|tx_data|mem[49][2]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [3] & (\A_SPW_TOP|tx_data|mem[57][2]~q )) ) 
// ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [5] & ( \A_SPW_TOP|tx_data|mem[17][2]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [3]) # (\A_SPW_TOP|tx_data|mem[25][2]~q ) ) ) ) # ( \A_SPW_TOP|tx_data|wr_ptr [5] & ( !\A_SPW_TOP|tx_data|mem[17][2]~q  & ( 
// (!\A_SPW_TOP|tx_data|wr_ptr [3] & ((\A_SPW_TOP|tx_data|mem[49][2]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [3] & (\A_SPW_TOP|tx_data|mem[57][2]~q )) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [5] & ( !\A_SPW_TOP|tx_data|mem[17][2]~q  & ( (\A_SPW_TOP|tx_data|wr_ptr 
// [3] & \A_SPW_TOP|tx_data|mem[25][2]~q ) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datab(!\A_SPW_TOP|tx_data|mem[25][2]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[57][2]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[49][2]~q ),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .dataf(!\A_SPW_TOP|tx_data|mem[17][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux6~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux6~7 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux6~7 .lut_mask = 64'h111105AFBBBB05AF;
defparam \A_SPW_TOP|tx_data|Mux6~7 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y10_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux6~9 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux6~9_combout  = ( \A_SPW_TOP|tx_data|Mux6~8_combout  & ( \A_SPW_TOP|tx_data|Mux6~7_combout  & ( ((!\A_SPW_TOP|tx_data|wr_ptr [2] & ((\A_SPW_TOP|tx_data|Mux6~5_combout ))) # (\A_SPW_TOP|tx_data|wr_ptr [2] & 
// (\A_SPW_TOP|tx_data|Mux6~6_combout ))) # (\A_SPW_TOP|tx_data|wr_ptr [4]) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux6~8_combout  & ( \A_SPW_TOP|tx_data|Mux6~7_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & ((!\A_SPW_TOP|tx_data|wr_ptr [2] & 
// ((\A_SPW_TOP|tx_data|Mux6~5_combout ))) # (\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|Mux6~6_combout )))) # (\A_SPW_TOP|tx_data|wr_ptr [4] & (((!\A_SPW_TOP|tx_data|wr_ptr [2])))) ) ) ) # ( \A_SPW_TOP|tx_data|Mux6~8_combout  & ( 
// !\A_SPW_TOP|tx_data|Mux6~7_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & ((!\A_SPW_TOP|tx_data|wr_ptr [2] & ((\A_SPW_TOP|tx_data|Mux6~5_combout ))) # (\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|Mux6~6_combout )))) # (\A_SPW_TOP|tx_data|wr_ptr 
// [4] & (((\A_SPW_TOP|tx_data|wr_ptr [2])))) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux6~8_combout  & ( !\A_SPW_TOP|tx_data|Mux6~7_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & ((!\A_SPW_TOP|tx_data|wr_ptr [2] & ((\A_SPW_TOP|tx_data|Mux6~5_combout ))) # 
// (\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|Mux6~6_combout )))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datab(!\A_SPW_TOP|tx_data|Mux6~6_combout ),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datad(!\A_SPW_TOP|tx_data|Mux6~5_combout ),
        .datae(!\A_SPW_TOP|tx_data|Mux6~8_combout ),
        .dataf(!\A_SPW_TOP|tx_data|Mux6~7_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux6~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux6~9 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux6~9 .lut_mask = 64'h02A207A752F257F7;
defparam \A_SPW_TOP|tx_data|Mux6~9 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y12_N45
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector434~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector434~0_combout  = ( \A_SPW_TOP|tx_data|mem[47][2]~q  & ( (!\A_SPW_TOP|tx_data|Selector428~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux6~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [2])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[47][2]~q  & ( (\A_SPW_TOP|tx_data|Selector428~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux6~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [2]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [2]),
        .datac(!\A_SPW_TOP|tx_data|Selector428~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[47][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector434~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector434~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector434~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|tx_data|Selector434~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y12_N35
dffeas \A_SPW_TOP|tx_data|mem[47][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector434~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[47][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[47][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[47][2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y12_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector362~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector362~0_combout  = ( \A_SPW_TOP|tx_data|mem[39][2]~q  & ( (!\A_SPW_TOP|tx_data|Selector356~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux6~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [2])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[39][2]~q  & ( (\A_SPW_TOP|tx_data|Selector356~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux6~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [2]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [2]),
        .datac(!\A_SPW_TOP|tx_data|Selector356~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[39][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector362~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector362~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector362~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|tx_data|Selector362~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y12_N17
dffeas \A_SPW_TOP|tx_data|mem[39][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector362~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[39][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[39][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[39][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y12_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector326~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector326~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector320~0_combout  & ((\A_SPW_TOP|tx_data|mem[35][2]~q ))) # (\A_SPW_TOP|tx_data|Selector320~0_combout  & (\u0|write_data_fifo_tx|data_out 
// [2])) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector320~0_combout  & ((\A_SPW_TOP|tx_data|mem[35][2]~q ))) # (\A_SPW_TOP|tx_data|Selector320~0_combout  & (\A_SPW_TOP|tx_data|Mux6~20_combout )) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [2]),
        .datab(!\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector320~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|mem[35][2]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector326~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector326~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector326~0 .lut_mask = 64'h03F303F305F505F5;
defparam \A_SPW_TOP|tx_data|Selector326~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y12_N47
dffeas \A_SPW_TOP|tx_data|mem[35][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector326~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[35][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[35][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[35][2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y12_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector398~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector398~0_combout  = ( \A_SPW_TOP|tx_data|Selector392~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux6~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [2]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector392~0_combout  & ( \A_SPW_TOP|tx_data|mem[43][2]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [2]),
        .datac(!\A_SPW_TOP|tx_data|mem[43][2]~q ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector392~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector398~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector398~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector398~0 .lut_mask = 64'h0F0F0F0F55335533;
defparam \A_SPW_TOP|tx_data|Selector398~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y12_N2
dffeas \A_SPW_TOP|tx_data|mem[43][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector398~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[43][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[43][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[43][2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y12_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux6~16 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux6~16_combout  = ( \A_SPW_TOP|tx_data|mem[43][2]~q  & ( \A_SPW_TOP|tx_data|wr_ptr [2] & ( (!\A_SPW_TOP|tx_data|wr_ptr [3] & ((\A_SPW_TOP|tx_data|mem[39][2]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [3] & (\A_SPW_TOP|tx_data|mem[47][2]~q )) ) 
// ) ) # ( !\A_SPW_TOP|tx_data|mem[43][2]~q  & ( \A_SPW_TOP|tx_data|wr_ptr [2] & ( (!\A_SPW_TOP|tx_data|wr_ptr [3] & ((\A_SPW_TOP|tx_data|mem[39][2]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [3] & (\A_SPW_TOP|tx_data|mem[47][2]~q )) ) ) ) # ( 
// \A_SPW_TOP|tx_data|mem[43][2]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [2] & ( (\A_SPW_TOP|tx_data|wr_ptr [3]) # (\A_SPW_TOP|tx_data|mem[35][2]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[43][2]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [2] & ( 
// (\A_SPW_TOP|tx_data|mem[35][2]~q  & !\A_SPW_TOP|tx_data|wr_ptr [3]) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[47][2]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[39][2]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[35][2]~q ),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datae(!\A_SPW_TOP|tx_data|mem[43][2]~q ),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux6~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux6~16 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux6~16 .lut_mask = 64'h0F000FFF33553355;
defparam \A_SPW_TOP|tx_data|Mux6~16 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y10_N15
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector290~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector290~0_combout  = ( \A_SPW_TOP|tx_data|mem[31][2]~q  & ( (!\A_SPW_TOP|tx_data|Selector284~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux6~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [2])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[31][2]~q  & ( (\A_SPW_TOP|tx_data|Selector284~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux6~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [2]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector284~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [2]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[31][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector290~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector290~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector290~0 .lut_mask = 64'h04070407F4F7F4F7;
defparam \A_SPW_TOP|tx_data|Selector290~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y10_N50
dffeas \A_SPW_TOP|tx_data|mem[31][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector290~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[31][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[31][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[31][2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y10_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector254~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector254~0_combout  = ( \A_SPW_TOP|tx_data|Selector248~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux6~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [2]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector248~0_combout  & ( \A_SPW_TOP|tx_data|mem[27][2]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [2]),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[27][2]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector248~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector254~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector254~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector254~0 .lut_mask = 64'h00FF00FF53535353;
defparam \A_SPW_TOP|tx_data|Selector254~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y10_N47
dffeas \A_SPW_TOP|tx_data|mem[27][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector254~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[27][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[27][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[27][2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y10_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector218~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector218~0_combout  = ( \A_SPW_TOP|tx_data|Selector212~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux6~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [2]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector212~0_combout  & ( \A_SPW_TOP|tx_data|mem[23][2]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[23][2]~q ),
        .datad(!\u0|write_data_fifo_tx|data_out [2]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector212~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector218~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector218~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector218~0 .lut_mask = 64'h0F0F0F0F44774477;
defparam \A_SPW_TOP|tx_data|Selector218~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y10_N35
dffeas \A_SPW_TOP|tx_data|mem[23][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector218~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[23][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[23][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[23][2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y10_N57
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector182~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector182~0_combout  = ( \A_SPW_TOP|tx_data|Mux6~20_combout  & ( (!\A_SPW_TOP|tx_data|Selector176~0_combout  & (((\A_SPW_TOP|tx_data|mem[19][2]~q )))) # (\A_SPW_TOP|tx_data|Selector176~0_combout  & 
// ((!\A_SPW_TOP|tx_data|state_data_write.00~q ) # ((\u0|write_data_fifo_tx|data_out [2])))) ) ) # ( !\A_SPW_TOP|tx_data|Mux6~20_combout  & ( (!\A_SPW_TOP|tx_data|Selector176~0_combout  & (((\A_SPW_TOP|tx_data|mem[19][2]~q )))) # 
// (\A_SPW_TOP|tx_data|Selector176~0_combout  & (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [2]))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\u0|write_data_fifo_tx|data_out [2]),
        .datac(!\A_SPW_TOP|tx_data|Selector176~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|mem[19][2]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector182~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector182~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector182~0 .lut_mask = 64'h01F101F10BFB0BFB;
defparam \A_SPW_TOP|tx_data|Selector182~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y10_N29
dffeas \A_SPW_TOP|tx_data|mem[19][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector182~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[19][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[19][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[19][2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y10_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux6~17 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux6~17_combout  = ( \A_SPW_TOP|tx_data|mem[19][2]~q  & ( \A_SPW_TOP|tx_data|wr_ptr [3] & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & ((\A_SPW_TOP|tx_data|mem[27][2]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|mem[31][2]~q )) ) 
// ) ) # ( !\A_SPW_TOP|tx_data|mem[19][2]~q  & ( \A_SPW_TOP|tx_data|wr_ptr [3] & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & ((\A_SPW_TOP|tx_data|mem[27][2]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|mem[31][2]~q )) ) ) ) # ( 
// \A_SPW_TOP|tx_data|mem[19][2]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [3] & ( (!\A_SPW_TOP|tx_data|wr_ptr [2]) # (\A_SPW_TOP|tx_data|mem[23][2]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[19][2]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [3] & ( 
// (\A_SPW_TOP|tx_data|mem[23][2]~q  & \A_SPW_TOP|tx_data|wr_ptr [2]) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[31][2]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[27][2]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[23][2]~q ),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datae(!\A_SPW_TOP|tx_data|mem[19][2]~q ),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux6~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux6~17 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux6~17 .lut_mask = 64'h000FFF0F33553355;
defparam \A_SPW_TOP|tx_data|Mux6~17 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y10_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector542~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector542~0_combout  = ( \A_SPW_TOP|tx_data|Selector536~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux6~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [2]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector536~0_combout  & ( \A_SPW_TOP|tx_data|mem[59][2]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\u0|write_data_fifo_tx|data_out [2]),
        .datad(!\A_SPW_TOP|tx_data|mem[59][2]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector536~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector542~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector542~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector542~0 .lut_mask = 64'h00FF00FF47474747;
defparam \A_SPW_TOP|tx_data|Selector542~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y10_N23
dffeas \A_SPW_TOP|tx_data|mem[59][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector542~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[59][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[59][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[59][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y10_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector506~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector506~0_combout  = ( \A_SPW_TOP|tx_data|mem[55][2]~q  & ( (!\A_SPW_TOP|tx_data|Selector500~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux6~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [2])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[55][2]~q  & ( (\A_SPW_TOP|tx_data|Selector500~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux6~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [2]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector500~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [2]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[55][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector506~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector506~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector506~0 .lut_mask = 64'h04070407F4F7F4F7;
defparam \A_SPW_TOP|tx_data|Selector506~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y10_N32
dffeas \A_SPW_TOP|tx_data|mem[55][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector506~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[55][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[55][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[55][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y10_N51
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector578~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector578~0_combout  = ( \A_SPW_TOP|tx_data|mem[63][2]~q  & ( (!\A_SPW_TOP|tx_data|Selector572~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux6~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [2])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[63][2]~q  & ( (\A_SPW_TOP|tx_data|Selector572~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux6~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [2]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector572~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [2]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[63][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector578~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector578~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector578~0 .lut_mask = 64'h04070407F4F7F4F7;
defparam \A_SPW_TOP|tx_data|Selector578~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y10_N44
dffeas \A_SPW_TOP|tx_data|mem[63][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector578~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[63][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[63][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[63][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y10_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector470~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector470~0_combout  = ( \A_SPW_TOP|tx_data|Mux6~20_combout  & ( (!\A_SPW_TOP|tx_data|Selector464~0_combout  & (((\A_SPW_TOP|tx_data|mem[51][2]~q )))) # (\A_SPW_TOP|tx_data|Selector464~0_combout  & 
// (((!\A_SPW_TOP|tx_data|state_data_write.00~q )) # (\u0|write_data_fifo_tx|data_out [2]))) ) ) # ( !\A_SPW_TOP|tx_data|Mux6~20_combout  & ( (!\A_SPW_TOP|tx_data|Selector464~0_combout  & (((\A_SPW_TOP|tx_data|mem[51][2]~q )))) # 
// (\A_SPW_TOP|tx_data|Selector464~0_combout  & (\u0|write_data_fifo_tx|data_out [2] & (\A_SPW_TOP|tx_data|state_data_write.00~q ))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [2]),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector464~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|mem[51][2]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector470~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector470~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector470~0 .lut_mask = 64'h01F101F10DFD0DFD;
defparam \A_SPW_TOP|tx_data|Selector470~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y10_N23
dffeas \A_SPW_TOP|tx_data|mem[51][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector470~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[51][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[51][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[51][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y10_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux6~18 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux6~18_combout  = ( \A_SPW_TOP|tx_data|mem[51][2]~q  & ( \A_SPW_TOP|tx_data|wr_ptr [2] & ( (!\A_SPW_TOP|tx_data|wr_ptr [3] & (\A_SPW_TOP|tx_data|mem[55][2]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [3] & ((\A_SPW_TOP|tx_data|mem[63][2]~q ))) ) 
// ) ) # ( !\A_SPW_TOP|tx_data|mem[51][2]~q  & ( \A_SPW_TOP|tx_data|wr_ptr [2] & ( (!\A_SPW_TOP|tx_data|wr_ptr [3] & (\A_SPW_TOP|tx_data|mem[55][2]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [3] & ((\A_SPW_TOP|tx_data|mem[63][2]~q ))) ) ) ) # ( 
// \A_SPW_TOP|tx_data|mem[51][2]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [2] & ( (!\A_SPW_TOP|tx_data|wr_ptr [3]) # (\A_SPW_TOP|tx_data|mem[59][2]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[51][2]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [2] & ( 
// (\A_SPW_TOP|tx_data|mem[59][2]~q  & \A_SPW_TOP|tx_data|wr_ptr [3]) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[59][2]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[55][2]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[63][2]~q ),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datae(!\A_SPW_TOP|tx_data|mem[51][2]~q ),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux6~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux6~18 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux6~18 .lut_mask = 64'h0055FF55330F330F;
defparam \A_SPW_TOP|tx_data|Mux6~18 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y12_N39
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector74~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector74~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector68~0_combout  & ((\A_SPW_TOP|tx_data|mem[7][2]~q ))) # (\A_SPW_TOP|tx_data|Selector68~0_combout  & (\u0|write_data_fifo_tx|data_out 
// [2])) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector68~0_combout  & ((\A_SPW_TOP|tx_data|mem[7][2]~q ))) # (\A_SPW_TOP|tx_data|Selector68~0_combout  & (\A_SPW_TOP|tx_data|Mux6~20_combout )) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [2]),
        .datab(!\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector68~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|mem[7][2]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector74~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector74~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector74~0 .lut_mask = 64'h03F303F305F505F5;
defparam \A_SPW_TOP|tx_data|Selector74~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y12_N56
dffeas \A_SPW_TOP|tx_data|mem[7][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector74~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[7][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[7][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[7][2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y12_N39
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector146~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector146~0_combout  = ( \A_SPW_TOP|tx_data|Selector140~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux6~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [2]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector140~0_combout  & ( \A_SPW_TOP|tx_data|mem[15][2]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [2]),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[15][2]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector140~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector146~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector146~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector146~0 .lut_mask = 64'h00FF00FF53535353;
defparam \A_SPW_TOP|tx_data|Selector146~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y12_N29
dffeas \A_SPW_TOP|tx_data|mem[15][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector146~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[15][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[15][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[15][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y12_N51
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector38~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector38~0_combout  = ( \A_SPW_TOP|tx_data|mem[3][2]~q  & ( (!\A_SPW_TOP|tx_data|Selector32~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux6~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [2]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[3][2]~q  & ( (\A_SPW_TOP|tx_data|Selector32~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux6~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [2])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [2]),
        .datab(!\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector32~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[3][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector38~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector38~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector38~0 .lut_mask = 64'h03050305F3F5F3F5;
defparam \A_SPW_TOP|tx_data|Selector38~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y12_N11
dffeas \A_SPW_TOP|tx_data|mem[3][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector38~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[3][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[3][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[3][2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y12_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector110~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector110~0_combout  = ( \A_SPW_TOP|tx_data|mem[11][2]~q  & ( (!\A_SPW_TOP|tx_data|Selector104~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux6~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [2])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[11][2]~q  & ( (\A_SPW_TOP|tx_data|Selector104~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux6~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [2]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [2]),
        .datac(!\A_SPW_TOP|tx_data|Selector104~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[11][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector110~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector110~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector110~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|tx_data|Selector110~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y12_N53
dffeas \A_SPW_TOP|tx_data|mem[11][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector110~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[11][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[11][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[11][2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y12_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux6~15 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux6~15_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [3] & ( \A_SPW_TOP|tx_data|mem[11][2]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [2]) # (\A_SPW_TOP|tx_data|mem[15][2]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [3] & ( 
// \A_SPW_TOP|tx_data|mem[11][2]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & ((\A_SPW_TOP|tx_data|mem[3][2]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|mem[7][2]~q )) ) ) ) # ( \A_SPW_TOP|tx_data|wr_ptr [3] & ( !\A_SPW_TOP|tx_data|mem[11][2]~q  
// & ( (\A_SPW_TOP|tx_data|wr_ptr [2] & \A_SPW_TOP|tx_data|mem[15][2]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [3] & ( !\A_SPW_TOP|tx_data|mem[11][2]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & ((\A_SPW_TOP|tx_data|mem[3][2]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr 
// [2] & (\A_SPW_TOP|tx_data|mem[7][2]~q )) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datab(!\A_SPW_TOP|tx_data|mem[7][2]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[15][2]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[3][2]~q ),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .dataf(!\A_SPW_TOP|tx_data|mem[11][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux6~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux6~15 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux6~15 .lut_mask = 64'h11BB050511BBAFAF;
defparam \A_SPW_TOP|tx_data|Mux6~15 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y12_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux6~19 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux6~19_combout  = ( \A_SPW_TOP|tx_data|Mux6~18_combout  & ( \A_SPW_TOP|tx_data|Mux6~15_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & (((!\A_SPW_TOP|tx_data|wr_ptr [5])) # (\A_SPW_TOP|tx_data|Mux6~16_combout ))) # 
// (\A_SPW_TOP|tx_data|wr_ptr [4] & (((\A_SPW_TOP|tx_data|wr_ptr [5]) # (\A_SPW_TOP|tx_data|Mux6~17_combout )))) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux6~18_combout  & ( \A_SPW_TOP|tx_data|Mux6~15_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & 
// (((!\A_SPW_TOP|tx_data|wr_ptr [5])) # (\A_SPW_TOP|tx_data|Mux6~16_combout ))) # (\A_SPW_TOP|tx_data|wr_ptr [4] & (((\A_SPW_TOP|tx_data|Mux6~17_combout  & !\A_SPW_TOP|tx_data|wr_ptr [5])))) ) ) ) # ( \A_SPW_TOP|tx_data|Mux6~18_combout  & ( 
// !\A_SPW_TOP|tx_data|Mux6~15_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|Mux6~16_combout  & ((\A_SPW_TOP|tx_data|wr_ptr [5])))) # (\A_SPW_TOP|tx_data|wr_ptr [4] & (((\A_SPW_TOP|tx_data|wr_ptr [5]) # 
// (\A_SPW_TOP|tx_data|Mux6~17_combout )))) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux6~18_combout  & ( !\A_SPW_TOP|tx_data|Mux6~15_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|Mux6~16_combout  & ((\A_SPW_TOP|tx_data|wr_ptr [5])))) # 
// (\A_SPW_TOP|tx_data|wr_ptr [4] & (((\A_SPW_TOP|tx_data|Mux6~17_combout  & !\A_SPW_TOP|tx_data|wr_ptr [5])))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux6~16_combout ),
        .datab(!\A_SPW_TOP|tx_data|Mux6~17_combout ),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datae(!\A_SPW_TOP|tx_data|Mux6~18_combout ),
        .dataf(!\A_SPW_TOP|tx_data|Mux6~15_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux6~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux6~19 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux6~19 .lut_mask = 64'h0350035FF350F35F;
defparam \A_SPW_TOP|tx_data|Mux6~19 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y11_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector353~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector353~0_combout  = ( \A_SPW_TOP|tx_data|Mux6~20_combout  & ( (!\A_SPW_TOP|tx_data|Selector347~0_combout  & (((\A_SPW_TOP|tx_data|mem[38][2]~q )))) # (\A_SPW_TOP|tx_data|Selector347~0_combout  & 
// ((!\A_SPW_TOP|tx_data|state_data_write.00~q ) # ((\u0|write_data_fifo_tx|data_out [2])))) ) ) # ( !\A_SPW_TOP|tx_data|Mux6~20_combout  & ( (!\A_SPW_TOP|tx_data|Selector347~0_combout  & (((\A_SPW_TOP|tx_data|mem[38][2]~q )))) # 
// (\A_SPW_TOP|tx_data|Selector347~0_combout  & (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [2]))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Selector347~0_combout ),
        .datac(!\u0|write_data_fifo_tx|data_out [2]),
        .datad(!\A_SPW_TOP|tx_data|mem[38][2]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector353~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector353~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector353~0 .lut_mask = 64'h01CD01CD23EF23EF;
defparam \A_SPW_TOP|tx_data|Selector353~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X45_Y11_N23
dffeas \A_SPW_TOP|tx_data|mem[38][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector353~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[38][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[38][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[38][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y12_N27
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector425~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector425~0_combout  = ( \A_SPW_TOP|tx_data|mem[46][2]~q  & ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector419~0_combout ) # (\u0|write_data_fifo_tx|data_out [2]) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|mem[46][2]~q  & ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (\A_SPW_TOP|tx_data|Selector419~0_combout  & \u0|write_data_fifo_tx|data_out [2]) ) ) ) # ( \A_SPW_TOP|tx_data|mem[46][2]~q  & ( !\A_SPW_TOP|tx_data|state_data_write.00~q  
// & ( (!\A_SPW_TOP|tx_data|Selector419~0_combout ) # (\A_SPW_TOP|tx_data|Mux6~20_combout ) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[46][2]~q  & ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( (\A_SPW_TOP|tx_data|Selector419~0_combout  & 
// \A_SPW_TOP|tx_data|Mux6~20_combout ) ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|tx_data|Selector419~0_combout ),
        .datac(!\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [2]),
        .datae(!\A_SPW_TOP|tx_data|mem[46][2]~q ),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector425~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector425~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector425~0 .lut_mask = 64'h0303CFCF0033CCFF;
defparam \A_SPW_TOP|tx_data|Selector425~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y12_N59
dffeas \A_SPW_TOP|tx_data|mem[46][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector425~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[46][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[46][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[46][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y12_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector65~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector65~0_combout  = ( \A_SPW_TOP|tx_data|mem[6][2]~q  & ( \A_SPW_TOP|tx_data|Mux6~20_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q ) # ((!\A_SPW_TOP|tx_data|Selector59~0_combout ) # (\u0|write_data_fifo_tx|data_out [2])) ) 
// ) ) # ( !\A_SPW_TOP|tx_data|mem[6][2]~q  & ( \A_SPW_TOP|tx_data|Mux6~20_combout  & ( (\A_SPW_TOP|tx_data|Selector59~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q ) # (\u0|write_data_fifo_tx|data_out [2]))) ) ) ) # ( 
// \A_SPW_TOP|tx_data|mem[6][2]~q  & ( !\A_SPW_TOP|tx_data|Mux6~20_combout  & ( (!\A_SPW_TOP|tx_data|Selector59~0_combout ) # ((\A_SPW_TOP|tx_data|state_data_write.00~q  & \u0|write_data_fifo_tx|data_out [2])) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[6][2]~q  & ( 
// !\A_SPW_TOP|tx_data|Mux6~20_combout  & ( (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [2] & \A_SPW_TOP|tx_data|Selector59~0_combout )) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\u0|write_data_fifo_tx|data_out [2]),
        .datac(gnd),
        .datad(!\A_SPW_TOP|tx_data|Selector59~0_combout ),
        .datae(!\A_SPW_TOP|tx_data|mem[6][2]~q ),
        .dataf(!\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector65~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector65~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector65~0 .lut_mask = 64'h0011FF1100BBFFBB;
defparam \A_SPW_TOP|tx_data|Selector65~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y12_N50
dffeas \A_SPW_TOP|tx_data|mem[6][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector65~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[6][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[6][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[6][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y12_N15
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector137~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector137~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector131~0_combout  & ((\A_SPW_TOP|tx_data|mem[14][2]~q ))) # (\A_SPW_TOP|tx_data|Selector131~0_combout  & (\u0|write_data_fifo_tx|data_out 
// [2])) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector131~0_combout  & ((\A_SPW_TOP|tx_data|mem[14][2]~q ))) # (\A_SPW_TOP|tx_data|Selector131~0_combout  & (\A_SPW_TOP|tx_data|Mux6~20_combout )) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [2]),
        .datab(!\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector131~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|mem[14][2]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector137~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector137~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector137~0 .lut_mask = 64'h03F303F305F505F5;
defparam \A_SPW_TOP|tx_data|Selector137~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y12_N29
dffeas \A_SPW_TOP|tx_data|mem[14][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector137~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[14][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[14][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[14][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y12_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux6~11 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux6~11_combout  = ( \A_SPW_TOP|tx_data|mem[14][2]~q  & ( \A_SPW_TOP|tx_data|wr_ptr [3] & ( (!\A_SPW_TOP|tx_data|wr_ptr [5]) # (\A_SPW_TOP|tx_data|mem[46][2]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[14][2]~q  & ( \A_SPW_TOP|tx_data|wr_ptr 
// [3] & ( (\A_SPW_TOP|tx_data|mem[46][2]~q  & \A_SPW_TOP|tx_data|wr_ptr [5]) ) ) ) # ( \A_SPW_TOP|tx_data|mem[14][2]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [3] & ( (!\A_SPW_TOP|tx_data|wr_ptr [5] & ((\A_SPW_TOP|tx_data|mem[6][2]~q ))) # 
// (\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|mem[38][2]~q )) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[14][2]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [3] & ( (!\A_SPW_TOP|tx_data|wr_ptr [5] & ((\A_SPW_TOP|tx_data|mem[6][2]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [5] 
// & (\A_SPW_TOP|tx_data|mem[38][2]~q )) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[38][2]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[46][2]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[6][2]~q ),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datae(!\A_SPW_TOP|tx_data|mem[14][2]~q ),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux6~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux6~11 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux6~11 .lut_mask = 64'h0F550F550033FF33;
defparam \A_SPW_TOP|tx_data|Mux6~11 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y12_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector389~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector389~0_combout  = ( \A_SPW_TOP|tx_data|mem[42][2]~q  & ( (!\A_SPW_TOP|tx_data|Selector383~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux6~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [2])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[42][2]~q  & ( (\A_SPW_TOP|tx_data|Selector383~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux6~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [2]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector383~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [2]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[42][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector389~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector389~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector389~0 .lut_mask = 64'h04070407F4F7F4F7;
defparam \A_SPW_TOP|tx_data|Selector389~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y12_N50
dffeas \A_SPW_TOP|tx_data|mem[42][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector389~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[42][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[42][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[42][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y12_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector29~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector29~0_combout  = ( \A_SPW_TOP|tx_data|mem[2][2]~q  & ( (!\A_SPW_TOP|tx_data|Selector23~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux6~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [2])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[2][2]~q  & ( (\A_SPW_TOP|tx_data|Selector23~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux6~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [2]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector23~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [2]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[2][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector29~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector29~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector29~0 .lut_mask = 64'h04070407F4F7F4F7;
defparam \A_SPW_TOP|tx_data|Selector29~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y12_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|mem[2][2]~feeder (
// Equation(s):
// \A_SPW_TOP|tx_data|mem[2][2]~feeder_combout  = ( \A_SPW_TOP|tx_data|Selector29~0_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector29~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|mem[2][2]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[2][2]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|mem[2][2]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|tx_data|mem[2][2]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y12_N32
dffeas \A_SPW_TOP|tx_data|mem[2][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|tx_data|mem[2][2]~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[2][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[2][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[2][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y12_N45
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector101~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector101~0_combout  = ( \A_SPW_TOP|tx_data|Selector95~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux6~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [2]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector95~0_combout  & ( \A_SPW_TOP|tx_data|mem[10][2]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[10][2]~q ),
        .datad(!\u0|write_data_fifo_tx|data_out [2]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector95~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector101~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector101~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector101~0 .lut_mask = 64'h0F0F0F0F44774477;
defparam \A_SPW_TOP|tx_data|Selector101~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y12_N8
dffeas \A_SPW_TOP|tx_data|mem[10][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector101~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[10][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[10][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[10][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y12_N57
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector317~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector317~0_combout  = ( \A_SPW_TOP|tx_data|mem[34][2]~q  & ( (!\A_SPW_TOP|tx_data|Selector311~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux6~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [2])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[34][2]~q  & ( (\A_SPW_TOP|tx_data|Selector311~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux6~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [2]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\u0|write_data_fifo_tx|data_out [2]),
        .datad(!\A_SPW_TOP|tx_data|Selector311~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[34][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector317~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector317~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector317~0 .lut_mask = 64'h00470047FF47FF47;
defparam \A_SPW_TOP|tx_data|Selector317~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y12_N41
dffeas \A_SPW_TOP|tx_data|mem[34][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector317~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[34][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[34][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[34][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y12_N9
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux6~10 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux6~10_combout  = ( \A_SPW_TOP|tx_data|mem[10][2]~q  & ( \A_SPW_TOP|tx_data|mem[34][2]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [5] & (((\A_SPW_TOP|tx_data|wr_ptr [3]) # (\A_SPW_TOP|tx_data|mem[2][2]~q )))) # (\A_SPW_TOP|tx_data|wr_ptr [5] & 
// (((!\A_SPW_TOP|tx_data|wr_ptr [3])) # (\A_SPW_TOP|tx_data|mem[42][2]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[10][2]~q  & ( \A_SPW_TOP|tx_data|mem[34][2]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [5] & (((\A_SPW_TOP|tx_data|mem[2][2]~q  & 
// !\A_SPW_TOP|tx_data|wr_ptr [3])))) # (\A_SPW_TOP|tx_data|wr_ptr [5] & (((!\A_SPW_TOP|tx_data|wr_ptr [3])) # (\A_SPW_TOP|tx_data|mem[42][2]~q ))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[10][2]~q  & ( !\A_SPW_TOP|tx_data|mem[34][2]~q  & ( 
// (!\A_SPW_TOP|tx_data|wr_ptr [5] & (((\A_SPW_TOP|tx_data|wr_ptr [3]) # (\A_SPW_TOP|tx_data|mem[2][2]~q )))) # (\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|mem[42][2]~q  & ((\A_SPW_TOP|tx_data|wr_ptr [3])))) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|mem[10][2]~q  & ( !\A_SPW_TOP|tx_data|mem[34][2]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [5] & (((\A_SPW_TOP|tx_data|mem[2][2]~q  & !\A_SPW_TOP|tx_data|wr_ptr [3])))) # (\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|mem[42][2]~q  & 
// ((\A_SPW_TOP|tx_data|wr_ptr [3])))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[42][2]~q ),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datac(!\A_SPW_TOP|tx_data|mem[2][2]~q ),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datae(!\A_SPW_TOP|tx_data|mem[10][2]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[34][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux6~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux6~10 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux6~10 .lut_mask = 64'h0C110CDD3F113FDD;
defparam \A_SPW_TOP|tx_data|Mux6~10 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y12_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector461~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector461~0_combout  = ( \A_SPW_TOP|tx_data|mem[50][2]~q  & ( (!\A_SPW_TOP|tx_data|Selector455~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux6~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [2])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[50][2]~q  & ( (\A_SPW_TOP|tx_data|Selector455~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux6~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [2]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [2]),
        .datac(!\A_SPW_TOP|tx_data|Selector455~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[50][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector461~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector461~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector461~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|tx_data|Selector461~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y12_N11
dffeas \A_SPW_TOP|tx_data|mem[50][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector461~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[50][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[50][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[50][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y10_N27
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector173~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector173~0_combout  = ( \A_SPW_TOP|tx_data|mem[18][2]~q  & ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector167~0_combout ) # (\u0|write_data_fifo_tx|data_out [2]) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|mem[18][2]~q  & ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (\u0|write_data_fifo_tx|data_out [2] & \A_SPW_TOP|tx_data|Selector167~0_combout ) ) ) ) # ( \A_SPW_TOP|tx_data|mem[18][2]~q  & ( !\A_SPW_TOP|tx_data|state_data_write.00~q  
// & ( (!\A_SPW_TOP|tx_data|Selector167~0_combout ) # (\A_SPW_TOP|tx_data|Mux6~20_combout ) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[18][2]~q  & ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( (\A_SPW_TOP|tx_data|Mux6~20_combout  & 
// \A_SPW_TOP|tx_data|Selector167~0_combout ) ) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [2]),
        .datab(!\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector167~0_combout ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|tx_data|mem[18][2]~q ),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector173~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector173~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector173~0 .lut_mask = 64'h0303F3F30505F5F5;
defparam \A_SPW_TOP|tx_data|Selector173~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X45_Y10_N56
dffeas \A_SPW_TOP|tx_data|mem[18][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector173~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[18][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[18][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[18][2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y10_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector533~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector533~0_combout  = ( \A_SPW_TOP|tx_data|mem[58][2]~q  & ( (!\A_SPW_TOP|tx_data|Selector527~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux6~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [2])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[58][2]~q  & ( (\A_SPW_TOP|tx_data|Selector527~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux6~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [2]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector527~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [2]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[58][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector533~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector533~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector533~0 .lut_mask = 64'h04070407F4F7F4F7;
defparam \A_SPW_TOP|tx_data|Selector533~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y10_N26
dffeas \A_SPW_TOP|tx_data|mem[58][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector533~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[58][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[58][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[58][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X51_Y10_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector245~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector245~0_combout  = ( \A_SPW_TOP|tx_data|mem[26][2]~q  & ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector239~0_combout ) # (\u0|write_data_fifo_tx|data_out [2]) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|mem[26][2]~q  & ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (\A_SPW_TOP|tx_data|Selector239~0_combout  & \u0|write_data_fifo_tx|data_out [2]) ) ) ) # ( \A_SPW_TOP|tx_data|mem[26][2]~q  & ( !\A_SPW_TOP|tx_data|state_data_write.00~q  
// & ( (!\A_SPW_TOP|tx_data|Selector239~0_combout ) # (\A_SPW_TOP|tx_data|Mux6~20_combout ) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[26][2]~q  & ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( (\A_SPW_TOP|tx_data|Mux6~20_combout  & 
// \A_SPW_TOP|tx_data|Selector239~0_combout ) ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector239~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [2]),
        .datae(!\A_SPW_TOP|tx_data|mem[26][2]~q ),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector245~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector245~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector245~0 .lut_mask = 64'h0303F3F3000FF0FF;
defparam \A_SPW_TOP|tx_data|Selector245~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y10_N8
dffeas \A_SPW_TOP|tx_data|mem[26][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector245~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[26][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[26][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[26][2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y10_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux6~12 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux6~12_combout  = ( \A_SPW_TOP|tx_data|mem[58][2]~q  & ( \A_SPW_TOP|tx_data|mem[26][2]~q  & ( ((!\A_SPW_TOP|tx_data|wr_ptr [5] & ((\A_SPW_TOP|tx_data|mem[18][2]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|mem[50][2]~q 
// ))) # (\A_SPW_TOP|tx_data|wr_ptr [3]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[58][2]~q  & ( \A_SPW_TOP|tx_data|mem[26][2]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [3] & ((!\A_SPW_TOP|tx_data|wr_ptr [5] & ((\A_SPW_TOP|tx_data|mem[18][2]~q ))) # 
// (\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|mem[50][2]~q )))) # (\A_SPW_TOP|tx_data|wr_ptr [3] & (((!\A_SPW_TOP|tx_data|wr_ptr [5])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[58][2]~q  & ( !\A_SPW_TOP|tx_data|mem[26][2]~q  & ( 
// (!\A_SPW_TOP|tx_data|wr_ptr [3] & ((!\A_SPW_TOP|tx_data|wr_ptr [5] & ((\A_SPW_TOP|tx_data|mem[18][2]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|mem[50][2]~q )))) # (\A_SPW_TOP|tx_data|wr_ptr [3] & (((\A_SPW_TOP|tx_data|wr_ptr [5])))) ) ) 
// ) # ( !\A_SPW_TOP|tx_data|mem[58][2]~q  & ( !\A_SPW_TOP|tx_data|mem[26][2]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [3] & ((!\A_SPW_TOP|tx_data|wr_ptr [5] & ((\A_SPW_TOP|tx_data|mem[18][2]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [5] & 
// (\A_SPW_TOP|tx_data|mem[50][2]~q )))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[50][2]~q ),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datac(!\A_SPW_TOP|tx_data|mem[18][2]~q ),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datae(!\A_SPW_TOP|tx_data|mem[58][2]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[26][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux6~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux6~12 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux6~12 .lut_mask = 64'h0C440C773F443F77;
defparam \A_SPW_TOP|tx_data|Mux6~12 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y12_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector497~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector497~0_combout  = ( \A_SPW_TOP|tx_data|mem[54][2]~q  & ( (!\A_SPW_TOP|tx_data|Selector491~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux6~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [2]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[54][2]~q  & ( (\A_SPW_TOP|tx_data|Selector491~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux6~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [2])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [2]),
        .datab(!\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector491~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[54][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector497~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector497~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector497~0 .lut_mask = 64'h03050305F3F5F3F5;
defparam \A_SPW_TOP|tx_data|Selector497~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y12_N26
dffeas \A_SPW_TOP|tx_data|mem[54][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector497~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[54][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[54][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[54][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y12_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector281~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector281~0_combout  = ( \u0|write_data_fifo_tx|data_out [2] & ( \A_SPW_TOP|tx_data|mem[30][2]~q  & ( (!\A_SPW_TOP|tx_data|Selector275~0_combout ) # ((\A_SPW_TOP|tx_data|state_data_write.00~q ) # (\A_SPW_TOP|tx_data|Mux6~20_combout )) 
// ) ) ) # ( !\u0|write_data_fifo_tx|data_out [2] & ( \A_SPW_TOP|tx_data|mem[30][2]~q  & ( (!\A_SPW_TOP|tx_data|Selector275~0_combout ) # ((\A_SPW_TOP|tx_data|Mux6~20_combout  & !\A_SPW_TOP|tx_data|state_data_write.00~q )) ) ) ) # ( 
// \u0|write_data_fifo_tx|data_out [2] & ( !\A_SPW_TOP|tx_data|mem[30][2]~q  & ( (\A_SPW_TOP|tx_data|Selector275~0_combout  & ((\A_SPW_TOP|tx_data|state_data_write.00~q ) # (\A_SPW_TOP|tx_data|Mux6~20_combout ))) ) ) ) # ( !\u0|write_data_fifo_tx|data_out 
// [2] & ( !\A_SPW_TOP|tx_data|mem[30][2]~q  & ( (\A_SPW_TOP|tx_data|Selector275~0_combout  & (\A_SPW_TOP|tx_data|Mux6~20_combout  & !\A_SPW_TOP|tx_data|state_data_write.00~q )) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Selector275~0_combout ),
        .datab(!\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(gnd),
        .datae(!\u0|write_data_fifo_tx|data_out [2]),
        .dataf(!\A_SPW_TOP|tx_data|mem[30][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector281~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector281~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector281~0 .lut_mask = 64'h10101515BABABFBF;
defparam \A_SPW_TOP|tx_data|Selector281~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y12_N32
dffeas \A_SPW_TOP|tx_data|mem[30][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector281~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[30][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[30][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[30][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y12_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector569~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector569~0_combout  = ( \A_SPW_TOP|tx_data|mem[62][2]~q  & ( (!\A_SPW_TOP|tx_data|Selector563~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux6~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [2]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[62][2]~q  & ( (\A_SPW_TOP|tx_data|Selector563~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux6~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [2])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [2]),
        .datab(!\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|tx_data|Selector563~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[62][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector569~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector569~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector569~0 .lut_mask = 64'h00350035FF35FF35;
defparam \A_SPW_TOP|tx_data|Selector569~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y12_N20
dffeas \A_SPW_TOP|tx_data|mem[62][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector569~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[62][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[62][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[62][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y12_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector209~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector209~0_combout  = ( \A_SPW_TOP|tx_data|mem[22][2]~q  & ( (!\A_SPW_TOP|tx_data|Selector203~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux6~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [2]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[22][2]~q  & ( (\A_SPW_TOP|tx_data|Selector203~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux6~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [2])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [2]),
        .datab(!\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector203~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[22][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector209~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector209~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector209~0 .lut_mask = 64'h03050305F3F5F3F5;
defparam \A_SPW_TOP|tx_data|Selector209~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y12_N35
dffeas \A_SPW_TOP|tx_data|mem[22][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector209~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[22][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[22][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[22][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y12_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux6~13 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux6~13_combout  = ( \A_SPW_TOP|tx_data|mem[62][2]~q  & ( \A_SPW_TOP|tx_data|mem[22][2]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [3] & (((!\A_SPW_TOP|tx_data|wr_ptr [5])) # (\A_SPW_TOP|tx_data|mem[54][2]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [3] 
// & (((\A_SPW_TOP|tx_data|wr_ptr [5]) # (\A_SPW_TOP|tx_data|mem[30][2]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[62][2]~q  & ( \A_SPW_TOP|tx_data|mem[22][2]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [3] & (((!\A_SPW_TOP|tx_data|wr_ptr [5])) # 
// (\A_SPW_TOP|tx_data|mem[54][2]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [3] & (((\A_SPW_TOP|tx_data|mem[30][2]~q  & !\A_SPW_TOP|tx_data|wr_ptr [5])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[62][2]~q  & ( !\A_SPW_TOP|tx_data|mem[22][2]~q  & ( 
// (!\A_SPW_TOP|tx_data|wr_ptr [3] & (\A_SPW_TOP|tx_data|mem[54][2]~q  & ((\A_SPW_TOP|tx_data|wr_ptr [5])))) # (\A_SPW_TOP|tx_data|wr_ptr [3] & (((\A_SPW_TOP|tx_data|wr_ptr [5]) # (\A_SPW_TOP|tx_data|mem[30][2]~q )))) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|mem[62][2]~q  & ( !\A_SPW_TOP|tx_data|mem[22][2]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [3] & (\A_SPW_TOP|tx_data|mem[54][2]~q  & ((\A_SPW_TOP|tx_data|wr_ptr [5])))) # (\A_SPW_TOP|tx_data|wr_ptr [3] & (((\A_SPW_TOP|tx_data|mem[30][2]~q  & 
// !\A_SPW_TOP|tx_data|wr_ptr [5])))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[54][2]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[30][2]~q ),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datae(!\A_SPW_TOP|tx_data|mem[62][2]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[22][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux6~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux6~13 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux6~13 .lut_mask = 64'h0350035FF350F35F;
defparam \A_SPW_TOP|tx_data|Mux6~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y12_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux6~14 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux6~14_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [2] & ( \A_SPW_TOP|tx_data|Mux6~13_combout  & ( (\A_SPW_TOP|tx_data|wr_ptr [4]) # (\A_SPW_TOP|tx_data|Mux6~11_combout ) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [2] & ( 
// \A_SPW_TOP|tx_data|Mux6~13_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|Mux6~10_combout )) # (\A_SPW_TOP|tx_data|wr_ptr [4] & ((\A_SPW_TOP|tx_data|Mux6~12_combout ))) ) ) ) # ( \A_SPW_TOP|tx_data|wr_ptr [2] & ( 
// !\A_SPW_TOP|tx_data|Mux6~13_combout  & ( (\A_SPW_TOP|tx_data|Mux6~11_combout  & !\A_SPW_TOP|tx_data|wr_ptr [4]) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [2] & ( !\A_SPW_TOP|tx_data|Mux6~13_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & 
// (\A_SPW_TOP|tx_data|Mux6~10_combout )) # (\A_SPW_TOP|tx_data|wr_ptr [4] & ((\A_SPW_TOP|tx_data|Mux6~12_combout ))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux6~11_combout ),
        .datab(!\A_SPW_TOP|tx_data|Mux6~10_combout ),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datad(!\A_SPW_TOP|tx_data|Mux6~12_combout ),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .dataf(!\A_SPW_TOP|tx_data|Mux6~13_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux6~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux6~14 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux6~14 .lut_mask = 64'h303F5050303F5F5F;
defparam \A_SPW_TOP|tx_data|Mux6~14 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y12_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux6~20 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux6~20_combout  = ( \A_SPW_TOP|tx_data|Mux6~19_combout  & ( \A_SPW_TOP|tx_data|Mux6~14_combout  & ( ((!\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|Mux6~4_combout )) # (\A_SPW_TOP|tx_data|wr_ptr [0] & 
// ((\A_SPW_TOP|tx_data|Mux6~9_combout )))) # (\A_SPW_TOP|tx_data|wr_ptr [1]) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux6~19_combout  & ( \A_SPW_TOP|tx_data|Mux6~14_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & (((\A_SPW_TOP|tx_data|wr_ptr [1])) # 
// (\A_SPW_TOP|tx_data|Mux6~4_combout ))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & (((\A_SPW_TOP|tx_data|Mux6~9_combout  & !\A_SPW_TOP|tx_data|wr_ptr [1])))) ) ) ) # ( \A_SPW_TOP|tx_data|Mux6~19_combout  & ( !\A_SPW_TOP|tx_data|Mux6~14_combout  & ( 
// (!\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|Mux6~4_combout  & ((!\A_SPW_TOP|tx_data|wr_ptr [1])))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & (((\A_SPW_TOP|tx_data|wr_ptr [1]) # (\A_SPW_TOP|tx_data|Mux6~9_combout )))) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|Mux6~19_combout  & ( !\A_SPW_TOP|tx_data|Mux6~14_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [1] & ((!\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|Mux6~4_combout )) # (\A_SPW_TOP|tx_data|wr_ptr [0] & 
// ((\A_SPW_TOP|tx_data|Mux6~9_combout ))))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux6~4_combout ),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datac(!\A_SPW_TOP|tx_data|Mux6~9_combout ),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datae(!\A_SPW_TOP|tx_data|Mux6~19_combout ),
        .dataf(!\A_SPW_TOP|tx_data|Mux6~14_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux6~20 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux6~20 .lut_mask = 64'h4700473347CC47FF;
defparam \A_SPW_TOP|tx_data|Mux6~20 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y12_N27
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector20~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector20~0_combout  = ( \A_SPW_TOP|tx_data|Selector14~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux6~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out 
// [2]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector14~0_combout  & ( \A_SPW_TOP|tx_data|mem[1][2]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux6~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\u0|write_data_fifo_tx|data_out [2]),
        .datad(!\A_SPW_TOP|tx_data|mem[1][2]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector14~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector20~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector20~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector20~0 .lut_mask = 64'h00FF00FF47474747;
defparam \A_SPW_TOP|tx_data|Selector20~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y12_N38
dffeas \A_SPW_TOP|tx_data|mem[1][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector20~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[1][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[1][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[1][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y12_N21
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux15~10 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux15~10_combout  = ( \A_SPW_TOP|tx_data|rd_ptr [3] & ( \A_SPW_TOP|tx_data|mem[9][2]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5]) # (\A_SPW_TOP|tx_data|mem[41][2]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [3] & ( 
// \A_SPW_TOP|tx_data|mem[9][2]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|mem[1][2]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [5] & ((\A_SPW_TOP|tx_data|mem[33][2]~q ))) ) ) ) # ( \A_SPW_TOP|tx_data|rd_ptr [3] & ( !\A_SPW_TOP|tx_data|mem[9][2]~q  
// & ( (\A_SPW_TOP|tx_data|mem[41][2]~q  & \A_SPW_TOP|tx_data|rd_ptr [5]) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [3] & ( !\A_SPW_TOP|tx_data|mem[9][2]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|mem[1][2]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [5] 
// & ((\A_SPW_TOP|tx_data|mem[33][2]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[1][2]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[41][2]~q ),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [5]),
        .datad(!\A_SPW_TOP|tx_data|mem[33][2]~q ),
        .datae(!\A_SPW_TOP|tx_data|rd_ptr [3]),
        .dataf(!\A_SPW_TOP|tx_data|mem[9][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux15~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux15~10 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux15~10 .lut_mask = 64'h505F0303505FF3F3;
defparam \A_SPW_TOP|tx_data|Mux15~10 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y12_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux15~13 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux15~13_combout  = ( \A_SPW_TOP|tx_data|mem[15][2]~q  & ( \A_SPW_TOP|tx_data|mem[39][2]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & (((\A_SPW_TOP|tx_data|rd_ptr [3]) # (\A_SPW_TOP|tx_data|mem[7][2]~q )))) # (\A_SPW_TOP|tx_data|rd_ptr [5] 
// & (((!\A_SPW_TOP|tx_data|rd_ptr [3])) # (\A_SPW_TOP|tx_data|mem[47][2]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[15][2]~q  & ( \A_SPW_TOP|tx_data|mem[39][2]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & (((\A_SPW_TOP|tx_data|mem[7][2]~q  & 
// !\A_SPW_TOP|tx_data|rd_ptr [3])))) # (\A_SPW_TOP|tx_data|rd_ptr [5] & (((!\A_SPW_TOP|tx_data|rd_ptr [3])) # (\A_SPW_TOP|tx_data|mem[47][2]~q ))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[15][2]~q  & ( !\A_SPW_TOP|tx_data|mem[39][2]~q  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [5] & (((\A_SPW_TOP|tx_data|rd_ptr [3]) # (\A_SPW_TOP|tx_data|mem[7][2]~q )))) # (\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|mem[47][2]~q  & ((\A_SPW_TOP|tx_data|rd_ptr [3])))) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|mem[15][2]~q  & ( !\A_SPW_TOP|tx_data|mem[39][2]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & (((\A_SPW_TOP|tx_data|mem[7][2]~q  & !\A_SPW_TOP|tx_data|rd_ptr [3])))) # (\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|mem[47][2]~q  & 
// ((\A_SPW_TOP|tx_data|rd_ptr [3])))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[47][2]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[7][2]~q ),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [5]),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [3]),
        .datae(!\A_SPW_TOP|tx_data|mem[15][2]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[39][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux15~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux15~13 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux15~13 .lut_mask = 64'h300530F53F053FF5;
defparam \A_SPW_TOP|tx_data|Mux15~13 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y12_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux15~12 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux15~12_combout  = ( \A_SPW_TOP|tx_data|mem[43][2]~q  & ( \A_SPW_TOP|tx_data|mem[35][2]~q  & ( ((!\A_SPW_TOP|tx_data|rd_ptr [3] & ((\A_SPW_TOP|tx_data|mem[3][2]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [3] & (\A_SPW_TOP|tx_data|mem[11][2]~q 
// ))) # (\A_SPW_TOP|tx_data|rd_ptr [5]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[43][2]~q  & ( \A_SPW_TOP|tx_data|mem[35][2]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & ((!\A_SPW_TOP|tx_data|rd_ptr [3] & ((\A_SPW_TOP|tx_data|mem[3][2]~q ))) # 
// (\A_SPW_TOP|tx_data|rd_ptr [3] & (\A_SPW_TOP|tx_data|mem[11][2]~q )))) # (\A_SPW_TOP|tx_data|rd_ptr [5] & (!\A_SPW_TOP|tx_data|rd_ptr [3])) ) ) ) # ( \A_SPW_TOP|tx_data|mem[43][2]~q  & ( !\A_SPW_TOP|tx_data|mem[35][2]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr 
// [5] & ((!\A_SPW_TOP|tx_data|rd_ptr [3] & ((\A_SPW_TOP|tx_data|mem[3][2]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [3] & (\A_SPW_TOP|tx_data|mem[11][2]~q )))) # (\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|rd_ptr [3])) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|mem[43][2]~q  & ( !\A_SPW_TOP|tx_data|mem[35][2]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & ((!\A_SPW_TOP|tx_data|rd_ptr [3] & ((\A_SPW_TOP|tx_data|mem[3][2]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [3] & (\A_SPW_TOP|tx_data|mem[11][2]~q )))) 
// ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [5]),
        .datab(!\A_SPW_TOP|tx_data|rd_ptr [3]),
        .datac(!\A_SPW_TOP|tx_data|mem[11][2]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[3][2]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[43][2]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[35][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux15~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux15~12 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux15~12 .lut_mask = 64'h028A139B46CE57DF;
defparam \A_SPW_TOP|tx_data|Mux15~12 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y10_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux15~11 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux15~11_combout  = ( \A_SPW_TOP|tx_data|mem[5][2]~q  & ( \A_SPW_TOP|tx_data|mem[13][2]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5]) # ((!\A_SPW_TOP|tx_data|rd_ptr [3] & ((\A_SPW_TOP|tx_data|mem[37][2]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [3] 
// & (\A_SPW_TOP|tx_data|mem[45][2]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[5][2]~q  & ( \A_SPW_TOP|tx_data|mem[13][2]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & (((\A_SPW_TOP|tx_data|rd_ptr [3])))) # (\A_SPW_TOP|tx_data|rd_ptr [5] & 
// ((!\A_SPW_TOP|tx_data|rd_ptr [3] & ((\A_SPW_TOP|tx_data|mem[37][2]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [3] & (\A_SPW_TOP|tx_data|mem[45][2]~q )))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[5][2]~q  & ( !\A_SPW_TOP|tx_data|mem[13][2]~q  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [5] & (((!\A_SPW_TOP|tx_data|rd_ptr [3])))) # (\A_SPW_TOP|tx_data|rd_ptr [5] & ((!\A_SPW_TOP|tx_data|rd_ptr [3] & ((\A_SPW_TOP|tx_data|mem[37][2]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [3] & (\A_SPW_TOP|tx_data|mem[45][2]~q )))) ) 
// ) ) # ( !\A_SPW_TOP|tx_data|mem[5][2]~q  & ( !\A_SPW_TOP|tx_data|mem[13][2]~q  & ( (\A_SPW_TOP|tx_data|rd_ptr [5] & ((!\A_SPW_TOP|tx_data|rd_ptr [3] & ((\A_SPW_TOP|tx_data|mem[37][2]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [3] & 
// (\A_SPW_TOP|tx_data|mem[45][2]~q )))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[45][2]~q ),
        .datab(!\A_SPW_TOP|tx_data|rd_ptr [5]),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [3]),
        .datad(!\A_SPW_TOP|tx_data|mem[37][2]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[5][2]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[13][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux15~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux15~11 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux15~11 .lut_mask = 64'h0131C1F10D3DCDFD;
defparam \A_SPW_TOP|tx_data|Mux15~11 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y12_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux15~14 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux15~14_combout  = ( \A_SPW_TOP|tx_data|rd_ptr [2] & ( \A_SPW_TOP|tx_data|Mux15~11_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [1]) # (\A_SPW_TOP|tx_data|Mux15~13_combout ) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [2] & ( 
// \A_SPW_TOP|tx_data|Mux15~11_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|Mux15~10_combout )) # (\A_SPW_TOP|tx_data|rd_ptr [1] & ((\A_SPW_TOP|tx_data|Mux15~12_combout ))) ) ) ) # ( \A_SPW_TOP|tx_data|rd_ptr [2] & ( 
// !\A_SPW_TOP|tx_data|Mux15~11_combout  & ( (\A_SPW_TOP|tx_data|Mux15~13_combout  & \A_SPW_TOP|tx_data|rd_ptr [1]) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [2] & ( !\A_SPW_TOP|tx_data|Mux15~11_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [1] & 
// (\A_SPW_TOP|tx_data|Mux15~10_combout )) # (\A_SPW_TOP|tx_data|rd_ptr [1] & ((\A_SPW_TOP|tx_data|Mux15~12_combout ))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux15~10_combout ),
        .datab(!\A_SPW_TOP|tx_data|Mux15~13_combout ),
        .datac(!\A_SPW_TOP|tx_data|Mux15~12_combout ),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .datae(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .dataf(!\A_SPW_TOP|tx_data|Mux15~11_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux15~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux15~14 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux15~14 .lut_mask = 64'h550F0033550FFF33;
defparam \A_SPW_TOP|tx_data|Mux15~14 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y10_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux15~16 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux15~16_combout  = ( \A_SPW_TOP|tx_data|mem[55][2]~q  & ( \A_SPW_TOP|tx_data|rd_ptr [1] & ( (\A_SPW_TOP|tx_data|rd_ptr [2]) # (\A_SPW_TOP|tx_data|mem[51][2]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[55][2]~q  & ( \A_SPW_TOP|tx_data|rd_ptr 
// [1] & ( (\A_SPW_TOP|tx_data|mem[51][2]~q  & !\A_SPW_TOP|tx_data|rd_ptr [2]) ) ) ) # ( \A_SPW_TOP|tx_data|mem[55][2]~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [1] & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[49][2]~q )) # 
// (\A_SPW_TOP|tx_data|rd_ptr [2] & ((\A_SPW_TOP|tx_data|mem[53][2]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[55][2]~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [1] & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[49][2]~q )) # (\A_SPW_TOP|tx_data|rd_ptr 
// [2] & ((\A_SPW_TOP|tx_data|mem[53][2]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[51][2]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[49][2]~q ),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .datad(!\A_SPW_TOP|tx_data|mem[53][2]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[55][2]~q ),
        .dataf(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux15~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux15~16 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux15~16 .lut_mask = 64'h303F303F50505F5F;
defparam \A_SPW_TOP|tx_data|Mux15~16 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y10_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux15~15 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux15~15_combout  = ( \A_SPW_TOP|tx_data|mem[19][2]~q  & ( \A_SPW_TOP|tx_data|mem[23][2]~q  & ( ((!\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[17][2]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [2] & ((\A_SPW_TOP|tx_data|mem[21][2]~q 
// )))) # (\A_SPW_TOP|tx_data|rd_ptr [1]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[19][2]~q  & ( \A_SPW_TOP|tx_data|mem[23][2]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [1] & ((!\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[17][2]~q )) # 
// (\A_SPW_TOP|tx_data|rd_ptr [2] & ((\A_SPW_TOP|tx_data|mem[21][2]~q ))))) # (\A_SPW_TOP|tx_data|rd_ptr [1] & (((\A_SPW_TOP|tx_data|rd_ptr [2])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[19][2]~q  & ( !\A_SPW_TOP|tx_data|mem[23][2]~q  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [1] & ((!\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[17][2]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [2] & ((\A_SPW_TOP|tx_data|mem[21][2]~q ))))) # (\A_SPW_TOP|tx_data|rd_ptr [1] & (((!\A_SPW_TOP|tx_data|rd_ptr [2])))) ) 
// ) ) # ( !\A_SPW_TOP|tx_data|mem[19][2]~q  & ( !\A_SPW_TOP|tx_data|mem[23][2]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [1] & ((!\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[17][2]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [2] & 
// ((\A_SPW_TOP|tx_data|mem[21][2]~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[17][2]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[21][2]~q ),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .datae(!\A_SPW_TOP|tx_data|mem[19][2]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[23][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux15~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux15~15 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux15~15 .lut_mask = 64'h50305F30503F5F3F;
defparam \A_SPW_TOP|tx_data|Mux15~15 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y10_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux15~18 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux15~18_combout  = ( \A_SPW_TOP|tx_data|rd_ptr [2] & ( \A_SPW_TOP|tx_data|rd_ptr [1] & ( \A_SPW_TOP|tx_data|mem[63][2]~q  ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [2] & ( \A_SPW_TOP|tx_data|rd_ptr [1] & ( \A_SPW_TOP|tx_data|mem[59][2]~q  ) 
// ) ) # ( \A_SPW_TOP|tx_data|rd_ptr [2] & ( !\A_SPW_TOP|tx_data|rd_ptr [1] & ( \A_SPW_TOP|tx_data|mem[61][2]~q  ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [2] & ( !\A_SPW_TOP|tx_data|rd_ptr [1] & ( \A_SPW_TOP|tx_data|mem[57][2]~q  ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[57][2]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[63][2]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[59][2]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[61][2]~q ),
        .datae(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .dataf(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux15~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux15~18 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux15~18 .lut_mask = 64'h555500FF0F0F3333;
defparam \A_SPW_TOP|tx_data|Mux15~18 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y10_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux15~17 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux15~17_combout  = ( \A_SPW_TOP|tx_data|mem[27][2]~q  & ( \A_SPW_TOP|tx_data|rd_ptr [1] & ( (!\A_SPW_TOP|tx_data|rd_ptr [2]) # (\A_SPW_TOP|tx_data|mem[31][2]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[27][2]~q  & ( \A_SPW_TOP|tx_data|rd_ptr 
// [1] & ( (\A_SPW_TOP|tx_data|mem[31][2]~q  & \A_SPW_TOP|tx_data|rd_ptr [2]) ) ) ) # ( \A_SPW_TOP|tx_data|mem[27][2]~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [1] & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & ((\A_SPW_TOP|tx_data|mem[25][2]~q ))) # 
// (\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[29][2]~q )) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[27][2]~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [1] & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & ((\A_SPW_TOP|tx_data|mem[25][2]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr 
// [2] & (\A_SPW_TOP|tx_data|mem[29][2]~q )) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[31][2]~q ),
        .datab(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .datac(!\A_SPW_TOP|tx_data|mem[29][2]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[25][2]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[27][2]~q ),
        .dataf(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux15~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux15~17 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux15~17 .lut_mask = 64'h03CF03CF1111DDDD;
defparam \A_SPW_TOP|tx_data|Mux15~17 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y10_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux15~19 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux15~19_combout  = ( \A_SPW_TOP|tx_data|Mux15~18_combout  & ( \A_SPW_TOP|tx_data|Mux15~17_combout  & ( ((!\A_SPW_TOP|tx_data|rd_ptr [5] & ((\A_SPW_TOP|tx_data|Mux15~15_combout ))) # (\A_SPW_TOP|tx_data|rd_ptr [5] & 
// (\A_SPW_TOP|tx_data|Mux15~16_combout ))) # (\A_SPW_TOP|tx_data|rd_ptr [3]) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux15~18_combout  & ( \A_SPW_TOP|tx_data|Mux15~17_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [3] & ((!\A_SPW_TOP|tx_data|rd_ptr [5] & 
// ((\A_SPW_TOP|tx_data|Mux15~15_combout ))) # (\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|Mux15~16_combout )))) # (\A_SPW_TOP|tx_data|rd_ptr [3] & (((!\A_SPW_TOP|tx_data|rd_ptr [5])))) ) ) ) # ( \A_SPW_TOP|tx_data|Mux15~18_combout  & ( 
// !\A_SPW_TOP|tx_data|Mux15~17_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [3] & ((!\A_SPW_TOP|tx_data|rd_ptr [5] & ((\A_SPW_TOP|tx_data|Mux15~15_combout ))) # (\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|Mux15~16_combout )))) # 
// (\A_SPW_TOP|tx_data|rd_ptr [3] & (((\A_SPW_TOP|tx_data|rd_ptr [5])))) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux15~18_combout  & ( !\A_SPW_TOP|tx_data|Mux15~17_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [3] & ((!\A_SPW_TOP|tx_data|rd_ptr [5] & 
// ((\A_SPW_TOP|tx_data|Mux15~15_combout ))) # (\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|Mux15~16_combout )))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [3]),
        .datab(!\A_SPW_TOP|tx_data|Mux15~16_combout ),
        .datac(!\A_SPW_TOP|tx_data|Mux15~15_combout ),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [5]),
        .datae(!\A_SPW_TOP|tx_data|Mux15~18_combout ),
        .dataf(!\A_SPW_TOP|tx_data|Mux15~17_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux15~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux15~19 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux15~19 .lut_mask = 64'h0A220A775F225F77;
defparam \A_SPW_TOP|tx_data|Mux15~19 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y12_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux15~3 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux15~3_combout  = ( \A_SPW_TOP|tx_data|mem[14][2]~q  & ( \A_SPW_TOP|tx_data|mem[38][2]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [3] & (((\A_SPW_TOP|tx_data|rd_ptr [5]) # (\A_SPW_TOP|tx_data|mem[6][2]~q )))) # (\A_SPW_TOP|tx_data|rd_ptr [3] & 
// (((!\A_SPW_TOP|tx_data|rd_ptr [5])) # (\A_SPW_TOP|tx_data|mem[46][2]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[14][2]~q  & ( \A_SPW_TOP|tx_data|mem[38][2]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [3] & (((\A_SPW_TOP|tx_data|rd_ptr [5]) # 
// (\A_SPW_TOP|tx_data|mem[6][2]~q )))) # (\A_SPW_TOP|tx_data|rd_ptr [3] & (\A_SPW_TOP|tx_data|mem[46][2]~q  & ((\A_SPW_TOP|tx_data|rd_ptr [5])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[14][2]~q  & ( !\A_SPW_TOP|tx_data|mem[38][2]~q  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [3] & (((\A_SPW_TOP|tx_data|mem[6][2]~q  & !\A_SPW_TOP|tx_data|rd_ptr [5])))) # (\A_SPW_TOP|tx_data|rd_ptr [3] & (((!\A_SPW_TOP|tx_data|rd_ptr [5])) # (\A_SPW_TOP|tx_data|mem[46][2]~q ))) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|mem[14][2]~q  & ( !\A_SPW_TOP|tx_data|mem[38][2]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [3] & (((\A_SPW_TOP|tx_data|mem[6][2]~q  & !\A_SPW_TOP|tx_data|rd_ptr [5])))) # (\A_SPW_TOP|tx_data|rd_ptr [3] & (\A_SPW_TOP|tx_data|mem[46][2]~q  & 
// ((\A_SPW_TOP|tx_data|rd_ptr [5])))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [3]),
        .datab(!\A_SPW_TOP|tx_data|mem[46][2]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[6][2]~q ),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [5]),
        .datae(!\A_SPW_TOP|tx_data|mem[14][2]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[38][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux15~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux15~3 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux15~3 .lut_mask = 64'h0A115F110ABB5FBB;
defparam \A_SPW_TOP|tx_data|Mux15~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y12_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux15~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux15~1_combout  = ( \A_SPW_TOP|tx_data|mem[12][2]~q  & ( \A_SPW_TOP|tx_data|mem[4][2]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5]) # ((!\A_SPW_TOP|tx_data|rd_ptr [3] & ((\A_SPW_TOP|tx_data|mem[36][2]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [3] & 
// (\A_SPW_TOP|tx_data|mem[44][2]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[12][2]~q  & ( \A_SPW_TOP|tx_data|mem[4][2]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & (((!\A_SPW_TOP|tx_data|rd_ptr [3])))) # (\A_SPW_TOP|tx_data|rd_ptr [5] & 
// ((!\A_SPW_TOP|tx_data|rd_ptr [3] & ((\A_SPW_TOP|tx_data|mem[36][2]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [3] & (\A_SPW_TOP|tx_data|mem[44][2]~q )))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[12][2]~q  & ( !\A_SPW_TOP|tx_data|mem[4][2]~q  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [5] & (((\A_SPW_TOP|tx_data|rd_ptr [3])))) # (\A_SPW_TOP|tx_data|rd_ptr [5] & ((!\A_SPW_TOP|tx_data|rd_ptr [3] & ((\A_SPW_TOP|tx_data|mem[36][2]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [3] & (\A_SPW_TOP|tx_data|mem[44][2]~q )))) ) ) 
// ) # ( !\A_SPW_TOP|tx_data|mem[12][2]~q  & ( !\A_SPW_TOP|tx_data|mem[4][2]~q  & ( (\A_SPW_TOP|tx_data|rd_ptr [5] & ((!\A_SPW_TOP|tx_data|rd_ptr [3] & ((\A_SPW_TOP|tx_data|mem[36][2]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [3] & (\A_SPW_TOP|tx_data|mem[44][2]~q 
// )))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [5]),
        .datab(!\A_SPW_TOP|tx_data|mem[44][2]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[36][2]~q ),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [3]),
        .datae(!\A_SPW_TOP|tx_data|mem[12][2]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[4][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux15~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux15~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux15~1 .lut_mask = 64'h051105BBAF11AFBB;
defparam \A_SPW_TOP|tx_data|Mux15~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y12_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux15~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux15~0_combout  = ( \A_SPW_TOP|tx_data|mem[0][2]~q  & ( \A_SPW_TOP|tx_data|mem[32][2]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [3]) # ((!\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|mem[8][2]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [5] & 
// ((\A_SPW_TOP|tx_data|mem[40][2]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[0][2]~q  & ( \A_SPW_TOP|tx_data|mem[32][2]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [3] & (((\A_SPW_TOP|tx_data|rd_ptr [5])))) # (\A_SPW_TOP|tx_data|rd_ptr [3] & 
// ((!\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|mem[8][2]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [5] & ((\A_SPW_TOP|tx_data|mem[40][2]~q ))))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[0][2]~q  & ( !\A_SPW_TOP|tx_data|mem[32][2]~q  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [3] & (((!\A_SPW_TOP|tx_data|rd_ptr [5])))) # (\A_SPW_TOP|tx_data|rd_ptr [3] & ((!\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|mem[8][2]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [5] & ((\A_SPW_TOP|tx_data|mem[40][2]~q ))))) ) ) 
// ) # ( !\A_SPW_TOP|tx_data|mem[0][2]~q  & ( !\A_SPW_TOP|tx_data|mem[32][2]~q  & ( (\A_SPW_TOP|tx_data|rd_ptr [3] & ((!\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|mem[8][2]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [5] & ((\A_SPW_TOP|tx_data|mem[40][2]~q 
// ))))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[8][2]~q ),
        .datab(!\A_SPW_TOP|tx_data|rd_ptr [3]),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [5]),
        .datad(!\A_SPW_TOP|tx_data|mem[40][2]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[0][2]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[32][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux15~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux15~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux15~0 .lut_mask = 64'h1013D0D31C1FDCDF;
defparam \A_SPW_TOP|tx_data|Mux15~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y12_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux15~2 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux15~2_combout  = ( \A_SPW_TOP|tx_data|rd_ptr [3] & ( \A_SPW_TOP|tx_data|mem[2][2]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & ((\A_SPW_TOP|tx_data|mem[10][2]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|mem[42][2]~q )) ) 
// ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [3] & ( \A_SPW_TOP|tx_data|mem[2][2]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5]) # (\A_SPW_TOP|tx_data|mem[34][2]~q ) ) ) ) # ( \A_SPW_TOP|tx_data|rd_ptr [3] & ( !\A_SPW_TOP|tx_data|mem[2][2]~q  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [5] & ((\A_SPW_TOP|tx_data|mem[10][2]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|mem[42][2]~q )) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [3] & ( !\A_SPW_TOP|tx_data|mem[2][2]~q  & ( 
// (\A_SPW_TOP|tx_data|mem[34][2]~q  & \A_SPW_TOP|tx_data|rd_ptr [5]) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[42][2]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[34][2]~q ),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [5]),
        .datad(!\A_SPW_TOP|tx_data|mem[10][2]~q ),
        .datae(!\A_SPW_TOP|tx_data|rd_ptr [3]),
        .dataf(!\A_SPW_TOP|tx_data|mem[2][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux15~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux15~2 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux15~2 .lut_mask = 64'h030305F5F3F305F5;
defparam \A_SPW_TOP|tx_data|Mux15~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y12_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux15~4 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux15~4_combout  = ( \A_SPW_TOP|tx_data|Mux15~2_combout  & ( \A_SPW_TOP|tx_data|rd_ptr [1] & ( (!\A_SPW_TOP|tx_data|rd_ptr [2]) # (\A_SPW_TOP|tx_data|Mux15~3_combout ) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux15~2_combout  & ( 
// \A_SPW_TOP|tx_data|rd_ptr [1] & ( (\A_SPW_TOP|tx_data|Mux15~3_combout  & \A_SPW_TOP|tx_data|rd_ptr [2]) ) ) ) # ( \A_SPW_TOP|tx_data|Mux15~2_combout  & ( !\A_SPW_TOP|tx_data|rd_ptr [1] & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & 
// ((\A_SPW_TOP|tx_data|Mux15~0_combout ))) # (\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|Mux15~1_combout )) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux15~2_combout  & ( !\A_SPW_TOP|tx_data|rd_ptr [1] & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & 
// ((\A_SPW_TOP|tx_data|Mux15~0_combout ))) # (\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|Mux15~1_combout )) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux15~3_combout ),
        .datab(!\A_SPW_TOP|tx_data|Mux15~1_combout ),
        .datac(!\A_SPW_TOP|tx_data|Mux15~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .datae(!\A_SPW_TOP|tx_data|Mux15~2_combout ),
        .dataf(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux15~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux15~4 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux15~4 .lut_mask = 64'h0F330F330055FF55;
defparam \A_SPW_TOP|tx_data|Mux15~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y12_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux15~8 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux15~8_combout  = ( \A_SPW_TOP|tx_data|mem[30][2]~q  & ( \A_SPW_TOP|tx_data|mem[62][2]~q  & ( ((!\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|mem[22][2]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [5] & ((\A_SPW_TOP|tx_data|mem[54][2]~q 
// )))) # (\A_SPW_TOP|tx_data|rd_ptr [3]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[30][2]~q  & ( \A_SPW_TOP|tx_data|mem[62][2]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|mem[22][2]~q  & (!\A_SPW_TOP|tx_data|rd_ptr [3]))) # 
// (\A_SPW_TOP|tx_data|rd_ptr [5] & (((\A_SPW_TOP|tx_data|mem[54][2]~q ) # (\A_SPW_TOP|tx_data|rd_ptr [3])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[30][2]~q  & ( !\A_SPW_TOP|tx_data|mem[62][2]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & (((\A_SPW_TOP|tx_data|rd_ptr 
// [3])) # (\A_SPW_TOP|tx_data|mem[22][2]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [5] & (((!\A_SPW_TOP|tx_data|rd_ptr [3] & \A_SPW_TOP|tx_data|mem[54][2]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[30][2]~q  & ( !\A_SPW_TOP|tx_data|mem[62][2]~q  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [3] & ((!\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|mem[22][2]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [5] & ((\A_SPW_TOP|tx_data|mem[54][2]~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[22][2]~q ),
        .datab(!\A_SPW_TOP|tx_data|rd_ptr [5]),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [3]),
        .datad(!\A_SPW_TOP|tx_data|mem[54][2]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[30][2]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[62][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux15~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux15~8 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux15~8 .lut_mask = 64'h40704C7C43734F7F;
defparam \A_SPW_TOP|tx_data|Mux15~8 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y10_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux15~5 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux15~5_combout  = ( \A_SPW_TOP|tx_data|mem[48][2]~q  & ( \A_SPW_TOP|tx_data|mem[24][2]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & (((\A_SPW_TOP|tx_data|rd_ptr [3]) # (\A_SPW_TOP|tx_data|mem[16][2]~q )))) # (\A_SPW_TOP|tx_data|rd_ptr [5] 
// & (((!\A_SPW_TOP|tx_data|rd_ptr [3])) # (\A_SPW_TOP|tx_data|mem[56][2]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[48][2]~q  & ( \A_SPW_TOP|tx_data|mem[24][2]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & (((\A_SPW_TOP|tx_data|rd_ptr [3]) # 
// (\A_SPW_TOP|tx_data|mem[16][2]~q )))) # (\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|mem[56][2]~q  & ((\A_SPW_TOP|tx_data|rd_ptr [3])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[48][2]~q  & ( !\A_SPW_TOP|tx_data|mem[24][2]~q  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [5] & (((\A_SPW_TOP|tx_data|mem[16][2]~q  & !\A_SPW_TOP|tx_data|rd_ptr [3])))) # (\A_SPW_TOP|tx_data|rd_ptr [5] & (((!\A_SPW_TOP|tx_data|rd_ptr [3])) # (\A_SPW_TOP|tx_data|mem[56][2]~q ))) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|mem[48][2]~q  & ( !\A_SPW_TOP|tx_data|mem[24][2]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & (((\A_SPW_TOP|tx_data|mem[16][2]~q  & !\A_SPW_TOP|tx_data|rd_ptr [3])))) # (\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|mem[56][2]~q  & 
// ((\A_SPW_TOP|tx_data|rd_ptr [3])))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[56][2]~q ),
        .datab(!\A_SPW_TOP|tx_data|rd_ptr [5]),
        .datac(!\A_SPW_TOP|tx_data|mem[16][2]~q ),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [3]),
        .datae(!\A_SPW_TOP|tx_data|mem[48][2]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[24][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux15~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux15~5 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux15~5 .lut_mask = 64'h0C113F110CDD3FDD;
defparam \A_SPW_TOP|tx_data|Mux15~5 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y10_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux15~7 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux15~7_combout  = ( \A_SPW_TOP|tx_data|mem[26][2]~q  & ( \A_SPW_TOP|tx_data|mem[58][2]~q  & ( ((!\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|mem[18][2]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [5] & ((\A_SPW_TOP|tx_data|mem[50][2]~q 
// )))) # (\A_SPW_TOP|tx_data|rd_ptr [3]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[26][2]~q  & ( \A_SPW_TOP|tx_data|mem[58][2]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|mem[18][2]~q  & (!\A_SPW_TOP|tx_data|rd_ptr [3]))) # 
// (\A_SPW_TOP|tx_data|rd_ptr [5] & (((\A_SPW_TOP|tx_data|mem[50][2]~q ) # (\A_SPW_TOP|tx_data|rd_ptr [3])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[26][2]~q  & ( !\A_SPW_TOP|tx_data|mem[58][2]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & (((\A_SPW_TOP|tx_data|rd_ptr 
// [3])) # (\A_SPW_TOP|tx_data|mem[18][2]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [5] & (((!\A_SPW_TOP|tx_data|rd_ptr [3] & \A_SPW_TOP|tx_data|mem[50][2]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[26][2]~q  & ( !\A_SPW_TOP|tx_data|mem[58][2]~q  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [3] & ((!\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|mem[18][2]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [5] & ((\A_SPW_TOP|tx_data|mem[50][2]~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[18][2]~q ),
        .datab(!\A_SPW_TOP|tx_data|rd_ptr [5]),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [3]),
        .datad(!\A_SPW_TOP|tx_data|mem[50][2]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[26][2]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[58][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux15~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux15~7 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux15~7 .lut_mask = 64'h40704C7C43734F7F;
defparam \A_SPW_TOP|tx_data|Mux15~7 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y10_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux15~6 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux15~6_combout  = ( \A_SPW_TOP|tx_data|mem[20][2]~q  & ( \A_SPW_TOP|tx_data|mem[52][2]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [3]) # ((!\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|mem[28][2]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [5] & 
// ((\A_SPW_TOP|tx_data|mem[60][2]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[20][2]~q  & ( \A_SPW_TOP|tx_data|mem[52][2]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|mem[28][2]~q  & ((\A_SPW_TOP|tx_data|rd_ptr [3])))) # 
// (\A_SPW_TOP|tx_data|rd_ptr [5] & (((!\A_SPW_TOP|tx_data|rd_ptr [3]) # (\A_SPW_TOP|tx_data|mem[60][2]~q )))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[20][2]~q  & ( !\A_SPW_TOP|tx_data|mem[52][2]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & 
// (((!\A_SPW_TOP|tx_data|rd_ptr [3])) # (\A_SPW_TOP|tx_data|mem[28][2]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [5] & (((\A_SPW_TOP|tx_data|mem[60][2]~q  & \A_SPW_TOP|tx_data|rd_ptr [3])))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[20][2]~q  & ( 
// !\A_SPW_TOP|tx_data|mem[52][2]~q  & ( (\A_SPW_TOP|tx_data|rd_ptr [3] & ((!\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|mem[28][2]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [5] & ((\A_SPW_TOP|tx_data|mem[60][2]~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[28][2]~q ),
        .datab(!\A_SPW_TOP|tx_data|rd_ptr [5]),
        .datac(!\A_SPW_TOP|tx_data|mem[60][2]~q ),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [3]),
        .datae(!\A_SPW_TOP|tx_data|mem[20][2]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[52][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux15~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux15~6 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux15~6 .lut_mask = 64'h0047CC473347FF47;
defparam \A_SPW_TOP|tx_data|Mux15~6 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y10_N21
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux15~9 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux15~9_combout  = ( \A_SPW_TOP|tx_data|Mux15~7_combout  & ( \A_SPW_TOP|tx_data|Mux15~6_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & (((\A_SPW_TOP|tx_data|Mux15~5_combout )) # (\A_SPW_TOP|tx_data|rd_ptr [1]))) # 
// (\A_SPW_TOP|tx_data|rd_ptr [2] & ((!\A_SPW_TOP|tx_data|rd_ptr [1]) # ((\A_SPW_TOP|tx_data|Mux15~8_combout )))) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux15~7_combout  & ( \A_SPW_TOP|tx_data|Mux15~6_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & 
// (!\A_SPW_TOP|tx_data|rd_ptr [1] & ((\A_SPW_TOP|tx_data|Mux15~5_combout )))) # (\A_SPW_TOP|tx_data|rd_ptr [2] & ((!\A_SPW_TOP|tx_data|rd_ptr [1]) # ((\A_SPW_TOP|tx_data|Mux15~8_combout )))) ) ) ) # ( \A_SPW_TOP|tx_data|Mux15~7_combout  & ( 
// !\A_SPW_TOP|tx_data|Mux15~6_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & (((\A_SPW_TOP|tx_data|Mux15~5_combout )) # (\A_SPW_TOP|tx_data|rd_ptr [1]))) # (\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|Mux15~8_combout 
// ))) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux15~7_combout  & ( !\A_SPW_TOP|tx_data|Mux15~6_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & (!\A_SPW_TOP|tx_data|rd_ptr [1] & ((\A_SPW_TOP|tx_data|Mux15~5_combout )))) # (\A_SPW_TOP|tx_data|rd_ptr [2] & 
// (\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|Mux15~8_combout ))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .datab(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .datac(!\A_SPW_TOP|tx_data|Mux15~8_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux15~5_combout ),
        .datae(!\A_SPW_TOP|tx_data|Mux15~7_combout ),
        .dataf(!\A_SPW_TOP|tx_data|Mux15~6_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux15~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux15~9 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux15~9 .lut_mask = 64'h018923AB45CD67EF;
defparam \A_SPW_TOP|tx_data|Mux15~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y10_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux15~20 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux15~20_combout  = ( \A_SPW_TOP|tx_data|Mux15~9_combout  & ( \A_SPW_TOP|tx_data|rd_ptr [0] & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & (\A_SPW_TOP|tx_data|Mux15~14_combout )) # (\A_SPW_TOP|tx_data|rd_ptr [4] & 
// ((\A_SPW_TOP|tx_data|Mux15~19_combout ))) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux15~9_combout  & ( \A_SPW_TOP|tx_data|rd_ptr [0] & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & (\A_SPW_TOP|tx_data|Mux15~14_combout )) # (\A_SPW_TOP|tx_data|rd_ptr [4] & 
// ((\A_SPW_TOP|tx_data|Mux15~19_combout ))) ) ) ) # ( \A_SPW_TOP|tx_data|Mux15~9_combout  & ( !\A_SPW_TOP|tx_data|rd_ptr [0] & ( (\A_SPW_TOP|tx_data|Mux15~4_combout ) # (\A_SPW_TOP|tx_data|rd_ptr [4]) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux15~9_combout  & ( 
// !\A_SPW_TOP|tx_data|rd_ptr [0] & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & \A_SPW_TOP|tx_data|Mux15~4_combout ) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux15~14_combout ),
        .datab(!\A_SPW_TOP|tx_data|Mux15~19_combout ),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .datad(!\A_SPW_TOP|tx_data|Mux15~4_combout ),
        .datae(!\A_SPW_TOP|tx_data|Mux15~9_combout ),
        .dataf(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux15~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux15~20 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux15~20 .lut_mask = 64'h00F00FFF53535353;
defparam \A_SPW_TOP|tx_data|Mux15~20 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y10_N8
dffeas \A_SPW_TOP|tx_data|data_out[2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|tx_data|Mux15~20_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|data_out [2]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|data_out[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|data_out[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X54_Y7_N57
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector38~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector38~0_combout  = ( \A_SPW_TOP|SPW|TX|tx_data_in_0 [2] & ( (!\A_SPW_TOP|SPW|TX|Selector40~0_combout ) # ((\A_SPW_TOP|tx_data|data_out [2] & \A_SPW_TOP|SPW|TX|Selector32~0_combout )) ) ) # ( !\A_SPW_TOP|SPW|TX|tx_data_in_0 [2] & ( 
// (\A_SPW_TOP|tx_data|data_out [2] & \A_SPW_TOP|SPW|TX|Selector32~0_combout ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|tx_data|data_out [2]),
        .datac(!\A_SPW_TOP|SPW|TX|Selector40~0_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|Selector32~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|tx_data_in_0 [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector38~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector38~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector38~0 .lut_mask = 64'h00330033F0F3F0F3;
defparam \A_SPW_TOP|SPW|TX|Selector38~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X54_Y7_N17
dffeas \A_SPW_TOP|SPW|TX|tx_data_in_0[2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|Selector38~0_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|tx_data_in_0 [2]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_data_in_0[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|tx_data_in_0[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y17_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_payload~3 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_payload~3_combout  = ( \u0|hps_0|fpga_interfaces|h2f_WDATA [3] & ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_WDATA [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_010|src_payload~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_payload~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_payload~3 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_payload~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y17_N1
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_010|src_payload~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y14_N24
cyclonev_lcell_comb \u0|write_data_fifo_tx|data_out[3]~feeder (
// Equation(s):
// \u0|write_data_fifo_tx|data_out[3]~feeder_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [3] )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|write_data_fifo_tx|data_out[3]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|write_data_fifo_tx|data_out[3]~feeder .extended_lut = "off";
defparam \u0|write_data_fifo_tx|data_out[3]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|write_data_fifo_tx|data_out[3]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y14_N26
dffeas \u0|write_data_fifo_tx|data_out[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|write_data_fifo_tx|data_out[3]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|write_data_fifo_tx|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|write_data_fifo_tx|data_out [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|write_data_fifo_tx|data_out[3] .is_wysiwyg = "true";
defparam \u0|write_data_fifo_tx|data_out[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y10_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector451~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector451~0_combout  = ( \A_SPW_TOP|tx_data|Mux5~20_combout  & ( (!\A_SPW_TOP|tx_data|Selector446~0_combout  & (((\A_SPW_TOP|tx_data|mem[49][3]~q )))) # (\A_SPW_TOP|tx_data|Selector446~0_combout  & 
// ((!\A_SPW_TOP|tx_data|state_data_write.00~q ) # ((\u0|write_data_fifo_tx|data_out [3])))) ) ) # ( !\A_SPW_TOP|tx_data|Mux5~20_combout  & ( (!\A_SPW_TOP|tx_data|Selector446~0_combout  & (((\A_SPW_TOP|tx_data|mem[49][3]~q )))) # 
// (\A_SPW_TOP|tx_data|Selector446~0_combout  & (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [3]))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\u0|write_data_fifo_tx|data_out [3]),
        .datac(!\A_SPW_TOP|tx_data|Selector446~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|mem[49][3]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector451~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector451~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector451~0 .lut_mask = 64'h01F101F10BFB0BFB;
defparam \A_SPW_TOP|tx_data|Selector451~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y10_N29
dffeas \A_SPW_TOP|tx_data|mem[49][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector451~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[49][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[49][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[49][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y10_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector487~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector487~0_combout  = ( \A_SPW_TOP|tx_data|mem[53][3]~q  & ( (!\A_SPW_TOP|tx_data|Selector482~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux5~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [3])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[53][3]~q  & ( (\A_SPW_TOP|tx_data|Selector482~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux5~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [3]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector482~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [3]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[53][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector487~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector487~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector487~0 .lut_mask = 64'h04070407F4F7F4F7;
defparam \A_SPW_TOP|tx_data|Selector487~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y10_N11
dffeas \A_SPW_TOP|tx_data|mem[53][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector487~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[53][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[53][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[53][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y10_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector307~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector307~0_combout  = ( \u0|write_data_fifo_tx|data_out [3] & ( (!\A_SPW_TOP|tx_data|Selector302~0_combout  & (((\A_SPW_TOP|tx_data|mem[33][3]~q )))) # (\A_SPW_TOP|tx_data|Selector302~0_combout  & 
// (((\A_SPW_TOP|tx_data|state_data_write.00~q )) # (\A_SPW_TOP|tx_data|Mux5~20_combout ))) ) ) # ( !\u0|write_data_fifo_tx|data_out [3] & ( (!\A_SPW_TOP|tx_data|Selector302~0_combout  & (((\A_SPW_TOP|tx_data|mem[33][3]~q )))) # 
// (\A_SPW_TOP|tx_data|Selector302~0_combout  & (\A_SPW_TOP|tx_data|Mux5~20_combout  & (!\A_SPW_TOP|tx_data|state_data_write.00~q ))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector302~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|mem[33][3]~q ),
        .datae(gnd),
        .dataf(!\u0|write_data_fifo_tx|data_out [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector307~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector307~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector307~0 .lut_mask = 64'h04F404F407F707F7;
defparam \A_SPW_TOP|tx_data|Selector307~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y10_N29
dffeas \A_SPW_TOP|tx_data|mem[33][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector307~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[33][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[33][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[33][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y10_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector343~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector343~0_combout  = ( \A_SPW_TOP|tx_data|mem[37][3]~q  & ( (!\A_SPW_TOP|tx_data|Selector338~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux5~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [3])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[37][3]~q  & ( (\A_SPW_TOP|tx_data|Selector338~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux5~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [3]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector338~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [3]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[37][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector343~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector343~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector343~0 .lut_mask = 64'h04070407F4F7F4F7;
defparam \A_SPW_TOP|tx_data|Selector343~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y10_N32
dffeas \A_SPW_TOP|tx_data|mem[37][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector343~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[37][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[37][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[37][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y10_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux5~11 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux5~11_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [4] & ( \A_SPW_TOP|tx_data|mem[37][3]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|mem[49][3]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [2] & ((\A_SPW_TOP|tx_data|mem[53][3]~q ))) ) 
// ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [4] & ( \A_SPW_TOP|tx_data|mem[37][3]~q  & ( (\A_SPW_TOP|tx_data|wr_ptr [2]) # (\A_SPW_TOP|tx_data|mem[33][3]~q ) ) ) ) # ( \A_SPW_TOP|tx_data|wr_ptr [4] & ( !\A_SPW_TOP|tx_data|mem[37][3]~q  & ( 
// (!\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|mem[49][3]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [2] & ((\A_SPW_TOP|tx_data|mem[53][3]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [4] & ( !\A_SPW_TOP|tx_data|mem[37][3]~q  & ( 
// (\A_SPW_TOP|tx_data|mem[33][3]~q  & !\A_SPW_TOP|tx_data|wr_ptr [2]) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[49][3]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[53][3]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[33][3]~q ),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .dataf(!\A_SPW_TOP|tx_data|mem[37][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux5~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux5~11 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux5~11 .lut_mask = 64'h0F0055330FFF5533;
defparam \A_SPW_TOP|tx_data|Mux5~11 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y10_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector316~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector316~0_combout  = ( \A_SPW_TOP|tx_data|Selector311~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux5~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [3]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector311~0_combout  & ( \A_SPW_TOP|tx_data|mem[34][3]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [3]),
        .datac(!\A_SPW_TOP|tx_data|mem[34][3]~q ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector311~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector316~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector316~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector316~0 .lut_mask = 64'h0F0F0F0F55335533;
defparam \A_SPW_TOP|tx_data|Selector316~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y10_N53
dffeas \A_SPW_TOP|tx_data|mem[34][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector316~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[34][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[34][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[34][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y10_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector460~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector460~0_combout  = ( \A_SPW_TOP|tx_data|mem[50][3]~q  & ( (!\A_SPW_TOP|tx_data|Selector455~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux5~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [3])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[50][3]~q  & ( (\A_SPW_TOP|tx_data|Selector455~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux5~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [3]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [3]),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|tx_data|Selector455~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[50][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector460~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector460~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector460~0 .lut_mask = 64'h00530053FF53FF53;
defparam \A_SPW_TOP|tx_data|Selector460~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y10_N8
dffeas \A_SPW_TOP|tx_data|mem[50][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector460~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[50][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[50][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[50][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y10_N33
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector496~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector496~0_combout  = ( \A_SPW_TOP|tx_data|mem[54][3]~q  & ( (!\A_SPW_TOP|tx_data|Selector491~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux5~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [3])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[54][3]~q  & ( (\A_SPW_TOP|tx_data|Selector491~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux5~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [3]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [3]),
        .datac(!\A_SPW_TOP|tx_data|Selector491~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[54][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector496~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector496~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector496~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|tx_data|Selector496~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y10_N26
dffeas \A_SPW_TOP|tx_data|mem[54][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector496~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[54][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[54][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[54][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y10_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector352~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector352~0_combout  = ( \A_SPW_TOP|tx_data|mem[38][3]~q  & ( (!\A_SPW_TOP|tx_data|Selector347~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux5~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [3])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[38][3]~q  & ( (\A_SPW_TOP|tx_data|Selector347~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux5~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [3]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [3]),
        .datac(!\A_SPW_TOP|tx_data|Selector347~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[38][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector352~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector352~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector352~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|tx_data|Selector352~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y10_N17
dffeas \A_SPW_TOP|tx_data|mem[38][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector352~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[38][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[38][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[38][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y10_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux5~12 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux5~12_combout  = ( \A_SPW_TOP|tx_data|mem[54][3]~q  & ( \A_SPW_TOP|tx_data|mem[38][3]~q  & ( ((!\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|mem[34][3]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [4] & ((\A_SPW_TOP|tx_data|mem[50][3]~q 
// )))) # (\A_SPW_TOP|tx_data|wr_ptr [2]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[54][3]~q  & ( \A_SPW_TOP|tx_data|mem[38][3]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & ((!\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|mem[34][3]~q )) # 
// (\A_SPW_TOP|tx_data|wr_ptr [4] & ((\A_SPW_TOP|tx_data|mem[50][3]~q ))))) # (\A_SPW_TOP|tx_data|wr_ptr [2] & (((!\A_SPW_TOP|tx_data|wr_ptr [4])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[54][3]~q  & ( !\A_SPW_TOP|tx_data|mem[38][3]~q  & ( 
// (!\A_SPW_TOP|tx_data|wr_ptr [2] & ((!\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|mem[34][3]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [4] & ((\A_SPW_TOP|tx_data|mem[50][3]~q ))))) # (\A_SPW_TOP|tx_data|wr_ptr [2] & (((\A_SPW_TOP|tx_data|wr_ptr [4])))) ) ) 
// ) # ( !\A_SPW_TOP|tx_data|mem[54][3]~q  & ( !\A_SPW_TOP|tx_data|mem[38][3]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & ((!\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|mem[34][3]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [4] & ((\A_SPW_TOP|tx_data|mem[50][3]~q 
// ))))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[34][3]~q ),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datad(!\A_SPW_TOP|tx_data|mem[50][3]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[54][3]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[38][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux5~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux5~12 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux5~12 .lut_mask = 64'h404C434F707C737F;
defparam \A_SPW_TOP|tx_data|Mux5~12 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y10_N57
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector334~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector334~0_combout  = ( \A_SPW_TOP|tx_data|mem[36][3]~q  & ( (!\A_SPW_TOP|tx_data|Selector329~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux5~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [3])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[36][3]~q  & ( (\A_SPW_TOP|tx_data|Selector329~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux5~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [3]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector329~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [3]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[36][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector334~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector334~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector334~0 .lut_mask = 64'h04070407F4F7F4F7;
defparam \A_SPW_TOP|tx_data|Selector334~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y10_N53
dffeas \A_SPW_TOP|tx_data|mem[36][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector334~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[36][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[36][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[36][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y10_N21
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector478~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector478~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector473~0_combout  & ((\A_SPW_TOP|tx_data|mem[52][3]~q ))) # (\A_SPW_TOP|tx_data|Selector473~0_combout  & (\u0|write_data_fifo_tx|data_out 
// [3])) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector473~0_combout  & ((\A_SPW_TOP|tx_data|mem[52][3]~q ))) # (\A_SPW_TOP|tx_data|Selector473~0_combout  & (\A_SPW_TOP|tx_data|Mux5~20_combout )) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [3]),
        .datac(!\A_SPW_TOP|tx_data|Selector473~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|mem[52][3]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector478~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector478~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector478~0 .lut_mask = 64'h05F505F503F303F3;
defparam \A_SPW_TOP|tx_data|Selector478~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y10_N5
dffeas \A_SPW_TOP|tx_data|mem[52][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector478~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[52][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[52][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[52][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y10_N45
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector442~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector442~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector437~0_combout  & ((\A_SPW_TOP|tx_data|mem[48][3]~q ))) # (\A_SPW_TOP|tx_data|Selector437~0_combout  & (\u0|write_data_fifo_tx|data_out 
// [3])) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector437~0_combout  & ((\A_SPW_TOP|tx_data|mem[48][3]~q ))) # (\A_SPW_TOP|tx_data|Selector437~0_combout  & (\A_SPW_TOP|tx_data|Mux5~20_combout )) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [3]),
        .datac(!\A_SPW_TOP|tx_data|Selector437~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|mem[48][3]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector442~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector442~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector442~0 .lut_mask = 64'h05F505F503F303F3;
defparam \A_SPW_TOP|tx_data|Selector442~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y10_N59
dffeas \A_SPW_TOP|tx_data|mem[48][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector442~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[48][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[48][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[48][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y10_N39
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector298~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector298~0_combout  = ( \A_SPW_TOP|tx_data|Mux5~20_combout  & ( (!\A_SPW_TOP|tx_data|Selector293~0_combout  & (((\A_SPW_TOP|tx_data|mem[32][3]~q )))) # (\A_SPW_TOP|tx_data|Selector293~0_combout  & 
// ((!\A_SPW_TOP|tx_data|state_data_write.00~q ) # ((\u0|write_data_fifo_tx|data_out [3])))) ) ) # ( !\A_SPW_TOP|tx_data|Mux5~20_combout  & ( (!\A_SPW_TOP|tx_data|Selector293~0_combout  & (((\A_SPW_TOP|tx_data|mem[32][3]~q )))) # 
// (\A_SPW_TOP|tx_data|Selector293~0_combout  & (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [3]))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\u0|write_data_fifo_tx|data_out [3]),
        .datac(!\A_SPW_TOP|tx_data|Selector293~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|mem[32][3]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector298~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector298~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector298~0 .lut_mask = 64'h01F101F10BFB0BFB;
defparam \A_SPW_TOP|tx_data|Selector298~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y10_N2
dffeas \A_SPW_TOP|tx_data|mem[32][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector298~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[32][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[32][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[32][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y10_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux5~10 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux5~10_combout  = ( \A_SPW_TOP|tx_data|mem[32][3]~q  & ( \A_SPW_TOP|tx_data|wr_ptr [4] & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & ((\A_SPW_TOP|tx_data|mem[48][3]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|mem[52][3]~q )) ) 
// ) ) # ( !\A_SPW_TOP|tx_data|mem[32][3]~q  & ( \A_SPW_TOP|tx_data|wr_ptr [4] & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & ((\A_SPW_TOP|tx_data|mem[48][3]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|mem[52][3]~q )) ) ) ) # ( 
// \A_SPW_TOP|tx_data|mem[32][3]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [4] & ( (!\A_SPW_TOP|tx_data|wr_ptr [2]) # (\A_SPW_TOP|tx_data|mem[36][3]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[32][3]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [4] & ( 
// (\A_SPW_TOP|tx_data|mem[36][3]~q  & \A_SPW_TOP|tx_data|wr_ptr [2]) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[36][3]~q ),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datac(!\A_SPW_TOP|tx_data|mem[52][3]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[48][3]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[32][3]~q ),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux5~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux5~10 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux5~10 .lut_mask = 64'h1111DDDD03CF03CF;
defparam \A_SPW_TOP|tx_data|Mux5~10 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y10_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector361~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector361~0_combout  = ( \u0|write_data_fifo_tx|data_out [3] & ( (!\A_SPW_TOP|tx_data|Selector356~0_combout  & (((\A_SPW_TOP|tx_data|mem[39][3]~q )))) # (\A_SPW_TOP|tx_data|Selector356~0_combout  & 
// (((\A_SPW_TOP|tx_data|state_data_write.00~q )) # (\A_SPW_TOP|tx_data|Mux5~20_combout ))) ) ) # ( !\u0|write_data_fifo_tx|data_out [3] & ( (!\A_SPW_TOP|tx_data|Selector356~0_combout  & (((\A_SPW_TOP|tx_data|mem[39][3]~q )))) # 
// (\A_SPW_TOP|tx_data|Selector356~0_combout  & (\A_SPW_TOP|tx_data|Mux5~20_combout  & (!\A_SPW_TOP|tx_data|state_data_write.00~q ))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector356~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|mem[39][3]~q ),
        .datae(gnd),
        .dataf(!\u0|write_data_fifo_tx|data_out [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector361~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector361~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector361~0 .lut_mask = 64'h04F404F407F707F7;
defparam \A_SPW_TOP|tx_data|Selector361~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y10_N23
dffeas \A_SPW_TOP|tx_data|mem[39][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector361~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[39][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[39][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[39][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y10_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector469~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector469~0_combout  = ( \A_SPW_TOP|tx_data|mem[51][3]~q  & ( (!\A_SPW_TOP|tx_data|Selector464~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux5~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [3])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[51][3]~q  & ( (\A_SPW_TOP|tx_data|Selector464~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux5~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [3]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector464~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [3]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[51][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector469~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector469~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector469~0 .lut_mask = 64'h04070407F4F7F4F7;
defparam \A_SPW_TOP|tx_data|Selector469~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y10_N20
dffeas \A_SPW_TOP|tx_data|mem[51][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector469~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[51][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[51][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[51][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y10_N39
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector505~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector505~0_combout  = ( \A_SPW_TOP|tx_data|Selector500~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux5~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [3]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector500~0_combout  & ( \A_SPW_TOP|tx_data|mem[55][3]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[55][3]~q ),
        .datad(!\u0|write_data_fifo_tx|data_out [3]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector500~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector505~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector505~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector505~0 .lut_mask = 64'h0F0F0F0F44774477;
defparam \A_SPW_TOP|tx_data|Selector505~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y10_N17
dffeas \A_SPW_TOP|tx_data|mem[55][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector505~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[55][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[55][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[55][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y10_N45
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector325~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector325~0_combout  = ( \A_SPW_TOP|tx_data|mem[35][3]~q  & ( (!\A_SPW_TOP|tx_data|Selector320~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux5~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [3])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[35][3]~q  & ( (\A_SPW_TOP|tx_data|Selector320~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux5~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [3]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\u0|write_data_fifo_tx|data_out [3]),
        .datad(!\A_SPW_TOP|tx_data|Selector320~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[35][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector325~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector325~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector325~0 .lut_mask = 64'h00470047FF47FF47;
defparam \A_SPW_TOP|tx_data|Selector325~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y10_N35
dffeas \A_SPW_TOP|tx_data|mem[35][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector325~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[35][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[35][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[35][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y10_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux5~13 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux5~13_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [4] & ( \A_SPW_TOP|tx_data|mem[35][3]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|mem[51][3]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [2] & ((\A_SPW_TOP|tx_data|mem[55][3]~q ))) ) 
// ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [4] & ( \A_SPW_TOP|tx_data|mem[35][3]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [2]) # (\A_SPW_TOP|tx_data|mem[39][3]~q ) ) ) ) # ( \A_SPW_TOP|tx_data|wr_ptr [4] & ( !\A_SPW_TOP|tx_data|mem[35][3]~q  & ( 
// (!\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|mem[51][3]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [2] & ((\A_SPW_TOP|tx_data|mem[55][3]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [4] & ( !\A_SPW_TOP|tx_data|mem[35][3]~q  & ( 
// (\A_SPW_TOP|tx_data|mem[39][3]~q  & \A_SPW_TOP|tx_data|wr_ptr [2]) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[39][3]~q ),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datac(!\A_SPW_TOP|tx_data|mem[51][3]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[55][3]~q ),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .dataf(!\A_SPW_TOP|tx_data|mem[35][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux5~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux5~13 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux5~13 .lut_mask = 64'h11110C3FDDDD0C3F;
defparam \A_SPW_TOP|tx_data|Mux5~13 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y10_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux5~14 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux5~14_combout  = ( \A_SPW_TOP|tx_data|Mux5~10_combout  & ( \A_SPW_TOP|tx_data|Mux5~13_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & (((!\A_SPW_TOP|tx_data|wr_ptr [1]) # (\A_SPW_TOP|tx_data|Mux5~12_combout )))) # 
// (\A_SPW_TOP|tx_data|wr_ptr [0] & (((\A_SPW_TOP|tx_data|wr_ptr [1])) # (\A_SPW_TOP|tx_data|Mux5~11_combout ))) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux5~10_combout  & ( \A_SPW_TOP|tx_data|Mux5~13_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & 
// (((\A_SPW_TOP|tx_data|wr_ptr [1] & \A_SPW_TOP|tx_data|Mux5~12_combout )))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & (((\A_SPW_TOP|tx_data|wr_ptr [1])) # (\A_SPW_TOP|tx_data|Mux5~11_combout ))) ) ) ) # ( \A_SPW_TOP|tx_data|Mux5~10_combout  & ( 
// !\A_SPW_TOP|tx_data|Mux5~13_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & (((!\A_SPW_TOP|tx_data|wr_ptr [1]) # (\A_SPW_TOP|tx_data|Mux5~12_combout )))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|Mux5~11_combout  & (!\A_SPW_TOP|tx_data|wr_ptr 
// [1]))) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux5~10_combout  & ( !\A_SPW_TOP|tx_data|Mux5~13_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & (((\A_SPW_TOP|tx_data|wr_ptr [1] & \A_SPW_TOP|tx_data|Mux5~12_combout )))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & 
// (\A_SPW_TOP|tx_data|Mux5~11_combout  & (!\A_SPW_TOP|tx_data|wr_ptr [1]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datab(!\A_SPW_TOP|tx_data|Mux5~11_combout ),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datad(!\A_SPW_TOP|tx_data|Mux5~12_combout ),
        .datae(!\A_SPW_TOP|tx_data|Mux5~10_combout ),
        .dataf(!\A_SPW_TOP|tx_data|Mux5~13_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux5~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux5~14 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux5~14 .lut_mask = 64'h101AB0BA151FB5BF;
defparam \A_SPW_TOP|tx_data|Mux5~14 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y11_N57
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector190~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector190~0_combout  = ( \A_SPW_TOP|tx_data|Mux5~20_combout  & ( (!\A_SPW_TOP|tx_data|Selector185~0_combout  & (((\A_SPW_TOP|tx_data|mem[20][3]~q )))) # (\A_SPW_TOP|tx_data|Selector185~0_combout  & 
// (((!\A_SPW_TOP|tx_data|state_data_write.00~q )) # (\u0|write_data_fifo_tx|data_out [3]))) ) ) # ( !\A_SPW_TOP|tx_data|Mux5~20_combout  & ( (!\A_SPW_TOP|tx_data|Selector185~0_combout  & (((\A_SPW_TOP|tx_data|mem[20][3]~q )))) # 
// (\A_SPW_TOP|tx_data|Selector185~0_combout  & (\u0|write_data_fifo_tx|data_out [3] & (\A_SPW_TOP|tx_data|state_data_write.00~q ))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [3]),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector185~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|mem[20][3]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector190~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector190~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector190~0 .lut_mask = 64'h01F101F10DFD0DFD;
defparam \A_SPW_TOP|tx_data|Selector190~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y11_N5
dffeas \A_SPW_TOP|tx_data|mem[20][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector190~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[20][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[20][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[20][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y11_N45
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector154~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector154~0_combout  = ( \A_SPW_TOP|tx_data|Selector149~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux5~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\u0|write_data_fifo_tx|data_out [3])) ) ) # ( !\A_SPW_TOP|tx_data|Selector149~0_combout  & ( \A_SPW_TOP|tx_data|mem[16][3]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\u0|write_data_fifo_tx|data_out [3]),
        .datac(!\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .datad(!\A_SPW_TOP|tx_data|mem[16][3]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector149~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector154~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector154~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector154~0 .lut_mask = 64'h00FF00FF1B1B1B1B;
defparam \A_SPW_TOP|tx_data|Selector154~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X45_Y11_N5
dffeas \A_SPW_TOP|tx_data|mem[16][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector154~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[16][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[16][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[16][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y11_N45
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector46~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector46~0_combout  = ( \A_SPW_TOP|tx_data|Selector41~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux5~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out 
// [3]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector41~0_combout  & ( \A_SPW_TOP|tx_data|mem[4][3]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [3]),
        .datac(!\A_SPW_TOP|tx_data|mem[4][3]~q ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector41~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector46~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector46~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector46~0 .lut_mask = 64'h0F0F0F0F55335533;
defparam \A_SPW_TOP|tx_data|Selector46~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y11_N17
dffeas \A_SPW_TOP|tx_data|mem[4][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector46~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[4][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[4][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[4][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y11_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector10~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector10~0_combout  = ( \A_SPW_TOP|tx_data|mem[0][3]~q  & ( (!\A_SPW_TOP|tx_data|Selector5~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux5~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [3]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[0][3]~q  & ( (\A_SPW_TOP|tx_data|Selector5~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux5~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [3])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [3]),
        .datab(!\A_SPW_TOP|tx_data|Selector5~0_combout ),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[0][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector10~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector10~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector10~0 .lut_mask = 64'h01310131CDFDCDFD;
defparam \A_SPW_TOP|tx_data|Selector10~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X45_Y11_N53
dffeas \A_SPW_TOP|tx_data|mem[0][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector10~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[0][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[0][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[0][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y11_N15
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux5~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux5~0_combout  = ( \A_SPW_TOP|tx_data|mem[4][3]~q  & ( \A_SPW_TOP|tx_data|mem[0][3]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [4]) # ((!\A_SPW_TOP|tx_data|wr_ptr [2] & ((\A_SPW_TOP|tx_data|mem[16][3]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [2] & 
// (\A_SPW_TOP|tx_data|mem[20][3]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[4][3]~q  & ( \A_SPW_TOP|tx_data|mem[0][3]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & (((!\A_SPW_TOP|tx_data|wr_ptr [4]) # (\A_SPW_TOP|tx_data|mem[16][3]~q )))) # 
// (\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|mem[20][3]~q  & (\A_SPW_TOP|tx_data|wr_ptr [4]))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[4][3]~q  & ( !\A_SPW_TOP|tx_data|mem[0][3]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & (((\A_SPW_TOP|tx_data|wr_ptr [4] & 
// \A_SPW_TOP|tx_data|mem[16][3]~q )))) # (\A_SPW_TOP|tx_data|wr_ptr [2] & (((!\A_SPW_TOP|tx_data|wr_ptr [4])) # (\A_SPW_TOP|tx_data|mem[20][3]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[4][3]~q  & ( !\A_SPW_TOP|tx_data|mem[0][3]~q  & ( 
// (\A_SPW_TOP|tx_data|wr_ptr [4] & ((!\A_SPW_TOP|tx_data|wr_ptr [2] & ((\A_SPW_TOP|tx_data|mem[16][3]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|mem[20][3]~q )))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[20][3]~q ),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datad(!\A_SPW_TOP|tx_data|mem[16][3]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[4][3]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[0][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux5~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux5~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux5~0 .lut_mask = 64'h010D313DC1CDF1FD;
defparam \A_SPW_TOP|tx_data|Mux5~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y11_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector64~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector64~0_combout  = ( \A_SPW_TOP|tx_data|mem[6][3]~q  & ( (!\A_SPW_TOP|tx_data|Selector59~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux5~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [3])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[6][3]~q  & ( (\A_SPW_TOP|tx_data|Selector59~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux5~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [3]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\u0|write_data_fifo_tx|data_out [3]),
        .datad(!\A_SPW_TOP|tx_data|Selector59~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[6][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector64~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector64~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector64~0 .lut_mask = 64'h00470047FF47FF47;
defparam \A_SPW_TOP|tx_data|Selector64~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y11_N14
dffeas \A_SPW_TOP|tx_data|mem[6][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector64~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[6][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[6][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[6][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y11_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector28~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector28~0_combout  = ( \A_SPW_TOP|tx_data|Selector23~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux5~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out 
// [3]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector23~0_combout  & ( \A_SPW_TOP|tx_data|mem[2][3]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .datac(!\u0|write_data_fifo_tx|data_out [3]),
        .datad(!\A_SPW_TOP|tx_data|mem[2][3]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector23~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector28~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector28~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector28~0 .lut_mask = 64'h00FF00FF27272727;
defparam \A_SPW_TOP|tx_data|Selector28~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X45_Y11_N29
dffeas \A_SPW_TOP|tx_data|mem[2][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector28~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[2][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[2][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[2][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y11_N21
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector208~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector208~0_combout  = ( \A_SPW_TOP|tx_data|Selector203~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux5~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [3]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector203~0_combout  & ( \A_SPW_TOP|tx_data|mem[22][3]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[22][3]~q ),
        .datad(!\u0|write_data_fifo_tx|data_out [3]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector203~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector208~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector208~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector208~0 .lut_mask = 64'h0F0F0F0F44774477;
defparam \A_SPW_TOP|tx_data|Selector208~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y11_N47
dffeas \A_SPW_TOP|tx_data|mem[22][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector208~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[22][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[22][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[22][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y11_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector172~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector172~0_combout  = ( \A_SPW_TOP|tx_data|mem[18][3]~q  & ( (!\A_SPW_TOP|tx_data|Selector167~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux5~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [3]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[18][3]~q  & ( (\A_SPW_TOP|tx_data|Selector167~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux5~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [3])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [3]),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .datad(!\A_SPW_TOP|tx_data|Selector167~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[18][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector172~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector172~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector172~0 .lut_mask = 64'h001D001DFF1DFF1D;
defparam \A_SPW_TOP|tx_data|Selector172~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y11_N11
dffeas \A_SPW_TOP|tx_data|mem[18][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector172~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[18][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[18][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[18][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y11_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux5~2 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux5~2_combout  = ( \A_SPW_TOP|tx_data|mem[22][3]~q  & ( \A_SPW_TOP|tx_data|mem[18][3]~q  & ( ((!\A_SPW_TOP|tx_data|wr_ptr [2] & ((\A_SPW_TOP|tx_data|mem[2][3]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|mem[6][3]~q ))) 
// # (\A_SPW_TOP|tx_data|wr_ptr [4]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[22][3]~q  & ( \A_SPW_TOP|tx_data|mem[18][3]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & (((\A_SPW_TOP|tx_data|mem[2][3]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [4]))) # (\A_SPW_TOP|tx_data|wr_ptr 
// [2] & (!\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|mem[6][3]~q ))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[22][3]~q  & ( !\A_SPW_TOP|tx_data|mem[18][3]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & (!\A_SPW_TOP|tx_data|wr_ptr [4] & 
// ((\A_SPW_TOP|tx_data|mem[2][3]~q )))) # (\A_SPW_TOP|tx_data|wr_ptr [2] & (((\A_SPW_TOP|tx_data|mem[6][3]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [4]))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[22][3]~q  & ( !\A_SPW_TOP|tx_data|mem[18][3]~q  & ( 
// (!\A_SPW_TOP|tx_data|wr_ptr [4] & ((!\A_SPW_TOP|tx_data|wr_ptr [2] & ((\A_SPW_TOP|tx_data|mem[2][3]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|mem[6][3]~q )))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datac(!\A_SPW_TOP|tx_data|mem[6][3]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[2][3]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[22][3]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[18][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux5~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux5~2 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux5~2 .lut_mask = 64'h048C159D26AE37BF;
defparam \A_SPW_TOP|tx_data|Mux5~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y11_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector19~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector19~0_combout  = ( \A_SPW_TOP|tx_data|mem[1][3]~q  & ( (!\A_SPW_TOP|tx_data|Selector14~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux5~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [3]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[1][3]~q  & ( (\A_SPW_TOP|tx_data|Selector14~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux5~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [3])))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\u0|write_data_fifo_tx|data_out [3]),
        .datac(!\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .datad(!\A_SPW_TOP|tx_data|Selector14~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[1][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector19~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector19~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector19~0 .lut_mask = 64'h001B001BFF1BFF1B;
defparam \A_SPW_TOP|tx_data|Selector19~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y11_N53
dffeas \A_SPW_TOP|tx_data|mem[1][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector19~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[1][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[1][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[1][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y11_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector55~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector55~0_combout  = ( \A_SPW_TOP|tx_data|Selector50~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux5~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out 
// [3]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector50~0_combout  & ( \A_SPW_TOP|tx_data|mem[5][3]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [3]),
        .datac(!\A_SPW_TOP|tx_data|mem[5][3]~q ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector50~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector55~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector55~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector55~0 .lut_mask = 64'h0F0F0F0F55335533;
defparam \A_SPW_TOP|tx_data|Selector55~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y11_N59
dffeas \A_SPW_TOP|tx_data|mem[5][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector55~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[5][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[5][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[5][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y11_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector163~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector163~0_combout  = ( \A_SPW_TOP|tx_data|Selector158~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux5~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [3]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector158~0_combout  & ( \A_SPW_TOP|tx_data|mem[17][3]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\u0|write_data_fifo_tx|data_out [3]),
        .datad(!\A_SPW_TOP|tx_data|mem[17][3]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector158~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector163~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector163~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector163~0 .lut_mask = 64'h00FF00FF47474747;
defparam \A_SPW_TOP|tx_data|Selector163~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y11_N29
dffeas \A_SPW_TOP|tx_data|mem[17][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector163~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[17][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[17][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[17][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y11_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector199~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector199~0_combout  = ( \A_SPW_TOP|tx_data|mem[21][3]~q  & ( (!\A_SPW_TOP|tx_data|Selector194~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux5~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [3])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[21][3]~q  & ( (\A_SPW_TOP|tx_data|Selector194~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux5~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [3]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [3]),
        .datac(!\A_SPW_TOP|tx_data|Selector194~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[21][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector199~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector199~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector199~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|tx_data|Selector199~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y11_N41
dffeas \A_SPW_TOP|tx_data|mem[21][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector199~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[21][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[21][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[21][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y11_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux5~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux5~1_combout  = ( \A_SPW_TOP|tx_data|mem[17][3]~q  & ( \A_SPW_TOP|tx_data|mem[21][3]~q  & ( ((!\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|mem[1][3]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [2] & ((\A_SPW_TOP|tx_data|mem[5][3]~q )))) 
// # (\A_SPW_TOP|tx_data|wr_ptr [4]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[17][3]~q  & ( \A_SPW_TOP|tx_data|mem[21][3]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|mem[1][3]~q  & ((!\A_SPW_TOP|tx_data|wr_ptr [4])))) # (\A_SPW_TOP|tx_data|wr_ptr 
// [2] & (((\A_SPW_TOP|tx_data|wr_ptr [4]) # (\A_SPW_TOP|tx_data|mem[5][3]~q )))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[17][3]~q  & ( !\A_SPW_TOP|tx_data|mem[21][3]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & (((\A_SPW_TOP|tx_data|wr_ptr [4])) # 
// (\A_SPW_TOP|tx_data|mem[1][3]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [2] & (((\A_SPW_TOP|tx_data|mem[5][3]~q  & !\A_SPW_TOP|tx_data|wr_ptr [4])))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[17][3]~q  & ( !\A_SPW_TOP|tx_data|mem[21][3]~q  & ( 
// (!\A_SPW_TOP|tx_data|wr_ptr [4] & ((!\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|mem[1][3]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [2] & ((\A_SPW_TOP|tx_data|mem[5][3]~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[1][3]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[5][3]~q ),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datae(!\A_SPW_TOP|tx_data|mem[17][3]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[21][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux5~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux5~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux5~1 .lut_mask = 64'h530053F0530F53FF;
defparam \A_SPW_TOP|tx_data|Mux5~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y11_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector181~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector181~0_combout  = ( \A_SPW_TOP|tx_data|Selector176~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux5~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [3]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector176~0_combout  & ( \A_SPW_TOP|tx_data|mem[19][3]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [3]),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[19][3]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector176~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector181~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector181~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector181~0 .lut_mask = 64'h00FF00FF53535353;
defparam \A_SPW_TOP|tx_data|Selector181~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y11_N29
dffeas \A_SPW_TOP|tx_data|mem[19][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector181~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[19][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[19][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[19][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y11_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector73~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector73~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector68~0_combout  & ((\A_SPW_TOP|tx_data|mem[7][3]~q ))) # (\A_SPW_TOP|tx_data|Selector68~0_combout  & (\u0|write_data_fifo_tx|data_out 
// [3])) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector68~0_combout  & ((\A_SPW_TOP|tx_data|mem[7][3]~q ))) # (\A_SPW_TOP|tx_data|Selector68~0_combout  & (\A_SPW_TOP|tx_data|Mux5~20_combout )) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [3]),
        .datac(!\A_SPW_TOP|tx_data|Selector68~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|mem[7][3]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector73~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector73~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector73~0 .lut_mask = 64'h05F505F503F303F3;
defparam \A_SPW_TOP|tx_data|Selector73~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y11_N38
dffeas \A_SPW_TOP|tx_data|mem[7][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector73~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[7][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[7][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[7][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y11_N33
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector217~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector217~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector212~0_combout  & ((\A_SPW_TOP|tx_data|mem[23][3]~q ))) # (\A_SPW_TOP|tx_data|Selector212~0_combout  & (\u0|write_data_fifo_tx|data_out 
// [3])) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector212~0_combout  & ((\A_SPW_TOP|tx_data|mem[23][3]~q ))) # (\A_SPW_TOP|tx_data|Selector212~0_combout  & (\A_SPW_TOP|tx_data|Mux5~20_combout )) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [3]),
        .datac(!\A_SPW_TOP|tx_data|Selector212~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|mem[23][3]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector217~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector217~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector217~0 .lut_mask = 64'h05F505F503F303F3;
defparam \A_SPW_TOP|tx_data|Selector217~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y11_N56
dffeas \A_SPW_TOP|tx_data|mem[23][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector217~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[23][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[23][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[23][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y11_N21
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector37~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector37~0_combout  = ( \A_SPW_TOP|tx_data|Mux5~20_combout  & ( (!\A_SPW_TOP|tx_data|Selector32~0_combout  & (((\A_SPW_TOP|tx_data|mem[3][3]~q )))) # (\A_SPW_TOP|tx_data|Selector32~0_combout  & 
// ((!\A_SPW_TOP|tx_data|state_data_write.00~q ) # ((\u0|write_data_fifo_tx|data_out [3])))) ) ) # ( !\A_SPW_TOP|tx_data|Mux5~20_combout  & ( (!\A_SPW_TOP|tx_data|Selector32~0_combout  & (((\A_SPW_TOP|tx_data|mem[3][3]~q )))) # 
// (\A_SPW_TOP|tx_data|Selector32~0_combout  & (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [3]))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\u0|write_data_fifo_tx|data_out [3]),
        .datac(!\A_SPW_TOP|tx_data|mem[3][3]~q ),
        .datad(!\A_SPW_TOP|tx_data|Selector32~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector37~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector37~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector37~0 .lut_mask = 64'h0F110F110FBB0FBB;
defparam \A_SPW_TOP|tx_data|Selector37~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y11_N8
dffeas \A_SPW_TOP|tx_data|mem[3][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector37~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[3][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[3][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[3][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y11_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux5~3 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux5~3_combout  = ( \A_SPW_TOP|tx_data|mem[23][3]~q  & ( \A_SPW_TOP|tx_data|mem[3][3]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & (((!\A_SPW_TOP|tx_data|wr_ptr [2]) # (\A_SPW_TOP|tx_data|mem[7][3]~q )))) # (\A_SPW_TOP|tx_data|wr_ptr [4] & 
// (((\A_SPW_TOP|tx_data|wr_ptr [2])) # (\A_SPW_TOP|tx_data|mem[19][3]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[23][3]~q  & ( \A_SPW_TOP|tx_data|mem[3][3]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & (((!\A_SPW_TOP|tx_data|wr_ptr [2]) # 
// (\A_SPW_TOP|tx_data|mem[7][3]~q )))) # (\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|mem[19][3]~q  & ((!\A_SPW_TOP|tx_data|wr_ptr [2])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[23][3]~q  & ( !\A_SPW_TOP|tx_data|mem[3][3]~q  & ( 
// (!\A_SPW_TOP|tx_data|wr_ptr [4] & (((\A_SPW_TOP|tx_data|mem[7][3]~q  & \A_SPW_TOP|tx_data|wr_ptr [2])))) # (\A_SPW_TOP|tx_data|wr_ptr [4] & (((\A_SPW_TOP|tx_data|wr_ptr [2])) # (\A_SPW_TOP|tx_data|mem[19][3]~q ))) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|mem[23][3]~q  & ( !\A_SPW_TOP|tx_data|mem[3][3]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & (((\A_SPW_TOP|tx_data|mem[7][3]~q  & \A_SPW_TOP|tx_data|wr_ptr [2])))) # (\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|mem[19][3]~q  & 
// ((!\A_SPW_TOP|tx_data|wr_ptr [2])))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[19][3]~q ),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datac(!\A_SPW_TOP|tx_data|mem[7][3]~q ),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datae(!\A_SPW_TOP|tx_data|mem[23][3]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[3][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux5~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux5~3 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux5~3 .lut_mask = 64'h110C113FDD0CDD3F;
defparam \A_SPW_TOP|tx_data|Mux5~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y11_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux5~4 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux5~4_combout  = ( \A_SPW_TOP|tx_data|Mux5~3_combout  & ( \A_SPW_TOP|tx_data|wr_ptr [1] & ( (\A_SPW_TOP|tx_data|Mux5~2_combout ) # (\A_SPW_TOP|tx_data|wr_ptr [0]) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux5~3_combout  & ( 
// \A_SPW_TOP|tx_data|wr_ptr [1] & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & \A_SPW_TOP|tx_data|Mux5~2_combout ) ) ) ) # ( \A_SPW_TOP|tx_data|Mux5~3_combout  & ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & 
// (\A_SPW_TOP|tx_data|Mux5~0_combout )) # (\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|Mux5~1_combout ))) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux5~3_combout  & ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & 
// (\A_SPW_TOP|tx_data|Mux5~0_combout )) # (\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|Mux5~1_combout ))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datab(!\A_SPW_TOP|tx_data|Mux5~0_combout ),
        .datac(!\A_SPW_TOP|tx_data|Mux5~2_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux5~1_combout ),
        .datae(!\A_SPW_TOP|tx_data|Mux5~3_combout ),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux5~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux5~4 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux5~4 .lut_mask = 64'h227722770A0A5F5F;
defparam \A_SPW_TOP|tx_data|Mux5~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y10_N39
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector271~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector271~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector266~0_combout  & ((\A_SPW_TOP|tx_data|mem[29][3]~q ))) # (\A_SPW_TOP|tx_data|Selector266~0_combout  & (\u0|write_data_fifo_tx|data_out 
// [3])) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector266~0_combout  & ((\A_SPW_TOP|tx_data|mem[29][3]~q ))) # (\A_SPW_TOP|tx_data|Selector266~0_combout  & (\A_SPW_TOP|tx_data|Mux5~20_combout )) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [3]),
        .datac(!\A_SPW_TOP|tx_data|Selector266~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|mem[29][3]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector271~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector271~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector271~0 .lut_mask = 64'h05F505F503F303F3;
defparam \A_SPW_TOP|tx_data|Selector271~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y10_N47
dffeas \A_SPW_TOP|tx_data|mem[29][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector271~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[29][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[29][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[29][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y10_N45
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector235~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector235~0_combout  = ( \A_SPW_TOP|tx_data|Mux5~20_combout  & ( \A_SPW_TOP|tx_data|Selector230~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q ) # (\u0|write_data_fifo_tx|data_out [3]) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|Mux5~20_combout  & ( \A_SPW_TOP|tx_data|Selector230~0_combout  & ( (\u0|write_data_fifo_tx|data_out [3] & \A_SPW_TOP|tx_data|state_data_write.00~q ) ) ) ) # ( \A_SPW_TOP|tx_data|Mux5~20_combout  & ( 
// !\A_SPW_TOP|tx_data|Selector230~0_combout  & ( \A_SPW_TOP|tx_data|mem[25][3]~q  ) ) ) # ( !\A_SPW_TOP|tx_data|Mux5~20_combout  & ( !\A_SPW_TOP|tx_data|Selector230~0_combout  & ( \A_SPW_TOP|tx_data|mem[25][3]~q  ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[25][3]~q ),
        .datab(!\u0|write_data_fifo_tx|data_out [3]),
        .datac(gnd),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(!\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .dataf(!\A_SPW_TOP|tx_data|Selector230~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector235~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector235~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector235~0 .lut_mask = 64'h555555550033FF33;
defparam \A_SPW_TOP|tx_data|Selector235~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X45_Y10_N35
dffeas \A_SPW_TOP|tx_data|mem[25][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector235~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[25][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[25][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[25][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y10_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector127~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector127~0_combout  = ( \A_SPW_TOP|tx_data|mem[13][3]~q  & ( (!\A_SPW_TOP|tx_data|Selector122~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux5~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [3]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[13][3]~q  & ( (\A_SPW_TOP|tx_data|Selector122~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux5~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [3])))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\u0|write_data_fifo_tx|data_out [3]),
        .datac(!\A_SPW_TOP|tx_data|Selector122~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[13][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector127~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector127~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector127~0 .lut_mask = 64'h010B010BF1FBF1FB;
defparam \A_SPW_TOP|tx_data|Selector127~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y10_N14
dffeas \A_SPW_TOP|tx_data|mem[13][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector127~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[13][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[13][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[13][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y10_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector91~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector91~0_combout  = ( \A_SPW_TOP|tx_data|Mux5~20_combout  & ( (!\A_SPW_TOP|tx_data|Selector86~0_combout  & (((\A_SPW_TOP|tx_data|mem[9][3]~q )))) # (\A_SPW_TOP|tx_data|Selector86~0_combout  & 
// ((!\A_SPW_TOP|tx_data|state_data_write.00~q ) # ((\u0|write_data_fifo_tx|data_out [3])))) ) ) # ( !\A_SPW_TOP|tx_data|Mux5~20_combout  & ( (!\A_SPW_TOP|tx_data|Selector86~0_combout  & (((\A_SPW_TOP|tx_data|mem[9][3]~q )))) # 
// (\A_SPW_TOP|tx_data|Selector86~0_combout  & (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [3]))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\u0|write_data_fifo_tx|data_out [3]),
        .datac(!\A_SPW_TOP|tx_data|Selector86~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|mem[9][3]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector91~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector91~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector91~0 .lut_mask = 64'h01F101F10BFB0BFB;
defparam \A_SPW_TOP|tx_data|Selector91~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y10_N11
dffeas \A_SPW_TOP|tx_data|mem[9][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector91~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[9][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[9][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[9][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y10_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux5~6 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux5~6_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [2] & ( \A_SPW_TOP|tx_data|mem[9][3]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & ((\A_SPW_TOP|tx_data|mem[13][3]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|mem[29][3]~q )) ) ) 
// ) # ( !\A_SPW_TOP|tx_data|wr_ptr [2] & ( \A_SPW_TOP|tx_data|mem[9][3]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [4]) # (\A_SPW_TOP|tx_data|mem[25][3]~q ) ) ) ) # ( \A_SPW_TOP|tx_data|wr_ptr [2] & ( !\A_SPW_TOP|tx_data|mem[9][3]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr 
// [4] & ((\A_SPW_TOP|tx_data|mem[13][3]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|mem[29][3]~q )) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [2] & ( !\A_SPW_TOP|tx_data|mem[9][3]~q  & ( (\A_SPW_TOP|tx_data|wr_ptr [4] & 
// \A_SPW_TOP|tx_data|mem[25][3]~q ) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datab(!\A_SPW_TOP|tx_data|mem[29][3]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[25][3]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[13][3]~q ),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .dataf(!\A_SPW_TOP|tx_data|mem[9][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux5~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux5~6 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux5~6 .lut_mask = 64'h050511BBAFAF11BB;
defparam \A_SPW_TOP|tx_data|Mux5~6 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y10_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector253~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector253~0_combout  = ( \A_SPW_TOP|tx_data|mem[27][3]~q  & ( (!\A_SPW_TOP|tx_data|Selector248~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux5~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [3])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[27][3]~q  & ( (\A_SPW_TOP|tx_data|Selector248~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux5~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [3]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [3]),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|tx_data|Selector248~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[27][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector253~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector253~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector253~0 .lut_mask = 64'h00530053FF53FF53;
defparam \A_SPW_TOP|tx_data|Selector253~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y10_N53
dffeas \A_SPW_TOP|tx_data|mem[27][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector253~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[27][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[27][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[27][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y10_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector109~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector109~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( \A_SPW_TOP|tx_data|Selector104~0_combout  & ( \u0|write_data_fifo_tx|data_out [3] ) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( 
// \A_SPW_TOP|tx_data|Selector104~0_combout  & ( \A_SPW_TOP|tx_data|Mux5~20_combout  ) ) ) # ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( !\A_SPW_TOP|tx_data|Selector104~0_combout  & ( \A_SPW_TOP|tx_data|mem[11][3]~q  ) ) ) # ( 
// !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( !\A_SPW_TOP|tx_data|Selector104~0_combout  & ( \A_SPW_TOP|tx_data|mem[11][3]~q  ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|tx_data|mem[11][3]~q ),
        .datac(!\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [3]),
        .datae(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .dataf(!\A_SPW_TOP|tx_data|Selector104~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector109~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector109~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector109~0 .lut_mask = 64'h333333330F0F00FF;
defparam \A_SPW_TOP|tx_data|Selector109~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y10_N14
dffeas \A_SPW_TOP|tx_data|mem[11][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector109~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[11][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[11][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[11][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y10_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector145~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector145~0_combout  = ( \A_SPW_TOP|tx_data|mem[15][3]~q  & ( (!\A_SPW_TOP|tx_data|Selector140~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux5~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [3]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[15][3]~q  & ( (\A_SPW_TOP|tx_data|Selector140~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux5~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [3])))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\u0|write_data_fifo_tx|data_out [3]),
        .datac(!\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .datad(!\A_SPW_TOP|tx_data|Selector140~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[15][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector145~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector145~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector145~0 .lut_mask = 64'h001B001BFF1BFF1B;
defparam \A_SPW_TOP|tx_data|Selector145~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y10_N35
dffeas \A_SPW_TOP|tx_data|mem[15][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector145~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[15][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[15][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[15][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y10_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux5~8 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux5~8_combout  = ( \A_SPW_TOP|tx_data|mem[31][3]~q  & ( \A_SPW_TOP|tx_data|wr_ptr [4] & ( (\A_SPW_TOP|tx_data|wr_ptr [2]) # (\A_SPW_TOP|tx_data|mem[27][3]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[31][3]~q  & ( \A_SPW_TOP|tx_data|wr_ptr 
// [4] & ( (\A_SPW_TOP|tx_data|mem[27][3]~q  & !\A_SPW_TOP|tx_data|wr_ptr [2]) ) ) ) # ( \A_SPW_TOP|tx_data|mem[31][3]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [4] & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|mem[11][3]~q )) # 
// (\A_SPW_TOP|tx_data|wr_ptr [2] & ((\A_SPW_TOP|tx_data|mem[15][3]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[31][3]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [4] & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|mem[11][3]~q )) # (\A_SPW_TOP|tx_data|wr_ptr 
// [2] & ((\A_SPW_TOP|tx_data|mem[15][3]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[27][3]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[11][3]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[15][3]~q ),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datae(!\A_SPW_TOP|tx_data|mem[31][3]~q ),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux5~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux5~8 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux5~8 .lut_mask = 64'h330F330F550055FF;
defparam \A_SPW_TOP|tx_data|Mux5~8 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y11_N45
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector118~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector118~0_combout  = ( \A_SPW_TOP|tx_data|mem[12][3]~q  & ( \A_SPW_TOP|tx_data|Selector113~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux5~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [3]))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[12][3]~q  & ( \A_SPW_TOP|tx_data|Selector113~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux5~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [3]))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[12][3]~q  & ( !\A_SPW_TOP|tx_data|Selector113~0_combout  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [3]),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|tx_data|mem[12][3]~q ),
        .dataf(!\A_SPW_TOP|tx_data|Selector113~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector118~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector118~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector118~0 .lut_mask = 64'h0000FFFF53535353;
defparam \A_SPW_TOP|tx_data|Selector118~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y11_N35
dffeas \A_SPW_TOP|tx_data|mem[12][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector118~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[12][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[12][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[12][3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y10_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector226~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector226~0_combout  = ( \u0|write_data_fifo_tx|data_out [3] & ( (!\A_SPW_TOP|tx_data|Selector221~0_combout  & (((\A_SPW_TOP|tx_data|mem[24][3]~q )))) # (\A_SPW_TOP|tx_data|Selector221~0_combout  & 
// (((\A_SPW_TOP|tx_data|state_data_write.00~q )) # (\A_SPW_TOP|tx_data|Mux5~20_combout ))) ) ) # ( !\u0|write_data_fifo_tx|data_out [3] & ( (!\A_SPW_TOP|tx_data|Selector221~0_combout  & (((\A_SPW_TOP|tx_data|mem[24][3]~q )))) # 
// (\A_SPW_TOP|tx_data|Selector221~0_combout  & (\A_SPW_TOP|tx_data|Mux5~20_combout  & (!\A_SPW_TOP|tx_data|state_data_write.00~q ))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[24][3]~q ),
        .datad(!\A_SPW_TOP|tx_data|Selector221~0_combout ),
        .datae(!\u0|write_data_fifo_tx|data_out [3]),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector226~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector226~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector226~0 .lut_mask = 64'h0F440F770F440F77;
defparam \A_SPW_TOP|tx_data|Selector226~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y10_N50
dffeas \A_SPW_TOP|tx_data|mem[24][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector226~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[24][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[24][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[24][3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y10_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector82~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector82~0_combout  = ( \A_SPW_TOP|tx_data|Selector77~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux5~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out 
// [3]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector77~0_combout  & ( \A_SPW_TOP|tx_data|mem[8][3]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[8][3]~q ),
        .datad(!\u0|write_data_fifo_tx|data_out [3]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector77~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector82~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector82~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector82~0 .lut_mask = 64'h0F0F0F0F44774477;
defparam \A_SPW_TOP|tx_data|Selector82~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y10_N59
dffeas \A_SPW_TOP|tx_data|mem[8][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector82~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[8][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[8][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[8][3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y10_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector262~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector262~0_combout  = ( \A_SPW_TOP|tx_data|mem[28][3]~q  & ( (!\A_SPW_TOP|tx_data|Selector257~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux5~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [3])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[28][3]~q  & ( (\A_SPW_TOP|tx_data|Selector257~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux5~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [3]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector257~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [3]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[28][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector262~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector262~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector262~0 .lut_mask = 64'h04070407F4F7F4F7;
defparam \A_SPW_TOP|tx_data|Selector262~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y10_N17
dffeas \A_SPW_TOP|tx_data|mem[28][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector262~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[28][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[28][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[28][3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y10_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux5~5 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux5~5_combout  = ( \A_SPW_TOP|tx_data|mem[8][3]~q  & ( \A_SPW_TOP|tx_data|mem[28][3]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & (((!\A_SPW_TOP|tx_data|wr_ptr [4]) # (\A_SPW_TOP|tx_data|mem[24][3]~q )))) # (\A_SPW_TOP|tx_data|wr_ptr [2] & 
// (((\A_SPW_TOP|tx_data|wr_ptr [4])) # (\A_SPW_TOP|tx_data|mem[12][3]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[8][3]~q  & ( \A_SPW_TOP|tx_data|mem[28][3]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & (((\A_SPW_TOP|tx_data|mem[24][3]~q  & \A_SPW_TOP|tx_data|wr_ptr 
// [4])))) # (\A_SPW_TOP|tx_data|wr_ptr [2] & (((\A_SPW_TOP|tx_data|wr_ptr [4])) # (\A_SPW_TOP|tx_data|mem[12][3]~q ))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[8][3]~q  & ( !\A_SPW_TOP|tx_data|mem[28][3]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & 
// (((!\A_SPW_TOP|tx_data|wr_ptr [4]) # (\A_SPW_TOP|tx_data|mem[24][3]~q )))) # (\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|mem[12][3]~q  & ((!\A_SPW_TOP|tx_data|wr_ptr [4])))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[8][3]~q  & ( 
// !\A_SPW_TOP|tx_data|mem[28][3]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & (((\A_SPW_TOP|tx_data|mem[24][3]~q  & \A_SPW_TOP|tx_data|wr_ptr [4])))) # (\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|mem[12][3]~q  & ((!\A_SPW_TOP|tx_data|wr_ptr [4])))) ) ) 
// )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datab(!\A_SPW_TOP|tx_data|mem[12][3]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[24][3]~q ),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datae(!\A_SPW_TOP|tx_data|mem[8][3]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[28][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux5~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux5~5 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux5~5 .lut_mask = 64'h110ABB0A115FBB5F;
defparam \A_SPW_TOP|tx_data|Mux5~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y11_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector280~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector280~0_combout  = ( \A_SPW_TOP|tx_data|mem[30][3]~q  & ( (!\A_SPW_TOP|tx_data|Selector275~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux5~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [3]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[30][3]~q  & ( (\A_SPW_TOP|tx_data|Selector275~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux5~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [3])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [3]),
        .datab(!\A_SPW_TOP|tx_data|Selector275~0_combout ),
        .datac(!\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[30][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector280~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector280~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector280~0 .lut_mask = 64'h03110311CFDDCFDD;
defparam \A_SPW_TOP|tx_data|Selector280~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y11_N8
dffeas \A_SPW_TOP|tx_data|mem[30][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector280~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[30][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[30][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[30][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y10_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector100~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector100~0_combout  = ( \A_SPW_TOP|tx_data|Selector95~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux5~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\u0|write_data_fifo_tx|data_out [3])) ) ) # ( !\A_SPW_TOP|tx_data|Selector95~0_combout  & ( \A_SPW_TOP|tx_data|mem[10][3]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\u0|write_data_fifo_tx|data_out [3]),
        .datac(!\A_SPW_TOP|tx_data|mem[10][3]~q ),
        .datad(!\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .datae(!\A_SPW_TOP|tx_data|Selector95~0_combout ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector100~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector100~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector100~0 .lut_mask = 64'h0F0F11BB0F0F11BB;
defparam \A_SPW_TOP|tx_data|Selector100~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X45_Y10_N2
dffeas \A_SPW_TOP|tx_data|mem[10][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector100~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[10][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[10][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[10][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y11_N39
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector136~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector136~0_combout  = ( \A_SPW_TOP|tx_data|mem[14][3]~q  & ( (!\A_SPW_TOP|tx_data|Selector131~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux5~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [3])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[14][3]~q  & ( (\A_SPW_TOP|tx_data|Selector131~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux5~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [3]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector131~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [3]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[14][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector136~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector136~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector136~0 .lut_mask = 64'h04070407F4F7F4F7;
defparam \A_SPW_TOP|tx_data|Selector136~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y11_N53
dffeas \A_SPW_TOP|tx_data|mem[14][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector136~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[14][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[14][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[14][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y10_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector244~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector244~0_combout  = ( \A_SPW_TOP|tx_data|mem[26][3]~q  & ( (!\A_SPW_TOP|tx_data|Selector239~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux5~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [3]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[26][3]~q  & ( (\A_SPW_TOP|tx_data|Selector239~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux5~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [3])))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\u0|write_data_fifo_tx|data_out [3]),
        .datac(!\A_SPW_TOP|tx_data|Selector239~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[26][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector244~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector244~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector244~0 .lut_mask = 64'h010B010BF1FBF1FB;
defparam \A_SPW_TOP|tx_data|Selector244~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y10_N11
dffeas \A_SPW_TOP|tx_data|mem[26][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector244~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[26][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[26][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[26][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y10_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux5~7 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux5~7_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [2] & ( \A_SPW_TOP|tx_data|mem[26][3]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & ((\A_SPW_TOP|tx_data|mem[14][3]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|mem[30][3]~q )) ) 
// ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [2] & ( \A_SPW_TOP|tx_data|mem[26][3]~q  & ( (\A_SPW_TOP|tx_data|wr_ptr [4]) # (\A_SPW_TOP|tx_data|mem[10][3]~q ) ) ) ) # ( \A_SPW_TOP|tx_data|wr_ptr [2] & ( !\A_SPW_TOP|tx_data|mem[26][3]~q  & ( 
// (!\A_SPW_TOP|tx_data|wr_ptr [4] & ((\A_SPW_TOP|tx_data|mem[14][3]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|mem[30][3]~q )) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [2] & ( !\A_SPW_TOP|tx_data|mem[26][3]~q  & ( 
// (\A_SPW_TOP|tx_data|mem[10][3]~q  & !\A_SPW_TOP|tx_data|wr_ptr [4]) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[30][3]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[10][3]~q ),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datad(!\A_SPW_TOP|tx_data|mem[14][3]~q ),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .dataf(!\A_SPW_TOP|tx_data|mem[26][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux5~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux5~7 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux5~7 .lut_mask = 64'h303005F53F3F05F5;
defparam \A_SPW_TOP|tx_data|Mux5~7 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y10_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux5~9 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux5~9_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [1] & ( \A_SPW_TOP|tx_data|Mux5~7_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [0]) # (\A_SPW_TOP|tx_data|Mux5~8_combout ) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( 
// \A_SPW_TOP|tx_data|Mux5~7_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|Mux5~5_combout ))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|Mux5~6_combout )) ) ) ) # ( \A_SPW_TOP|tx_data|wr_ptr [1] & ( 
// !\A_SPW_TOP|tx_data|Mux5~7_combout  & ( (\A_SPW_TOP|tx_data|wr_ptr [0] & \A_SPW_TOP|tx_data|Mux5~8_combout ) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( !\A_SPW_TOP|tx_data|Mux5~7_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & 
// ((\A_SPW_TOP|tx_data|Mux5~5_combout ))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|Mux5~6_combout )) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datab(!\A_SPW_TOP|tx_data|Mux5~6_combout ),
        .datac(!\A_SPW_TOP|tx_data|Mux5~8_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux5~5_combout ),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .dataf(!\A_SPW_TOP|tx_data|Mux5~7_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux5~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux5~9 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux5~9 .lut_mask = 64'h11BB050511BBAFAF;
defparam \A_SPW_TOP|tx_data|Mux5~9 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y10_N39
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector388~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector388~0_combout  = ( \u0|write_data_fifo_tx|data_out [3] & ( (!\A_SPW_TOP|tx_data|Selector383~0_combout  & (((\A_SPW_TOP|tx_data|mem[42][3]~q )))) # (\A_SPW_TOP|tx_data|Selector383~0_combout  & 
// (((\A_SPW_TOP|tx_data|state_data_write.00~q )) # (\A_SPW_TOP|tx_data|Mux5~20_combout ))) ) ) # ( !\u0|write_data_fifo_tx|data_out [3] & ( (!\A_SPW_TOP|tx_data|Selector383~0_combout  & (((\A_SPW_TOP|tx_data|mem[42][3]~q )))) # 
// (\A_SPW_TOP|tx_data|Selector383~0_combout  & (\A_SPW_TOP|tx_data|Mux5~20_combout  & (!\A_SPW_TOP|tx_data|state_data_write.00~q ))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector383~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|mem[42][3]~q ),
        .datae(gnd),
        .dataf(!\u0|write_data_fifo_tx|data_out [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector388~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector388~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector388~0 .lut_mask = 64'h04F404F407F707F7;
defparam \A_SPW_TOP|tx_data|Selector388~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y10_N29
dffeas \A_SPW_TOP|tx_data|mem[42][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector388~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[42][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[42][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[42][3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y10_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector370~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector370~0_combout  = ( \A_SPW_TOP|tx_data|mem[40][3]~q  & ( (!\A_SPW_TOP|tx_data|Selector365~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux5~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [3])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[40][3]~q  & ( (\A_SPW_TOP|tx_data|Selector365~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux5~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [3]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\u0|write_data_fifo_tx|data_out [3]),
        .datad(!\A_SPW_TOP|tx_data|Selector365~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[40][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector370~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector370~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector370~0 .lut_mask = 64'h00470047FF47FF47;
defparam \A_SPW_TOP|tx_data|Selector370~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y10_N11
dffeas \A_SPW_TOP|tx_data|mem[40][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector370~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[40][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[40][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[40][3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y10_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector532~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector532~0_combout  = ( \u0|write_data_fifo_tx|data_out [3] & ( (!\A_SPW_TOP|tx_data|Selector527~0_combout  & (((\A_SPW_TOP|tx_data|mem[58][3]~q )))) # (\A_SPW_TOP|tx_data|Selector527~0_combout  & 
// (((\A_SPW_TOP|tx_data|state_data_write.00~q )) # (\A_SPW_TOP|tx_data|Mux5~20_combout ))) ) ) # ( !\u0|write_data_fifo_tx|data_out [3] & ( (!\A_SPW_TOP|tx_data|Selector527~0_combout  & (((\A_SPW_TOP|tx_data|mem[58][3]~q )))) # 
// (\A_SPW_TOP|tx_data|Selector527~0_combout  & (\A_SPW_TOP|tx_data|Mux5~20_combout  & (!\A_SPW_TOP|tx_data|state_data_write.00~q ))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector527~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|mem[58][3]~q ),
        .datae(gnd),
        .dataf(!\u0|write_data_fifo_tx|data_out [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector532~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector532~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector532~0 .lut_mask = 64'h04F404F407F707F7;
defparam \A_SPW_TOP|tx_data|Selector532~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y10_N23
dffeas \A_SPW_TOP|tx_data|mem[58][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector532~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[58][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[58][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[58][3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y10_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector514~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector514~0_combout  = ( \u0|write_data_fifo_tx|data_out [3] & ( (!\A_SPW_TOP|tx_data|Selector509~0_combout  & (\A_SPW_TOP|tx_data|mem[56][3]~q )) # (\A_SPW_TOP|tx_data|Selector509~0_combout  & 
// (((\A_SPW_TOP|tx_data|state_data_write.00~q ) # (\A_SPW_TOP|tx_data|Mux5~20_combout )))) ) ) # ( !\u0|write_data_fifo_tx|data_out [3] & ( (!\A_SPW_TOP|tx_data|Selector509~0_combout  & (\A_SPW_TOP|tx_data|mem[56][3]~q )) # 
// (\A_SPW_TOP|tx_data|Selector509~0_combout  & (((\A_SPW_TOP|tx_data|Mux5~20_combout  & !\A_SPW_TOP|tx_data|state_data_write.00~q )))) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[56][3]~q ),
        .datab(!\A_SPW_TOP|tx_data|Selector509~0_combout ),
        .datac(!\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(!\u0|write_data_fifo_tx|data_out [3]),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector514~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector514~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector514~0 .lut_mask = 64'h4744477747444777;
defparam \A_SPW_TOP|tx_data|Selector514~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y10_N35
dffeas \A_SPW_TOP|tx_data|mem[56][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector514~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[56][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[56][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[56][3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y10_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux5~15 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux5~15_combout  = ( \A_SPW_TOP|tx_data|mem[58][3]~q  & ( \A_SPW_TOP|tx_data|mem[56][3]~q  & ( ((!\A_SPW_TOP|tx_data|wr_ptr [1] & ((\A_SPW_TOP|tx_data|mem[40][3]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|mem[42][3]~q 
// ))) # (\A_SPW_TOP|tx_data|wr_ptr [4]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[58][3]~q  & ( \A_SPW_TOP|tx_data|mem[56][3]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & ((!\A_SPW_TOP|tx_data|wr_ptr [1] & ((\A_SPW_TOP|tx_data|mem[40][3]~q ))) # 
// (\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|mem[42][3]~q )))) # (\A_SPW_TOP|tx_data|wr_ptr [4] & (!\A_SPW_TOP|tx_data|wr_ptr [1])) ) ) ) # ( \A_SPW_TOP|tx_data|mem[58][3]~q  & ( !\A_SPW_TOP|tx_data|mem[56][3]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr 
// [4] & ((!\A_SPW_TOP|tx_data|wr_ptr [1] & ((\A_SPW_TOP|tx_data|mem[40][3]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|mem[42][3]~q )))) # (\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|wr_ptr [1])) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|mem[58][3]~q  & ( !\A_SPW_TOP|tx_data|mem[56][3]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & ((!\A_SPW_TOP|tx_data|wr_ptr [1] & ((\A_SPW_TOP|tx_data|mem[40][3]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|mem[42][3]~q )))) 
// ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datac(!\A_SPW_TOP|tx_data|mem[42][3]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[40][3]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[58][3]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[56][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux5~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux5~15 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux5~15 .lut_mask = 64'h028A139B46CE57DF;
defparam \A_SPW_TOP|tx_data|Mux5~15 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y10_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector415~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector415~0_combout  = ( \A_SPW_TOP|tx_data|Selector410~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux5~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [3]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector410~0_combout  & ( \A_SPW_TOP|tx_data|mem[45][3]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[45][3]~q ),
        .datad(!\u0|write_data_fifo_tx|data_out [3]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector410~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector415~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector415~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector415~0 .lut_mask = 64'h0F0F0F0F44774477;
defparam \A_SPW_TOP|tx_data|Selector415~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y10_N29
dffeas \A_SPW_TOP|tx_data|mem[45][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector415~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[45][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[45][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[45][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y10_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector577~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector577~0_combout  = ( \A_SPW_TOP|tx_data|mem[63][3]~q  & ( (!\A_SPW_TOP|tx_data|Selector572~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux5~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [3])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[63][3]~q  & ( (\A_SPW_TOP|tx_data|Selector572~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux5~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [3]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector572~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [3]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[63][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector577~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector577~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector577~0 .lut_mask = 64'h04070407F4F7F4F7;
defparam \A_SPW_TOP|tx_data|Selector577~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y10_N11
dffeas \A_SPW_TOP|tx_data|mem[63][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector577~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[63][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[63][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[63][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y10_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector559~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector559~0_combout  = ( \u0|write_data_fifo_tx|data_out [3] & ( (!\A_SPW_TOP|tx_data|Selector554~0_combout  & (((\A_SPW_TOP|tx_data|mem[61][3]~q )))) # (\A_SPW_TOP|tx_data|Selector554~0_combout  & 
// (((\A_SPW_TOP|tx_data|state_data_write.00~q )) # (\A_SPW_TOP|tx_data|Mux5~20_combout ))) ) ) # ( !\u0|write_data_fifo_tx|data_out [3] & ( (!\A_SPW_TOP|tx_data|Selector554~0_combout  & (((\A_SPW_TOP|tx_data|mem[61][3]~q )))) # 
// (\A_SPW_TOP|tx_data|Selector554~0_combout  & (\A_SPW_TOP|tx_data|Mux5~20_combout  & (!\A_SPW_TOP|tx_data|state_data_write.00~q ))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector554~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|mem[61][3]~q ),
        .datae(gnd),
        .dataf(!\u0|write_data_fifo_tx|data_out [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector559~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector559~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector559~0 .lut_mask = 64'h04F404F407F707F7;
defparam \A_SPW_TOP|tx_data|Selector559~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y10_N23
dffeas \A_SPW_TOP|tx_data|mem[61][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector559~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[61][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[61][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[61][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y10_N15
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector433~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector433~0_combout  = ( \A_SPW_TOP|tx_data|mem[47][3]~q  & ( (!\A_SPW_TOP|tx_data|Selector428~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux5~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [3])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[47][3]~q  & ( (\A_SPW_TOP|tx_data|Selector428~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux5~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [3]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector428~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [3]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[47][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector433~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector433~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector433~0 .lut_mask = 64'h04070407F4F7F4F7;
defparam \A_SPW_TOP|tx_data|Selector433~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y10_N20
dffeas \A_SPW_TOP|tx_data|mem[47][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector433~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[47][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[47][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[47][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y10_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux5~18 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux5~18_combout  = ( \A_SPW_TOP|tx_data|mem[61][3]~q  & ( \A_SPW_TOP|tx_data|mem[47][3]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & (((\A_SPW_TOP|tx_data|wr_ptr [1])) # (\A_SPW_TOP|tx_data|mem[45][3]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [4] 
// & (((!\A_SPW_TOP|tx_data|wr_ptr [1]) # (\A_SPW_TOP|tx_data|mem[63][3]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[61][3]~q  & ( \A_SPW_TOP|tx_data|mem[47][3]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & (((\A_SPW_TOP|tx_data|wr_ptr [1])) # 
// (\A_SPW_TOP|tx_data|mem[45][3]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [4] & (((\A_SPW_TOP|tx_data|wr_ptr [1] & \A_SPW_TOP|tx_data|mem[63][3]~q )))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[61][3]~q  & ( !\A_SPW_TOP|tx_data|mem[47][3]~q  & ( 
// (!\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|mem[45][3]~q  & (!\A_SPW_TOP|tx_data|wr_ptr [1]))) # (\A_SPW_TOP|tx_data|wr_ptr [4] & (((!\A_SPW_TOP|tx_data|wr_ptr [1]) # (\A_SPW_TOP|tx_data|mem[63][3]~q )))) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|mem[61][3]~q  & ( !\A_SPW_TOP|tx_data|mem[47][3]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|mem[45][3]~q  & (!\A_SPW_TOP|tx_data|wr_ptr [1]))) # (\A_SPW_TOP|tx_data|wr_ptr [4] & (((\A_SPW_TOP|tx_data|wr_ptr [1] & 
// \A_SPW_TOP|tx_data|mem[63][3]~q )))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[45][3]~q ),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datad(!\A_SPW_TOP|tx_data|mem[63][3]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[61][3]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[47][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux5~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux5~18 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux5~18 .lut_mask = 64'h404370734C4F7C7F;
defparam \A_SPW_TOP|tx_data|Mux5~18 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y10_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector406~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector406~0_combout  = ( \A_SPW_TOP|tx_data|Selector401~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux5~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [3]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector401~0_combout  & ( \A_SPW_TOP|tx_data|mem[44][3]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[44][3]~q ),
        .datad(!\u0|write_data_fifo_tx|data_out [3]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector401~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector406~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector406~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector406~0 .lut_mask = 64'h0F0F0F0F44774477;
defparam \A_SPW_TOP|tx_data|Selector406~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y10_N53
dffeas \A_SPW_TOP|tx_data|mem[44][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector406~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[44][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[44][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[44][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y10_N21
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector550~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector550~0_combout  = ( \A_SPW_TOP|tx_data|mem[60][3]~q  & ( (!\A_SPW_TOP|tx_data|Selector545~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux5~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [3]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[60][3]~q  & ( (\A_SPW_TOP|tx_data|Selector545~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux5~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [3])))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\u0|write_data_fifo_tx|data_out [3]),
        .datac(!\A_SPW_TOP|tx_data|Selector545~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[60][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector550~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector550~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector550~0 .lut_mask = 64'h010B010BF1FBF1FB;
defparam \A_SPW_TOP|tx_data|Selector550~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y10_N17
dffeas \A_SPW_TOP|tx_data|mem[60][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector550~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[60][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[60][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[60][3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y10_N45
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector568~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector568~0_combout  = ( \A_SPW_TOP|tx_data|mem[62][3]~q  & ( (!\A_SPW_TOP|tx_data|Selector563~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux5~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [3])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[62][3]~q  & ( (\A_SPW_TOP|tx_data|Selector563~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux5~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [3]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector563~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [3]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[62][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector568~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector568~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector568~0 .lut_mask = 64'h04070407F4F7F4F7;
defparam \A_SPW_TOP|tx_data|Selector568~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y10_N53
dffeas \A_SPW_TOP|tx_data|mem[62][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector568~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[62][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[62][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[62][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y10_N45
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector424~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector424~0_combout  = ( \A_SPW_TOP|tx_data|mem[46][3]~q  & ( (!\A_SPW_TOP|tx_data|Selector419~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux5~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [3])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[46][3]~q  & ( (\A_SPW_TOP|tx_data|Selector419~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux5~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [3]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector419~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [3]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[46][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector424~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector424~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector424~0 .lut_mask = 64'h04070407F4F7F4F7;
defparam \A_SPW_TOP|tx_data|Selector424~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y10_N41
dffeas \A_SPW_TOP|tx_data|mem[46][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector424~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[46][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[46][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[46][3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y10_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux5~17 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux5~17_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [1] & ( \A_SPW_TOP|tx_data|mem[46][3]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [4]) # (\A_SPW_TOP|tx_data|mem[62][3]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( 
// \A_SPW_TOP|tx_data|mem[46][3]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|mem[44][3]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [4] & ((\A_SPW_TOP|tx_data|mem[60][3]~q ))) ) ) ) # ( \A_SPW_TOP|tx_data|wr_ptr [1] & ( 
// !\A_SPW_TOP|tx_data|mem[46][3]~q  & ( (\A_SPW_TOP|tx_data|mem[62][3]~q  & \A_SPW_TOP|tx_data|wr_ptr [4]) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( !\A_SPW_TOP|tx_data|mem[46][3]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|mem[44][3]~q 
// )) # (\A_SPW_TOP|tx_data|wr_ptr [4] & ((\A_SPW_TOP|tx_data|mem[60][3]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[44][3]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[60][3]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[62][3]~q ),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .dataf(!\A_SPW_TOP|tx_data|mem[46][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux5~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux5~17 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux5~17 .lut_mask = 64'h5533000F5533FF0F;
defparam \A_SPW_TOP|tx_data|Mux5~17 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y10_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector523~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector523~0_combout  = ( \A_SPW_TOP|tx_data|Selector518~0_combout  & ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( \u0|write_data_fifo_tx|data_out [3] ) ) ) # ( !\A_SPW_TOP|tx_data|Selector518~0_combout  & ( 
// \A_SPW_TOP|tx_data|state_data_write.00~q  & ( \A_SPW_TOP|tx_data|mem[57][3]~q  ) ) ) # ( \A_SPW_TOP|tx_data|Selector518~0_combout  & ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( \A_SPW_TOP|tx_data|Mux5~20_combout  ) ) ) # ( 
// !\A_SPW_TOP|tx_data|Selector518~0_combout  & ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( \A_SPW_TOP|tx_data|mem[57][3]~q  ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[57][3]~q ),
        .datab(!\u0|write_data_fifo_tx|data_out [3]),
        .datac(!\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|tx_data|Selector518~0_combout ),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector523~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector523~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector523~0 .lut_mask = 64'h55550F0F55553333;
defparam \A_SPW_TOP|tx_data|Selector523~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X45_Y10_N26
dffeas \A_SPW_TOP|tx_data|mem[57][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector523~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[57][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[57][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[57][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y10_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector397~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector397~0_combout  = ( \A_SPW_TOP|tx_data|Selector392~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux5~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\u0|write_data_fifo_tx|data_out [3])) ) ) # ( !\A_SPW_TOP|tx_data|Selector392~0_combout  & ( \A_SPW_TOP|tx_data|mem[43][3]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\u0|write_data_fifo_tx|data_out [3]),
        .datac(!\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .datad(!\A_SPW_TOP|tx_data|mem[43][3]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector392~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector397~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector397~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector397~0 .lut_mask = 64'h00FF00FF1B1B1B1B;
defparam \A_SPW_TOP|tx_data|Selector397~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y10_N29
dffeas \A_SPW_TOP|tx_data|mem[43][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector397~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[43][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[43][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[43][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y10_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector541~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector541~0_combout  = ( \A_SPW_TOP|tx_data|Selector536~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux5~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [3]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector536~0_combout  & ( \A_SPW_TOP|tx_data|mem[59][3]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[59][3]~q ),
        .datad(!\u0|write_data_fifo_tx|data_out [3]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector536~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector541~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector541~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector541~0 .lut_mask = 64'h0F0F0F0F44774477;
defparam \A_SPW_TOP|tx_data|Selector541~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y10_N38
dffeas \A_SPW_TOP|tx_data|mem[59][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector541~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[59][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[59][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[59][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y10_N57
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector379~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector379~0_combout  = ( \A_SPW_TOP|tx_data|mem[41][3]~q  & ( (!\A_SPW_TOP|tx_data|Selector374~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux5~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [3])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[41][3]~q  & ( (\A_SPW_TOP|tx_data|Selector374~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux5~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [3]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\u0|write_data_fifo_tx|data_out [3]),
        .datad(!\A_SPW_TOP|tx_data|Selector374~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[41][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector379~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector379~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector379~0 .lut_mask = 64'h00470047FF47FF47;
defparam \A_SPW_TOP|tx_data|Selector379~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y10_N35
dffeas \A_SPW_TOP|tx_data|mem[41][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector379~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[41][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[41][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[41][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y10_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux5~16 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux5~16_combout  = ( \A_SPW_TOP|tx_data|mem[59][3]~q  & ( \A_SPW_TOP|tx_data|mem[41][3]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & (((!\A_SPW_TOP|tx_data|wr_ptr [1]) # (\A_SPW_TOP|tx_data|mem[43][3]~q )))) # (\A_SPW_TOP|tx_data|wr_ptr [4] 
// & (((\A_SPW_TOP|tx_data|wr_ptr [1])) # (\A_SPW_TOP|tx_data|mem[57][3]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[59][3]~q  & ( \A_SPW_TOP|tx_data|mem[41][3]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & (((!\A_SPW_TOP|tx_data|wr_ptr [1]) # 
// (\A_SPW_TOP|tx_data|mem[43][3]~q )))) # (\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|mem[57][3]~q  & (!\A_SPW_TOP|tx_data|wr_ptr [1]))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[59][3]~q  & ( !\A_SPW_TOP|tx_data|mem[41][3]~q  & ( 
// (!\A_SPW_TOP|tx_data|wr_ptr [4] & (((\A_SPW_TOP|tx_data|wr_ptr [1] & \A_SPW_TOP|tx_data|mem[43][3]~q )))) # (\A_SPW_TOP|tx_data|wr_ptr [4] & (((\A_SPW_TOP|tx_data|wr_ptr [1])) # (\A_SPW_TOP|tx_data|mem[57][3]~q ))) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|mem[59][3]~q  & ( !\A_SPW_TOP|tx_data|mem[41][3]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & (((\A_SPW_TOP|tx_data|wr_ptr [1] & \A_SPW_TOP|tx_data|mem[43][3]~q )))) # (\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|mem[57][3]~q  & 
// (!\A_SPW_TOP|tx_data|wr_ptr [1]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[57][3]~q ),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datad(!\A_SPW_TOP|tx_data|mem[43][3]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[59][3]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[41][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux5~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux5~16 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux5~16 .lut_mask = 64'h101C131FD0DCD3DF;
defparam \A_SPW_TOP|tx_data|Mux5~16 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y10_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux5~19 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux5~19_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [0] & ( \A_SPW_TOP|tx_data|Mux5~16_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [2]) # (\A_SPW_TOP|tx_data|Mux5~18_combout ) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [0] & ( 
// \A_SPW_TOP|tx_data|Mux5~16_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|Mux5~15_combout )) # (\A_SPW_TOP|tx_data|wr_ptr [2] & ((\A_SPW_TOP|tx_data|Mux5~17_combout ))) ) ) ) # ( \A_SPW_TOP|tx_data|wr_ptr [0] & ( 
// !\A_SPW_TOP|tx_data|Mux5~16_combout  & ( (\A_SPW_TOP|tx_data|Mux5~18_combout  & \A_SPW_TOP|tx_data|wr_ptr [2]) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [0] & ( !\A_SPW_TOP|tx_data|Mux5~16_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & 
// (\A_SPW_TOP|tx_data|Mux5~15_combout )) # (\A_SPW_TOP|tx_data|wr_ptr [2] & ((\A_SPW_TOP|tx_data|Mux5~17_combout ))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux5~15_combout ),
        .datab(!\A_SPW_TOP|tx_data|Mux5~18_combout ),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datad(!\A_SPW_TOP|tx_data|Mux5~17_combout ),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .dataf(!\A_SPW_TOP|tx_data|Mux5~16_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux5~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux5~19 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux5~19 .lut_mask = 64'h505F0303505FF3F3;
defparam \A_SPW_TOP|tx_data|Mux5~19 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y10_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux5~20 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux5~20_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [3] & ( \A_SPW_TOP|tx_data|Mux5~19_combout  & ( (\A_SPW_TOP|tx_data|wr_ptr [5]) # (\A_SPW_TOP|tx_data|Mux5~9_combout ) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [3] & ( 
// \A_SPW_TOP|tx_data|Mux5~19_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [5] & ((\A_SPW_TOP|tx_data|Mux5~4_combout ))) # (\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|Mux5~14_combout )) ) ) ) # ( \A_SPW_TOP|tx_data|wr_ptr [3] & ( 
// !\A_SPW_TOP|tx_data|Mux5~19_combout  & ( (\A_SPW_TOP|tx_data|Mux5~9_combout  & !\A_SPW_TOP|tx_data|wr_ptr [5]) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [3] & ( !\A_SPW_TOP|tx_data|Mux5~19_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [5] & 
// ((\A_SPW_TOP|tx_data|Mux5~4_combout ))) # (\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|Mux5~14_combout )) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux5~14_combout ),
        .datab(!\A_SPW_TOP|tx_data|Mux5~4_combout ),
        .datac(!\A_SPW_TOP|tx_data|Mux5~9_combout ),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .dataf(!\A_SPW_TOP|tx_data|Mux5~19_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux5~20 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux5~20 .lut_mask = 64'h33550F0033550FFF;
defparam \A_SPW_TOP|tx_data|Mux5~20 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y10_N57
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector289~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector289~0_combout  = ( \A_SPW_TOP|tx_data|Mux5~20_combout  & ( (!\A_SPW_TOP|tx_data|Selector284~0_combout  & (((\A_SPW_TOP|tx_data|mem[31][3]~q )))) # (\A_SPW_TOP|tx_data|Selector284~0_combout  & 
// ((!\A_SPW_TOP|tx_data|state_data_write.00~q ) # ((\u0|write_data_fifo_tx|data_out [3])))) ) ) # ( !\A_SPW_TOP|tx_data|Mux5~20_combout  & ( (!\A_SPW_TOP|tx_data|Selector284~0_combout  & (((\A_SPW_TOP|tx_data|mem[31][3]~q )))) # 
// (\A_SPW_TOP|tx_data|Selector284~0_combout  & (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [3]))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\u0|write_data_fifo_tx|data_out [3]),
        .datac(!\A_SPW_TOP|tx_data|mem[31][3]~q ),
        .datad(!\A_SPW_TOP|tx_data|Selector284~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Mux5~20_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector289~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector289~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector289~0 .lut_mask = 64'h0F110F110FBB0FBB;
defparam \A_SPW_TOP|tx_data|Selector289~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y10_N8
dffeas \A_SPW_TOP|tx_data|mem[31][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector289~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[31][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[31][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[31][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y10_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux14~8 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux14~8_combout  = ( \A_SPW_TOP|tx_data|rd_ptr [2] & ( \A_SPW_TOP|tx_data|mem[25][3]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [1] & ((\A_SPW_TOP|tx_data|mem[29][3]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|mem[31][3]~q )) ) 
// ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [2] & ( \A_SPW_TOP|tx_data|mem[25][3]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [1]) # (\A_SPW_TOP|tx_data|mem[27][3]~q ) ) ) ) # ( \A_SPW_TOP|tx_data|rd_ptr [2] & ( !\A_SPW_TOP|tx_data|mem[25][3]~q  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [1] & ((\A_SPW_TOP|tx_data|mem[29][3]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|mem[31][3]~q )) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [2] & ( !\A_SPW_TOP|tx_data|mem[25][3]~q  & ( (\A_SPW_TOP|tx_data|rd_ptr 
// [1] & \A_SPW_TOP|tx_data|mem[27][3]~q ) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .datab(!\A_SPW_TOP|tx_data|mem[31][3]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[27][3]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[29][3]~q ),
        .datae(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .dataf(!\A_SPW_TOP|tx_data|mem[25][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux14~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux14~8 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux14~8 .lut_mask = 64'h050511BBAFAF11BB;
defparam \A_SPW_TOP|tx_data|Mux14~8 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y10_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux14~7 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux14~7_combout  = ( \A_SPW_TOP|tx_data|mem[24][3]~q  & ( \A_SPW_TOP|tx_data|rd_ptr [1] & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[26][3]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [2] & ((\A_SPW_TOP|tx_data|mem[30][3]~q ))) ) 
// ) ) # ( !\A_SPW_TOP|tx_data|mem[24][3]~q  & ( \A_SPW_TOP|tx_data|rd_ptr [1] & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[26][3]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [2] & ((\A_SPW_TOP|tx_data|mem[30][3]~q ))) ) ) ) # ( 
// \A_SPW_TOP|tx_data|mem[24][3]~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [1] & ( (!\A_SPW_TOP|tx_data|rd_ptr [2]) # (\A_SPW_TOP|tx_data|mem[28][3]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[24][3]~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [1] & ( 
// (\A_SPW_TOP|tx_data|mem[28][3]~q  & \A_SPW_TOP|tx_data|rd_ptr [2]) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[28][3]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[26][3]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[30][3]~q ),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .datae(!\A_SPW_TOP|tx_data|mem[24][3]~q ),
        .dataf(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux14~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux14~7 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux14~7 .lut_mask = 64'h0055FF55330F330F;
defparam \A_SPW_TOP|tx_data|Mux14~7 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y10_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux14~6 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux14~6_combout  = ( \A_SPW_TOP|tx_data|rd_ptr [2] & ( \A_SPW_TOP|tx_data|mem[15][3]~q  & ( (\A_SPW_TOP|tx_data|rd_ptr [1]) # (\A_SPW_TOP|tx_data|mem[13][3]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [2] & ( 
// \A_SPW_TOP|tx_data|mem[15][3]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|mem[9][3]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [1] & ((\A_SPW_TOP|tx_data|mem[11][3]~q ))) ) ) ) # ( \A_SPW_TOP|tx_data|rd_ptr [2] & ( !\A_SPW_TOP|tx_data|mem[15][3]~q 
//  & ( (\A_SPW_TOP|tx_data|mem[13][3]~q  & !\A_SPW_TOP|tx_data|rd_ptr [1]) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [2] & ( !\A_SPW_TOP|tx_data|mem[15][3]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|mem[9][3]~q )) # (\A_SPW_TOP|tx_data|rd_ptr 
// [1] & ((\A_SPW_TOP|tx_data|mem[11][3]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[9][3]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[13][3]~q ),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .datad(!\A_SPW_TOP|tx_data|mem[11][3]~q ),
        .datae(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .dataf(!\A_SPW_TOP|tx_data|mem[15][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux14~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux14~6 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux14~6 .lut_mask = 64'h505F3030505F3F3F;
defparam \A_SPW_TOP|tx_data|Mux14~6 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y10_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux14~5 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux14~5_combout  = ( \A_SPW_TOP|tx_data|rd_ptr [1] & ( \A_SPW_TOP|tx_data|rd_ptr [2] & ( \A_SPW_TOP|tx_data|mem[14][3]~q  ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [1] & ( \A_SPW_TOP|tx_data|rd_ptr [2] & ( \A_SPW_TOP|tx_data|mem[12][3]~q  ) 
// ) ) # ( \A_SPW_TOP|tx_data|rd_ptr [1] & ( !\A_SPW_TOP|tx_data|rd_ptr [2] & ( \A_SPW_TOP|tx_data|mem[10][3]~q  ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [1] & ( !\A_SPW_TOP|tx_data|rd_ptr [2] & ( \A_SPW_TOP|tx_data|mem[8][3]~q  ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[14][3]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[8][3]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[10][3]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[12][3]~q ),
        .datae(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .dataf(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux14~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux14~5 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux14~5 .lut_mask = 64'h33330F0F00FF5555;
defparam \A_SPW_TOP|tx_data|Mux14~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y10_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux14~9 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux14~9_combout  = ( \A_SPW_TOP|tx_data|Mux14~6_combout  & ( \A_SPW_TOP|tx_data|Mux14~5_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4]) # ((!\A_SPW_TOP|tx_data|rd_ptr [0] & ((\A_SPW_TOP|tx_data|Mux14~7_combout ))) # 
// (\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|Mux14~8_combout ))) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux14~6_combout  & ( \A_SPW_TOP|tx_data|Mux14~5_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & (((!\A_SPW_TOP|tx_data|rd_ptr [0])))) # 
// (\A_SPW_TOP|tx_data|rd_ptr [4] & ((!\A_SPW_TOP|tx_data|rd_ptr [0] & ((\A_SPW_TOP|tx_data|Mux14~7_combout ))) # (\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|Mux14~8_combout )))) ) ) ) # ( \A_SPW_TOP|tx_data|Mux14~6_combout  & ( 
// !\A_SPW_TOP|tx_data|Mux14~5_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & (((\A_SPW_TOP|tx_data|rd_ptr [0])))) # (\A_SPW_TOP|tx_data|rd_ptr [4] & ((!\A_SPW_TOP|tx_data|rd_ptr [0] & ((\A_SPW_TOP|tx_data|Mux14~7_combout ))) # (\A_SPW_TOP|tx_data|rd_ptr [0] 
// & (\A_SPW_TOP|tx_data|Mux14~8_combout )))) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux14~6_combout  & ( !\A_SPW_TOP|tx_data|Mux14~5_combout  & ( (\A_SPW_TOP|tx_data|rd_ptr [4] & ((!\A_SPW_TOP|tx_data|rd_ptr [0] & ((\A_SPW_TOP|tx_data|Mux14~7_combout ))) # 
// (\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|Mux14~8_combout )))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .datab(!\A_SPW_TOP|tx_data|Mux14~8_combout ),
        .datac(!\A_SPW_TOP|tx_data|Mux14~7_combout ),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .datae(!\A_SPW_TOP|tx_data|Mux14~6_combout ),
        .dataf(!\A_SPW_TOP|tx_data|Mux14~5_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux14~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux14~9 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux14~9 .lut_mask = 64'h051105BBAF11AFBB;
defparam \A_SPW_TOP|tx_data|Mux14~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y10_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux14~15 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux14~15_combout  = ( \A_SPW_TOP|tx_data|mem[45][3]~q  & ( \A_SPW_TOP|tx_data|mem[40][3]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & (((!\A_SPW_TOP|tx_data|rd_ptr [0])) # (\A_SPW_TOP|tx_data|mem[41][3]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr 
// [2] & (((\A_SPW_TOP|tx_data|rd_ptr [0]) # (\A_SPW_TOP|tx_data|mem[44][3]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[45][3]~q  & ( \A_SPW_TOP|tx_data|mem[40][3]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & (((!\A_SPW_TOP|tx_data|rd_ptr [0])) # 
// (\A_SPW_TOP|tx_data|mem[41][3]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [2] & (((\A_SPW_TOP|tx_data|mem[44][3]~q  & !\A_SPW_TOP|tx_data|rd_ptr [0])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[45][3]~q  & ( !\A_SPW_TOP|tx_data|mem[40][3]~q  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[41][3]~q  & ((\A_SPW_TOP|tx_data|rd_ptr [0])))) # (\A_SPW_TOP|tx_data|rd_ptr [2] & (((\A_SPW_TOP|tx_data|rd_ptr [0]) # (\A_SPW_TOP|tx_data|mem[44][3]~q )))) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|mem[45][3]~q  & ( !\A_SPW_TOP|tx_data|mem[40][3]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[41][3]~q  & ((\A_SPW_TOP|tx_data|rd_ptr [0])))) # (\A_SPW_TOP|tx_data|rd_ptr [2] & (((\A_SPW_TOP|tx_data|mem[44][3]~q  & 
// !\A_SPW_TOP|tx_data|rd_ptr [0])))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[41][3]~q ),
        .datab(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .datac(!\A_SPW_TOP|tx_data|mem[44][3]~q ),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .datae(!\A_SPW_TOP|tx_data|mem[45][3]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[40][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux14~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux14~15 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux14~15 .lut_mask = 64'h03440377CF44CF77;
defparam \A_SPW_TOP|tx_data|Mux14~15 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y10_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux14~16 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux14~16_combout  = ( \A_SPW_TOP|tx_data|rd_ptr [2] & ( \A_SPW_TOP|tx_data|mem[56][3]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|mem[60][3]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [0] & ((\A_SPW_TOP|tx_data|mem[61][3]~q ))) 
// ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [2] & ( \A_SPW_TOP|tx_data|mem[56][3]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [0]) # (\A_SPW_TOP|tx_data|mem[57][3]~q ) ) ) ) # ( \A_SPW_TOP|tx_data|rd_ptr [2] & ( !\A_SPW_TOP|tx_data|mem[56][3]~q  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|mem[60][3]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [0] & ((\A_SPW_TOP|tx_data|mem[61][3]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [2] & ( !\A_SPW_TOP|tx_data|mem[56][3]~q  & ( 
// (\A_SPW_TOP|tx_data|mem[57][3]~q  & \A_SPW_TOP|tx_data|rd_ptr [0]) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[57][3]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[60][3]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[61][3]~q ),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .datae(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .dataf(!\A_SPW_TOP|tx_data|mem[56][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux14~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux14~16 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux14~16 .lut_mask = 64'h0055330FFF55330F;
defparam \A_SPW_TOP|tx_data|Mux14~16 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y10_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux14~17 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux14~17_combout  = ( \A_SPW_TOP|tx_data|mem[47][3]~q  & ( \A_SPW_TOP|tx_data|mem[46][3]~q  & ( ((!\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|mem[42][3]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [0] & ((\A_SPW_TOP|tx_data|mem[43][3]~q 
// )))) # (\A_SPW_TOP|tx_data|rd_ptr [2]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[47][3]~q  & ( \A_SPW_TOP|tx_data|mem[46][3]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & ((!\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|mem[42][3]~q )) # 
// (\A_SPW_TOP|tx_data|rd_ptr [0] & ((\A_SPW_TOP|tx_data|mem[43][3]~q ))))) # (\A_SPW_TOP|tx_data|rd_ptr [2] & (((!\A_SPW_TOP|tx_data|rd_ptr [0])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[47][3]~q  & ( !\A_SPW_TOP|tx_data|mem[46][3]~q  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [2] & ((!\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|mem[42][3]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [0] & ((\A_SPW_TOP|tx_data|mem[43][3]~q ))))) # (\A_SPW_TOP|tx_data|rd_ptr [2] & (((\A_SPW_TOP|tx_data|rd_ptr [0])))) ) ) 
// ) # ( !\A_SPW_TOP|tx_data|mem[47][3]~q  & ( !\A_SPW_TOP|tx_data|mem[46][3]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & ((!\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|mem[42][3]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [0] & ((\A_SPW_TOP|tx_data|mem[43][3]~q 
// ))))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[42][3]~q ),
        .datab(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .datad(!\A_SPW_TOP|tx_data|mem[43][3]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[47][3]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[46][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux14~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux14~17 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux14~17 .lut_mask = 64'h404C434F707C737F;
defparam \A_SPW_TOP|tx_data|Mux14~17 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y10_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux14~18 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux14~18_combout  = ( \A_SPW_TOP|tx_data|rd_ptr [2] & ( \A_SPW_TOP|tx_data|mem[63][3]~q  & ( (\A_SPW_TOP|tx_data|rd_ptr [0]) # (\A_SPW_TOP|tx_data|mem[62][3]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [2] & ( 
// \A_SPW_TOP|tx_data|mem[63][3]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|mem[58][3]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [0] & ((\A_SPW_TOP|tx_data|mem[59][3]~q ))) ) ) ) # ( \A_SPW_TOP|tx_data|rd_ptr [2] & ( 
// !\A_SPW_TOP|tx_data|mem[63][3]~q  & ( (\A_SPW_TOP|tx_data|mem[62][3]~q  & !\A_SPW_TOP|tx_data|rd_ptr [0]) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [2] & ( !\A_SPW_TOP|tx_data|mem[63][3]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|mem[58][3]~q 
// )) # (\A_SPW_TOP|tx_data|rd_ptr [0] & ((\A_SPW_TOP|tx_data|mem[59][3]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[58][3]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[62][3]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[59][3]~q ),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .datae(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .dataf(!\A_SPW_TOP|tx_data|mem[63][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux14~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux14~18 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux14~18 .lut_mask = 64'h550F3300550F33FF;
defparam \A_SPW_TOP|tx_data|Mux14~18 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y10_N57
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux14~19 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux14~19_combout  = ( \A_SPW_TOP|tx_data|Mux14~17_combout  & ( \A_SPW_TOP|tx_data|Mux14~18_combout  & ( ((!\A_SPW_TOP|tx_data|rd_ptr [4] & (\A_SPW_TOP|tx_data|Mux14~15_combout )) # (\A_SPW_TOP|tx_data|rd_ptr [4] & 
// ((\A_SPW_TOP|tx_data|Mux14~16_combout )))) # (\A_SPW_TOP|tx_data|rd_ptr [1]) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux14~17_combout  & ( \A_SPW_TOP|tx_data|Mux14~18_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [1] & ((!\A_SPW_TOP|tx_data|rd_ptr [4] & 
// (\A_SPW_TOP|tx_data|Mux14~15_combout )) # (\A_SPW_TOP|tx_data|rd_ptr [4] & ((\A_SPW_TOP|tx_data|Mux14~16_combout ))))) # (\A_SPW_TOP|tx_data|rd_ptr [1] & (((\A_SPW_TOP|tx_data|rd_ptr [4])))) ) ) ) # ( \A_SPW_TOP|tx_data|Mux14~17_combout  & ( 
// !\A_SPW_TOP|tx_data|Mux14~18_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [1] & ((!\A_SPW_TOP|tx_data|rd_ptr [4] & (\A_SPW_TOP|tx_data|Mux14~15_combout )) # (\A_SPW_TOP|tx_data|rd_ptr [4] & ((\A_SPW_TOP|tx_data|Mux14~16_combout ))))) # 
// (\A_SPW_TOP|tx_data|rd_ptr [1] & (((!\A_SPW_TOP|tx_data|rd_ptr [4])))) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux14~17_combout  & ( !\A_SPW_TOP|tx_data|Mux14~18_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [1] & ((!\A_SPW_TOP|tx_data|rd_ptr [4] & 
// (\A_SPW_TOP|tx_data|Mux14~15_combout )) # (\A_SPW_TOP|tx_data|rd_ptr [4] & ((\A_SPW_TOP|tx_data|Mux14~16_combout ))))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux14~15_combout ),
        .datab(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .datac(!\A_SPW_TOP|tx_data|Mux14~16_combout ),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .datae(!\A_SPW_TOP|tx_data|Mux14~17_combout ),
        .dataf(!\A_SPW_TOP|tx_data|Mux14~18_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux14~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux14~19 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux14~19 .lut_mask = 64'h440C770C443F773F;
defparam \A_SPW_TOP|tx_data|Mux14~19 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y11_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux14~2 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux14~2_combout  = ( \A_SPW_TOP|tx_data|mem[20][3]~q  & ( \A_SPW_TOP|tx_data|rd_ptr [1] & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[18][3]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [2] & ((\A_SPW_TOP|tx_data|mem[22][3]~q ))) ) 
// ) ) # ( !\A_SPW_TOP|tx_data|mem[20][3]~q  & ( \A_SPW_TOP|tx_data|rd_ptr [1] & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[18][3]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [2] & ((\A_SPW_TOP|tx_data|mem[22][3]~q ))) ) ) ) # ( 
// \A_SPW_TOP|tx_data|mem[20][3]~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [1] & ( (\A_SPW_TOP|tx_data|mem[16][3]~q ) # (\A_SPW_TOP|tx_data|rd_ptr [2]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[20][3]~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [1] & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] 
// & \A_SPW_TOP|tx_data|mem[16][3]~q ) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .datab(!\A_SPW_TOP|tx_data|mem[18][3]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[16][3]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[22][3]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[20][3]~q ),
        .dataf(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux14~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux14~2 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux14~2 .lut_mask = 64'h0A0A5F5F22772277;
defparam \A_SPW_TOP|tx_data|Mux14~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y11_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux14~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux14~1_combout  = ( \A_SPW_TOP|tx_data|mem[7][3]~q  & ( \A_SPW_TOP|tx_data|rd_ptr [1] & ( (\A_SPW_TOP|tx_data|rd_ptr [2]) # (\A_SPW_TOP|tx_data|mem[3][3]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[7][3]~q  & ( \A_SPW_TOP|tx_data|rd_ptr [1] 
// & ( (\A_SPW_TOP|tx_data|mem[3][3]~q  & !\A_SPW_TOP|tx_data|rd_ptr [2]) ) ) ) # ( \A_SPW_TOP|tx_data|mem[7][3]~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [1] & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[1][3]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [2] & 
// ((\A_SPW_TOP|tx_data|mem[5][3]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[7][3]~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [1] & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[1][3]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [2] & ((\A_SPW_TOP|tx_data|mem[5][3]~q 
// ))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[1][3]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[3][3]~q ),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .datad(!\A_SPW_TOP|tx_data|mem[5][3]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[7][3]~q ),
        .dataf(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux14~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux14~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux14~1 .lut_mask = 64'h505F505F30303F3F;
defparam \A_SPW_TOP|tx_data|Mux14~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y11_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux14~3 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux14~3_combout  = ( \A_SPW_TOP|tx_data|mem[19][3]~q  & ( \A_SPW_TOP|tx_data|rd_ptr [1] & ( (!\A_SPW_TOP|tx_data|rd_ptr [2]) # (\A_SPW_TOP|tx_data|mem[23][3]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[19][3]~q  & ( \A_SPW_TOP|tx_data|rd_ptr 
// [1] & ( (\A_SPW_TOP|tx_data|rd_ptr [2] & \A_SPW_TOP|tx_data|mem[23][3]~q ) ) ) ) # ( \A_SPW_TOP|tx_data|mem[19][3]~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [1] & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[17][3]~q )) # (\A_SPW_TOP|tx_data|rd_ptr 
// [2] & ((\A_SPW_TOP|tx_data|mem[21][3]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[19][3]~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [1] & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[17][3]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [2] & 
// ((\A_SPW_TOP|tx_data|mem[21][3]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .datab(!\A_SPW_TOP|tx_data|mem[17][3]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[23][3]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[21][3]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[19][3]~q ),
        .dataf(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux14~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux14~3 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux14~3 .lut_mask = 64'h227722770505AFAF;
defparam \A_SPW_TOP|tx_data|Mux14~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y11_N9
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux14~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux14~0_combout  = ( \A_SPW_TOP|tx_data|rd_ptr [2] & ( \A_SPW_TOP|tx_data|mem[6][3]~q  & ( (\A_SPW_TOP|tx_data|rd_ptr [1]) # (\A_SPW_TOP|tx_data|mem[4][3]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [2] & ( \A_SPW_TOP|tx_data|mem[6][3]~q  
// & ( (!\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|mem[0][3]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [1] & ((\A_SPW_TOP|tx_data|mem[2][3]~q ))) ) ) ) # ( \A_SPW_TOP|tx_data|rd_ptr [2] & ( !\A_SPW_TOP|tx_data|mem[6][3]~q  & ( 
// (\A_SPW_TOP|tx_data|mem[4][3]~q  & !\A_SPW_TOP|tx_data|rd_ptr [1]) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [2] & ( !\A_SPW_TOP|tx_data|mem[6][3]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|mem[0][3]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [1] & 
// ((\A_SPW_TOP|tx_data|mem[2][3]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[0][3]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[4][3]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[2][3]~q ),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .datae(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .dataf(!\A_SPW_TOP|tx_data|mem[6][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux14~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux14~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux14~0 .lut_mask = 64'h550F3300550F33FF;
defparam \A_SPW_TOP|tx_data|Mux14~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y11_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux14~4 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux14~4_combout  = ( \A_SPW_TOP|tx_data|rd_ptr [0] & ( \A_SPW_TOP|tx_data|rd_ptr [4] & ( \A_SPW_TOP|tx_data|Mux14~3_combout  ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [0] & ( \A_SPW_TOP|tx_data|rd_ptr [4] & ( 
// \A_SPW_TOP|tx_data|Mux14~2_combout  ) ) ) # ( \A_SPW_TOP|tx_data|rd_ptr [0] & ( !\A_SPW_TOP|tx_data|rd_ptr [4] & ( \A_SPW_TOP|tx_data|Mux14~1_combout  ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [0] & ( !\A_SPW_TOP|tx_data|rd_ptr [4] & ( 
// \A_SPW_TOP|tx_data|Mux14~0_combout  ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux14~2_combout ),
        .datab(!\A_SPW_TOP|tx_data|Mux14~1_combout ),
        .datac(!\A_SPW_TOP|tx_data|Mux14~3_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux14~0_combout ),
        .datae(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .dataf(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux14~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux14~4 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux14~4 .lut_mask = 64'h00FF333355550F0F;
defparam \A_SPW_TOP|tx_data|Mux14~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y10_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux14~12 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux14~12_combout  = ( \A_SPW_TOP|tx_data|mem[50][3]~q  & ( \A_SPW_TOP|tx_data|mem[54][3]~q  & ( ((!\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[48][3]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [2] & ((\A_SPW_TOP|tx_data|mem[52][3]~q 
// )))) # (\A_SPW_TOP|tx_data|rd_ptr [1]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[50][3]~q  & ( \A_SPW_TOP|tx_data|mem[54][3]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[48][3]~q  & ((!\A_SPW_TOP|tx_data|rd_ptr [1])))) # 
// (\A_SPW_TOP|tx_data|rd_ptr [2] & (((\A_SPW_TOP|tx_data|rd_ptr [1]) # (\A_SPW_TOP|tx_data|mem[52][3]~q )))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[50][3]~q  & ( !\A_SPW_TOP|tx_data|mem[54][3]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & (((\A_SPW_TOP|tx_data|rd_ptr 
// [1])) # (\A_SPW_TOP|tx_data|mem[48][3]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [2] & (((\A_SPW_TOP|tx_data|mem[52][3]~q  & !\A_SPW_TOP|tx_data|rd_ptr [1])))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[50][3]~q  & ( !\A_SPW_TOP|tx_data|mem[54][3]~q  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [1] & ((!\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[48][3]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [2] & ((\A_SPW_TOP|tx_data|mem[52][3]~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .datab(!\A_SPW_TOP|tx_data|mem[48][3]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[52][3]~q ),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .datae(!\A_SPW_TOP|tx_data|mem[50][3]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[54][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux14~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux14~12 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux14~12 .lut_mask = 64'h270027AA275527FF;
defparam \A_SPW_TOP|tx_data|Mux14~12 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y10_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux14~13 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux14~13_combout  = ( \A_SPW_TOP|tx_data|mem[51][3]~q  & ( \A_SPW_TOP|tx_data|mem[53][3]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [1] & (((\A_SPW_TOP|tx_data|rd_ptr [2]) # (\A_SPW_TOP|tx_data|mem[49][3]~q )))) # (\A_SPW_TOP|tx_data|rd_ptr [1] 
// & (((!\A_SPW_TOP|tx_data|rd_ptr [2])) # (\A_SPW_TOP|tx_data|mem[55][3]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[51][3]~q  & ( \A_SPW_TOP|tx_data|mem[53][3]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [1] & (((\A_SPW_TOP|tx_data|rd_ptr [2]) # 
// (\A_SPW_TOP|tx_data|mem[49][3]~q )))) # (\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|mem[55][3]~q  & ((\A_SPW_TOP|tx_data|rd_ptr [2])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[51][3]~q  & ( !\A_SPW_TOP|tx_data|mem[53][3]~q  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [1] & (((\A_SPW_TOP|tx_data|mem[49][3]~q  & !\A_SPW_TOP|tx_data|rd_ptr [2])))) # (\A_SPW_TOP|tx_data|rd_ptr [1] & (((!\A_SPW_TOP|tx_data|rd_ptr [2])) # (\A_SPW_TOP|tx_data|mem[55][3]~q ))) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|mem[51][3]~q  & ( !\A_SPW_TOP|tx_data|mem[53][3]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [1] & (((\A_SPW_TOP|tx_data|mem[49][3]~q  & !\A_SPW_TOP|tx_data|rd_ptr [2])))) # (\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|mem[55][3]~q  & 
// ((\A_SPW_TOP|tx_data|rd_ptr [2])))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .datab(!\A_SPW_TOP|tx_data|mem[55][3]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[49][3]~q ),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .datae(!\A_SPW_TOP|tx_data|mem[51][3]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[53][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux14~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux14~13 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux14~13 .lut_mask = 64'h0A115F110ABB5FBB;
defparam \A_SPW_TOP|tx_data|Mux14~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y10_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux14~10 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux14~10_combout  = ( \A_SPW_TOP|tx_data|mem[32][3]~q  & ( \A_SPW_TOP|tx_data|rd_ptr [2] & ( (!\A_SPW_TOP|tx_data|rd_ptr [1] & ((\A_SPW_TOP|tx_data|mem[36][3]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|mem[38][3]~q )) 
// ) ) ) # ( !\A_SPW_TOP|tx_data|mem[32][3]~q  & ( \A_SPW_TOP|tx_data|rd_ptr [2] & ( (!\A_SPW_TOP|tx_data|rd_ptr [1] & ((\A_SPW_TOP|tx_data|mem[36][3]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|mem[38][3]~q )) ) ) ) # ( 
// \A_SPW_TOP|tx_data|mem[32][3]~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [2] & ( (!\A_SPW_TOP|tx_data|rd_ptr [1]) # (\A_SPW_TOP|tx_data|mem[34][3]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[32][3]~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [2] & ( (\A_SPW_TOP|tx_data|rd_ptr [1] 
// & \A_SPW_TOP|tx_data|mem[34][3]~q ) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .datab(!\A_SPW_TOP|tx_data|mem[38][3]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[34][3]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[36][3]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[32][3]~q ),
        .dataf(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux14~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux14~10 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux14~10 .lut_mask = 64'h0505AFAF11BB11BB;
defparam \A_SPW_TOP|tx_data|Mux14~10 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y10_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux14~11 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux14~11_combout  = ( \A_SPW_TOP|tx_data|mem[37][3]~q  & ( \A_SPW_TOP|tx_data|mem[35][3]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & (((\A_SPW_TOP|tx_data|rd_ptr [1])) # (\A_SPW_TOP|tx_data|mem[33][3]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [2] 
// & (((!\A_SPW_TOP|tx_data|rd_ptr [1]) # (\A_SPW_TOP|tx_data|mem[39][3]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[37][3]~q  & ( \A_SPW_TOP|tx_data|mem[35][3]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & (((\A_SPW_TOP|tx_data|rd_ptr [1])) # 
// (\A_SPW_TOP|tx_data|mem[33][3]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [2] & (((\A_SPW_TOP|tx_data|mem[39][3]~q  & \A_SPW_TOP|tx_data|rd_ptr [1])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[37][3]~q  & ( !\A_SPW_TOP|tx_data|mem[35][3]~q  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[33][3]~q  & ((!\A_SPW_TOP|tx_data|rd_ptr [1])))) # (\A_SPW_TOP|tx_data|rd_ptr [2] & (((!\A_SPW_TOP|tx_data|rd_ptr [1]) # (\A_SPW_TOP|tx_data|mem[39][3]~q )))) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|mem[37][3]~q  & ( !\A_SPW_TOP|tx_data|mem[35][3]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[33][3]~q  & ((!\A_SPW_TOP|tx_data|rd_ptr [1])))) # (\A_SPW_TOP|tx_data|rd_ptr [2] & (((\A_SPW_TOP|tx_data|mem[39][3]~q  & 
// \A_SPW_TOP|tx_data|rd_ptr [1])))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[33][3]~q ),
        .datab(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .datac(!\A_SPW_TOP|tx_data|mem[39][3]~q ),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .datae(!\A_SPW_TOP|tx_data|mem[37][3]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[35][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux14~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux14~11 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux14~11 .lut_mask = 64'h4403770344CF77CF;
defparam \A_SPW_TOP|tx_data|Mux14~11 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y10_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux14~14 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux14~14_combout  = ( \A_SPW_TOP|tx_data|rd_ptr [4] & ( \A_SPW_TOP|tx_data|Mux14~11_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|Mux14~12_combout )) # (\A_SPW_TOP|tx_data|rd_ptr [0] & 
// ((\A_SPW_TOP|tx_data|Mux14~13_combout ))) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [4] & ( \A_SPW_TOP|tx_data|Mux14~11_combout  & ( (\A_SPW_TOP|tx_data|rd_ptr [0]) # (\A_SPW_TOP|tx_data|Mux14~10_combout ) ) ) ) # ( \A_SPW_TOP|tx_data|rd_ptr [4] & ( 
// !\A_SPW_TOP|tx_data|Mux14~11_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|Mux14~12_combout )) # (\A_SPW_TOP|tx_data|rd_ptr [0] & ((\A_SPW_TOP|tx_data|Mux14~13_combout ))) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [4] & ( 
// !\A_SPW_TOP|tx_data|Mux14~11_combout  & ( (\A_SPW_TOP|tx_data|Mux14~10_combout  & !\A_SPW_TOP|tx_data|rd_ptr [0]) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux14~12_combout ),
        .datab(!\A_SPW_TOP|tx_data|Mux14~13_combout ),
        .datac(!\A_SPW_TOP|tx_data|Mux14~10_combout ),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .datae(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .dataf(!\A_SPW_TOP|tx_data|Mux14~11_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux14~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux14~14 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux14~14 .lut_mask = 64'h0F0055330FFF5533;
defparam \A_SPW_TOP|tx_data|Mux14~14 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y10_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux14~20 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux14~20_combout  = ( \A_SPW_TOP|tx_data|rd_ptr [5] & ( \A_SPW_TOP|tx_data|rd_ptr [3] & ( \A_SPW_TOP|tx_data|Mux14~19_combout  ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [5] & ( \A_SPW_TOP|tx_data|rd_ptr [3] & ( 
// \A_SPW_TOP|tx_data|Mux14~9_combout  ) ) ) # ( \A_SPW_TOP|tx_data|rd_ptr [5] & ( !\A_SPW_TOP|tx_data|rd_ptr [3] & ( \A_SPW_TOP|tx_data|Mux14~14_combout  ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [5] & ( !\A_SPW_TOP|tx_data|rd_ptr [3] & ( 
// \A_SPW_TOP|tx_data|Mux14~4_combout  ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux14~9_combout ),
        .datab(!\A_SPW_TOP|tx_data|Mux14~19_combout ),
        .datac(!\A_SPW_TOP|tx_data|Mux14~4_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux14~14_combout ),
        .datae(!\A_SPW_TOP|tx_data|rd_ptr [5]),
        .dataf(!\A_SPW_TOP|tx_data|rd_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux14~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux14~20 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux14~20 .lut_mask = 64'h0F0F00FF55553333;
defparam \A_SPW_TOP|tx_data|Mux14~20 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X45_Y10_N20
dffeas \A_SPW_TOP|tx_data|data_out[3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|tx_data|Mux14~20_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|data_out [3]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|data_out[3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|data_out[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X51_Y7_N24
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector37~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector37~0_combout  = ( \A_SPW_TOP|SPW|TX|Selector40~0_combout  & ( (\A_SPW_TOP|tx_data|data_out [3] & \A_SPW_TOP|SPW|TX|Selector32~0_combout ) ) ) # ( !\A_SPW_TOP|SPW|TX|Selector40~0_combout  & ( ((\A_SPW_TOP|tx_data|data_out [3] & 
// \A_SPW_TOP|SPW|TX|Selector32~0_combout )) # (\A_SPW_TOP|SPW|TX|tx_data_in_0 [3]) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|tx_data|data_out [3]),
        .datac(!\A_SPW_TOP|SPW|TX|tx_data_in_0 [3]),
        .datad(!\A_SPW_TOP|SPW|TX|Selector32~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|Selector40~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector37~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector37~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector37~0 .lut_mask = 64'h0F3F0F3F00330033;
defparam \A_SPW_TOP|SPW|TX|Selector37~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X54_Y7_N8
dffeas \A_SPW_TOP|SPW|TX|tx_data_in_0[3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|Selector37~0_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|tx_data_in_0 [3]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_data_in_0[3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|tx_data_in_0[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X51_Y7_N21
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout~39 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout~39_combout  = ( \A_SPW_TOP|SPW|TX|tx_data_in_0 [3] & ( \A_SPW_TOP|SPW|TX|global_counter_transfer [1] & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & ((\A_SPW_TOP|SPW|TX|tx_data_in_0 [0]))) # 
// (\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & (\A_SPW_TOP|SPW|TX|tx_data_in_0 [1])) ) ) ) # ( !\A_SPW_TOP|SPW|TX|tx_data_in_0 [3] & ( \A_SPW_TOP|SPW|TX|global_counter_transfer [1] & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & 
// ((\A_SPW_TOP|SPW|TX|tx_data_in_0 [0]))) # (\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & (\A_SPW_TOP|SPW|TX|tx_data_in_0 [1])) ) ) ) # ( \A_SPW_TOP|SPW|TX|tx_data_in_0 [3] & ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & ( 
// (\A_SPW_TOP|SPW|TX|tx_data_in_0 [2]) # (\A_SPW_TOP|SPW|TX|global_counter_transfer [0]) ) ) ) # ( !\A_SPW_TOP|SPW|TX|tx_data_in_0 [3] & ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & 
// \A_SPW_TOP|SPW|TX|tx_data_in_0 [2]) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
        .datab(!\A_SPW_TOP|SPW|TX|tx_data_in_0 [2]),
        .datac(!\A_SPW_TOP|SPW|TX|tx_data_in_0 [1]),
        .datad(!\A_SPW_TOP|SPW|TX|tx_data_in_0 [0]),
        .datae(!\A_SPW_TOP|SPW|TX|tx_data_in_0 [3]),
        .dataf(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|tx_dout~39_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout~39 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout~39 .lut_mask = 64'h2222777705AF05AF;
defparam \A_SPW_TOP|SPW|TX|tx_dout~39 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X51_Y7_N30
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout~19 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout~19_combout  = ( \A_SPW_TOP|SPW|TX|global_counter_transfer [2] & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & (!\A_SPW_TOP|SPW|TX|tx_data_in_0 [8] & (!\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & 
// \A_SPW_TOP|SPW|TX|tx_dout~39_combout ))) ) ) # ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & ( (\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & (!\A_SPW_TOP|SPW|TX|tx_data_in_0 [8] & (!\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & 
// \A_SPW_TOP|SPW|TX|tx_dout~39_combout ))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
        .datab(!\A_SPW_TOP|SPW|TX|tx_data_in_0 [8]),
        .datac(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
        .datad(!\A_SPW_TOP|SPW|TX|tx_dout~39_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|tx_dout~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout~19 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout~19 .lut_mask = 64'h0040004000800080;
defparam \A_SPW_TOP|SPW|TX|tx_dout~19 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y7_N3
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|LessThan6~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|LessThan6~0_combout  = ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [3] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
        .dataf(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|LessThan6~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|LessThan6~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|LessThan6~0 .lut_mask = 64'hFFFF000000000000;
defparam \A_SPW_TOP|SPW|TX|LessThan6~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X51_Y7_N0
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout~15 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout~15_combout  = ( \A_SPW_TOP|SPW|TX|always0~8_combout  & ( \A_SPW_TOP|SPW|TX|always0~9_combout  & ( (!\A_SPW_TOP|SPW|TX|LessThan6~0_combout  & (((!\A_SPW_TOP|SPW|TX|tx_dout~q )))) # (\A_SPW_TOP|SPW|TX|LessThan6~0_combout  & 
// ((!\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & (!\A_SPW_TOP|SPW|TX|tx_dout~q  & !\A_SPW_TOP|SPW|TX|global_counter_transfer [1])) # (\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & ((\A_SPW_TOP|SPW|TX|global_counter_transfer [1]))))) ) ) ) # ( 
// !\A_SPW_TOP|SPW|TX|always0~8_combout  & ( \A_SPW_TOP|SPW|TX|always0~9_combout  & ( (!\A_SPW_TOP|SPW|TX|LessThan6~0_combout  & (((!\A_SPW_TOP|SPW|TX|tx_dout~q )))) # (\A_SPW_TOP|SPW|TX|LessThan6~0_combout  & ((!\A_SPW_TOP|SPW|TX|global_counter_transfer [0] 
// & (!\A_SPW_TOP|SPW|TX|tx_dout~q  & !\A_SPW_TOP|SPW|TX|global_counter_transfer [1])) # (\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & ((\A_SPW_TOP|SPW|TX|global_counter_transfer [1]))))) ) ) ) # ( \A_SPW_TOP|SPW|TX|always0~8_combout  & ( 
// !\A_SPW_TOP|SPW|TX|always0~9_combout  & ( (!\A_SPW_TOP|SPW|TX|LessThan6~0_combout  & (((!\A_SPW_TOP|SPW|TX|tx_dout~q )))) # (\A_SPW_TOP|SPW|TX|LessThan6~0_combout  & (!\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & ((!\A_SPW_TOP|SPW|TX|tx_dout~q ) # 
// (\A_SPW_TOP|SPW|TX|global_counter_transfer [1])))) ) ) ) # ( !\A_SPW_TOP|SPW|TX|always0~8_combout  & ( !\A_SPW_TOP|SPW|TX|always0~9_combout  & ( !\A_SPW_TOP|SPW|TX|tx_dout~q  ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
        .datab(!\A_SPW_TOP|SPW|TX|LessThan6~0_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|tx_dout~q ),
        .datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
        .datae(!\A_SPW_TOP|SPW|TX|always0~8_combout ),
        .dataf(!\A_SPW_TOP|SPW|TX|always0~9_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|tx_dout~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout~15 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout~15 .lut_mask = 64'hF0F0E0E2E0D1E0D1;
defparam \A_SPW_TOP|SPW|TX|tx_dout~15 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X51_Y7_N9
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout~18 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout~18_combout  = ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & ( (!\A_SPW_TOP|SPW|TX|tx_data_in_0 [8] & ((!\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & (\A_SPW_TOP|SPW|TX|global_counter_transfer [2])) # 
// (\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & ((!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]) # (!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]))))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
        .datab(!\A_SPW_TOP|SPW|TX|tx_data_in_0 [8]),
        .datac(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
        .datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|tx_dout~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout~18 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout~18 .lut_mask = 64'h4C484C4800000000;
defparam \A_SPW_TOP|SPW|TX|tx_dout~18 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y14_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_payload~7 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_payload~7_combout  = ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_WDATA [7] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_WDATA [7]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_010|src_payload~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_payload~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_payload~7 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_payload~7 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y14_N8
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[7] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_010|src_payload~7_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [7]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[7] .power_up = "low";
// synopsys translate_on

// Location: FF_X30_Y14_N17
dffeas \u0|write_data_fifo_tx|data_out[7] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [7]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|write_data_fifo_tx|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|write_data_fifo_tx|data_out [7]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|write_data_fifo_tx|data_out[7] .is_wysiwyg = "true";
defparam \u0|write_data_fifo_tx|data_out[7] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y11_N27
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector231~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector231~0_combout  = ( \A_SPW_TOP|tx_data|Selector230~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux1~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [7]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector230~0_combout  & ( \A_SPW_TOP|tx_data|mem[25][7]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [7]),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[25][7]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector230~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector231~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector231~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector231~0 .lut_mask = 64'h00FF00FF53535353;
defparam \A_SPW_TOP|tx_data|Selector231~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y11_N35
dffeas \A_SPW_TOP|tx_data|mem[25][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector231~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[25][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[25][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[25][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X51_Y11_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector240~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector240~0_combout  = ( \A_SPW_TOP|tx_data|Selector239~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux1~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [7]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector239~0_combout  & ( \A_SPW_TOP|tx_data|mem[26][7]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[26][7]~q ),
        .datad(!\u0|write_data_fifo_tx|data_out [7]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector239~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector240~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector240~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector240~0 .lut_mask = 64'h0F0F0F0F44774477;
defparam \A_SPW_TOP|tx_data|Selector240~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X51_Y11_N47
dffeas \A_SPW_TOP|tx_data|mem[26][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector240~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[26][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[26][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[26][7] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y11_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector222~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector222~0_combout  = ( \A_SPW_TOP|tx_data|mem[24][7]~q  & ( (!\A_SPW_TOP|tx_data|Selector221~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux1~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [7]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[24][7]~q  & ( (\A_SPW_TOP|tx_data|Selector221~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux1~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [7])))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\u0|write_data_fifo_tx|data_out [7]),
        .datac(!\A_SPW_TOP|tx_data|Selector221~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[24][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector222~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector222~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector222~0 .lut_mask = 64'h010B010BF1FBF1FB;
defparam \A_SPW_TOP|tx_data|Selector222~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y11_N35
dffeas \A_SPW_TOP|tx_data|mem[24][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector222~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[24][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[24][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[24][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X51_Y11_N57
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector249~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector249~0_combout  = ( \u0|write_data_fifo_tx|data_out [7] & ( (!\A_SPW_TOP|tx_data|Selector248~0_combout  & (((\A_SPW_TOP|tx_data|mem[27][7]~q )))) # (\A_SPW_TOP|tx_data|Selector248~0_combout  & 
// (((\A_SPW_TOP|tx_data|state_data_write.00~q )) # (\A_SPW_TOP|tx_data|Mux1~20_combout ))) ) ) # ( !\u0|write_data_fifo_tx|data_out [7] & ( (!\A_SPW_TOP|tx_data|Selector248~0_combout  & (((\A_SPW_TOP|tx_data|mem[27][7]~q )))) # 
// (\A_SPW_TOP|tx_data|Selector248~0_combout  & (\A_SPW_TOP|tx_data|Mux1~20_combout  & (!\A_SPW_TOP|tx_data|state_data_write.00~q ))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector248~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|mem[27][7]~q ),
        .datae(gnd),
        .dataf(!\u0|write_data_fifo_tx|data_out [7]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector249~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector249~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector249~0 .lut_mask = 64'h04F404F407F707F7;
defparam \A_SPW_TOP|tx_data|Selector249~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X51_Y11_N29
dffeas \A_SPW_TOP|tx_data|mem[27][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector249~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[27][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[27][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[27][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X51_Y11_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux1~6 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux1~6_combout  = ( \A_SPW_TOP|tx_data|mem[27][7]~q  & ( \A_SPW_TOP|tx_data|wr_ptr [1] & ( (\A_SPW_TOP|tx_data|wr_ptr [0]) # (\A_SPW_TOP|tx_data|mem[26][7]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[27][7]~q  & ( \A_SPW_TOP|tx_data|wr_ptr 
// [1] & ( (\A_SPW_TOP|tx_data|mem[26][7]~q  & !\A_SPW_TOP|tx_data|wr_ptr [0]) ) ) ) # ( \A_SPW_TOP|tx_data|mem[27][7]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|mem[24][7]~q ))) # 
// (\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|mem[25][7]~q )) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[27][7]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|mem[24][7]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr 
// [0] & (\A_SPW_TOP|tx_data|mem[25][7]~q )) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[25][7]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[26][7]~q ),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datad(!\A_SPW_TOP|tx_data|mem[24][7]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[27][7]~q ),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux1~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux1~6 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux1~6 .lut_mask = 64'h05F505F530303F3F;
defparam \A_SPW_TOP|tx_data|Mux1~6 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y11_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector456~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector456~0_combout  = ( \A_SPW_TOP|tx_data|mem[50][7]~q  & ( (!\A_SPW_TOP|tx_data|Selector455~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux1~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [7])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[50][7]~q  & ( (\A_SPW_TOP|tx_data|Selector455~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux1~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [7]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [7]),
        .datac(!\A_SPW_TOP|tx_data|Selector455~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[50][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector456~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector456~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector456~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|tx_data|Selector456~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y11_N20
dffeas \A_SPW_TOP|tx_data|mem[50][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector456~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[50][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[50][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[50][7] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y11_N57
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector438~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector438~0_combout  = ( \A_SPW_TOP|tx_data|Selector437~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux1~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [7]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector437~0_combout  & ( \A_SPW_TOP|tx_data|mem[48][7]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\u0|write_data_fifo_tx|data_out [7]),
        .datad(!\A_SPW_TOP|tx_data|mem[48][7]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector437~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector438~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector438~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector438~0 .lut_mask = 64'h00FF00FF47474747;
defparam \A_SPW_TOP|tx_data|Selector438~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y11_N47
dffeas \A_SPW_TOP|tx_data|mem[48][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector438~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[48][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[48][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[48][7] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y11_N39
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector465~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector465~0_combout  = ( \A_SPW_TOP|tx_data|mem[51][7]~q  & ( (!\A_SPW_TOP|tx_data|Selector464~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux1~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [7])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[51][7]~q  & ( (\A_SPW_TOP|tx_data|Selector464~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux1~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [7]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [7]),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|tx_data|Selector464~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[51][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector465~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector465~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector465~0 .lut_mask = 64'h00530053FF53FF53;
defparam \A_SPW_TOP|tx_data|Selector465~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y11_N14
dffeas \A_SPW_TOP|tx_data|mem[51][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector465~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[51][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[51][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[51][7] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y11_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector447~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector447~0_combout  = ( \A_SPW_TOP|tx_data|mem[49][7]~q  & ( (!\A_SPW_TOP|tx_data|Selector446~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux1~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [7])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[49][7]~q  & ( (\A_SPW_TOP|tx_data|Selector446~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux1~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [7]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [7]),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|tx_data|Selector446~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[49][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector447~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector447~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector447~0 .lut_mask = 64'h00530053FF53FF53;
defparam \A_SPW_TOP|tx_data|Selector447~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y11_N44
dffeas \A_SPW_TOP|tx_data|mem[49][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector447~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[49][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[49][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[49][7] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y11_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux1~7 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux1~7_combout  = ( \A_SPW_TOP|tx_data|mem[51][7]~q  & ( \A_SPW_TOP|tx_data|mem[49][7]~q  & ( ((!\A_SPW_TOP|tx_data|wr_ptr [1] & ((\A_SPW_TOP|tx_data|mem[48][7]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|mem[50][7]~q 
// ))) # (\A_SPW_TOP|tx_data|wr_ptr [0]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[51][7]~q  & ( \A_SPW_TOP|tx_data|mem[49][7]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & ((!\A_SPW_TOP|tx_data|wr_ptr [1] & ((\A_SPW_TOP|tx_data|mem[48][7]~q ))) # 
// (\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|mem[50][7]~q )))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & (((!\A_SPW_TOP|tx_data|wr_ptr [1])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[51][7]~q  & ( !\A_SPW_TOP|tx_data|mem[49][7]~q  & ( 
// (!\A_SPW_TOP|tx_data|wr_ptr [0] & ((!\A_SPW_TOP|tx_data|wr_ptr [1] & ((\A_SPW_TOP|tx_data|mem[48][7]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|mem[50][7]~q )))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & (((\A_SPW_TOP|tx_data|wr_ptr [1])))) ) ) 
// ) # ( !\A_SPW_TOP|tx_data|mem[51][7]~q  & ( !\A_SPW_TOP|tx_data|mem[49][7]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & ((!\A_SPW_TOP|tx_data|wr_ptr [1] & ((\A_SPW_TOP|tx_data|mem[48][7]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [1] & 
// (\A_SPW_TOP|tx_data|mem[50][7]~q )))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[50][7]~q ),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datad(!\A_SPW_TOP|tx_data|mem[48][7]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[51][7]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[49][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux1~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux1~7 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux1~7 .lut_mask = 64'h04C407C734F437F7;
defparam \A_SPW_TOP|tx_data|Mux1~7 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y11_N45
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector168~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector168~0_combout  = ( \A_SPW_TOP|tx_data|Selector167~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux1~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\u0|write_data_fifo_tx|data_out [7])) ) ) # ( !\A_SPW_TOP|tx_data|Selector167~0_combout  & ( \A_SPW_TOP|tx_data|mem[18][7]~q  ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [7]),
        .datab(!\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[18][7]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector167~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector168~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector168~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector168~0 .lut_mask = 64'h00FF00FF35353535;
defparam \A_SPW_TOP|tx_data|Selector168~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y11_N5
dffeas \A_SPW_TOP|tx_data|mem[18][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector168~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[18][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[18][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[18][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y11_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector159~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector159~0_combout  = ( \A_SPW_TOP|tx_data|mem[17][7]~q  & ( (!\A_SPW_TOP|tx_data|Selector158~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux1~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [7])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[17][7]~q  & ( (\A_SPW_TOP|tx_data|Selector158~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux1~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [7]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector158~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [7]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[17][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector159~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector159~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector159~0 .lut_mask = 64'h02070207F2F7F2F7;
defparam \A_SPW_TOP|tx_data|Selector159~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y11_N8
dffeas \A_SPW_TOP|tx_data|mem[17][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector159~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[17][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[17][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[17][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y11_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector177~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector177~0_combout  = ( \A_SPW_TOP|tx_data|mem[19][7]~q  & ( (!\A_SPW_TOP|tx_data|Selector176~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux1~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [7]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[19][7]~q  & ( (\A_SPW_TOP|tx_data|Selector176~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux1~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [7])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [7]),
        .datab(!\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|tx_data|Selector176~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[19][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector177~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector177~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector177~0 .lut_mask = 64'h00350035FF35FF35;
defparam \A_SPW_TOP|tx_data|Selector177~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y11_N26
dffeas \A_SPW_TOP|tx_data|mem[19][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector177~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[19][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[19][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[19][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y11_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector150~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector150~0_combout  = ( \A_SPW_TOP|tx_data|mem[16][7]~q  & ( (!\A_SPW_TOP|tx_data|Selector149~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux1~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [7]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[16][7]~q  & ( (\A_SPW_TOP|tx_data|Selector149~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux1~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [7])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [7]),
        .datab(!\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|tx_data|Selector149~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[16][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector150~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector150~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector150~0 .lut_mask = 64'h00350035FF35FF35;
defparam \A_SPW_TOP|tx_data|Selector150~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y11_N11
dffeas \A_SPW_TOP|tx_data|mem[16][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector150~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[16][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[16][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[16][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y11_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux1~5 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux1~5_combout  = ( \A_SPW_TOP|tx_data|mem[19][7]~q  & ( \A_SPW_TOP|tx_data|mem[16][7]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [1] & ((!\A_SPW_TOP|tx_data|wr_ptr [0]) # ((\A_SPW_TOP|tx_data|mem[17][7]~q )))) # (\A_SPW_TOP|tx_data|wr_ptr [1] 
// & (((\A_SPW_TOP|tx_data|mem[18][7]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [0]))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[19][7]~q  & ( \A_SPW_TOP|tx_data|mem[16][7]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [1] & ((!\A_SPW_TOP|tx_data|wr_ptr [0]) # 
// ((\A_SPW_TOP|tx_data|mem[17][7]~q )))) # (\A_SPW_TOP|tx_data|wr_ptr [1] & (!\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|mem[18][7]~q ))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[19][7]~q  & ( !\A_SPW_TOP|tx_data|mem[16][7]~q  & ( 
// (!\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|mem[17][7]~q )))) # (\A_SPW_TOP|tx_data|wr_ptr [1] & (((\A_SPW_TOP|tx_data|mem[18][7]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [0]))) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|mem[19][7]~q  & ( !\A_SPW_TOP|tx_data|mem[16][7]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|mem[17][7]~q )))) # (\A_SPW_TOP|tx_data|wr_ptr [1] & (!\A_SPW_TOP|tx_data|wr_ptr [0] & 
// (\A_SPW_TOP|tx_data|mem[18][7]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datac(!\A_SPW_TOP|tx_data|mem[18][7]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[17][7]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[19][7]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[16][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux1~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux1~5 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux1~5 .lut_mask = 64'h042615378CAE9DBF;
defparam \A_SPW_TOP|tx_data|Mux1~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y8_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector537~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector537~0_combout  = ( \u0|write_data_fifo_tx|data_out [7] & ( (!\A_SPW_TOP|tx_data|Selector536~0_combout  & (((\A_SPW_TOP|tx_data|mem[59][7]~q )))) # (\A_SPW_TOP|tx_data|Selector536~0_combout  & 
// (((\A_SPW_TOP|tx_data|Mux1~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q ))) ) ) # ( !\u0|write_data_fifo_tx|data_out [7] & ( (!\A_SPW_TOP|tx_data|Selector536~0_combout  & (((\A_SPW_TOP|tx_data|mem[59][7]~q )))) # 
// (\A_SPW_TOP|tx_data|Selector536~0_combout  & (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux1~20_combout ))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector536~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|mem[59][7]~q ),
        .datae(gnd),
        .dataf(!\u0|write_data_fifo_tx|data_out [7]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector537~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector537~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector537~0 .lut_mask = 64'h02F202F207F707F7;
defparam \A_SPW_TOP|tx_data|Selector537~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y8_N29
dffeas \A_SPW_TOP|tx_data|mem[59][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector537~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[59][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[59][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[59][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X51_Y11_N39
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector528~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector528~0_combout  = ( \A_SPW_TOP|tx_data|mem[58][7]~q  & ( (!\A_SPW_TOP|tx_data|Selector527~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux1~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [7]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[58][7]~q  & ( (\A_SPW_TOP|tx_data|Selector527~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux1~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [7])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [7]),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector527~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[58][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector528~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector528~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector528~0 .lut_mask = 64'h010D010DF1FDF1FD;
defparam \A_SPW_TOP|tx_data|Selector528~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X51_Y11_N26
dffeas \A_SPW_TOP|tx_data|mem[58][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector528~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[58][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[58][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[58][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y8_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector519~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector519~0_combout  = ( \u0|write_data_fifo_tx|data_out [7] & ( (!\A_SPW_TOP|tx_data|Selector518~0_combout  & (((\A_SPW_TOP|tx_data|mem[57][7]~q )))) # (\A_SPW_TOP|tx_data|Selector518~0_combout  & 
// (((\A_SPW_TOP|tx_data|Mux1~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q ))) ) ) # ( !\u0|write_data_fifo_tx|data_out [7] & ( (!\A_SPW_TOP|tx_data|Selector518~0_combout  & (((\A_SPW_TOP|tx_data|mem[57][7]~q )))) # 
// (\A_SPW_TOP|tx_data|Selector518~0_combout  & (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux1~20_combout ))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector518~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|mem[57][7]~q ),
        .datae(gnd),
        .dataf(!\u0|write_data_fifo_tx|data_out [7]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector519~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector519~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector519~0 .lut_mask = 64'h02F202F207F707F7;
defparam \A_SPW_TOP|tx_data|Selector519~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y8_N47
dffeas \A_SPW_TOP|tx_data|mem[57][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector519~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[57][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[57][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[57][7] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y11_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector510~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector510~0_combout  = ( \A_SPW_TOP|tx_data|Selector509~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux1~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\u0|write_data_fifo_tx|data_out [7])) ) ) # ( !\A_SPW_TOP|tx_data|Selector509~0_combout  & ( \A_SPW_TOP|tx_data|mem[56][7]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\u0|write_data_fifo_tx|data_out [7]),
        .datac(!\A_SPW_TOP|tx_data|mem[56][7]~q ),
        .datad(!\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector509~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector510~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector510~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector510~0 .lut_mask = 64'h0F0F0F0F11BB11BB;
defparam \A_SPW_TOP|tx_data|Selector510~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y11_N17
dffeas \A_SPW_TOP|tx_data|mem[56][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector510~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[56][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[56][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[56][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y8_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux1~8 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux1~8_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [1] & ( \A_SPW_TOP|tx_data|mem[56][7]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|mem[58][7]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|mem[59][7]~q )) ) 
// ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( \A_SPW_TOP|tx_data|mem[56][7]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [0]) # (\A_SPW_TOP|tx_data|mem[57][7]~q ) ) ) ) # ( \A_SPW_TOP|tx_data|wr_ptr [1] & ( !\A_SPW_TOP|tx_data|mem[56][7]~q  & ( 
// (!\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|mem[58][7]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|mem[59][7]~q )) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( !\A_SPW_TOP|tx_data|mem[56][7]~q  & ( (\A_SPW_TOP|tx_data|wr_ptr 
// [0] & \A_SPW_TOP|tx_data|mem[57][7]~q ) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[59][7]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[58][7]~q ),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datad(!\A_SPW_TOP|tx_data|mem[57][7]~q ),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .dataf(!\A_SPW_TOP|tx_data|mem[56][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux1~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux1~8 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux1~8 .lut_mask = 64'h000F3535F0FF3535;
defparam \A_SPW_TOP|tx_data|Mux1~8 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y8_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux1~9 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux1~9_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [5] & ( \A_SPW_TOP|tx_data|wr_ptr [3] & ( \A_SPW_TOP|tx_data|Mux1~8_combout  ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [5] & ( \A_SPW_TOP|tx_data|wr_ptr [3] & ( \A_SPW_TOP|tx_data|Mux1~6_combout  
// ) ) ) # ( \A_SPW_TOP|tx_data|wr_ptr [5] & ( !\A_SPW_TOP|tx_data|wr_ptr [3] & ( \A_SPW_TOP|tx_data|Mux1~7_combout  ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [5] & ( !\A_SPW_TOP|tx_data|wr_ptr [3] & ( \A_SPW_TOP|tx_data|Mux1~5_combout  ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux1~6_combout ),
        .datab(!\A_SPW_TOP|tx_data|Mux1~7_combout ),
        .datac(!\A_SPW_TOP|tx_data|Mux1~5_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux1~8_combout ),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux1~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux1~9 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux1~9 .lut_mask = 64'h0F0F3333555500FF;
defparam \A_SPW_TOP|tx_data|Mux1~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y8_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector195~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector195~0_combout  = ( \A_SPW_TOP|tx_data|mem[21][7]~q  & ( (!\A_SPW_TOP|tx_data|Selector194~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux1~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [7])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[21][7]~q  & ( (\A_SPW_TOP|tx_data|Selector194~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux1~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [7]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector194~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [7]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[21][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector195~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector195~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector195~0 .lut_mask = 64'h02070207F2F7F2F7;
defparam \A_SPW_TOP|tx_data|Selector195~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y8_N53
dffeas \A_SPW_TOP|tx_data|mem[21][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector195~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[21][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[21][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[21][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y8_N21
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector213~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector213~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( \u0|write_data_fifo_tx|data_out [7] & ( (\A_SPW_TOP|tx_data|Selector212~0_combout ) # (\A_SPW_TOP|tx_data|mem[23][7]~q ) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( \u0|write_data_fifo_tx|data_out [7] & ( (!\A_SPW_TOP|tx_data|Selector212~0_combout  & (\A_SPW_TOP|tx_data|mem[23][7]~q )) # (\A_SPW_TOP|tx_data|Selector212~0_combout  & ((\A_SPW_TOP|tx_data|Mux1~20_combout 
// ))) ) ) ) # ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( !\u0|write_data_fifo_tx|data_out [7] & ( (\A_SPW_TOP|tx_data|mem[23][7]~q  & !\A_SPW_TOP|tx_data|Selector212~0_combout ) ) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( 
// !\u0|write_data_fifo_tx|data_out [7] & ( (!\A_SPW_TOP|tx_data|Selector212~0_combout  & (\A_SPW_TOP|tx_data|mem[23][7]~q )) # (\A_SPW_TOP|tx_data|Selector212~0_combout  & ((\A_SPW_TOP|tx_data|Mux1~20_combout ))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[23][7]~q ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|tx_data|Selector212~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .datae(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .dataf(!\u0|write_data_fifo_tx|data_out [7]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector213~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector213~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector213~0 .lut_mask = 64'h505F5050505F5F5F;
defparam \A_SPW_TOP|tx_data|Selector213~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y8_N35
dffeas \A_SPW_TOP|tx_data|mem[23][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector213~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[23][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[23][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[23][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y8_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector501~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector501~0_combout  = ( \A_SPW_TOP|tx_data|mem[55][7]~q  & ( (!\A_SPW_TOP|tx_data|Selector500~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux1~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [7])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[55][7]~q  & ( (\A_SPW_TOP|tx_data|Selector500~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux1~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [7]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector500~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [7]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[55][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector501~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector501~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector501~0 .lut_mask = 64'h02070207F2F7F2F7;
defparam \A_SPW_TOP|tx_data|Selector501~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y8_N32
dffeas \A_SPW_TOP|tx_data|mem[55][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector501~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[55][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[55][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[55][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y8_N15
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector483~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector483~0_combout  = ( \A_SPW_TOP|tx_data|mem[53][7]~q  & ( (!\A_SPW_TOP|tx_data|Selector482~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux1~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [7])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[53][7]~q  & ( (\A_SPW_TOP|tx_data|Selector482~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux1~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [7]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector482~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [7]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[53][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector483~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector483~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector483~0 .lut_mask = 64'h02070207F2F7F2F7;
defparam \A_SPW_TOP|tx_data|Selector483~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y8_N50
dffeas \A_SPW_TOP|tx_data|mem[53][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector483~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[53][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[53][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[53][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y8_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux1~17 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux1~17_combout  = ( \A_SPW_TOP|tx_data|mem[55][7]~q  & ( \A_SPW_TOP|tx_data|mem[53][7]~q  & ( ((!\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|mem[21][7]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [1] & ((\A_SPW_TOP|tx_data|mem[23][7]~q 
// )))) # (\A_SPW_TOP|tx_data|wr_ptr [5]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[55][7]~q  & ( \A_SPW_TOP|tx_data|mem[53][7]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [1] & (((\A_SPW_TOP|tx_data|wr_ptr [5])) # (\A_SPW_TOP|tx_data|mem[21][7]~q ))) # 
// (\A_SPW_TOP|tx_data|wr_ptr [1] & (((\A_SPW_TOP|tx_data|mem[23][7]~q  & !\A_SPW_TOP|tx_data|wr_ptr [5])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[55][7]~q  & ( !\A_SPW_TOP|tx_data|mem[53][7]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [1] & 
// (\A_SPW_TOP|tx_data|mem[21][7]~q  & ((!\A_SPW_TOP|tx_data|wr_ptr [5])))) # (\A_SPW_TOP|tx_data|wr_ptr [1] & (((\A_SPW_TOP|tx_data|wr_ptr [5]) # (\A_SPW_TOP|tx_data|mem[23][7]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[55][7]~q  & ( 
// !\A_SPW_TOP|tx_data|mem[53][7]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [5] & ((!\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|mem[21][7]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [1] & ((\A_SPW_TOP|tx_data|mem[23][7]~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[21][7]~q ),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datac(!\A_SPW_TOP|tx_data|mem[23][7]~q ),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datae(!\A_SPW_TOP|tx_data|mem[55][7]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[53][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux1~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux1~17 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux1~17 .lut_mask = 64'h4700473347CC47FF;
defparam \A_SPW_TOP|tx_data|Mux1~17 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y8_N21
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector186~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector186~0_combout  = ( \A_SPW_TOP|tx_data|mem[20][7]~q  & ( (!\A_SPW_TOP|tx_data|Selector185~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux1~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [7])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[20][7]~q  & ( (\A_SPW_TOP|tx_data|Selector185~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux1~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [7]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector185~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [7]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[20][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector186~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector186~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector186~0 .lut_mask = 64'h02070207F2F7F2F7;
defparam \A_SPW_TOP|tx_data|Selector186~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y8_N35
dffeas \A_SPW_TOP|tx_data|mem[20][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector186~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[20][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[20][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[20][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y8_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector204~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector204~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( \A_SPW_TOP|tx_data|Selector203~0_combout  & ( \u0|write_data_fifo_tx|data_out [7] ) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( 
// \A_SPW_TOP|tx_data|Selector203~0_combout  & ( \A_SPW_TOP|tx_data|Mux1~20_combout  ) ) ) # ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( !\A_SPW_TOP|tx_data|Selector203~0_combout  & ( \A_SPW_TOP|tx_data|mem[22][7]~q  ) ) ) # ( 
// !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( !\A_SPW_TOP|tx_data|Selector203~0_combout  & ( \A_SPW_TOP|tx_data|mem[22][7]~q  ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .datac(!\u0|write_data_fifo_tx|data_out [7]),
        .datad(!\A_SPW_TOP|tx_data|mem[22][7]~q ),
        .datae(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .dataf(!\A_SPW_TOP|tx_data|Selector203~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector204~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector204~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector204~0 .lut_mask = 64'h00FF00FF33330F0F;
defparam \A_SPW_TOP|tx_data|Selector204~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y8_N11
dffeas \A_SPW_TOP|tx_data|mem[22][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector204~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[22][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[22][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[22][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y8_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector492~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector492~0_combout  = ( \A_SPW_TOP|tx_data|mem[54][7]~q  & ( (!\A_SPW_TOP|tx_data|Selector491~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux1~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [7])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[54][7]~q  & ( (\A_SPW_TOP|tx_data|Selector491~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux1~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [7]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .datac(!\u0|write_data_fifo_tx|data_out [7]),
        .datad(!\A_SPW_TOP|tx_data|Selector491~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[54][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector492~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector492~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector492~0 .lut_mask = 64'h00270027FF27FF27;
defparam \A_SPW_TOP|tx_data|Selector492~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y8_N53
dffeas \A_SPW_TOP|tx_data|mem[54][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector492~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[54][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[54][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[54][7] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y8_N51
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector474~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector474~0_combout  = ( \u0|write_data_fifo_tx|data_out [7] & ( (!\A_SPW_TOP|tx_data|Selector473~0_combout  & (((\A_SPW_TOP|tx_data|mem[52][7]~q )))) # (\A_SPW_TOP|tx_data|Selector473~0_combout  & 
// (((\A_SPW_TOP|tx_data|state_data_write.00~q )) # (\A_SPW_TOP|tx_data|Mux1~20_combout ))) ) ) # ( !\u0|write_data_fifo_tx|data_out [7] & ( (!\A_SPW_TOP|tx_data|Selector473~0_combout  & (((\A_SPW_TOP|tx_data|mem[52][7]~q )))) # 
// (\A_SPW_TOP|tx_data|Selector473~0_combout  & (\A_SPW_TOP|tx_data|Mux1~20_combout  & (!\A_SPW_TOP|tx_data|state_data_write.00~q ))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[52][7]~q ),
        .datad(!\A_SPW_TOP|tx_data|Selector473~0_combout ),
        .datae(gnd),
        .dataf(!\u0|write_data_fifo_tx|data_out [7]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector474~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector474~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector474~0 .lut_mask = 64'h0F440F440F770F77;
defparam \A_SPW_TOP|tx_data|Selector474~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y8_N44
dffeas \A_SPW_TOP|tx_data|mem[52][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector474~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[52][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[52][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[52][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y8_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux1~15 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux1~15_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [5] & ( \A_SPW_TOP|tx_data|mem[52][7]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [1]) # (\A_SPW_TOP|tx_data|mem[54][7]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [5] & ( 
// \A_SPW_TOP|tx_data|mem[52][7]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|mem[20][7]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [1] & ((\A_SPW_TOP|tx_data|mem[22][7]~q ))) ) ) ) # ( \A_SPW_TOP|tx_data|wr_ptr [5] & ( 
// !\A_SPW_TOP|tx_data|mem[52][7]~q  & ( (\A_SPW_TOP|tx_data|mem[54][7]~q  & \A_SPW_TOP|tx_data|wr_ptr [1]) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [5] & ( !\A_SPW_TOP|tx_data|mem[52][7]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|mem[20][7]~q 
// )) # (\A_SPW_TOP|tx_data|wr_ptr [1] & ((\A_SPW_TOP|tx_data|mem[22][7]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[20][7]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[22][7]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[54][7]~q ),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .dataf(!\A_SPW_TOP|tx_data|mem[52][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux1~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux1~15 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux1~15 .lut_mask = 64'h5533000F5533FF0F;
defparam \A_SPW_TOP|tx_data|Mux1~15 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y8_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector258~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector258~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector257~0_combout  & ((\A_SPW_TOP|tx_data|mem[28][7]~q ))) # (\A_SPW_TOP|tx_data|Selector257~0_combout  & (\u0|write_data_fifo_tx|data_out 
// [7])) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector257~0_combout  & ((\A_SPW_TOP|tx_data|mem[28][7]~q ))) # (\A_SPW_TOP|tx_data|Selector257~0_combout  & (\A_SPW_TOP|tx_data|Mux1~20_combout )) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [7]),
        .datab(!\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|mem[28][7]~q ),
        .datad(!\A_SPW_TOP|tx_data|Selector257~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector258~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector258~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector258~0 .lut_mask = 64'h0F330F330F550F55;
defparam \A_SPW_TOP|tx_data|Selector258~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y8_N23
dffeas \A_SPW_TOP|tx_data|mem[28][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector258~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[28][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[28][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[28][7] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y8_N33
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector564~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector564~0_combout  = ( \A_SPW_TOP|tx_data|Selector563~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux1~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\u0|write_data_fifo_tx|data_out [7])) ) ) # ( !\A_SPW_TOP|tx_data|Selector563~0_combout  & ( \A_SPW_TOP|tx_data|mem[62][7]~q  ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [7]),
        .datab(!\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|mem[62][7]~q ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector563~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector564~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector564~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector564~0 .lut_mask = 64'h0F0F0F0F33553355;
defparam \A_SPW_TOP|tx_data|Selector564~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y8_N17
dffeas \A_SPW_TOP|tx_data|mem[62][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector564~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[62][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[62][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[62][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y8_N39
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector276~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector276~0_combout  = ( \A_SPW_TOP|tx_data|Selector275~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux1~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [7]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector275~0_combout  & ( \A_SPW_TOP|tx_data|mem[30][7]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\u0|write_data_fifo_tx|data_out [7]),
        .datad(!\A_SPW_TOP|tx_data|mem[30][7]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector275~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector276~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector276~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector276~0 .lut_mask = 64'h00FF00FF47474747;
defparam \A_SPW_TOP|tx_data|Selector276~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y8_N5
dffeas \A_SPW_TOP|tx_data|mem[30][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector276~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[30][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[30][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[30][7] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y8_N39
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector546~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector546~0_combout  = ( \A_SPW_TOP|tx_data|Selector545~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux1~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\u0|write_data_fifo_tx|data_out [7])) ) ) # ( !\A_SPW_TOP|tx_data|Selector545~0_combout  & ( \A_SPW_TOP|tx_data|mem[60][7]~q  ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [7]),
        .datab(!\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|mem[60][7]~q ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector545~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector546~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector546~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector546~0 .lut_mask = 64'h0F0F0F0F33553355;
defparam \A_SPW_TOP|tx_data|Selector546~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y8_N59
dffeas \A_SPW_TOP|tx_data|mem[60][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector546~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[60][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[60][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[60][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y8_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux1~16 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux1~16_combout  = ( \A_SPW_TOP|tx_data|mem[30][7]~q  & ( \A_SPW_TOP|tx_data|mem[60][7]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [1] & (((\A_SPW_TOP|tx_data|wr_ptr [5])) # (\A_SPW_TOP|tx_data|mem[28][7]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [1] 
// & (((!\A_SPW_TOP|tx_data|wr_ptr [5]) # (\A_SPW_TOP|tx_data|mem[62][7]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[30][7]~q  & ( \A_SPW_TOP|tx_data|mem[60][7]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [1] & (((\A_SPW_TOP|tx_data|wr_ptr [5])) # 
// (\A_SPW_TOP|tx_data|mem[28][7]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [1] & (((\A_SPW_TOP|tx_data|mem[62][7]~q  & \A_SPW_TOP|tx_data|wr_ptr [5])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[30][7]~q  & ( !\A_SPW_TOP|tx_data|mem[60][7]~q  & ( 
// (!\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|mem[28][7]~q  & ((!\A_SPW_TOP|tx_data|wr_ptr [5])))) # (\A_SPW_TOP|tx_data|wr_ptr [1] & (((!\A_SPW_TOP|tx_data|wr_ptr [5]) # (\A_SPW_TOP|tx_data|mem[62][7]~q )))) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|mem[30][7]~q  & ( !\A_SPW_TOP|tx_data|mem[60][7]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|mem[28][7]~q  & ((!\A_SPW_TOP|tx_data|wr_ptr [5])))) # (\A_SPW_TOP|tx_data|wr_ptr [1] & (((\A_SPW_TOP|tx_data|mem[62][7]~q  & 
// \A_SPW_TOP|tx_data|wr_ptr [5])))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datab(!\A_SPW_TOP|tx_data|mem[28][7]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[62][7]~q ),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datae(!\A_SPW_TOP|tx_data|mem[30][7]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[60][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux1~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux1~16 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux1~16 .lut_mask = 64'h2205770522AF77AF;
defparam \A_SPW_TOP|tx_data|Mux1~16 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y8_N45
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector285~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector285~0_combout  = ( \A_SPW_TOP|tx_data|Selector284~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux1~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [7]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector284~0_combout  & ( \A_SPW_TOP|tx_data|mem[31][7]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\u0|write_data_fifo_tx|data_out [7]),
        .datad(!\A_SPW_TOP|tx_data|mem[31][7]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector284~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector285~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector285~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector285~0 .lut_mask = 64'h00FF00FF47474747;
defparam \A_SPW_TOP|tx_data|Selector285~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y8_N29
dffeas \A_SPW_TOP|tx_data|mem[31][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector285~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[31][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[31][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[31][7] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y8_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector555~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector555~0_combout  = ( \A_SPW_TOP|tx_data|Selector554~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux1~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\u0|write_data_fifo_tx|data_out [7])) ) ) # ( !\A_SPW_TOP|tx_data|Selector554~0_combout  & ( \A_SPW_TOP|tx_data|mem[61][7]~q  ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [7]),
        .datab(!\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|mem[61][7]~q ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector554~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector555~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector555~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector555~0 .lut_mask = 64'h0F0F0F0F33553355;
defparam \A_SPW_TOP|tx_data|Selector555~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y8_N56
dffeas \A_SPW_TOP|tx_data|mem[61][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector555~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[61][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[61][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[61][7] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y8_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector573~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector573~0_combout  = ( \A_SPW_TOP|tx_data|Selector572~0_combout  & ( \A_SPW_TOP|tx_data|mem[63][7]~q  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux1~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [7])) ) ) ) # ( !\A_SPW_TOP|tx_data|Selector572~0_combout  & ( \A_SPW_TOP|tx_data|mem[63][7]~q  ) ) # ( \A_SPW_TOP|tx_data|Selector572~0_combout  & ( 
// !\A_SPW_TOP|tx_data|mem[63][7]~q  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux1~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [7])) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(gnd),
        .datac(!\u0|write_data_fifo_tx|data_out [7]),
        .datad(!\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .datae(!\A_SPW_TOP|tx_data|Selector572~0_combout ),
        .dataf(!\A_SPW_TOP|tx_data|mem[63][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector573~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector573~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector573~0 .lut_mask = 64'h000005AFFFFF05AF;
defparam \A_SPW_TOP|tx_data|Selector573~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y8_N14
dffeas \A_SPW_TOP|tx_data|mem[63][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector573~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[63][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[63][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[63][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y8_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector267~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector267~0_combout  = ( \A_SPW_TOP|tx_data|Selector266~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux1~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [7]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector266~0_combout  & ( \A_SPW_TOP|tx_data|mem[29][7]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[29][7]~q ),
        .datad(!\u0|write_data_fifo_tx|data_out [7]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector266~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector267~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector267~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector267~0 .lut_mask = 64'h0F0F0F0F44774477;
defparam \A_SPW_TOP|tx_data|Selector267~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y8_N23
dffeas \A_SPW_TOP|tx_data|mem[29][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector267~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[29][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[29][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[29][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y8_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux1~18 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux1~18_combout  = ( \A_SPW_TOP|tx_data|mem[29][7]~q  & ( \A_SPW_TOP|tx_data|wr_ptr [1] & ( (!\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|mem[31][7]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [5] & ((\A_SPW_TOP|tx_data|mem[63][7]~q ))) ) 
// ) ) # ( !\A_SPW_TOP|tx_data|mem[29][7]~q  & ( \A_SPW_TOP|tx_data|wr_ptr [1] & ( (!\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|mem[31][7]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [5] & ((\A_SPW_TOP|tx_data|mem[63][7]~q ))) ) ) ) # ( 
// \A_SPW_TOP|tx_data|mem[29][7]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( (!\A_SPW_TOP|tx_data|wr_ptr [5]) # (\A_SPW_TOP|tx_data|mem[61][7]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[29][7]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( 
// (\A_SPW_TOP|tx_data|mem[61][7]~q  & \A_SPW_TOP|tx_data|wr_ptr [5]) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[31][7]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[61][7]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[63][7]~q ),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datae(!\A_SPW_TOP|tx_data|mem[29][7]~q ),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux1~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux1~18 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux1~18 .lut_mask = 64'h0033FF33550F550F;
defparam \A_SPW_TOP|tx_data|Mux1~18 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y8_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux1~19 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux1~19_combout  = ( \A_SPW_TOP|tx_data|Mux1~18_combout  & ( \A_SPW_TOP|tx_data|wr_ptr [3] & ( (\A_SPW_TOP|tx_data|Mux1~16_combout ) # (\A_SPW_TOP|tx_data|wr_ptr [0]) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux1~18_combout  & ( 
// \A_SPW_TOP|tx_data|wr_ptr [3] & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & \A_SPW_TOP|tx_data|Mux1~16_combout ) ) ) ) # ( \A_SPW_TOP|tx_data|Mux1~18_combout  & ( !\A_SPW_TOP|tx_data|wr_ptr [3] & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & 
// ((\A_SPW_TOP|tx_data|Mux1~15_combout ))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|Mux1~17_combout )) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux1~18_combout  & ( !\A_SPW_TOP|tx_data|wr_ptr [3] & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & 
// ((\A_SPW_TOP|tx_data|Mux1~15_combout ))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|Mux1~17_combout )) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux1~17_combout ),
        .datab(!\A_SPW_TOP|tx_data|Mux1~15_combout ),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datad(!\A_SPW_TOP|tx_data|Mux1~16_combout ),
        .datae(!\A_SPW_TOP|tx_data|Mux1~18_combout ),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux1~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux1~19 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux1~19 .lut_mask = 64'h3535353500F00FFF;
defparam \A_SPW_TOP|tx_data|Mux1~19 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y8_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector114~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector114~0_combout  = ( \A_SPW_TOP|tx_data|mem[12][7]~q  & ( (!\A_SPW_TOP|tx_data|Selector113~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux1~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [7])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[12][7]~q  & ( (\A_SPW_TOP|tx_data|Selector113~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux1~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [7]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector113~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [7]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[12][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector114~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector114~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector114~0 .lut_mask = 64'h04070407F4F7F4F7;
defparam \A_SPW_TOP|tx_data|Selector114~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y8_N53
dffeas \A_SPW_TOP|tx_data|mem[12][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector114~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[12][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[12][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[12][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y8_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector132~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector132~0_combout  = ( \A_SPW_TOP|tx_data|Selector131~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux1~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [7]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector131~0_combout  & ( \A_SPW_TOP|tx_data|mem[14][7]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\u0|write_data_fifo_tx|data_out [7]),
        .datad(!\A_SPW_TOP|tx_data|mem[14][7]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector131~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector132~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector132~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector132~0 .lut_mask = 64'h00FF00FF47474747;
defparam \A_SPW_TOP|tx_data|Selector132~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y8_N11
dffeas \A_SPW_TOP|tx_data|mem[14][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector132~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[14][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[14][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[14][7] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y8_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector123~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector123~0_combout  = ( \A_SPW_TOP|tx_data|mem[13][7]~q  & ( (!\A_SPW_TOP|tx_data|Selector122~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux1~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [7]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[13][7]~q  & ( (\A_SPW_TOP|tx_data|Selector122~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux1~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [7])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [7]),
        .datab(!\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector122~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[13][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector123~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector123~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector123~0 .lut_mask = 64'h03050305F3F5F3F5;
defparam \A_SPW_TOP|tx_data|Selector123~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y8_N20
dffeas \A_SPW_TOP|tx_data|mem[13][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector123~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[13][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[13][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[13][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y8_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector141~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector141~0_combout  = ( \A_SPW_TOP|tx_data|mem[15][7]~q  & ( (!\A_SPW_TOP|tx_data|Selector140~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux1~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [7])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[15][7]~q  & ( (\A_SPW_TOP|tx_data|Selector140~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux1~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [7]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\u0|write_data_fifo_tx|data_out [7]),
        .datad(!\A_SPW_TOP|tx_data|Selector140~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[15][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector141~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector141~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector141~0 .lut_mask = 64'h00470047FF47FF47;
defparam \A_SPW_TOP|tx_data|Selector141~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y8_N35
dffeas \A_SPW_TOP|tx_data|mem[15][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector141~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[15][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[15][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[15][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y8_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux1~11 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux1~11_combout  = ( \A_SPW_TOP|tx_data|mem[13][7]~q  & ( \A_SPW_TOP|tx_data|mem[15][7]~q  & ( ((!\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|mem[12][7]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [1] & ((\A_SPW_TOP|tx_data|mem[14][7]~q 
// )))) # (\A_SPW_TOP|tx_data|wr_ptr [0]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[13][7]~q  & ( \A_SPW_TOP|tx_data|mem[15][7]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & ((!\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|mem[12][7]~q )) # 
// (\A_SPW_TOP|tx_data|wr_ptr [1] & ((\A_SPW_TOP|tx_data|mem[14][7]~q ))))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & (((\A_SPW_TOP|tx_data|wr_ptr [1])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[13][7]~q  & ( !\A_SPW_TOP|tx_data|mem[15][7]~q  & ( 
// (!\A_SPW_TOP|tx_data|wr_ptr [0] & ((!\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|mem[12][7]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [1] & ((\A_SPW_TOP|tx_data|mem[14][7]~q ))))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & (((!\A_SPW_TOP|tx_data|wr_ptr [1])))) ) 
// ) ) # ( !\A_SPW_TOP|tx_data|mem[13][7]~q  & ( !\A_SPW_TOP|tx_data|mem[15][7]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & ((!\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|mem[12][7]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [1] & 
// ((\A_SPW_TOP|tx_data|mem[14][7]~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[12][7]~q ),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datad(!\A_SPW_TOP|tx_data|mem[14][7]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[13][7]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[15][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux1~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux1~11 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux1~11 .lut_mask = 64'h404C707C434F737F;
defparam \A_SPW_TOP|tx_data|Mux1~11 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y8_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector69~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector69~0_combout  = ( \A_SPW_TOP|tx_data|mem[7][7]~q  & ( (!\A_SPW_TOP|tx_data|Selector68~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux1~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [7])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[7][7]~q  & ( (\A_SPW_TOP|tx_data|Selector68~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux1~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [7]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\u0|write_data_fifo_tx|data_out [7]),
        .datad(!\A_SPW_TOP|tx_data|Selector68~0_combout ),
        .datae(!\A_SPW_TOP|tx_data|mem[7][7]~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector69~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector69~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector69~0 .lut_mask = 64'h0047FF470047FF47;
defparam \A_SPW_TOP|tx_data|Selector69~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y8_N5
dffeas \A_SPW_TOP|tx_data|mem[7][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector69~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[7][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[7][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[7][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y8_N33
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector60~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector60~0_combout  = ( \A_SPW_TOP|tx_data|Selector59~0_combout  & ( \A_SPW_TOP|tx_data|Mux1~20_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q ) # (\u0|write_data_fifo_tx|data_out [7]) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|Selector59~0_combout  & ( \A_SPW_TOP|tx_data|Mux1~20_combout  & ( \A_SPW_TOP|tx_data|mem[6][7]~q  ) ) ) # ( \A_SPW_TOP|tx_data|Selector59~0_combout  & ( !\A_SPW_TOP|tx_data|Mux1~20_combout  & ( (\A_SPW_TOP|tx_data|state_data_write.00~q 
//  & \u0|write_data_fifo_tx|data_out [7]) ) ) ) # ( !\A_SPW_TOP|tx_data|Selector59~0_combout  & ( !\A_SPW_TOP|tx_data|Mux1~20_combout  & ( \A_SPW_TOP|tx_data|mem[6][7]~q  ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[6][7]~q ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(!\u0|write_data_fifo_tx|data_out [7]),
        .datae(!\A_SPW_TOP|tx_data|Selector59~0_combout ),
        .dataf(!\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector60~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector60~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector60~0 .lut_mask = 64'h5555000F5555F0FF;
defparam \A_SPW_TOP|tx_data|Selector60~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y8_N47
dffeas \A_SPW_TOP|tx_data|mem[6][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector60~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[6][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[6][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[6][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y8_N57
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector51~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector51~0_combout  = ( \A_SPW_TOP|tx_data|mem[5][7]~q  & ( (!\A_SPW_TOP|tx_data|Selector50~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux1~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [7])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[5][7]~q  & ( (\A_SPW_TOP|tx_data|Selector50~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux1~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [7]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector50~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [7]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[5][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector51~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector51~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector51~0 .lut_mask = 64'h02070207F2F7F2F7;
defparam \A_SPW_TOP|tx_data|Selector51~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y8_N20
dffeas \A_SPW_TOP|tx_data|mem[5][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector51~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[5][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[5][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[5][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y8_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector42~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector42~0_combout  = ( \A_SPW_TOP|tx_data|mem[4][7]~q  & ( (!\A_SPW_TOP|tx_data|Selector41~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux1~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [7])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[4][7]~q  & ( (\A_SPW_TOP|tx_data|Selector41~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux1~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [7]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector41~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [7]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[4][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector42~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector42~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector42~0 .lut_mask = 64'h02070207F2F7F2F7;
defparam \A_SPW_TOP|tx_data|Selector42~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y8_N11
dffeas \A_SPW_TOP|tx_data|mem[4][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector42~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[4][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[4][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[4][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y8_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux1~10 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux1~10_combout  = ( \A_SPW_TOP|tx_data|mem[5][7]~q  & ( \A_SPW_TOP|tx_data|mem[4][7]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [1]) # ((!\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|mem[6][7]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & 
// (\A_SPW_TOP|tx_data|mem[7][7]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[5][7]~q  & ( \A_SPW_TOP|tx_data|mem[4][7]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [1] & (((!\A_SPW_TOP|tx_data|wr_ptr [0])))) # (\A_SPW_TOP|tx_data|wr_ptr [1] & ((!\A_SPW_TOP|tx_data|wr_ptr 
// [0] & ((\A_SPW_TOP|tx_data|mem[6][7]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|mem[7][7]~q )))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[5][7]~q  & ( !\A_SPW_TOP|tx_data|mem[4][7]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [1] & 
// (((\A_SPW_TOP|tx_data|wr_ptr [0])))) # (\A_SPW_TOP|tx_data|wr_ptr [1] & ((!\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|mem[6][7]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|mem[7][7]~q )))) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|mem[5][7]~q  & ( !\A_SPW_TOP|tx_data|mem[4][7]~q  & ( (\A_SPW_TOP|tx_data|wr_ptr [1] & ((!\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|mem[6][7]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|mem[7][7]~q )))) ) ) 
// )

        .dataa(!\A_SPW_TOP|tx_data|mem[7][7]~q ),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datad(!\A_SPW_TOP|tx_data|mem[6][7]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[5][7]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[4][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux1~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux1~10 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux1~10 .lut_mask = 64'h01310D3DC1F1CDFD;
defparam \A_SPW_TOP|tx_data|Mux1~10 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y8_N39
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector348~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector348~0_combout  = ( \A_SPW_TOP|tx_data|mem[38][7]~q  & ( \A_SPW_TOP|tx_data|Selector347~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux1~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [7]))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[38][7]~q  & ( \A_SPW_TOP|tx_data|Selector347~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux1~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [7]))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[38][7]~q  & ( !\A_SPW_TOP|tx_data|Selector347~0_combout  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(!\u0|write_data_fifo_tx|data_out [7]),
        .datae(!\A_SPW_TOP|tx_data|mem[38][7]~q ),
        .dataf(!\A_SPW_TOP|tx_data|Selector347~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector348~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector348~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector348~0 .lut_mask = 64'h0000FFFF505F505F;
defparam \A_SPW_TOP|tx_data|Selector348~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y8_N2
dffeas \A_SPW_TOP|tx_data|mem[38][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector348~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[38][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[38][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[38][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y8_N39
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector330~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector330~0_combout  = ( \A_SPW_TOP|tx_data|mem[36][7]~q  & ( (!\A_SPW_TOP|tx_data|Selector329~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux1~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [7])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[36][7]~q  & ( (\A_SPW_TOP|tx_data|Selector329~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux1~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [7]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .datac(!\u0|write_data_fifo_tx|data_out [7]),
        .datad(!\A_SPW_TOP|tx_data|Selector329~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[36][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector330~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector330~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector330~0 .lut_mask = 64'h00270027FF27FF27;
defparam \A_SPW_TOP|tx_data|Selector330~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y8_N44
dffeas \A_SPW_TOP|tx_data|mem[36][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector330~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[36][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[36][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[36][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y8_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector357~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector357~0_combout  = ( \u0|write_data_fifo_tx|data_out [7] & ( (!\A_SPW_TOP|tx_data|Selector356~0_combout  & (((\A_SPW_TOP|tx_data|mem[39][7]~q )))) # (\A_SPW_TOP|tx_data|Selector356~0_combout  & 
// (((\A_SPW_TOP|tx_data|Mux1~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q ))) ) ) # ( !\u0|write_data_fifo_tx|data_out [7] & ( (!\A_SPW_TOP|tx_data|Selector356~0_combout  & (((\A_SPW_TOP|tx_data|mem[39][7]~q )))) # 
// (\A_SPW_TOP|tx_data|Selector356~0_combout  & (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux1~20_combout ))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|mem[39][7]~q ),
        .datad(!\A_SPW_TOP|tx_data|Selector356~0_combout ),
        .datae(gnd),
        .dataf(!\u0|write_data_fifo_tx|data_out [7]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector357~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector357~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector357~0 .lut_mask = 64'h0F220F220F770F77;
defparam \A_SPW_TOP|tx_data|Selector357~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y8_N23
dffeas \A_SPW_TOP|tx_data|mem[39][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector357~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[39][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[39][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[39][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y8_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector339~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector339~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( \A_SPW_TOP|tx_data|Selector338~0_combout  & ( \u0|write_data_fifo_tx|data_out [7] ) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( 
// \A_SPW_TOP|tx_data|Selector338~0_combout  & ( \A_SPW_TOP|tx_data|Mux1~20_combout  ) ) ) # ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( !\A_SPW_TOP|tx_data|Selector338~0_combout  & ( \A_SPW_TOP|tx_data|mem[37][7]~q  ) ) ) # ( 
// !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( !\A_SPW_TOP|tx_data|Selector338~0_combout  & ( \A_SPW_TOP|tx_data|mem[37][7]~q  ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|mem[37][7]~q ),
        .datac(gnd),
        .datad(!\u0|write_data_fifo_tx|data_out [7]),
        .datae(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .dataf(!\A_SPW_TOP|tx_data|Selector338~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector339~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector339~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector339~0 .lut_mask = 64'h33333333555500FF;
defparam \A_SPW_TOP|tx_data|Selector339~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y8_N26
dffeas \A_SPW_TOP|tx_data|mem[37][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector339~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[37][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[37][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[37][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y8_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux1~12 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux1~12_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [1] & ( \A_SPW_TOP|tx_data|wr_ptr [0] & ( \A_SPW_TOP|tx_data|mem[39][7]~q  ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( \A_SPW_TOP|tx_data|wr_ptr [0] & ( \A_SPW_TOP|tx_data|mem[37][7]~q  ) 
// ) ) # ( \A_SPW_TOP|tx_data|wr_ptr [1] & ( !\A_SPW_TOP|tx_data|wr_ptr [0] & ( \A_SPW_TOP|tx_data|mem[38][7]~q  ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( !\A_SPW_TOP|tx_data|wr_ptr [0] & ( \A_SPW_TOP|tx_data|mem[36][7]~q  ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[38][7]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[36][7]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[39][7]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[37][7]~q ),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux1~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux1~12 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux1~12 .lut_mask = 64'h3333555500FF0F0F;
defparam \A_SPW_TOP|tx_data|Mux1~12 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y8_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector402~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector402~0_combout  = ( \A_SPW_TOP|tx_data|Selector401~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux1~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [7]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector401~0_combout  & ( \A_SPW_TOP|tx_data|mem[44][7]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\u0|write_data_fifo_tx|data_out [7]),
        .datad(!\A_SPW_TOP|tx_data|mem[44][7]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector401~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector402~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector402~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector402~0 .lut_mask = 64'h00FF00FF47474747;
defparam \A_SPW_TOP|tx_data|Selector402~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y8_N26
dffeas \A_SPW_TOP|tx_data|mem[44][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector402~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[44][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[44][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[44][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y8_N57
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector420~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector420~0_combout  = ( \A_SPW_TOP|tx_data|Selector419~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux1~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [7]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector419~0_combout  & ( \A_SPW_TOP|tx_data|mem[46][7]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\u0|write_data_fifo_tx|data_out [7]),
        .datad(!\A_SPW_TOP|tx_data|mem[46][7]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector419~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector420~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector420~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector420~0 .lut_mask = 64'h00FF00FF47474747;
defparam \A_SPW_TOP|tx_data|Selector420~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y8_N8
dffeas \A_SPW_TOP|tx_data|mem[46][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector420~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[46][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[46][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[46][7] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y8_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector429~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector429~0_combout  = ( \A_SPW_TOP|tx_data|Selector428~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux1~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\u0|write_data_fifo_tx|data_out [7])) ) ) # ( !\A_SPW_TOP|tx_data|Selector428~0_combout  & ( \A_SPW_TOP|tx_data|mem[47][7]~q  ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [7]),
        .datab(!\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[47][7]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector428~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector429~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector429~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector429~0 .lut_mask = 64'h00FF00FF35353535;
defparam \A_SPW_TOP|tx_data|Selector429~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y8_N29
dffeas \A_SPW_TOP|tx_data|mem[47][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector429~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[47][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[47][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[47][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y8_N27
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector411~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector411~0_combout  = ( \A_SPW_TOP|tx_data|Selector410~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux1~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [7]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector410~0_combout  & ( \A_SPW_TOP|tx_data|mem[45][7]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|mem[45][7]~q ),
        .datad(!\u0|write_data_fifo_tx|data_out [7]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector410~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector411~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector411~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector411~0 .lut_mask = 64'h0F0F0F0F22772277;
defparam \A_SPW_TOP|tx_data|Selector411~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y8_N47
dffeas \A_SPW_TOP|tx_data|mem[45][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector411~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[45][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[45][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[45][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y8_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux1~13 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux1~13_combout  = ( \A_SPW_TOP|tx_data|mem[45][7]~q  & ( \A_SPW_TOP|tx_data|wr_ptr [1] & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|mem[46][7]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|mem[47][7]~q ))) ) 
// ) ) # ( !\A_SPW_TOP|tx_data|mem[45][7]~q  & ( \A_SPW_TOP|tx_data|wr_ptr [1] & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|mem[46][7]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|mem[47][7]~q ))) ) ) ) # ( 
// \A_SPW_TOP|tx_data|mem[45][7]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( (\A_SPW_TOP|tx_data|wr_ptr [0]) # (\A_SPW_TOP|tx_data|mem[44][7]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[45][7]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( 
// (\A_SPW_TOP|tx_data|mem[44][7]~q  & !\A_SPW_TOP|tx_data|wr_ptr [0]) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[44][7]~q ),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datac(!\A_SPW_TOP|tx_data|mem[46][7]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[47][7]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[45][7]~q ),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux1~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux1~13 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux1~13 .lut_mask = 64'h444477770C3F0C3F;
defparam \A_SPW_TOP|tx_data|Mux1~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y8_N15
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux1~14 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux1~14_combout  = ( \A_SPW_TOP|tx_data|Mux1~12_combout  & ( \A_SPW_TOP|tx_data|Mux1~13_combout  & ( ((!\A_SPW_TOP|tx_data|wr_ptr [3] & ((\A_SPW_TOP|tx_data|Mux1~10_combout ))) # (\A_SPW_TOP|tx_data|wr_ptr [3] & 
// (\A_SPW_TOP|tx_data|Mux1~11_combout ))) # (\A_SPW_TOP|tx_data|wr_ptr [5]) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux1~12_combout  & ( \A_SPW_TOP|tx_data|Mux1~13_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [3] & (((\A_SPW_TOP|tx_data|Mux1~10_combout  & 
// !\A_SPW_TOP|tx_data|wr_ptr [5])))) # (\A_SPW_TOP|tx_data|wr_ptr [3] & (((\A_SPW_TOP|tx_data|wr_ptr [5])) # (\A_SPW_TOP|tx_data|Mux1~11_combout ))) ) ) ) # ( \A_SPW_TOP|tx_data|Mux1~12_combout  & ( !\A_SPW_TOP|tx_data|Mux1~13_combout  & ( 
// (!\A_SPW_TOP|tx_data|wr_ptr [3] & (((\A_SPW_TOP|tx_data|wr_ptr [5]) # (\A_SPW_TOP|tx_data|Mux1~10_combout )))) # (\A_SPW_TOP|tx_data|wr_ptr [3] & (\A_SPW_TOP|tx_data|Mux1~11_combout  & ((!\A_SPW_TOP|tx_data|wr_ptr [5])))) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|Mux1~12_combout  & ( !\A_SPW_TOP|tx_data|Mux1~13_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [5] & ((!\A_SPW_TOP|tx_data|wr_ptr [3] & ((\A_SPW_TOP|tx_data|Mux1~10_combout ))) # (\A_SPW_TOP|tx_data|wr_ptr [3] & 
// (\A_SPW_TOP|tx_data|Mux1~11_combout )))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux1~11_combout ),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datac(!\A_SPW_TOP|tx_data|Mux1~10_combout ),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datae(!\A_SPW_TOP|tx_data|Mux1~12_combout ),
        .dataf(!\A_SPW_TOP|tx_data|Mux1~13_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux1~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux1~14 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux1~14 .lut_mask = 64'h1D001DCC1D331DFF;
defparam \A_SPW_TOP|tx_data|Mux1~14 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y11_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector24~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector24~0_combout  = ( \A_SPW_TOP|tx_data|Selector23~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux1~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\u0|write_data_fifo_tx|data_out [7])) ) ) # ( !\A_SPW_TOP|tx_data|Selector23~0_combout  & ( \A_SPW_TOP|tx_data|mem[2][7]~q  ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [7]),
        .datab(!\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[2][7]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector23~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector24~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector24~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector24~0 .lut_mask = 64'h00FF00FF35353535;
defparam \A_SPW_TOP|tx_data|Selector24~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y11_N23
dffeas \A_SPW_TOP|tx_data|mem[2][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector24~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[2][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[2][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[2][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y11_N33
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector33~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector33~0_combout  = ( \A_SPW_TOP|tx_data|mem[3][7]~q  & ( (!\A_SPW_TOP|tx_data|Selector32~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux1~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [7])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[3][7]~q  & ( (\A_SPW_TOP|tx_data|Selector32~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux1~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [7]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector32~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [7]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[3][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector33~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector33~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector33~0 .lut_mask = 64'h02070207F2F7F2F7;
defparam \A_SPW_TOP|tx_data|Selector33~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y11_N20
dffeas \A_SPW_TOP|tx_data|mem[3][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector33~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[3][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[3][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[3][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y11_N57
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector15~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector15~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector14~0_combout  & ((\A_SPW_TOP|tx_data|mem[1][7]~q ))) # (\A_SPW_TOP|tx_data|Selector14~0_combout  & (\u0|write_data_fifo_tx|data_out 
// [7])) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector14~0_combout  & (\A_SPW_TOP|tx_data|mem[1][7]~q )) # (\A_SPW_TOP|tx_data|Selector14~0_combout  & ((\A_SPW_TOP|tx_data|Mux1~20_combout ))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [7]),
        .datab(!\A_SPW_TOP|tx_data|mem[1][7]~q ),
        .datac(!\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .datad(!\A_SPW_TOP|tx_data|Selector14~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector15~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector15~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector15~0 .lut_mask = 64'h330F330F33553355;
defparam \A_SPW_TOP|tx_data|Selector15~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y11_N17
dffeas \A_SPW_TOP|tx_data|mem[1][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector15~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[1][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[1][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[1][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y11_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux1~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux1~0_combout  = ( \A_SPW_TOP|tx_data|mem[3][7]~q  & ( \A_SPW_TOP|tx_data|mem[1][7]~q  & ( ((!\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|mem[0][7]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [1] & ((\A_SPW_TOP|tx_data|mem[2][7]~q )))) # 
// (\A_SPW_TOP|tx_data|wr_ptr [0]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[3][7]~q  & ( \A_SPW_TOP|tx_data|mem[1][7]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & ((!\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|mem[0][7]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [1] & 
// ((\A_SPW_TOP|tx_data|mem[2][7]~q ))))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & (((!\A_SPW_TOP|tx_data|wr_ptr [1])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[3][7]~q  & ( !\A_SPW_TOP|tx_data|mem[1][7]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & 
// ((!\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|mem[0][7]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [1] & ((\A_SPW_TOP|tx_data|mem[2][7]~q ))))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & (((\A_SPW_TOP|tx_data|wr_ptr [1])))) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|mem[3][7]~q  & ( !\A_SPW_TOP|tx_data|mem[1][7]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & ((!\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|mem[0][7]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [1] & ((\A_SPW_TOP|tx_data|mem[2][7]~q ))))) ) ) 
// )

        .dataa(!\A_SPW_TOP|tx_data|mem[0][7]~q ),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datac(!\A_SPW_TOP|tx_data|mem[2][7]~q ),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datae(!\A_SPW_TOP|tx_data|mem[3][7]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[1][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux1~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux1~0 .lut_mask = 64'h440C443F770C773F;
defparam \A_SPW_TOP|tx_data|Mux1~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y12_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector384~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector384~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( \A_SPW_TOP|tx_data|mem[42][7]~q  & ( (!\A_SPW_TOP|tx_data|Selector383~0_combout ) # (\u0|write_data_fifo_tx|data_out [7]) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( \A_SPW_TOP|tx_data|mem[42][7]~q  & ( (!\A_SPW_TOP|tx_data|Selector383~0_combout ) # (\A_SPW_TOP|tx_data|Mux1~20_combout ) ) ) ) # ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( 
// !\A_SPW_TOP|tx_data|mem[42][7]~q  & ( (\A_SPW_TOP|tx_data|Selector383~0_combout  & \u0|write_data_fifo_tx|data_out [7]) ) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( !\A_SPW_TOP|tx_data|mem[42][7]~q  & ( 
// (\A_SPW_TOP|tx_data|Selector383~0_combout  & \A_SPW_TOP|tx_data|Mux1~20_combout ) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Selector383~0_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [7]),
        .datac(!\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[42][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector384~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector384~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector384~0 .lut_mask = 64'h05051111AFAFBBBB;
defparam \A_SPW_TOP|tx_data|Selector384~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y12_N35
dffeas \A_SPW_TOP|tx_data|mem[42][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector384~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[42][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[42][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[42][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y8_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector366~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector366~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( \A_SPW_TOP|tx_data|Selector365~0_combout  & ( \u0|write_data_fifo_tx|data_out [7] ) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( 
// \A_SPW_TOP|tx_data|Selector365~0_combout  & ( \A_SPW_TOP|tx_data|Mux1~20_combout  ) ) ) # ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( !\A_SPW_TOP|tx_data|Selector365~0_combout  & ( \A_SPW_TOP|tx_data|mem[40][7]~q  ) ) ) # ( 
// !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( !\A_SPW_TOP|tx_data|Selector365~0_combout  & ( \A_SPW_TOP|tx_data|mem[40][7]~q  ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .datac(!\u0|write_data_fifo_tx|data_out [7]),
        .datad(!\A_SPW_TOP|tx_data|mem[40][7]~q ),
        .datae(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .dataf(!\A_SPW_TOP|tx_data|Selector365~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector366~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector366~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector366~0 .lut_mask = 64'h00FF00FF33330F0F;
defparam \A_SPW_TOP|tx_data|Selector366~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y8_N17
dffeas \A_SPW_TOP|tx_data|mem[40][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector366~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[40][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[40][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[40][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y10_N15
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector375~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector375~0_combout  = ( \u0|write_data_fifo_tx|data_out [7] & ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (\A_SPW_TOP|tx_data|mem[41][7]~q ) # (\A_SPW_TOP|tx_data|Selector374~0_combout ) ) ) ) # ( !\u0|write_data_fifo_tx|data_out 
// [7] & ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector374~0_combout  & \A_SPW_TOP|tx_data|mem[41][7]~q ) ) ) ) # ( \u0|write_data_fifo_tx|data_out [7] & ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( 
// (!\A_SPW_TOP|tx_data|Selector374~0_combout  & ((\A_SPW_TOP|tx_data|mem[41][7]~q ))) # (\A_SPW_TOP|tx_data|Selector374~0_combout  & (\A_SPW_TOP|tx_data|Mux1~20_combout )) ) ) ) # ( !\u0|write_data_fifo_tx|data_out [7] & ( 
// !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector374~0_combout  & ((\A_SPW_TOP|tx_data|mem[41][7]~q ))) # (\A_SPW_TOP|tx_data|Selector374~0_combout  & (\A_SPW_TOP|tx_data|Mux1~20_combout )) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|Selector374~0_combout ),
        .datac(!\A_SPW_TOP|tx_data|mem[41][7]~q ),
        .datad(gnd),
        .datae(!\u0|write_data_fifo_tx|data_out [7]),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector375~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector375~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector375~0 .lut_mask = 64'h1D1D1D1D0C0C3F3F;
defparam \A_SPW_TOP|tx_data|Selector375~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y10_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|mem[41][7]~feeder (
// Equation(s):
// \A_SPW_TOP|tx_data|mem[41][7]~feeder_combout  = ( \A_SPW_TOP|tx_data|Selector375~0_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector375~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|mem[41][7]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[41][7]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|mem[41][7]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|tx_data|mem[41][7]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X45_Y10_N32
dffeas \A_SPW_TOP|tx_data|mem[41][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|tx_data|mem[41][7]~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[41][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[41][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[41][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X51_Y11_N15
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector393~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector393~0_combout  = ( \A_SPW_TOP|tx_data|mem[43][7]~q  & ( (!\A_SPW_TOP|tx_data|Selector392~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux1~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [7])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[43][7]~q  & ( (\A_SPW_TOP|tx_data|Selector392~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux1~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [7]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector392~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [7]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[43][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector393~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector393~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector393~0 .lut_mask = 64'h04070407F4F7F4F7;
defparam \A_SPW_TOP|tx_data|Selector393~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X51_Y11_N8
dffeas \A_SPW_TOP|tx_data|mem[43][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector393~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[43][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[43][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[43][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X51_Y11_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux1~3 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux1~3_combout  = ( \A_SPW_TOP|tx_data|mem[43][7]~q  & ( \A_SPW_TOP|tx_data|wr_ptr [0] & ( (\A_SPW_TOP|tx_data|wr_ptr [1]) # (\A_SPW_TOP|tx_data|mem[41][7]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[43][7]~q  & ( \A_SPW_TOP|tx_data|wr_ptr 
// [0] & ( (\A_SPW_TOP|tx_data|mem[41][7]~q  & !\A_SPW_TOP|tx_data|wr_ptr [1]) ) ) ) # ( \A_SPW_TOP|tx_data|mem[43][7]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [0] & ( (!\A_SPW_TOP|tx_data|wr_ptr [1] & ((\A_SPW_TOP|tx_data|mem[40][7]~q ))) # 
// (\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|mem[42][7]~q )) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[43][7]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [0] & ( (!\A_SPW_TOP|tx_data|wr_ptr [1] & ((\A_SPW_TOP|tx_data|mem[40][7]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr 
// [1] & (\A_SPW_TOP|tx_data|mem[42][7]~q )) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[42][7]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[40][7]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[41][7]~q ),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datae(!\A_SPW_TOP|tx_data|mem[43][7]~q ),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux1~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux1~3 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux1~3 .lut_mask = 64'h335533550F000FFF;
defparam \A_SPW_TOP|tx_data|Mux1~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X51_Y11_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector78~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector78~0_combout  = ( \A_SPW_TOP|tx_data|mem[8][7]~q  & ( (!\A_SPW_TOP|tx_data|Selector77~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux1~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [7])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[8][7]~q  & ( (\A_SPW_TOP|tx_data|Selector77~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux1~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [7]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\u0|write_data_fifo_tx|data_out [7]),
        .datad(!\A_SPW_TOP|tx_data|Selector77~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[8][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector78~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector78~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector78~0 .lut_mask = 64'h00470047FF47FF47;
defparam \A_SPW_TOP|tx_data|Selector78~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X51_Y11_N53
dffeas \A_SPW_TOP|tx_data|mem[8][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector78~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[8][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[8][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[8][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X51_Y11_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector105~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector105~0_combout  = ( \A_SPW_TOP|tx_data|mem[11][7]~q  & ( (!\A_SPW_TOP|tx_data|Selector104~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux1~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [7])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[11][7]~q  & ( (\A_SPW_TOP|tx_data|Selector104~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux1~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [7]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\u0|write_data_fifo_tx|data_out [7]),
        .datad(!\A_SPW_TOP|tx_data|Selector104~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[11][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector105~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector105~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector105~0 .lut_mask = 64'h00470047FF47FF47;
defparam \A_SPW_TOP|tx_data|Selector105~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X51_Y11_N11
dffeas \A_SPW_TOP|tx_data|mem[11][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector105~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[11][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[11][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[11][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X51_Y11_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector87~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector87~0_combout  = ( \A_SPW_TOP|tx_data|Selector86~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux1~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\u0|write_data_fifo_tx|data_out [7])) ) ) # ( !\A_SPW_TOP|tx_data|Selector86~0_combout  & ( \A_SPW_TOP|tx_data|mem[9][7]~q  ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [7]),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .datad(!\A_SPW_TOP|tx_data|mem[9][7]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector86~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector87~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector87~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector87~0 .lut_mask = 64'h00FF00FF1D1D1D1D;
defparam \A_SPW_TOP|tx_data|Selector87~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X51_Y11_N23
dffeas \A_SPW_TOP|tx_data|mem[9][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector87~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[9][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[9][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[9][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X51_Y11_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector96~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector96~0_combout  = ( \A_SPW_TOP|tx_data|mem[10][7]~q  & ( (!\A_SPW_TOP|tx_data|Selector95~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux1~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [7])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[10][7]~q  & ( (\A_SPW_TOP|tx_data|Selector95~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux1~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [7]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector95~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [7]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[10][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector96~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector96~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector96~0 .lut_mask = 64'h04070407F4F7F4F7;
defparam \A_SPW_TOP|tx_data|Selector96~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X51_Y11_N35
dffeas \A_SPW_TOP|tx_data|mem[10][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector96~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[10][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[10][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[10][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X51_Y11_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux1~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux1~1_combout  = ( \A_SPW_TOP|tx_data|mem[9][7]~q  & ( \A_SPW_TOP|tx_data|mem[10][7]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [1] & (((\A_SPW_TOP|tx_data|wr_ptr [0])) # (\A_SPW_TOP|tx_data|mem[8][7]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [1] & 
// (((!\A_SPW_TOP|tx_data|wr_ptr [0]) # (\A_SPW_TOP|tx_data|mem[11][7]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[9][7]~q  & ( \A_SPW_TOP|tx_data|mem[10][7]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|mem[8][7]~q  & (!\A_SPW_TOP|tx_data|wr_ptr 
// [0]))) # (\A_SPW_TOP|tx_data|wr_ptr [1] & (((!\A_SPW_TOP|tx_data|wr_ptr [0]) # (\A_SPW_TOP|tx_data|mem[11][7]~q )))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[9][7]~q  & ( !\A_SPW_TOP|tx_data|mem[10][7]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [1] & 
// (((\A_SPW_TOP|tx_data|wr_ptr [0])) # (\A_SPW_TOP|tx_data|mem[8][7]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [1] & (((\A_SPW_TOP|tx_data|wr_ptr [0] & \A_SPW_TOP|tx_data|mem[11][7]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[9][7]~q  & ( 
// !\A_SPW_TOP|tx_data|mem[10][7]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|mem[8][7]~q  & (!\A_SPW_TOP|tx_data|wr_ptr [0]))) # (\A_SPW_TOP|tx_data|wr_ptr [1] & (((\A_SPW_TOP|tx_data|wr_ptr [0] & \A_SPW_TOP|tx_data|mem[11][7]~q )))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[8][7]~q ),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datad(!\A_SPW_TOP|tx_data|mem[11][7]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[9][7]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[10][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux1~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux1~1 .lut_mask = 64'h40434C4F70737C7F;
defparam \A_SPW_TOP|tx_data|Mux1~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y11_N39
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector294~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector294~0_combout  = ( \A_SPW_TOP|tx_data|Selector293~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux1~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\u0|write_data_fifo_tx|data_out [7])) ) ) # ( !\A_SPW_TOP|tx_data|Selector293~0_combout  & ( \A_SPW_TOP|tx_data|mem[32][7]~q  ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [7]),
        .datab(!\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[32][7]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector293~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector294~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector294~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector294~0 .lut_mask = 64'h00FF00FF35353535;
defparam \A_SPW_TOP|tx_data|Selector294~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y11_N29
dffeas \A_SPW_TOP|tx_data|mem[32][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector294~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[32][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[32][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[32][7] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y11_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector303~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector303~0_combout  = ( \u0|write_data_fifo_tx|data_out [7] & ( (!\A_SPW_TOP|tx_data|Selector302~0_combout  & (((\A_SPW_TOP|tx_data|mem[33][7]~q )))) # (\A_SPW_TOP|tx_data|Selector302~0_combout  & 
// (((\A_SPW_TOP|tx_data|state_data_write.00~q )) # (\A_SPW_TOP|tx_data|Mux1~20_combout ))) ) ) # ( !\u0|write_data_fifo_tx|data_out [7] & ( (!\A_SPW_TOP|tx_data|Selector302~0_combout  & (((\A_SPW_TOP|tx_data|mem[33][7]~q )))) # 
// (\A_SPW_TOP|tx_data|Selector302~0_combout  & (\A_SPW_TOP|tx_data|Mux1~20_combout  & (!\A_SPW_TOP|tx_data|state_data_write.00~q ))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector302~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|mem[33][7]~q ),
        .datae(gnd),
        .dataf(!\u0|write_data_fifo_tx|data_out [7]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector303~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector303~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector303~0 .lut_mask = 64'h04F404F407F707F7;
defparam \A_SPW_TOP|tx_data|Selector303~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y11_N23
dffeas \A_SPW_TOP|tx_data|mem[33][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector303~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[33][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[33][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[33][7] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y11_N9
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector321~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector321~0_combout  = ( \A_SPW_TOP|tx_data|mem[35][7]~q  & ( (!\A_SPW_TOP|tx_data|Selector320~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux1~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [7])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[35][7]~q  & ( (\A_SPW_TOP|tx_data|Selector320~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux1~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [7]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [7]),
        .datac(!\A_SPW_TOP|tx_data|Selector320~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[35][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector321~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector321~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector321~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|tx_data|Selector321~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y11_N32
dffeas \A_SPW_TOP|tx_data|mem[35][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector321~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[35][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[35][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[35][7] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y11_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector312~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector312~0_combout  = ( \A_SPW_TOP|tx_data|mem[34][7]~q  & ( (!\A_SPW_TOP|tx_data|Selector311~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux1~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [7])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[34][7]~q  & ( (\A_SPW_TOP|tx_data|Selector311~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux1~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [7]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [7]),
        .datac(!\A_SPW_TOP|tx_data|Selector311~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[34][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector312~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector312~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector312~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|tx_data|Selector312~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y11_N50
dffeas \A_SPW_TOP|tx_data|mem[34][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector312~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[34][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[34][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[34][7] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y11_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux1~2 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux1~2_combout  = ( \A_SPW_TOP|tx_data|mem[35][7]~q  & ( \A_SPW_TOP|tx_data|mem[34][7]~q  & ( ((!\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|mem[32][7]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|mem[33][7]~q 
// )))) # (\A_SPW_TOP|tx_data|wr_ptr [1]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[35][7]~q  & ( \A_SPW_TOP|tx_data|mem[34][7]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [1] & ((!\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|mem[32][7]~q )) # 
// (\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|mem[33][7]~q ))))) # (\A_SPW_TOP|tx_data|wr_ptr [1] & (((!\A_SPW_TOP|tx_data|wr_ptr [0])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[35][7]~q  & ( !\A_SPW_TOP|tx_data|mem[34][7]~q  & ( 
// (!\A_SPW_TOP|tx_data|wr_ptr [1] & ((!\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|mem[32][7]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|mem[33][7]~q ))))) # (\A_SPW_TOP|tx_data|wr_ptr [1] & (((\A_SPW_TOP|tx_data|wr_ptr [0])))) ) ) 
// ) # ( !\A_SPW_TOP|tx_data|mem[35][7]~q  & ( !\A_SPW_TOP|tx_data|mem[34][7]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [1] & ((!\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|mem[32][7]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|mem[33][7]~q 
// ))))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datab(!\A_SPW_TOP|tx_data|mem[32][7]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[33][7]~q ),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datae(!\A_SPW_TOP|tx_data|mem[35][7]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[34][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux1~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux1~2 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux1~2 .lut_mask = 64'h220A225F770A775F;
defparam \A_SPW_TOP|tx_data|Mux1~2 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y11_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux1~4 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux1~4_combout  = ( \A_SPW_TOP|tx_data|Mux1~1_combout  & ( \A_SPW_TOP|tx_data|Mux1~2_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [3] & (((\A_SPW_TOP|tx_data|wr_ptr [5])) # (\A_SPW_TOP|tx_data|Mux1~0_combout ))) # (\A_SPW_TOP|tx_data|wr_ptr 
// [3] & (((!\A_SPW_TOP|tx_data|wr_ptr [5]) # (\A_SPW_TOP|tx_data|Mux1~3_combout )))) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux1~1_combout  & ( \A_SPW_TOP|tx_data|Mux1~2_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [3] & (((\A_SPW_TOP|tx_data|wr_ptr [5])) # 
// (\A_SPW_TOP|tx_data|Mux1~0_combout ))) # (\A_SPW_TOP|tx_data|wr_ptr [3] & (((\A_SPW_TOP|tx_data|wr_ptr [5] & \A_SPW_TOP|tx_data|Mux1~3_combout )))) ) ) ) # ( \A_SPW_TOP|tx_data|Mux1~1_combout  & ( !\A_SPW_TOP|tx_data|Mux1~2_combout  & ( 
// (!\A_SPW_TOP|tx_data|wr_ptr [3] & (\A_SPW_TOP|tx_data|Mux1~0_combout  & (!\A_SPW_TOP|tx_data|wr_ptr [5]))) # (\A_SPW_TOP|tx_data|wr_ptr [3] & (((!\A_SPW_TOP|tx_data|wr_ptr [5]) # (\A_SPW_TOP|tx_data|Mux1~3_combout )))) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|Mux1~1_combout  & ( !\A_SPW_TOP|tx_data|Mux1~2_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [3] & (\A_SPW_TOP|tx_data|Mux1~0_combout  & (!\A_SPW_TOP|tx_data|wr_ptr [5]))) # (\A_SPW_TOP|tx_data|wr_ptr [3] & (((\A_SPW_TOP|tx_data|wr_ptr [5] 
// & \A_SPW_TOP|tx_data|Mux1~3_combout )))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux1~0_combout ),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datad(!\A_SPW_TOP|tx_data|Mux1~3_combout ),
        .datae(!\A_SPW_TOP|tx_data|Mux1~1_combout ),
        .dataf(!\A_SPW_TOP|tx_data|Mux1~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux1~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux1~4 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux1~4 .lut_mask = 64'h404370734C4F7C7F;
defparam \A_SPW_TOP|tx_data|Mux1~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y8_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux1~20 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux1~20_combout  = ( \A_SPW_TOP|tx_data|Mux1~14_combout  & ( \A_SPW_TOP|tx_data|Mux1~4_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [4]) # ((!\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|Mux1~9_combout )) # (\A_SPW_TOP|tx_data|wr_ptr 
// [2] & ((\A_SPW_TOP|tx_data|Mux1~19_combout )))) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux1~14_combout  & ( \A_SPW_TOP|tx_data|Mux1~4_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & (((!\A_SPW_TOP|tx_data|wr_ptr [4])) # (\A_SPW_TOP|tx_data|Mux1~9_combout ))) # 
// (\A_SPW_TOP|tx_data|wr_ptr [2] & (((\A_SPW_TOP|tx_data|Mux1~19_combout  & \A_SPW_TOP|tx_data|wr_ptr [4])))) ) ) ) # ( \A_SPW_TOP|tx_data|Mux1~14_combout  & ( !\A_SPW_TOP|tx_data|Mux1~4_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & 
// (\A_SPW_TOP|tx_data|Mux1~9_combout  & ((\A_SPW_TOP|tx_data|wr_ptr [4])))) # (\A_SPW_TOP|tx_data|wr_ptr [2] & (((!\A_SPW_TOP|tx_data|wr_ptr [4]) # (\A_SPW_TOP|tx_data|Mux1~19_combout )))) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux1~14_combout  & ( 
// !\A_SPW_TOP|tx_data|Mux1~4_combout  & ( (\A_SPW_TOP|tx_data|wr_ptr [4] & ((!\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|Mux1~9_combout )) # (\A_SPW_TOP|tx_data|wr_ptr [2] & ((\A_SPW_TOP|tx_data|Mux1~19_combout ))))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux1~9_combout ),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datac(!\A_SPW_TOP|tx_data|Mux1~19_combout ),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datae(!\A_SPW_TOP|tx_data|Mux1~14_combout ),
        .dataf(!\A_SPW_TOP|tx_data|Mux1~4_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux1~20 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux1~20 .lut_mask = 64'h00473347CC47FF47;
defparam \A_SPW_TOP|tx_data|Mux1~20 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y11_N51
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector6~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector6~0_combout  = ( \A_SPW_TOP|tx_data|Selector5~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux1~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out 
// [7])) ) ) # ( !\A_SPW_TOP|tx_data|Selector5~0_combout  & ( \A_SPW_TOP|tx_data|mem[0][7]~q  ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [7]),
        .datab(!\A_SPW_TOP|tx_data|Mux1~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[0][7]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector5~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector6~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector6~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector6~0 .lut_mask = 64'h00FF00FF35353535;
defparam \A_SPW_TOP|tx_data|Selector6~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y11_N56
dffeas \A_SPW_TOP|tx_data|mem[0][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector6~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[0][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[0][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[0][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y11_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux10~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux10~0_combout  = ( \A_SPW_TOP|tx_data|mem[17][7]~q  & ( \A_SPW_TOP|tx_data|mem[16][7]~q  & ( ((!\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|mem[0][7]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [0] & ((\A_SPW_TOP|tx_data|mem[1][7]~q 
// )))) # (\A_SPW_TOP|tx_data|rd_ptr [4]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[17][7]~q  & ( \A_SPW_TOP|tx_data|mem[16][7]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [0] & (((\A_SPW_TOP|tx_data|rd_ptr [4])) # (\A_SPW_TOP|tx_data|mem[0][7]~q ))) # 
// (\A_SPW_TOP|tx_data|rd_ptr [0] & (((\A_SPW_TOP|tx_data|mem[1][7]~q  & !\A_SPW_TOP|tx_data|rd_ptr [4])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[17][7]~q  & ( !\A_SPW_TOP|tx_data|mem[16][7]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|mem[0][7]~q 
//  & ((!\A_SPW_TOP|tx_data|rd_ptr [4])))) # (\A_SPW_TOP|tx_data|rd_ptr [0] & (((\A_SPW_TOP|tx_data|rd_ptr [4]) # (\A_SPW_TOP|tx_data|mem[1][7]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[17][7]~q  & ( !\A_SPW_TOP|tx_data|mem[16][7]~q  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [4] & ((!\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|mem[0][7]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [0] & ((\A_SPW_TOP|tx_data|mem[1][7]~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[0][7]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[1][7]~q ),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .datae(!\A_SPW_TOP|tx_data|mem[17][7]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[16][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux10~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux10~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux10~0 .lut_mask = 64'h5300530F53F053FF;
defparam \A_SPW_TOP|tx_data|Mux10~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y8_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux10~3 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux10~3_combout  = ( \A_SPW_TOP|tx_data|mem[57][7]~q  & ( \A_SPW_TOP|tx_data|mem[40][7]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & (((!\A_SPW_TOP|tx_data|rd_ptr [0])) # (\A_SPW_TOP|tx_data|mem[41][7]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [4] 
// & (((\A_SPW_TOP|tx_data|rd_ptr [0]) # (\A_SPW_TOP|tx_data|mem[56][7]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[57][7]~q  & ( \A_SPW_TOP|tx_data|mem[40][7]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & (((!\A_SPW_TOP|tx_data|rd_ptr [0])) # 
// (\A_SPW_TOP|tx_data|mem[41][7]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [4] & (((\A_SPW_TOP|tx_data|mem[56][7]~q  & !\A_SPW_TOP|tx_data|rd_ptr [0])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[57][7]~q  & ( !\A_SPW_TOP|tx_data|mem[40][7]~q  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [4] & (\A_SPW_TOP|tx_data|mem[41][7]~q  & ((\A_SPW_TOP|tx_data|rd_ptr [0])))) # (\A_SPW_TOP|tx_data|rd_ptr [4] & (((\A_SPW_TOP|tx_data|rd_ptr [0]) # (\A_SPW_TOP|tx_data|mem[56][7]~q )))) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|mem[57][7]~q  & ( !\A_SPW_TOP|tx_data|mem[40][7]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & (\A_SPW_TOP|tx_data|mem[41][7]~q  & ((\A_SPW_TOP|tx_data|rd_ptr [0])))) # (\A_SPW_TOP|tx_data|rd_ptr [4] & (((\A_SPW_TOP|tx_data|mem[56][7]~q  & 
// !\A_SPW_TOP|tx_data|rd_ptr [0])))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[41][7]~q ),
        .datab(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .datac(!\A_SPW_TOP|tx_data|mem[56][7]~q ),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .datae(!\A_SPW_TOP|tx_data|mem[57][7]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[40][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux10~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux10~3 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux10~3 .lut_mask = 64'h03440377CF44CF77;
defparam \A_SPW_TOP|tx_data|Mux10~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X51_Y11_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux10~2 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux10~2_combout  = ( \A_SPW_TOP|tx_data|mem[9][7]~q  & ( \A_SPW_TOP|tx_data|mem[8][7]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4]) # ((!\A_SPW_TOP|tx_data|rd_ptr [0] & ((\A_SPW_TOP|tx_data|mem[24][7]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [0] & 
// (\A_SPW_TOP|tx_data|mem[25][7]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[9][7]~q  & ( \A_SPW_TOP|tx_data|mem[8][7]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & (((!\A_SPW_TOP|tx_data|rd_ptr [0])))) # (\A_SPW_TOP|tx_data|rd_ptr [4] & ((!\A_SPW_TOP|tx_data|rd_ptr 
// [0] & ((\A_SPW_TOP|tx_data|mem[24][7]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|mem[25][7]~q )))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[9][7]~q  & ( !\A_SPW_TOP|tx_data|mem[8][7]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & 
// (((\A_SPW_TOP|tx_data|rd_ptr [0])))) # (\A_SPW_TOP|tx_data|rd_ptr [4] & ((!\A_SPW_TOP|tx_data|rd_ptr [0] & ((\A_SPW_TOP|tx_data|mem[24][7]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|mem[25][7]~q )))) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|mem[9][7]~q  & ( !\A_SPW_TOP|tx_data|mem[8][7]~q  & ( (\A_SPW_TOP|tx_data|rd_ptr [4] & ((!\A_SPW_TOP|tx_data|rd_ptr [0] & ((\A_SPW_TOP|tx_data|mem[24][7]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|mem[25][7]~q )))) ) 
// ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[25][7]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[24][7]~q ),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .datae(!\A_SPW_TOP|tx_data|mem[9][7]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[8][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux10~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux10~2 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux10~2 .lut_mask = 64'h030503F5F305F3F5;
defparam \A_SPW_TOP|tx_data|Mux10~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y11_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux10~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux10~1_combout  = ( \A_SPW_TOP|tx_data|mem[33][7]~q  & ( \A_SPW_TOP|tx_data|mem[48][7]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & (((\A_SPW_TOP|tx_data|rd_ptr [0])) # (\A_SPW_TOP|tx_data|mem[32][7]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [4] 
// & (((!\A_SPW_TOP|tx_data|rd_ptr [0]) # (\A_SPW_TOP|tx_data|mem[49][7]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[33][7]~q  & ( \A_SPW_TOP|tx_data|mem[48][7]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & (\A_SPW_TOP|tx_data|mem[32][7]~q  & 
// (!\A_SPW_TOP|tx_data|rd_ptr [0]))) # (\A_SPW_TOP|tx_data|rd_ptr [4] & (((!\A_SPW_TOP|tx_data|rd_ptr [0]) # (\A_SPW_TOP|tx_data|mem[49][7]~q )))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[33][7]~q  & ( !\A_SPW_TOP|tx_data|mem[48][7]~q  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [4] & (((\A_SPW_TOP|tx_data|rd_ptr [0])) # (\A_SPW_TOP|tx_data|mem[32][7]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [4] & (((\A_SPW_TOP|tx_data|rd_ptr [0] & \A_SPW_TOP|tx_data|mem[49][7]~q )))) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|mem[33][7]~q  & ( !\A_SPW_TOP|tx_data|mem[48][7]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & (\A_SPW_TOP|tx_data|mem[32][7]~q  & (!\A_SPW_TOP|tx_data|rd_ptr [0]))) # (\A_SPW_TOP|tx_data|rd_ptr [4] & (((\A_SPW_TOP|tx_data|rd_ptr [0] & 
// \A_SPW_TOP|tx_data|mem[49][7]~q )))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[32][7]~q ),
        .datab(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .datad(!\A_SPW_TOP|tx_data|mem[49][7]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[33][7]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[48][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux10~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux10~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux10~1 .lut_mask = 64'h40434C4F70737C7F;
defparam \A_SPW_TOP|tx_data|Mux10~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y11_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux10~4 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux10~4_combout  = ( \A_SPW_TOP|tx_data|rd_ptr [5] & ( \A_SPW_TOP|tx_data|Mux10~1_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [3]) # (\A_SPW_TOP|tx_data|Mux10~3_combout ) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [5] & ( 
// \A_SPW_TOP|tx_data|Mux10~1_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [3] & (\A_SPW_TOP|tx_data|Mux10~0_combout )) # (\A_SPW_TOP|tx_data|rd_ptr [3] & ((\A_SPW_TOP|tx_data|Mux10~2_combout ))) ) ) ) # ( \A_SPW_TOP|tx_data|rd_ptr [5] & ( 
// !\A_SPW_TOP|tx_data|Mux10~1_combout  & ( (\A_SPW_TOP|tx_data|Mux10~3_combout  & \A_SPW_TOP|tx_data|rd_ptr [3]) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [5] & ( !\A_SPW_TOP|tx_data|Mux10~1_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [3] & 
// (\A_SPW_TOP|tx_data|Mux10~0_combout )) # (\A_SPW_TOP|tx_data|rd_ptr [3] & ((\A_SPW_TOP|tx_data|Mux10~2_combout ))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux10~0_combout ),
        .datab(!\A_SPW_TOP|tx_data|Mux10~3_combout ),
        .datac(!\A_SPW_TOP|tx_data|Mux10~2_combout ),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [3]),
        .datae(!\A_SPW_TOP|tx_data|rd_ptr [5]),
        .dataf(!\A_SPW_TOP|tx_data|Mux10~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux10~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux10~4 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux10~4 .lut_mask = 64'h550F0033550FFF33;
defparam \A_SPW_TOP|tx_data|Mux10~4 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y8_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux10~18 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux10~18_combout  = ( \A_SPW_TOP|tx_data|mem[47][7]~q  & ( \A_SPW_TOP|tx_data|mem[62][7]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [0] & (((\A_SPW_TOP|tx_data|rd_ptr [4])) # (\A_SPW_TOP|tx_data|mem[46][7]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [0] 
// & (((!\A_SPW_TOP|tx_data|rd_ptr [4]) # (\A_SPW_TOP|tx_data|mem[63][7]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[47][7]~q  & ( \A_SPW_TOP|tx_data|mem[62][7]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [0] & (((\A_SPW_TOP|tx_data|rd_ptr [4])) # 
// (\A_SPW_TOP|tx_data|mem[46][7]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [0] & (((\A_SPW_TOP|tx_data|mem[63][7]~q  & \A_SPW_TOP|tx_data|rd_ptr [4])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[47][7]~q  & ( !\A_SPW_TOP|tx_data|mem[62][7]~q  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|mem[46][7]~q  & ((!\A_SPW_TOP|tx_data|rd_ptr [4])))) # (\A_SPW_TOP|tx_data|rd_ptr [0] & (((!\A_SPW_TOP|tx_data|rd_ptr [4]) # (\A_SPW_TOP|tx_data|mem[63][7]~q )))) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|mem[47][7]~q  & ( !\A_SPW_TOP|tx_data|mem[62][7]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|mem[46][7]~q  & ((!\A_SPW_TOP|tx_data|rd_ptr [4])))) # (\A_SPW_TOP|tx_data|rd_ptr [0] & (((\A_SPW_TOP|tx_data|mem[63][7]~q  & 
// \A_SPW_TOP|tx_data|rd_ptr [4])))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[46][7]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[63][7]~q ),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .datae(!\A_SPW_TOP|tx_data|mem[47][7]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[62][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux10~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux10~18 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux10~18 .lut_mask = 64'h50035F0350F35FF3;
defparam \A_SPW_TOP|tx_data|Mux10~18 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y8_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux10~17 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux10~17_combout  = ( \A_SPW_TOP|tx_data|mem[31][7]~q  & ( \A_SPW_TOP|tx_data|mem[15][7]~q  & ( ((!\A_SPW_TOP|tx_data|rd_ptr [4] & (\A_SPW_TOP|tx_data|mem[14][7]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [4] & ((\A_SPW_TOP|tx_data|mem[30][7]~q 
// )))) # (\A_SPW_TOP|tx_data|rd_ptr [0]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[31][7]~q  & ( \A_SPW_TOP|tx_data|mem[15][7]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [0] & ((!\A_SPW_TOP|tx_data|rd_ptr [4] & (\A_SPW_TOP|tx_data|mem[14][7]~q )) # 
// (\A_SPW_TOP|tx_data|rd_ptr [4] & ((\A_SPW_TOP|tx_data|mem[30][7]~q ))))) # (\A_SPW_TOP|tx_data|rd_ptr [0] & (((!\A_SPW_TOP|tx_data|rd_ptr [4])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[31][7]~q  & ( !\A_SPW_TOP|tx_data|mem[15][7]~q  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [0] & ((!\A_SPW_TOP|tx_data|rd_ptr [4] & (\A_SPW_TOP|tx_data|mem[14][7]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [4] & ((\A_SPW_TOP|tx_data|mem[30][7]~q ))))) # (\A_SPW_TOP|tx_data|rd_ptr [0] & (((\A_SPW_TOP|tx_data|rd_ptr [4])))) ) ) 
// ) # ( !\A_SPW_TOP|tx_data|mem[31][7]~q  & ( !\A_SPW_TOP|tx_data|mem[15][7]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [0] & ((!\A_SPW_TOP|tx_data|rd_ptr [4] & (\A_SPW_TOP|tx_data|mem[14][7]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [4] & ((\A_SPW_TOP|tx_data|mem[30][7]~q 
// ))))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .datab(!\A_SPW_TOP|tx_data|mem[14][7]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[30][7]~q ),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .datae(!\A_SPW_TOP|tx_data|mem[31][7]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[15][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux10~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux10~17 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux10~17 .lut_mask = 64'h220A225F770A775F;
defparam \A_SPW_TOP|tx_data|Mux10~17 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y8_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux10~15 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux10~15_combout  = ( \A_SPW_TOP|tx_data|mem[6][7]~q  & ( \A_SPW_TOP|tx_data|mem[22][7]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [0]) # ((!\A_SPW_TOP|tx_data|rd_ptr [4] & (\A_SPW_TOP|tx_data|mem[7][7]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [4] & 
// ((\A_SPW_TOP|tx_data|mem[23][7]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[6][7]~q  & ( \A_SPW_TOP|tx_data|mem[22][7]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & (\A_SPW_TOP|tx_data|mem[7][7]~q  & ((\A_SPW_TOP|tx_data|rd_ptr [0])))) # 
// (\A_SPW_TOP|tx_data|rd_ptr [4] & (((!\A_SPW_TOP|tx_data|rd_ptr [0]) # (\A_SPW_TOP|tx_data|mem[23][7]~q )))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[6][7]~q  & ( !\A_SPW_TOP|tx_data|mem[22][7]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & (((!\A_SPW_TOP|tx_data|rd_ptr 
// [0])) # (\A_SPW_TOP|tx_data|mem[7][7]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [4] & (((\A_SPW_TOP|tx_data|mem[23][7]~q  & \A_SPW_TOP|tx_data|rd_ptr [0])))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[6][7]~q  & ( !\A_SPW_TOP|tx_data|mem[22][7]~q  & ( 
// (\A_SPW_TOP|tx_data|rd_ptr [0] & ((!\A_SPW_TOP|tx_data|rd_ptr [4] & (\A_SPW_TOP|tx_data|mem[7][7]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [4] & ((\A_SPW_TOP|tx_data|mem[23][7]~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[7][7]~q ),
        .datab(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .datac(!\A_SPW_TOP|tx_data|mem[23][7]~q ),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .datae(!\A_SPW_TOP|tx_data|mem[6][7]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[22][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux10~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux10~15 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux10~15 .lut_mask = 64'h0047CC473347FF47;
defparam \A_SPW_TOP|tx_data|Mux10~15 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y8_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux10~16 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux10~16_combout  = ( \A_SPW_TOP|tx_data|mem[38][7]~q  & ( \A_SPW_TOP|tx_data|mem[55][7]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & ((!\A_SPW_TOP|tx_data|rd_ptr [0]) # ((\A_SPW_TOP|tx_data|mem[39][7]~q )))) # (\A_SPW_TOP|tx_data|rd_ptr 
// [4] & (((\A_SPW_TOP|tx_data|mem[54][7]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [0]))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[38][7]~q  & ( \A_SPW_TOP|tx_data|mem[55][7]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & (\A_SPW_TOP|tx_data|rd_ptr [0] & 
// (\A_SPW_TOP|tx_data|mem[39][7]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [4] & (((\A_SPW_TOP|tx_data|mem[54][7]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [0]))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[38][7]~q  & ( !\A_SPW_TOP|tx_data|mem[55][7]~q  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [4] & ((!\A_SPW_TOP|tx_data|rd_ptr [0]) # ((\A_SPW_TOP|tx_data|mem[39][7]~q )))) # (\A_SPW_TOP|tx_data|rd_ptr [4] & (!\A_SPW_TOP|tx_data|rd_ptr [0] & ((\A_SPW_TOP|tx_data|mem[54][7]~q )))) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|mem[38][7]~q  & ( !\A_SPW_TOP|tx_data|mem[55][7]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & (\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|mem[39][7]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [4] & (!\A_SPW_TOP|tx_data|rd_ptr [0] & 
// ((\A_SPW_TOP|tx_data|mem[54][7]~q )))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .datab(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .datac(!\A_SPW_TOP|tx_data|mem[39][7]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[54][7]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[38][7]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[55][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux10~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux10~16 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux10~16 .lut_mask = 64'h02468ACE13579BDF;
defparam \A_SPW_TOP|tx_data|Mux10~16 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y8_N9
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux10~19 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux10~19_combout  = ( \A_SPW_TOP|tx_data|rd_ptr [3] & ( \A_SPW_TOP|tx_data|Mux10~16_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & ((\A_SPW_TOP|tx_data|Mux10~17_combout ))) # (\A_SPW_TOP|tx_data|rd_ptr [5] & 
// (\A_SPW_TOP|tx_data|Mux10~18_combout )) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [3] & ( \A_SPW_TOP|tx_data|Mux10~16_combout  & ( (\A_SPW_TOP|tx_data|Mux10~15_combout ) # (\A_SPW_TOP|tx_data|rd_ptr [5]) ) ) ) # ( \A_SPW_TOP|tx_data|rd_ptr [3] & ( 
// !\A_SPW_TOP|tx_data|Mux10~16_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & ((\A_SPW_TOP|tx_data|Mux10~17_combout ))) # (\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|Mux10~18_combout )) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [3] & ( 
// !\A_SPW_TOP|tx_data|Mux10~16_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & \A_SPW_TOP|tx_data|Mux10~15_combout ) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [5]),
        .datab(!\A_SPW_TOP|tx_data|Mux10~18_combout ),
        .datac(!\A_SPW_TOP|tx_data|Mux10~17_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux10~15_combout ),
        .datae(!\A_SPW_TOP|tx_data|rd_ptr [3]),
        .dataf(!\A_SPW_TOP|tx_data|Mux10~16_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux10~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux10~19 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux10~19 .lut_mask = 64'h00AA1B1B55FF1B1B;
defparam \A_SPW_TOP|tx_data|Mux10~19 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y11_N51
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux10~6 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux10~6_combout  = ( \A_SPW_TOP|tx_data|rd_ptr [4] & ( \A_SPW_TOP|tx_data|rd_ptr [0] & ( \A_SPW_TOP|tx_data|mem[51][7]~q  ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [4] & ( \A_SPW_TOP|tx_data|rd_ptr [0] & ( \A_SPW_TOP|tx_data|mem[35][7]~q  ) 
// ) ) # ( \A_SPW_TOP|tx_data|rd_ptr [4] & ( !\A_SPW_TOP|tx_data|rd_ptr [0] & ( \A_SPW_TOP|tx_data|mem[50][7]~q  ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [4] & ( !\A_SPW_TOP|tx_data|rd_ptr [0] & ( \A_SPW_TOP|tx_data|mem[34][7]~q  ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[34][7]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[35][7]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[51][7]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[50][7]~q ),
        .datae(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .dataf(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux10~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux10~6 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux10~6 .lut_mask = 64'h555500FF33330F0F;
defparam \A_SPW_TOP|tx_data|Mux10~6 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X51_Y11_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux10~8 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux10~8_combout  = ( \A_SPW_TOP|tx_data|mem[58][7]~q  & ( \A_SPW_TOP|tx_data|mem[59][7]~q  & ( ((!\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|mem[42][7]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [0] & ((\A_SPW_TOP|tx_data|mem[43][7]~q 
// )))) # (\A_SPW_TOP|tx_data|rd_ptr [4]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[58][7]~q  & ( \A_SPW_TOP|tx_data|mem[59][7]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & ((!\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|mem[42][7]~q )) # 
// (\A_SPW_TOP|tx_data|rd_ptr [0] & ((\A_SPW_TOP|tx_data|mem[43][7]~q ))))) # (\A_SPW_TOP|tx_data|rd_ptr [4] & (\A_SPW_TOP|tx_data|rd_ptr [0])) ) ) ) # ( \A_SPW_TOP|tx_data|mem[58][7]~q  & ( !\A_SPW_TOP|tx_data|mem[59][7]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr 
// [4] & ((!\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|mem[42][7]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [0] & ((\A_SPW_TOP|tx_data|mem[43][7]~q ))))) # (\A_SPW_TOP|tx_data|rd_ptr [4] & (!\A_SPW_TOP|tx_data|rd_ptr [0])) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|mem[58][7]~q  & ( !\A_SPW_TOP|tx_data|mem[59][7]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & ((!\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|mem[42][7]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [0] & ((\A_SPW_TOP|tx_data|mem[43][7]~q ))))) 
// ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .datab(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .datac(!\A_SPW_TOP|tx_data|mem[42][7]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[43][7]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[58][7]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[59][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux10~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux10~8 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux10~8 .lut_mask = 64'h082A4C6E193B5D7F;
defparam \A_SPW_TOP|tx_data|Mux10~8 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y11_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux10~5 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux10~5_combout  = ( \A_SPW_TOP|tx_data|mem[2][7]~q  & ( \A_SPW_TOP|tx_data|mem[19][7]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [0] & (((!\A_SPW_TOP|tx_data|rd_ptr [4])) # (\A_SPW_TOP|tx_data|mem[18][7]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [0] 
// & (((\A_SPW_TOP|tx_data|rd_ptr [4]) # (\A_SPW_TOP|tx_data|mem[3][7]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[2][7]~q  & ( \A_SPW_TOP|tx_data|mem[19][7]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|mem[18][7]~q  & 
// ((\A_SPW_TOP|tx_data|rd_ptr [4])))) # (\A_SPW_TOP|tx_data|rd_ptr [0] & (((\A_SPW_TOP|tx_data|rd_ptr [4]) # (\A_SPW_TOP|tx_data|mem[3][7]~q )))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[2][7]~q  & ( !\A_SPW_TOP|tx_data|mem[19][7]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr 
// [0] & (((!\A_SPW_TOP|tx_data|rd_ptr [4])) # (\A_SPW_TOP|tx_data|mem[18][7]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [0] & (((\A_SPW_TOP|tx_data|mem[3][7]~q  & !\A_SPW_TOP|tx_data|rd_ptr [4])))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[2][7]~q  & ( 
// !\A_SPW_TOP|tx_data|mem[19][7]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|mem[18][7]~q  & ((\A_SPW_TOP|tx_data|rd_ptr [4])))) # (\A_SPW_TOP|tx_data|rd_ptr [0] & (((\A_SPW_TOP|tx_data|mem[3][7]~q  & !\A_SPW_TOP|tx_data|rd_ptr [4])))) ) ) 
// )

        .dataa(!\A_SPW_TOP|tx_data|mem[18][7]~q ),
        .datab(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .datac(!\A_SPW_TOP|tx_data|mem[3][7]~q ),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .datae(!\A_SPW_TOP|tx_data|mem[2][7]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[19][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux10~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux10~5 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux10~5 .lut_mask = 64'h0344CF440377CF77;
defparam \A_SPW_TOP|tx_data|Mux10~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X51_Y11_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux10~7 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux10~7_combout  = ( \A_SPW_TOP|tx_data|rd_ptr [4] & ( \A_SPW_TOP|tx_data|rd_ptr [0] & ( \A_SPW_TOP|tx_data|mem[27][7]~q  ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [4] & ( \A_SPW_TOP|tx_data|rd_ptr [0] & ( \A_SPW_TOP|tx_data|mem[11][7]~q  ) 
// ) ) # ( \A_SPW_TOP|tx_data|rd_ptr [4] & ( !\A_SPW_TOP|tx_data|rd_ptr [0] & ( \A_SPW_TOP|tx_data|mem[26][7]~q  ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [4] & ( !\A_SPW_TOP|tx_data|rd_ptr [0] & ( \A_SPW_TOP|tx_data|mem[10][7]~q  ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[27][7]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[11][7]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[10][7]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[26][7]~q ),
        .datae(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .dataf(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux10~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux10~7 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux10~7 .lut_mask = 64'h0F0F00FF33335555;
defparam \A_SPW_TOP|tx_data|Mux10~7 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y11_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux10~9 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux10~9_combout  = ( \A_SPW_TOP|tx_data|Mux10~5_combout  & ( \A_SPW_TOP|tx_data|Mux10~7_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5]) # ((!\A_SPW_TOP|tx_data|rd_ptr [3] & (\A_SPW_TOP|tx_data|Mux10~6_combout )) # 
// (\A_SPW_TOP|tx_data|rd_ptr [3] & ((\A_SPW_TOP|tx_data|Mux10~8_combout )))) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux10~5_combout  & ( \A_SPW_TOP|tx_data|Mux10~7_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & (((\A_SPW_TOP|tx_data|rd_ptr [3])))) # 
// (\A_SPW_TOP|tx_data|rd_ptr [5] & ((!\A_SPW_TOP|tx_data|rd_ptr [3] & (\A_SPW_TOP|tx_data|Mux10~6_combout )) # (\A_SPW_TOP|tx_data|rd_ptr [3] & ((\A_SPW_TOP|tx_data|Mux10~8_combout ))))) ) ) ) # ( \A_SPW_TOP|tx_data|Mux10~5_combout  & ( 
// !\A_SPW_TOP|tx_data|Mux10~7_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & (((!\A_SPW_TOP|tx_data|rd_ptr [3])))) # (\A_SPW_TOP|tx_data|rd_ptr [5] & ((!\A_SPW_TOP|tx_data|rd_ptr [3] & (\A_SPW_TOP|tx_data|Mux10~6_combout )) # (\A_SPW_TOP|tx_data|rd_ptr [3] 
// & ((\A_SPW_TOP|tx_data|Mux10~8_combout ))))) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux10~5_combout  & ( !\A_SPW_TOP|tx_data|Mux10~7_combout  & ( (\A_SPW_TOP|tx_data|rd_ptr [5] & ((!\A_SPW_TOP|tx_data|rd_ptr [3] & (\A_SPW_TOP|tx_data|Mux10~6_combout )) # 
// (\A_SPW_TOP|tx_data|rd_ptr [3] & ((\A_SPW_TOP|tx_data|Mux10~8_combout ))))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux10~6_combout ),
        .datab(!\A_SPW_TOP|tx_data|rd_ptr [5]),
        .datac(!\A_SPW_TOP|tx_data|Mux10~8_combout ),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [3]),
        .datae(!\A_SPW_TOP|tx_data|Mux10~5_combout ),
        .dataf(!\A_SPW_TOP|tx_data|Mux10~7_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux10~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux10~9 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux10~9 .lut_mask = 64'h1103DD0311CFDDCF;
defparam \A_SPW_TOP|tx_data|Mux10~9 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y8_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux10~13 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux10~13_combout  = ( \A_SPW_TOP|tx_data|mem[61][7]~q  & ( \A_SPW_TOP|tx_data|rd_ptr [0] & ( (\A_SPW_TOP|tx_data|mem[45][7]~q ) # (\A_SPW_TOP|tx_data|rd_ptr [4]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[61][7]~q  & ( \A_SPW_TOP|tx_data|rd_ptr 
// [0] & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & \A_SPW_TOP|tx_data|mem[45][7]~q ) ) ) ) # ( \A_SPW_TOP|tx_data|mem[61][7]~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [0] & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & (\A_SPW_TOP|tx_data|mem[44][7]~q )) # 
// (\A_SPW_TOP|tx_data|rd_ptr [4] & ((\A_SPW_TOP|tx_data|mem[60][7]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[61][7]~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [0] & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & (\A_SPW_TOP|tx_data|mem[44][7]~q )) # (\A_SPW_TOP|tx_data|rd_ptr 
// [4] & ((\A_SPW_TOP|tx_data|mem[60][7]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[44][7]~q ),
        .datab(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .datac(!\A_SPW_TOP|tx_data|mem[45][7]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[60][7]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[61][7]~q ),
        .dataf(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux10~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux10~13 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux10~13 .lut_mask = 64'h447744770C0C3F3F;
defparam \A_SPW_TOP|tx_data|Mux10~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y8_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux10~12 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux10~12_combout  = ( \A_SPW_TOP|tx_data|mem[29][7]~q  & ( \A_SPW_TOP|tx_data|mem[12][7]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [0] & (((!\A_SPW_TOP|tx_data|rd_ptr [4])) # (\A_SPW_TOP|tx_data|mem[28][7]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr 
// [0] & (((\A_SPW_TOP|tx_data|rd_ptr [4]) # (\A_SPW_TOP|tx_data|mem[13][7]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[29][7]~q  & ( \A_SPW_TOP|tx_data|mem[12][7]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [0] & (((!\A_SPW_TOP|tx_data|rd_ptr [4])) # 
// (\A_SPW_TOP|tx_data|mem[28][7]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [0] & (((\A_SPW_TOP|tx_data|mem[13][7]~q  & !\A_SPW_TOP|tx_data|rd_ptr [4])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[29][7]~q  & ( !\A_SPW_TOP|tx_data|mem[12][7]~q  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|mem[28][7]~q  & ((\A_SPW_TOP|tx_data|rd_ptr [4])))) # (\A_SPW_TOP|tx_data|rd_ptr [0] & (((\A_SPW_TOP|tx_data|rd_ptr [4]) # (\A_SPW_TOP|tx_data|mem[13][7]~q )))) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|mem[29][7]~q  & ( !\A_SPW_TOP|tx_data|mem[12][7]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|mem[28][7]~q  & ((\A_SPW_TOP|tx_data|rd_ptr [4])))) # (\A_SPW_TOP|tx_data|rd_ptr [0] & (((\A_SPW_TOP|tx_data|mem[13][7]~q  & 
// !\A_SPW_TOP|tx_data|rd_ptr [4])))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .datab(!\A_SPW_TOP|tx_data|mem[28][7]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[13][7]~q ),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .datae(!\A_SPW_TOP|tx_data|mem[29][7]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[12][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux10~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux10~12 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux10~12 .lut_mask = 64'h05220577AF22AF77;
defparam \A_SPW_TOP|tx_data|Mux10~12 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y8_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux10~10 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux10~10_combout  = ( \A_SPW_TOP|tx_data|rd_ptr [0] & ( \A_SPW_TOP|tx_data|mem[20][7]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & ((\A_SPW_TOP|tx_data|mem[5][7]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [4] & (\A_SPW_TOP|tx_data|mem[21][7]~q )) ) 
// ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [0] & ( \A_SPW_TOP|tx_data|mem[20][7]~q  & ( (\A_SPW_TOP|tx_data|rd_ptr [4]) # (\A_SPW_TOP|tx_data|mem[4][7]~q ) ) ) ) # ( \A_SPW_TOP|tx_data|rd_ptr [0] & ( !\A_SPW_TOP|tx_data|mem[20][7]~q  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [4] & ((\A_SPW_TOP|tx_data|mem[5][7]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [4] & (\A_SPW_TOP|tx_data|mem[21][7]~q )) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [0] & ( !\A_SPW_TOP|tx_data|mem[20][7]~q  & ( 
// (\A_SPW_TOP|tx_data|mem[4][7]~q  & !\A_SPW_TOP|tx_data|rd_ptr [4]) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[21][7]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[4][7]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[5][7]~q ),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .datae(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .dataf(!\A_SPW_TOP|tx_data|mem[20][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux10~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux10~10 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux10~10 .lut_mask = 64'h33000F5533FF0F55;
defparam \A_SPW_TOP|tx_data|Mux10~10 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y8_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux10~11 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux10~11_combout  = ( \A_SPW_TOP|tx_data|rd_ptr [4] & ( \A_SPW_TOP|tx_data|mem[37][7]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|mem[52][7]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [0] & ((\A_SPW_TOP|tx_data|mem[53][7]~q ))) 
// ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [4] & ( \A_SPW_TOP|tx_data|mem[37][7]~q  & ( (\A_SPW_TOP|tx_data|mem[36][7]~q ) # (\A_SPW_TOP|tx_data|rd_ptr [0]) ) ) ) # ( \A_SPW_TOP|tx_data|rd_ptr [4] & ( !\A_SPW_TOP|tx_data|mem[37][7]~q  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|mem[52][7]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [0] & ((\A_SPW_TOP|tx_data|mem[53][7]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [4] & ( !\A_SPW_TOP|tx_data|mem[37][7]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr 
// [0] & \A_SPW_TOP|tx_data|mem[36][7]~q ) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .datab(!\A_SPW_TOP|tx_data|mem[52][7]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[36][7]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[53][7]~q ),
        .datae(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .dataf(!\A_SPW_TOP|tx_data|mem[37][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux10~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux10~11 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux10~11 .lut_mask = 64'h0A0A22775F5F2277;
defparam \A_SPW_TOP|tx_data|Mux10~11 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y8_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux10~14 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux10~14_combout  = ( \A_SPW_TOP|tx_data|rd_ptr [3] & ( \A_SPW_TOP|tx_data|Mux10~11_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & ((\A_SPW_TOP|tx_data|Mux10~12_combout ))) # (\A_SPW_TOP|tx_data|rd_ptr [5] & 
// (\A_SPW_TOP|tx_data|Mux10~13_combout )) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [3] & ( \A_SPW_TOP|tx_data|Mux10~11_combout  & ( (\A_SPW_TOP|tx_data|Mux10~10_combout ) # (\A_SPW_TOP|tx_data|rd_ptr [5]) ) ) ) # ( \A_SPW_TOP|tx_data|rd_ptr [3] & ( 
// !\A_SPW_TOP|tx_data|Mux10~11_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & ((\A_SPW_TOP|tx_data|Mux10~12_combout ))) # (\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|Mux10~13_combout )) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [3] & ( 
// !\A_SPW_TOP|tx_data|Mux10~11_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & \A_SPW_TOP|tx_data|Mux10~10_combout ) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [5]),
        .datab(!\A_SPW_TOP|tx_data|Mux10~13_combout ),
        .datac(!\A_SPW_TOP|tx_data|Mux10~12_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux10~10_combout ),
        .datae(!\A_SPW_TOP|tx_data|rd_ptr [3]),
        .dataf(!\A_SPW_TOP|tx_data|Mux10~11_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux10~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux10~14 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux10~14 .lut_mask = 64'h00AA1B1B55FF1B1B;
defparam \A_SPW_TOP|tx_data|Mux10~14 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y9_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux10~20 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux10~20_combout  = ( \A_SPW_TOP|tx_data|Mux10~9_combout  & ( \A_SPW_TOP|tx_data|Mux10~14_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & (((\A_SPW_TOP|tx_data|Mux10~4_combout )) # (\A_SPW_TOP|tx_data|rd_ptr [1]))) # 
// (\A_SPW_TOP|tx_data|rd_ptr [2] & ((!\A_SPW_TOP|tx_data|rd_ptr [1]) # ((\A_SPW_TOP|tx_data|Mux10~19_combout )))) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux10~9_combout  & ( \A_SPW_TOP|tx_data|Mux10~14_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & 
// (!\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|Mux10~4_combout ))) # (\A_SPW_TOP|tx_data|rd_ptr [2] & ((!\A_SPW_TOP|tx_data|rd_ptr [1]) # ((\A_SPW_TOP|tx_data|Mux10~19_combout )))) ) ) ) # ( \A_SPW_TOP|tx_data|Mux10~9_combout  & ( 
// !\A_SPW_TOP|tx_data|Mux10~14_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & (((\A_SPW_TOP|tx_data|Mux10~4_combout )) # (\A_SPW_TOP|tx_data|rd_ptr [1]))) # (\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|rd_ptr [1] & 
// ((\A_SPW_TOP|tx_data|Mux10~19_combout )))) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux10~9_combout  & ( !\A_SPW_TOP|tx_data|Mux10~14_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & (!\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|Mux10~4_combout ))) # 
// (\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|rd_ptr [1] & ((\A_SPW_TOP|tx_data|Mux10~19_combout )))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .datab(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .datac(!\A_SPW_TOP|tx_data|Mux10~4_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux10~19_combout ),
        .datae(!\A_SPW_TOP|tx_data|Mux10~9_combout ),
        .dataf(!\A_SPW_TOP|tx_data|Mux10~14_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux10~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux10~20 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux10~20 .lut_mask = 64'h08192A3B4C5D6E7F;
defparam \A_SPW_TOP|tx_data|Mux10~20 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y9_N8
dffeas \A_SPW_TOP|tx_data|data_out[7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|tx_data|Mux10~20_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|data_out [7]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|data_out[7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|data_out[7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X51_Y7_N15
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector33~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector33~0_combout  = ( \A_SPW_TOP|SPW|TX|tx_data_in_0 [7] & ( (!\A_SPW_TOP|SPW|TX|Selector40~0_combout ) # ((\A_SPW_TOP|tx_data|data_out [7] & \A_SPW_TOP|SPW|TX|Selector32~0_combout )) ) ) # ( !\A_SPW_TOP|SPW|TX|tx_data_in_0 [7] & ( 
// (\A_SPW_TOP|tx_data|data_out [7] & \A_SPW_TOP|SPW|TX|Selector32~0_combout ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|SPW|TX|Selector40~0_combout ),
        .datac(!\A_SPW_TOP|tx_data|data_out [7]),
        .datad(!\A_SPW_TOP|SPW|TX|Selector32~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|tx_data_in_0 [7]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector33~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector33~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector33~0 .lut_mask = 64'h000F000FCCCFCCCF;
defparam \A_SPW_TOP|SPW|TX|Selector33~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X53_Y7_N35
dffeas \A_SPW_TOP|SPW|TX|tx_data_in_0[7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|Selector33~0_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|tx_data_in_0 [7]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_data_in_0[7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|tx_data_in_0[7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X53_Y7_N33
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout~38 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout~38_combout  = ( \A_SPW_TOP|SPW|TX|global_counter_transfer [3] & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & (!\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & ((!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]) # 
// (\A_SPW_TOP|SPW|TX|tx_data_in_0 [7])))) ) ) # ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & ( (\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & (\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & \A_SPW_TOP|SPW|TX|global_counter_transfer [1])) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
        .datab(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
        .datac(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
        .datad(!\A_SPW_TOP|SPW|TX|tx_data_in_0 [7]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|tx_dout~38_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout~38 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout~38 .lut_mask = 64'h0101010180A080A0;
defparam \A_SPW_TOP|SPW|TX|tx_dout~38 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y15_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector520~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector520~0_combout  = ( \A_SPW_TOP|tx_data|mem[57][6]~q  & ( (!\A_SPW_TOP|tx_data|Selector518~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux2~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [6]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[57][6]~q  & ( (\A_SPW_TOP|tx_data|Selector518~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux2~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [6])))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\u0|write_data_fifo_tx|data_out [6]),
        .datac(!\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .datad(!\A_SPW_TOP|tx_data|Selector518~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[57][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector520~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector520~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector520~0 .lut_mask = 64'h001B001BFF1BFF1B;
defparam \A_SPW_TOP|tx_data|Selector520~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y15_N17
dffeas \A_SPW_TOP|tx_data|mem[57][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector520~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[57][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[57][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[57][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y14_N39
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector376~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector376~0_combout  = ( \A_SPW_TOP|tx_data|mem[41][6]~q  & ( (!\A_SPW_TOP|tx_data|Selector374~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux2~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [6])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[41][6]~q  & ( (\A_SPW_TOP|tx_data|Selector374~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux2~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [6]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [6]),
        .datac(!\A_SPW_TOP|tx_data|Selector374~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[41][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector376~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector376~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector376~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|tx_data|Selector376~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y14_N26
dffeas \A_SPW_TOP|tx_data|mem[41][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector376~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[41][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[41][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[41][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y14_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector394~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector394~0_combout  = ( \A_SPW_TOP|tx_data|mem[43][6]~q  & ( (!\A_SPW_TOP|tx_data|Selector392~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux2~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [6])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[43][6]~q  & ( (\A_SPW_TOP|tx_data|Selector392~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux2~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [6]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [6]),
        .datac(!\A_SPW_TOP|tx_data|Selector392~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[43][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector394~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector394~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector394~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|tx_data|Selector394~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y14_N17
dffeas \A_SPW_TOP|tx_data|mem[43][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector394~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[43][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[43][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[43][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y14_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector538~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector538~0_combout  = ( \A_SPW_TOP|tx_data|Selector536~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux2~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [6]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector536~0_combout  & ( \A_SPW_TOP|tx_data|mem[59][6]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [6]),
        .datac(!\A_SPW_TOP|tx_data|mem[59][6]~q ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector536~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector538~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector538~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector538~0 .lut_mask = 64'h0F0F0F0F55335533;
defparam \A_SPW_TOP|tx_data|Selector538~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y14_N23
dffeas \A_SPW_TOP|tx_data|mem[59][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector538~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[59][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[59][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[59][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y14_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux2~16 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux2~16_combout  = ( \A_SPW_TOP|tx_data|mem[59][6]~q  & ( \A_SPW_TOP|tx_data|wr_ptr [1] & ( (\A_SPW_TOP|tx_data|mem[43][6]~q ) # (\A_SPW_TOP|tx_data|wr_ptr [4]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[59][6]~q  & ( \A_SPW_TOP|tx_data|wr_ptr 
// [1] & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & \A_SPW_TOP|tx_data|mem[43][6]~q ) ) ) ) # ( \A_SPW_TOP|tx_data|mem[59][6]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & ((\A_SPW_TOP|tx_data|mem[41][6]~q ))) # 
// (\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|mem[57][6]~q )) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[59][6]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & ((\A_SPW_TOP|tx_data|mem[41][6]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr 
// [4] & (\A_SPW_TOP|tx_data|mem[57][6]~q )) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datab(!\A_SPW_TOP|tx_data|mem[57][6]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[41][6]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[43][6]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[59][6]~q ),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux2~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux2~16 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux2~16 .lut_mask = 64'h1B1B1B1B00AA55FF;
defparam \A_SPW_TOP|tx_data|Mux2~16 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y14_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector547~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector547~0_combout  = ( \u0|write_data_fifo_tx|data_out [6] & ( (!\A_SPW_TOP|tx_data|Selector545~0_combout  & (((\A_SPW_TOP|tx_data|mem[60][6]~q )))) # (\A_SPW_TOP|tx_data|Selector545~0_combout  & 
// (((\A_SPW_TOP|tx_data|state_data_write.00~q )) # (\A_SPW_TOP|tx_data|Mux2~20_combout ))) ) ) # ( !\u0|write_data_fifo_tx|data_out [6] & ( (!\A_SPW_TOP|tx_data|Selector545~0_combout  & (((\A_SPW_TOP|tx_data|mem[60][6]~q )))) # 
// (\A_SPW_TOP|tx_data|Selector545~0_combout  & (\A_SPW_TOP|tx_data|Mux2~20_combout  & (!\A_SPW_TOP|tx_data|state_data_write.00~q ))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[60][6]~q ),
        .datad(!\A_SPW_TOP|tx_data|Selector545~0_combout ),
        .datae(gnd),
        .dataf(!\u0|write_data_fifo_tx|data_out [6]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector547~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector547~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector547~0 .lut_mask = 64'h0F440F440F770F77;
defparam \A_SPW_TOP|tx_data|Selector547~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y14_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|mem[60][6]~feeder (
// Equation(s):
// \A_SPW_TOP|tx_data|mem[60][6]~feeder_combout  = ( \A_SPW_TOP|tx_data|Selector547~0_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector547~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|mem[60][6]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[60][6]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|mem[60][6]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|tx_data|mem[60][6]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y14_N5
dffeas \A_SPW_TOP|tx_data|mem[60][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|tx_data|mem[60][6]~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[60][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[60][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[60][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y14_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector403~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector403~0_combout  = ( \u0|write_data_fifo_tx|data_out [6] & ( (!\A_SPW_TOP|tx_data|Selector401~0_combout  & (((\A_SPW_TOP|tx_data|mem[44][6]~q )))) # (\A_SPW_TOP|tx_data|Selector401~0_combout  & 
// (((\A_SPW_TOP|tx_data|state_data_write.00~q )) # (\A_SPW_TOP|tx_data|Mux2~20_combout ))) ) ) # ( !\u0|write_data_fifo_tx|data_out [6] & ( (!\A_SPW_TOP|tx_data|Selector401~0_combout  & (((\A_SPW_TOP|tx_data|mem[44][6]~q )))) # 
// (\A_SPW_TOP|tx_data|Selector401~0_combout  & (\A_SPW_TOP|tx_data|Mux2~20_combout  & (!\A_SPW_TOP|tx_data|state_data_write.00~q ))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[44][6]~q ),
        .datad(!\A_SPW_TOP|tx_data|Selector401~0_combout ),
        .datae(gnd),
        .dataf(!\u0|write_data_fifo_tx|data_out [6]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector403~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector403~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector403~0 .lut_mask = 64'h0F440F440F770F77;
defparam \A_SPW_TOP|tx_data|Selector403~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y14_N23
dffeas \A_SPW_TOP|tx_data|mem[44][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector403~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[44][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[44][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[44][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y14_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector421~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector421~0_combout  = ( \A_SPW_TOP|tx_data|mem[46][6]~q  & ( (!\A_SPW_TOP|tx_data|Selector419~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux2~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [6])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[46][6]~q  & ( (\A_SPW_TOP|tx_data|Selector419~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux2~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [6]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\u0|write_data_fifo_tx|data_out [6]),
        .datad(!\A_SPW_TOP|tx_data|Selector419~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[46][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector421~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector421~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector421~0 .lut_mask = 64'h00470047FF47FF47;
defparam \A_SPW_TOP|tx_data|Selector421~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y14_N39
cyclonev_lcell_comb \A_SPW_TOP|tx_data|mem[46][6]~feeder (
// Equation(s):
// \A_SPW_TOP|tx_data|mem[46][6]~feeder_combout  = ( \A_SPW_TOP|tx_data|Selector421~0_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector421~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|mem[46][6]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[46][6]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|mem[46][6]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|tx_data|mem[46][6]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y14_N41
dffeas \A_SPW_TOP|tx_data|mem[46][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|tx_data|mem[46][6]~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[46][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[46][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[46][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y14_N27
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector565~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector565~0_combout  = ( \A_SPW_TOP|tx_data|mem[62][6]~q  & ( (!\A_SPW_TOP|tx_data|Selector563~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux2~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [6])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[62][6]~q  & ( (\A_SPW_TOP|tx_data|Selector563~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux2~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [6]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\u0|write_data_fifo_tx|data_out [6]),
        .datad(!\A_SPW_TOP|tx_data|Selector563~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[62][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector565~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector565~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector565~0 .lut_mask = 64'h00470047FF47FF47;
defparam \A_SPW_TOP|tx_data|Selector565~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y14_N8
dffeas \A_SPW_TOP|tx_data|mem[62][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector565~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[62][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[62][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[62][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y14_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux2~17 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux2~17_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [4] & ( \A_SPW_TOP|tx_data|mem[62][6]~q  & ( (\A_SPW_TOP|tx_data|wr_ptr [1]) # (\A_SPW_TOP|tx_data|mem[60][6]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [4] & ( 
// \A_SPW_TOP|tx_data|mem[62][6]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|mem[44][6]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [1] & ((\A_SPW_TOP|tx_data|mem[46][6]~q ))) ) ) ) # ( \A_SPW_TOP|tx_data|wr_ptr [4] & ( 
// !\A_SPW_TOP|tx_data|mem[62][6]~q  & ( (\A_SPW_TOP|tx_data|mem[60][6]~q  & !\A_SPW_TOP|tx_data|wr_ptr [1]) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [4] & ( !\A_SPW_TOP|tx_data|mem[62][6]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|mem[44][6]~q 
// )) # (\A_SPW_TOP|tx_data|wr_ptr [1] & ((\A_SPW_TOP|tx_data|mem[46][6]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[60][6]~q ),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datac(!\A_SPW_TOP|tx_data|mem[44][6]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[46][6]~q ),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .dataf(!\A_SPW_TOP|tx_data|mem[62][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux2~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux2~17 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux2~17 .lut_mask = 64'h0C3F44440C3F7777;
defparam \A_SPW_TOP|tx_data|Mux2~17 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y14_N57
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector385~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector385~0_combout  = ( \A_SPW_TOP|tx_data|mem[42][6]~q  & ( (!\A_SPW_TOP|tx_data|Selector383~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux2~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [6])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[42][6]~q  & ( (\A_SPW_TOP|tx_data|Selector383~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux2~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [6]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector383~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [6]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[42][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector385~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector385~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector385~0 .lut_mask = 64'h04070407F4F7F4F7;
defparam \A_SPW_TOP|tx_data|Selector385~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y14_N53
dffeas \A_SPW_TOP|tx_data|mem[42][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector385~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[42][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[42][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[42][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y14_N9
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector367~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector367~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( \A_SPW_TOP|tx_data|mem[40][6]~q  & ( (!\A_SPW_TOP|tx_data|Selector365~0_combout ) # (\u0|write_data_fifo_tx|data_out [6]) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( \A_SPW_TOP|tx_data|mem[40][6]~q  & ( (!\A_SPW_TOP|tx_data|Selector365~0_combout ) # (\A_SPW_TOP|tx_data|Mux2~20_combout ) ) ) ) # ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( 
// !\A_SPW_TOP|tx_data|mem[40][6]~q  & ( (\u0|write_data_fifo_tx|data_out [6] & \A_SPW_TOP|tx_data|Selector365~0_combout ) ) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( !\A_SPW_TOP|tx_data|mem[40][6]~q  & ( (\A_SPW_TOP|tx_data|Mux2~20_combout  & 
// \A_SPW_TOP|tx_data|Selector365~0_combout ) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [6]),
        .datac(gnd),
        .datad(!\A_SPW_TOP|tx_data|Selector365~0_combout ),
        .datae(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[40][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector367~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector367~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector367~0 .lut_mask = 64'h00550033FF55FF33;
defparam \A_SPW_TOP|tx_data|Selector367~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y14_N35
dffeas \A_SPW_TOP|tx_data|mem[40][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector367~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[40][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[40][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[40][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y14_N15
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector529~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector529~0_combout  = ( \A_SPW_TOP|tx_data|Selector527~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux2~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [6]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector527~0_combout  & ( \A_SPW_TOP|tx_data|mem[58][6]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[58][6]~q ),
        .datad(!\u0|write_data_fifo_tx|data_out [6]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector527~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector529~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector529~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector529~0 .lut_mask = 64'h0F0F0F0F44774477;
defparam \A_SPW_TOP|tx_data|Selector529~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y14_N47
dffeas \A_SPW_TOP|tx_data|mem[58][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector529~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[58][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[58][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[58][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y14_N51
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector511~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector511~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( \A_SPW_TOP|tx_data|mem[56][6]~q  & ( (!\A_SPW_TOP|tx_data|Selector509~0_combout ) # (\u0|write_data_fifo_tx|data_out [6]) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( \A_SPW_TOP|tx_data|mem[56][6]~q  & ( (!\A_SPW_TOP|tx_data|Selector509~0_combout ) # (\A_SPW_TOP|tx_data|Mux2~20_combout ) ) ) ) # ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( 
// !\A_SPW_TOP|tx_data|mem[56][6]~q  & ( (\u0|write_data_fifo_tx|data_out [6] & \A_SPW_TOP|tx_data|Selector509~0_combout ) ) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( !\A_SPW_TOP|tx_data|mem[56][6]~q  & ( (\A_SPW_TOP|tx_data|Mux2~20_combout  & 
// \A_SPW_TOP|tx_data|Selector509~0_combout ) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .datab(gnd),
        .datac(!\u0|write_data_fifo_tx|data_out [6]),
        .datad(!\A_SPW_TOP|tx_data|Selector509~0_combout ),
        .datae(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[56][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector511~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector511~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector511~0 .lut_mask = 64'h0055000FFF55FF0F;
defparam \A_SPW_TOP|tx_data|Selector511~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y14_N8
dffeas \A_SPW_TOP|tx_data|mem[56][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector511~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[56][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[56][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[56][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y14_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux2~15 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux2~15_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [4] & ( \A_SPW_TOP|tx_data|mem[56][6]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [1]) # (\A_SPW_TOP|tx_data|mem[58][6]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [4] & ( 
// \A_SPW_TOP|tx_data|mem[56][6]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [1] & ((\A_SPW_TOP|tx_data|mem[40][6]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|mem[42][6]~q )) ) ) ) # ( \A_SPW_TOP|tx_data|wr_ptr [4] & ( 
// !\A_SPW_TOP|tx_data|mem[56][6]~q  & ( (\A_SPW_TOP|tx_data|wr_ptr [1] & \A_SPW_TOP|tx_data|mem[58][6]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [4] & ( !\A_SPW_TOP|tx_data|mem[56][6]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [1] & ((\A_SPW_TOP|tx_data|mem[40][6]~q 
// ))) # (\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|mem[42][6]~q )) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[42][6]~q ),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datac(!\A_SPW_TOP|tx_data|mem[40][6]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[58][6]~q ),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .dataf(!\A_SPW_TOP|tx_data|mem[56][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux2~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux2~15 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux2~15 .lut_mask = 64'h1D1D00331D1DCCFF;
defparam \A_SPW_TOP|tx_data|Mux2~15 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y14_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector430~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector430~0_combout  = ( \A_SPW_TOP|tx_data|Selector428~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux2~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [6]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector428~0_combout  & ( \A_SPW_TOP|tx_data|mem[47][6]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [6]),
        .datac(!\A_SPW_TOP|tx_data|mem[47][6]~q ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector428~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector430~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector430~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector430~0 .lut_mask = 64'h0F0F0F0F55335533;
defparam \A_SPW_TOP|tx_data|Selector430~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y14_N50
dffeas \A_SPW_TOP|tx_data|mem[47][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector430~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[47][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[47][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[47][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y14_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector556~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector556~0_combout  = ( \u0|write_data_fifo_tx|data_out [6] & ( (!\A_SPW_TOP|tx_data|Selector554~0_combout  & (((\A_SPW_TOP|tx_data|mem[61][6]~q )))) # (\A_SPW_TOP|tx_data|Selector554~0_combout  & 
// (((\A_SPW_TOP|tx_data|state_data_write.00~q )) # (\A_SPW_TOP|tx_data|Mux2~20_combout ))) ) ) # ( !\u0|write_data_fifo_tx|data_out [6] & ( (!\A_SPW_TOP|tx_data|Selector554~0_combout  & (((\A_SPW_TOP|tx_data|mem[61][6]~q )))) # 
// (\A_SPW_TOP|tx_data|Selector554~0_combout  & (\A_SPW_TOP|tx_data|Mux2~20_combout  & (!\A_SPW_TOP|tx_data|state_data_write.00~q ))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector554~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|mem[61][6]~q ),
        .datae(gnd),
        .dataf(!\u0|write_data_fifo_tx|data_out [6]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector556~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector556~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector556~0 .lut_mask = 64'h04F404F407F707F7;
defparam \A_SPW_TOP|tx_data|Selector556~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y14_N47
dffeas \A_SPW_TOP|tx_data|mem[61][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector556~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[61][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[61][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[61][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y15_N57
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector412~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector412~0_combout  = ( \A_SPW_TOP|tx_data|Mux2~20_combout  & ( (!\A_SPW_TOP|tx_data|Selector410~0_combout  & (((\A_SPW_TOP|tx_data|mem[45][6]~q )))) # (\A_SPW_TOP|tx_data|Selector410~0_combout  & 
// ((!\A_SPW_TOP|tx_data|state_data_write.00~q ) # ((\u0|write_data_fifo_tx|data_out [6])))) ) ) # ( !\A_SPW_TOP|tx_data|Mux2~20_combout  & ( (!\A_SPW_TOP|tx_data|Selector410~0_combout  & (((\A_SPW_TOP|tx_data|mem[45][6]~q )))) # 
// (\A_SPW_TOP|tx_data|Selector410~0_combout  & (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [6]))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\u0|write_data_fifo_tx|data_out [6]),
        .datac(!\A_SPW_TOP|tx_data|Selector410~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|mem[45][6]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector412~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector412~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector412~0 .lut_mask = 64'h01F101F10BFB0BFB;
defparam \A_SPW_TOP|tx_data|Selector412~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y15_N23
dffeas \A_SPW_TOP|tx_data|mem[45][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector412~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[45][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[45][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[45][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y14_N57
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector574~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector574~0_combout  = ( \A_SPW_TOP|tx_data|mem[63][6]~q  & ( (!\A_SPW_TOP|tx_data|Selector572~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux2~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [6])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[63][6]~q  & ( (\A_SPW_TOP|tx_data|Selector572~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux2~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [6]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\u0|write_data_fifo_tx|data_out [6]),
        .datad(!\A_SPW_TOP|tx_data|Selector572~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[63][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector574~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector574~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector574~0 .lut_mask = 64'h00470047FF47FF47;
defparam \A_SPW_TOP|tx_data|Selector574~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y14_N35
dffeas \A_SPW_TOP|tx_data|mem[63][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector574~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[63][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[63][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[63][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y14_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux2~18 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux2~18_combout  = ( \A_SPW_TOP|tx_data|mem[45][6]~q  & ( \A_SPW_TOP|tx_data|mem[63][6]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & ((!\A_SPW_TOP|tx_data|wr_ptr [1]) # ((\A_SPW_TOP|tx_data|mem[47][6]~q )))) # (\A_SPW_TOP|tx_data|wr_ptr [4] 
// & (((\A_SPW_TOP|tx_data|mem[61][6]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [1]))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[45][6]~q  & ( \A_SPW_TOP|tx_data|mem[63][6]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|wr_ptr [1] & 
// (\A_SPW_TOP|tx_data|mem[47][6]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [4] & (((\A_SPW_TOP|tx_data|mem[61][6]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [1]))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[45][6]~q  & ( !\A_SPW_TOP|tx_data|mem[63][6]~q  & ( 
// (!\A_SPW_TOP|tx_data|wr_ptr [4] & ((!\A_SPW_TOP|tx_data|wr_ptr [1]) # ((\A_SPW_TOP|tx_data|mem[47][6]~q )))) # (\A_SPW_TOP|tx_data|wr_ptr [4] & (!\A_SPW_TOP|tx_data|wr_ptr [1] & ((\A_SPW_TOP|tx_data|mem[61][6]~q )))) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|mem[45][6]~q  & ( !\A_SPW_TOP|tx_data|mem[63][6]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|mem[47][6]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [4] & (!\A_SPW_TOP|tx_data|wr_ptr [1] & 
// ((\A_SPW_TOP|tx_data|mem[61][6]~q )))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datac(!\A_SPW_TOP|tx_data|mem[47][6]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[61][6]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[45][6]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[63][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux2~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux2~18 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux2~18 .lut_mask = 64'h02468ACE13579BDF;
defparam \A_SPW_TOP|tx_data|Mux2~18 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y14_N9
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux2~19 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux2~19_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [2] & ( \A_SPW_TOP|tx_data|Mux2~18_combout  & ( (\A_SPW_TOP|tx_data|wr_ptr [0]) # (\A_SPW_TOP|tx_data|Mux2~17_combout ) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [2] & ( 
// \A_SPW_TOP|tx_data|Mux2~18_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|Mux2~15_combout ))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|Mux2~16_combout )) ) ) ) # ( \A_SPW_TOP|tx_data|wr_ptr [2] & ( 
// !\A_SPW_TOP|tx_data|Mux2~18_combout  & ( (\A_SPW_TOP|tx_data|Mux2~17_combout  & !\A_SPW_TOP|tx_data|wr_ptr [0]) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [2] & ( !\A_SPW_TOP|tx_data|Mux2~18_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & 
// ((\A_SPW_TOP|tx_data|Mux2~15_combout ))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|Mux2~16_combout )) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux2~16_combout ),
        .datab(!\A_SPW_TOP|tx_data|Mux2~17_combout ),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datad(!\A_SPW_TOP|tx_data|Mux2~15_combout ),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .dataf(!\A_SPW_TOP|tx_data|Mux2~18_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux2~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux2~19 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux2~19 .lut_mask = 64'h05F5303005F53F3F;
defparam \A_SPW_TOP|tx_data|Mux2~19 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y15_N45
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector448~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector448~0_combout  = ( \A_SPW_TOP|tx_data|mem[49][6]~q  & ( (!\A_SPW_TOP|tx_data|Selector446~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux2~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [6])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[49][6]~q  & ( (\A_SPW_TOP|tx_data|Selector446~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux2~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [6]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [6]),
        .datac(!\A_SPW_TOP|tx_data|Selector446~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[49][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector448~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector448~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector448~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|tx_data|Selector448~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y15_N35
dffeas \A_SPW_TOP|tx_data|mem[49][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector448~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[49][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[49][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[49][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y15_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector304~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector304~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector302~0_combout  & ((\A_SPW_TOP|tx_data|mem[33][6]~q ))) # (\A_SPW_TOP|tx_data|Selector302~0_combout  & (\u0|write_data_fifo_tx|data_out 
// [6])) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector302~0_combout  & ((\A_SPW_TOP|tx_data|mem[33][6]~q ))) # (\A_SPW_TOP|tx_data|Selector302~0_combout  & (\A_SPW_TOP|tx_data|Mux2~20_combout )) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [6]),
        .datac(!\A_SPW_TOP|tx_data|mem[33][6]~q ),
        .datad(!\A_SPW_TOP|tx_data|Selector302~0_combout ),
        .datae(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector304~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector304~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector304~0 .lut_mask = 64'h0F550F330F550F33;
defparam \A_SPW_TOP|tx_data|Selector304~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X45_Y15_N35
dffeas \A_SPW_TOP|tx_data|mem[33][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector304~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[33][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[33][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[33][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y15_N57
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector340~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector340~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( \A_SPW_TOP|tx_data|Selector338~0_combout  & ( \u0|write_data_fifo_tx|data_out [6] ) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( 
// \A_SPW_TOP|tx_data|Selector338~0_combout  & ( \A_SPW_TOP|tx_data|Mux2~20_combout  ) ) ) # ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( !\A_SPW_TOP|tx_data|Selector338~0_combout  & ( \A_SPW_TOP|tx_data|mem[37][6]~q  ) ) ) # ( 
// !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( !\A_SPW_TOP|tx_data|Selector338~0_combout  & ( \A_SPW_TOP|tx_data|mem[37][6]~q  ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [6]),
        .datac(!\A_SPW_TOP|tx_data|mem[37][6]~q ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .dataf(!\A_SPW_TOP|tx_data|Selector338~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector340~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector340~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector340~0 .lut_mask = 64'h0F0F0F0F55553333;
defparam \A_SPW_TOP|tx_data|Selector340~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y15_N17
dffeas \A_SPW_TOP|tx_data|mem[37][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector340~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[37][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[37][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[37][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y15_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector484~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector484~0_combout  = ( \A_SPW_TOP|tx_data|Selector482~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux2~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [6]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector482~0_combout  & ( \A_SPW_TOP|tx_data|mem[53][6]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [6]),
        .datac(!\A_SPW_TOP|tx_data|mem[53][6]~q ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector482~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector484~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector484~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector484~0 .lut_mask = 64'h0F0F0F0F55335533;
defparam \A_SPW_TOP|tx_data|Selector484~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y15_N8
dffeas \A_SPW_TOP|tx_data|mem[53][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector484~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[53][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[53][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[53][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y15_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux2~11 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux2~11_combout  = ( \A_SPW_TOP|tx_data|mem[53][6]~q  & ( \A_SPW_TOP|tx_data|wr_ptr [4] & ( (\A_SPW_TOP|tx_data|wr_ptr [2]) # (\A_SPW_TOP|tx_data|mem[49][6]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[53][6]~q  & ( \A_SPW_TOP|tx_data|wr_ptr 
// [4] & ( (\A_SPW_TOP|tx_data|mem[49][6]~q  & !\A_SPW_TOP|tx_data|wr_ptr [2]) ) ) ) # ( \A_SPW_TOP|tx_data|mem[53][6]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [4] & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|mem[33][6]~q )) # 
// (\A_SPW_TOP|tx_data|wr_ptr [2] & ((\A_SPW_TOP|tx_data|mem[37][6]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[53][6]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [4] & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|mem[33][6]~q )) # (\A_SPW_TOP|tx_data|wr_ptr 
// [2] & ((\A_SPW_TOP|tx_data|mem[37][6]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[49][6]~q ),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datac(!\A_SPW_TOP|tx_data|mem[33][6]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[37][6]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[53][6]~q ),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux2~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux2~11 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux2~11 .lut_mask = 64'h0C3F0C3F44447777;
defparam \A_SPW_TOP|tx_data|Mux2~11 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y15_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector322~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector322~0_combout  = ( \A_SPW_TOP|tx_data|Selector320~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux2~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [6]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector320~0_combout  & ( \A_SPW_TOP|tx_data|mem[35][6]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [6]),
        .datac(!\A_SPW_TOP|tx_data|mem[35][6]~q ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector320~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector322~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector322~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector322~0 .lut_mask = 64'h0F0F0F0F55335533;
defparam \A_SPW_TOP|tx_data|Selector322~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y15_N53
dffeas \A_SPW_TOP|tx_data|mem[35][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector322~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[35][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[35][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[35][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y15_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector358~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector358~0_combout  = ( \A_SPW_TOP|tx_data|mem[39][6]~q  & ( (!\A_SPW_TOP|tx_data|Selector356~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux2~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [6]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[39][6]~q  & ( (\A_SPW_TOP|tx_data|Selector356~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux2~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [6])))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\u0|write_data_fifo_tx|data_out [6]),
        .datac(!\A_SPW_TOP|tx_data|Selector356~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[39][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector358~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector358~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector358~0 .lut_mask = 64'h010B010BF1FBF1FB;
defparam \A_SPW_TOP|tx_data|Selector358~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y15_N32
dffeas \A_SPW_TOP|tx_data|mem[39][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector358~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[39][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[39][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[39][6] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y15_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector466~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector466~0_combout  = ( \A_SPW_TOP|tx_data|mem[51][6]~q  & ( (!\A_SPW_TOP|tx_data|Selector464~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux2~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [6])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[51][6]~q  & ( (\A_SPW_TOP|tx_data|Selector464~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux2~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [6]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\u0|write_data_fifo_tx|data_out [6]),
        .datad(!\A_SPW_TOP|tx_data|Selector464~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[51][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector466~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector466~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector466~0 .lut_mask = 64'h00470047FF47FF47;
defparam \A_SPW_TOP|tx_data|Selector466~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y15_N17
dffeas \A_SPW_TOP|tx_data|mem[51][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector466~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[51][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[51][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[51][6] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y15_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector502~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector502~0_combout  = ( \A_SPW_TOP|tx_data|mem[55][6]~q  & ( (!\A_SPW_TOP|tx_data|Selector500~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux2~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [6])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[55][6]~q  & ( (\A_SPW_TOP|tx_data|Selector500~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux2~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [6]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [6]),
        .datac(!\A_SPW_TOP|tx_data|Selector500~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[55][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector502~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector502~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector502~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|tx_data|Selector502~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y15_N32
dffeas \A_SPW_TOP|tx_data|mem[55][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector502~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[55][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[55][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[55][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y15_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux2~13 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux2~13_combout  = ( \A_SPW_TOP|tx_data|mem[55][6]~q  & ( \A_SPW_TOP|tx_data|wr_ptr [2] & ( (\A_SPW_TOP|tx_data|wr_ptr [4]) # (\A_SPW_TOP|tx_data|mem[39][6]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[55][6]~q  & ( \A_SPW_TOP|tx_data|wr_ptr 
// [2] & ( (\A_SPW_TOP|tx_data|mem[39][6]~q  & !\A_SPW_TOP|tx_data|wr_ptr [4]) ) ) ) # ( \A_SPW_TOP|tx_data|mem[55][6]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [2] & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|mem[35][6]~q )) # 
// (\A_SPW_TOP|tx_data|wr_ptr [4] & ((\A_SPW_TOP|tx_data|mem[51][6]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[55][6]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [2] & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|mem[35][6]~q )) # (\A_SPW_TOP|tx_data|wr_ptr 
// [4] & ((\A_SPW_TOP|tx_data|mem[51][6]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[35][6]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[39][6]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[51][6]~q ),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datae(!\A_SPW_TOP|tx_data|mem[55][6]~q ),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux2~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux2~13 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux2~13 .lut_mask = 64'h550F550F330033FF;
defparam \A_SPW_TOP|tx_data|Mux2~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y15_N39
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector457~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector457~0_combout  = ( \A_SPW_TOP|tx_data|Selector455~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux2~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [6]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector455~0_combout  & ( \A_SPW_TOP|tx_data|mem[50][6]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [6]),
        .datac(!\A_SPW_TOP|tx_data|mem[50][6]~q ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector455~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector457~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector457~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector457~0 .lut_mask = 64'h0F0F0F0F55335533;
defparam \A_SPW_TOP|tx_data|Selector457~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y15_N14
dffeas \A_SPW_TOP|tx_data|mem[50][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector457~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[50][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[50][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[50][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y15_N21
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector313~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector313~0_combout  = ( \A_SPW_TOP|tx_data|mem[34][6]~q  & ( (!\A_SPW_TOP|tx_data|Selector311~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux2~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [6])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[34][6]~q  & ( (\A_SPW_TOP|tx_data|Selector311~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux2~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [6]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\u0|write_data_fifo_tx|data_out [6]),
        .datad(!\A_SPW_TOP|tx_data|Selector311~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[34][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector313~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector313~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector313~0 .lut_mask = 64'h00470047FF47FF47;
defparam \A_SPW_TOP|tx_data|Selector313~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X45_Y15_N41
dffeas \A_SPW_TOP|tx_data|mem[34][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector313~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[34][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[34][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[34][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y15_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector349~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector349~0_combout  = ( \A_SPW_TOP|tx_data|mem[38][6]~q  & ( (!\A_SPW_TOP|tx_data|Selector347~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux2~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [6])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[38][6]~q  & ( (\A_SPW_TOP|tx_data|Selector347~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux2~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [6]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [6]),
        .datac(!\A_SPW_TOP|tx_data|Selector347~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[38][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector349~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector349~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector349~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|tx_data|Selector349~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X45_Y15_N32
dffeas \A_SPW_TOP|tx_data|mem[38][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector349~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[38][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[38][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[38][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y15_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector493~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector493~0_combout  = ( \A_SPW_TOP|tx_data|Selector491~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux2~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [6]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector491~0_combout  & ( \A_SPW_TOP|tx_data|mem[54][6]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [6]),
        .datac(!\A_SPW_TOP|tx_data|mem[54][6]~q ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector491~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector493~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector493~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector493~0 .lut_mask = 64'h0F0F0F0F55335533;
defparam \A_SPW_TOP|tx_data|Selector493~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y15_N56
dffeas \A_SPW_TOP|tx_data|mem[54][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector493~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[54][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[54][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[54][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y15_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux2~12 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux2~12_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [2] & ( \A_SPW_TOP|tx_data|mem[54][6]~q  & ( (\A_SPW_TOP|tx_data|mem[38][6]~q ) # (\A_SPW_TOP|tx_data|wr_ptr [4]) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [2] & ( 
// \A_SPW_TOP|tx_data|mem[54][6]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & ((\A_SPW_TOP|tx_data|mem[34][6]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|mem[50][6]~q )) ) ) ) # ( \A_SPW_TOP|tx_data|wr_ptr [2] & ( 
// !\A_SPW_TOP|tx_data|mem[54][6]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & \A_SPW_TOP|tx_data|mem[38][6]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [2] & ( !\A_SPW_TOP|tx_data|mem[54][6]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & 
// ((\A_SPW_TOP|tx_data|mem[34][6]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|mem[50][6]~q )) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[50][6]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[34][6]~q ),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datad(!\A_SPW_TOP|tx_data|mem[38][6]~q ),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .dataf(!\A_SPW_TOP|tx_data|mem[54][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux2~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux2~12 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux2~12 .lut_mask = 64'h353500F035350FFF;
defparam \A_SPW_TOP|tx_data|Mux2~12 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y15_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector295~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector295~0_combout  = ( \A_SPW_TOP|tx_data|mem[32][6]~q  & ( (!\A_SPW_TOP|tx_data|Selector293~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux2~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [6])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[32][6]~q  & ( (\A_SPW_TOP|tx_data|Selector293~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux2~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [6]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector293~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [6]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[32][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector295~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector295~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector295~0 .lut_mask = 64'h04070407F4F7F4F7;
defparam \A_SPW_TOP|tx_data|Selector295~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X45_Y15_N11
dffeas \A_SPW_TOP|tx_data|mem[32][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector295~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[32][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[32][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[32][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y15_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector439~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector439~0_combout  = ( \A_SPW_TOP|tx_data|mem[48][6]~q  & ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector437~0_combout ) # (\u0|write_data_fifo_tx|data_out [6]) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|mem[48][6]~q  & ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (\u0|write_data_fifo_tx|data_out [6] & \A_SPW_TOP|tx_data|Selector437~0_combout ) ) ) ) # ( \A_SPW_TOP|tx_data|mem[48][6]~q  & ( !\A_SPW_TOP|tx_data|state_data_write.00~q  
// & ( (!\A_SPW_TOP|tx_data|Selector437~0_combout ) # (\A_SPW_TOP|tx_data|Mux2~20_combout ) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[48][6]~q  & ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( (\A_SPW_TOP|tx_data|Mux2~20_combout  & 
// \A_SPW_TOP|tx_data|Selector437~0_combout ) ) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [6]),
        .datab(!\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector437~0_combout ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|tx_data|mem[48][6]~q ),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector439~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector439~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector439~0 .lut_mask = 64'h0303F3F30505F5F5;
defparam \A_SPW_TOP|tx_data|Selector439~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y15_N47
dffeas \A_SPW_TOP|tx_data|mem[48][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector439~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[48][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[48][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[48][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y15_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector331~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector331~0_combout  = ( \A_SPW_TOP|tx_data|Selector329~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux2~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [6]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector329~0_combout  & ( \A_SPW_TOP|tx_data|mem[36][6]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [6]),
        .datac(!\A_SPW_TOP|tx_data|mem[36][6]~q ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector329~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector331~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector331~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector331~0 .lut_mask = 64'h0F0F0F0F55335533;
defparam \A_SPW_TOP|tx_data|Selector331~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X45_Y15_N17
dffeas \A_SPW_TOP|tx_data|mem[36][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector331~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[36][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[36][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[36][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y15_N27
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector475~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector475~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector473~0_combout  & (\A_SPW_TOP|tx_data|mem[52][6]~q )) # (\A_SPW_TOP|tx_data|Selector473~0_combout  & ((\u0|write_data_fifo_tx|data_out 
// [6]))) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector473~0_combout  & (\A_SPW_TOP|tx_data|mem[52][6]~q )) # (\A_SPW_TOP|tx_data|Selector473~0_combout  & ((\A_SPW_TOP|tx_data|Mux2~20_combout ))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Selector473~0_combout ),
        .datab(!\A_SPW_TOP|tx_data|mem[52][6]~q ),
        .datac(!\u0|write_data_fifo_tx|data_out [6]),
        .datad(!\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector475~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector475~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector475~0 .lut_mask = 64'h2277227727272727;
defparam \A_SPW_TOP|tx_data|Selector475~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X45_Y15_N38
dffeas \A_SPW_TOP|tx_data|mem[52][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector475~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[52][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[52][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[52][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y15_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux2~10 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux2~10_combout  = ( \A_SPW_TOP|tx_data|mem[52][6]~q  & ( \A_SPW_TOP|tx_data|wr_ptr [4] & ( (\A_SPW_TOP|tx_data|mem[48][6]~q ) # (\A_SPW_TOP|tx_data|wr_ptr [2]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[52][6]~q  & ( \A_SPW_TOP|tx_data|wr_ptr 
// [4] & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & \A_SPW_TOP|tx_data|mem[48][6]~q ) ) ) ) # ( \A_SPW_TOP|tx_data|mem[52][6]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [4] & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|mem[32][6]~q )) # 
// (\A_SPW_TOP|tx_data|wr_ptr [2] & ((\A_SPW_TOP|tx_data|mem[36][6]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[52][6]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [4] & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|mem[32][6]~q )) # (\A_SPW_TOP|tx_data|wr_ptr 
// [2] & ((\A_SPW_TOP|tx_data|mem[36][6]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datab(!\A_SPW_TOP|tx_data|mem[32][6]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[48][6]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[36][6]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[52][6]~q ),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux2~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux2~10 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux2~10 .lut_mask = 64'h227722770A0A5F5F;
defparam \A_SPW_TOP|tx_data|Mux2~10 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y15_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux2~14 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux2~14_combout  = ( \A_SPW_TOP|tx_data|Mux2~10_combout  & ( \A_SPW_TOP|tx_data|wr_ptr [1] & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|Mux2~12_combout ))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & 
// (\A_SPW_TOP|tx_data|Mux2~13_combout )) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux2~10_combout  & ( \A_SPW_TOP|tx_data|wr_ptr [1] & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|Mux2~12_combout ))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & 
// (\A_SPW_TOP|tx_data|Mux2~13_combout )) ) ) ) # ( \A_SPW_TOP|tx_data|Mux2~10_combout  & ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( (!\A_SPW_TOP|tx_data|wr_ptr [0]) # (\A_SPW_TOP|tx_data|Mux2~11_combout ) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux2~10_combout  & ( 
// !\A_SPW_TOP|tx_data|wr_ptr [1] & ( (\A_SPW_TOP|tx_data|Mux2~11_combout  & \A_SPW_TOP|tx_data|wr_ptr [0]) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux2~11_combout ),
        .datab(!\A_SPW_TOP|tx_data|Mux2~13_combout ),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datad(!\A_SPW_TOP|tx_data|Mux2~12_combout ),
        .datae(!\A_SPW_TOP|tx_data|Mux2~10_combout ),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux2~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux2~14 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux2~14 .lut_mask = 64'h0505F5F503F303F3;
defparam \A_SPW_TOP|tx_data|Mux2~14 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y15_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector196~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector196~0_combout  = ( \A_SPW_TOP|tx_data|Selector194~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux2~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\u0|write_data_fifo_tx|data_out [6])) ) ) # ( !\A_SPW_TOP|tx_data|Selector194~0_combout  & ( \A_SPW_TOP|tx_data|mem[21][6]~q  ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [6]),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .datad(!\A_SPW_TOP|tx_data|mem[21][6]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector194~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector196~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector196~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector196~0 .lut_mask = 64'h00FF00FF1D1D1D1D;
defparam \A_SPW_TOP|tx_data|Selector196~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y15_N29
dffeas \A_SPW_TOP|tx_data|mem[21][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector196~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[21][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[21][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[21][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y15_N57
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector52~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector52~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector50~0_combout  & ((\A_SPW_TOP|tx_data|mem[5][6]~q ))) # (\A_SPW_TOP|tx_data|Selector50~0_combout  & (\u0|write_data_fifo_tx|data_out 
// [6])) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector50~0_combout  & ((\A_SPW_TOP|tx_data|mem[5][6]~q ))) # (\A_SPW_TOP|tx_data|Selector50~0_combout  & (\A_SPW_TOP|tx_data|Mux2~20_combout )) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [6]),
        .datab(!\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|mem[5][6]~q ),
        .datad(!\A_SPW_TOP|tx_data|Selector50~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector52~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector52~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector52~0 .lut_mask = 64'h0F330F330F550F55;
defparam \A_SPW_TOP|tx_data|Selector52~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y15_N41
dffeas \A_SPW_TOP|tx_data|mem[5][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector52~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[5][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[5][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[5][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y15_N33
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector160~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector160~0_combout  = ( \A_SPW_TOP|tx_data|Selector158~0_combout  & ( \A_SPW_TOP|tx_data|mem[17][6]~q  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux2~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [6])) ) ) ) # ( !\A_SPW_TOP|tx_data|Selector158~0_combout  & ( \A_SPW_TOP|tx_data|mem[17][6]~q  ) ) # ( \A_SPW_TOP|tx_data|Selector158~0_combout  & ( 
// !\A_SPW_TOP|tx_data|mem[17][6]~q  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux2~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [6])) ) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [6]),
        .datab(!\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|tx_data|Selector158~0_combout ),
        .dataf(!\A_SPW_TOP|tx_data|mem[17][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector160~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector160~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector160~0 .lut_mask = 64'h00003535FFFF3535;
defparam \A_SPW_TOP|tx_data|Selector160~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y15_N53
dffeas \A_SPW_TOP|tx_data|mem[17][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector160~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[17][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[17][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[17][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y15_N15
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector16~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector16~0_combout  = ( \A_SPW_TOP|tx_data|Selector14~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux2~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\u0|write_data_fifo_tx|data_out [6])) ) ) # ( !\A_SPW_TOP|tx_data|Selector14~0_combout  & ( \A_SPW_TOP|tx_data|mem[1][6]~q  ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [6]),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[1][6]~q ),
        .datad(!\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .datae(!\A_SPW_TOP|tx_data|Selector14~0_combout ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector16~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector16~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector16~0 .lut_mask = 64'h0F0F11DD0F0F11DD;
defparam \A_SPW_TOP|tx_data|Selector16~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y15_N14
dffeas \A_SPW_TOP|tx_data|mem[1][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector16~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[1][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[1][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[1][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y15_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux2~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux2~1_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [2] & ( \A_SPW_TOP|tx_data|mem[1][6]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & ((\A_SPW_TOP|tx_data|mem[5][6]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|mem[21][6]~q )) ) ) 
// ) # ( !\A_SPW_TOP|tx_data|wr_ptr [2] & ( \A_SPW_TOP|tx_data|mem[1][6]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [4]) # (\A_SPW_TOP|tx_data|mem[17][6]~q ) ) ) ) # ( \A_SPW_TOP|tx_data|wr_ptr [2] & ( !\A_SPW_TOP|tx_data|mem[1][6]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr 
// [4] & ((\A_SPW_TOP|tx_data|mem[5][6]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|mem[21][6]~q )) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [2] & ( !\A_SPW_TOP|tx_data|mem[1][6]~q  & ( (\A_SPW_TOP|tx_data|mem[17][6]~q  & 
// \A_SPW_TOP|tx_data|wr_ptr [4]) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[21][6]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[5][6]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[17][6]~q ),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .dataf(!\A_SPW_TOP|tx_data|mem[1][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux2~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux2~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux2~1 .lut_mask = 64'h000F3355FF0F3355;
defparam \A_SPW_TOP|tx_data|Mux2~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y15_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector205~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector205~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( \A_SPW_TOP|tx_data|mem[22][6]~q  & ( (!\A_SPW_TOP|tx_data|Selector203~0_combout ) # (\u0|write_data_fifo_tx|data_out [6]) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( \A_SPW_TOP|tx_data|mem[22][6]~q  & ( (!\A_SPW_TOP|tx_data|Selector203~0_combout ) # (\A_SPW_TOP|tx_data|Mux2~20_combout ) ) ) ) # ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( 
// !\A_SPW_TOP|tx_data|mem[22][6]~q  & ( (\u0|write_data_fifo_tx|data_out [6] & \A_SPW_TOP|tx_data|Selector203~0_combout ) ) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( !\A_SPW_TOP|tx_data|mem[22][6]~q  & ( (\A_SPW_TOP|tx_data|Mux2~20_combout  & 
// \A_SPW_TOP|tx_data|Selector203~0_combout ) ) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [6]),
        .datab(!\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector203~0_combout ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[22][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector205~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector205~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector205~0 .lut_mask = 64'h03030505F3F3F5F5;
defparam \A_SPW_TOP|tx_data|Selector205~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y15_N41
dffeas \A_SPW_TOP|tx_data|mem[22][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector205~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[22][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[22][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[22][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y15_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector25~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector25~0_combout  = ( \A_SPW_TOP|tx_data|Selector23~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux2~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out 
// [6]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector23~0_combout  & ( \A_SPW_TOP|tx_data|mem[2][6]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [6]),
        .datac(!\A_SPW_TOP|tx_data|mem[2][6]~q ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector23~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector25~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector25~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector25~0 .lut_mask = 64'h0F0F0F0F55335533;
defparam \A_SPW_TOP|tx_data|Selector25~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y15_N17
dffeas \A_SPW_TOP|tx_data|mem[2][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector25~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[2][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[2][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[2][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y15_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector169~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector169~0_combout  = ( \A_SPW_TOP|tx_data|mem[18][6]~q  & ( (!\A_SPW_TOP|tx_data|Selector167~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux2~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [6])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[18][6]~q  & ( (\A_SPW_TOP|tx_data|Selector167~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux2~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [6]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector167~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [6]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[18][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector169~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector169~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector169~0 .lut_mask = 64'h04070407F4F7F4F7;
defparam \A_SPW_TOP|tx_data|Selector169~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X45_Y15_N14
dffeas \A_SPW_TOP|tx_data|mem[18][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector169~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[18][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[18][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[18][6] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y15_N27
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux2~2 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux2~2_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [2] & ( \A_SPW_TOP|tx_data|mem[18][6]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & ((\A_SPW_TOP|tx_data|mem[6][6]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|mem[22][6]~q )) ) ) 
// ) # ( !\A_SPW_TOP|tx_data|wr_ptr [2] & ( \A_SPW_TOP|tx_data|mem[18][6]~q  & ( (\A_SPW_TOP|tx_data|mem[2][6]~q ) # (\A_SPW_TOP|tx_data|wr_ptr [4]) ) ) ) # ( \A_SPW_TOP|tx_data|wr_ptr [2] & ( !\A_SPW_TOP|tx_data|mem[18][6]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr 
// [4] & ((\A_SPW_TOP|tx_data|mem[6][6]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|mem[22][6]~q )) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [2] & ( !\A_SPW_TOP|tx_data|mem[18][6]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & 
// \A_SPW_TOP|tx_data|mem[2][6]~q ) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[22][6]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[6][6]~q ),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datad(!\A_SPW_TOP|tx_data|mem[2][6]~q ),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .dataf(!\A_SPW_TOP|tx_data|mem[18][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux2~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux2~2 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux2~2 .lut_mask = 64'h00F035350FFF3535;
defparam \A_SPW_TOP|tx_data|Mux2~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y15_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector34~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector34~0_combout  = ( \A_SPW_TOP|tx_data|Selector32~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux2~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\u0|write_data_fifo_tx|data_out [6])) ) ) # ( !\A_SPW_TOP|tx_data|Selector32~0_combout  & ( \A_SPW_TOP|tx_data|mem[3][6]~q  ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [6]),
        .datab(!\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[3][6]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector32~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector34~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector34~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector34~0 .lut_mask = 64'h00FF00FF35353535;
defparam \A_SPW_TOP|tx_data|Selector34~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y15_N23
dffeas \A_SPW_TOP|tx_data|mem[3][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector34~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[3][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[3][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[3][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y15_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector70~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector70~0_combout  = ( \A_SPW_TOP|tx_data|mem[7][6]~q  & ( (!\A_SPW_TOP|tx_data|Selector68~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux2~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [6]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[7][6]~q  & ( (\A_SPW_TOP|tx_data|Selector68~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux2~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [6])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [6]),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector68~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[7][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector70~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector70~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector70~0 .lut_mask = 64'h010D010DF1FDF1FD;
defparam \A_SPW_TOP|tx_data|Selector70~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y15_N32
dffeas \A_SPW_TOP|tx_data|mem[7][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector70~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[7][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[7][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[7][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y15_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector214~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector214~0_combout  = ( \A_SPW_TOP|tx_data|mem[23][6]~q  & ( (!\A_SPW_TOP|tx_data|Selector212~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux2~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [6])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[23][6]~q  & ( (\A_SPW_TOP|tx_data|Selector212~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux2~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [6]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\u0|write_data_fifo_tx|data_out [6]),
        .datad(!\A_SPW_TOP|tx_data|Selector212~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[23][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector214~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector214~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector214~0 .lut_mask = 64'h00470047FF47FF47;
defparam \A_SPW_TOP|tx_data|Selector214~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y15_N44
dffeas \A_SPW_TOP|tx_data|mem[23][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector214~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[23][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[23][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[23][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y15_N9
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector178~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector178~0_combout  = ( \A_SPW_TOP|tx_data|mem[19][6]~q  & ( (!\A_SPW_TOP|tx_data|Selector176~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux2~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [6])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[19][6]~q  & ( (\A_SPW_TOP|tx_data|Selector176~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux2~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [6]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector176~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [6]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[19][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector178~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector178~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector178~0 .lut_mask = 64'h04070407F4F7F4F7;
defparam \A_SPW_TOP|tx_data|Selector178~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y15_N50
dffeas \A_SPW_TOP|tx_data|mem[19][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector178~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[19][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[19][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[19][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y15_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux2~3 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux2~3_combout  = ( \A_SPW_TOP|tx_data|mem[23][6]~q  & ( \A_SPW_TOP|tx_data|mem[19][6]~q  & ( ((!\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|mem[3][6]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [2] & ((\A_SPW_TOP|tx_data|mem[7][6]~q )))) 
// # (\A_SPW_TOP|tx_data|wr_ptr [4]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[23][6]~q  & ( \A_SPW_TOP|tx_data|mem[19][6]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & (((\A_SPW_TOP|tx_data|mem[3][6]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [4]))) # (\A_SPW_TOP|tx_data|wr_ptr 
// [2] & (!\A_SPW_TOP|tx_data|wr_ptr [4] & ((\A_SPW_TOP|tx_data|mem[7][6]~q )))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[23][6]~q  & ( !\A_SPW_TOP|tx_data|mem[19][6]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & (!\A_SPW_TOP|tx_data|wr_ptr [4] & 
// (\A_SPW_TOP|tx_data|mem[3][6]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [2] & (((\A_SPW_TOP|tx_data|mem[7][6]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [4]))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[23][6]~q  & ( !\A_SPW_TOP|tx_data|mem[19][6]~q  & ( 
// (!\A_SPW_TOP|tx_data|wr_ptr [4] & ((!\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|mem[3][6]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [2] & ((\A_SPW_TOP|tx_data|mem[7][6]~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datac(!\A_SPW_TOP|tx_data|mem[3][6]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[7][6]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[23][6]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[19][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux2~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux2~3 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux2~3 .lut_mask = 64'h084C195D2A6E3B7F;
defparam \A_SPW_TOP|tx_data|Mux2~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y15_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector43~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector43~0_combout  = ( \A_SPW_TOP|tx_data|mem[4][6]~q  & ( (!\A_SPW_TOP|tx_data|Selector41~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux2~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [6])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[4][6]~q  & ( (\A_SPW_TOP|tx_data|Selector41~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux2~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [6]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [6]),
        .datac(!\A_SPW_TOP|tx_data|Selector41~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[4][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector43~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector43~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector43~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|tx_data|Selector43~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y15_N53
dffeas \A_SPW_TOP|tx_data|mem[4][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector43~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[4][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[4][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[4][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y15_N45
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector187~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector187~0_combout  = ( \A_SPW_TOP|tx_data|mem[20][6]~q  & ( (!\A_SPW_TOP|tx_data|Selector185~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux2~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [6])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[20][6]~q  & ( (\A_SPW_TOP|tx_data|Selector185~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux2~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [6]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\u0|write_data_fifo_tx|data_out [6]),
        .datad(!\A_SPW_TOP|tx_data|Selector185~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[20][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector187~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector187~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector187~0 .lut_mask = 64'h00470047FF47FF47;
defparam \A_SPW_TOP|tx_data|Selector187~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X45_Y15_N50
dffeas \A_SPW_TOP|tx_data|mem[20][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector187~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[20][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[20][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[20][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y15_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector151~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector151~0_combout  = ( \A_SPW_TOP|tx_data|Selector149~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux2~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [6]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector149~0_combout  & ( \A_SPW_TOP|tx_data|mem[16][6]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[16][6]~q ),
        .datad(!\u0|write_data_fifo_tx|data_out [6]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector149~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector151~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector151~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector151~0 .lut_mask = 64'h0F0F0F0F44774477;
defparam \A_SPW_TOP|tx_data|Selector151~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X45_Y15_N53
dffeas \A_SPW_TOP|tx_data|mem[16][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector151~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[16][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[16][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[16][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y15_N57
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector7~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector7~0_combout  = ( \A_SPW_TOP|tx_data|mem[0][6]~q  & ( (!\A_SPW_TOP|tx_data|Selector5~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux2~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  
// & ((\u0|write_data_fifo_tx|data_out [6])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[0][6]~q  & ( (\A_SPW_TOP|tx_data|Selector5~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux2~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [6]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\u0|write_data_fifo_tx|data_out [6]),
        .datad(!\A_SPW_TOP|tx_data|Selector5~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[0][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector7~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector7~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector7~0 .lut_mask = 64'h00470047FF47FF47;
defparam \A_SPW_TOP|tx_data|Selector7~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X45_Y15_N26
dffeas \A_SPW_TOP|tx_data|mem[0][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector7~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[0][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[0][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[0][6] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y15_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux2~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux2~0_combout  = ( \A_SPW_TOP|tx_data|mem[16][6]~q  & ( \A_SPW_TOP|tx_data|mem[0][6]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [2]) # ((!\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|mem[4][6]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [4] & 
// ((\A_SPW_TOP|tx_data|mem[20][6]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[16][6]~q  & ( \A_SPW_TOP|tx_data|mem[0][6]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & (((!\A_SPW_TOP|tx_data|wr_ptr [2])) # (\A_SPW_TOP|tx_data|mem[4][6]~q ))) # 
// (\A_SPW_TOP|tx_data|wr_ptr [4] & (((\A_SPW_TOP|tx_data|wr_ptr [2] & \A_SPW_TOP|tx_data|mem[20][6]~q )))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[16][6]~q  & ( !\A_SPW_TOP|tx_data|mem[0][6]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|mem[4][6]~q  
// & (\A_SPW_TOP|tx_data|wr_ptr [2]))) # (\A_SPW_TOP|tx_data|wr_ptr [4] & (((!\A_SPW_TOP|tx_data|wr_ptr [2]) # (\A_SPW_TOP|tx_data|mem[20][6]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[16][6]~q  & ( !\A_SPW_TOP|tx_data|mem[0][6]~q  & ( 
// (\A_SPW_TOP|tx_data|wr_ptr [2] & ((!\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|mem[4][6]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [4] & ((\A_SPW_TOP|tx_data|mem[20][6]~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[4][6]~q ),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datad(!\A_SPW_TOP|tx_data|mem[20][6]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[16][6]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[0][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux2~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux2~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux2~0 .lut_mask = 64'h04073437C4C7F4F7;
defparam \A_SPW_TOP|tx_data|Mux2~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y15_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux2~4 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux2~4_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [0] & ( \A_SPW_TOP|tx_data|Mux2~0_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|Mux2~1_combout )) # (\A_SPW_TOP|tx_data|wr_ptr [1] & ((\A_SPW_TOP|tx_data|Mux2~3_combout 
// ))) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [0] & ( \A_SPW_TOP|tx_data|Mux2~0_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [1]) # (\A_SPW_TOP|tx_data|Mux2~2_combout ) ) ) ) # ( \A_SPW_TOP|tx_data|wr_ptr [0] & ( !\A_SPW_TOP|tx_data|Mux2~0_combout  & ( 
// (!\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|Mux2~1_combout )) # (\A_SPW_TOP|tx_data|wr_ptr [1] & ((\A_SPW_TOP|tx_data|Mux2~3_combout ))) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [0] & ( !\A_SPW_TOP|tx_data|Mux2~0_combout  & ( 
// (\A_SPW_TOP|tx_data|wr_ptr [1] & \A_SPW_TOP|tx_data|Mux2~2_combout ) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux2~1_combout ),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datac(!\A_SPW_TOP|tx_data|Mux2~2_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux2~3_combout ),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .dataf(!\A_SPW_TOP|tx_data|Mux2~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux2~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux2~4 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux2~4 .lut_mask = 64'h03034477CFCF4477;
defparam \A_SPW_TOP|tx_data|Mux2~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y15_N21
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector106~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector106~0_combout  = ( \A_SPW_TOP|tx_data|Mux2~20_combout  & ( (!\A_SPW_TOP|tx_data|Selector104~0_combout  & (((\A_SPW_TOP|tx_data|mem[11][6]~q )))) # (\A_SPW_TOP|tx_data|Selector104~0_combout  & 
// ((!\A_SPW_TOP|tx_data|state_data_write.00~q ) # ((\u0|write_data_fifo_tx|data_out [6])))) ) ) # ( !\A_SPW_TOP|tx_data|Mux2~20_combout  & ( (!\A_SPW_TOP|tx_data|Selector104~0_combout  & (((\A_SPW_TOP|tx_data|mem[11][6]~q )))) # 
// (\A_SPW_TOP|tx_data|Selector104~0_combout  & (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [6]))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\u0|write_data_fifo_tx|data_out [6]),
        .datac(!\A_SPW_TOP|tx_data|Selector104~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|mem[11][6]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector106~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector106~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector106~0 .lut_mask = 64'h01F101F10BFB0BFB;
defparam \A_SPW_TOP|tx_data|Selector106~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y15_N29
dffeas \A_SPW_TOP|tx_data|mem[11][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector106~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[11][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[11][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[11][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y15_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector97~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector97~0_combout  = ( \A_SPW_TOP|tx_data|mem[10][6]~q  & ( (!\A_SPW_TOP|tx_data|Selector95~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux2~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [6])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[10][6]~q  & ( (\A_SPW_TOP|tx_data|Selector95~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux2~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [6]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [6]),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|tx_data|Selector95~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[10][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector97~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector97~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector97~0 .lut_mask = 64'h00530053FF53FF53;
defparam \A_SPW_TOP|tx_data|Selector97~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y15_N11
dffeas \A_SPW_TOP|tx_data|mem[10][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector97~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[10][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[10][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[10][6] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y15_N27
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector142~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector142~0_combout  = ( \A_SPW_TOP|tx_data|mem[15][6]~q  & ( (!\A_SPW_TOP|tx_data|Selector140~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux2~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [6])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[15][6]~q  & ( (\A_SPW_TOP|tx_data|Selector140~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux2~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [6]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [6]),
        .datac(!\A_SPW_TOP|tx_data|Selector140~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[15][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector142~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector142~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector142~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|tx_data|Selector142~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y15_N8
dffeas \A_SPW_TOP|tx_data|mem[15][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector142~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[15][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[15][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[15][6] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y15_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector133~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector133~0_combout  = ( \A_SPW_TOP|tx_data|mem[14][6]~q  & ( (!\A_SPW_TOP|tx_data|Selector131~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux2~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [6])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[14][6]~q  & ( (\A_SPW_TOP|tx_data|Selector131~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux2~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [6]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [6]),
        .datac(!\A_SPW_TOP|tx_data|Selector131~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[14][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector133~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector133~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector133~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|tx_data|Selector133~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y15_N11
dffeas \A_SPW_TOP|tx_data|mem[14][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector133~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[14][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[14][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[14][6] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y15_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux2~7 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux2~7_combout  = ( \A_SPW_TOP|tx_data|mem[15][6]~q  & ( \A_SPW_TOP|tx_data|mem[14][6]~q  & ( ((!\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|mem[10][6]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|mem[11][6]~q 
// ))) # (\A_SPW_TOP|tx_data|wr_ptr [2]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[15][6]~q  & ( \A_SPW_TOP|tx_data|mem[14][6]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & ((!\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|mem[10][6]~q ))) # 
// (\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|mem[11][6]~q )))) # (\A_SPW_TOP|tx_data|wr_ptr [2] & (((!\A_SPW_TOP|tx_data|wr_ptr [0])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[15][6]~q  & ( !\A_SPW_TOP|tx_data|mem[14][6]~q  & ( 
// (!\A_SPW_TOP|tx_data|wr_ptr [2] & ((!\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|mem[10][6]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|mem[11][6]~q )))) # (\A_SPW_TOP|tx_data|wr_ptr [2] & (((\A_SPW_TOP|tx_data|wr_ptr [0])))) ) ) 
// ) # ( !\A_SPW_TOP|tx_data|mem[15][6]~q  & ( !\A_SPW_TOP|tx_data|mem[14][6]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & ((!\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|mem[10][6]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & 
// (\A_SPW_TOP|tx_data|mem[11][6]~q )))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datab(!\A_SPW_TOP|tx_data|mem[11][6]~q ),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datad(!\A_SPW_TOP|tx_data|mem[10][6]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[15][6]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[14][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux2~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux2~7 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux2~7 .lut_mask = 64'h02A207A752F257F7;
defparam \A_SPW_TOP|tx_data|Mux2~7 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y15_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector88~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector88~0_combout  = ( \A_SPW_TOP|tx_data|mem[9][6]~q  & ( (!\A_SPW_TOP|tx_data|Selector86~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux2~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [6])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[9][6]~q  & ( (\A_SPW_TOP|tx_data|Selector86~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux2~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [6]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector86~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [6]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[9][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector88~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector88~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector88~0 .lut_mask = 64'h04070407F4F7F4F7;
defparam \A_SPW_TOP|tx_data|Selector88~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y15_N35
dffeas \A_SPW_TOP|tx_data|mem[9][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector88~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[9][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[9][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[9][6] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y15_N45
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector115~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector115~0_combout  = ( \A_SPW_TOP|tx_data|mem[12][6]~q  & ( (!\A_SPW_TOP|tx_data|Selector113~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux2~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [6])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[12][6]~q  & ( (\A_SPW_TOP|tx_data|Selector113~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux2~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [6]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector113~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [6]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[12][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector115~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector115~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector115~0 .lut_mask = 64'h04070407F4F7F4F7;
defparam \A_SPW_TOP|tx_data|Selector115~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y15_N53
dffeas \A_SPW_TOP|tx_data|mem[12][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector115~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[12][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[12][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[12][6] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y15_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector79~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector79~0_combout  = ( \A_SPW_TOP|tx_data|mem[8][6]~q  & ( (!\A_SPW_TOP|tx_data|Selector77~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux2~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [6])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[8][6]~q  & ( (\A_SPW_TOP|tx_data|Selector77~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux2~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [6]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [6]),
        .datac(!\A_SPW_TOP|tx_data|Selector77~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[8][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector79~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector79~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector79~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|tx_data|Selector79~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y15_N56
dffeas \A_SPW_TOP|tx_data|mem[8][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector79~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[8][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[8][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[8][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y15_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector124~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector124~0_combout  = ( \A_SPW_TOP|tx_data|Selector122~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux2~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [6]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector122~0_combout  & ( \A_SPW_TOP|tx_data|mem[13][6]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [6]),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[13][6]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector122~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector124~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector124~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector124~0 .lut_mask = 64'h00FF00FF53535353;
defparam \A_SPW_TOP|tx_data|Selector124~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y15_N29
dffeas \A_SPW_TOP|tx_data|mem[13][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector124~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[13][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[13][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[13][6] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y15_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux2~5 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux2~5_combout  = ( \A_SPW_TOP|tx_data|mem[13][6]~q  & ( \A_SPW_TOP|tx_data|wr_ptr [2] & ( (\A_SPW_TOP|tx_data|mem[12][6]~q ) # (\A_SPW_TOP|tx_data|wr_ptr [0]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[13][6]~q  & ( \A_SPW_TOP|tx_data|wr_ptr 
// [2] & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & \A_SPW_TOP|tx_data|mem[12][6]~q ) ) ) ) # ( \A_SPW_TOP|tx_data|mem[13][6]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [2] & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|mem[8][6]~q ))) # 
// (\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|mem[9][6]~q )) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[13][6]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [2] & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|mem[8][6]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [0] 
// & (\A_SPW_TOP|tx_data|mem[9][6]~q )) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[9][6]~q ),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datac(!\A_SPW_TOP|tx_data|mem[12][6]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[8][6]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[13][6]~q ),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux2~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux2~5 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux2~5 .lut_mask = 64'h11DD11DD0C0C3F3F;
defparam \A_SPW_TOP|tx_data|Mux2~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y15_N9
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector277~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector277~0_combout  = ( \A_SPW_TOP|tx_data|mem[30][6]~q  & ( (!\A_SPW_TOP|tx_data|Selector275~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux2~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [6])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[30][6]~q  & ( (\A_SPW_TOP|tx_data|Selector275~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux2~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [6]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [6]),
        .datac(!\A_SPW_TOP|tx_data|Selector275~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[30][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector277~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector277~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector277~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|tx_data|Selector277~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y15_N20
dffeas \A_SPW_TOP|tx_data|mem[30][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector277~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[30][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[30][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[30][6] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y15_N39
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector250~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector250~0_combout  = ( \A_SPW_TOP|tx_data|Selector248~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux2~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [6]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector248~0_combout  & ( \A_SPW_TOP|tx_data|mem[27][6]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\u0|write_data_fifo_tx|data_out [6]),
        .datad(!\A_SPW_TOP|tx_data|mem[27][6]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector248~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector250~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector250~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector250~0 .lut_mask = 64'h00FF00FF47474747;
defparam \A_SPW_TOP|tx_data|Selector250~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y15_N23
dffeas \A_SPW_TOP|tx_data|mem[27][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector250~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[27][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[27][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[27][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y15_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector286~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector286~0_combout  = ( \A_SPW_TOP|tx_data|mem[31][6]~q  & ( (!\A_SPW_TOP|tx_data|Selector284~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux2~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [6])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[31][6]~q  & ( (\A_SPW_TOP|tx_data|Selector284~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux2~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [6]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [6]),
        .datac(!\A_SPW_TOP|tx_data|Selector284~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[31][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector286~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector286~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector286~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|tx_data|Selector286~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y15_N14
dffeas \A_SPW_TOP|tx_data|mem[31][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector286~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[31][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[31][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[31][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y15_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector241~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector241~0_combout  = ( \A_SPW_TOP|tx_data|mem[26][6]~q  & ( (!\A_SPW_TOP|tx_data|Selector239~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux2~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [6])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[26][6]~q  & ( (\A_SPW_TOP|tx_data|Selector239~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux2~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [6]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [6]),
        .datac(!\A_SPW_TOP|tx_data|Selector239~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[26][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector241~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector241~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector241~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|tx_data|Selector241~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y15_N53
dffeas \A_SPW_TOP|tx_data|mem[26][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector241~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[26][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[26][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[26][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y15_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux2~8 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux2~8_combout  = ( \A_SPW_TOP|tx_data|mem[31][6]~q  & ( \A_SPW_TOP|tx_data|mem[26][6]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & (((!\A_SPW_TOP|tx_data|wr_ptr [0]) # (\A_SPW_TOP|tx_data|mem[27][6]~q )))) # (\A_SPW_TOP|tx_data|wr_ptr [2] 
// & (((\A_SPW_TOP|tx_data|wr_ptr [0])) # (\A_SPW_TOP|tx_data|mem[30][6]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[31][6]~q  & ( \A_SPW_TOP|tx_data|mem[26][6]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & (((!\A_SPW_TOP|tx_data|wr_ptr [0]) # 
// (\A_SPW_TOP|tx_data|mem[27][6]~q )))) # (\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|mem[30][6]~q  & ((!\A_SPW_TOP|tx_data|wr_ptr [0])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[31][6]~q  & ( !\A_SPW_TOP|tx_data|mem[26][6]~q  & ( 
// (!\A_SPW_TOP|tx_data|wr_ptr [2] & (((\A_SPW_TOP|tx_data|mem[27][6]~q  & \A_SPW_TOP|tx_data|wr_ptr [0])))) # (\A_SPW_TOP|tx_data|wr_ptr [2] & (((\A_SPW_TOP|tx_data|wr_ptr [0])) # (\A_SPW_TOP|tx_data|mem[30][6]~q ))) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|mem[31][6]~q  & ( !\A_SPW_TOP|tx_data|mem[26][6]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & (((\A_SPW_TOP|tx_data|mem[27][6]~q  & \A_SPW_TOP|tx_data|wr_ptr [0])))) # (\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|mem[30][6]~q  & 
// ((!\A_SPW_TOP|tx_data|wr_ptr [0])))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[30][6]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[27][6]~q ),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datae(!\A_SPW_TOP|tx_data|mem[31][6]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[26][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux2~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux2~8 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux2~8 .lut_mask = 64'h0530053FF530F53F;
defparam \A_SPW_TOP|tx_data|Mux2~8 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y15_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector232~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector232~0_combout  = ( \A_SPW_TOP|tx_data|mem[25][6]~q  & ( (!\A_SPW_TOP|tx_data|Selector230~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux2~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [6])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[25][6]~q  & ( (\A_SPW_TOP|tx_data|Selector230~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux2~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [6]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [6]),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|tx_data|Selector230~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[25][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector232~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector232~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector232~0 .lut_mask = 64'h00530053FF53FF53;
defparam \A_SPW_TOP|tx_data|Selector232~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y15_N59
dffeas \A_SPW_TOP|tx_data|mem[25][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector232~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[25][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[25][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[25][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y15_N45
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector259~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector259~0_combout  = ( \A_SPW_TOP|tx_data|mem[28][6]~q  & ( (!\A_SPW_TOP|tx_data|Selector257~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux2~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [6])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[28][6]~q  & ( (\A_SPW_TOP|tx_data|Selector257~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux2~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [6]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [6]),
        .datac(!\A_SPW_TOP|tx_data|Selector257~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[28][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector259~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector259~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector259~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|tx_data|Selector259~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y15_N35
dffeas \A_SPW_TOP|tx_data|mem[28][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector259~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[28][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[28][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[28][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y15_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector268~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector268~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector266~0_combout  & ((\A_SPW_TOP|tx_data|mem[29][6]~q ))) # (\A_SPW_TOP|tx_data|Selector266~0_combout  & (\u0|write_data_fifo_tx|data_out 
// [6])) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector266~0_combout  & ((\A_SPW_TOP|tx_data|mem[29][6]~q ))) # (\A_SPW_TOP|tx_data|Selector266~0_combout  & (\A_SPW_TOP|tx_data|Mux2~20_combout )) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [6]),
        .datac(!\A_SPW_TOP|tx_data|mem[29][6]~q ),
        .datad(!\A_SPW_TOP|tx_data|Selector266~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector268~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector268~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector268~0 .lut_mask = 64'h0F550F550F330F33;
defparam \A_SPW_TOP|tx_data|Selector268~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y15_N26
dffeas \A_SPW_TOP|tx_data|mem[29][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector268~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[29][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[29][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[29][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y15_N39
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector223~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector223~0_combout  = ( \A_SPW_TOP|tx_data|mem[24][6]~q  & ( (!\A_SPW_TOP|tx_data|Selector221~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux2~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [6])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[24][6]~q  & ( (\A_SPW_TOP|tx_data|Selector221~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux2~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [6]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [6]),
        .datac(!\A_SPW_TOP|tx_data|Selector221~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[24][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector223~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector223~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector223~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|tx_data|Selector223~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y15_N50
dffeas \A_SPW_TOP|tx_data|mem[24][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector223~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[24][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[24][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[24][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y15_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux2~6 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux2~6_combout  = ( \A_SPW_TOP|tx_data|mem[29][6]~q  & ( \A_SPW_TOP|tx_data|mem[24][6]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & (((!\A_SPW_TOP|tx_data|wr_ptr [2]) # (\A_SPW_TOP|tx_data|mem[28][6]~q )))) # (\A_SPW_TOP|tx_data|wr_ptr [0] 
// & (((\A_SPW_TOP|tx_data|wr_ptr [2])) # (\A_SPW_TOP|tx_data|mem[25][6]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[29][6]~q  & ( \A_SPW_TOP|tx_data|mem[24][6]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & (((!\A_SPW_TOP|tx_data|wr_ptr [2]) # 
// (\A_SPW_TOP|tx_data|mem[28][6]~q )))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|mem[25][6]~q  & ((!\A_SPW_TOP|tx_data|wr_ptr [2])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[29][6]~q  & ( !\A_SPW_TOP|tx_data|mem[24][6]~q  & ( 
// (!\A_SPW_TOP|tx_data|wr_ptr [0] & (((\A_SPW_TOP|tx_data|mem[28][6]~q  & \A_SPW_TOP|tx_data|wr_ptr [2])))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & (((\A_SPW_TOP|tx_data|wr_ptr [2])) # (\A_SPW_TOP|tx_data|mem[25][6]~q ))) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|mem[29][6]~q  & ( !\A_SPW_TOP|tx_data|mem[24][6]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & (((\A_SPW_TOP|tx_data|mem[28][6]~q  & \A_SPW_TOP|tx_data|wr_ptr [2])))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|mem[25][6]~q  & 
// ((!\A_SPW_TOP|tx_data|wr_ptr [2])))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[25][6]~q ),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datac(!\A_SPW_TOP|tx_data|mem[28][6]~q ),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datae(!\A_SPW_TOP|tx_data|mem[29][6]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[24][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux2~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux2~6 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux2~6 .lut_mask = 64'h110C113FDD0CDD3F;
defparam \A_SPW_TOP|tx_data|Mux2~6 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y15_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux2~9 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux2~9_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [1] & ( \A_SPW_TOP|tx_data|Mux2~6_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|Mux2~7_combout )) # (\A_SPW_TOP|tx_data|wr_ptr [4] & ((\A_SPW_TOP|tx_data|Mux2~8_combout 
// ))) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( \A_SPW_TOP|tx_data|Mux2~6_combout  & ( (\A_SPW_TOP|tx_data|Mux2~5_combout ) # (\A_SPW_TOP|tx_data|wr_ptr [4]) ) ) ) # ( \A_SPW_TOP|tx_data|wr_ptr [1] & ( !\A_SPW_TOP|tx_data|Mux2~6_combout  & ( 
// (!\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|Mux2~7_combout )) # (\A_SPW_TOP|tx_data|wr_ptr [4] & ((\A_SPW_TOP|tx_data|Mux2~8_combout ))) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( !\A_SPW_TOP|tx_data|Mux2~6_combout  & ( 
// (!\A_SPW_TOP|tx_data|wr_ptr [4] & \A_SPW_TOP|tx_data|Mux2~5_combout ) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux2~7_combout ),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datac(!\A_SPW_TOP|tx_data|Mux2~5_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux2~8_combout ),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .dataf(!\A_SPW_TOP|tx_data|Mux2~6_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux2~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux2~9 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux2~9 .lut_mask = 64'h0C0C44773F3F4477;
defparam \A_SPW_TOP|tx_data|Mux2~9 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y15_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux2~20 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux2~20_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [5] & ( \A_SPW_TOP|tx_data|wr_ptr [3] & ( \A_SPW_TOP|tx_data|Mux2~19_combout  ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [5] & ( \A_SPW_TOP|tx_data|wr_ptr [3] & ( 
// \A_SPW_TOP|tx_data|Mux2~9_combout  ) ) ) # ( \A_SPW_TOP|tx_data|wr_ptr [5] & ( !\A_SPW_TOP|tx_data|wr_ptr [3] & ( \A_SPW_TOP|tx_data|Mux2~14_combout  ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [5] & ( !\A_SPW_TOP|tx_data|wr_ptr [3] & ( 
// \A_SPW_TOP|tx_data|Mux2~4_combout  ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux2~19_combout ),
        .datab(!\A_SPW_TOP|tx_data|Mux2~14_combout ),
        .datac(!\A_SPW_TOP|tx_data|Mux2~4_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux2~9_combout ),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux2~20 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux2~20 .lut_mask = 64'h0F0F333300FF5555;
defparam \A_SPW_TOP|tx_data|Mux2~20 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y15_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector61~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector61~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( \u0|write_data_fifo_tx|data_out [6] & ( (\A_SPW_TOP|tx_data|mem[6][6]~q ) # (\A_SPW_TOP|tx_data|Selector59~0_combout ) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( \u0|write_data_fifo_tx|data_out [6] & ( (!\A_SPW_TOP|tx_data|Selector59~0_combout  & ((\A_SPW_TOP|tx_data|mem[6][6]~q ))) # (\A_SPW_TOP|tx_data|Selector59~0_combout  & (\A_SPW_TOP|tx_data|Mux2~20_combout )) ) 
// ) ) # ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( !\u0|write_data_fifo_tx|data_out [6] & ( (!\A_SPW_TOP|tx_data|Selector59~0_combout  & \A_SPW_TOP|tx_data|mem[6][6]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( 
// !\u0|write_data_fifo_tx|data_out [6] & ( (!\A_SPW_TOP|tx_data|Selector59~0_combout  & ((\A_SPW_TOP|tx_data|mem[6][6]~q ))) # (\A_SPW_TOP|tx_data|Selector59~0_combout  & (\A_SPW_TOP|tx_data|Mux2~20_combout )) ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|tx_data|Mux2~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector59~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|mem[6][6]~q ),
        .datae(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .dataf(!\u0|write_data_fifo_tx|data_out [6]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector61~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector61~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector61~0 .lut_mask = 64'h03F300F003F30FFF;
defparam \A_SPW_TOP|tx_data|Selector61~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y15_N26
dffeas \A_SPW_TOP|tx_data|mem[6][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector61~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[6][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[6][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[6][6] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y15_N45
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux11~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux11~0_combout  = ( \A_SPW_TOP|tx_data|mem[2][6]~q  & ( \A_SPW_TOP|tx_data|mem[4][6]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & (((\A_SPW_TOP|tx_data|mem[0][6]~q ) # (\A_SPW_TOP|tx_data|rd_ptr [1])))) # (\A_SPW_TOP|tx_data|rd_ptr [2] & 
// (((!\A_SPW_TOP|tx_data|rd_ptr [1])) # (\A_SPW_TOP|tx_data|mem[6][6]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[2][6]~q  & ( \A_SPW_TOP|tx_data|mem[4][6]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & (((!\A_SPW_TOP|tx_data|rd_ptr [1] & 
// \A_SPW_TOP|tx_data|mem[0][6]~q )))) # (\A_SPW_TOP|tx_data|rd_ptr [2] & (((!\A_SPW_TOP|tx_data|rd_ptr [1])) # (\A_SPW_TOP|tx_data|mem[6][6]~q ))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[2][6]~q  & ( !\A_SPW_TOP|tx_data|mem[4][6]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr 
// [2] & (((\A_SPW_TOP|tx_data|mem[0][6]~q ) # (\A_SPW_TOP|tx_data|rd_ptr [1])))) # (\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[6][6]~q  & (\A_SPW_TOP|tx_data|rd_ptr [1]))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[2][6]~q  & ( 
// !\A_SPW_TOP|tx_data|mem[4][6]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & (((!\A_SPW_TOP|tx_data|rd_ptr [1] & \A_SPW_TOP|tx_data|mem[0][6]~q )))) # (\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[6][6]~q  & (\A_SPW_TOP|tx_data|rd_ptr [1]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .datab(!\A_SPW_TOP|tx_data|mem[6][6]~q ),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .datad(!\A_SPW_TOP|tx_data|mem[0][6]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[2][6]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[4][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux11~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux11~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux11~0 .lut_mask = 64'h01A10BAB51F15BFB;
defparam \A_SPW_TOP|tx_data|Mux11~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y15_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux11~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux11~1_combout  = ( \A_SPW_TOP|tx_data|rd_ptr [1] & ( \A_SPW_TOP|tx_data|mem[5][6]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[3][6]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [2] & ((\A_SPW_TOP|tx_data|mem[7][6]~q ))) ) ) 
// ) # ( !\A_SPW_TOP|tx_data|rd_ptr [1] & ( \A_SPW_TOP|tx_data|mem[5][6]~q  & ( (\A_SPW_TOP|tx_data|rd_ptr [2]) # (\A_SPW_TOP|tx_data|mem[1][6]~q ) ) ) ) # ( \A_SPW_TOP|tx_data|rd_ptr [1] & ( !\A_SPW_TOP|tx_data|mem[5][6]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr 
// [2] & (\A_SPW_TOP|tx_data|mem[3][6]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [2] & ((\A_SPW_TOP|tx_data|mem[7][6]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [1] & ( !\A_SPW_TOP|tx_data|mem[5][6]~q  & ( (\A_SPW_TOP|tx_data|mem[1][6]~q  & 
// !\A_SPW_TOP|tx_data|rd_ptr [2]) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[3][6]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[1][6]~q ),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .datad(!\A_SPW_TOP|tx_data|mem[7][6]~q ),
        .datae(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .dataf(!\A_SPW_TOP|tx_data|mem[5][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux11~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux11~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux11~1 .lut_mask = 64'h3030505F3F3F505F;
defparam \A_SPW_TOP|tx_data|Mux11~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y15_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux11~3 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux11~3_combout  = ( \A_SPW_TOP|tx_data|mem[19][6]~q  & ( \A_SPW_TOP|tx_data|mem[17][6]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [2]) # ((!\A_SPW_TOP|tx_data|rd_ptr [1] & ((\A_SPW_TOP|tx_data|mem[21][6]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [1] 
// & (\A_SPW_TOP|tx_data|mem[23][6]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[19][6]~q  & ( \A_SPW_TOP|tx_data|mem[17][6]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & (((!\A_SPW_TOP|tx_data|rd_ptr [1])))) # (\A_SPW_TOP|tx_data|rd_ptr [2] & 
// ((!\A_SPW_TOP|tx_data|rd_ptr [1] & ((\A_SPW_TOP|tx_data|mem[21][6]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|mem[23][6]~q )))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[19][6]~q  & ( !\A_SPW_TOP|tx_data|mem[17][6]~q  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [2] & (((\A_SPW_TOP|tx_data|rd_ptr [1])))) # (\A_SPW_TOP|tx_data|rd_ptr [2] & ((!\A_SPW_TOP|tx_data|rd_ptr [1] & ((\A_SPW_TOP|tx_data|mem[21][6]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|mem[23][6]~q )))) ) ) 
// ) # ( !\A_SPW_TOP|tx_data|mem[19][6]~q  & ( !\A_SPW_TOP|tx_data|mem[17][6]~q  & ( (\A_SPW_TOP|tx_data|rd_ptr [2] & ((!\A_SPW_TOP|tx_data|rd_ptr [1] & ((\A_SPW_TOP|tx_data|mem[21][6]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|mem[23][6]~q 
// )))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .datab(!\A_SPW_TOP|tx_data|mem[23][6]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[21][6]~q ),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .datae(!\A_SPW_TOP|tx_data|mem[19][6]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[17][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux11~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux11~3 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux11~3 .lut_mask = 64'h051105BBAF11AFBB;
defparam \A_SPW_TOP|tx_data|Mux11~3 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y15_N51
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux11~2 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux11~2_combout  = ( \A_SPW_TOP|tx_data|rd_ptr [1] & ( \A_SPW_TOP|tx_data|mem[22][6]~q  & ( (\A_SPW_TOP|tx_data|mem[18][6]~q ) # (\A_SPW_TOP|tx_data|rd_ptr [2]) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [1] & ( 
// \A_SPW_TOP|tx_data|mem[22][6]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[16][6]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [2] & ((\A_SPW_TOP|tx_data|mem[20][6]~q ))) ) ) ) # ( \A_SPW_TOP|tx_data|rd_ptr [1] & ( 
// !\A_SPW_TOP|tx_data|mem[22][6]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & \A_SPW_TOP|tx_data|mem[18][6]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [1] & ( !\A_SPW_TOP|tx_data|mem[22][6]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[16][6]~q 
// )) # (\A_SPW_TOP|tx_data|rd_ptr [2] & ((\A_SPW_TOP|tx_data|mem[20][6]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .datab(!\A_SPW_TOP|tx_data|mem[18][6]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[16][6]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[20][6]~q ),
        .datae(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .dataf(!\A_SPW_TOP|tx_data|mem[22][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux11~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux11~2 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux11~2 .lut_mask = 64'h0A5F22220A5F7777;
defparam \A_SPW_TOP|tx_data|Mux11~2 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y15_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux11~4 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux11~4_combout  = ( \A_SPW_TOP|tx_data|Mux11~3_combout  & ( \A_SPW_TOP|tx_data|Mux11~2_combout  & ( ((!\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|Mux11~0_combout )) # (\A_SPW_TOP|tx_data|rd_ptr [0] & 
// ((\A_SPW_TOP|tx_data|Mux11~1_combout )))) # (\A_SPW_TOP|tx_data|rd_ptr [4]) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux11~3_combout  & ( \A_SPW_TOP|tx_data|Mux11~2_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [0] & (((\A_SPW_TOP|tx_data|rd_ptr [4])) # 
// (\A_SPW_TOP|tx_data|Mux11~0_combout ))) # (\A_SPW_TOP|tx_data|rd_ptr [0] & (((\A_SPW_TOP|tx_data|Mux11~1_combout  & !\A_SPW_TOP|tx_data|rd_ptr [4])))) ) ) ) # ( \A_SPW_TOP|tx_data|Mux11~3_combout  & ( !\A_SPW_TOP|tx_data|Mux11~2_combout  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|Mux11~0_combout  & ((!\A_SPW_TOP|tx_data|rd_ptr [4])))) # (\A_SPW_TOP|tx_data|rd_ptr [0] & (((\A_SPW_TOP|tx_data|rd_ptr [4]) # (\A_SPW_TOP|tx_data|Mux11~1_combout )))) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|Mux11~3_combout  & ( !\A_SPW_TOP|tx_data|Mux11~2_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & ((!\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|Mux11~0_combout )) # (\A_SPW_TOP|tx_data|rd_ptr [0] & 
// ((\A_SPW_TOP|tx_data|Mux11~1_combout ))))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .datab(!\A_SPW_TOP|tx_data|Mux11~0_combout ),
        .datac(!\A_SPW_TOP|tx_data|Mux11~1_combout ),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .datae(!\A_SPW_TOP|tx_data|Mux11~3_combout ),
        .dataf(!\A_SPW_TOP|tx_data|Mux11~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux11~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux11~4 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux11~4 .lut_mask = 64'h2700275527AA27FF;
defparam \A_SPW_TOP|tx_data|Mux11~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y15_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux11~6 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux11~6_combout  = ( \A_SPW_TOP|tx_data|mem[39][6]~q  & ( \A_SPW_TOP|tx_data|rd_ptr [1] & ( (\A_SPW_TOP|tx_data|rd_ptr [2]) # (\A_SPW_TOP|tx_data|mem[35][6]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[39][6]~q  & ( \A_SPW_TOP|tx_data|rd_ptr 
// [1] & ( (\A_SPW_TOP|tx_data|mem[35][6]~q  & !\A_SPW_TOP|tx_data|rd_ptr [2]) ) ) ) # ( \A_SPW_TOP|tx_data|mem[39][6]~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [1] & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & ((\A_SPW_TOP|tx_data|mem[33][6]~q ))) # 
// (\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[37][6]~q )) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[39][6]~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [1] & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & ((\A_SPW_TOP|tx_data|mem[33][6]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr 
// [2] & (\A_SPW_TOP|tx_data|mem[37][6]~q )) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[35][6]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[37][6]~q ),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .datad(!\A_SPW_TOP|tx_data|mem[33][6]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[39][6]~q ),
        .dataf(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux11~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux11~6 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux11~6 .lut_mask = 64'h03F303F350505F5F;
defparam \A_SPW_TOP|tx_data|Mux11~6 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y15_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux11~8 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux11~8_combout  = ( \A_SPW_TOP|tx_data|mem[51][6]~q  & ( \A_SPW_TOP|tx_data|mem[49][6]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [2]) # ((!\A_SPW_TOP|tx_data|rd_ptr [1] & ((\A_SPW_TOP|tx_data|mem[53][6]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [1] 
// & (\A_SPW_TOP|tx_data|mem[55][6]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[51][6]~q  & ( \A_SPW_TOP|tx_data|mem[49][6]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [1] & (((!\A_SPW_TOP|tx_data|rd_ptr [2]) # (\A_SPW_TOP|tx_data|mem[53][6]~q )))) # 
// (\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|mem[55][6]~q  & (\A_SPW_TOP|tx_data|rd_ptr [2]))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[51][6]~q  & ( !\A_SPW_TOP|tx_data|mem[49][6]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [1] & (((\A_SPW_TOP|tx_data|rd_ptr [2] 
// & \A_SPW_TOP|tx_data|mem[53][6]~q )))) # (\A_SPW_TOP|tx_data|rd_ptr [1] & (((!\A_SPW_TOP|tx_data|rd_ptr [2])) # (\A_SPW_TOP|tx_data|mem[55][6]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[51][6]~q  & ( !\A_SPW_TOP|tx_data|mem[49][6]~q  & ( 
// (\A_SPW_TOP|tx_data|rd_ptr [2] & ((!\A_SPW_TOP|tx_data|rd_ptr [1] & ((\A_SPW_TOP|tx_data|mem[53][6]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|mem[55][6]~q )))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .datab(!\A_SPW_TOP|tx_data|mem[55][6]~q ),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .datad(!\A_SPW_TOP|tx_data|mem[53][6]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[51][6]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[49][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux11~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux11~8 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux11~8 .lut_mask = 64'h010B515BA1ABF1FB;
defparam \A_SPW_TOP|tx_data|Mux11~8 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y15_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux11~7 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux11~7_combout  = ( \A_SPW_TOP|tx_data|mem[50][6]~q  & ( \A_SPW_TOP|tx_data|rd_ptr [1] & ( (!\A_SPW_TOP|tx_data|rd_ptr [2]) # (\A_SPW_TOP|tx_data|mem[54][6]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[50][6]~q  & ( \A_SPW_TOP|tx_data|rd_ptr 
// [1] & ( (\A_SPW_TOP|tx_data|rd_ptr [2] & \A_SPW_TOP|tx_data|mem[54][6]~q ) ) ) ) # ( \A_SPW_TOP|tx_data|mem[50][6]~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [1] & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & ((\A_SPW_TOP|tx_data|mem[48][6]~q ))) # 
// (\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[52][6]~q )) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[50][6]~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [1] & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & ((\A_SPW_TOP|tx_data|mem[48][6]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr 
// [2] & (\A_SPW_TOP|tx_data|mem[52][6]~q )) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .datab(!\A_SPW_TOP|tx_data|mem[52][6]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[54][6]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[48][6]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[50][6]~q ),
        .dataf(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux11~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux11~7 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux11~7 .lut_mask = 64'h11BB11BB0505AFAF;
defparam \A_SPW_TOP|tx_data|Mux11~7 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y15_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux11~5 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux11~5_combout  = ( \A_SPW_TOP|tx_data|mem[38][6]~q  & ( \A_SPW_TOP|tx_data|mem[36][6]~q  & ( ((!\A_SPW_TOP|tx_data|rd_ptr [1] & ((\A_SPW_TOP|tx_data|mem[32][6]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|mem[34][6]~q 
// ))) # (\A_SPW_TOP|tx_data|rd_ptr [2]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[38][6]~q  & ( \A_SPW_TOP|tx_data|mem[36][6]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & ((!\A_SPW_TOP|tx_data|rd_ptr [1] & ((\A_SPW_TOP|tx_data|mem[32][6]~q ))) # 
// (\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|mem[34][6]~q )))) # (\A_SPW_TOP|tx_data|rd_ptr [2] & (((!\A_SPW_TOP|tx_data|rd_ptr [1])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[38][6]~q  & ( !\A_SPW_TOP|tx_data|mem[36][6]~q  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [2] & ((!\A_SPW_TOP|tx_data|rd_ptr [1] & ((\A_SPW_TOP|tx_data|mem[32][6]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|mem[34][6]~q )))) # (\A_SPW_TOP|tx_data|rd_ptr [2] & (((\A_SPW_TOP|tx_data|rd_ptr [1])))) ) ) 
// ) # ( !\A_SPW_TOP|tx_data|mem[38][6]~q  & ( !\A_SPW_TOP|tx_data|mem[36][6]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & ((!\A_SPW_TOP|tx_data|rd_ptr [1] & ((\A_SPW_TOP|tx_data|mem[32][6]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [1] & 
// (\A_SPW_TOP|tx_data|mem[34][6]~q )))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .datab(!\A_SPW_TOP|tx_data|mem[34][6]~q ),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .datad(!\A_SPW_TOP|tx_data|mem[32][6]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[38][6]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[36][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux11~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux11~5 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux11~5 .lut_mask = 64'h02A207A752F257F7;
defparam \A_SPW_TOP|tx_data|Mux11~5 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y15_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux11~9 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux11~9_combout  = ( \A_SPW_TOP|tx_data|rd_ptr [0] & ( \A_SPW_TOP|tx_data|rd_ptr [4] & ( \A_SPW_TOP|tx_data|Mux11~8_combout  ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [0] & ( \A_SPW_TOP|tx_data|rd_ptr [4] & ( 
// \A_SPW_TOP|tx_data|Mux11~7_combout  ) ) ) # ( \A_SPW_TOP|tx_data|rd_ptr [0] & ( !\A_SPW_TOP|tx_data|rd_ptr [4] & ( \A_SPW_TOP|tx_data|Mux11~6_combout  ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [0] & ( !\A_SPW_TOP|tx_data|rd_ptr [4] & ( 
// \A_SPW_TOP|tx_data|Mux11~5_combout  ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux11~6_combout ),
        .datab(!\A_SPW_TOP|tx_data|Mux11~8_combout ),
        .datac(!\A_SPW_TOP|tx_data|Mux11~7_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux11~5_combout ),
        .datae(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .dataf(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux11~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux11~9 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux11~9 .lut_mask = 64'h00FF55550F0F3333;
defparam \A_SPW_TOP|tx_data|Mux11~9 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y15_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux11~11 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux11~11_combout  = ( \A_SPW_TOP|tx_data|mem[13][6]~q  & ( \A_SPW_TOP|tx_data|mem[15][6]~q  & ( ((!\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|mem[12][6]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [1] & ((\A_SPW_TOP|tx_data|mem[14][6]~q 
// )))) # (\A_SPW_TOP|tx_data|rd_ptr [0]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[13][6]~q  & ( \A_SPW_TOP|tx_data|mem[15][6]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|mem[12][6]~q  & ((!\A_SPW_TOP|tx_data|rd_ptr [0])))) # 
// (\A_SPW_TOP|tx_data|rd_ptr [1] & (((\A_SPW_TOP|tx_data|rd_ptr [0]) # (\A_SPW_TOP|tx_data|mem[14][6]~q )))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[13][6]~q  & ( !\A_SPW_TOP|tx_data|mem[15][6]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [1] & (((\A_SPW_TOP|tx_data|rd_ptr 
// [0])) # (\A_SPW_TOP|tx_data|mem[12][6]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [1] & (((\A_SPW_TOP|tx_data|mem[14][6]~q  & !\A_SPW_TOP|tx_data|rd_ptr [0])))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[13][6]~q  & ( !\A_SPW_TOP|tx_data|mem[15][6]~q  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [0] & ((!\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|mem[12][6]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [1] & ((\A_SPW_TOP|tx_data|mem[14][6]~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[12][6]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[14][6]~q ),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .datae(!\A_SPW_TOP|tx_data|mem[13][6]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[15][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux11~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux11~11 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux11~11 .lut_mask = 64'h530053F0530F53FF;
defparam \A_SPW_TOP|tx_data|Mux11~11 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y15_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux11~13 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux11~13_combout  = ( \A_SPW_TOP|tx_data|mem[30][6]~q  & ( \A_SPW_TOP|tx_data|mem[28][6]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [0]) # ((!\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|mem[29][6]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [1] & 
// ((\A_SPW_TOP|tx_data|mem[31][6]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[30][6]~q  & ( \A_SPW_TOP|tx_data|mem[28][6]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [0] & (((!\A_SPW_TOP|tx_data|rd_ptr [1])))) # (\A_SPW_TOP|tx_data|rd_ptr [0] & 
// ((!\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|mem[29][6]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [1] & ((\A_SPW_TOP|tx_data|mem[31][6]~q ))))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[30][6]~q  & ( !\A_SPW_TOP|tx_data|mem[28][6]~q  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [0] & (((\A_SPW_TOP|tx_data|rd_ptr [1])))) # (\A_SPW_TOP|tx_data|rd_ptr [0] & ((!\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|mem[29][6]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [1] & ((\A_SPW_TOP|tx_data|mem[31][6]~q ))))) ) ) 
// ) # ( !\A_SPW_TOP|tx_data|mem[30][6]~q  & ( !\A_SPW_TOP|tx_data|mem[28][6]~q  & ( (\A_SPW_TOP|tx_data|rd_ptr [0] & ((!\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|mem[29][6]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [1] & ((\A_SPW_TOP|tx_data|mem[31][6]~q 
// ))))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[29][6]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[31][6]~q ),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .datae(!\A_SPW_TOP|tx_data|mem[30][6]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[28][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux11~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux11~13 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux11~13 .lut_mask = 64'h050305F3F503F5F3;
defparam \A_SPW_TOP|tx_data|Mux11~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y15_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux11~12 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux11~12_combout  = ( \A_SPW_TOP|tx_data|rd_ptr [0] & ( \A_SPW_TOP|tx_data|mem[26][6]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|mem[25][6]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [1] & ((\A_SPW_TOP|tx_data|mem[27][6]~q ))) 
// ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [0] & ( \A_SPW_TOP|tx_data|mem[26][6]~q  & ( (\A_SPW_TOP|tx_data|rd_ptr [1]) # (\A_SPW_TOP|tx_data|mem[24][6]~q ) ) ) ) # ( \A_SPW_TOP|tx_data|rd_ptr [0] & ( !\A_SPW_TOP|tx_data|mem[26][6]~q  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|mem[25][6]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [1] & ((\A_SPW_TOP|tx_data|mem[27][6]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [0] & ( !\A_SPW_TOP|tx_data|mem[26][6]~q  & ( 
// (\A_SPW_TOP|tx_data|mem[24][6]~q  & !\A_SPW_TOP|tx_data|rd_ptr [1]) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[24][6]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[25][6]~q ),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .datad(!\A_SPW_TOP|tx_data|mem[27][6]~q ),
        .datae(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .dataf(!\A_SPW_TOP|tx_data|mem[26][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux11~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux11~12 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux11~12 .lut_mask = 64'h5050303F5F5F303F;
defparam \A_SPW_TOP|tx_data|Mux11~12 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y15_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux11~10 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux11~10_combout  = ( \A_SPW_TOP|tx_data|mem[8][6]~q  & ( \A_SPW_TOP|tx_data|mem[10][6]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [0]) # ((!\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|mem[9][6]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [1] & 
// ((\A_SPW_TOP|tx_data|mem[11][6]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[8][6]~q  & ( \A_SPW_TOP|tx_data|mem[10][6]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [0] & (((\A_SPW_TOP|tx_data|rd_ptr [1])))) # (\A_SPW_TOP|tx_data|rd_ptr [0] & 
// ((!\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|mem[9][6]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [1] & ((\A_SPW_TOP|tx_data|mem[11][6]~q ))))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[8][6]~q  & ( !\A_SPW_TOP|tx_data|mem[10][6]~q  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [0] & (((!\A_SPW_TOP|tx_data|rd_ptr [1])))) # (\A_SPW_TOP|tx_data|rd_ptr [0] & ((!\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|mem[9][6]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [1] & ((\A_SPW_TOP|tx_data|mem[11][6]~q ))))) ) ) 
// ) # ( !\A_SPW_TOP|tx_data|mem[8][6]~q  & ( !\A_SPW_TOP|tx_data|mem[10][6]~q  & ( (\A_SPW_TOP|tx_data|rd_ptr [0] & ((!\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|mem[9][6]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [1] & ((\A_SPW_TOP|tx_data|mem[11][6]~q 
// ))))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[9][6]~q ),
        .datab(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .datad(!\A_SPW_TOP|tx_data|mem[11][6]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[8][6]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[10][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux11~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux11~10 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux11~10 .lut_mask = 64'h1013D0D31C1FDCDF;
defparam \A_SPW_TOP|tx_data|Mux11~10 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y15_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux11~14 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux11~14_combout  = ( \A_SPW_TOP|tx_data|Mux11~10_combout  & ( \A_SPW_TOP|tx_data|rd_ptr [4] & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & ((\A_SPW_TOP|tx_data|Mux11~12_combout ))) # (\A_SPW_TOP|tx_data|rd_ptr [2] & 
// (\A_SPW_TOP|tx_data|Mux11~13_combout )) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux11~10_combout  & ( \A_SPW_TOP|tx_data|rd_ptr [4] & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & ((\A_SPW_TOP|tx_data|Mux11~12_combout ))) # (\A_SPW_TOP|tx_data|rd_ptr [2] & 
// (\A_SPW_TOP|tx_data|Mux11~13_combout )) ) ) ) # ( \A_SPW_TOP|tx_data|Mux11~10_combout  & ( !\A_SPW_TOP|tx_data|rd_ptr [4] & ( (!\A_SPW_TOP|tx_data|rd_ptr [2]) # (\A_SPW_TOP|tx_data|Mux11~11_combout ) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux11~10_combout  & ( 
// !\A_SPW_TOP|tx_data|rd_ptr [4] & ( (\A_SPW_TOP|tx_data|Mux11~11_combout  & \A_SPW_TOP|tx_data|rd_ptr [2]) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux11~11_combout ),
        .datab(!\A_SPW_TOP|tx_data|Mux11~13_combout ),
        .datac(!\A_SPW_TOP|tx_data|Mux11~12_combout ),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .datae(!\A_SPW_TOP|tx_data|Mux11~10_combout ),
        .dataf(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux11~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux11~14 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux11~14 .lut_mask = 64'h0055FF550F330F33;
defparam \A_SPW_TOP|tx_data|Mux11~14 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y14_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux11~17 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux11~17_combout  = ( \A_SPW_TOP|tx_data|mem[58][6]~q  & ( \A_SPW_TOP|tx_data|mem[62][6]~q  & ( ((!\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[42][6]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [2] & ((\A_SPW_TOP|tx_data|mem[46][6]~q 
// )))) # (\A_SPW_TOP|tx_data|rd_ptr [4]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[58][6]~q  & ( \A_SPW_TOP|tx_data|mem[62][6]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & ((!\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[42][6]~q )) # 
// (\A_SPW_TOP|tx_data|rd_ptr [2] & ((\A_SPW_TOP|tx_data|mem[46][6]~q ))))) # (\A_SPW_TOP|tx_data|rd_ptr [4] & (((\A_SPW_TOP|tx_data|rd_ptr [2])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[58][6]~q  & ( !\A_SPW_TOP|tx_data|mem[62][6]~q  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [4] & ((!\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[42][6]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [2] & ((\A_SPW_TOP|tx_data|mem[46][6]~q ))))) # (\A_SPW_TOP|tx_data|rd_ptr [4] & (((!\A_SPW_TOP|tx_data|rd_ptr [2])))) ) 
// ) ) # ( !\A_SPW_TOP|tx_data|mem[58][6]~q  & ( !\A_SPW_TOP|tx_data|mem[62][6]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & ((!\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[42][6]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [2] & 
// ((\A_SPW_TOP|tx_data|mem[46][6]~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[42][6]~q ),
        .datab(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .datad(!\A_SPW_TOP|tx_data|mem[46][6]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[58][6]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[62][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux11~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux11~17 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux11~17 .lut_mask = 64'h404C707C434F737F;
defparam \A_SPW_TOP|tx_data|Mux11~17 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y14_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux11~18 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux11~18_combout  = ( \A_SPW_TOP|tx_data|mem[59][6]~q  & ( \A_SPW_TOP|tx_data|mem[63][6]~q  & ( ((!\A_SPW_TOP|tx_data|rd_ptr [2] & ((\A_SPW_TOP|tx_data|mem[43][6]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[47][6]~q 
// ))) # (\A_SPW_TOP|tx_data|rd_ptr [4]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[59][6]~q  & ( \A_SPW_TOP|tx_data|mem[63][6]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & (!\A_SPW_TOP|tx_data|rd_ptr [4] & ((\A_SPW_TOP|tx_data|mem[43][6]~q )))) # 
// (\A_SPW_TOP|tx_data|rd_ptr [2] & (((\A_SPW_TOP|tx_data|mem[47][6]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [4]))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[59][6]~q  & ( !\A_SPW_TOP|tx_data|mem[63][6]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & 
// (((\A_SPW_TOP|tx_data|mem[43][6]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [4]))) # (\A_SPW_TOP|tx_data|rd_ptr [2] & (!\A_SPW_TOP|tx_data|rd_ptr [4] & (\A_SPW_TOP|tx_data|mem[47][6]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[59][6]~q  & ( 
// !\A_SPW_TOP|tx_data|mem[63][6]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & ((!\A_SPW_TOP|tx_data|rd_ptr [2] & ((\A_SPW_TOP|tx_data|mem[43][6]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[47][6]~q )))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .datab(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .datac(!\A_SPW_TOP|tx_data|mem[47][6]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[43][6]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[59][6]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[63][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux11~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux11~18 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux11~18 .lut_mask = 64'h048C26AE159D37BF;
defparam \A_SPW_TOP|tx_data|Mux11~18 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y14_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux11~15 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux11~15_combout  = ( \A_SPW_TOP|tx_data|mem[44][6]~q  & ( \A_SPW_TOP|tx_data|rd_ptr [2] & ( (!\A_SPW_TOP|tx_data|rd_ptr [4]) # (\A_SPW_TOP|tx_data|mem[60][6]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[44][6]~q  & ( \A_SPW_TOP|tx_data|rd_ptr 
// [2] & ( (\A_SPW_TOP|tx_data|mem[60][6]~q  & \A_SPW_TOP|tx_data|rd_ptr [4]) ) ) ) # ( \A_SPW_TOP|tx_data|mem[44][6]~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [2] & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & (\A_SPW_TOP|tx_data|mem[40][6]~q )) # (\A_SPW_TOP|tx_data|rd_ptr 
// [4] & ((\A_SPW_TOP|tx_data|mem[56][6]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[44][6]~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [2] & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & (\A_SPW_TOP|tx_data|mem[40][6]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [4] & 
// ((\A_SPW_TOP|tx_data|mem[56][6]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[40][6]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[56][6]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[60][6]~q ),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .datae(!\A_SPW_TOP|tx_data|mem[44][6]~q ),
        .dataf(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux11~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux11~15 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux11~15 .lut_mask = 64'h55335533000FFF0F;
defparam \A_SPW_TOP|tx_data|Mux11~15 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y14_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux11~16 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux11~16_combout  = ( \A_SPW_TOP|tx_data|mem[45][6]~q  & ( \A_SPW_TOP|tx_data|rd_ptr [4] & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[57][6]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [2] & ((\A_SPW_TOP|tx_data|mem[61][6]~q ))) 
// ) ) ) # ( !\A_SPW_TOP|tx_data|mem[45][6]~q  & ( \A_SPW_TOP|tx_data|rd_ptr [4] & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|mem[57][6]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [2] & ((\A_SPW_TOP|tx_data|mem[61][6]~q ))) ) ) ) # ( 
// \A_SPW_TOP|tx_data|mem[45][6]~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [4] & ( (\A_SPW_TOP|tx_data|mem[41][6]~q ) # (\A_SPW_TOP|tx_data|rd_ptr [2]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[45][6]~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [4] & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] 
// & \A_SPW_TOP|tx_data|mem[41][6]~q ) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .datab(!\A_SPW_TOP|tx_data|mem[57][6]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[41][6]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[61][6]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[45][6]~q ),
        .dataf(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux11~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux11~16 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux11~16 .lut_mask = 64'h0A0A5F5F22772277;
defparam \A_SPW_TOP|tx_data|Mux11~16 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y14_N27
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux11~19 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux11~19_combout  = ( \A_SPW_TOP|tx_data|Mux11~15_combout  & ( \A_SPW_TOP|tx_data|Mux11~16_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [1]) # ((!\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|Mux11~17_combout )) # 
// (\A_SPW_TOP|tx_data|rd_ptr [0] & ((\A_SPW_TOP|tx_data|Mux11~18_combout )))) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux11~15_combout  & ( \A_SPW_TOP|tx_data|Mux11~16_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [1] & (((\A_SPW_TOP|tx_data|rd_ptr [0])))) # 
// (\A_SPW_TOP|tx_data|rd_ptr [1] & ((!\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|Mux11~17_combout )) # (\A_SPW_TOP|tx_data|rd_ptr [0] & ((\A_SPW_TOP|tx_data|Mux11~18_combout ))))) ) ) ) # ( \A_SPW_TOP|tx_data|Mux11~15_combout  & ( 
// !\A_SPW_TOP|tx_data|Mux11~16_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [1] & (((!\A_SPW_TOP|tx_data|rd_ptr [0])))) # (\A_SPW_TOP|tx_data|rd_ptr [1] & ((!\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|Mux11~17_combout )) # (\A_SPW_TOP|tx_data|rd_ptr 
// [0] & ((\A_SPW_TOP|tx_data|Mux11~18_combout ))))) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux11~15_combout  & ( !\A_SPW_TOP|tx_data|Mux11~16_combout  & ( (\A_SPW_TOP|tx_data|rd_ptr [1] & ((!\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|Mux11~17_combout )) # 
// (\A_SPW_TOP|tx_data|rd_ptr [0] & ((\A_SPW_TOP|tx_data|Mux11~18_combout ))))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .datab(!\A_SPW_TOP|tx_data|Mux11~17_combout ),
        .datac(!\A_SPW_TOP|tx_data|Mux11~18_combout ),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .datae(!\A_SPW_TOP|tx_data|Mux11~15_combout ),
        .dataf(!\A_SPW_TOP|tx_data|Mux11~16_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux11~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux11~19 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux11~19 .lut_mask = 64'h1105BB0511AFBBAF;
defparam \A_SPW_TOP|tx_data|Mux11~19 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y14_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux11~20 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux11~20_combout  = ( \A_SPW_TOP|tx_data|Mux11~19_combout  & ( \A_SPW_TOP|tx_data|rd_ptr [5] & ( (\A_SPW_TOP|tx_data|rd_ptr [3]) # (\A_SPW_TOP|tx_data|Mux11~9_combout ) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux11~19_combout  & ( 
// \A_SPW_TOP|tx_data|rd_ptr [5] & ( (\A_SPW_TOP|tx_data|Mux11~9_combout  & !\A_SPW_TOP|tx_data|rd_ptr [3]) ) ) ) # ( \A_SPW_TOP|tx_data|Mux11~19_combout  & ( !\A_SPW_TOP|tx_data|rd_ptr [5] & ( (!\A_SPW_TOP|tx_data|rd_ptr [3] & 
// (\A_SPW_TOP|tx_data|Mux11~4_combout )) # (\A_SPW_TOP|tx_data|rd_ptr [3] & ((\A_SPW_TOP|tx_data|Mux11~14_combout ))) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux11~19_combout  & ( !\A_SPW_TOP|tx_data|rd_ptr [5] & ( (!\A_SPW_TOP|tx_data|rd_ptr [3] & 
// (\A_SPW_TOP|tx_data|Mux11~4_combout )) # (\A_SPW_TOP|tx_data|rd_ptr [3] & ((\A_SPW_TOP|tx_data|Mux11~14_combout ))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux11~4_combout ),
        .datab(!\A_SPW_TOP|tx_data|Mux11~9_combout ),
        .datac(!\A_SPW_TOP|tx_data|Mux11~14_combout ),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [3]),
        .datae(!\A_SPW_TOP|tx_data|Mux11~19_combout ),
        .dataf(!\A_SPW_TOP|tx_data|rd_ptr [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux11~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux11~20 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux11~20 .lut_mask = 64'h550F550F330033FF;
defparam \A_SPW_TOP|tx_data|Mux11~20 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y14_N56
dffeas \A_SPW_TOP|tx_data|data_out[6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|tx_data|Mux11~20_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|data_out [6]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|data_out[6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|data_out[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X53_Y7_N18
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector34~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector34~0_combout  = ( \A_SPW_TOP|SPW|TX|tx_data_in_0 [6] & ( (!\A_SPW_TOP|SPW|TX|Selector40~0_combout ) # ((\A_SPW_TOP|SPW|TX|Selector32~0_combout  & \A_SPW_TOP|tx_data|data_out [6])) ) ) # ( !\A_SPW_TOP|SPW|TX|tx_data_in_0 [6] & ( 
// (\A_SPW_TOP|SPW|TX|Selector32~0_combout  & \A_SPW_TOP|tx_data|data_out [6]) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|Selector40~0_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|Selector32~0_combout ),
        .datac(!\A_SPW_TOP|tx_data|data_out [6]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|tx_data_in_0 [6]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector34~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector34~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector34~0 .lut_mask = 64'h03030303ABABABAB;
defparam \A_SPW_TOP|SPW|TX|Selector34~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X53_Y7_N17
dffeas \A_SPW_TOP|SPW|TX|tx_data_in_0[6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|Selector34~0_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|tx_data_in_0 [6]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_data_in_0[6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|tx_data_in_0[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y14_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_payload~5 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_payload~5_combout  = ( \u0|hps_0|fpga_interfaces|h2f_WDATA [5] & ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_WDATA [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_010|src_payload~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_payload~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_payload~5 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_payload~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y14_N32
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_010|src_payload~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[5] .power_up = "low";
// synopsys translate_on

// Location: FF_X30_Y14_N44
dffeas \u0|write_data_fifo_tx|data_out[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [5]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|write_data_fifo_tx|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|write_data_fifo_tx|data_out [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|write_data_fifo_tx|data_out[5] .is_wysiwyg = "true";
defparam \u0|write_data_fifo_tx|data_out[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y14_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector242~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector242~0_combout  = ( \A_SPW_TOP|tx_data|mem[26][5]~q  & ( (!\A_SPW_TOP|tx_data|Selector239~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux3~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [5]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[26][5]~q  & ( (\A_SPW_TOP|tx_data|Selector239~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux3~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [5])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [5]),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector239~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[26][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector242~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector242~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector242~0 .lut_mask = 64'h010D010DF1FDF1FD;
defparam \A_SPW_TOP|tx_data|Selector242~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y14_N35
dffeas \A_SPW_TOP|tx_data|mem[26][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector242~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[26][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[26][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[26][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y14_N15
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector170~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector170~0_combout  = ( \A_SPW_TOP|tx_data|mem[18][5]~q  & ( (!\A_SPW_TOP|tx_data|Selector167~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux3~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [5]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[18][5]~q  & ( (\A_SPW_TOP|tx_data|Selector167~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux3~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [5])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [5]),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .datad(!\A_SPW_TOP|tx_data|Selector167~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[18][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector170~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector170~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector170~0 .lut_mask = 64'h001D001DFF1DFF1D;
defparam \A_SPW_TOP|tx_data|Selector170~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y14_N39
cyclonev_lcell_comb \A_SPW_TOP|tx_data|mem[18][5]~feeder (
// Equation(s):
// \A_SPW_TOP|tx_data|mem[18][5]~feeder_combout  = ( \A_SPW_TOP|tx_data|Selector170~0_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector170~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|mem[18][5]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[18][5]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|mem[18][5]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|tx_data|mem[18][5]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y14_N41
dffeas \A_SPW_TOP|tx_data|mem[18][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|tx_data|mem[18][5]~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[18][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[18][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[18][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y14_N21
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector458~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector458~0_combout  = ( \A_SPW_TOP|tx_data|mem[50][5]~q  & ( (!\A_SPW_TOP|tx_data|Selector455~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux3~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [5]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[50][5]~q  & ( (\A_SPW_TOP|tx_data|Selector455~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux3~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [5])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [5]),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .datad(!\A_SPW_TOP|tx_data|Selector455~0_combout ),
        .datae(!\A_SPW_TOP|tx_data|mem[50][5]~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector458~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector458~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector458~0 .lut_mask = 64'h001DFF1D001DFF1D;
defparam \A_SPW_TOP|tx_data|Selector458~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y14_N29
dffeas \A_SPW_TOP|tx_data|mem[50][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector458~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[50][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[50][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[50][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y14_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector530~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector530~0_combout  = ( \A_SPW_TOP|tx_data|Selector527~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux3~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\u0|write_data_fifo_tx|data_out [5])) ) ) # ( !\A_SPW_TOP|tx_data|Selector527~0_combout  & ( \A_SPW_TOP|tx_data|mem[58][5]~q  ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [5]),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[58][5]~q ),
        .datad(!\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector527~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector530~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector530~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector530~0 .lut_mask = 64'h0F0F0F0F11DD11DD;
defparam \A_SPW_TOP|tx_data|Selector530~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y14_N20
dffeas \A_SPW_TOP|tx_data|mem[58][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector530~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[58][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[58][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[58][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y14_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux3~12 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux3~12_combout  = ( \A_SPW_TOP|tx_data|mem[50][5]~q  & ( \A_SPW_TOP|tx_data|mem[58][5]~q  & ( ((!\A_SPW_TOP|tx_data|wr_ptr [3] & ((\A_SPW_TOP|tx_data|mem[18][5]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [3] & (\A_SPW_TOP|tx_data|mem[26][5]~q 
// ))) # (\A_SPW_TOP|tx_data|wr_ptr [5]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[50][5]~q  & ( \A_SPW_TOP|tx_data|mem[58][5]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [3] & (((!\A_SPW_TOP|tx_data|wr_ptr [5] & \A_SPW_TOP|tx_data|mem[18][5]~q )))) # 
// (\A_SPW_TOP|tx_data|wr_ptr [3] & (((\A_SPW_TOP|tx_data|wr_ptr [5])) # (\A_SPW_TOP|tx_data|mem[26][5]~q ))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[50][5]~q  & ( !\A_SPW_TOP|tx_data|mem[58][5]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [3] & 
// (((\A_SPW_TOP|tx_data|mem[18][5]~q ) # (\A_SPW_TOP|tx_data|wr_ptr [5])))) # (\A_SPW_TOP|tx_data|wr_ptr [3] & (\A_SPW_TOP|tx_data|mem[26][5]~q  & (!\A_SPW_TOP|tx_data|wr_ptr [5]))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[50][5]~q  & ( 
// !\A_SPW_TOP|tx_data|mem[58][5]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [5] & ((!\A_SPW_TOP|tx_data|wr_ptr [3] & ((\A_SPW_TOP|tx_data|mem[18][5]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [3] & (\A_SPW_TOP|tx_data|mem[26][5]~q )))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[26][5]~q ),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datad(!\A_SPW_TOP|tx_data|mem[18][5]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[50][5]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[58][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux3~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux3~12 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux3~12 .lut_mask = 64'h10D01CDC13D31FDF;
defparam \A_SPW_TOP|tx_data|Mux3~12 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y14_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector26~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector26~0_combout  = ( \A_SPW_TOP|tx_data|mem[2][5]~q  & ( (!\A_SPW_TOP|tx_data|Selector23~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux3~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [5])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[2][5]~q  & ( (\A_SPW_TOP|tx_data|Selector23~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux3~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [5]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector23~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [5]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[2][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector26~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector26~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector26~0 .lut_mask = 64'h04070407F4F7F4F7;
defparam \A_SPW_TOP|tx_data|Selector26~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y14_N35
dffeas \A_SPW_TOP|tx_data|mem[2][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector26~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[2][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[2][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[2][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y14_N51
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector314~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector314~0_combout  = ( \A_SPW_TOP|tx_data|mem[34][5]~q  & ( \A_SPW_TOP|tx_data|Mux3~20_combout  & ( (!\A_SPW_TOP|tx_data|Selector311~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q ) # (\u0|write_data_fifo_tx|data_out 
// [5])) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[34][5]~q  & ( \A_SPW_TOP|tx_data|Mux3~20_combout  & ( (\A_SPW_TOP|tx_data|Selector311~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q ) # (\u0|write_data_fifo_tx|data_out [5]))) ) ) ) # ( 
// \A_SPW_TOP|tx_data|mem[34][5]~q  & ( !\A_SPW_TOP|tx_data|Mux3~20_combout  & ( (!\A_SPW_TOP|tx_data|Selector311~0_combout ) # ((\u0|write_data_fifo_tx|data_out [5] & \A_SPW_TOP|tx_data|state_data_write.00~q )) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[34][5]~q  & 
// ( !\A_SPW_TOP|tx_data|Mux3~20_combout  & ( (\A_SPW_TOP|tx_data|Selector311~0_combout  & (\u0|write_data_fifo_tx|data_out [5] & \A_SPW_TOP|tx_data|state_data_write.00~q )) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Selector311~0_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [5]),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|tx_data|mem[34][5]~q ),
        .dataf(!\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector314~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector314~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector314~0 .lut_mask = 64'h0101ABAB5151FBFB;
defparam \A_SPW_TOP|tx_data|Selector314~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y14_N23
dffeas \A_SPW_TOP|tx_data|mem[34][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector314~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[34][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[34][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[34][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y14_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector386~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector386~0_combout  = ( \u0|write_data_fifo_tx|data_out [5] & ( \A_SPW_TOP|tx_data|mem[42][5]~q  & ( ((!\A_SPW_TOP|tx_data|Selector383~0_combout ) # (\A_SPW_TOP|tx_data|Mux3~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q ) 
// ) ) ) # ( !\u0|write_data_fifo_tx|data_out [5] & ( \A_SPW_TOP|tx_data|mem[42][5]~q  & ( (!\A_SPW_TOP|tx_data|Selector383~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & \A_SPW_TOP|tx_data|Mux3~20_combout )) ) ) ) # ( 
// \u0|write_data_fifo_tx|data_out [5] & ( !\A_SPW_TOP|tx_data|mem[42][5]~q  & ( (\A_SPW_TOP|tx_data|Selector383~0_combout  & ((\A_SPW_TOP|tx_data|Mux3~20_combout ) # (\A_SPW_TOP|tx_data|state_data_write.00~q ))) ) ) ) # ( !\u0|write_data_fifo_tx|data_out 
// [5] & ( !\A_SPW_TOP|tx_data|mem[42][5]~q  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux3~20_combout  & \A_SPW_TOP|tx_data|Selector383~0_combout )) ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .datad(!\A_SPW_TOP|tx_data|Selector383~0_combout ),
        .datae(!\u0|write_data_fifo_tx|data_out [5]),
        .dataf(!\A_SPW_TOP|tx_data|mem[42][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector386~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector386~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector386~0 .lut_mask = 64'h000C003FFF0CFF3F;
defparam \A_SPW_TOP|tx_data|Selector386~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y14_N8
dffeas \A_SPW_TOP|tx_data|mem[42][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector386~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[42][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[42][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[42][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y14_N57
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector98~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector98~0_combout  = ( \A_SPW_TOP|tx_data|mem[10][5]~q  & ( (!\A_SPW_TOP|tx_data|Selector95~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux3~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [5])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[10][5]~q  & ( (\A_SPW_TOP|tx_data|Selector95~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux3~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [5]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\u0|write_data_fifo_tx|data_out [5]),
        .datad(!\A_SPW_TOP|tx_data|Selector95~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[10][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector98~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector98~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector98~0 .lut_mask = 64'h00470047FF47FF47;
defparam \A_SPW_TOP|tx_data|Selector98~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y14_N26
dffeas \A_SPW_TOP|tx_data|mem[10][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector98~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[10][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[10][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[10][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y14_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux3~10 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux3~10_combout  = ( \A_SPW_TOP|tx_data|mem[42][5]~q  & ( \A_SPW_TOP|tx_data|mem[10][5]~q  & ( ((!\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|mem[2][5]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [5] & ((\A_SPW_TOP|tx_data|mem[34][5]~q 
// )))) # (\A_SPW_TOP|tx_data|wr_ptr [3]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[42][5]~q  & ( \A_SPW_TOP|tx_data|mem[10][5]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [5] & (((\A_SPW_TOP|tx_data|wr_ptr [3])) # (\A_SPW_TOP|tx_data|mem[2][5]~q ))) # 
// (\A_SPW_TOP|tx_data|wr_ptr [5] & (((\A_SPW_TOP|tx_data|mem[34][5]~q  & !\A_SPW_TOP|tx_data|wr_ptr [3])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[42][5]~q  & ( !\A_SPW_TOP|tx_data|mem[10][5]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [5] & 
// (\A_SPW_TOP|tx_data|mem[2][5]~q  & ((!\A_SPW_TOP|tx_data|wr_ptr [3])))) # (\A_SPW_TOP|tx_data|wr_ptr [5] & (((\A_SPW_TOP|tx_data|wr_ptr [3]) # (\A_SPW_TOP|tx_data|mem[34][5]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[42][5]~q  & ( 
// !\A_SPW_TOP|tx_data|mem[10][5]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [3] & ((!\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|mem[2][5]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [5] & ((\A_SPW_TOP|tx_data|mem[34][5]~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[2][5]~q ),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datac(!\A_SPW_TOP|tx_data|mem[34][5]~q ),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datae(!\A_SPW_TOP|tx_data|mem[42][5]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[10][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux3~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux3~10 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux3~10 .lut_mask = 64'h4700473347CC47FF;
defparam \A_SPW_TOP|tx_data|Mux3~10 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y14_N57
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector278~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector278~0_combout  = ( \A_SPW_TOP|tx_data|Mux3~20_combout  & ( \A_SPW_TOP|tx_data|mem[30][5]~q  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q ) # ((!\A_SPW_TOP|tx_data|Selector275~0_combout ) # (\u0|write_data_fifo_tx|data_out 
// [5])) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux3~20_combout  & ( \A_SPW_TOP|tx_data|mem[30][5]~q  & ( (!\A_SPW_TOP|tx_data|Selector275~0_combout ) # ((\A_SPW_TOP|tx_data|state_data_write.00~q  & \u0|write_data_fifo_tx|data_out [5])) ) ) ) # ( 
// \A_SPW_TOP|tx_data|Mux3~20_combout  & ( !\A_SPW_TOP|tx_data|mem[30][5]~q  & ( (\A_SPW_TOP|tx_data|Selector275~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q ) # (\u0|write_data_fifo_tx|data_out [5]))) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|Mux3~20_combout  & ( !\A_SPW_TOP|tx_data|mem[30][5]~q  & ( (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [5] & \A_SPW_TOP|tx_data|Selector275~0_combout )) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(gnd),
        .datac(!\u0|write_data_fifo_tx|data_out [5]),
        .datad(!\A_SPW_TOP|tx_data|Selector275~0_combout ),
        .datae(!\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .dataf(!\A_SPW_TOP|tx_data|mem[30][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector278~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector278~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector278~0 .lut_mask = 64'h000500AFFF05FFAF;
defparam \A_SPW_TOP|tx_data|Selector278~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X45_Y14_N53
dffeas \A_SPW_TOP|tx_data|mem[30][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector278~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[30][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[30][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[30][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y14_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector566~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector566~0_combout  = ( \A_SPW_TOP|tx_data|mem[62][5]~q  & ( (!\A_SPW_TOP|tx_data|Selector563~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux3~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [5]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[62][5]~q  & ( (\A_SPW_TOP|tx_data|Selector563~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux3~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [5])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [5]),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector563~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[62][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector566~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector566~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector566~0 .lut_mask = 64'h010D010DF1FDF1FD;
defparam \A_SPW_TOP|tx_data|Selector566~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y14_N11
dffeas \A_SPW_TOP|tx_data|mem[62][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector566~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[62][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[62][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[62][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y14_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector494~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector494~0_combout  = ( \A_SPW_TOP|tx_data|mem[54][5]~q  & ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector491~0_combout ) # (\u0|write_data_fifo_tx|data_out [5]) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|mem[54][5]~q  & ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (\u0|write_data_fifo_tx|data_out [5] & \A_SPW_TOP|tx_data|Selector491~0_combout ) ) ) ) # ( \A_SPW_TOP|tx_data|mem[54][5]~q  & ( !\A_SPW_TOP|tx_data|state_data_write.00~q  
// & ( (!\A_SPW_TOP|tx_data|Selector491~0_combout ) # (\A_SPW_TOP|tx_data|Mux3~20_combout ) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[54][5]~q  & ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( (\A_SPW_TOP|tx_data|Mux3~20_combout  & 
// \A_SPW_TOP|tx_data|Selector491~0_combout ) ) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [5]),
        .datab(!\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .datac(gnd),
        .datad(!\A_SPW_TOP|tx_data|Selector491~0_combout ),
        .datae(!\A_SPW_TOP|tx_data|mem[54][5]~q ),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector494~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector494~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector494~0 .lut_mask = 64'h0033FF330055FF55;
defparam \A_SPW_TOP|tx_data|Selector494~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y14_N47
dffeas \A_SPW_TOP|tx_data|mem[54][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector494~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[54][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[54][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[54][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y14_N57
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector206~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector206~0_combout  = ( \A_SPW_TOP|tx_data|Selector203~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux3~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\u0|write_data_fifo_tx|data_out [5])) ) ) # ( !\A_SPW_TOP|tx_data|Selector203~0_combout  & ( \A_SPW_TOP|tx_data|mem[22][5]~q  ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [5]),
        .datab(!\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[22][5]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector203~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector206~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector206~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector206~0 .lut_mask = 64'h00FF00FF35353535;
defparam \A_SPW_TOP|tx_data|Selector206~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y14_N17
dffeas \A_SPW_TOP|tx_data|mem[22][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector206~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[22][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[22][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[22][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y14_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux3~13 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux3~13_combout  = ( \A_SPW_TOP|tx_data|mem[54][5]~q  & ( \A_SPW_TOP|tx_data|mem[22][5]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [3]) # ((!\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|mem[30][5]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [5] & 
// ((\A_SPW_TOP|tx_data|mem[62][5]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[54][5]~q  & ( \A_SPW_TOP|tx_data|mem[22][5]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [3] & (((!\A_SPW_TOP|tx_data|wr_ptr [5])))) # (\A_SPW_TOP|tx_data|wr_ptr [3] & 
// ((!\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|mem[30][5]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [5] & ((\A_SPW_TOP|tx_data|mem[62][5]~q ))))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[54][5]~q  & ( !\A_SPW_TOP|tx_data|mem[22][5]~q  & ( 
// (!\A_SPW_TOP|tx_data|wr_ptr [3] & (((\A_SPW_TOP|tx_data|wr_ptr [5])))) # (\A_SPW_TOP|tx_data|wr_ptr [3] & ((!\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|mem[30][5]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [5] & ((\A_SPW_TOP|tx_data|mem[62][5]~q ))))) ) ) 
// ) # ( !\A_SPW_TOP|tx_data|mem[54][5]~q  & ( !\A_SPW_TOP|tx_data|mem[22][5]~q  & ( (\A_SPW_TOP|tx_data|wr_ptr [3] & ((!\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|mem[30][5]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [5] & ((\A_SPW_TOP|tx_data|mem[62][5]~q 
// ))))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datab(!\A_SPW_TOP|tx_data|mem[30][5]~q ),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datad(!\A_SPW_TOP|tx_data|mem[62][5]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[54][5]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[22][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux3~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux3~13 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux3~13 .lut_mask = 64'h10151A1FB0B5BABF;
defparam \A_SPW_TOP|tx_data|Mux3~13 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y14_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector350~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector350~0_combout  = ( \A_SPW_TOP|tx_data|Mux3~20_combout  & ( (!\A_SPW_TOP|tx_data|Selector347~0_combout  & (((\A_SPW_TOP|tx_data|mem[38][5]~q )))) # (\A_SPW_TOP|tx_data|Selector347~0_combout  & 
// (((!\A_SPW_TOP|tx_data|state_data_write.00~q )) # (\u0|write_data_fifo_tx|data_out [5]))) ) ) # ( !\A_SPW_TOP|tx_data|Mux3~20_combout  & ( (!\A_SPW_TOP|tx_data|Selector347~0_combout  & (((\A_SPW_TOP|tx_data|mem[38][5]~q )))) # 
// (\A_SPW_TOP|tx_data|Selector347~0_combout  & (\u0|write_data_fifo_tx|data_out [5] & (\A_SPW_TOP|tx_data|state_data_write.00~q ))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [5]),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector347~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|mem[38][5]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector350~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector350~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector350~0 .lut_mask = 64'h01F101F10DFD0DFD;
defparam \A_SPW_TOP|tx_data|Selector350~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y14_N50
dffeas \A_SPW_TOP|tx_data|mem[38][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector350~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[38][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[38][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[38][5] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y14_N57
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector62~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector62~0_combout  = ( \A_SPW_TOP|tx_data|mem[6][5]~q  & ( (!\A_SPW_TOP|tx_data|Selector59~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux3~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [5]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[6][5]~q  & ( (\A_SPW_TOP|tx_data|Selector59~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux3~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [5])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [5]),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .datad(!\A_SPW_TOP|tx_data|Selector59~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[6][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector62~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector62~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector62~0 .lut_mask = 64'h001D001DFF1DFF1D;
defparam \A_SPW_TOP|tx_data|Selector62~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y14_N47
dffeas \A_SPW_TOP|tx_data|mem[6][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector62~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[6][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[6][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[6][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y14_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector422~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector422~0_combout  = ( \A_SPW_TOP|tx_data|Selector419~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux3~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [5]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector419~0_combout  & ( \A_SPW_TOP|tx_data|mem[46][5]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[46][5]~q ),
        .datad(!\u0|write_data_fifo_tx|data_out [5]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector419~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector422~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector422~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector422~0 .lut_mask = 64'h0F0F0F0F44774477;
defparam \A_SPW_TOP|tx_data|Selector422~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y14_N17
dffeas \A_SPW_TOP|tx_data|mem[46][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector422~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[46][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[46][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[46][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y14_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector134~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector134~0_combout  = ( \A_SPW_TOP|tx_data|mem[14][5]~q  & ( (!\A_SPW_TOP|tx_data|Selector131~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux3~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [5])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[14][5]~q  & ( (\A_SPW_TOP|tx_data|Selector131~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux3~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [5]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector131~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [5]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[14][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector134~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector134~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector134~0 .lut_mask = 64'h04070407F4F7F4F7;
defparam \A_SPW_TOP|tx_data|Selector134~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y14_N14
dffeas \A_SPW_TOP|tx_data|mem[14][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector134~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[14][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[14][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[14][5] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y14_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux3~11 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux3~11_combout  = ( \A_SPW_TOP|tx_data|mem[46][5]~q  & ( \A_SPW_TOP|tx_data|mem[14][5]~q  & ( ((!\A_SPW_TOP|tx_data|wr_ptr [5] & ((\A_SPW_TOP|tx_data|mem[6][5]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|mem[38][5]~q 
// ))) # (\A_SPW_TOP|tx_data|wr_ptr [3]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[46][5]~q  & ( \A_SPW_TOP|tx_data|mem[14][5]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [3] & ((!\A_SPW_TOP|tx_data|wr_ptr [5] & ((\A_SPW_TOP|tx_data|mem[6][5]~q ))) # 
// (\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|mem[38][5]~q )))) # (\A_SPW_TOP|tx_data|wr_ptr [3] & (!\A_SPW_TOP|tx_data|wr_ptr [5])) ) ) ) # ( \A_SPW_TOP|tx_data|mem[46][5]~q  & ( !\A_SPW_TOP|tx_data|mem[14][5]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr 
// [3] & ((!\A_SPW_TOP|tx_data|wr_ptr [5] & ((\A_SPW_TOP|tx_data|mem[6][5]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|mem[38][5]~q )))) # (\A_SPW_TOP|tx_data|wr_ptr [3] & (\A_SPW_TOP|tx_data|wr_ptr [5])) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|mem[46][5]~q  & ( !\A_SPW_TOP|tx_data|mem[14][5]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [3] & ((!\A_SPW_TOP|tx_data|wr_ptr [5] & ((\A_SPW_TOP|tx_data|mem[6][5]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|mem[38][5]~q )))) 
// ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datac(!\A_SPW_TOP|tx_data|mem[38][5]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[6][5]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[46][5]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[14][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux3~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux3~11 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux3~11 .lut_mask = 64'h028A139B46CE57DF;
defparam \A_SPW_TOP|tx_data|Mux3~11 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y14_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux3~14 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux3~14_combout  = ( \A_SPW_TOP|tx_data|Mux3~11_combout  & ( \A_SPW_TOP|tx_data|wr_ptr [2] & ( (!\A_SPW_TOP|tx_data|wr_ptr [4]) # (\A_SPW_TOP|tx_data|Mux3~13_combout ) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux3~11_combout  & ( 
// \A_SPW_TOP|tx_data|wr_ptr [2] & ( (\A_SPW_TOP|tx_data|wr_ptr [4] & \A_SPW_TOP|tx_data|Mux3~13_combout ) ) ) ) # ( \A_SPW_TOP|tx_data|Mux3~11_combout  & ( !\A_SPW_TOP|tx_data|wr_ptr [2] & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & 
// ((\A_SPW_TOP|tx_data|Mux3~10_combout ))) # (\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|Mux3~12_combout )) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux3~11_combout  & ( !\A_SPW_TOP|tx_data|wr_ptr [2] & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & 
// ((\A_SPW_TOP|tx_data|Mux3~10_combout ))) # (\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|Mux3~12_combout )) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux3~12_combout ),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datac(!\A_SPW_TOP|tx_data|Mux3~10_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux3~13_combout ),
        .datae(!\A_SPW_TOP|tx_data|Mux3~11_combout ),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux3~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux3~14 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux3~14 .lut_mask = 64'h1D1D1D1D0033CCFF;
defparam \A_SPW_TOP|tx_data|Mux3~14 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y14_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector8~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector8~0_combout  = ( \A_SPW_TOP|tx_data|mem[0][5]~q  & ( (!\A_SPW_TOP|tx_data|Selector5~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux3~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  
// & ((\u0|write_data_fifo_tx|data_out [5])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[0][5]~q  & ( (\A_SPW_TOP|tx_data|Selector5~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux3~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [5]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Selector5~0_combout ),
        .datab(!\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .datac(!\u0|write_data_fifo_tx|data_out [5]),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[0][5]~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector8~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector8~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector8~0 .lut_mask = 64'h1105BBAF1105BBAF;
defparam \A_SPW_TOP|tx_data|Selector8~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y14_N2
dffeas \A_SPW_TOP|tx_data|mem[0][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector8~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[0][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[0][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[0][5] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y14_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector296~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector296~0_combout  = ( \A_SPW_TOP|tx_data|Selector293~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux3~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\u0|write_data_fifo_tx|data_out [5])) ) ) # ( !\A_SPW_TOP|tx_data|Selector293~0_combout  & ( \A_SPW_TOP|tx_data|mem[32][5]~q  ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [5]),
        .datab(!\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[32][5]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector293~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector296~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector296~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector296~0 .lut_mask = 64'h00FF00FF35353535;
defparam \A_SPW_TOP|tx_data|Selector296~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y14_N59
dffeas \A_SPW_TOP|tx_data|mem[32][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector296~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[32][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[32][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[32][5] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y14_N33
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector80~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector80~0_combout  = ( \A_SPW_TOP|tx_data|Selector77~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux3~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\u0|write_data_fifo_tx|data_out [5])) ) ) # ( !\A_SPW_TOP|tx_data|Selector77~0_combout  & ( \A_SPW_TOP|tx_data|mem[8][5]~q  ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [5]),
        .datab(!\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[8][5]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector77~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector80~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector80~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector80~0 .lut_mask = 64'h00FF00FF35353535;
defparam \A_SPW_TOP|tx_data|Selector80~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y14_N38
dffeas \A_SPW_TOP|tx_data|mem[8][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector80~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[8][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[8][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[8][5] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y14_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector368~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector368~0_combout  = ( \A_SPW_TOP|tx_data|mem[40][5]~q  & ( (!\A_SPW_TOP|tx_data|Selector365~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux3~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [5]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[40][5]~q  & ( (\A_SPW_TOP|tx_data|Selector365~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux3~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [5])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [5]),
        .datab(!\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector365~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[40][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector368~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector368~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector368~0 .lut_mask = 64'h03050305F3F5F3F5;
defparam \A_SPW_TOP|tx_data|Selector368~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y14_N26
dffeas \A_SPW_TOP|tx_data|mem[40][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector368~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[40][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[40][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[40][5] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y14_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux3~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux3~0_combout  = ( \A_SPW_TOP|tx_data|mem[8][5]~q  & ( \A_SPW_TOP|tx_data|mem[40][5]~q  & ( ((!\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|mem[0][5]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [5] & ((\A_SPW_TOP|tx_data|mem[32][5]~q )))) 
// # (\A_SPW_TOP|tx_data|wr_ptr [3]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[8][5]~q  & ( \A_SPW_TOP|tx_data|mem[40][5]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [3] & ((!\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|mem[0][5]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [5] 
// & ((\A_SPW_TOP|tx_data|mem[32][5]~q ))))) # (\A_SPW_TOP|tx_data|wr_ptr [3] & (((\A_SPW_TOP|tx_data|wr_ptr [5])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[8][5]~q  & ( !\A_SPW_TOP|tx_data|mem[40][5]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [3] & 
// ((!\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|mem[0][5]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [5] & ((\A_SPW_TOP|tx_data|mem[32][5]~q ))))) # (\A_SPW_TOP|tx_data|wr_ptr [3] & (((!\A_SPW_TOP|tx_data|wr_ptr [5])))) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|mem[8][5]~q  & ( !\A_SPW_TOP|tx_data|mem[40][5]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [3] & ((!\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|mem[0][5]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [5] & ((\A_SPW_TOP|tx_data|mem[32][5]~q ))))) ) 
// ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[0][5]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[32][5]~q ),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datae(!\A_SPW_TOP|tx_data|mem[8][5]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[40][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux3~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux3~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux3~0 .lut_mask = 64'h50305F30503F5F3F;
defparam \A_SPW_TOP|tx_data|Mux3~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y14_N39
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector116~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector116~0_combout  = ( \A_SPW_TOP|tx_data|Selector113~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux3~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [5]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector113~0_combout  & ( \A_SPW_TOP|tx_data|mem[12][5]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\u0|write_data_fifo_tx|data_out [5]),
        .datad(!\A_SPW_TOP|tx_data|mem[12][5]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector113~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector116~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector116~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector116~0 .lut_mask = 64'h00FF00FF47474747;
defparam \A_SPW_TOP|tx_data|Selector116~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y14_N29
dffeas \A_SPW_TOP|tx_data|mem[12][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector116~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[12][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[12][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[12][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y14_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector404~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector404~0_combout  = ( \A_SPW_TOP|tx_data|mem[44][5]~q  & ( (!\A_SPW_TOP|tx_data|Selector401~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux3~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [5])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[44][5]~q  & ( (\A_SPW_TOP|tx_data|Selector401~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux3~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [5]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector401~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [5]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[44][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector404~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector404~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector404~0 .lut_mask = 64'h04070407F4F7F4F7;
defparam \A_SPW_TOP|tx_data|Selector404~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y14_N11
dffeas \A_SPW_TOP|tx_data|mem[44][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector404~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[44][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[44][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[44][5] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y14_N45
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector44~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector44~0_combout  = ( \u0|write_data_fifo_tx|data_out [5] & ( (!\A_SPW_TOP|tx_data|Selector41~0_combout  & (((\A_SPW_TOP|tx_data|mem[4][5]~q )))) # (\A_SPW_TOP|tx_data|Selector41~0_combout  & (((\A_SPW_TOP|tx_data|Mux3~20_combout )) 
// # (\A_SPW_TOP|tx_data|state_data_write.00~q ))) ) ) # ( !\u0|write_data_fifo_tx|data_out [5] & ( (!\A_SPW_TOP|tx_data|Selector41~0_combout  & (((\A_SPW_TOP|tx_data|mem[4][5]~q )))) # (\A_SPW_TOP|tx_data|Selector41~0_combout  & 
// (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux3~20_combout ))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|mem[4][5]~q ),
        .datad(!\A_SPW_TOP|tx_data|Selector41~0_combout ),
        .datae(gnd),
        .dataf(!\u0|write_data_fifo_tx|data_out [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector44~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector44~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector44~0 .lut_mask = 64'h0F220F220F770F77;
defparam \A_SPW_TOP|tx_data|Selector44~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y14_N17
dffeas \A_SPW_TOP|tx_data|mem[4][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector44~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[4][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[4][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[4][5] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y14_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector332~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector332~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector329~0_combout  & ((\A_SPW_TOP|tx_data|mem[36][5]~q ))) # (\A_SPW_TOP|tx_data|Selector329~0_combout  & (\u0|write_data_fifo_tx|data_out 
// [5])) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector329~0_combout  & ((\A_SPW_TOP|tx_data|mem[36][5]~q ))) # (\A_SPW_TOP|tx_data|Selector329~0_combout  & (\A_SPW_TOP|tx_data|Mux3~20_combout )) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [5]),
        .datab(!\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|mem[36][5]~q ),
        .datad(!\A_SPW_TOP|tx_data|Selector329~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector332~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector332~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector332~0 .lut_mask = 64'h0F330F330F550F55;
defparam \A_SPW_TOP|tx_data|Selector332~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y14_N32
dffeas \A_SPW_TOP|tx_data|mem[36][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector332~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[36][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[36][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[36][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y14_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux3~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux3~1_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [5] & ( \A_SPW_TOP|tx_data|mem[36][5]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [3]) # (\A_SPW_TOP|tx_data|mem[44][5]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [5] & ( 
// \A_SPW_TOP|tx_data|mem[36][5]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [3] & ((\A_SPW_TOP|tx_data|mem[4][5]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [3] & (\A_SPW_TOP|tx_data|mem[12][5]~q )) ) ) ) # ( \A_SPW_TOP|tx_data|wr_ptr [5] & ( !\A_SPW_TOP|tx_data|mem[36][5]~q 
//  & ( (\A_SPW_TOP|tx_data|mem[44][5]~q  & \A_SPW_TOP|tx_data|wr_ptr [3]) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [5] & ( !\A_SPW_TOP|tx_data|mem[36][5]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [3] & ((\A_SPW_TOP|tx_data|mem[4][5]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr 
// [3] & (\A_SPW_TOP|tx_data|mem[12][5]~q )) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[12][5]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[44][5]~q ),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datad(!\A_SPW_TOP|tx_data|mem[4][5]~q ),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .dataf(!\A_SPW_TOP|tx_data|mem[36][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux3~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux3~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux3~1 .lut_mask = 64'h05F5030305F5F3F3;
defparam \A_SPW_TOP|tx_data|Mux3~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y14_N39
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector440~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector440~0_combout  = ( \A_SPW_TOP|tx_data|mem[48][5]~q  & ( (!\A_SPW_TOP|tx_data|Selector437~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux3~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [5]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[48][5]~q  & ( (\A_SPW_TOP|tx_data|Selector437~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux3~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [5])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [5]),
        .datab(!\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|tx_data|Selector437~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[48][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector440~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector440~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector440~0 .lut_mask = 64'h00350035FF35FF35;
defparam \A_SPW_TOP|tx_data|Selector440~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y14_N35
dffeas \A_SPW_TOP|tx_data|mem[48][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector440~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[48][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[48][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[48][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y14_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector224~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector224~0_combout  = ( \A_SPW_TOP|tx_data|Mux3~20_combout  & ( \A_SPW_TOP|tx_data|mem[24][5]~q  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q ) # ((!\A_SPW_TOP|tx_data|Selector221~0_combout ) # (\u0|write_data_fifo_tx|data_out 
// [5])) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux3~20_combout  & ( \A_SPW_TOP|tx_data|mem[24][5]~q  & ( (!\A_SPW_TOP|tx_data|Selector221~0_combout ) # ((\A_SPW_TOP|tx_data|state_data_write.00~q  & \u0|write_data_fifo_tx|data_out [5])) ) ) ) # ( 
// \A_SPW_TOP|tx_data|Mux3~20_combout  & ( !\A_SPW_TOP|tx_data|mem[24][5]~q  & ( (\A_SPW_TOP|tx_data|Selector221~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q ) # (\u0|write_data_fifo_tx|data_out [5]))) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|Mux3~20_combout  & ( !\A_SPW_TOP|tx_data|mem[24][5]~q  & ( (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [5] & \A_SPW_TOP|tx_data|Selector221~0_combout )) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(gnd),
        .datac(!\u0|write_data_fifo_tx|data_out [5]),
        .datad(!\A_SPW_TOP|tx_data|Selector221~0_combout ),
        .datae(!\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .dataf(!\A_SPW_TOP|tx_data|mem[24][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector224~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector224~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector224~0 .lut_mask = 64'h000500AFFF05FFAF;
defparam \A_SPW_TOP|tx_data|Selector224~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y14_N44
dffeas \A_SPW_TOP|tx_data|mem[24][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector224~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[24][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[24][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[24][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y13_N15
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector152~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector152~0_combout  = ( \A_SPW_TOP|tx_data|Selector149~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux3~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [5]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector149~0_combout  & ( \A_SPW_TOP|tx_data|mem[16][5]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|mem[16][5]~q ),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(!\u0|write_data_fifo_tx|data_out [5]),
        .datae(!\A_SPW_TOP|tx_data|Selector149~0_combout ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector152~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector152~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector152~0 .lut_mask = 64'h3333505F3333505F;
defparam \A_SPW_TOP|tx_data|Selector152~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y13_N14
dffeas \A_SPW_TOP|tx_data|mem[16][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector152~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[16][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[16][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[16][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y14_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector512~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector512~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector509~0_combout  & ((\A_SPW_TOP|tx_data|mem[56][5]~q ))) # (\A_SPW_TOP|tx_data|Selector509~0_combout  & (\u0|write_data_fifo_tx|data_out 
// [5])) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector509~0_combout  & ((\A_SPW_TOP|tx_data|mem[56][5]~q ))) # (\A_SPW_TOP|tx_data|Selector509~0_combout  & (\A_SPW_TOP|tx_data|Mux3~20_combout )) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [5]),
        .datab(!\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|mem[56][5]~q ),
        .datad(!\A_SPW_TOP|tx_data|Selector509~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector512~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector512~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector512~0 .lut_mask = 64'h0F330F330F550F55;
defparam \A_SPW_TOP|tx_data|Selector512~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y14_N23
dffeas \A_SPW_TOP|tx_data|mem[56][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector512~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[56][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[56][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[56][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y14_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux3~2 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux3~2_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [5] & ( \A_SPW_TOP|tx_data|wr_ptr [3] & ( \A_SPW_TOP|tx_data|mem[56][5]~q  ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [5] & ( \A_SPW_TOP|tx_data|wr_ptr [3] & ( \A_SPW_TOP|tx_data|mem[24][5]~q  ) ) 
// ) # ( \A_SPW_TOP|tx_data|wr_ptr [5] & ( !\A_SPW_TOP|tx_data|wr_ptr [3] & ( \A_SPW_TOP|tx_data|mem[48][5]~q  ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [5] & ( !\A_SPW_TOP|tx_data|wr_ptr [3] & ( \A_SPW_TOP|tx_data|mem[16][5]~q  ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[48][5]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[24][5]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[16][5]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[56][5]~q ),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux3~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux3~2 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux3~2 .lut_mask = 64'h0F0F5555333300FF;
defparam \A_SPW_TOP|tx_data|Mux3~2 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y14_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector476~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector476~0_combout  = ( \A_SPW_TOP|tx_data|mem[52][5]~q  & ( (!\A_SPW_TOP|tx_data|Selector473~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux3~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [5])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[52][5]~q  & ( (\A_SPW_TOP|tx_data|Selector473~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux3~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [5]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .datac(!\u0|write_data_fifo_tx|data_out [5]),
        .datad(!\A_SPW_TOP|tx_data|Selector473~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[52][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector476~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector476~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector476~0 .lut_mask = 64'h00270027FF27FF27;
defparam \A_SPW_TOP|tx_data|Selector476~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y14_N41
dffeas \A_SPW_TOP|tx_data|mem[52][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector476~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[52][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[52][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[52][5] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y14_N51
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector260~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector260~0_combout  = ( \A_SPW_TOP|tx_data|mem[28][5]~q  & ( (!\A_SPW_TOP|tx_data|Selector257~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux3~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [5]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[28][5]~q  & ( (\A_SPW_TOP|tx_data|Selector257~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux3~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [5])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [5]),
        .datab(!\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector257~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[28][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector260~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector260~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector260~0 .lut_mask = 64'h03050305F3F5F3F5;
defparam \A_SPW_TOP|tx_data|Selector260~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y14_N8
dffeas \A_SPW_TOP|tx_data|mem[28][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector260~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[28][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[28][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[28][5] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y14_N21
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector188~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector188~0_combout  = ( \u0|write_data_fifo_tx|data_out [5] & ( (!\A_SPW_TOP|tx_data|Selector185~0_combout  & (((\A_SPW_TOP|tx_data|mem[20][5]~q )))) # (\A_SPW_TOP|tx_data|Selector185~0_combout  & 
// (((\A_SPW_TOP|tx_data|Mux3~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q ))) ) ) # ( !\u0|write_data_fifo_tx|data_out [5] & ( (!\A_SPW_TOP|tx_data|Selector185~0_combout  & (((\A_SPW_TOP|tx_data|mem[20][5]~q )))) # 
// (\A_SPW_TOP|tx_data|Selector185~0_combout  & (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux3~20_combout ))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|mem[20][5]~q ),
        .datad(!\A_SPW_TOP|tx_data|Selector185~0_combout ),
        .datae(gnd),
        .dataf(!\u0|write_data_fifo_tx|data_out [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector188~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector188~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector188~0 .lut_mask = 64'h0F220F220F770F77;
defparam \A_SPW_TOP|tx_data|Selector188~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y14_N11
dffeas \A_SPW_TOP|tx_data|mem[20][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector188~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[20][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[20][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[20][5] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y14_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux3~3 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux3~3_combout  = ( \A_SPW_TOP|tx_data|mem[60][5]~q  & ( \A_SPW_TOP|tx_data|mem[20][5]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [3] & (((!\A_SPW_TOP|tx_data|wr_ptr [5])) # (\A_SPW_TOP|tx_data|mem[52][5]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [3] 
// & (((\A_SPW_TOP|tx_data|wr_ptr [5]) # (\A_SPW_TOP|tx_data|mem[28][5]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[60][5]~q  & ( \A_SPW_TOP|tx_data|mem[20][5]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [3] & (((!\A_SPW_TOP|tx_data|wr_ptr [5])) # 
// (\A_SPW_TOP|tx_data|mem[52][5]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [3] & (((\A_SPW_TOP|tx_data|mem[28][5]~q  & !\A_SPW_TOP|tx_data|wr_ptr [5])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[60][5]~q  & ( !\A_SPW_TOP|tx_data|mem[20][5]~q  & ( 
// (!\A_SPW_TOP|tx_data|wr_ptr [3] & (\A_SPW_TOP|tx_data|mem[52][5]~q  & ((\A_SPW_TOP|tx_data|wr_ptr [5])))) # (\A_SPW_TOP|tx_data|wr_ptr [3] & (((\A_SPW_TOP|tx_data|wr_ptr [5]) # (\A_SPW_TOP|tx_data|mem[28][5]~q )))) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|mem[60][5]~q  & ( !\A_SPW_TOP|tx_data|mem[20][5]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [3] & (\A_SPW_TOP|tx_data|mem[52][5]~q  & ((\A_SPW_TOP|tx_data|wr_ptr [5])))) # (\A_SPW_TOP|tx_data|wr_ptr [3] & (((\A_SPW_TOP|tx_data|mem[28][5]~q  & 
// !\A_SPW_TOP|tx_data|wr_ptr [5])))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datab(!\A_SPW_TOP|tx_data|mem[52][5]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[28][5]~q ),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datae(!\A_SPW_TOP|tx_data|mem[60][5]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[20][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux3~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux3~3 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux3~3 .lut_mask = 64'h05220577AF22AF77;
defparam \A_SPW_TOP|tx_data|Mux3~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y14_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux3~4 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux3~4_combout  = ( \A_SPW_TOP|tx_data|Mux3~3_combout  & ( \A_SPW_TOP|tx_data|wr_ptr [4] & ( (\A_SPW_TOP|tx_data|Mux3~2_combout ) # (\A_SPW_TOP|tx_data|wr_ptr [2]) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux3~3_combout  & ( 
// \A_SPW_TOP|tx_data|wr_ptr [4] & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & \A_SPW_TOP|tx_data|Mux3~2_combout ) ) ) ) # ( \A_SPW_TOP|tx_data|Mux3~3_combout  & ( !\A_SPW_TOP|tx_data|wr_ptr [4] & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & 
// (\A_SPW_TOP|tx_data|Mux3~0_combout )) # (\A_SPW_TOP|tx_data|wr_ptr [2] & ((\A_SPW_TOP|tx_data|Mux3~1_combout ))) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux3~3_combout  & ( !\A_SPW_TOP|tx_data|wr_ptr [4] & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & 
// (\A_SPW_TOP|tx_data|Mux3~0_combout )) # (\A_SPW_TOP|tx_data|wr_ptr [2] & ((\A_SPW_TOP|tx_data|Mux3~1_combout ))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datab(!\A_SPW_TOP|tx_data|Mux3~0_combout ),
        .datac(!\A_SPW_TOP|tx_data|Mux3~1_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux3~2_combout ),
        .datae(!\A_SPW_TOP|tx_data|Mux3~3_combout ),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux3~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux3~4 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux3~4 .lut_mask = 64'h2727272700AA55FF;
defparam \A_SPW_TOP|tx_data|Mux3~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y14_N39
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector449~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector449~0_combout  = ( \A_SPW_TOP|tx_data|Selector446~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux3~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [5]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector446~0_combout  & ( \A_SPW_TOP|tx_data|mem[49][5]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .datac(!\u0|write_data_fifo_tx|data_out [5]),
        .datad(!\A_SPW_TOP|tx_data|mem[49][5]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector446~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector449~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector449~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector449~0 .lut_mask = 64'h00FF00FF27272727;
defparam \A_SPW_TOP|tx_data|Selector449~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y14_N27
cyclonev_lcell_comb \A_SPW_TOP|tx_data|mem[49][5]~feeder (
// Equation(s):
// \A_SPW_TOP|tx_data|mem[49][5]~feeder_combout  = ( \A_SPW_TOP|tx_data|Selector449~0_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector449~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|mem[49][5]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[49][5]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|mem[49][5]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|tx_data|mem[49][5]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X45_Y14_N29
dffeas \A_SPW_TOP|tx_data|mem[49][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|tx_data|mem[49][5]~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[49][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[49][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[49][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y14_N21
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector521~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector521~0_combout  = ( \u0|write_data_fifo_tx|data_out [5] & ( (!\A_SPW_TOP|tx_data|Selector518~0_combout  & (((\A_SPW_TOP|tx_data|mem[57][5]~q )))) # (\A_SPW_TOP|tx_data|Selector518~0_combout  & 
// (((\A_SPW_TOP|tx_data|state_data_write.00~q )) # (\A_SPW_TOP|tx_data|Mux3~20_combout ))) ) ) # ( !\u0|write_data_fifo_tx|data_out [5] & ( (!\A_SPW_TOP|tx_data|Selector518~0_combout  & (((\A_SPW_TOP|tx_data|mem[57][5]~q )))) # 
// (\A_SPW_TOP|tx_data|Selector518~0_combout  & (\A_SPW_TOP|tx_data|Mux3~20_combout  & (!\A_SPW_TOP|tx_data|state_data_write.00~q ))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[57][5]~q ),
        .datad(!\A_SPW_TOP|tx_data|Selector518~0_combout ),
        .datae(gnd),
        .dataf(!\u0|write_data_fifo_tx|data_out [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector521~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector521~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector521~0 .lut_mask = 64'h0F440F440F770F77;
defparam \A_SPW_TOP|tx_data|Selector521~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y14_N41
dffeas \A_SPW_TOP|tx_data|mem[57][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector521~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[57][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[57][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[57][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y14_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector161~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector161~0_combout  = ( \A_SPW_TOP|tx_data|mem[17][5]~q  & ( (!\A_SPW_TOP|tx_data|Selector158~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux3~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [5])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[17][5]~q  & ( (\A_SPW_TOP|tx_data|Selector158~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux3~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [5]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector158~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [5]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[17][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector161~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector161~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector161~0 .lut_mask = 64'h02070207F2F7F2F7;
defparam \A_SPW_TOP|tx_data|Selector161~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X45_Y14_N8
dffeas \A_SPW_TOP|tx_data|mem[17][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector161~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[17][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[17][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[17][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y14_N15
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector233~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector233~0_combout  = ( \A_SPW_TOP|tx_data|Selector230~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux3~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [5]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector230~0_combout  & ( \A_SPW_TOP|tx_data|mem[25][5]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [5]),
        .datac(!\A_SPW_TOP|tx_data|mem[25][5]~q ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector230~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector233~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector233~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector233~0 .lut_mask = 64'h0F0F0F0F55335533;
defparam \A_SPW_TOP|tx_data|Selector233~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y14_N47
dffeas \A_SPW_TOP|tx_data|mem[25][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector233~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[25][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[25][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[25][5] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y14_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux3~7 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux3~7_combout  = ( \A_SPW_TOP|tx_data|mem[17][5]~q  & ( \A_SPW_TOP|tx_data|mem[25][5]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [5]) # ((!\A_SPW_TOP|tx_data|wr_ptr [3] & (\A_SPW_TOP|tx_data|mem[49][5]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [3] & 
// ((\A_SPW_TOP|tx_data|mem[57][5]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[17][5]~q  & ( \A_SPW_TOP|tx_data|mem[25][5]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [3] & (\A_SPW_TOP|tx_data|mem[49][5]~q  & ((\A_SPW_TOP|tx_data|wr_ptr [5])))) # 
// (\A_SPW_TOP|tx_data|wr_ptr [3] & (((!\A_SPW_TOP|tx_data|wr_ptr [5]) # (\A_SPW_TOP|tx_data|mem[57][5]~q )))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[17][5]~q  & ( !\A_SPW_TOP|tx_data|mem[25][5]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [3] & 
// (((!\A_SPW_TOP|tx_data|wr_ptr [5])) # (\A_SPW_TOP|tx_data|mem[49][5]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [3] & (((\A_SPW_TOP|tx_data|mem[57][5]~q  & \A_SPW_TOP|tx_data|wr_ptr [5])))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[17][5]~q  & ( 
// !\A_SPW_TOP|tx_data|mem[25][5]~q  & ( (\A_SPW_TOP|tx_data|wr_ptr [5] & ((!\A_SPW_TOP|tx_data|wr_ptr [3] & (\A_SPW_TOP|tx_data|mem[49][5]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [3] & ((\A_SPW_TOP|tx_data|mem[57][5]~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datab(!\A_SPW_TOP|tx_data|mem[49][5]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[57][5]~q ),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datae(!\A_SPW_TOP|tx_data|mem[17][5]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[25][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux3~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux3~7 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux3~7 .lut_mask = 64'h0027AA275527FF27;
defparam \A_SPW_TOP|tx_data|Mux3~7 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y14_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector53~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector53~0_combout  = ( \A_SPW_TOP|tx_data|Selector50~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux3~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out 
// [5]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector50~0_combout  & ( \A_SPW_TOP|tx_data|mem[5][5]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .datac(!\u0|write_data_fifo_tx|data_out [5]),
        .datad(!\A_SPW_TOP|tx_data|mem[5][5]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector50~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector53~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector53~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector53~0 .lut_mask = 64'h00FF00FF27272727;
defparam \A_SPW_TOP|tx_data|Selector53~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X45_Y14_N56
dffeas \A_SPW_TOP|tx_data|mem[5][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector53~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[5][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[5][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[5][5] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y14_N57
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector125~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector125~0_combout  = ( \A_SPW_TOP|tx_data|Selector122~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux3~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\u0|write_data_fifo_tx|data_out [5])) ) ) # ( !\A_SPW_TOP|tx_data|Selector122~0_combout  & ( \A_SPW_TOP|tx_data|mem[13][5]~q  ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [5]),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .datad(!\A_SPW_TOP|tx_data|mem[13][5]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector122~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector125~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector125~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector125~0 .lut_mask = 64'h00FF00FF1D1D1D1D;
defparam \A_SPW_TOP|tx_data|Selector125~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y14_N47
dffeas \A_SPW_TOP|tx_data|mem[13][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector125~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[13][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[13][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[13][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y14_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector413~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector413~0_combout  = ( \A_SPW_TOP|tx_data|mem[45][5]~q  & ( (!\A_SPW_TOP|tx_data|Selector410~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux3~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [5])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[45][5]~q  & ( (\A_SPW_TOP|tx_data|Selector410~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux3~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [5]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [5]),
        .datac(!\A_SPW_TOP|tx_data|Selector410~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[45][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector413~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector413~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector413~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|tx_data|Selector413~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y14_N38
dffeas \A_SPW_TOP|tx_data|mem[45][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector413~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[45][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[45][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[45][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y14_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector341~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector341~0_combout  = ( \A_SPW_TOP|tx_data|mem[37][5]~q  & ( (!\A_SPW_TOP|tx_data|Selector338~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux3~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [5])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[37][5]~q  & ( (\A_SPW_TOP|tx_data|Selector338~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux3~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [5]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector338~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [5]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[37][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector341~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector341~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector341~0 .lut_mask = 64'h02070207F2F7F2F7;
defparam \A_SPW_TOP|tx_data|Selector341~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X45_Y14_N20
dffeas \A_SPW_TOP|tx_data|mem[37][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector341~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[37][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[37][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[37][5] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y14_N9
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux3~6 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux3~6_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [5] & ( \A_SPW_TOP|tx_data|wr_ptr [3] & ( \A_SPW_TOP|tx_data|mem[45][5]~q  ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [5] & ( \A_SPW_TOP|tx_data|wr_ptr [3] & ( \A_SPW_TOP|tx_data|mem[13][5]~q  ) ) 
// ) # ( \A_SPW_TOP|tx_data|wr_ptr [5] & ( !\A_SPW_TOP|tx_data|wr_ptr [3] & ( \A_SPW_TOP|tx_data|mem[37][5]~q  ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [5] & ( !\A_SPW_TOP|tx_data|wr_ptr [3] & ( \A_SPW_TOP|tx_data|mem[5][5]~q  ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[5][5]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[13][5]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[45][5]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[37][5]~q ),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux3~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux3~6 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux3~6 .lut_mask = 64'h555500FF33330F0F;
defparam \A_SPW_TOP|tx_data|Mux3~6 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y14_N51
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector305~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector305~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector302~0_combout  & (\A_SPW_TOP|tx_data|mem[33][5]~q )) # (\A_SPW_TOP|tx_data|Selector302~0_combout  & ((\u0|write_data_fifo_tx|data_out 
// [5]))) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector302~0_combout  & (\A_SPW_TOP|tx_data|mem[33][5]~q )) # (\A_SPW_TOP|tx_data|Selector302~0_combout  & ((\A_SPW_TOP|tx_data|Mux3~20_combout ))) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[33][5]~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector302~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [5]),
        .datae(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector305~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector305~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector305~0 .lut_mask = 64'h5353505F5353505F;
defparam \A_SPW_TOP|tx_data|Selector305~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y14_N50
dffeas \A_SPW_TOP|tx_data|mem[33][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector305~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[33][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[33][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[33][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y14_N9
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector89~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector89~0_combout  = ( \A_SPW_TOP|tx_data|Selector86~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux3~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\u0|write_data_fifo_tx|data_out [5])) ) ) # ( !\A_SPW_TOP|tx_data|Selector86~0_combout  & ( \A_SPW_TOP|tx_data|mem[9][5]~q  ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [5]),
        .datab(!\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|mem[9][5]~q ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector86~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector89~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector89~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector89~0 .lut_mask = 64'h0F0F0F0F33553355;
defparam \A_SPW_TOP|tx_data|Selector89~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y14_N47
dffeas \A_SPW_TOP|tx_data|mem[9][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector89~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[9][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[9][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[9][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y14_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector377~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector377~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector374~0_combout  & ((\A_SPW_TOP|tx_data|mem[41][5]~q ))) # (\A_SPW_TOP|tx_data|Selector374~0_combout  & (\u0|write_data_fifo_tx|data_out 
// [5])) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector374~0_combout  & ((\A_SPW_TOP|tx_data|mem[41][5]~q ))) # (\A_SPW_TOP|tx_data|Selector374~0_combout  & (\A_SPW_TOP|tx_data|Mux3~20_combout )) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [5]),
        .datab(!\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|mem[41][5]~q ),
        .datad(!\A_SPW_TOP|tx_data|Selector374~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector377~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector377~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector377~0 .lut_mask = 64'h0F330F330F550F55;
defparam \A_SPW_TOP|tx_data|Selector377~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y14_N26
dffeas \A_SPW_TOP|tx_data|mem[41][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector377~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[41][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[41][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[41][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y13_N27
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector17~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector17~0_combout  = ( \u0|write_data_fifo_tx|data_out [5] & ( (!\A_SPW_TOP|tx_data|Selector14~0_combout  & (((\A_SPW_TOP|tx_data|mem[1][5]~q )))) # (\A_SPW_TOP|tx_data|Selector14~0_combout  & (((\A_SPW_TOP|tx_data|Mux3~20_combout )) 
// # (\A_SPW_TOP|tx_data|state_data_write.00~q ))) ) ) # ( !\u0|write_data_fifo_tx|data_out [5] & ( (!\A_SPW_TOP|tx_data|Selector14~0_combout  & (((\A_SPW_TOP|tx_data|mem[1][5]~q )))) # (\A_SPW_TOP|tx_data|Selector14~0_combout  & 
// (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux3~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Selector14~0_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[1][5]~q ),
        .datad(!\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .datae(gnd),
        .dataf(!\u0|write_data_fifo_tx|data_out [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector17~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector17~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector17~0 .lut_mask = 64'h0A4E0A4E1B5F1B5F;
defparam \A_SPW_TOP|tx_data|Selector17~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X45_Y13_N14
dffeas \A_SPW_TOP|tx_data|mem[1][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector17~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[1][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[1][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[1][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y14_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux3~5 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux3~5_combout  = ( \A_SPW_TOP|tx_data|mem[41][5]~q  & ( \A_SPW_TOP|tx_data|mem[1][5]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [3] & (((!\A_SPW_TOP|tx_data|wr_ptr [5])) # (\A_SPW_TOP|tx_data|mem[33][5]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [3] & 
// (((\A_SPW_TOP|tx_data|wr_ptr [5]) # (\A_SPW_TOP|tx_data|mem[9][5]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[41][5]~q  & ( \A_SPW_TOP|tx_data|mem[1][5]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [3] & (((!\A_SPW_TOP|tx_data|wr_ptr [5])) # 
// (\A_SPW_TOP|tx_data|mem[33][5]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [3] & (((\A_SPW_TOP|tx_data|mem[9][5]~q  & !\A_SPW_TOP|tx_data|wr_ptr [5])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[41][5]~q  & ( !\A_SPW_TOP|tx_data|mem[1][5]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr 
// [3] & (\A_SPW_TOP|tx_data|mem[33][5]~q  & ((\A_SPW_TOP|tx_data|wr_ptr [5])))) # (\A_SPW_TOP|tx_data|wr_ptr [3] & (((\A_SPW_TOP|tx_data|wr_ptr [5]) # (\A_SPW_TOP|tx_data|mem[9][5]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[41][5]~q  & ( 
// !\A_SPW_TOP|tx_data|mem[1][5]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [3] & (\A_SPW_TOP|tx_data|mem[33][5]~q  & ((\A_SPW_TOP|tx_data|wr_ptr [5])))) # (\A_SPW_TOP|tx_data|wr_ptr [3] & (((\A_SPW_TOP|tx_data|mem[9][5]~q  & !\A_SPW_TOP|tx_data|wr_ptr [5])))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[33][5]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[9][5]~q ),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datae(!\A_SPW_TOP|tx_data|mem[41][5]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[1][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux3~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux3~5 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux3~5 .lut_mask = 64'h0350035FF350F35F;
defparam \A_SPW_TOP|tx_data|Mux3~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y14_N33
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector197~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector197~0_combout  = ( \u0|write_data_fifo_tx|data_out [5] & ( (!\A_SPW_TOP|tx_data|Selector194~0_combout  & (((\A_SPW_TOP|tx_data|mem[21][5]~q )))) # (\A_SPW_TOP|tx_data|Selector194~0_combout  & 
// (((\A_SPW_TOP|tx_data|state_data_write.00~q )) # (\A_SPW_TOP|tx_data|Mux3~20_combout ))) ) ) # ( !\u0|write_data_fifo_tx|data_out [5] & ( (!\A_SPW_TOP|tx_data|Selector194~0_combout  & (((\A_SPW_TOP|tx_data|mem[21][5]~q )))) # 
// (\A_SPW_TOP|tx_data|Selector194~0_combout  & (\A_SPW_TOP|tx_data|Mux3~20_combout  & (!\A_SPW_TOP|tx_data|state_data_write.00~q ))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector194~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|mem[21][5]~q ),
        .datae(gnd),
        .dataf(!\u0|write_data_fifo_tx|data_out [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector197~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector197~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector197~0 .lut_mask = 64'h04F404F407F707F7;
defparam \A_SPW_TOP|tx_data|Selector197~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y14_N8
dffeas \A_SPW_TOP|tx_data|mem[21][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector197~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[21][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[21][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[21][5] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y14_N39
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector269~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector269~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector266~0_combout  & ((\A_SPW_TOP|tx_data|mem[29][5]~q ))) # (\A_SPW_TOP|tx_data|Selector266~0_combout  & (\u0|write_data_fifo_tx|data_out 
// [5])) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector266~0_combout  & ((\A_SPW_TOP|tx_data|mem[29][5]~q ))) # (\A_SPW_TOP|tx_data|Selector266~0_combout  & (\A_SPW_TOP|tx_data|Mux3~20_combout )) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [5]),
        .datab(!\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|mem[29][5]~q ),
        .datad(!\A_SPW_TOP|tx_data|Selector266~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector269~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector269~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector269~0 .lut_mask = 64'h0F330F330F550F55;
defparam \A_SPW_TOP|tx_data|Selector269~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y14_N56
dffeas \A_SPW_TOP|tx_data|mem[29][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector269~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[29][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[29][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[29][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y14_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector485~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector485~0_combout  = ( \A_SPW_TOP|tx_data|Selector482~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux3~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\u0|write_data_fifo_tx|data_out [5])) ) ) # ( !\A_SPW_TOP|tx_data|Selector482~0_combout  & ( \A_SPW_TOP|tx_data|mem[53][5]~q  ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [5]),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[53][5]~q ),
        .datad(!\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector482~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector485~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector485~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector485~0 .lut_mask = 64'h0F0F0F0F11DD11DD;
defparam \A_SPW_TOP|tx_data|Selector485~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y14_N35
dffeas \A_SPW_TOP|tx_data|mem[53][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector485~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[53][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[53][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[53][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y14_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector557~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector557~0_combout  = ( \A_SPW_TOP|tx_data|Selector554~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux3~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [5]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector554~0_combout  & ( \A_SPW_TOP|tx_data|mem[61][5]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\u0|write_data_fifo_tx|data_out [5]),
        .datad(!\A_SPW_TOP|tx_data|mem[61][5]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector554~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector557~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector557~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector557~0 .lut_mask = 64'h00FF00FF47474747;
defparam \A_SPW_TOP|tx_data|Selector557~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y14_N59
dffeas \A_SPW_TOP|tx_data|mem[61][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector557~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[61][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[61][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[61][5] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y14_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux3~8 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux3~8_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [5] & ( \A_SPW_TOP|tx_data|wr_ptr [3] & ( \A_SPW_TOP|tx_data|mem[61][5]~q  ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [5] & ( \A_SPW_TOP|tx_data|wr_ptr [3] & ( \A_SPW_TOP|tx_data|mem[29][5]~q  ) ) 
// ) # ( \A_SPW_TOP|tx_data|wr_ptr [5] & ( !\A_SPW_TOP|tx_data|wr_ptr [3] & ( \A_SPW_TOP|tx_data|mem[53][5]~q  ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [5] & ( !\A_SPW_TOP|tx_data|wr_ptr [3] & ( \A_SPW_TOP|tx_data|mem[21][5]~q  ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[21][5]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[29][5]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[53][5]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[61][5]~q ),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux3~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux3~8 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux3~8 .lut_mask = 64'h55550F0F333300FF;
defparam \A_SPW_TOP|tx_data|Mux3~8 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y14_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux3~9 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux3~9_combout  = ( \A_SPW_TOP|tx_data|Mux3~8_combout  & ( \A_SPW_TOP|tx_data|wr_ptr [2] & ( (\A_SPW_TOP|tx_data|wr_ptr [4]) # (\A_SPW_TOP|tx_data|Mux3~6_combout ) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux3~8_combout  & ( 
// \A_SPW_TOP|tx_data|wr_ptr [2] & ( (\A_SPW_TOP|tx_data|Mux3~6_combout  & !\A_SPW_TOP|tx_data|wr_ptr [4]) ) ) ) # ( \A_SPW_TOP|tx_data|Mux3~8_combout  & ( !\A_SPW_TOP|tx_data|wr_ptr [2] & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & 
// ((\A_SPW_TOP|tx_data|Mux3~5_combout ))) # (\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|Mux3~7_combout )) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux3~8_combout  & ( !\A_SPW_TOP|tx_data|wr_ptr [2] & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & 
// ((\A_SPW_TOP|tx_data|Mux3~5_combout ))) # (\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|Mux3~7_combout )) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux3~7_combout ),
        .datab(!\A_SPW_TOP|tx_data|Mux3~6_combout ),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datad(!\A_SPW_TOP|tx_data|Mux3~5_combout ),
        .datae(!\A_SPW_TOP|tx_data|Mux3~8_combout ),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux3~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux3~9 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux3~9 .lut_mask = 64'h05F505F530303F3F;
defparam \A_SPW_TOP|tx_data|Mux3~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y14_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector575~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector575~0_combout  = ( \A_SPW_TOP|tx_data|mem[63][5]~q  & ( (!\A_SPW_TOP|tx_data|Selector572~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux3~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [5])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[63][5]~q  & ( (\A_SPW_TOP|tx_data|Selector572~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux3~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [5]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\u0|write_data_fifo_tx|data_out [5]),
        .datad(!\A_SPW_TOP|tx_data|Selector572~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[63][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector575~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector575~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector575~0 .lut_mask = 64'h00470047FF47FF47;
defparam \A_SPW_TOP|tx_data|Selector575~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y14_N50
dffeas \A_SPW_TOP|tx_data|mem[63][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector575~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[63][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[63][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[63][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y14_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector539~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector539~0_combout  = ( \A_SPW_TOP|tx_data|mem[59][5]~q  & ( (!\A_SPW_TOP|tx_data|Selector536~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux3~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [5])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[59][5]~q  & ( (\A_SPW_TOP|tx_data|Selector536~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux3~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [5]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\u0|write_data_fifo_tx|data_out [5]),
        .datad(!\A_SPW_TOP|tx_data|Selector536~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[59][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector539~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector539~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector539~0 .lut_mask = 64'h00470047FF47FF47;
defparam \A_SPW_TOP|tx_data|Selector539~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y14_N44
dffeas \A_SPW_TOP|tx_data|mem[59][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector539~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[59][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[59][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[59][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y14_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector467~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector467~0_combout  = ( \A_SPW_TOP|tx_data|mem[51][5]~q  & ( (!\A_SPW_TOP|tx_data|Selector464~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux3~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [5])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[51][5]~q  & ( (\A_SPW_TOP|tx_data|Selector464~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux3~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [5]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .datac(!\u0|write_data_fifo_tx|data_out [5]),
        .datad(!\A_SPW_TOP|tx_data|Selector464~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[51][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector467~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector467~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector467~0 .lut_mask = 64'h00270027FF27FF27;
defparam \A_SPW_TOP|tx_data|Selector467~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y14_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|mem[51][5]~feeder (
// Equation(s):
// \A_SPW_TOP|tx_data|mem[51][5]~feeder_combout  = ( \A_SPW_TOP|tx_data|Selector467~0_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector467~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|mem[51][5]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[51][5]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|mem[51][5]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|tx_data|mem[51][5]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X45_Y14_N14
dffeas \A_SPW_TOP|tx_data|mem[51][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|tx_data|mem[51][5]~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[51][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[51][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[51][5] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y14_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector503~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector503~0_combout  = ( \A_SPW_TOP|tx_data|mem[55][5]~q  & ( (!\A_SPW_TOP|tx_data|Selector500~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux3~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [5]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[55][5]~q  & ( (\A_SPW_TOP|tx_data|Selector500~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux3~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [5])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [5]),
        .datab(!\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector500~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[55][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector503~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector503~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector503~0 .lut_mask = 64'h03050305F3F5F3F5;
defparam \A_SPW_TOP|tx_data|Selector503~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y14_N53
dffeas \A_SPW_TOP|tx_data|mem[55][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector503~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[55][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[55][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[55][5] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y14_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux3~18 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux3~18_combout  = ( \A_SPW_TOP|tx_data|mem[51][5]~q  & ( \A_SPW_TOP|tx_data|mem[55][5]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [3]) # ((!\A_SPW_TOP|tx_data|wr_ptr [2] & ((\A_SPW_TOP|tx_data|mem[59][5]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [2] 
// & (\A_SPW_TOP|tx_data|mem[63][5]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[51][5]~q  & ( \A_SPW_TOP|tx_data|mem[55][5]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [3] & (((\A_SPW_TOP|tx_data|wr_ptr [2])))) # (\A_SPW_TOP|tx_data|wr_ptr [3] & 
// ((!\A_SPW_TOP|tx_data|wr_ptr [2] & ((\A_SPW_TOP|tx_data|mem[59][5]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|mem[63][5]~q )))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[51][5]~q  & ( !\A_SPW_TOP|tx_data|mem[55][5]~q  & ( 
// (!\A_SPW_TOP|tx_data|wr_ptr [3] & (((!\A_SPW_TOP|tx_data|wr_ptr [2])))) # (\A_SPW_TOP|tx_data|wr_ptr [3] & ((!\A_SPW_TOP|tx_data|wr_ptr [2] & ((\A_SPW_TOP|tx_data|mem[59][5]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|mem[63][5]~q )))) ) 
// ) ) # ( !\A_SPW_TOP|tx_data|mem[51][5]~q  & ( !\A_SPW_TOP|tx_data|mem[55][5]~q  & ( (\A_SPW_TOP|tx_data|wr_ptr [3] & ((!\A_SPW_TOP|tx_data|wr_ptr [2] & ((\A_SPW_TOP|tx_data|mem[59][5]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [2] & 
// (\A_SPW_TOP|tx_data|mem[63][5]~q )))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datab(!\A_SPW_TOP|tx_data|mem[63][5]~q ),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datad(!\A_SPW_TOP|tx_data|mem[59][5]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[51][5]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[55][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux3~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux3~18 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux3~18 .lut_mask = 64'h0151A1F10B5BABFB;
defparam \A_SPW_TOP|tx_data|Mux3~18 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y14_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector431~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector431~0_combout  = ( \A_SPW_TOP|tx_data|Selector428~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux3~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\u0|write_data_fifo_tx|data_out [5])) ) ) # ( !\A_SPW_TOP|tx_data|Selector428~0_combout  & ( \A_SPW_TOP|tx_data|mem[47][5]~q  ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [5]),
        .datab(!\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|mem[47][5]~q ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector428~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector431~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector431~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector431~0 .lut_mask = 64'h0F0F0F0F33553355;
defparam \A_SPW_TOP|tx_data|Selector431~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y14_N47
dffeas \A_SPW_TOP|tx_data|mem[47][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector431~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[47][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[47][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[47][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y14_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector359~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector359~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector356~0_combout  & ((\A_SPW_TOP|tx_data|mem[39][5]~q ))) # (\A_SPW_TOP|tx_data|Selector356~0_combout  & (\u0|write_data_fifo_tx|data_out 
// [5])) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector356~0_combout  & ((\A_SPW_TOP|tx_data|mem[39][5]~q ))) # (\A_SPW_TOP|tx_data|Selector356~0_combout  & (\A_SPW_TOP|tx_data|Mux3~20_combout )) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [5]),
        .datab(!\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector356~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|mem[39][5]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector359~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector359~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector359~0 .lut_mask = 64'h03F303F305F505F5;
defparam \A_SPW_TOP|tx_data|Selector359~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y14_N29
dffeas \A_SPW_TOP|tx_data|mem[39][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector359~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[39][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[39][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[39][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y14_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector323~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector323~0_combout  = ( \A_SPW_TOP|tx_data|mem[35][5]~q  & ( (!\A_SPW_TOP|tx_data|Selector320~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux3~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [5]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[35][5]~q  & ( (\A_SPW_TOP|tx_data|Selector320~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux3~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [5])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [5]),
        .datab(!\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector320~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[35][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector323~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector323~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector323~0 .lut_mask = 64'h03050305F3F5F3F5;
defparam \A_SPW_TOP|tx_data|Selector323~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y14_N50
dffeas \A_SPW_TOP|tx_data|mem[35][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector323~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[35][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[35][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[35][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y14_N39
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector395~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector395~0_combout  = ( \A_SPW_TOP|tx_data|Selector392~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux3~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\u0|write_data_fifo_tx|data_out [5])) ) ) # ( !\A_SPW_TOP|tx_data|Selector392~0_combout  & ( \A_SPW_TOP|tx_data|mem[43][5]~q  ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [5]),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[43][5]~q ),
        .datad(!\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector392~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector395~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector395~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector395~0 .lut_mask = 64'h0F0F0F0F11DD11DD;
defparam \A_SPW_TOP|tx_data|Selector395~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y14_N17
dffeas \A_SPW_TOP|tx_data|mem[43][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector395~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[43][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[43][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[43][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y14_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux3~16 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux3~16_combout  = ( \A_SPW_TOP|tx_data|mem[35][5]~q  & ( \A_SPW_TOP|tx_data|mem[43][5]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [2]) # ((!\A_SPW_TOP|tx_data|wr_ptr [3] & ((\A_SPW_TOP|tx_data|mem[39][5]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [3] 
// & (\A_SPW_TOP|tx_data|mem[47][5]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[35][5]~q  & ( \A_SPW_TOP|tx_data|mem[43][5]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & (((\A_SPW_TOP|tx_data|wr_ptr [3])))) # (\A_SPW_TOP|tx_data|wr_ptr [2] & 
// ((!\A_SPW_TOP|tx_data|wr_ptr [3] & ((\A_SPW_TOP|tx_data|mem[39][5]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [3] & (\A_SPW_TOP|tx_data|mem[47][5]~q )))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[35][5]~q  & ( !\A_SPW_TOP|tx_data|mem[43][5]~q  & ( 
// (!\A_SPW_TOP|tx_data|wr_ptr [2] & (((!\A_SPW_TOP|tx_data|wr_ptr [3])))) # (\A_SPW_TOP|tx_data|wr_ptr [2] & ((!\A_SPW_TOP|tx_data|wr_ptr [3] & ((\A_SPW_TOP|tx_data|mem[39][5]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [3] & (\A_SPW_TOP|tx_data|mem[47][5]~q )))) ) 
// ) ) # ( !\A_SPW_TOP|tx_data|mem[35][5]~q  & ( !\A_SPW_TOP|tx_data|mem[43][5]~q  & ( (\A_SPW_TOP|tx_data|wr_ptr [2] & ((!\A_SPW_TOP|tx_data|wr_ptr [3] & ((\A_SPW_TOP|tx_data|mem[39][5]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [3] & 
// (\A_SPW_TOP|tx_data|mem[47][5]~q )))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datab(!\A_SPW_TOP|tx_data|mem[47][5]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[39][5]~q ),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datae(!\A_SPW_TOP|tx_data|mem[35][5]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[43][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux3~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux3~16 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux3~16 .lut_mask = 64'h0511AF1105BBAFBB;
defparam \A_SPW_TOP|tx_data|Mux3~16 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y14_N57
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector35~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector35~0_combout  = ( \A_SPW_TOP|tx_data|mem[3][5]~q  & ( (!\A_SPW_TOP|tx_data|Selector32~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux3~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [5]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[3][5]~q  & ( (\A_SPW_TOP|tx_data|Selector32~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux3~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [5])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [5]),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector32~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[3][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector35~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector35~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector35~0 .lut_mask = 64'h010D010DF1FDF1FD;
defparam \A_SPW_TOP|tx_data|Selector35~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y14_N53
dffeas \A_SPW_TOP|tx_data|mem[3][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector35~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[3][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[3][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[3][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y14_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector107~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector107~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector104~0_combout  & ((\A_SPW_TOP|tx_data|mem[11][5]~q ))) # (\A_SPW_TOP|tx_data|Selector104~0_combout  & (\u0|write_data_fifo_tx|data_out 
// [5])) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector104~0_combout  & ((\A_SPW_TOP|tx_data|mem[11][5]~q ))) # (\A_SPW_TOP|tx_data|Selector104~0_combout  & (\A_SPW_TOP|tx_data|Mux3~20_combout )) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [5]),
        .datab(!\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector104~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|mem[11][5]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector107~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector107~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector107~0 .lut_mask = 64'h03F303F305F505F5;
defparam \A_SPW_TOP|tx_data|Selector107~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y14_N29
dffeas \A_SPW_TOP|tx_data|mem[11][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector107~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[11][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[11][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[11][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y14_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector143~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector143~0_combout  = ( \A_SPW_TOP|tx_data|mem[15][5]~q  & ( (!\A_SPW_TOP|tx_data|Selector140~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux3~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [5]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[15][5]~q  & ( (\A_SPW_TOP|tx_data|Selector140~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux3~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [5])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [5]),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector140~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[15][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector143~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector143~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector143~0 .lut_mask = 64'h010D010DF1FDF1FD;
defparam \A_SPW_TOP|tx_data|Selector143~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y14_N14
dffeas \A_SPW_TOP|tx_data|mem[15][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector143~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[15][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[15][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[15][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y14_N21
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector71~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector71~0_combout  = ( \A_SPW_TOP|tx_data|Selector68~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux3~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\u0|write_data_fifo_tx|data_out [5])) ) ) # ( !\A_SPW_TOP|tx_data|Selector68~0_combout  & ( \A_SPW_TOP|tx_data|mem[7][5]~q  ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [5]),
        .datab(!\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|mem[7][5]~q ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector68~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector71~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector71~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector71~0 .lut_mask = 64'h0F0F0F0F33553355;
defparam \A_SPW_TOP|tx_data|Selector71~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y14_N11
dffeas \A_SPW_TOP|tx_data|mem[7][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector71~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[7][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[7][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[7][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y14_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux3~15 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux3~15_combout  = ( \A_SPW_TOP|tx_data|mem[15][5]~q  & ( \A_SPW_TOP|tx_data|mem[7][5]~q  & ( ((!\A_SPW_TOP|tx_data|wr_ptr [3] & (\A_SPW_TOP|tx_data|mem[3][5]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [3] & ((\A_SPW_TOP|tx_data|mem[11][5]~q 
// )))) # (\A_SPW_TOP|tx_data|wr_ptr [2]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[15][5]~q  & ( \A_SPW_TOP|tx_data|mem[7][5]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & ((!\A_SPW_TOP|tx_data|wr_ptr [3] & (\A_SPW_TOP|tx_data|mem[3][5]~q )) # (\A_SPW_TOP|tx_data|wr_ptr 
// [3] & ((\A_SPW_TOP|tx_data|mem[11][5]~q ))))) # (\A_SPW_TOP|tx_data|wr_ptr [2] & (((!\A_SPW_TOP|tx_data|wr_ptr [3])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[15][5]~q  & ( !\A_SPW_TOP|tx_data|mem[7][5]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & 
// ((!\A_SPW_TOP|tx_data|wr_ptr [3] & (\A_SPW_TOP|tx_data|mem[3][5]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [3] & ((\A_SPW_TOP|tx_data|mem[11][5]~q ))))) # (\A_SPW_TOP|tx_data|wr_ptr [2] & (((\A_SPW_TOP|tx_data|wr_ptr [3])))) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|mem[15][5]~q  & ( !\A_SPW_TOP|tx_data|mem[7][5]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & ((!\A_SPW_TOP|tx_data|wr_ptr [3] & (\A_SPW_TOP|tx_data|mem[3][5]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [3] & ((\A_SPW_TOP|tx_data|mem[11][5]~q ))))) ) 
// ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[3][5]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[11][5]~q ),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datae(!\A_SPW_TOP|tx_data|mem[15][5]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[7][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux3~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux3~15 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux3~15 .lut_mask = 64'h5030503F5F305F3F;
defparam \A_SPW_TOP|tx_data|Mux3~15 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y14_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector215~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector215~0_combout  = ( \A_SPW_TOP|tx_data|Selector212~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux3~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\u0|write_data_fifo_tx|data_out [5])) ) ) # ( !\A_SPW_TOP|tx_data|Selector212~0_combout  & ( \A_SPW_TOP|tx_data|mem[23][5]~q  ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [5]),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[23][5]~q ),
        .datad(!\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector212~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector215~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector215~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector215~0 .lut_mask = 64'h0F0F0F0F11DD11DD;
defparam \A_SPW_TOP|tx_data|Selector215~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y14_N29
dffeas \A_SPW_TOP|tx_data|mem[23][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector215~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[23][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[23][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[23][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y14_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector251~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector251~0_combout  = ( \A_SPW_TOP|tx_data|Selector248~0_combout  & ( \A_SPW_TOP|tx_data|Mux3~20_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q ) # (\u0|write_data_fifo_tx|data_out [5]) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|Selector248~0_combout  & ( \A_SPW_TOP|tx_data|Mux3~20_combout  & ( \A_SPW_TOP|tx_data|mem[27][5]~q  ) ) ) # ( \A_SPW_TOP|tx_data|Selector248~0_combout  & ( !\A_SPW_TOP|tx_data|Mux3~20_combout  & ( (\u0|write_data_fifo_tx|data_out [5] & 
// \A_SPW_TOP|tx_data|state_data_write.00~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|Selector248~0_combout  & ( !\A_SPW_TOP|tx_data|Mux3~20_combout  & ( \A_SPW_TOP|tx_data|mem[27][5]~q  ) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [5]),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[27][5]~q ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|tx_data|Selector248~0_combout ),
        .dataf(!\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector251~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector251~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector251~0 .lut_mask = 64'h0F0F11110F0FDDDD;
defparam \A_SPW_TOP|tx_data|Selector251~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y14_N26
dffeas \A_SPW_TOP|tx_data|mem[27][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector251~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[27][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[27][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[27][5] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y14_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector287~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector287~0_combout  = ( \A_SPW_TOP|tx_data|mem[31][5]~q  & ( (!\A_SPW_TOP|tx_data|Selector284~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux3~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [5]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[31][5]~q  & ( (\A_SPW_TOP|tx_data|Selector284~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux3~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [5])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [5]),
        .datab(!\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|tx_data|Selector284~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[31][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector287~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector287~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector287~0 .lut_mask = 64'h00350035FF35FF35;
defparam \A_SPW_TOP|tx_data|Selector287~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y14_N17
dffeas \A_SPW_TOP|tx_data|mem[31][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector287~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[31][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[31][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[31][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y14_N45
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector179~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector179~0_combout  = ( \A_SPW_TOP|tx_data|Selector176~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux3~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [5]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector176~0_combout  & ( \A_SPW_TOP|tx_data|mem[19][5]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|mem[19][5]~q ),
        .datad(!\u0|write_data_fifo_tx|data_out [5]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector176~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector179~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector179~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector179~0 .lut_mask = 64'h0F0F0F0F22772277;
defparam \A_SPW_TOP|tx_data|Selector179~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X45_Y14_N11
dffeas \A_SPW_TOP|tx_data|mem[19][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector179~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[19][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[19][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[19][5] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y14_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux3~17 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux3~17_combout  = ( \A_SPW_TOP|tx_data|mem[19][5]~q  & ( \A_SPW_TOP|tx_data|wr_ptr [3] & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|mem[27][5]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [2] & ((\A_SPW_TOP|tx_data|mem[31][5]~q ))) ) 
// ) ) # ( !\A_SPW_TOP|tx_data|mem[19][5]~q  & ( \A_SPW_TOP|tx_data|wr_ptr [3] & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & (\A_SPW_TOP|tx_data|mem[27][5]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [2] & ((\A_SPW_TOP|tx_data|mem[31][5]~q ))) ) ) ) # ( 
// \A_SPW_TOP|tx_data|mem[19][5]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [3] & ( (!\A_SPW_TOP|tx_data|wr_ptr [2]) # (\A_SPW_TOP|tx_data|mem[23][5]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[19][5]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [3] & ( 
// (\A_SPW_TOP|tx_data|mem[23][5]~q  & \A_SPW_TOP|tx_data|wr_ptr [2]) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[23][5]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[27][5]~q ),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datad(!\A_SPW_TOP|tx_data|mem[31][5]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[19][5]~q ),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux3~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux3~17 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux3~17 .lut_mask = 64'h0505F5F5303F303F;
defparam \A_SPW_TOP|tx_data|Mux3~17 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y14_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux3~19 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux3~19_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [5] & ( \A_SPW_TOP|tx_data|Mux3~17_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & ((\A_SPW_TOP|tx_data|Mux3~16_combout ))) # (\A_SPW_TOP|tx_data|wr_ptr [4] & 
// (\A_SPW_TOP|tx_data|Mux3~18_combout )) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [5] & ( \A_SPW_TOP|tx_data|Mux3~17_combout  & ( (\A_SPW_TOP|tx_data|wr_ptr [4]) # (\A_SPW_TOP|tx_data|Mux3~15_combout ) ) ) ) # ( \A_SPW_TOP|tx_data|wr_ptr [5] & ( 
// !\A_SPW_TOP|tx_data|Mux3~17_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [4] & ((\A_SPW_TOP|tx_data|Mux3~16_combout ))) # (\A_SPW_TOP|tx_data|wr_ptr [4] & (\A_SPW_TOP|tx_data|Mux3~18_combout )) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [5] & ( 
// !\A_SPW_TOP|tx_data|Mux3~17_combout  & ( (\A_SPW_TOP|tx_data|Mux3~15_combout  & !\A_SPW_TOP|tx_data|wr_ptr [4]) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux3~18_combout ),
        .datab(!\A_SPW_TOP|tx_data|Mux3~16_combout ),
        .datac(!\A_SPW_TOP|tx_data|Mux3~15_combout ),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .dataf(!\A_SPW_TOP|tx_data|Mux3~17_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux3~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux3~19 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux3~19 .lut_mask = 64'h0F0033550FFF3355;
defparam \A_SPW_TOP|tx_data|Mux3~19 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y14_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux3~20 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux3~20_combout  = ( \A_SPW_TOP|tx_data|Mux3~19_combout  & ( \A_SPW_TOP|tx_data|wr_ptr [1] & ( (\A_SPW_TOP|tx_data|wr_ptr [0]) # (\A_SPW_TOP|tx_data|Mux3~14_combout ) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux3~19_combout  & ( 
// \A_SPW_TOP|tx_data|wr_ptr [1] & ( (\A_SPW_TOP|tx_data|Mux3~14_combout  & !\A_SPW_TOP|tx_data|wr_ptr [0]) ) ) ) # ( \A_SPW_TOP|tx_data|Mux3~19_combout  & ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & 
// (\A_SPW_TOP|tx_data|Mux3~4_combout )) # (\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|Mux3~9_combout ))) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux3~19_combout  & ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & 
// (\A_SPW_TOP|tx_data|Mux3~4_combout )) # (\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|Mux3~9_combout ))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux3~14_combout ),
        .datab(!\A_SPW_TOP|tx_data|Mux3~4_combout ),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datad(!\A_SPW_TOP|tx_data|Mux3~9_combout ),
        .datae(!\A_SPW_TOP|tx_data|Mux3~19_combout ),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux3~20 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux3~20 .lut_mask = 64'h303F303F50505F5F;
defparam \A_SPW_TOP|tx_data|Mux3~20 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y14_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector548~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector548~0_combout  = ( \u0|write_data_fifo_tx|data_out [5] & ( (!\A_SPW_TOP|tx_data|Selector545~0_combout  & (((\A_SPW_TOP|tx_data|mem[60][5]~q )))) # (\A_SPW_TOP|tx_data|Selector545~0_combout  & 
// (((\A_SPW_TOP|tx_data|Mux3~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q ))) ) ) # ( !\u0|write_data_fifo_tx|data_out [5] & ( (!\A_SPW_TOP|tx_data|Selector545~0_combout  & (((\A_SPW_TOP|tx_data|mem[60][5]~q )))) # 
// (\A_SPW_TOP|tx_data|Selector545~0_combout  & (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux3~20_combout ))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux3~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|mem[60][5]~q ),
        .datad(!\A_SPW_TOP|tx_data|Selector545~0_combout ),
        .datae(gnd),
        .dataf(!\u0|write_data_fifo_tx|data_out [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector548~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector548~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector548~0 .lut_mask = 64'h0F220F220F770F77;
defparam \A_SPW_TOP|tx_data|Selector548~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y14_N29
dffeas \A_SPW_TOP|tx_data|mem[60][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector548~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[60][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[60][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[60][5] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y14_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux12~6 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux12~6_combout  = ( \A_SPW_TOP|tx_data|mem[28][5]~q  & ( \A_SPW_TOP|tx_data|mem[20][5]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5]) # ((!\A_SPW_TOP|tx_data|rd_ptr [3] & ((\A_SPW_TOP|tx_data|mem[52][5]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [3] 
// & (\A_SPW_TOP|tx_data|mem[60][5]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[28][5]~q  & ( \A_SPW_TOP|tx_data|mem[20][5]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & (((!\A_SPW_TOP|tx_data|rd_ptr [3])))) # (\A_SPW_TOP|tx_data|rd_ptr [5] & 
// ((!\A_SPW_TOP|tx_data|rd_ptr [3] & ((\A_SPW_TOP|tx_data|mem[52][5]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [3] & (\A_SPW_TOP|tx_data|mem[60][5]~q )))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[28][5]~q  & ( !\A_SPW_TOP|tx_data|mem[20][5]~q  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [5] & (((\A_SPW_TOP|tx_data|rd_ptr [3])))) # (\A_SPW_TOP|tx_data|rd_ptr [5] & ((!\A_SPW_TOP|tx_data|rd_ptr [3] & ((\A_SPW_TOP|tx_data|mem[52][5]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [3] & (\A_SPW_TOP|tx_data|mem[60][5]~q )))) ) ) 
// ) # ( !\A_SPW_TOP|tx_data|mem[28][5]~q  & ( !\A_SPW_TOP|tx_data|mem[20][5]~q  & ( (\A_SPW_TOP|tx_data|rd_ptr [5] & ((!\A_SPW_TOP|tx_data|rd_ptr [3] & ((\A_SPW_TOP|tx_data|mem[52][5]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [3] & (\A_SPW_TOP|tx_data|mem[60][5]~q 
// )))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[60][5]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[52][5]~q ),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [5]),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [3]),
        .datae(!\A_SPW_TOP|tx_data|mem[28][5]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[20][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux12~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux12~6 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux12~6 .lut_mask = 64'h030503F5F305F3F5;
defparam \A_SPW_TOP|tx_data|Mux12~6 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y14_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux12~7 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux12~7_combout  = ( \A_SPW_TOP|tx_data|mem[50][5]~q  & ( \A_SPW_TOP|tx_data|mem[58][5]~q  & ( ((!\A_SPW_TOP|tx_data|rd_ptr [3] & ((\A_SPW_TOP|tx_data|mem[18][5]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [3] & (\A_SPW_TOP|tx_data|mem[26][5]~q 
// ))) # (\A_SPW_TOP|tx_data|rd_ptr [5]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[50][5]~q  & ( \A_SPW_TOP|tx_data|mem[58][5]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [3] & (((\A_SPW_TOP|tx_data|mem[18][5]~q  & !\A_SPW_TOP|tx_data|rd_ptr [5])))) # 
// (\A_SPW_TOP|tx_data|rd_ptr [3] & (((\A_SPW_TOP|tx_data|rd_ptr [5])) # (\A_SPW_TOP|tx_data|mem[26][5]~q ))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[50][5]~q  & ( !\A_SPW_TOP|tx_data|mem[58][5]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [3] & (((\A_SPW_TOP|tx_data|rd_ptr 
// [5]) # (\A_SPW_TOP|tx_data|mem[18][5]~q )))) # (\A_SPW_TOP|tx_data|rd_ptr [3] & (\A_SPW_TOP|tx_data|mem[26][5]~q  & ((!\A_SPW_TOP|tx_data|rd_ptr [5])))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[50][5]~q  & ( !\A_SPW_TOP|tx_data|mem[58][5]~q  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [5] & ((!\A_SPW_TOP|tx_data|rd_ptr [3] & ((\A_SPW_TOP|tx_data|mem[18][5]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [3] & (\A_SPW_TOP|tx_data|mem[26][5]~q )))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[26][5]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[18][5]~q ),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [3]),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [5]),
        .datae(!\A_SPW_TOP|tx_data|mem[50][5]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[58][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux12~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux12~7 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux12~7 .lut_mask = 64'h350035F0350F35FF;
defparam \A_SPW_TOP|tx_data|Mux12~7 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y14_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux12~5 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux12~5_combout  = ( \A_SPW_TOP|tx_data|rd_ptr [5] & ( \A_SPW_TOP|tx_data|rd_ptr [3] & ( \A_SPW_TOP|tx_data|mem[56][5]~q  ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [5] & ( \A_SPW_TOP|tx_data|rd_ptr [3] & ( \A_SPW_TOP|tx_data|mem[24][5]~q  ) 
// ) ) # ( \A_SPW_TOP|tx_data|rd_ptr [5] & ( !\A_SPW_TOP|tx_data|rd_ptr [3] & ( \A_SPW_TOP|tx_data|mem[48][5]~q  ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [5] & ( !\A_SPW_TOP|tx_data|rd_ptr [3] & ( \A_SPW_TOP|tx_data|mem[16][5]~q  ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[48][5]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[24][5]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[56][5]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[16][5]~q ),
        .datae(!\A_SPW_TOP|tx_data|rd_ptr [5]),
        .dataf(!\A_SPW_TOP|tx_data|rd_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux12~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux12~5 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux12~5 .lut_mask = 64'h00FF555533330F0F;
defparam \A_SPW_TOP|tx_data|Mux12~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y14_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux12~8 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux12~8_combout  = ( \A_SPW_TOP|tx_data|mem[54][5]~q  & ( \A_SPW_TOP|tx_data|mem[22][5]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [3]) # ((!\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|mem[30][5]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [5] & 
// ((\A_SPW_TOP|tx_data|mem[62][5]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[54][5]~q  & ( \A_SPW_TOP|tx_data|mem[22][5]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [3] & (((!\A_SPW_TOP|tx_data|rd_ptr [5])))) # (\A_SPW_TOP|tx_data|rd_ptr [3] & 
// ((!\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|mem[30][5]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [5] & ((\A_SPW_TOP|tx_data|mem[62][5]~q ))))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[54][5]~q  & ( !\A_SPW_TOP|tx_data|mem[22][5]~q  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [3] & (((\A_SPW_TOP|tx_data|rd_ptr [5])))) # (\A_SPW_TOP|tx_data|rd_ptr [3] & ((!\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|mem[30][5]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [5] & ((\A_SPW_TOP|tx_data|mem[62][5]~q ))))) ) ) 
// ) # ( !\A_SPW_TOP|tx_data|mem[54][5]~q  & ( !\A_SPW_TOP|tx_data|mem[22][5]~q  & ( (\A_SPW_TOP|tx_data|rd_ptr [3] & ((!\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|mem[30][5]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [5] & ((\A_SPW_TOP|tx_data|mem[62][5]~q 
// ))))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [3]),
        .datab(!\A_SPW_TOP|tx_data|mem[30][5]~q ),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [5]),
        .datad(!\A_SPW_TOP|tx_data|mem[62][5]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[54][5]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[22][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux12~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux12~8 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux12~8 .lut_mask = 64'h10151A1FB0B5BABF;
defparam \A_SPW_TOP|tx_data|Mux12~8 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y14_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux12~9 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux12~9_combout  = ( \A_SPW_TOP|tx_data|rd_ptr [2] & ( \A_SPW_TOP|tx_data|Mux12~8_combout  & ( (\A_SPW_TOP|tx_data|rd_ptr [1]) # (\A_SPW_TOP|tx_data|Mux12~6_combout ) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [2] & ( 
// \A_SPW_TOP|tx_data|Mux12~8_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [1] & ((\A_SPW_TOP|tx_data|Mux12~5_combout ))) # (\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|Mux12~7_combout )) ) ) ) # ( \A_SPW_TOP|tx_data|rd_ptr [2] & ( 
// !\A_SPW_TOP|tx_data|Mux12~8_combout  & ( (\A_SPW_TOP|tx_data|Mux12~6_combout  & !\A_SPW_TOP|tx_data|rd_ptr [1]) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [2] & ( !\A_SPW_TOP|tx_data|Mux12~8_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [1] & 
// ((\A_SPW_TOP|tx_data|Mux12~5_combout ))) # (\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|Mux12~7_combout )) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux12~6_combout ),
        .datab(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .datac(!\A_SPW_TOP|tx_data|Mux12~7_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux12~5_combout ),
        .datae(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .dataf(!\A_SPW_TOP|tx_data|Mux12~8_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux12~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux12~9 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux12~9 .lut_mask = 64'h03CF444403CF7777;
defparam \A_SPW_TOP|tx_data|Mux12~9 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y14_N33
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux12~17 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux12~17_combout  = ( \A_SPW_TOP|tx_data|mem[21][5]~q  & ( \A_SPW_TOP|tx_data|mem[55][5]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [1] & (((!\A_SPW_TOP|tx_data|rd_ptr [5])) # (\A_SPW_TOP|tx_data|mem[53][5]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr 
// [1] & (((\A_SPW_TOP|tx_data|mem[23][5]~q ) # (\A_SPW_TOP|tx_data|rd_ptr [5])))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[21][5]~q  & ( \A_SPW_TOP|tx_data|mem[55][5]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|mem[53][5]~q  & 
// (\A_SPW_TOP|tx_data|rd_ptr [5]))) # (\A_SPW_TOP|tx_data|rd_ptr [1] & (((\A_SPW_TOP|tx_data|mem[23][5]~q ) # (\A_SPW_TOP|tx_data|rd_ptr [5])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[21][5]~q  & ( !\A_SPW_TOP|tx_data|mem[55][5]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr 
// [1] & (((!\A_SPW_TOP|tx_data|rd_ptr [5])) # (\A_SPW_TOP|tx_data|mem[53][5]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [1] & (((!\A_SPW_TOP|tx_data|rd_ptr [5] & \A_SPW_TOP|tx_data|mem[23][5]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[21][5]~q  & ( 
// !\A_SPW_TOP|tx_data|mem[55][5]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|mem[53][5]~q  & (\A_SPW_TOP|tx_data|rd_ptr [5]))) # (\A_SPW_TOP|tx_data|rd_ptr [1] & (((!\A_SPW_TOP|tx_data|rd_ptr [5] & \A_SPW_TOP|tx_data|mem[23][5]~q )))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[53][5]~q ),
        .datab(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [5]),
        .datad(!\A_SPW_TOP|tx_data|mem[23][5]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[21][5]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[55][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux12~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux12~17 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux12~17 .lut_mask = 64'h0434C4F40737C7F7;
defparam \A_SPW_TOP|tx_data|Mux12~17 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y14_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux12~16 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux12~16_combout  = ( \A_SPW_TOP|tx_data|mem[25][5]~q  & ( \A_SPW_TOP|tx_data|mem[57][5]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [1]) # ((!\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|mem[27][5]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [5] & 
// ((\A_SPW_TOP|tx_data|mem[59][5]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[25][5]~q  & ( \A_SPW_TOP|tx_data|mem[57][5]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|mem[27][5]~q ))) # 
// (\A_SPW_TOP|tx_data|rd_ptr [5] & ((!\A_SPW_TOP|tx_data|rd_ptr [1]) # ((\A_SPW_TOP|tx_data|mem[59][5]~q )))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[25][5]~q  & ( !\A_SPW_TOP|tx_data|mem[57][5]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & ((!\A_SPW_TOP|tx_data|rd_ptr 
// [1]) # ((\A_SPW_TOP|tx_data|mem[27][5]~q )))) # (\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|rd_ptr [1] & ((\A_SPW_TOP|tx_data|mem[59][5]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[25][5]~q  & ( !\A_SPW_TOP|tx_data|mem[57][5]~q  & ( 
// (\A_SPW_TOP|tx_data|rd_ptr [1] & ((!\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|mem[27][5]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [5] & ((\A_SPW_TOP|tx_data|mem[59][5]~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [5]),
        .datab(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .datac(!\A_SPW_TOP|tx_data|mem[27][5]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[59][5]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[25][5]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[57][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux12~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux12~16 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux12~16 .lut_mask = 64'h02138A9B4657CEDF;
defparam \A_SPW_TOP|tx_data|Mux12~16 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y14_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux12~18 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux12~18_combout  = ( \A_SPW_TOP|tx_data|mem[29][5]~q  & ( \A_SPW_TOP|tx_data|rd_ptr [5] & ( (!\A_SPW_TOP|tx_data|rd_ptr [1] & ((\A_SPW_TOP|tx_data|mem[61][5]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|mem[63][5]~q )) 
// ) ) ) # ( !\A_SPW_TOP|tx_data|mem[29][5]~q  & ( \A_SPW_TOP|tx_data|rd_ptr [5] & ( (!\A_SPW_TOP|tx_data|rd_ptr [1] & ((\A_SPW_TOP|tx_data|mem[61][5]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|mem[63][5]~q )) ) ) ) # ( 
// \A_SPW_TOP|tx_data|mem[29][5]~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [5] & ( (!\A_SPW_TOP|tx_data|rd_ptr [1]) # (\A_SPW_TOP|tx_data|mem[31][5]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[29][5]~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [5] & ( 
// (\A_SPW_TOP|tx_data|mem[31][5]~q  & \A_SPW_TOP|tx_data|rd_ptr [1]) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[63][5]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[61][5]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[31][5]~q ),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .datae(!\A_SPW_TOP|tx_data|mem[29][5]~q ),
        .dataf(!\A_SPW_TOP|tx_data|rd_ptr [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux12~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux12~18 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux12~18 .lut_mask = 64'h000FFF0F33553355;
defparam \A_SPW_TOP|tx_data|Mux12~18 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y14_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux12~15 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux12~15_combout  = ( \A_SPW_TOP|tx_data|rd_ptr [1] & ( \A_SPW_TOP|tx_data|mem[19][5]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5]) # (\A_SPW_TOP|tx_data|mem[51][5]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [1] & ( 
// \A_SPW_TOP|tx_data|mem[19][5]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & ((\A_SPW_TOP|tx_data|mem[17][5]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|mem[49][5]~q )) ) ) ) # ( \A_SPW_TOP|tx_data|rd_ptr [1] & ( 
// !\A_SPW_TOP|tx_data|mem[19][5]~q  & ( (\A_SPW_TOP|tx_data|rd_ptr [5] & \A_SPW_TOP|tx_data|mem[51][5]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [1] & ( !\A_SPW_TOP|tx_data|mem[19][5]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & ((\A_SPW_TOP|tx_data|mem[17][5]~q 
// ))) # (\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|mem[49][5]~q )) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [5]),
        .datab(!\A_SPW_TOP|tx_data|mem[51][5]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[49][5]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[17][5]~q ),
        .datae(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .dataf(!\A_SPW_TOP|tx_data|mem[19][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux12~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux12~15 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux12~15 .lut_mask = 64'h05AF111105AFBBBB;
defparam \A_SPW_TOP|tx_data|Mux12~15 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y14_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux12~19 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux12~19_combout  = ( \A_SPW_TOP|tx_data|Mux12~18_combout  & ( \A_SPW_TOP|tx_data|Mux12~15_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & (((!\A_SPW_TOP|tx_data|rd_ptr [3]) # (\A_SPW_TOP|tx_data|Mux12~16_combout )))) # 
// (\A_SPW_TOP|tx_data|rd_ptr [2] & (((\A_SPW_TOP|tx_data|rd_ptr [3])) # (\A_SPW_TOP|tx_data|Mux12~17_combout ))) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux12~18_combout  & ( \A_SPW_TOP|tx_data|Mux12~15_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & 
// (((!\A_SPW_TOP|tx_data|rd_ptr [3]) # (\A_SPW_TOP|tx_data|Mux12~16_combout )))) # (\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|Mux12~17_combout  & (!\A_SPW_TOP|tx_data|rd_ptr [3]))) ) ) ) # ( \A_SPW_TOP|tx_data|Mux12~18_combout  & ( 
// !\A_SPW_TOP|tx_data|Mux12~15_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & (((\A_SPW_TOP|tx_data|rd_ptr [3] & \A_SPW_TOP|tx_data|Mux12~16_combout )))) # (\A_SPW_TOP|tx_data|rd_ptr [2] & (((\A_SPW_TOP|tx_data|rd_ptr [3])) # 
// (\A_SPW_TOP|tx_data|Mux12~17_combout ))) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux12~18_combout  & ( !\A_SPW_TOP|tx_data|Mux12~15_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & (((\A_SPW_TOP|tx_data|rd_ptr [3] & \A_SPW_TOP|tx_data|Mux12~16_combout )))) # 
// (\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|Mux12~17_combout  & (!\A_SPW_TOP|tx_data|rd_ptr [3]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .datab(!\A_SPW_TOP|tx_data|Mux12~17_combout ),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [3]),
        .datad(!\A_SPW_TOP|tx_data|Mux12~16_combout ),
        .datae(!\A_SPW_TOP|tx_data|Mux12~18_combout ),
        .dataf(!\A_SPW_TOP|tx_data|Mux12~15_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux12~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux12~19 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux12~19 .lut_mask = 64'h101A151FB0BAB5BF;
defparam \A_SPW_TOP|tx_data|Mux12~19 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y14_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux12~13 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux12~13_combout  = ( \A_SPW_TOP|tx_data|mem[47][5]~q  & ( \A_SPW_TOP|tx_data|mem[7][5]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [3] & (((!\A_SPW_TOP|tx_data|rd_ptr [5])) # (\A_SPW_TOP|tx_data|mem[39][5]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [3] 
// & (((\A_SPW_TOP|tx_data|rd_ptr [5]) # (\A_SPW_TOP|tx_data|mem[15][5]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[47][5]~q  & ( \A_SPW_TOP|tx_data|mem[7][5]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [3] & (((!\A_SPW_TOP|tx_data|rd_ptr [5])) # 
// (\A_SPW_TOP|tx_data|mem[39][5]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [3] & (((\A_SPW_TOP|tx_data|mem[15][5]~q  & !\A_SPW_TOP|tx_data|rd_ptr [5])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[47][5]~q  & ( !\A_SPW_TOP|tx_data|mem[7][5]~q  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [3] & (\A_SPW_TOP|tx_data|mem[39][5]~q  & ((\A_SPW_TOP|tx_data|rd_ptr [5])))) # (\A_SPW_TOP|tx_data|rd_ptr [3] & (((\A_SPW_TOP|tx_data|rd_ptr [5]) # (\A_SPW_TOP|tx_data|mem[15][5]~q )))) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|mem[47][5]~q  & ( !\A_SPW_TOP|tx_data|mem[7][5]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [3] & (\A_SPW_TOP|tx_data|mem[39][5]~q  & ((\A_SPW_TOP|tx_data|rd_ptr [5])))) # (\A_SPW_TOP|tx_data|rd_ptr [3] & (((\A_SPW_TOP|tx_data|mem[15][5]~q  & 
// !\A_SPW_TOP|tx_data|rd_ptr [5])))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[39][5]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[15][5]~q ),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [3]),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [5]),
        .datae(!\A_SPW_TOP|tx_data|mem[47][5]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[7][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux12~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux12~13 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux12~13 .lut_mask = 64'h0350035FF350F35F;
defparam \A_SPW_TOP|tx_data|Mux12~13 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y14_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux12~11 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux12~11_combout  = ( \A_SPW_TOP|tx_data|rd_ptr [5] & ( \A_SPW_TOP|tx_data|rd_ptr [3] & ( \A_SPW_TOP|tx_data|mem[45][5]~q  ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [5] & ( \A_SPW_TOP|tx_data|rd_ptr [3] & ( \A_SPW_TOP|tx_data|mem[13][5]~q  ) 
// ) ) # ( \A_SPW_TOP|tx_data|rd_ptr [5] & ( !\A_SPW_TOP|tx_data|rd_ptr [3] & ( \A_SPW_TOP|tx_data|mem[37][5]~q  ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [5] & ( !\A_SPW_TOP|tx_data|rd_ptr [3] & ( \A_SPW_TOP|tx_data|mem[5][5]~q  ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[5][5]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[13][5]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[37][5]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[45][5]~q ),
        .datae(!\A_SPW_TOP|tx_data|rd_ptr [5]),
        .dataf(!\A_SPW_TOP|tx_data|rd_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux12~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux12~11 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux12~11 .lut_mask = 64'h55550F0F333300FF;
defparam \A_SPW_TOP|tx_data|Mux12~11 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y14_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux12~12 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux12~12_combout  = ( \A_SPW_TOP|tx_data|mem[11][5]~q  & ( \A_SPW_TOP|tx_data|mem[35][5]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & (((\A_SPW_TOP|tx_data|rd_ptr [3])) # (\A_SPW_TOP|tx_data|mem[3][5]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [5] 
// & (((!\A_SPW_TOP|tx_data|rd_ptr [3]) # (\A_SPW_TOP|tx_data|mem[43][5]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[11][5]~q  & ( \A_SPW_TOP|tx_data|mem[35][5]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|mem[3][5]~q  & 
// (!\A_SPW_TOP|tx_data|rd_ptr [3]))) # (\A_SPW_TOP|tx_data|rd_ptr [5] & (((!\A_SPW_TOP|tx_data|rd_ptr [3]) # (\A_SPW_TOP|tx_data|mem[43][5]~q )))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[11][5]~q  & ( !\A_SPW_TOP|tx_data|mem[35][5]~q  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [5] & (((\A_SPW_TOP|tx_data|rd_ptr [3])) # (\A_SPW_TOP|tx_data|mem[3][5]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [5] & (((\A_SPW_TOP|tx_data|rd_ptr [3] & \A_SPW_TOP|tx_data|mem[43][5]~q )))) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|mem[11][5]~q  & ( !\A_SPW_TOP|tx_data|mem[35][5]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|mem[3][5]~q  & (!\A_SPW_TOP|tx_data|rd_ptr [3]))) # (\A_SPW_TOP|tx_data|rd_ptr [5] & (((\A_SPW_TOP|tx_data|rd_ptr [3] & 
// \A_SPW_TOP|tx_data|mem[43][5]~q )))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[3][5]~q ),
        .datab(!\A_SPW_TOP|tx_data|rd_ptr [5]),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [3]),
        .datad(!\A_SPW_TOP|tx_data|mem[43][5]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[11][5]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[35][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux12~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux12~12 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux12~12 .lut_mask = 64'h40434C4F70737C7F;
defparam \A_SPW_TOP|tx_data|Mux12~12 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y14_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux12~10 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux12~10_combout  = ( \A_SPW_TOP|tx_data|rd_ptr [5] & ( \A_SPW_TOP|tx_data|mem[1][5]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [3] & ((\A_SPW_TOP|tx_data|mem[33][5]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [3] & (\A_SPW_TOP|tx_data|mem[41][5]~q )) ) 
// ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [5] & ( \A_SPW_TOP|tx_data|mem[1][5]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [3]) # (\A_SPW_TOP|tx_data|mem[9][5]~q ) ) ) ) # ( \A_SPW_TOP|tx_data|rd_ptr [5] & ( !\A_SPW_TOP|tx_data|mem[1][5]~q  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [3] & ((\A_SPW_TOP|tx_data|mem[33][5]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [3] & (\A_SPW_TOP|tx_data|mem[41][5]~q )) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [5] & ( !\A_SPW_TOP|tx_data|mem[1][5]~q  & ( 
// (\A_SPW_TOP|tx_data|mem[9][5]~q  & \A_SPW_TOP|tx_data|rd_ptr [3]) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[41][5]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[9][5]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[33][5]~q ),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [3]),
        .datae(!\A_SPW_TOP|tx_data|rd_ptr [5]),
        .dataf(!\A_SPW_TOP|tx_data|mem[1][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux12~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux12~10 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux12~10 .lut_mask = 64'h00330F55FF330F55;
defparam \A_SPW_TOP|tx_data|Mux12~10 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y14_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux12~14 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux12~14_combout  = ( \A_SPW_TOP|tx_data|rd_ptr [1] & ( \A_SPW_TOP|tx_data|Mux12~10_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & ((\A_SPW_TOP|tx_data|Mux12~12_combout ))) # (\A_SPW_TOP|tx_data|rd_ptr [2] & 
// (\A_SPW_TOP|tx_data|Mux12~13_combout )) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [1] & ( \A_SPW_TOP|tx_data|Mux12~10_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [2]) # (\A_SPW_TOP|tx_data|Mux12~11_combout ) ) ) ) # ( \A_SPW_TOP|tx_data|rd_ptr [1] & ( 
// !\A_SPW_TOP|tx_data|Mux12~10_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & ((\A_SPW_TOP|tx_data|Mux12~12_combout ))) # (\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|Mux12~13_combout )) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [1] & ( 
// !\A_SPW_TOP|tx_data|Mux12~10_combout  & ( (\A_SPW_TOP|tx_data|rd_ptr [2] & \A_SPW_TOP|tx_data|Mux12~11_combout ) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .datab(!\A_SPW_TOP|tx_data|Mux12~13_combout ),
        .datac(!\A_SPW_TOP|tx_data|Mux12~11_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux12~12_combout ),
        .datae(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .dataf(!\A_SPW_TOP|tx_data|Mux12~10_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux12~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux12~14 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux12~14 .lut_mask = 64'h050511BBAFAF11BB;
defparam \A_SPW_TOP|tx_data|Mux12~14 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y14_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux12~2 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux12~2_combout  = ( \A_SPW_TOP|tx_data|mem[10][5]~q  & ( \A_SPW_TOP|tx_data|rd_ptr [5] & ( (!\A_SPW_TOP|tx_data|rd_ptr [3] & (\A_SPW_TOP|tx_data|mem[34][5]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [3] & ((\A_SPW_TOP|tx_data|mem[42][5]~q ))) ) 
// ) ) # ( !\A_SPW_TOP|tx_data|mem[10][5]~q  & ( \A_SPW_TOP|tx_data|rd_ptr [5] & ( (!\A_SPW_TOP|tx_data|rd_ptr [3] & (\A_SPW_TOP|tx_data|mem[34][5]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [3] & ((\A_SPW_TOP|tx_data|mem[42][5]~q ))) ) ) ) # ( 
// \A_SPW_TOP|tx_data|mem[10][5]~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [5] & ( (\A_SPW_TOP|tx_data|rd_ptr [3]) # (\A_SPW_TOP|tx_data|mem[2][5]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[10][5]~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [5] & ( (\A_SPW_TOP|tx_data|mem[2][5]~q  
// & !\A_SPW_TOP|tx_data|rd_ptr [3]) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[2][5]~q ),
        .datab(!\A_SPW_TOP|tx_data|rd_ptr [3]),
        .datac(!\A_SPW_TOP|tx_data|mem[34][5]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[42][5]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[10][5]~q ),
        .dataf(!\A_SPW_TOP|tx_data|rd_ptr [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux12~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux12~2 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux12~2 .lut_mask = 64'h444477770C3F0C3F;
defparam \A_SPW_TOP|tx_data|Mux12~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y14_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux12~3 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux12~3_combout  = ( \A_SPW_TOP|tx_data|mem[14][5]~q  & ( \A_SPW_TOP|tx_data|mem[46][5]~q  & ( ((!\A_SPW_TOP|tx_data|rd_ptr [5] & ((\A_SPW_TOP|tx_data|mem[6][5]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|mem[38][5]~q 
// ))) # (\A_SPW_TOP|tx_data|rd_ptr [3]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[14][5]~q  & ( \A_SPW_TOP|tx_data|mem[46][5]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [3] & ((!\A_SPW_TOP|tx_data|rd_ptr [5] & ((\A_SPW_TOP|tx_data|mem[6][5]~q ))) # 
// (\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|mem[38][5]~q )))) # (\A_SPW_TOP|tx_data|rd_ptr [3] & (((\A_SPW_TOP|tx_data|rd_ptr [5])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[14][5]~q  & ( !\A_SPW_TOP|tx_data|mem[46][5]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr 
// [3] & ((!\A_SPW_TOP|tx_data|rd_ptr [5] & ((\A_SPW_TOP|tx_data|mem[6][5]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|mem[38][5]~q )))) # (\A_SPW_TOP|tx_data|rd_ptr [3] & (((!\A_SPW_TOP|tx_data|rd_ptr [5])))) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|mem[14][5]~q  & ( !\A_SPW_TOP|tx_data|mem[46][5]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [3] & ((!\A_SPW_TOP|tx_data|rd_ptr [5] & ((\A_SPW_TOP|tx_data|mem[6][5]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|mem[38][5]~q )))) 
// ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[38][5]~q ),
        .datab(!\A_SPW_TOP|tx_data|rd_ptr [3]),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [5]),
        .datad(!\A_SPW_TOP|tx_data|mem[6][5]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[14][5]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[46][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux12~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux12~3 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux12~3 .lut_mask = 64'h04C434F407C737F7;
defparam \A_SPW_TOP|tx_data|Mux12~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y14_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux12~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux12~1_combout  = ( \A_SPW_TOP|tx_data|mem[12][5]~q  & ( \A_SPW_TOP|tx_data|rd_ptr [3] & ( (!\A_SPW_TOP|tx_data|rd_ptr [5]) # (\A_SPW_TOP|tx_data|mem[44][5]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[12][5]~q  & ( \A_SPW_TOP|tx_data|rd_ptr 
// [3] & ( (\A_SPW_TOP|tx_data|rd_ptr [5] & \A_SPW_TOP|tx_data|mem[44][5]~q ) ) ) ) # ( \A_SPW_TOP|tx_data|mem[12][5]~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [3] & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|mem[4][5]~q )) # (\A_SPW_TOP|tx_data|rd_ptr 
// [5] & ((\A_SPW_TOP|tx_data|mem[36][5]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[12][5]~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [3] & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|mem[4][5]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [5] & 
// ((\A_SPW_TOP|tx_data|mem[36][5]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [5]),
        .datab(!\A_SPW_TOP|tx_data|mem[4][5]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[36][5]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[44][5]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[12][5]~q ),
        .dataf(!\A_SPW_TOP|tx_data|rd_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux12~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux12~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux12~1 .lut_mask = 64'h272727270055AAFF;
defparam \A_SPW_TOP|tx_data|Mux12~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y14_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux12~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux12~0_combout  = ( \A_SPW_TOP|tx_data|mem[8][5]~q  & ( \A_SPW_TOP|tx_data|rd_ptr [5] & ( (!\A_SPW_TOP|tx_data|rd_ptr [3] & ((\A_SPW_TOP|tx_data|mem[32][5]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [3] & (\A_SPW_TOP|tx_data|mem[40][5]~q )) ) 
// ) ) # ( !\A_SPW_TOP|tx_data|mem[8][5]~q  & ( \A_SPW_TOP|tx_data|rd_ptr [5] & ( (!\A_SPW_TOP|tx_data|rd_ptr [3] & ((\A_SPW_TOP|tx_data|mem[32][5]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [3] & (\A_SPW_TOP|tx_data|mem[40][5]~q )) ) ) ) # ( 
// \A_SPW_TOP|tx_data|mem[8][5]~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [5] & ( (\A_SPW_TOP|tx_data|rd_ptr [3]) # (\A_SPW_TOP|tx_data|mem[0][5]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[8][5]~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [5] & ( (\A_SPW_TOP|tx_data|mem[0][5]~q  & 
// !\A_SPW_TOP|tx_data|rd_ptr [3]) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[40][5]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[32][5]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[0][5]~q ),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [3]),
        .datae(!\A_SPW_TOP|tx_data|mem[8][5]~q ),
        .dataf(!\A_SPW_TOP|tx_data|rd_ptr [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux12~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux12~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux12~0 .lut_mask = 64'h0F000FFF33553355;
defparam \A_SPW_TOP|tx_data|Mux12~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y14_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux12~4 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux12~4_combout  = ( \A_SPW_TOP|tx_data|Mux12~1_combout  & ( \A_SPW_TOP|tx_data|Mux12~0_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [1]) # ((!\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|Mux12~2_combout )) # 
// (\A_SPW_TOP|tx_data|rd_ptr [2] & ((\A_SPW_TOP|tx_data|Mux12~3_combout )))) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux12~1_combout  & ( \A_SPW_TOP|tx_data|Mux12~0_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [1] & (((!\A_SPW_TOP|tx_data|rd_ptr [2])))) # 
// (\A_SPW_TOP|tx_data|rd_ptr [1] & ((!\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|Mux12~2_combout )) # (\A_SPW_TOP|tx_data|rd_ptr [2] & ((\A_SPW_TOP|tx_data|Mux12~3_combout ))))) ) ) ) # ( \A_SPW_TOP|tx_data|Mux12~1_combout  & ( 
// !\A_SPW_TOP|tx_data|Mux12~0_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [1] & (((\A_SPW_TOP|tx_data|rd_ptr [2])))) # (\A_SPW_TOP|tx_data|rd_ptr [1] & ((!\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|Mux12~2_combout )) # (\A_SPW_TOP|tx_data|rd_ptr [2] & 
// ((\A_SPW_TOP|tx_data|Mux12~3_combout ))))) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux12~1_combout  & ( !\A_SPW_TOP|tx_data|Mux12~0_combout  & ( (\A_SPW_TOP|tx_data|rd_ptr [1] & ((!\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|Mux12~2_combout )) # 
// (\A_SPW_TOP|tx_data|rd_ptr [2] & ((\A_SPW_TOP|tx_data|Mux12~3_combout ))))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux12~2_combout ),
        .datab(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .datac(!\A_SPW_TOP|tx_data|Mux12~3_combout ),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .datae(!\A_SPW_TOP|tx_data|Mux12~1_combout ),
        .dataf(!\A_SPW_TOP|tx_data|Mux12~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux12~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux12~4 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux12~4 .lut_mask = 64'h110311CFDD03DDCF;
defparam \A_SPW_TOP|tx_data|Mux12~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y14_N21
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux12~20 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux12~20_combout  = ( \A_SPW_TOP|tx_data|rd_ptr [0] & ( \A_SPW_TOP|tx_data|Mux12~4_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & ((\A_SPW_TOP|tx_data|Mux12~14_combout ))) # (\A_SPW_TOP|tx_data|rd_ptr [4] & 
// (\A_SPW_TOP|tx_data|Mux12~19_combout )) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [0] & ( \A_SPW_TOP|tx_data|Mux12~4_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4]) # (\A_SPW_TOP|tx_data|Mux12~9_combout ) ) ) ) # ( \A_SPW_TOP|tx_data|rd_ptr [0] & ( 
// !\A_SPW_TOP|tx_data|Mux12~4_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & ((\A_SPW_TOP|tx_data|Mux12~14_combout ))) # (\A_SPW_TOP|tx_data|rd_ptr [4] & (\A_SPW_TOP|tx_data|Mux12~19_combout )) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [0] & ( 
// !\A_SPW_TOP|tx_data|Mux12~4_combout  & ( (\A_SPW_TOP|tx_data|Mux12~9_combout  & \A_SPW_TOP|tx_data|rd_ptr [4]) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux12~9_combout ),
        .datab(!\A_SPW_TOP|tx_data|Mux12~19_combout ),
        .datac(!\A_SPW_TOP|tx_data|Mux12~14_combout ),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .datae(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .dataf(!\A_SPW_TOP|tx_data|Mux12~4_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux12~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux12~20 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux12~20 .lut_mask = 64'h00550F33FF550F33;
defparam \A_SPW_TOP|tx_data|Mux12~20 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y11_N53
dffeas \A_SPW_TOP|tx_data|data_out[5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Mux12~20_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|data_out [5]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|data_out[5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|data_out[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X53_Y7_N21
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector35~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector35~0_combout  = ( \A_SPW_TOP|SPW|TX|tx_data_in_0 [5] & ( (!\A_SPW_TOP|SPW|TX|Selector40~0_combout ) # ((\A_SPW_TOP|SPW|TX|Selector32~0_combout  & \A_SPW_TOP|tx_data|data_out [5])) ) ) # ( !\A_SPW_TOP|SPW|TX|tx_data_in_0 [5] & ( 
// (\A_SPW_TOP|SPW|TX|Selector32~0_combout  & \A_SPW_TOP|tx_data|data_out [5]) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|Selector40~0_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|Selector32~0_combout ),
        .datac(!\A_SPW_TOP|tx_data|data_out [5]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|tx_data_in_0 [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector35~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector35~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector35~0 .lut_mask = 64'h03030303ABABABAB;
defparam \A_SPW_TOP|SPW|TX|Selector35~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X54_Y7_N35
dffeas \A_SPW_TOP|SPW|TX|tx_data_in_0[5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|Selector35~0_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|tx_data_in_0 [5]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_data_in_0[5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|tx_data_in_0[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X53_Y7_N48
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout~17 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout~17_combout  = ( !\A_SPW_TOP|SPW|TX|tx_data_in_0 [8] & ( \A_SPW_TOP|SPW|TX|tx_data_in_0 [5] & ( (\A_SPW_TOP|SPW|TX|tx_dout~38_combout  & ((\A_SPW_TOP|SPW|TX|global_counter_transfer [0]) # (\A_SPW_TOP|SPW|TX|tx_data_in_0 [6]))) ) ) 
// ) # ( !\A_SPW_TOP|SPW|TX|tx_data_in_0 [8] & ( !\A_SPW_TOP|SPW|TX|tx_data_in_0 [5] & ( (\A_SPW_TOP|SPW|TX|tx_dout~38_combout  & (!\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & ((\A_SPW_TOP|SPW|TX|global_counter_transfer [0]) # 
// (\A_SPW_TOP|SPW|TX|tx_data_in_0 [6])))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|tx_dout~38_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|tx_data_in_0 [6]),
        .datac(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
        .datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
        .datae(!\A_SPW_TOP|SPW|TX|tx_data_in_0 [8]),
        .dataf(!\A_SPW_TOP|SPW|TX|tx_data_in_0 [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|tx_dout~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout~17 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout~17 .lut_mask = 64'h1050000011550000;
defparam \A_SPW_TOP|SPW|TX|tx_dout~17 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y17_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_payload~4 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_payload~4_combout  = ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_WDATA [4] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_WDATA [4]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_010|src_payload~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_payload~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_payload~4 .lut_mask = 64'h0000000000FF00FF;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_payload~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y17_N40
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_010|src_payload~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y15_N24
cyclonev_lcell_comb \u0|write_data_fifo_tx|data_out[4]~feeder (
// Equation(s):
// \u0|write_data_fifo_tx|data_out[4]~feeder_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [4] )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|write_data_fifo_tx|data_out[4]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|write_data_fifo_tx|data_out[4]~feeder .extended_lut = "off";
defparam \u0|write_data_fifo_tx|data_out[4]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|write_data_fifo_tx|data_out[4]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y15_N26
dffeas \u0|write_data_fifo_tx|data_out[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|write_data_fifo_tx|data_out[4]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|write_data_fifo_tx|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|write_data_fifo_tx|data_out [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|write_data_fifo_tx|data_out[4] .is_wysiwyg = "true";
defparam \u0|write_data_fifo_tx|data_out[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y10_N51
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector306~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector306~0_combout  = ( \A_SPW_TOP|tx_data|mem[33][4]~q  & ( (!\A_SPW_TOP|tx_data|Selector302~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux4~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [4]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[33][4]~q  & ( (\A_SPW_TOP|tx_data|Selector302~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux4~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [4])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [4]),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector302~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[33][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector306~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector306~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector306~0 .lut_mask = 64'h010D010DF1FDF1FD;
defparam \A_SPW_TOP|tx_data|Selector306~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y10_N20
dffeas \A_SPW_TOP|tx_data|mem[33][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector306~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[33][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[33][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[33][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y10_N45
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector315~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector315~0_combout  = ( \A_SPW_TOP|tx_data|mem[34][4]~q  & ( (!\A_SPW_TOP|tx_data|Selector311~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux4~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [4])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[34][4]~q  & ( (\A_SPW_TOP|tx_data|Selector311~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux4~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [4]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector311~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [4]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[34][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector315~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector315~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector315~0 .lut_mask = 64'h02070207F2F7F2F7;
defparam \A_SPW_TOP|tx_data|Selector315~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y10_N41
dffeas \A_SPW_TOP|tx_data|mem[34][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector315~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[34][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[34][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[34][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y10_N21
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector324~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector324~0_combout  = ( \A_SPW_TOP|tx_data|Selector320~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux4~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\u0|write_data_fifo_tx|data_out [4])) ) ) # ( !\A_SPW_TOP|tx_data|Selector320~0_combout  & ( \A_SPW_TOP|tx_data|mem[35][4]~q  ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [4]),
        .datab(!\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[35][4]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector320~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector324~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector324~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector324~0 .lut_mask = 64'h00FF00FF35353535;
defparam \A_SPW_TOP|tx_data|Selector324~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y10_N29
dffeas \A_SPW_TOP|tx_data|mem[35][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector324~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[35][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[35][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[35][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y10_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector297~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector297~0_combout  = ( \A_SPW_TOP|tx_data|mem[32][4]~q  & ( (!\A_SPW_TOP|tx_data|Selector293~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux4~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [4]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[32][4]~q  & ( (\A_SPW_TOP|tx_data|Selector293~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux4~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [4])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [4]),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector293~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[32][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector297~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector297~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector297~0 .lut_mask = 64'h010D010DF1FDF1FD;
defparam \A_SPW_TOP|tx_data|Selector297~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y10_N26
dffeas \A_SPW_TOP|tx_data|mem[32][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector297~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[32][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[32][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[32][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y10_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux4~2 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux4~2_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [0] & ( \A_SPW_TOP|tx_data|wr_ptr [1] & ( \A_SPW_TOP|tx_data|mem[35][4]~q  ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [0] & ( \A_SPW_TOP|tx_data|wr_ptr [1] & ( \A_SPW_TOP|tx_data|mem[34][4]~q  ) ) 
// ) # ( \A_SPW_TOP|tx_data|wr_ptr [0] & ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( \A_SPW_TOP|tx_data|mem[33][4]~q  ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [0] & ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( \A_SPW_TOP|tx_data|mem[32][4]~q  ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[33][4]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[34][4]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[35][4]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[32][4]~q ),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux4~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux4~2 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux4~2 .lut_mask = 64'h00FF555533330F0F;
defparam \A_SPW_TOP|tx_data|Mux4~2 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y11_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector90~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector90~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector86~0_combout  & ((\A_SPW_TOP|tx_data|mem[9][4]~q ))) # (\A_SPW_TOP|tx_data|Selector86~0_combout  & (\u0|write_data_fifo_tx|data_out 
// [4])) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector86~0_combout  & ((\A_SPW_TOP|tx_data|mem[9][4]~q ))) # (\A_SPW_TOP|tx_data|Selector86~0_combout  & (\A_SPW_TOP|tx_data|Mux4~20_combout )) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [4]),
        .datac(!\A_SPW_TOP|tx_data|Selector86~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|mem[9][4]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector90~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector90~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector90~0 .lut_mask = 64'h05F505F503F303F3;
defparam \A_SPW_TOP|tx_data|Selector90~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y11_N47
dffeas \A_SPW_TOP|tx_data|mem[9][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector90~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[9][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[9][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[9][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y11_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector81~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector81~0_combout  = ( \A_SPW_TOP|tx_data|mem[8][4]~q  & ( (!\A_SPW_TOP|tx_data|Selector77~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux4~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [4])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[8][4]~q  & ( (\A_SPW_TOP|tx_data|Selector77~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux4~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [4]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector77~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [4]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[8][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector81~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector81~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector81~0 .lut_mask = 64'h02070207F2F7F2F7;
defparam \A_SPW_TOP|tx_data|Selector81~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y11_N11
dffeas \A_SPW_TOP|tx_data|mem[8][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector81~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[8][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[8][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[8][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y11_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector108~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector108~0_combout  = ( \A_SPW_TOP|tx_data|mem[11][4]~q  & ( (!\A_SPW_TOP|tx_data|Selector104~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux4~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [4])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[11][4]~q  & ( (\A_SPW_TOP|tx_data|Selector104~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux4~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [4]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .datac(!\u0|write_data_fifo_tx|data_out [4]),
        .datad(!\A_SPW_TOP|tx_data|Selector104~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[11][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector108~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector108~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector108~0 .lut_mask = 64'h00270027FF27FF27;
defparam \A_SPW_TOP|tx_data|Selector108~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y11_N32
dffeas \A_SPW_TOP|tx_data|mem[11][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector108~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[11][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[11][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[11][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y11_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector99~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector99~0_combout  = ( \A_SPW_TOP|tx_data|Selector95~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux4~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out 
// [4]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector95~0_combout  & ( \A_SPW_TOP|tx_data|mem[10][4]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|mem[10][4]~q ),
        .datad(!\u0|write_data_fifo_tx|data_out [4]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector95~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector99~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector99~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector99~0 .lut_mask = 64'h0F0F0F0F22772277;
defparam \A_SPW_TOP|tx_data|Selector99~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y11_N53
dffeas \A_SPW_TOP|tx_data|mem[10][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector99~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[10][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[10][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[10][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y11_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux4~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux4~1_combout  = ( \A_SPW_TOP|tx_data|mem[11][4]~q  & ( \A_SPW_TOP|tx_data|mem[10][4]~q  & ( ((!\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|mem[8][4]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|mem[9][4]~q ))) 
// # (\A_SPW_TOP|tx_data|wr_ptr [1]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[11][4]~q  & ( \A_SPW_TOP|tx_data|mem[10][4]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [1] & ((!\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|mem[8][4]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr 
// [0] & (\A_SPW_TOP|tx_data|mem[9][4]~q )))) # (\A_SPW_TOP|tx_data|wr_ptr [1] & (((!\A_SPW_TOP|tx_data|wr_ptr [0])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[11][4]~q  & ( !\A_SPW_TOP|tx_data|mem[10][4]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [1] & 
// ((!\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|mem[8][4]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|mem[9][4]~q )))) # (\A_SPW_TOP|tx_data|wr_ptr [1] & (((\A_SPW_TOP|tx_data|wr_ptr [0])))) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|mem[11][4]~q  & ( !\A_SPW_TOP|tx_data|mem[10][4]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [1] & ((!\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|mem[8][4]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|mem[9][4]~q )))) ) 
// ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[9][4]~q ),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datad(!\A_SPW_TOP|tx_data|mem[8][4]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[11][4]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[10][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux4~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux4~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux4~1 .lut_mask = 64'h04C407C734F437F7;
defparam \A_SPW_TOP|tx_data|Mux4~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y11_N21
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector27~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector27~0_combout  = ( \A_SPW_TOP|tx_data|mem[2][4]~q  & ( (!\A_SPW_TOP|tx_data|Selector23~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux4~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [4]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[2][4]~q  & ( (\A_SPW_TOP|tx_data|Selector23~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux4~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [4])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [4]),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .datad(!\A_SPW_TOP|tx_data|Selector23~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[2][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector27~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector27~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector27~0 .lut_mask = 64'h001D001DFF1DFF1D;
defparam \A_SPW_TOP|tx_data|Selector27~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y11_N53
dffeas \A_SPW_TOP|tx_data|mem[2][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector27~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[2][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[2][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[2][4] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y11_N39
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector18~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector18~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector14~0_combout  & ((\A_SPW_TOP|tx_data|mem[1][4]~q ))) # (\A_SPW_TOP|tx_data|Selector14~0_combout  & (\u0|write_data_fifo_tx|data_out 
// [4])) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector14~0_combout  & ((\A_SPW_TOP|tx_data|mem[1][4]~q ))) # (\A_SPW_TOP|tx_data|Selector14~0_combout  & (\A_SPW_TOP|tx_data|Mux4~20_combout )) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [4]),
        .datac(!\A_SPW_TOP|tx_data|mem[1][4]~q ),
        .datad(!\A_SPW_TOP|tx_data|Selector14~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector18~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector18~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector18~0 .lut_mask = 64'h0F550F550F330F33;
defparam \A_SPW_TOP|tx_data|Selector18~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y11_N9
cyclonev_lcell_comb \A_SPW_TOP|tx_data|mem[1][4]~feeder (
// Equation(s):
// \A_SPW_TOP|tx_data|mem[1][4]~feeder_combout  = ( \A_SPW_TOP|tx_data|Selector18~0_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector18~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|mem[1][4]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[1][4]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|mem[1][4]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|tx_data|mem[1][4]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y11_N11
dffeas \A_SPW_TOP|tx_data|mem[1][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|tx_data|mem[1][4]~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[1][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[1][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[1][4] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y11_N27
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector36~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector36~0_combout  = ( \A_SPW_TOP|tx_data|Selector32~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux4~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\u0|write_data_fifo_tx|data_out [4])) ) ) # ( !\A_SPW_TOP|tx_data|Selector32~0_combout  & ( \A_SPW_TOP|tx_data|mem[3][4]~q  ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [4]),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[3][4]~q ),
        .datad(!\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector32~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector36~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector36~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector36~0 .lut_mask = 64'h0F0F0F0F11DD11DD;
defparam \A_SPW_TOP|tx_data|Selector36~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y11_N44
dffeas \A_SPW_TOP|tx_data|mem[3][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector36~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[3][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[3][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[3][4] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y11_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux4~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux4~0_combout  = ( \A_SPW_TOP|tx_data|mem[3][4]~q  & ( \A_SPW_TOP|tx_data|wr_ptr [0] & ( (\A_SPW_TOP|tx_data|mem[1][4]~q ) # (\A_SPW_TOP|tx_data|wr_ptr [1]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[3][4]~q  & ( \A_SPW_TOP|tx_data|wr_ptr [0] & 
// ( (!\A_SPW_TOP|tx_data|wr_ptr [1] & \A_SPW_TOP|tx_data|mem[1][4]~q ) ) ) ) # ( \A_SPW_TOP|tx_data|mem[3][4]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [0] & ( (!\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|mem[0][4]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [1] & 
// ((\A_SPW_TOP|tx_data|mem[2][4]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[3][4]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [0] & ( (!\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|mem[0][4]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [1] & ((\A_SPW_TOP|tx_data|mem[2][4]~q 
// ))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[0][4]~q ),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datac(!\A_SPW_TOP|tx_data|mem[2][4]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[1][4]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[3][4]~q ),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux4~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux4~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux4~0 .lut_mask = 64'h4747474700CC33FF;
defparam \A_SPW_TOP|tx_data|Mux4~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y11_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector387~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector387~0_combout  = ( \A_SPW_TOP|tx_data|Selector383~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux4~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\u0|write_data_fifo_tx|data_out [4])) ) ) # ( !\A_SPW_TOP|tx_data|Selector383~0_combout  & ( \A_SPW_TOP|tx_data|mem[42][4]~q  ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [4]),
        .datab(!\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|mem[42][4]~q ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector383~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector387~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector387~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector387~0 .lut_mask = 64'h0F0F0F0F33553355;
defparam \A_SPW_TOP|tx_data|Selector387~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y11_N29
dffeas \A_SPW_TOP|tx_data|mem[42][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector387~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[42][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[42][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[42][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y11_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector369~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector369~0_combout  = ( \A_SPW_TOP|tx_data|mem[40][4]~q  & ( (!\A_SPW_TOP|tx_data|Selector365~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux4~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [4]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[40][4]~q  & ( (\A_SPW_TOP|tx_data|Selector365~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux4~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [4])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [4]),
        .datab(!\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector365~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[40][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector369~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector369~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector369~0 .lut_mask = 64'h03050305F3F5F3F5;
defparam \A_SPW_TOP|tx_data|Selector369~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y11_N11
dffeas \A_SPW_TOP|tx_data|mem[40][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector369~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[40][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[40][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[40][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y11_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector378~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector378~0_combout  = ( \A_SPW_TOP|tx_data|mem[41][4]~q  & ( (!\A_SPW_TOP|tx_data|Selector374~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux4~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [4]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[41][4]~q  & ( (\A_SPW_TOP|tx_data|Selector374~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux4~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [4])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [4]),
        .datab(!\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector374~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[41][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector378~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector378~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector378~0 .lut_mask = 64'h03050305F3F5F3F5;
defparam \A_SPW_TOP|tx_data|Selector378~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y11_N32
dffeas \A_SPW_TOP|tx_data|mem[41][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector378~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[41][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[41][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[41][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y11_N39
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector396~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector396~0_combout  = ( \A_SPW_TOP|tx_data|mem[43][4]~q  & ( (!\A_SPW_TOP|tx_data|Selector392~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux4~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [4]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[43][4]~q  & ( (\A_SPW_TOP|tx_data|Selector392~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux4~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [4])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [4]),
        .datab(!\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|tx_data|Selector392~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[43][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector396~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector396~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector396~0 .lut_mask = 64'h00350035FF35FF35;
defparam \A_SPW_TOP|tx_data|Selector396~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y11_N50
dffeas \A_SPW_TOP|tx_data|mem[43][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector396~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[43][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[43][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[43][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y11_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux4~3 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux4~3_combout  = ( \A_SPW_TOP|tx_data|mem[41][4]~q  & ( \A_SPW_TOP|tx_data|mem[43][4]~q  & ( ((!\A_SPW_TOP|tx_data|wr_ptr [1] & ((\A_SPW_TOP|tx_data|mem[40][4]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|mem[42][4]~q 
// ))) # (\A_SPW_TOP|tx_data|wr_ptr [0]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[41][4]~q  & ( \A_SPW_TOP|tx_data|mem[43][4]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [1] & (((\A_SPW_TOP|tx_data|mem[40][4]~q  & !\A_SPW_TOP|tx_data|wr_ptr [0])))) # 
// (\A_SPW_TOP|tx_data|wr_ptr [1] & (((\A_SPW_TOP|tx_data|wr_ptr [0])) # (\A_SPW_TOP|tx_data|mem[42][4]~q ))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[41][4]~q  & ( !\A_SPW_TOP|tx_data|mem[43][4]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [1] & (((\A_SPW_TOP|tx_data|wr_ptr 
// [0]) # (\A_SPW_TOP|tx_data|mem[40][4]~q )))) # (\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|mem[42][4]~q  & ((!\A_SPW_TOP|tx_data|wr_ptr [0])))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[41][4]~q  & ( !\A_SPW_TOP|tx_data|mem[43][4]~q  & ( 
// (!\A_SPW_TOP|tx_data|wr_ptr [0] & ((!\A_SPW_TOP|tx_data|wr_ptr [1] & ((\A_SPW_TOP|tx_data|mem[40][4]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|mem[42][4]~q )))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[42][4]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[40][4]~q ),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datae(!\A_SPW_TOP|tx_data|mem[41][4]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[43][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux4~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux4~3 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux4~3 .lut_mask = 64'h350035F0350F35FF;
defparam \A_SPW_TOP|tx_data|Mux4~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y11_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux4~4 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux4~4_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [3] & ( \A_SPW_TOP|tx_data|Mux4~3_combout  & ( (\A_SPW_TOP|tx_data|Mux4~1_combout ) # (\A_SPW_TOP|tx_data|wr_ptr [5]) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [3] & ( 
// \A_SPW_TOP|tx_data|Mux4~3_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [5] & ((\A_SPW_TOP|tx_data|Mux4~0_combout ))) # (\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|Mux4~2_combout )) ) ) ) # ( \A_SPW_TOP|tx_data|wr_ptr [3] & ( 
// !\A_SPW_TOP|tx_data|Mux4~3_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [5] & \A_SPW_TOP|tx_data|Mux4~1_combout ) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [3] & ( !\A_SPW_TOP|tx_data|Mux4~3_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [5] & 
// ((\A_SPW_TOP|tx_data|Mux4~0_combout ))) # (\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|Mux4~2_combout )) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datab(!\A_SPW_TOP|tx_data|Mux4~2_combout ),
        .datac(!\A_SPW_TOP|tx_data|Mux4~1_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux4~0_combout ),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .dataf(!\A_SPW_TOP|tx_data|Mux4~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux4~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux4~4 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux4~4 .lut_mask = 64'h11BB0A0A11BB5F5F;
defparam \A_SPW_TOP|tx_data|Mux4~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y9_N57
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector360~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector360~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector356~0_combout  & ((\A_SPW_TOP|tx_data|mem[39][4]~q ))) # (\A_SPW_TOP|tx_data|Selector356~0_combout  & (\u0|write_data_fifo_tx|data_out 
// [4])) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector356~0_combout  & ((\A_SPW_TOP|tx_data|mem[39][4]~q ))) # (\A_SPW_TOP|tx_data|Selector356~0_combout  & (\A_SPW_TOP|tx_data|Mux4~20_combout )) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [4]),
        .datab(!\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector356~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|mem[39][4]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector360~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector360~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector360~0 .lut_mask = 64'h03F303F305F505F5;
defparam \A_SPW_TOP|tx_data|Selector360~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y9_N23
dffeas \A_SPW_TOP|tx_data|mem[39][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector360~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[39][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[39][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[39][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y9_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector351~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector351~0_combout  = ( \A_SPW_TOP|tx_data|mem[38][4]~q  & ( (!\A_SPW_TOP|tx_data|Selector347~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux4~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [4]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[38][4]~q  & ( (\A_SPW_TOP|tx_data|Selector347~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux4~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [4])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [4]),
        .datab(!\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|tx_data|Selector347~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[38][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector351~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector351~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector351~0 .lut_mask = 64'h00350035FF35FF35;
defparam \A_SPW_TOP|tx_data|Selector351~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y9_N53
dffeas \A_SPW_TOP|tx_data|mem[38][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector351~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[38][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[38][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[38][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y9_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector333~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector333~0_combout  = ( \A_SPW_TOP|tx_data|Selector329~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux4~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [4]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector329~0_combout  & ( \A_SPW_TOP|tx_data|mem[36][4]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [4]),
        .datac(!\A_SPW_TOP|tx_data|mem[36][4]~q ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector329~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector333~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector333~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector333~0 .lut_mask = 64'h0F0F0F0F55335533;
defparam \A_SPW_TOP|tx_data|Selector333~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y9_N5
dffeas \A_SPW_TOP|tx_data|mem[36][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector333~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[36][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[36][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[36][4] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y9_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector342~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector342~0_combout  = ( \A_SPW_TOP|tx_data|mem[37][4]~q  & ( (!\A_SPW_TOP|tx_data|Selector338~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux4~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [4]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[37][4]~q  & ( (\A_SPW_TOP|tx_data|Selector338~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux4~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [4])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [4]),
        .datab(!\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector338~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[37][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector342~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector342~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector342~0 .lut_mask = 64'h03050305F3F5F3F5;
defparam \A_SPW_TOP|tx_data|Selector342~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y9_N41
dffeas \A_SPW_TOP|tx_data|mem[37][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector342~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[37][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[37][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[37][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y9_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux4~12 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux4~12_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [1] & ( \A_SPW_TOP|tx_data|mem[37][4]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|mem[38][4]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|mem[39][4]~q )) ) 
// ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( \A_SPW_TOP|tx_data|mem[37][4]~q  & ( (\A_SPW_TOP|tx_data|mem[36][4]~q ) # (\A_SPW_TOP|tx_data|wr_ptr [0]) ) ) ) # ( \A_SPW_TOP|tx_data|wr_ptr [1] & ( !\A_SPW_TOP|tx_data|mem[37][4]~q  & ( 
// (!\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|mem[38][4]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|mem[39][4]~q )) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( !\A_SPW_TOP|tx_data|mem[37][4]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr 
// [0] & \A_SPW_TOP|tx_data|mem[36][4]~q ) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[39][4]~q ),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datac(!\A_SPW_TOP|tx_data|mem[38][4]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[36][4]~q ),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .dataf(!\A_SPW_TOP|tx_data|mem[37][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux4~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux4~12 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux4~12 .lut_mask = 64'h00CC1D1D33FF1D1D;
defparam \A_SPW_TOP|tx_data|Mux4~12 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y9_N39
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector63~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector63~0_combout  = ( \A_SPW_TOP|tx_data|mem[6][4]~q  & ( (!\A_SPW_TOP|tx_data|Selector59~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux4~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [4]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[6][4]~q  & ( (\A_SPW_TOP|tx_data|Selector59~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux4~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [4])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [4]),
        .datab(!\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector59~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[6][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector63~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector63~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector63~0 .lut_mask = 64'h03050305F3F5F3F5;
defparam \A_SPW_TOP|tx_data|Selector63~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y9_N26
dffeas \A_SPW_TOP|tx_data|mem[6][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector63~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[6][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[6][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[6][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y11_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector45~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector45~0_combout  = ( \A_SPW_TOP|tx_data|Selector41~0_combout  & ( \A_SPW_TOP|tx_data|mem[4][4]~q  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux4~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [4])) ) ) ) # ( !\A_SPW_TOP|tx_data|Selector41~0_combout  & ( \A_SPW_TOP|tx_data|mem[4][4]~q  ) ) # ( \A_SPW_TOP|tx_data|Selector41~0_combout  & ( 
// !\A_SPW_TOP|tx_data|mem[4][4]~q  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux4~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [4])) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(gnd),
        .datac(!\u0|write_data_fifo_tx|data_out [4]),
        .datad(!\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .datae(!\A_SPW_TOP|tx_data|Selector41~0_combout ),
        .dataf(!\A_SPW_TOP|tx_data|mem[4][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector45~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector45~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector45~0 .lut_mask = 64'h000005AFFFFF05AF;
defparam \A_SPW_TOP|tx_data|Selector45~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y11_N17
dffeas \A_SPW_TOP|tx_data|mem[4][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector45~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[4][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[4][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[4][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y9_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector72~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector72~0_combout  = ( \A_SPW_TOP|tx_data|mem[7][4]~q  & ( (!\A_SPW_TOP|tx_data|Selector68~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux4~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [4]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[7][4]~q  & ( (\A_SPW_TOP|tx_data|Selector68~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux4~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [4])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [4]),
        .datab(!\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector68~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[7][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector72~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector72~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector72~0 .lut_mask = 64'h03050305F3F5F3F5;
defparam \A_SPW_TOP|tx_data|Selector72~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y9_N17
dffeas \A_SPW_TOP|tx_data|mem[7][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector72~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[7][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[7][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[7][4] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y9_N57
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector54~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector54~0_combout  = ( \A_SPW_TOP|tx_data|Selector50~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux4~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\u0|write_data_fifo_tx|data_out [4])) ) ) # ( !\A_SPW_TOP|tx_data|Selector50~0_combout  & ( \A_SPW_TOP|tx_data|mem[5][4]~q  ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [4]),
        .datab(!\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|mem[5][4]~q ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector50~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector54~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector54~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector54~0 .lut_mask = 64'h0F0F0F0F33553355;
defparam \A_SPW_TOP|tx_data|Selector54~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y9_N17
dffeas \A_SPW_TOP|tx_data|mem[5][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector54~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[5][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[5][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[5][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y9_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux4~10 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux4~10_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [1] & ( \A_SPW_TOP|tx_data|mem[5][4]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|mem[6][4]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|mem[7][4]~q ))) ) ) 
// ) # ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( \A_SPW_TOP|tx_data|mem[5][4]~q  & ( (\A_SPW_TOP|tx_data|mem[4][4]~q ) # (\A_SPW_TOP|tx_data|wr_ptr [0]) ) ) ) # ( \A_SPW_TOP|tx_data|wr_ptr [1] & ( !\A_SPW_TOP|tx_data|mem[5][4]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr 
// [0] & (\A_SPW_TOP|tx_data|mem[6][4]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|mem[7][4]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( !\A_SPW_TOP|tx_data|mem[5][4]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & 
// \A_SPW_TOP|tx_data|mem[4][4]~q ) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[6][4]~q ),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datac(!\A_SPW_TOP|tx_data|mem[4][4]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[7][4]~q ),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .dataf(!\A_SPW_TOP|tx_data|mem[5][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux4~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux4~10 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux4~10 .lut_mask = 64'h0C0C44773F3F4477;
defparam \A_SPW_TOP|tx_data|Mux4~10 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y9_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector405~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector405~0_combout  = ( \A_SPW_TOP|tx_data|Selector401~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux4~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [4]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector401~0_combout  & ( \A_SPW_TOP|tx_data|mem[44][4]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [4]),
        .datac(!\A_SPW_TOP|tx_data|mem[44][4]~q ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector401~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector405~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector405~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector405~0 .lut_mask = 64'h0F0F0F0F55335533;
defparam \A_SPW_TOP|tx_data|Selector405~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y9_N50
dffeas \A_SPW_TOP|tx_data|mem[44][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector405~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[44][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[44][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[44][4] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y9_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector414~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector414~0_combout  = ( \u0|write_data_fifo_tx|data_out [4] & ( (!\A_SPW_TOP|tx_data|Selector410~0_combout  & (((\A_SPW_TOP|tx_data|mem[45][4]~q )))) # (\A_SPW_TOP|tx_data|Selector410~0_combout  & 
// (((\A_SPW_TOP|tx_data|Mux4~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q ))) ) ) # ( !\u0|write_data_fifo_tx|data_out [4] & ( (!\A_SPW_TOP|tx_data|Selector410~0_combout  & (((\A_SPW_TOP|tx_data|mem[45][4]~q )))) # 
// (\A_SPW_TOP|tx_data|Selector410~0_combout  & (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux4~20_combout ))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|mem[45][4]~q ),
        .datad(!\A_SPW_TOP|tx_data|Selector410~0_combout ),
        .datae(gnd),
        .dataf(!\u0|write_data_fifo_tx|data_out [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector414~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector414~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector414~0 .lut_mask = 64'h0F220F220F770F77;
defparam \A_SPW_TOP|tx_data|Selector414~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y9_N32
dffeas \A_SPW_TOP|tx_data|mem[45][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector414~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[45][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[45][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[45][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y9_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector432~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector432~0_combout  = ( \A_SPW_TOP|tx_data|Selector428~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux4~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [4]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector428~0_combout  & ( \A_SPW_TOP|tx_data|mem[47][4]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|mem[47][4]~q ),
        .datac(!\u0|write_data_fifo_tx|data_out [4]),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(!\A_SPW_TOP|tx_data|Selector428~0_combout ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector432~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector432~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector432~0 .lut_mask = 64'h3333550F3333550F;
defparam \A_SPW_TOP|tx_data|Selector432~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y9_N11
dffeas \A_SPW_TOP|tx_data|mem[47][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector432~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[47][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[47][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[47][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y9_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector423~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector423~0_combout  = ( \A_SPW_TOP|tx_data|Selector419~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux4~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [4]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector419~0_combout  & ( \A_SPW_TOP|tx_data|mem[46][4]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .datac(!\u0|write_data_fifo_tx|data_out [4]),
        .datad(!\A_SPW_TOP|tx_data|mem[46][4]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector419~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector423~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector423~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector423~0 .lut_mask = 64'h00FF00FF27272727;
defparam \A_SPW_TOP|tx_data|Selector423~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y9_N47
dffeas \A_SPW_TOP|tx_data|mem[46][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector423~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[46][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[46][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[46][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y9_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux4~13 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux4~13_combout  = ( \A_SPW_TOP|tx_data|mem[46][4]~q  & ( \A_SPW_TOP|tx_data|wr_ptr [1] & ( (!\A_SPW_TOP|tx_data|wr_ptr [0]) # (\A_SPW_TOP|tx_data|mem[47][4]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[46][4]~q  & ( \A_SPW_TOP|tx_data|wr_ptr 
// [1] & ( (\A_SPW_TOP|tx_data|wr_ptr [0] & \A_SPW_TOP|tx_data|mem[47][4]~q ) ) ) ) # ( \A_SPW_TOP|tx_data|mem[46][4]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|mem[44][4]~q )) # (\A_SPW_TOP|tx_data|wr_ptr 
// [0] & ((\A_SPW_TOP|tx_data|mem[45][4]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[46][4]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|mem[44][4]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [0] & 
// ((\A_SPW_TOP|tx_data|mem[45][4]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[44][4]~q ),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datac(!\A_SPW_TOP|tx_data|mem[45][4]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[47][4]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[46][4]~q ),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux4~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux4~13 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux4~13 .lut_mask = 64'h474747470033CCFF;
defparam \A_SPW_TOP|tx_data|Mux4~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y9_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector144~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector144~0_combout  = ( \A_SPW_TOP|tx_data|mem[15][4]~q  & ( (!\A_SPW_TOP|tx_data|Selector140~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux4~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [4])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[15][4]~q  & ( (\A_SPW_TOP|tx_data|Selector140~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux4~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [4]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector140~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [4]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[15][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector144~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector144~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector144~0 .lut_mask = 64'h02070207F2F7F2F7;
defparam \A_SPW_TOP|tx_data|Selector144~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y9_N35
dffeas \A_SPW_TOP|tx_data|mem[15][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector144~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[15][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[15][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[15][4] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y9_N21
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector117~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector117~0_combout  = ( \A_SPW_TOP|tx_data|mem[12][4]~q  & ( (!\A_SPW_TOP|tx_data|Selector113~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux4~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [4])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[12][4]~q  & ( (\A_SPW_TOP|tx_data|Selector113~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux4~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [4]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector113~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [4]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[12][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector117~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector117~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector117~0 .lut_mask = 64'h02070207F2F7F2F7;
defparam \A_SPW_TOP|tx_data|Selector117~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y9_N29
dffeas \A_SPW_TOP|tx_data|mem[12][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector117~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[12][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[12][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[12][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y10_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector135~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector135~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector131~0_combout  & ((\A_SPW_TOP|tx_data|mem[14][4]~q ))) # (\A_SPW_TOP|tx_data|Selector131~0_combout  & (\u0|write_data_fifo_tx|data_out 
// [4])) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector131~0_combout  & (\A_SPW_TOP|tx_data|mem[14][4]~q )) # (\A_SPW_TOP|tx_data|Selector131~0_combout  & ((\A_SPW_TOP|tx_data|Mux4~20_combout ))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [4]),
        .datab(!\A_SPW_TOP|tx_data|Selector131~0_combout ),
        .datac(!\A_SPW_TOP|tx_data|mem[14][4]~q ),
        .datad(!\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .datae(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector135~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector135~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector135~0 .lut_mask = 64'h0C3F1D1D0C3F1D1D;
defparam \A_SPW_TOP|tx_data|Selector135~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y10_N53
dffeas \A_SPW_TOP|tx_data|mem[14][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector135~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[14][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[14][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[14][4] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y9_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector126~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector126~0_combout  = ( \A_SPW_TOP|tx_data|mem[13][4]~q  & ( (!\A_SPW_TOP|tx_data|Selector122~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux4~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [4])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[13][4]~q  & ( (\A_SPW_TOP|tx_data|Selector122~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux4~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [4]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector122~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [4]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[13][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector126~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector126~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector126~0 .lut_mask = 64'h02070207F2F7F2F7;
defparam \A_SPW_TOP|tx_data|Selector126~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y9_N11
dffeas \A_SPW_TOP|tx_data|mem[13][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector126~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[13][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[13][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[13][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y9_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux4~11 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux4~11_combout  = ( \A_SPW_TOP|tx_data|mem[14][4]~q  & ( \A_SPW_TOP|tx_data|mem[13][4]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [1] & (((\A_SPW_TOP|tx_data|wr_ptr [0]) # (\A_SPW_TOP|tx_data|mem[12][4]~q )))) # (\A_SPW_TOP|tx_data|wr_ptr [1] 
// & (((!\A_SPW_TOP|tx_data|wr_ptr [0])) # (\A_SPW_TOP|tx_data|mem[15][4]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[14][4]~q  & ( \A_SPW_TOP|tx_data|mem[13][4]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [1] & (((\A_SPW_TOP|tx_data|wr_ptr [0]) # 
// (\A_SPW_TOP|tx_data|mem[12][4]~q )))) # (\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|mem[15][4]~q  & ((\A_SPW_TOP|tx_data|wr_ptr [0])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[14][4]~q  & ( !\A_SPW_TOP|tx_data|mem[13][4]~q  & ( 
// (!\A_SPW_TOP|tx_data|wr_ptr [1] & (((\A_SPW_TOP|tx_data|mem[12][4]~q  & !\A_SPW_TOP|tx_data|wr_ptr [0])))) # (\A_SPW_TOP|tx_data|wr_ptr [1] & (((!\A_SPW_TOP|tx_data|wr_ptr [0])) # (\A_SPW_TOP|tx_data|mem[15][4]~q ))) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|mem[14][4]~q  & ( !\A_SPW_TOP|tx_data|mem[13][4]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [1] & (((\A_SPW_TOP|tx_data|mem[12][4]~q  & !\A_SPW_TOP|tx_data|wr_ptr [0])))) # (\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|mem[15][4]~q  & 
// ((\A_SPW_TOP|tx_data|wr_ptr [0])))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[15][4]~q ),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datac(!\A_SPW_TOP|tx_data|mem[12][4]~q ),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datae(!\A_SPW_TOP|tx_data|mem[14][4]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[13][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux4~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux4~11 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux4~11 .lut_mask = 64'h0C113F110CDD3FDD;
defparam \A_SPW_TOP|tx_data|Mux4~11 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y9_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux4~14 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux4~14_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [3] & ( \A_SPW_TOP|tx_data|Mux4~11_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [5]) # (\A_SPW_TOP|tx_data|Mux4~13_combout ) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [3] & ( 
// \A_SPW_TOP|tx_data|Mux4~11_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [5] & ((\A_SPW_TOP|tx_data|Mux4~10_combout ))) # (\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|Mux4~12_combout )) ) ) ) # ( \A_SPW_TOP|tx_data|wr_ptr [3] & ( 
// !\A_SPW_TOP|tx_data|Mux4~11_combout  & ( (\A_SPW_TOP|tx_data|wr_ptr [5] & \A_SPW_TOP|tx_data|Mux4~13_combout ) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [3] & ( !\A_SPW_TOP|tx_data|Mux4~11_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [5] & 
// ((\A_SPW_TOP|tx_data|Mux4~10_combout ))) # (\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|Mux4~12_combout )) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datab(!\A_SPW_TOP|tx_data|Mux4~12_combout ),
        .datac(!\A_SPW_TOP|tx_data|Mux4~10_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux4~13_combout ),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .dataf(!\A_SPW_TOP|tx_data|Mux4~11_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux4~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux4~14 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux4~14 .lut_mask = 64'h1B1B00551B1BAAFF;
defparam \A_SPW_TOP|tx_data|Mux4~14 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y11_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector171~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector171~0_combout  = ( \A_SPW_TOP|tx_data|Selector167~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux4~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\u0|write_data_fifo_tx|data_out [4])) ) ) # ( !\A_SPW_TOP|tx_data|Selector167~0_combout  & ( \A_SPW_TOP|tx_data|mem[18][4]~q  ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [4]),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[18][4]~q ),
        .datad(!\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector167~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector171~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector171~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector171~0 .lut_mask = 64'h0F0F0F0F11DD11DD;
defparam \A_SPW_TOP|tx_data|Selector171~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y11_N2
dffeas \A_SPW_TOP|tx_data|mem[18][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector171~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[18][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[18][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[18][4] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y11_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector162~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector162~0_combout  = ( \A_SPW_TOP|tx_data|mem[17][4]~q  & ( (!\A_SPW_TOP|tx_data|Selector158~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux4~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [4]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[17][4]~q  & ( (\A_SPW_TOP|tx_data|Selector158~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux4~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [4])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [4]),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .datad(!\A_SPW_TOP|tx_data|Selector158~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[17][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector162~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector162~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector162~0 .lut_mask = 64'h001D001DFF1DFF1D;
defparam \A_SPW_TOP|tx_data|Selector162~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y11_N35
dffeas \A_SPW_TOP|tx_data|mem[17][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector162~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[17][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[17][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[17][4] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y11_N15
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector180~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector180~0_combout  = ( \A_SPW_TOP|tx_data|mem[19][4]~q  & ( (!\A_SPW_TOP|tx_data|Selector176~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux4~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [4]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[19][4]~q  & ( (\A_SPW_TOP|tx_data|Selector176~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux4~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [4])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [4]),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector176~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[19][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector180~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector180~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector180~0 .lut_mask = 64'h010D010DF1FDF1FD;
defparam \A_SPW_TOP|tx_data|Selector180~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y11_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|mem[19][4]~feeder (
// Equation(s):
// \A_SPW_TOP|tx_data|mem[19][4]~feeder_combout  = ( \A_SPW_TOP|tx_data|Selector180~0_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector180~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|mem[19][4]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[19][4]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|mem[19][4]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|tx_data|mem[19][4]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y11_N8
dffeas \A_SPW_TOP|tx_data|mem[19][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|tx_data|mem[19][4]~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[19][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[19][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[19][4] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y11_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector153~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector153~0_combout  = ( \A_SPW_TOP|tx_data|Selector149~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux4~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\u0|write_data_fifo_tx|data_out [4])) ) ) # ( !\A_SPW_TOP|tx_data|Selector149~0_combout  & ( \A_SPW_TOP|tx_data|mem[16][4]~q  ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [4]),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .datad(!\A_SPW_TOP|tx_data|mem[16][4]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector149~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector153~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector153~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector153~0 .lut_mask = 64'h00FF00FF1D1D1D1D;
defparam \A_SPW_TOP|tx_data|Selector153~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y11_N59
dffeas \A_SPW_TOP|tx_data|mem[16][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector153~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[16][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[16][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[16][4] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y11_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux4~5 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux4~5_combout  = ( \A_SPW_TOP|tx_data|mem[16][4]~q  & ( \A_SPW_TOP|tx_data|wr_ptr [0] & ( (!\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|mem[17][4]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [1] & ((\A_SPW_TOP|tx_data|mem[19][4]~q ))) ) 
// ) ) # ( !\A_SPW_TOP|tx_data|mem[16][4]~q  & ( \A_SPW_TOP|tx_data|wr_ptr [0] & ( (!\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|mem[17][4]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [1] & ((\A_SPW_TOP|tx_data|mem[19][4]~q ))) ) ) ) # ( 
// \A_SPW_TOP|tx_data|mem[16][4]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [0] & ( (!\A_SPW_TOP|tx_data|wr_ptr [1]) # (\A_SPW_TOP|tx_data|mem[18][4]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[16][4]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [0] & ( 
// (\A_SPW_TOP|tx_data|mem[18][4]~q  & \A_SPW_TOP|tx_data|wr_ptr [1]) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[18][4]~q ),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datac(!\A_SPW_TOP|tx_data|mem[17][4]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[19][4]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[16][4]~q ),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux4~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux4~5 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux4~5 .lut_mask = 64'h1111DDDD0C3F0C3F;
defparam \A_SPW_TOP|tx_data|Mux4~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y11_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector234~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector234~0_combout  = ( \u0|write_data_fifo_tx|data_out [4] & ( (!\A_SPW_TOP|tx_data|Selector230~0_combout  & (((\A_SPW_TOP|tx_data|mem[25][4]~q )))) # (\A_SPW_TOP|tx_data|Selector230~0_combout  & 
// (((\A_SPW_TOP|tx_data|Mux4~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q ))) ) ) # ( !\u0|write_data_fifo_tx|data_out [4] & ( (!\A_SPW_TOP|tx_data|Selector230~0_combout  & (((\A_SPW_TOP|tx_data|mem[25][4]~q )))) # 
// (\A_SPW_TOP|tx_data|Selector230~0_combout  & (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux4~20_combout ))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|mem[25][4]~q ),
        .datad(!\A_SPW_TOP|tx_data|Selector230~0_combout ),
        .datae(gnd),
        .dataf(!\u0|write_data_fifo_tx|data_out [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector234~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector234~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector234~0 .lut_mask = 64'h0F220F220F770F77;
defparam \A_SPW_TOP|tx_data|Selector234~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y11_N50
dffeas \A_SPW_TOP|tx_data|mem[25][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector234~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[25][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[25][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[25][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y11_N45
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector252~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector252~0_combout  = ( \A_SPW_TOP|tx_data|mem[27][4]~q  & ( (!\A_SPW_TOP|tx_data|Selector248~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux4~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [4])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[27][4]~q  & ( (\A_SPW_TOP|tx_data|Selector248~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux4~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [4]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .datac(!\u0|write_data_fifo_tx|data_out [4]),
        .datad(!\A_SPW_TOP|tx_data|Selector248~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[27][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector252~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector252~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector252~0 .lut_mask = 64'h00270027FF27FF27;
defparam \A_SPW_TOP|tx_data|Selector252~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y11_N35
dffeas \A_SPW_TOP|tx_data|mem[27][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector252~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[27][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[27][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[27][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y11_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector243~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector243~0_combout  = ( \A_SPW_TOP|tx_data|mem[26][4]~q  & ( (!\A_SPW_TOP|tx_data|Selector239~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux4~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [4])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[26][4]~q  & ( (\A_SPW_TOP|tx_data|Selector239~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux4~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [4]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector239~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [4]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[26][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector243~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector243~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector243~0 .lut_mask = 64'h02070207F2F7F2F7;
defparam \A_SPW_TOP|tx_data|Selector243~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y11_N17
dffeas \A_SPW_TOP|tx_data|mem[26][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector243~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[26][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[26][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[26][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y11_N39
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector225~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector225~0_combout  = ( \A_SPW_TOP|tx_data|Selector221~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux4~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [4]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector221~0_combout  & ( \A_SPW_TOP|tx_data|mem[24][4]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .datac(!\u0|write_data_fifo_tx|data_out [4]),
        .datad(!\A_SPW_TOP|tx_data|mem[24][4]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector221~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector225~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector225~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector225~0 .lut_mask = 64'h00FF00FF27272727;
defparam \A_SPW_TOP|tx_data|Selector225~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y11_N23
dffeas \A_SPW_TOP|tx_data|mem[24][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector225~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[24][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[24][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[24][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y11_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux4~6 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux4~6_combout  = ( \A_SPW_TOP|tx_data|mem[24][4]~q  & ( \A_SPW_TOP|tx_data|wr_ptr [0] & ( (!\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|mem[25][4]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [1] & ((\A_SPW_TOP|tx_data|mem[27][4]~q ))) ) 
// ) ) # ( !\A_SPW_TOP|tx_data|mem[24][4]~q  & ( \A_SPW_TOP|tx_data|wr_ptr [0] & ( (!\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|mem[25][4]~q )) # (\A_SPW_TOP|tx_data|wr_ptr [1] & ((\A_SPW_TOP|tx_data|mem[27][4]~q ))) ) ) ) # ( 
// \A_SPW_TOP|tx_data|mem[24][4]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [0] & ( (!\A_SPW_TOP|tx_data|wr_ptr [1]) # (\A_SPW_TOP|tx_data|mem[26][4]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[24][4]~q  & ( !\A_SPW_TOP|tx_data|wr_ptr [0] & ( (\A_SPW_TOP|tx_data|wr_ptr [1] 
// & \A_SPW_TOP|tx_data|mem[26][4]~q ) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[25][4]~q ),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datac(!\A_SPW_TOP|tx_data|mem[27][4]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[26][4]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[24][4]~q ),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux4~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux4~6 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux4~6 .lut_mask = 64'h0033CCFF47474747;
defparam \A_SPW_TOP|tx_data|Mux4~6 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y10_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector459~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector459~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector455~0_combout  & ((\A_SPW_TOP|tx_data|mem[50][4]~q ))) # (\A_SPW_TOP|tx_data|Selector455~0_combout  & (\u0|write_data_fifo_tx|data_out 
// [4])) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector455~0_combout  & ((\A_SPW_TOP|tx_data|mem[50][4]~q ))) # (\A_SPW_TOP|tx_data|Selector455~0_combout  & (\A_SPW_TOP|tx_data|Mux4~20_combout )) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [4]),
        .datab(!\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|mem[50][4]~q ),
        .datad(!\A_SPW_TOP|tx_data|Selector455~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector459~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector459~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector459~0 .lut_mask = 64'h0F330F330F550F55;
defparam \A_SPW_TOP|tx_data|Selector459~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y10_N5
dffeas \A_SPW_TOP|tx_data|mem[50][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector459~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[50][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[50][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[50][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y10_N57
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector468~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector468~0_combout  = ( \A_SPW_TOP|tx_data|Selector464~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux4~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\u0|write_data_fifo_tx|data_out [4])) ) ) # ( !\A_SPW_TOP|tx_data|Selector464~0_combout  & ( \A_SPW_TOP|tx_data|mem[51][4]~q  ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [4]),
        .datab(!\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|mem[51][4]~q ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector464~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector468~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector468~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector468~0 .lut_mask = 64'h0F0F0F0F33553355;
defparam \A_SPW_TOP|tx_data|Selector468~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y10_N11
dffeas \A_SPW_TOP|tx_data|mem[51][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector468~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[51][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[51][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[51][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y10_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector441~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector441~0_combout  = ( \A_SPW_TOP|tx_data|mem[48][4]~q  & ( (!\A_SPW_TOP|tx_data|Selector437~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux4~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [4])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[48][4]~q  & ( (\A_SPW_TOP|tx_data|Selector437~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux4~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [4]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector437~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [4]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[48][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector441~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector441~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector441~0 .lut_mask = 64'h02070207F2F7F2F7;
defparam \A_SPW_TOP|tx_data|Selector441~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y10_N35
dffeas \A_SPW_TOP|tx_data|mem[48][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector441~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[48][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[48][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[48][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y10_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector450~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector450~0_combout  = ( \A_SPW_TOP|tx_data|mem[49][4]~q  & ( (!\A_SPW_TOP|tx_data|Selector446~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux4~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [4]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[49][4]~q  & ( (\A_SPW_TOP|tx_data|Selector446~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux4~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [4])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [4]),
        .datab(!\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|tx_data|Selector446~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[49][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector450~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector450~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector450~0 .lut_mask = 64'h00350035FF35FF35;
defparam \A_SPW_TOP|tx_data|Selector450~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y10_N17
dffeas \A_SPW_TOP|tx_data|mem[49][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector450~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[49][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[49][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[49][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y10_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux4~7 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux4~7_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [0] & ( \A_SPW_TOP|tx_data|wr_ptr [1] & ( \A_SPW_TOP|tx_data|mem[51][4]~q  ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [0] & ( \A_SPW_TOP|tx_data|wr_ptr [1] & ( \A_SPW_TOP|tx_data|mem[50][4]~q  ) ) 
// ) # ( \A_SPW_TOP|tx_data|wr_ptr [0] & ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( \A_SPW_TOP|tx_data|mem[49][4]~q  ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [0] & ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( \A_SPW_TOP|tx_data|mem[48][4]~q  ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[50][4]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[51][4]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[48][4]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[49][4]~q ),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux4~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux4~7 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux4~7 .lut_mask = 64'h0F0F00FF55553333;
defparam \A_SPW_TOP|tx_data|Mux4~7 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y11_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector531~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector531~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector527~0_combout  & ((\A_SPW_TOP|tx_data|mem[58][4]~q ))) # (\A_SPW_TOP|tx_data|Selector527~0_combout  & (\u0|write_data_fifo_tx|data_out 
// [4])) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector527~0_combout  & ((\A_SPW_TOP|tx_data|mem[58][4]~q ))) # (\A_SPW_TOP|tx_data|Selector527~0_combout  & (\A_SPW_TOP|tx_data|Mux4~20_combout )) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [4]),
        .datab(!\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|mem[58][4]~q ),
        .datad(!\A_SPW_TOP|tx_data|Selector527~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector531~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector531~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector531~0 .lut_mask = 64'h0F330F330F550F55;
defparam \A_SPW_TOP|tx_data|Selector531~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y11_N23
dffeas \A_SPW_TOP|tx_data|mem[58][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector531~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[58][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[58][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[58][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y11_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector522~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector522~0_combout  = ( \A_SPW_TOP|tx_data|mem[57][4]~q  & ( (!\A_SPW_TOP|tx_data|Selector518~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux4~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [4]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[57][4]~q  & ( (\A_SPW_TOP|tx_data|Selector518~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux4~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [4])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [4]),
        .datab(!\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|tx_data|Selector518~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[57][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector522~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector522~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector522~0 .lut_mask = 64'h00350035FF35FF35;
defparam \A_SPW_TOP|tx_data|Selector522~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y11_N14
dffeas \A_SPW_TOP|tx_data|mem[57][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector522~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[57][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[57][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[57][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y11_N45
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector540~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector540~0_combout  = ( \A_SPW_TOP|tx_data|mem[59][4]~q  & ( (!\A_SPW_TOP|tx_data|Selector536~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\A_SPW_TOP|tx_data|Mux4~20_combout ))) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [4]))) ) ) # ( !\A_SPW_TOP|tx_data|mem[59][4]~q  & ( (\A_SPW_TOP|tx_data|Selector536~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|tx_data|Mux4~20_combout ))) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & (\u0|write_data_fifo_tx|data_out [4])))) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [4]),
        .datab(!\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector536~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[59][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector540~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector540~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector540~0 .lut_mask = 64'h03050305F3F5F3F5;
defparam \A_SPW_TOP|tx_data|Selector540~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y11_N20
dffeas \A_SPW_TOP|tx_data|mem[59][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector540~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[59][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[59][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[59][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y11_N57
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector513~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector513~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector509~0_combout  & ((\A_SPW_TOP|tx_data|mem[56][4]~q ))) # (\A_SPW_TOP|tx_data|Selector509~0_combout  & (\u0|write_data_fifo_tx|data_out 
// [4])) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector509~0_combout  & ((\A_SPW_TOP|tx_data|mem[56][4]~q ))) # (\A_SPW_TOP|tx_data|Selector509~0_combout  & (\A_SPW_TOP|tx_data|Mux4~20_combout )) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [4]),
        .datab(!\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|mem[56][4]~q ),
        .datad(!\A_SPW_TOP|tx_data|Selector509~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector513~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector513~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector513~0 .lut_mask = 64'h0F330F330F550F55;
defparam \A_SPW_TOP|tx_data|Selector513~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y11_N8
dffeas \A_SPW_TOP|tx_data|mem[56][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector513~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[56][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[56][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[56][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y11_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux4~8 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux4~8_combout  = ( \A_SPW_TOP|tx_data|mem[59][4]~q  & ( \A_SPW_TOP|tx_data|mem[56][4]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & (((!\A_SPW_TOP|tx_data|wr_ptr [1])) # (\A_SPW_TOP|tx_data|mem[58][4]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [0] 
// & (((\A_SPW_TOP|tx_data|mem[57][4]~q ) # (\A_SPW_TOP|tx_data|wr_ptr [1])))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[59][4]~q  & ( \A_SPW_TOP|tx_data|mem[56][4]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & (((!\A_SPW_TOP|tx_data|wr_ptr [1])) # 
// (\A_SPW_TOP|tx_data|mem[58][4]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & (((!\A_SPW_TOP|tx_data|wr_ptr [1] & \A_SPW_TOP|tx_data|mem[57][4]~q )))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[59][4]~q  & ( !\A_SPW_TOP|tx_data|mem[56][4]~q  & ( 
// (!\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|mem[58][4]~q  & (\A_SPW_TOP|tx_data|wr_ptr [1]))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & (((\A_SPW_TOP|tx_data|mem[57][4]~q ) # (\A_SPW_TOP|tx_data|wr_ptr [1])))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[59][4]~q 
//  & ( !\A_SPW_TOP|tx_data|mem[56][4]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|mem[58][4]~q  & (\A_SPW_TOP|tx_data|wr_ptr [1]))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & (((!\A_SPW_TOP|tx_data|wr_ptr [1] & \A_SPW_TOP|tx_data|mem[57][4]~q )))) 
// ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[58][4]~q ),
        .datab(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datad(!\A_SPW_TOP|tx_data|mem[57][4]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[59][4]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[56][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux4~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux4~8 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux4~8 .lut_mask = 64'h04340737C4F4C7F7;
defparam \A_SPW_TOP|tx_data|Mux4~8 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y11_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux4~9 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux4~9_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [3] & ( \A_SPW_TOP|tx_data|wr_ptr [5] & ( \A_SPW_TOP|tx_data|Mux4~8_combout  ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [3] & ( \A_SPW_TOP|tx_data|wr_ptr [5] & ( \A_SPW_TOP|tx_data|Mux4~7_combout  
// ) ) ) # ( \A_SPW_TOP|tx_data|wr_ptr [3] & ( !\A_SPW_TOP|tx_data|wr_ptr [5] & ( \A_SPW_TOP|tx_data|Mux4~6_combout  ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [3] & ( !\A_SPW_TOP|tx_data|wr_ptr [5] & ( \A_SPW_TOP|tx_data|Mux4~5_combout  ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux4~5_combout ),
        .datab(!\A_SPW_TOP|tx_data|Mux4~6_combout ),
        .datac(!\A_SPW_TOP|tx_data|Mux4~7_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux4~8_combout ),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux4~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux4~9 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux4~9 .lut_mask = 64'h555533330F0F00FF;
defparam \A_SPW_TOP|tx_data|Mux4~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y9_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector189~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector189~0_combout  = ( \A_SPW_TOP|tx_data|Selector185~0_combout  & ( \u0|write_data_fifo_tx|data_out [4] & ( (\A_SPW_TOP|tx_data|Mux4~20_combout ) # (\A_SPW_TOP|tx_data|state_data_write.00~q ) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|Selector185~0_combout  & ( \u0|write_data_fifo_tx|data_out [4] & ( \A_SPW_TOP|tx_data|mem[20][4]~q  ) ) ) # ( \A_SPW_TOP|tx_data|Selector185~0_combout  & ( !\u0|write_data_fifo_tx|data_out [4] & ( 
// (!\A_SPW_TOP|tx_data|state_data_write.00~q  & \A_SPW_TOP|tx_data|Mux4~20_combout ) ) ) ) # ( !\A_SPW_TOP|tx_data|Selector185~0_combout  & ( !\u0|write_data_fifo_tx|data_out [4] & ( \A_SPW_TOP|tx_data|mem[20][4]~q  ) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[20][4]~q ),
        .datac(!\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|tx_data|Selector185~0_combout ),
        .dataf(!\u0|write_data_fifo_tx|data_out [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector189~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector189~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector189~0 .lut_mask = 64'h33330A0A33335F5F;
defparam \A_SPW_TOP|tx_data|Selector189~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y9_N14
dffeas \A_SPW_TOP|tx_data|mem[20][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector189~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[20][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[20][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[20][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y9_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector486~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector486~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector482~0_combout  & ((\A_SPW_TOP|tx_data|mem[53][4]~q ))) # (\A_SPW_TOP|tx_data|Selector482~0_combout  & (\u0|write_data_fifo_tx|data_out 
// [4])) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector482~0_combout  & ((\A_SPW_TOP|tx_data|mem[53][4]~q ))) # (\A_SPW_TOP|tx_data|Selector482~0_combout  & (\A_SPW_TOP|tx_data|Mux4~20_combout )) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [4]),
        .datac(!\A_SPW_TOP|tx_data|mem[53][4]~q ),
        .datad(!\A_SPW_TOP|tx_data|Selector482~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector486~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector486~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector486~0 .lut_mask = 64'h0F550F550F330F33;
defparam \A_SPW_TOP|tx_data|Selector486~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y9_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|mem[53][4]~feeder (
// Equation(s):
// \A_SPW_TOP|tx_data|mem[53][4]~feeder_combout  = ( \A_SPW_TOP|tx_data|Selector486~0_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector486~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|mem[53][4]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[53][4]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|mem[53][4]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|tx_data|mem[53][4]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y9_N38
dffeas \A_SPW_TOP|tx_data|mem[53][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|tx_data|mem[53][4]~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[53][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[53][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[53][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y9_N27
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector477~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector477~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector473~0_combout  & ((\A_SPW_TOP|tx_data|mem[52][4]~q ))) # (\A_SPW_TOP|tx_data|Selector473~0_combout  & (\u0|write_data_fifo_tx|data_out 
// [4])) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector473~0_combout  & ((\A_SPW_TOP|tx_data|mem[52][4]~q ))) # (\A_SPW_TOP|tx_data|Selector473~0_combout  & (\A_SPW_TOP|tx_data|Mux4~20_combout )) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [4]),
        .datac(!\A_SPW_TOP|tx_data|Selector473~0_combout ),
        .datad(!\A_SPW_TOP|tx_data|mem[52][4]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector477~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector477~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector477~0 .lut_mask = 64'h05F505F503F303F3;
defparam \A_SPW_TOP|tx_data|Selector477~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y9_N23
dffeas \A_SPW_TOP|tx_data|mem[52][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector477~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[52][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[52][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[52][4] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y9_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector198~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector198~0_combout  = ( \A_SPW_TOP|tx_data|mem[21][4]~q  & ( (!\A_SPW_TOP|tx_data|Selector194~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux4~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [4])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[21][4]~q  & ( (\A_SPW_TOP|tx_data|Selector194~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux4~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [4]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector194~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [4]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[21][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector198~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector198~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector198~0 .lut_mask = 64'h02070207F2F7F2F7;
defparam \A_SPW_TOP|tx_data|Selector198~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y9_N35
dffeas \A_SPW_TOP|tx_data|mem[21][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector198~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[21][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[21][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[21][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y9_N15
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux4~15 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux4~15_combout  = ( \A_SPW_TOP|tx_data|mem[52][4]~q  & ( \A_SPW_TOP|tx_data|mem[21][4]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [5] & (((\A_SPW_TOP|tx_data|wr_ptr [0])) # (\A_SPW_TOP|tx_data|mem[20][4]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [5] 
// & (((!\A_SPW_TOP|tx_data|wr_ptr [0]) # (\A_SPW_TOP|tx_data|mem[53][4]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[52][4]~q  & ( \A_SPW_TOP|tx_data|mem[21][4]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [5] & (((\A_SPW_TOP|tx_data|wr_ptr [0])) # 
// (\A_SPW_TOP|tx_data|mem[20][4]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [5] & (((\A_SPW_TOP|tx_data|mem[53][4]~q  & \A_SPW_TOP|tx_data|wr_ptr [0])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[52][4]~q  & ( !\A_SPW_TOP|tx_data|mem[21][4]~q  & ( 
// (!\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|mem[20][4]~q  & ((!\A_SPW_TOP|tx_data|wr_ptr [0])))) # (\A_SPW_TOP|tx_data|wr_ptr [5] & (((!\A_SPW_TOP|tx_data|wr_ptr [0]) # (\A_SPW_TOP|tx_data|mem[53][4]~q )))) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|mem[52][4]~q  & ( !\A_SPW_TOP|tx_data|mem[21][4]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [5] & (\A_SPW_TOP|tx_data|mem[20][4]~q  & ((!\A_SPW_TOP|tx_data|wr_ptr [0])))) # (\A_SPW_TOP|tx_data|wr_ptr [5] & (((\A_SPW_TOP|tx_data|mem[53][4]~q  & 
// \A_SPW_TOP|tx_data|wr_ptr [0])))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datab(!\A_SPW_TOP|tx_data|mem[20][4]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[53][4]~q ),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datae(!\A_SPW_TOP|tx_data|mem[52][4]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[21][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux4~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux4~15 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux4~15 .lut_mask = 64'h2205770522AF77AF;
defparam \A_SPW_TOP|tx_data|Mux4~15 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y8_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector216~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector216~0_combout  = ( \A_SPW_TOP|tx_data|Selector212~0_combout  & ( \A_SPW_TOP|tx_data|Mux4~20_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q ) # (\u0|write_data_fifo_tx|data_out [4]) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|Selector212~0_combout  & ( \A_SPW_TOP|tx_data|Mux4~20_combout  & ( \A_SPW_TOP|tx_data|mem[23][4]~q  ) ) ) # ( \A_SPW_TOP|tx_data|Selector212~0_combout  & ( !\A_SPW_TOP|tx_data|Mux4~20_combout  & ( 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & \u0|write_data_fifo_tx|data_out [4]) ) ) ) # ( !\A_SPW_TOP|tx_data|Selector212~0_combout  & ( !\A_SPW_TOP|tx_data|Mux4~20_combout  & ( \A_SPW_TOP|tx_data|mem[23][4]~q  ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[23][4]~q ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\u0|write_data_fifo_tx|data_out [4]),
        .datad(gnd),
        .datae(!\A_SPW_TOP|tx_data|Selector212~0_combout ),
        .dataf(!\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector216~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector216~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector216~0 .lut_mask = 64'h555503035555CFCF;
defparam \A_SPW_TOP|tx_data|Selector216~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y8_N53
dffeas \A_SPW_TOP|tx_data|mem[23][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector216~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[23][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[23][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[23][4] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y8_N57
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector495~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector495~0_combout  = ( \A_SPW_TOP|tx_data|Selector491~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux4~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [4]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector491~0_combout  & ( \A_SPW_TOP|tx_data|mem[54][4]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[54][4]~q ),
        .datad(!\u0|write_data_fifo_tx|data_out [4]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector491~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector495~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector495~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector495~0 .lut_mask = 64'h0F0F0F0F44774477;
defparam \A_SPW_TOP|tx_data|Selector495~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y8_N41
dffeas \A_SPW_TOP|tx_data|mem[54][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector495~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[54][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[54][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[54][4] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y8_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector504~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector504~0_combout  = ( \u0|write_data_fifo_tx|data_out [4] & ( (!\A_SPW_TOP|tx_data|Selector500~0_combout  & (((\A_SPW_TOP|tx_data|mem[55][4]~q )))) # (\A_SPW_TOP|tx_data|Selector500~0_combout  & 
// (((\A_SPW_TOP|tx_data|state_data_write.00~q )) # (\A_SPW_TOP|tx_data|Mux4~20_combout ))) ) ) # ( !\u0|write_data_fifo_tx|data_out [4] & ( (!\A_SPW_TOP|tx_data|Selector500~0_combout  & (((\A_SPW_TOP|tx_data|mem[55][4]~q )))) # 
// (\A_SPW_TOP|tx_data|Selector500~0_combout  & (\A_SPW_TOP|tx_data|Mux4~20_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q )))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|Selector500~0_combout ),
        .datac(!\A_SPW_TOP|tx_data|mem[55][4]~q ),
        .datad(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datae(!\u0|write_data_fifo_tx|data_out [4]),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector504~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector504~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector504~0 .lut_mask = 64'h1D0C1D3F1D0C1D3F;
defparam \A_SPW_TOP|tx_data|Selector504~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y8_N23
dffeas \A_SPW_TOP|tx_data|mem[55][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector504~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[55][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[55][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[55][4] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y8_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector207~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector207~0_combout  = ( \A_SPW_TOP|tx_data|Selector203~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux4~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [4]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector203~0_combout  & ( \A_SPW_TOP|tx_data|mem[22][4]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[22][4]~q ),
        .datad(!\u0|write_data_fifo_tx|data_out [4]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector203~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector207~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector207~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector207~0 .lut_mask = 64'h0F0F0F0F44774477;
defparam \A_SPW_TOP|tx_data|Selector207~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y8_N26
dffeas \A_SPW_TOP|tx_data|mem[22][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector207~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[22][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[22][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[22][4] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y8_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux4~17 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux4~17_combout  = ( \A_SPW_TOP|tx_data|mem[55][4]~q  & ( \A_SPW_TOP|tx_data|mem[22][4]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & (((!\A_SPW_TOP|tx_data|wr_ptr [5]) # (\A_SPW_TOP|tx_data|mem[54][4]~q )))) # (\A_SPW_TOP|tx_data|wr_ptr [0] 
// & (((\A_SPW_TOP|tx_data|wr_ptr [5])) # (\A_SPW_TOP|tx_data|mem[23][4]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[55][4]~q  & ( \A_SPW_TOP|tx_data|mem[22][4]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & (((!\A_SPW_TOP|tx_data|wr_ptr [5]) # 
// (\A_SPW_TOP|tx_data|mem[54][4]~q )))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|mem[23][4]~q  & ((!\A_SPW_TOP|tx_data|wr_ptr [5])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[55][4]~q  & ( !\A_SPW_TOP|tx_data|mem[22][4]~q  & ( 
// (!\A_SPW_TOP|tx_data|wr_ptr [0] & (((\A_SPW_TOP|tx_data|mem[54][4]~q  & \A_SPW_TOP|tx_data|wr_ptr [5])))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & (((\A_SPW_TOP|tx_data|wr_ptr [5])) # (\A_SPW_TOP|tx_data|mem[23][4]~q ))) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|mem[55][4]~q  & ( !\A_SPW_TOP|tx_data|mem[22][4]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & (((\A_SPW_TOP|tx_data|mem[54][4]~q  & \A_SPW_TOP|tx_data|wr_ptr [5])))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|mem[23][4]~q  & 
// ((!\A_SPW_TOP|tx_data|wr_ptr [5])))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[23][4]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[54][4]~q ),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datad(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .datae(!\A_SPW_TOP|tx_data|mem[55][4]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[22][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux4~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux4~17 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux4~17 .lut_mask = 64'h0530053FF530F53F;
defparam \A_SPW_TOP|tx_data|Mux4~17 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y9_N45
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector558~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector558~0_combout  = ( \A_SPW_TOP|tx_data|mem[61][4]~q  & ( (!\A_SPW_TOP|tx_data|Selector554~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux4~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [4])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[61][4]~q  & ( (\A_SPW_TOP|tx_data|Selector554~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux4~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [4]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [4]),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|tx_data|Selector554~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[61][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector558~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector558~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector558~0 .lut_mask = 64'h00530053FF53FF53;
defparam \A_SPW_TOP|tx_data|Selector558~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y9_N35
dffeas \A_SPW_TOP|tx_data|mem[61][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector558~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[61][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[61][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[61][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y9_N57
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector549~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector549~0_combout  = ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector545~0_combout  & ((\A_SPW_TOP|tx_data|mem[60][4]~q ))) # (\A_SPW_TOP|tx_data|Selector545~0_combout  & (\u0|write_data_fifo_tx|data_out 
// [4])) ) ) # ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|Selector545~0_combout  & ((\A_SPW_TOP|tx_data|mem[60][4]~q ))) # (\A_SPW_TOP|tx_data|Selector545~0_combout  & (\A_SPW_TOP|tx_data|Mux4~20_combout )) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .datab(!\u0|write_data_fifo_tx|data_out [4]),
        .datac(!\A_SPW_TOP|tx_data|mem[60][4]~q ),
        .datad(!\A_SPW_TOP|tx_data|Selector545~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector549~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector549~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector549~0 .lut_mask = 64'h0F550F550F330F33;
defparam \A_SPW_TOP|tx_data|Selector549~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y9_N41
dffeas \A_SPW_TOP|tx_data|mem[60][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector549~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[60][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[60][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[60][4] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y9_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector270~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector270~0_combout  = ( \A_SPW_TOP|tx_data|mem[29][4]~q  & ( (!\A_SPW_TOP|tx_data|Selector266~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux4~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [4])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[29][4]~q  & ( (\A_SPW_TOP|tx_data|Selector266~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux4~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [4]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector266~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [4]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[29][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector270~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector270~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector270~0 .lut_mask = 64'h02070207F2F7F2F7;
defparam \A_SPW_TOP|tx_data|Selector270~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y9_N14
dffeas \A_SPW_TOP|tx_data|mem[29][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector270~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[29][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[29][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[29][4] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y9_N45
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector261~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector261~0_combout  = ( \A_SPW_TOP|tx_data|mem[28][4]~q  & ( (!\A_SPW_TOP|tx_data|Selector257~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux4~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [4])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[28][4]~q  & ( (\A_SPW_TOP|tx_data|Selector257~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux4~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [4]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .datac(!\A_SPW_TOP|tx_data|Selector257~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [4]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[28][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector261~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector261~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector261~0 .lut_mask = 64'h02070207F2F7F2F7;
defparam \A_SPW_TOP|tx_data|Selector261~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y9_N53
dffeas \A_SPW_TOP|tx_data|mem[28][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector261~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[28][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[28][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[28][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y9_N51
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux4~16 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux4~16_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [5] & ( \A_SPW_TOP|tx_data|wr_ptr [0] & ( \A_SPW_TOP|tx_data|mem[61][4]~q  ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [5] & ( \A_SPW_TOP|tx_data|wr_ptr [0] & ( \A_SPW_TOP|tx_data|mem[29][4]~q  ) 
// ) ) # ( \A_SPW_TOP|tx_data|wr_ptr [5] & ( !\A_SPW_TOP|tx_data|wr_ptr [0] & ( \A_SPW_TOP|tx_data|mem[60][4]~q  ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [5] & ( !\A_SPW_TOP|tx_data|wr_ptr [0] & ( \A_SPW_TOP|tx_data|mem[28][4]~q  ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[61][4]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[60][4]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[29][4]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[28][4]~q ),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux4~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux4~16 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux4~16 .lut_mask = 64'h00FF33330F0F5555;
defparam \A_SPW_TOP|tx_data|Mux4~16 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y8_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector576~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector576~0_combout  = ( \A_SPW_TOP|tx_data|mem[63][4]~q  & ( (!\A_SPW_TOP|tx_data|Selector572~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux4~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [4])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[63][4]~q  & ( (\A_SPW_TOP|tx_data|Selector572~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux4~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [4]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector572~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [4]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[63][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector576~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector576~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector576~0 .lut_mask = 64'h04070407F4F7F4F7;
defparam \A_SPW_TOP|tx_data|Selector576~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y8_N8
dffeas \A_SPW_TOP|tx_data|mem[63][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector576~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[63][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[63][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[63][4] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y8_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector288~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector288~0_combout  = ( \A_SPW_TOP|tx_data|Selector284~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux4~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// ((\u0|write_data_fifo_tx|data_out [4]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector284~0_combout  & ( \A_SPW_TOP|tx_data|mem[31][4]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[31][4]~q ),
        .datad(!\u0|write_data_fifo_tx|data_out [4]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector284~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector288~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector288~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector288~0 .lut_mask = 64'h0F0F0F0F44774477;
defparam \A_SPW_TOP|tx_data|Selector288~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y8_N35
dffeas \A_SPW_TOP|tx_data|mem[31][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector288~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[31][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[31][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[31][4] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y8_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector279~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector279~0_combout  = ( \A_SPW_TOP|tx_data|mem[30][4]~q  & ( (!\A_SPW_TOP|tx_data|Selector275~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux4~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [4])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[30][4]~q  & ( (\A_SPW_TOP|tx_data|Selector275~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux4~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [4]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector275~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [4]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[30][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector279~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector279~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector279~0 .lut_mask = 64'h04070407F4F7F4F7;
defparam \A_SPW_TOP|tx_data|Selector279~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y8_N17
dffeas \A_SPW_TOP|tx_data|mem[30][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector279~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[30][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[30][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[30][4] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y8_N45
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector567~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector567~0_combout  = ( \A_SPW_TOP|tx_data|mem[62][4]~q  & ( (!\A_SPW_TOP|tx_data|Selector563~0_combout ) # ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux4~20_combout )) # 
// (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [4])))) ) ) # ( !\A_SPW_TOP|tx_data|mem[62][4]~q  & ( (\A_SPW_TOP|tx_data|Selector563~0_combout  & ((!\A_SPW_TOP|tx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|tx_data|Mux4~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out [4]))))) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|tx_data|Selector563~0_combout ),
        .datad(!\u0|write_data_fifo_tx|data_out [4]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|mem[62][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector567~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector567~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector567~0 .lut_mask = 64'h04070407F4F7F4F7;
defparam \A_SPW_TOP|tx_data|Selector567~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y8_N11
dffeas \A_SPW_TOP|tx_data|mem[62][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector567~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[62][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[62][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[62][4] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y8_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux4~18 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux4~18_combout  = ( \A_SPW_TOP|tx_data|wr_ptr [5] & ( \A_SPW_TOP|tx_data|mem[62][4]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [0]) # (\A_SPW_TOP|tx_data|mem[63][4]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [5] & ( 
// \A_SPW_TOP|tx_data|mem[62][4]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|mem[30][4]~q ))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|mem[31][4]~q )) ) ) ) # ( \A_SPW_TOP|tx_data|wr_ptr [5] & ( 
// !\A_SPW_TOP|tx_data|mem[62][4]~q  & ( (\A_SPW_TOP|tx_data|wr_ptr [0] & \A_SPW_TOP|tx_data|mem[63][4]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [5] & ( !\A_SPW_TOP|tx_data|mem[62][4]~q  & ( (!\A_SPW_TOP|tx_data|wr_ptr [0] & ((\A_SPW_TOP|tx_data|mem[30][4]~q 
// ))) # (\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|mem[31][4]~q )) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [0]),
        .datab(!\A_SPW_TOP|tx_data|mem[63][4]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[31][4]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[30][4]~q ),
        .datae(!\A_SPW_TOP|tx_data|wr_ptr [5]),
        .dataf(!\A_SPW_TOP|tx_data|mem[62][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux4~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux4~18 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux4~18 .lut_mask = 64'h05AF111105AFBBBB;
defparam \A_SPW_TOP|tx_data|Mux4~18 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y8_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux4~19 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux4~19_combout  = ( \A_SPW_TOP|tx_data|Mux4~16_combout  & ( \A_SPW_TOP|tx_data|Mux4~18_combout  & ( ((!\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|Mux4~15_combout )) # (\A_SPW_TOP|tx_data|wr_ptr [1] & 
// ((\A_SPW_TOP|tx_data|Mux4~17_combout )))) # (\A_SPW_TOP|tx_data|wr_ptr [3]) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux4~16_combout  & ( \A_SPW_TOP|tx_data|Mux4~18_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [3] & ((!\A_SPW_TOP|tx_data|wr_ptr [1] & 
// (\A_SPW_TOP|tx_data|Mux4~15_combout )) # (\A_SPW_TOP|tx_data|wr_ptr [1] & ((\A_SPW_TOP|tx_data|Mux4~17_combout ))))) # (\A_SPW_TOP|tx_data|wr_ptr [3] & (((\A_SPW_TOP|tx_data|wr_ptr [1])))) ) ) ) # ( \A_SPW_TOP|tx_data|Mux4~16_combout  & ( 
// !\A_SPW_TOP|tx_data|Mux4~18_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [3] & ((!\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|Mux4~15_combout )) # (\A_SPW_TOP|tx_data|wr_ptr [1] & ((\A_SPW_TOP|tx_data|Mux4~17_combout ))))) # (\A_SPW_TOP|tx_data|wr_ptr 
// [3] & (((!\A_SPW_TOP|tx_data|wr_ptr [1])))) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux4~16_combout  & ( !\A_SPW_TOP|tx_data|Mux4~18_combout  & ( (!\A_SPW_TOP|tx_data|wr_ptr [3] & ((!\A_SPW_TOP|tx_data|wr_ptr [1] & (\A_SPW_TOP|tx_data|Mux4~15_combout )) # 
// (\A_SPW_TOP|tx_data|wr_ptr [1] & ((\A_SPW_TOP|tx_data|Mux4~17_combout ))))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|wr_ptr [3]),
        .datab(!\A_SPW_TOP|tx_data|Mux4~15_combout ),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [1]),
        .datad(!\A_SPW_TOP|tx_data|Mux4~17_combout ),
        .datae(!\A_SPW_TOP|tx_data|Mux4~16_combout ),
        .dataf(!\A_SPW_TOP|tx_data|Mux4~18_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux4~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux4~19 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux4~19 .lut_mask = 64'h202A707A252F757F;
defparam \A_SPW_TOP|tx_data|Mux4~19 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y10_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux4~20 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux4~20_combout  = ( \A_SPW_TOP|tx_data|Mux4~19_combout  & ( \A_SPW_TOP|tx_data|wr_ptr [4] & ( (\A_SPW_TOP|tx_data|Mux4~9_combout ) # (\A_SPW_TOP|tx_data|wr_ptr [2]) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux4~19_combout  & ( 
// \A_SPW_TOP|tx_data|wr_ptr [4] & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & \A_SPW_TOP|tx_data|Mux4~9_combout ) ) ) ) # ( \A_SPW_TOP|tx_data|Mux4~19_combout  & ( !\A_SPW_TOP|tx_data|wr_ptr [4] & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & 
// (\A_SPW_TOP|tx_data|Mux4~4_combout )) # (\A_SPW_TOP|tx_data|wr_ptr [2] & ((\A_SPW_TOP|tx_data|Mux4~14_combout ))) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux4~19_combout  & ( !\A_SPW_TOP|tx_data|wr_ptr [4] & ( (!\A_SPW_TOP|tx_data|wr_ptr [2] & 
// (\A_SPW_TOP|tx_data|Mux4~4_combout )) # (\A_SPW_TOP|tx_data|wr_ptr [2] & ((\A_SPW_TOP|tx_data|Mux4~14_combout ))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux4~4_combout ),
        .datab(!\A_SPW_TOP|tx_data|Mux4~14_combout ),
        .datac(!\A_SPW_TOP|tx_data|wr_ptr [2]),
        .datad(!\A_SPW_TOP|tx_data|Mux4~9_combout ),
        .datae(!\A_SPW_TOP|tx_data|Mux4~19_combout ),
        .dataf(!\A_SPW_TOP|tx_data|wr_ptr [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux4~20 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux4~20 .lut_mask = 64'h5353535300F00FFF;
defparam \A_SPW_TOP|tx_data|Mux4~20 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y11_N57
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Selector9~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Selector9~0_combout  = ( \A_SPW_TOP|tx_data|Selector5~0_combout  & ( (!\A_SPW_TOP|tx_data|state_data_write.00~q  & (\A_SPW_TOP|tx_data|Mux4~20_combout )) # (\A_SPW_TOP|tx_data|state_data_write.00~q  & ((\u0|write_data_fifo_tx|data_out 
// [4]))) ) ) # ( !\A_SPW_TOP|tx_data|Selector5~0_combout  & ( \A_SPW_TOP|tx_data|mem[0][4]~q  ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|tx_data|Mux4~20_combout ),
        .datac(!\u0|write_data_fifo_tx|data_out [4]),
        .datad(!\A_SPW_TOP|tx_data|mem[0][4]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|Selector5~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Selector9~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Selector9~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Selector9~0 .lut_mask = 64'h00FF00FF27272727;
defparam \A_SPW_TOP|tx_data|Selector9~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y11_N29
dffeas \A_SPW_TOP|tx_data|mem[0][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Selector9~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|mem[0][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem[0][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem[0][4] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y11_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux13~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux13~0_combout  = ( \A_SPW_TOP|tx_data|rd_ptr [4] & ( \A_SPW_TOP|tx_data|mem[1][4]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|mem[16][4]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [0] & ((\A_SPW_TOP|tx_data|mem[17][4]~q ))) ) 
// ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [4] & ( \A_SPW_TOP|tx_data|mem[1][4]~q  & ( (\A_SPW_TOP|tx_data|rd_ptr [0]) # (\A_SPW_TOP|tx_data|mem[0][4]~q ) ) ) ) # ( \A_SPW_TOP|tx_data|rd_ptr [4] & ( !\A_SPW_TOP|tx_data|mem[1][4]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr 
// [0] & (\A_SPW_TOP|tx_data|mem[16][4]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [0] & ((\A_SPW_TOP|tx_data|mem[17][4]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [4] & ( !\A_SPW_TOP|tx_data|mem[1][4]~q  & ( (\A_SPW_TOP|tx_data|mem[0][4]~q  & 
// !\A_SPW_TOP|tx_data|rd_ptr [0]) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[0][4]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[16][4]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[17][4]~q ),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .datae(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .dataf(!\A_SPW_TOP|tx_data|mem[1][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux13~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux13~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux13~0 .lut_mask = 64'h5500330F55FF330F;
defparam \A_SPW_TOP|tx_data|Mux13~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y11_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux13~3 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux13~3_combout  = ( \A_SPW_TOP|tx_data|mem[57][4]~q  & ( \A_SPW_TOP|tx_data|mem[56][4]~q  & ( ((!\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|mem[40][4]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [0] & ((\A_SPW_TOP|tx_data|mem[41][4]~q 
// )))) # (\A_SPW_TOP|tx_data|rd_ptr [4]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[57][4]~q  & ( \A_SPW_TOP|tx_data|mem[56][4]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [0] & (((\A_SPW_TOP|tx_data|rd_ptr [4])) # (\A_SPW_TOP|tx_data|mem[40][4]~q ))) # 
// (\A_SPW_TOP|tx_data|rd_ptr [0] & (((!\A_SPW_TOP|tx_data|rd_ptr [4] & \A_SPW_TOP|tx_data|mem[41][4]~q )))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[57][4]~q  & ( !\A_SPW_TOP|tx_data|mem[56][4]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [0] & 
// (\A_SPW_TOP|tx_data|mem[40][4]~q  & (!\A_SPW_TOP|tx_data|rd_ptr [4]))) # (\A_SPW_TOP|tx_data|rd_ptr [0] & (((\A_SPW_TOP|tx_data|mem[41][4]~q ) # (\A_SPW_TOP|tx_data|rd_ptr [4])))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[57][4]~q  & ( 
// !\A_SPW_TOP|tx_data|mem[56][4]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & ((!\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|mem[40][4]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [0] & ((\A_SPW_TOP|tx_data|mem[41][4]~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .datab(!\A_SPW_TOP|tx_data|mem[40][4]~q ),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .datad(!\A_SPW_TOP|tx_data|mem[41][4]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[57][4]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[56][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux13~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux13~3 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux13~3 .lut_mask = 64'h207025752A7A2F7F;
defparam \A_SPW_TOP|tx_data|Mux13~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y11_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux13~2 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux13~2_combout  = ( \A_SPW_TOP|tx_data|mem[25][4]~q  & ( \A_SPW_TOP|tx_data|mem[8][4]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & (((!\A_SPW_TOP|tx_data|rd_ptr [0])) # (\A_SPW_TOP|tx_data|mem[9][4]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [4] & 
// (((\A_SPW_TOP|tx_data|rd_ptr [0]) # (\A_SPW_TOP|tx_data|mem[24][4]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[25][4]~q  & ( \A_SPW_TOP|tx_data|mem[8][4]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & (((!\A_SPW_TOP|tx_data|rd_ptr [0])) # 
// (\A_SPW_TOP|tx_data|mem[9][4]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [4] & (((\A_SPW_TOP|tx_data|mem[24][4]~q  & !\A_SPW_TOP|tx_data|rd_ptr [0])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[25][4]~q  & ( !\A_SPW_TOP|tx_data|mem[8][4]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr 
// [4] & (\A_SPW_TOP|tx_data|mem[9][4]~q  & ((\A_SPW_TOP|tx_data|rd_ptr [0])))) # (\A_SPW_TOP|tx_data|rd_ptr [4] & (((\A_SPW_TOP|tx_data|rd_ptr [0]) # (\A_SPW_TOP|tx_data|mem[24][4]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[25][4]~q  & ( 
// !\A_SPW_TOP|tx_data|mem[8][4]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & (\A_SPW_TOP|tx_data|mem[9][4]~q  & ((\A_SPW_TOP|tx_data|rd_ptr [0])))) # (\A_SPW_TOP|tx_data|rd_ptr [4] & (((\A_SPW_TOP|tx_data|mem[24][4]~q  & !\A_SPW_TOP|tx_data|rd_ptr [0])))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[9][4]~q ),
        .datab(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .datac(!\A_SPW_TOP|tx_data|mem[24][4]~q ),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .datae(!\A_SPW_TOP|tx_data|mem[25][4]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[8][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux13~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux13~2 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux13~2 .lut_mask = 64'h03440377CF44CF77;
defparam \A_SPW_TOP|tx_data|Mux13~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y10_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux13~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux13~1_combout  = ( \A_SPW_TOP|tx_data|mem[33][4]~q  & ( \A_SPW_TOP|tx_data|rd_ptr [0] & ( (!\A_SPW_TOP|tx_data|rd_ptr [4]) # (\A_SPW_TOP|tx_data|mem[49][4]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[33][4]~q  & ( \A_SPW_TOP|tx_data|rd_ptr 
// [0] & ( (\A_SPW_TOP|tx_data|rd_ptr [4] & \A_SPW_TOP|tx_data|mem[49][4]~q ) ) ) ) # ( \A_SPW_TOP|tx_data|mem[33][4]~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [0] & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & ((\A_SPW_TOP|tx_data|mem[32][4]~q ))) # 
// (\A_SPW_TOP|tx_data|rd_ptr [4] & (\A_SPW_TOP|tx_data|mem[48][4]~q )) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[33][4]~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [0] & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & ((\A_SPW_TOP|tx_data|mem[32][4]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr 
// [4] & (\A_SPW_TOP|tx_data|mem[48][4]~q )) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[48][4]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[32][4]~q ),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .datad(!\A_SPW_TOP|tx_data|mem[49][4]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[33][4]~q ),
        .dataf(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux13~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux13~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux13~1 .lut_mask = 64'h35353535000FF0FF;
defparam \A_SPW_TOP|tx_data|Mux13~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X53_Y11_N33
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux13~4 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux13~4_combout  = ( \A_SPW_TOP|tx_data|rd_ptr [3] & ( \A_SPW_TOP|tx_data|Mux13~1_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & ((\A_SPW_TOP|tx_data|Mux13~2_combout ))) # (\A_SPW_TOP|tx_data|rd_ptr [5] & 
// (\A_SPW_TOP|tx_data|Mux13~3_combout )) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [3] & ( \A_SPW_TOP|tx_data|Mux13~1_combout  & ( (\A_SPW_TOP|tx_data|Mux13~0_combout ) # (\A_SPW_TOP|tx_data|rd_ptr [5]) ) ) ) # ( \A_SPW_TOP|tx_data|rd_ptr [3] & ( 
// !\A_SPW_TOP|tx_data|Mux13~1_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & ((\A_SPW_TOP|tx_data|Mux13~2_combout ))) # (\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|Mux13~3_combout )) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [3] & ( 
// !\A_SPW_TOP|tx_data|Mux13~1_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & \A_SPW_TOP|tx_data|Mux13~0_combout ) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [5]),
        .datab(!\A_SPW_TOP|tx_data|Mux13~0_combout ),
        .datac(!\A_SPW_TOP|tx_data|Mux13~3_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux13~2_combout ),
        .datae(!\A_SPW_TOP|tx_data|rd_ptr [3]),
        .dataf(!\A_SPW_TOP|tx_data|Mux13~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux13~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux13~4 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux13~4 .lut_mask = 64'h222205AF777705AF;
defparam \A_SPW_TOP|tx_data|Mux13~4 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y11_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux13~10 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux13~10_combout  = ( \A_SPW_TOP|tx_data|mem[18][4]~q  & ( \A_SPW_TOP|tx_data|rd_ptr [0] & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & (\A_SPW_TOP|tx_data|mem[3][4]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [4] & ((\A_SPW_TOP|tx_data|mem[19][4]~q ))) ) 
// ) ) # ( !\A_SPW_TOP|tx_data|mem[18][4]~q  & ( \A_SPW_TOP|tx_data|rd_ptr [0] & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & (\A_SPW_TOP|tx_data|mem[3][4]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [4] & ((\A_SPW_TOP|tx_data|mem[19][4]~q ))) ) ) ) # ( 
// \A_SPW_TOP|tx_data|mem[18][4]~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [0] & ( (\A_SPW_TOP|tx_data|mem[2][4]~q ) # (\A_SPW_TOP|tx_data|rd_ptr [4]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[18][4]~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [0] & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] 
// & \A_SPW_TOP|tx_data|mem[2][4]~q ) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .datab(!\A_SPW_TOP|tx_data|mem[3][4]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[2][4]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[19][4]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[18][4]~q ),
        .dataf(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux13~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux13~10 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux13~10 .lut_mask = 64'h0A0A5F5F22772277;
defparam \A_SPW_TOP|tx_data|Mux13~10 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y11_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux13~13 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux13~13_combout  = ( \A_SPW_TOP|tx_data|mem[58][4]~q  & ( \A_SPW_TOP|tx_data|mem[59][4]~q  & ( ((!\A_SPW_TOP|tx_data|rd_ptr [0] & ((\A_SPW_TOP|tx_data|mem[42][4]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|mem[43][4]~q 
// ))) # (\A_SPW_TOP|tx_data|rd_ptr [4]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[58][4]~q  & ( \A_SPW_TOP|tx_data|mem[59][4]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [0] & (((\A_SPW_TOP|tx_data|mem[42][4]~q  & !\A_SPW_TOP|tx_data|rd_ptr [4])))) # 
// (\A_SPW_TOP|tx_data|rd_ptr [0] & (((\A_SPW_TOP|tx_data|rd_ptr [4])) # (\A_SPW_TOP|tx_data|mem[43][4]~q ))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[58][4]~q  & ( !\A_SPW_TOP|tx_data|mem[59][4]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [0] & (((\A_SPW_TOP|tx_data|rd_ptr 
// [4]) # (\A_SPW_TOP|tx_data|mem[42][4]~q )))) # (\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|mem[43][4]~q  & ((!\A_SPW_TOP|tx_data|rd_ptr [4])))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[58][4]~q  & ( !\A_SPW_TOP|tx_data|mem[59][4]~q  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [4] & ((!\A_SPW_TOP|tx_data|rd_ptr [0] & ((\A_SPW_TOP|tx_data|mem[42][4]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|mem[43][4]~q )))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[43][4]~q ),
        .datab(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .datac(!\A_SPW_TOP|tx_data|mem[42][4]~q ),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .datae(!\A_SPW_TOP|tx_data|mem[58][4]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[59][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux13~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux13~13 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux13~13 .lut_mask = 64'h1D001DCC1D331DFF;
defparam \A_SPW_TOP|tx_data|Mux13~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y11_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux13~12 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux13~12_combout  = ( \A_SPW_TOP|tx_data|rd_ptr [0] & ( \A_SPW_TOP|tx_data|mem[26][4]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & ((\A_SPW_TOP|tx_data|mem[11][4]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [4] & (\A_SPW_TOP|tx_data|mem[27][4]~q )) 
// ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [0] & ( \A_SPW_TOP|tx_data|mem[26][4]~q  & ( (\A_SPW_TOP|tx_data|rd_ptr [4]) # (\A_SPW_TOP|tx_data|mem[10][4]~q ) ) ) ) # ( \A_SPW_TOP|tx_data|rd_ptr [0] & ( !\A_SPW_TOP|tx_data|mem[26][4]~q  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [4] & ((\A_SPW_TOP|tx_data|mem[11][4]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [4] & (\A_SPW_TOP|tx_data|mem[27][4]~q )) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [0] & ( !\A_SPW_TOP|tx_data|mem[26][4]~q  & ( 
// (\A_SPW_TOP|tx_data|mem[10][4]~q  & !\A_SPW_TOP|tx_data|rd_ptr [4]) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[10][4]~q ),
        .datab(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .datac(!\A_SPW_TOP|tx_data|mem[27][4]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[11][4]~q ),
        .datae(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .dataf(!\A_SPW_TOP|tx_data|mem[26][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux13~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux13~12 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux13~12 .lut_mask = 64'h444403CF777703CF;
defparam \A_SPW_TOP|tx_data|Mux13~12 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y10_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux13~11 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux13~11_combout  = ( \A_SPW_TOP|tx_data|mem[35][4]~q  & ( \A_SPW_TOP|tx_data|rd_ptr [0] & ( (!\A_SPW_TOP|tx_data|rd_ptr [4]) # (\A_SPW_TOP|tx_data|mem[51][4]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[35][4]~q  & ( \A_SPW_TOP|tx_data|rd_ptr 
// [0] & ( (\A_SPW_TOP|tx_data|mem[51][4]~q  & \A_SPW_TOP|tx_data|rd_ptr [4]) ) ) ) # ( \A_SPW_TOP|tx_data|mem[35][4]~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [0] & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & ((\A_SPW_TOP|tx_data|mem[34][4]~q ))) # 
// (\A_SPW_TOP|tx_data|rd_ptr [4] & (\A_SPW_TOP|tx_data|mem[50][4]~q )) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[35][4]~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [0] & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & ((\A_SPW_TOP|tx_data|mem[34][4]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr 
// [4] & (\A_SPW_TOP|tx_data|mem[50][4]~q )) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[50][4]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[51][4]~q ),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .datad(!\A_SPW_TOP|tx_data|mem[34][4]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[35][4]~q ),
        .dataf(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux13~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux13~11 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux13~11 .lut_mask = 64'h05F505F50303F3F3;
defparam \A_SPW_TOP|tx_data|Mux13~11 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X53_Y11_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux13~14 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux13~14_combout  = ( \A_SPW_TOP|tx_data|rd_ptr [3] & ( \A_SPW_TOP|tx_data|Mux13~11_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & ((\A_SPW_TOP|tx_data|Mux13~12_combout ))) # (\A_SPW_TOP|tx_data|rd_ptr [5] & 
// (\A_SPW_TOP|tx_data|Mux13~13_combout )) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [3] & ( \A_SPW_TOP|tx_data|Mux13~11_combout  & ( (\A_SPW_TOP|tx_data|rd_ptr [5]) # (\A_SPW_TOP|tx_data|Mux13~10_combout ) ) ) ) # ( \A_SPW_TOP|tx_data|rd_ptr [3] & ( 
// !\A_SPW_TOP|tx_data|Mux13~11_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & ((\A_SPW_TOP|tx_data|Mux13~12_combout ))) # (\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|Mux13~13_combout )) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [3] & ( 
// !\A_SPW_TOP|tx_data|Mux13~11_combout  & ( (\A_SPW_TOP|tx_data|Mux13~10_combout  & !\A_SPW_TOP|tx_data|rd_ptr [5]) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux13~10_combout ),
        .datab(!\A_SPW_TOP|tx_data|Mux13~13_combout ),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [5]),
        .datad(!\A_SPW_TOP|tx_data|Mux13~12_combout ),
        .datae(!\A_SPW_TOP|tx_data|rd_ptr [3]),
        .dataf(!\A_SPW_TOP|tx_data|Mux13~11_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux13~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux13~14 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux13~14 .lut_mask = 64'h505003F35F5F03F3;
defparam \A_SPW_TOP|tx_data|Mux13~14 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y8_N27
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux13~18 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux13~18_combout  = ( \A_SPW_TOP|tx_data|rd_ptr [0] & ( \A_SPW_TOP|tx_data|mem[62][4]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & ((\A_SPW_TOP|tx_data|mem[31][4]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|mem[63][4]~q )) 
// ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [0] & ( \A_SPW_TOP|tx_data|mem[62][4]~q  & ( (\A_SPW_TOP|tx_data|mem[30][4]~q ) # (\A_SPW_TOP|tx_data|rd_ptr [5]) ) ) ) # ( \A_SPW_TOP|tx_data|rd_ptr [0] & ( !\A_SPW_TOP|tx_data|mem[62][4]~q  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [5] & ((\A_SPW_TOP|tx_data|mem[31][4]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|mem[63][4]~q )) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [0] & ( !\A_SPW_TOP|tx_data|mem[62][4]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr 
// [5] & \A_SPW_TOP|tx_data|mem[30][4]~q ) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [5]),
        .datab(!\A_SPW_TOP|tx_data|mem[63][4]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[30][4]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[31][4]~q ),
        .datae(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .dataf(!\A_SPW_TOP|tx_data|mem[62][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux13~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux13~18 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux13~18 .lut_mask = 64'h0A0A11BB5F5F11BB;
defparam \A_SPW_TOP|tx_data|Mux13~18 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y8_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux13~17 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux13~17_combout  = ( \A_SPW_TOP|tx_data|mem[55][4]~q  & ( \A_SPW_TOP|tx_data|mem[22][4]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & (((!\A_SPW_TOP|tx_data|rd_ptr [0]) # (\A_SPW_TOP|tx_data|mem[23][4]~q )))) # (\A_SPW_TOP|tx_data|rd_ptr 
// [5] & (((\A_SPW_TOP|tx_data|rd_ptr [0])) # (\A_SPW_TOP|tx_data|mem[54][4]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[55][4]~q  & ( \A_SPW_TOP|tx_data|mem[22][4]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & (((!\A_SPW_TOP|tx_data|rd_ptr [0]) # 
// (\A_SPW_TOP|tx_data|mem[23][4]~q )))) # (\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|mem[54][4]~q  & ((!\A_SPW_TOP|tx_data|rd_ptr [0])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[55][4]~q  & ( !\A_SPW_TOP|tx_data|mem[22][4]~q  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [5] & (((\A_SPW_TOP|tx_data|mem[23][4]~q  & \A_SPW_TOP|tx_data|rd_ptr [0])))) # (\A_SPW_TOP|tx_data|rd_ptr [5] & (((\A_SPW_TOP|tx_data|rd_ptr [0])) # (\A_SPW_TOP|tx_data|mem[54][4]~q ))) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|mem[55][4]~q  & ( !\A_SPW_TOP|tx_data|mem[22][4]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & (((\A_SPW_TOP|tx_data|mem[23][4]~q  & \A_SPW_TOP|tx_data|rd_ptr [0])))) # (\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|mem[54][4]~q  & 
// ((!\A_SPW_TOP|tx_data|rd_ptr [0])))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [5]),
        .datab(!\A_SPW_TOP|tx_data|mem[54][4]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[23][4]~q ),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .datae(!\A_SPW_TOP|tx_data|mem[55][4]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[22][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux13~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux13~17 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux13~17 .lut_mask = 64'h110A115FBB0ABB5F;
defparam \A_SPW_TOP|tx_data|Mux13~17 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y9_N27
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux13~15 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux13~15_combout  = ( \A_SPW_TOP|tx_data|mem[39][4]~q  & ( \A_SPW_TOP|tx_data|rd_ptr [0] & ( (\A_SPW_TOP|tx_data|rd_ptr [5]) # (\A_SPW_TOP|tx_data|mem[7][4]~q ) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[39][4]~q  & ( \A_SPW_TOP|tx_data|rd_ptr 
// [0] & ( (\A_SPW_TOP|tx_data|mem[7][4]~q  & !\A_SPW_TOP|tx_data|rd_ptr [5]) ) ) ) # ( \A_SPW_TOP|tx_data|mem[39][4]~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [0] & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|mem[6][4]~q )) # (\A_SPW_TOP|tx_data|rd_ptr 
// [5] & ((\A_SPW_TOP|tx_data|mem[38][4]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[39][4]~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [0] & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|mem[6][4]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [5] & 
// ((\A_SPW_TOP|tx_data|mem[38][4]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[6][4]~q ),
        .datab(!\A_SPW_TOP|tx_data|mem[7][4]~q ),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [5]),
        .datad(!\A_SPW_TOP|tx_data|mem[38][4]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[39][4]~q ),
        .dataf(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux13~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux13~15 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux13~15 .lut_mask = 64'h505F505F30303F3F;
defparam \A_SPW_TOP|tx_data|Mux13~15 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y9_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux13~16 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux13~16_combout  = ( \A_SPW_TOP|tx_data|mem[14][4]~q  & ( \A_SPW_TOP|tx_data|mem[47][4]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [0] & (((!\A_SPW_TOP|tx_data|rd_ptr [5])) # (\A_SPW_TOP|tx_data|mem[46][4]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr 
// [0] & (((\A_SPW_TOP|tx_data|rd_ptr [5]) # (\A_SPW_TOP|tx_data|mem[15][4]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[14][4]~q  & ( \A_SPW_TOP|tx_data|mem[47][4]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|mem[46][4]~q  & 
// ((\A_SPW_TOP|tx_data|rd_ptr [5])))) # (\A_SPW_TOP|tx_data|rd_ptr [0] & (((\A_SPW_TOP|tx_data|rd_ptr [5]) # (\A_SPW_TOP|tx_data|mem[15][4]~q )))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[14][4]~q  & ( !\A_SPW_TOP|tx_data|mem[47][4]~q  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [0] & (((!\A_SPW_TOP|tx_data|rd_ptr [5])) # (\A_SPW_TOP|tx_data|mem[46][4]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [0] & (((\A_SPW_TOP|tx_data|mem[15][4]~q  & !\A_SPW_TOP|tx_data|rd_ptr [5])))) ) ) ) # ( 
// !\A_SPW_TOP|tx_data|mem[14][4]~q  & ( !\A_SPW_TOP|tx_data|mem[47][4]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|mem[46][4]~q  & ((\A_SPW_TOP|tx_data|rd_ptr [5])))) # (\A_SPW_TOP|tx_data|rd_ptr [0] & (((\A_SPW_TOP|tx_data|mem[15][4]~q  & 
// !\A_SPW_TOP|tx_data|rd_ptr [5])))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .datab(!\A_SPW_TOP|tx_data|mem[46][4]~q ),
        .datac(!\A_SPW_TOP|tx_data|mem[15][4]~q ),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [5]),
        .datae(!\A_SPW_TOP|tx_data|mem[14][4]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[47][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux13~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux13~16 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux13~16 .lut_mask = 64'h0522AF220577AF77;
defparam \A_SPW_TOP|tx_data|Mux13~16 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y9_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux13~19 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux13~19_combout  = ( \A_SPW_TOP|tx_data|Mux13~15_combout  & ( \A_SPW_TOP|tx_data|Mux13~16_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4]) # ((!\A_SPW_TOP|tx_data|rd_ptr [3] & ((\A_SPW_TOP|tx_data|Mux13~17_combout ))) # 
// (\A_SPW_TOP|tx_data|rd_ptr [3] & (\A_SPW_TOP|tx_data|Mux13~18_combout ))) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux13~15_combout  & ( \A_SPW_TOP|tx_data|Mux13~16_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & (((\A_SPW_TOP|tx_data|rd_ptr [3])))) # 
// (\A_SPW_TOP|tx_data|rd_ptr [4] & ((!\A_SPW_TOP|tx_data|rd_ptr [3] & ((\A_SPW_TOP|tx_data|Mux13~17_combout ))) # (\A_SPW_TOP|tx_data|rd_ptr [3] & (\A_SPW_TOP|tx_data|Mux13~18_combout )))) ) ) ) # ( \A_SPW_TOP|tx_data|Mux13~15_combout  & ( 
// !\A_SPW_TOP|tx_data|Mux13~16_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & (((!\A_SPW_TOP|tx_data|rd_ptr [3])))) # (\A_SPW_TOP|tx_data|rd_ptr [4] & ((!\A_SPW_TOP|tx_data|rd_ptr [3] & ((\A_SPW_TOP|tx_data|Mux13~17_combout ))) # (\A_SPW_TOP|tx_data|rd_ptr 
// [3] & (\A_SPW_TOP|tx_data|Mux13~18_combout )))) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux13~15_combout  & ( !\A_SPW_TOP|tx_data|Mux13~16_combout  & ( (\A_SPW_TOP|tx_data|rd_ptr [4] & ((!\A_SPW_TOP|tx_data|rd_ptr [3] & ((\A_SPW_TOP|tx_data|Mux13~17_combout ))) # 
// (\A_SPW_TOP|tx_data|rd_ptr [3] & (\A_SPW_TOP|tx_data|Mux13~18_combout )))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux13~18_combout ),
        .datab(!\A_SPW_TOP|tx_data|Mux13~17_combout ),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .datad(!\A_SPW_TOP|tx_data|rd_ptr [3]),
        .datae(!\A_SPW_TOP|tx_data|Mux13~15_combout ),
        .dataf(!\A_SPW_TOP|tx_data|Mux13~16_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux13~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux13~19 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux13~19 .lut_mask = 64'h0305F30503F5F3F5;
defparam \A_SPW_TOP|tx_data|Mux13~19 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y9_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux13~5 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux13~5_combout  = ( \A_SPW_TOP|tx_data|mem[12][4]~q  & ( \A_SPW_TOP|tx_data|mem[20][4]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & (((\A_SPW_TOP|tx_data|mem[4][4]~q ) # (\A_SPW_TOP|tx_data|rd_ptr [3])))) # (\A_SPW_TOP|tx_data|rd_ptr [4] & 
// (((!\A_SPW_TOP|tx_data|rd_ptr [3])) # (\A_SPW_TOP|tx_data|mem[28][4]~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[12][4]~q  & ( \A_SPW_TOP|tx_data|mem[20][4]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & (((!\A_SPW_TOP|tx_data|rd_ptr [3] & 
// \A_SPW_TOP|tx_data|mem[4][4]~q )))) # (\A_SPW_TOP|tx_data|rd_ptr [4] & (((!\A_SPW_TOP|tx_data|rd_ptr [3])) # (\A_SPW_TOP|tx_data|mem[28][4]~q ))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[12][4]~q  & ( !\A_SPW_TOP|tx_data|mem[20][4]~q  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [4] & (((\A_SPW_TOP|tx_data|mem[4][4]~q ) # (\A_SPW_TOP|tx_data|rd_ptr [3])))) # (\A_SPW_TOP|tx_data|rd_ptr [4] & (\A_SPW_TOP|tx_data|mem[28][4]~q  & (\A_SPW_TOP|tx_data|rd_ptr [3]))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[12][4]~q  
// & ( !\A_SPW_TOP|tx_data|mem[20][4]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & (((!\A_SPW_TOP|tx_data|rd_ptr [3] & \A_SPW_TOP|tx_data|mem[4][4]~q )))) # (\A_SPW_TOP|tx_data|rd_ptr [4] & (\A_SPW_TOP|tx_data|mem[28][4]~q  & (\A_SPW_TOP|tx_data|rd_ptr [3]))) ) 
// ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[28][4]~q ),
        .datab(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [3]),
        .datad(!\A_SPW_TOP|tx_data|mem[4][4]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[12][4]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[20][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux13~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux13~5 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux13~5 .lut_mask = 64'h01C10DCD31F13DFD;
defparam \A_SPW_TOP|tx_data|Mux13~5 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y9_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux13~7 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux13~7_combout  = ( \A_SPW_TOP|tx_data|mem[5][4]~q  & ( \A_SPW_TOP|tx_data|mem[13][4]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4]) # ((!\A_SPW_TOP|tx_data|rd_ptr [3] & (\A_SPW_TOP|tx_data|mem[21][4]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [3] & 
// ((\A_SPW_TOP|tx_data|mem[29][4]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[5][4]~q  & ( \A_SPW_TOP|tx_data|mem[13][4]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [3] & (\A_SPW_TOP|tx_data|mem[21][4]~q  & (\A_SPW_TOP|tx_data|rd_ptr [4]))) # (\A_SPW_TOP|tx_data|rd_ptr 
// [3] & (((!\A_SPW_TOP|tx_data|rd_ptr [4]) # (\A_SPW_TOP|tx_data|mem[29][4]~q )))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[5][4]~q  & ( !\A_SPW_TOP|tx_data|mem[13][4]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [3] & (((!\A_SPW_TOP|tx_data|rd_ptr [4])) # 
// (\A_SPW_TOP|tx_data|mem[21][4]~q ))) # (\A_SPW_TOP|tx_data|rd_ptr [3] & (((\A_SPW_TOP|tx_data|rd_ptr [4] & \A_SPW_TOP|tx_data|mem[29][4]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[5][4]~q  & ( !\A_SPW_TOP|tx_data|mem[13][4]~q  & ( (\A_SPW_TOP|tx_data|rd_ptr 
// [4] & ((!\A_SPW_TOP|tx_data|rd_ptr [3] & (\A_SPW_TOP|tx_data|mem[21][4]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [3] & ((\A_SPW_TOP|tx_data|mem[29][4]~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[21][4]~q ),
        .datab(!\A_SPW_TOP|tx_data|rd_ptr [3]),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .datad(!\A_SPW_TOP|tx_data|mem[29][4]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[5][4]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[13][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux13~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux13~7 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux13~7 .lut_mask = 64'h0407C4C73437F4F7;
defparam \A_SPW_TOP|tx_data|Mux13~7 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y9_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux13~8 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux13~8_combout  = ( \A_SPW_TOP|tx_data|mem[45][4]~q  & ( \A_SPW_TOP|tx_data|rd_ptr [4] & ( (!\A_SPW_TOP|tx_data|rd_ptr [3] & (\A_SPW_TOP|tx_data|mem[53][4]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [3] & ((\A_SPW_TOP|tx_data|mem[61][4]~q ))) ) 
// ) ) # ( !\A_SPW_TOP|tx_data|mem[45][4]~q  & ( \A_SPW_TOP|tx_data|rd_ptr [4] & ( (!\A_SPW_TOP|tx_data|rd_ptr [3] & (\A_SPW_TOP|tx_data|mem[53][4]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [3] & ((\A_SPW_TOP|tx_data|mem[61][4]~q ))) ) ) ) # ( 
// \A_SPW_TOP|tx_data|mem[45][4]~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [4] & ( (\A_SPW_TOP|tx_data|mem[37][4]~q ) # (\A_SPW_TOP|tx_data|rd_ptr [3]) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[45][4]~q  & ( !\A_SPW_TOP|tx_data|rd_ptr [4] & ( (!\A_SPW_TOP|tx_data|rd_ptr [3] 
// & \A_SPW_TOP|tx_data|mem[37][4]~q ) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[53][4]~q ),
        .datab(!\A_SPW_TOP|tx_data|rd_ptr [3]),
        .datac(!\A_SPW_TOP|tx_data|mem[61][4]~q ),
        .datad(!\A_SPW_TOP|tx_data|mem[37][4]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[45][4]~q ),
        .dataf(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux13~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux13~8 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux13~8 .lut_mask = 64'h00CC33FF47474747;
defparam \A_SPW_TOP|tx_data|Mux13~8 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y9_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux13~6 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux13~6_combout  = ( \A_SPW_TOP|tx_data|mem[36][4]~q  & ( \A_SPW_TOP|tx_data|mem[44][4]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4]) # ((!\A_SPW_TOP|tx_data|rd_ptr [3] & (\A_SPW_TOP|tx_data|mem[52][4]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [3] & 
// ((\A_SPW_TOP|tx_data|mem[60][4]~q )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem[36][4]~q  & ( \A_SPW_TOP|tx_data|mem[44][4]~q  & ( (!\A_SPW_TOP|tx_data|rd_ptr [4] & (((\A_SPW_TOP|tx_data|rd_ptr [3])))) # (\A_SPW_TOP|tx_data|rd_ptr [4] & 
// ((!\A_SPW_TOP|tx_data|rd_ptr [3] & (\A_SPW_TOP|tx_data|mem[52][4]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [3] & ((\A_SPW_TOP|tx_data|mem[60][4]~q ))))) ) ) ) # ( \A_SPW_TOP|tx_data|mem[36][4]~q  & ( !\A_SPW_TOP|tx_data|mem[44][4]~q  & ( 
// (!\A_SPW_TOP|tx_data|rd_ptr [4] & (((!\A_SPW_TOP|tx_data|rd_ptr [3])))) # (\A_SPW_TOP|tx_data|rd_ptr [4] & ((!\A_SPW_TOP|tx_data|rd_ptr [3] & (\A_SPW_TOP|tx_data|mem[52][4]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [3] & ((\A_SPW_TOP|tx_data|mem[60][4]~q ))))) ) 
// ) ) # ( !\A_SPW_TOP|tx_data|mem[36][4]~q  & ( !\A_SPW_TOP|tx_data|mem[44][4]~q  & ( (\A_SPW_TOP|tx_data|rd_ptr [4] & ((!\A_SPW_TOP|tx_data|rd_ptr [3] & (\A_SPW_TOP|tx_data|mem[52][4]~q )) # (\A_SPW_TOP|tx_data|rd_ptr [3] & 
// ((\A_SPW_TOP|tx_data|mem[60][4]~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|mem[52][4]~q ),
        .datab(!\A_SPW_TOP|tx_data|rd_ptr [4]),
        .datac(!\A_SPW_TOP|tx_data|rd_ptr [3]),
        .datad(!\A_SPW_TOP|tx_data|mem[60][4]~q ),
        .datae(!\A_SPW_TOP|tx_data|mem[36][4]~q ),
        .dataf(!\A_SPW_TOP|tx_data|mem[44][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux13~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux13~6 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux13~6 .lut_mask = 64'h1013D0D31C1FDCDF;
defparam \A_SPW_TOP|tx_data|Mux13~6 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y9_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux13~9 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux13~9_combout  = ( \A_SPW_TOP|tx_data|rd_ptr [0] & ( \A_SPW_TOP|tx_data|Mux13~6_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|Mux13~7_combout )) # (\A_SPW_TOP|tx_data|rd_ptr [5] & 
// ((\A_SPW_TOP|tx_data|Mux13~8_combout ))) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [0] & ( \A_SPW_TOP|tx_data|Mux13~6_combout  & ( (\A_SPW_TOP|tx_data|rd_ptr [5]) # (\A_SPW_TOP|tx_data|Mux13~5_combout ) ) ) ) # ( \A_SPW_TOP|tx_data|rd_ptr [0] & ( 
// !\A_SPW_TOP|tx_data|Mux13~6_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [5] & (\A_SPW_TOP|tx_data|Mux13~7_combout )) # (\A_SPW_TOP|tx_data|rd_ptr [5] & ((\A_SPW_TOP|tx_data|Mux13~8_combout ))) ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [0] & ( 
// !\A_SPW_TOP|tx_data|Mux13~6_combout  & ( (\A_SPW_TOP|tx_data|Mux13~5_combout  & !\A_SPW_TOP|tx_data|rd_ptr [5]) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|Mux13~5_combout ),
        .datab(!\A_SPW_TOP|tx_data|rd_ptr [5]),
        .datac(!\A_SPW_TOP|tx_data|Mux13~7_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux13~8_combout ),
        .datae(!\A_SPW_TOP|tx_data|rd_ptr [0]),
        .dataf(!\A_SPW_TOP|tx_data|Mux13~6_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux13~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux13~9 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux13~9 .lut_mask = 64'h44440C3F77770C3F;
defparam \A_SPW_TOP|tx_data|Mux13~9 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y9_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Mux13~20 (
// Equation(s):
// \A_SPW_TOP|tx_data|Mux13~20_combout  = ( \A_SPW_TOP|tx_data|Mux13~19_combout  & ( \A_SPW_TOP|tx_data|Mux13~9_combout  & ( ((!\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|Mux13~4_combout )) # (\A_SPW_TOP|tx_data|rd_ptr [1] & 
// ((\A_SPW_TOP|tx_data|Mux13~14_combout )))) # (\A_SPW_TOP|tx_data|rd_ptr [2]) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux13~19_combout  & ( \A_SPW_TOP|tx_data|Mux13~9_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & ((!\A_SPW_TOP|tx_data|rd_ptr [1] & 
// (\A_SPW_TOP|tx_data|Mux13~4_combout )) # (\A_SPW_TOP|tx_data|rd_ptr [1] & ((\A_SPW_TOP|tx_data|Mux13~14_combout ))))) # (\A_SPW_TOP|tx_data|rd_ptr [2] & (!\A_SPW_TOP|tx_data|rd_ptr [1])) ) ) ) # ( \A_SPW_TOP|tx_data|Mux13~19_combout  & ( 
// !\A_SPW_TOP|tx_data|Mux13~9_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & ((!\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|Mux13~4_combout )) # (\A_SPW_TOP|tx_data|rd_ptr [1] & ((\A_SPW_TOP|tx_data|Mux13~14_combout ))))) # 
// (\A_SPW_TOP|tx_data|rd_ptr [2] & (\A_SPW_TOP|tx_data|rd_ptr [1])) ) ) ) # ( !\A_SPW_TOP|tx_data|Mux13~19_combout  & ( !\A_SPW_TOP|tx_data|Mux13~9_combout  & ( (!\A_SPW_TOP|tx_data|rd_ptr [2] & ((!\A_SPW_TOP|tx_data|rd_ptr [1] & 
// (\A_SPW_TOP|tx_data|Mux13~4_combout )) # (\A_SPW_TOP|tx_data|rd_ptr [1] & ((\A_SPW_TOP|tx_data|Mux13~14_combout ))))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|rd_ptr [2]),
        .datab(!\A_SPW_TOP|tx_data|rd_ptr [1]),
        .datac(!\A_SPW_TOP|tx_data|Mux13~4_combout ),
        .datad(!\A_SPW_TOP|tx_data|Mux13~14_combout ),
        .datae(!\A_SPW_TOP|tx_data|Mux13~19_combout ),
        .dataf(!\A_SPW_TOP|tx_data|Mux13~9_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Mux13~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Mux13~20 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Mux13~20 .lut_mask = 64'h082A193B4C6E5D7F;
defparam \A_SPW_TOP|tx_data|Mux13~20 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y9_N50
dffeas \A_SPW_TOP|tx_data|data_out[4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|tx_data|Mux13~20_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|data_out [4]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|data_out[4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|data_out[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X53_Y7_N9
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector36~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector36~0_combout  = ( \A_SPW_TOP|SPW|TX|Selector32~0_combout  & ( ((!\A_SPW_TOP|SPW|TX|Selector40~0_combout  & \A_SPW_TOP|SPW|TX|tx_data_in_0 [4])) # (\A_SPW_TOP|tx_data|data_out [4]) ) ) # ( !\A_SPW_TOP|SPW|TX|Selector32~0_combout  
// & ( (!\A_SPW_TOP|SPW|TX|Selector40~0_combout  & \A_SPW_TOP|SPW|TX|tx_data_in_0 [4]) ) )

        .dataa(!\A_SPW_TOP|tx_data|data_out [4]),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|TX|Selector40~0_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|tx_data_in_0 [4]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|Selector32~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector36~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector36~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector36~0 .lut_mask = 64'h00F000F055F555F5;
defparam \A_SPW_TOP|SPW|TX|Selector36~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X53_Y7_N38
dffeas \A_SPW_TOP|SPW|TX|tx_data_in_0[4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|Selector36~0_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|tx_data_in_0 [4]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_data_in_0[4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|tx_data_in_0[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X51_Y7_N42
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout~14 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout~14_combout  = ( \A_SPW_TOP|SPW|TX|tx_data_in_0 [4] & ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & (!\A_SPW_TOP|SPW|TX|tx_data_in_0 [8] & 
// (\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & \A_SPW_TOP|SPW|TX|global_counter_transfer [2]))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
        .datab(!\A_SPW_TOP|SPW|TX|tx_data_in_0 [8]),
        .datac(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
        .datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
        .datae(!\A_SPW_TOP|SPW|TX|tx_data_in_0 [4]),
        .dataf(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|tx_dout~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout~14 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout~14 .lut_mask = 64'h0000000800000000;
defparam \A_SPW_TOP|SPW|TX|tx_dout~14 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X51_Y7_N36
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout~20 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout~20_combout  = ( \A_SPW_TOP|SPW|TX|tx_dout~17_combout  & ( !\A_SPW_TOP|SPW|TX|tx_dout~14_combout  & ( (!\A_SPW_TOP|SPW|TX|tx_dout~19_combout  & \A_SPW_TOP|SPW|TX|tx_dout~18_combout ) ) ) ) # ( !\A_SPW_TOP|SPW|TX|tx_dout~17_combout 
//  & ( !\A_SPW_TOP|SPW|TX|tx_dout~14_combout  & ( (!\A_SPW_TOP|SPW|TX|tx_dout~19_combout  & (((\A_SPW_TOP|SPW|TX|tx_dout~18_combout ) # (\A_SPW_TOP|SPW|TX|tx_dout~15_combout )) # (\A_SPW_TOP|SPW|TX|tx_dout~16_combout ))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|tx_dout~16_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|tx_dout~19_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|tx_dout~15_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|tx_dout~18_combout ),
        .datae(!\A_SPW_TOP|SPW|TX|tx_dout~17_combout ),
        .dataf(!\A_SPW_TOP|SPW|TX|tx_dout~14_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|tx_dout~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout~20 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout~20 .lut_mask = 64'h4CCC00CC00000000;
defparam \A_SPW_TOP|SPW|TX|tx_dout~20 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X58_Y7_N42
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout~6 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout~6_combout  = ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & (!\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & 
// ((\A_SPW_TOP|SPW|TX|last_type.EOP~q ) # (\A_SPW_TOP|SPW|TX|last_type.EEP~q )))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
        .datab(!\A_SPW_TOP|SPW|TX|last_type.EEP~q ),
        .datac(!\A_SPW_TOP|SPW|TX|last_type.EOP~q ),
        .datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
        .datae(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
        .dataf(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|tx_dout~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout~6 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout~6 .lut_mask = 64'h2A00000000000000;
defparam \A_SPW_TOP|SPW|TX|tx_dout~6 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X54_Y7_N18
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector74~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector74~0_combout  = ( \A_SPW_TOP|SPW|TX|tx_data_in_0 [8] & ( (!\A_SPW_TOP|SPW|TX|tx_data_in [8] & (!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q  & (\A_SPW_TOP|SPW|TX|Equal0~4_combout  & \A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q ))) 
// ) ) # ( !\A_SPW_TOP|SPW|TX|tx_data_in_0 [8] & ( (\A_SPW_TOP|SPW|TX|Equal0~4_combout  & (((!\A_SPW_TOP|SPW|TX|tx_data_in [8] & \A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q )) # (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q ))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|tx_data_in [8]),
        .datab(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q ),
        .datac(!\A_SPW_TOP|SPW|TX|Equal0~4_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|tx_data_in_0 [8]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector74~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector74~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector74~0 .lut_mask = 64'h030B030B00080008;
defparam \A_SPW_TOP|SPW|TX|Selector74~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X53_Y7_N54
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector25~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector25~0_combout  = ( \A_SPW_TOP|SPW|TX|tx_data_in [6] & ( (!\A_SPW_TOP|SPW|TX|Selector30~0_combout ) # ((!\A_SPW_TOP|SPW|TX|Selector30~2_combout  & ((\A_SPW_TOP|tx_data|data_out [6]) # (\A_SPW_TOP|SPW|TX|Equal0~6_combout )))) ) ) # 
// ( !\A_SPW_TOP|SPW|TX|tx_data_in [6] & ( (!\A_SPW_TOP|SPW|TX|Equal0~6_combout  & (\A_SPW_TOP|tx_data|data_out [6] & !\A_SPW_TOP|SPW|TX|Selector30~2_combout )) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|Selector30~0_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|Equal0~6_combout ),
        .datac(!\A_SPW_TOP|tx_data|data_out [6]),
        .datad(!\A_SPW_TOP|SPW|TX|Selector30~2_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|tx_data_in [6]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector25~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector25~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector25~0 .lut_mask = 64'h0C000C00BFAABFAA;
defparam \A_SPW_TOP|SPW|TX|Selector25~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X53_Y7_N41
dffeas \A_SPW_TOP|SPW|TX|tx_data_in[6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|Selector25~0_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|tx_data_in [6]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_data_in[6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|tx_data_in[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X53_Y7_N39
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector75~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector75~0_combout  = ( \A_SPW_TOP|SPW|TX|tx_data_in_0 [6] & ( (!\A_SPW_TOP|SPW|TX|Selector74~0_combout  & (((\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [6])))) # (\A_SPW_TOP|SPW|TX|Selector74~0_combout  & 
// (((\A_SPW_TOP|SPW|TX|tx_data_in [6])) # (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q ))) ) ) # ( !\A_SPW_TOP|SPW|TX|tx_data_in_0 [6] & ( (!\A_SPW_TOP|SPW|TX|Selector74~0_combout  & (((\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [6])))) # 
// (\A_SPW_TOP|SPW|TX|Selector74~0_combout  & (!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q  & ((\A_SPW_TOP|SPW|TX|tx_data_in [6])))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q ),
        .datab(!\A_SPW_TOP|SPW|TX|Selector74~0_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [6]),
        .datad(!\A_SPW_TOP|SPW|TX|tx_data_in [6]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|tx_data_in_0 [6]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector75~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector75~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector75~0 .lut_mask = 64'h0C2E0C2E1D3F1D3F;
defparam \A_SPW_TOP|SPW|TX|Selector75~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X53_Y7_N14
dffeas \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|Selector75~0_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [6]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X53_Y7_N57
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector26~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector26~0_combout  = ( \A_SPW_TOP|SPW|TX|Selector30~2_combout  & ( (!\A_SPW_TOP|SPW|TX|Selector30~0_combout  & \A_SPW_TOP|SPW|TX|tx_data_in [5]) ) ) # ( !\A_SPW_TOP|SPW|TX|Selector30~2_combout  & ( (!\A_SPW_TOP|SPW|TX|Equal0~6_combout 
//  & (((!\A_SPW_TOP|SPW|TX|Selector30~0_combout  & \A_SPW_TOP|SPW|TX|tx_data_in [5])) # (\A_SPW_TOP|tx_data|data_out [5]))) # (\A_SPW_TOP|SPW|TX|Equal0~6_combout  & (((\A_SPW_TOP|SPW|TX|tx_data_in [5])))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|Selector30~0_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|Equal0~6_combout ),
        .datac(!\A_SPW_TOP|tx_data|data_out [5]),
        .datad(!\A_SPW_TOP|SPW|TX|tx_data_in [5]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|Selector30~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector26~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector26~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector26~0 .lut_mask = 64'h0CBF0CBF00AA00AA;
defparam \A_SPW_TOP|SPW|TX|Selector26~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X53_Y7_N5
dffeas \A_SPW_TOP|SPW|TX|tx_data_in[5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|Selector26~0_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|tx_data_in [5]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_data_in[5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|tx_data_in[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X53_Y7_N3
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector76~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector76~0_combout  = ( \A_SPW_TOP|SPW|TX|tx_data_in_0 [5] & ( (!\A_SPW_TOP|SPW|TX|Selector74~0_combout  & (((\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [5])))) # (\A_SPW_TOP|SPW|TX|Selector74~0_combout  & 
// (((\A_SPW_TOP|SPW|TX|tx_data_in [5])) # (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q ))) ) ) # ( !\A_SPW_TOP|SPW|TX|tx_data_in_0 [5] & ( (!\A_SPW_TOP|SPW|TX|Selector74~0_combout  & (((\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [5])))) # 
// (\A_SPW_TOP|SPW|TX|Selector74~0_combout  & (!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q  & ((\A_SPW_TOP|SPW|TX|tx_data_in [5])))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q ),
        .datab(!\A_SPW_TOP|SPW|TX|Selector74~0_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [5]),
        .datad(!\A_SPW_TOP|SPW|TX|tx_data_in [5]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|tx_data_in_0 [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector76~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector76~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector76~0 .lut_mask = 64'h0C2E0C2E1D3F1D3F;
defparam \A_SPW_TOP|SPW|TX|Selector76~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X53_Y7_N53
dffeas \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|Selector76~0_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [5]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X53_Y7_N24
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector27~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector27~0_combout  = ( \A_SPW_TOP|SPW|TX|Selector30~2_combout  & ( (!\A_SPW_TOP|SPW|TX|Selector30~0_combout  & \A_SPW_TOP|SPW|TX|tx_data_in [4]) ) ) # ( !\A_SPW_TOP|SPW|TX|Selector30~2_combout  & ( (!\A_SPW_TOP|SPW|TX|Equal0~6_combout 
//  & (((!\A_SPW_TOP|SPW|TX|Selector30~0_combout  & \A_SPW_TOP|SPW|TX|tx_data_in [4])) # (\A_SPW_TOP|tx_data|data_out [4]))) # (\A_SPW_TOP|SPW|TX|Equal0~6_combout  & (((\A_SPW_TOP|SPW|TX|tx_data_in [4])))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|Selector30~0_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|Equal0~6_combout ),
        .datac(!\A_SPW_TOP|tx_data|data_out [4]),
        .datad(!\A_SPW_TOP|SPW|TX|tx_data_in [4]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|Selector30~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector27~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector27~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector27~0 .lut_mask = 64'h0CBF0CBF00AA00AA;
defparam \A_SPW_TOP|SPW|TX|Selector27~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X54_Y7_N23
dffeas \A_SPW_TOP|SPW|TX|tx_data_in[4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|Selector27~0_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|tx_data_in [4]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_data_in[4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|tx_data_in[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X53_Y7_N36
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector77~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector77~0_combout  = ( \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [4] & ( (!\A_SPW_TOP|SPW|TX|Selector74~0_combout ) # ((!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q  & (\A_SPW_TOP|SPW|TX|tx_data_in [4])) # 
// (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q  & ((\A_SPW_TOP|SPW|TX|tx_data_in_0 [4])))) ) ) # ( !\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [4] & ( (\A_SPW_TOP|SPW|TX|Selector74~0_combout  & ((!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q  & 
// (\A_SPW_TOP|SPW|TX|tx_data_in [4])) # (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q  & ((\A_SPW_TOP|SPW|TX|tx_data_in_0 [4]))))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q ),
        .datab(!\A_SPW_TOP|SPW|TX|Selector74~0_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|tx_data_in [4]),
        .datad(!\A_SPW_TOP|SPW|TX|tx_data_in_0 [4]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector77~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector77~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector77~0 .lut_mask = 64'h02130213CEDFCEDF;
defparam \A_SPW_TOP|SPW|TX|Selector77~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X53_Y7_N8
dffeas \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|Selector77~0_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [4]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X53_Y7_N27
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector24~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector24~0_combout  = ( \A_SPW_TOP|SPW|TX|Selector30~2_combout  & ( (!\A_SPW_TOP|SPW|TX|Selector30~0_combout  & \A_SPW_TOP|SPW|TX|tx_data_in [7]) ) ) # ( !\A_SPW_TOP|SPW|TX|Selector30~2_combout  & ( (!\A_SPW_TOP|SPW|TX|Equal0~6_combout 
//  & (((!\A_SPW_TOP|SPW|TX|Selector30~0_combout  & \A_SPW_TOP|SPW|TX|tx_data_in [7])) # (\A_SPW_TOP|tx_data|data_out [7]))) # (\A_SPW_TOP|SPW|TX|Equal0~6_combout  & (((\A_SPW_TOP|SPW|TX|tx_data_in [7])))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|Selector30~0_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|Equal0~6_combout ),
        .datac(!\A_SPW_TOP|tx_data|data_out [7]),
        .datad(!\A_SPW_TOP|SPW|TX|tx_data_in [7]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|Selector30~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector24~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector24~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector24~0 .lut_mask = 64'h0CBF0CBF00AA00AA;
defparam \A_SPW_TOP|SPW|TX|Selector24~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X53_Y7_N32
dffeas \A_SPW_TOP|SPW|TX|tx_data_in[7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|Selector24~0_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|tx_data_in [7]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_data_in[7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|tx_data_in[7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X53_Y7_N0
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector74~1 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector74~1_combout  = ( \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [7] & ( (!\A_SPW_TOP|SPW|TX|Selector74~0_combout ) # ((!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q  & ((\A_SPW_TOP|SPW|TX|tx_data_in [7]))) # 
// (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q  & (\A_SPW_TOP|SPW|TX|tx_data_in_0 [7]))) ) ) # ( !\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [7] & ( (\A_SPW_TOP|SPW|TX|Selector74~0_combout  & ((!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q  & 
// ((\A_SPW_TOP|SPW|TX|tx_data_in [7]))) # (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q  & (\A_SPW_TOP|SPW|TX|tx_data_in_0 [7])))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q ),
        .datab(!\A_SPW_TOP|SPW|TX|Selector74~0_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|tx_data_in_0 [7]),
        .datad(!\A_SPW_TOP|SPW|TX|tx_data_in [7]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [7]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector74~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector74~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector74~1 .lut_mask = 64'h01230123CDEFCDEF;
defparam \A_SPW_TOP|SPW|TX|Selector74~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X53_Y7_N20
dffeas \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|Selector74~1_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [7]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X53_Y7_N6
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout~4 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout~4_combout  = ( \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [7] & ( !\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [6] $ (!\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [5] $ (!\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [4])) ) ) # ( 
// !\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [7] & ( !\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [6] $ (!\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [5] $ (\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [4])) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [6]),
        .datac(!\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [5]),
        .datad(!\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [4]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [7]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|tx_dout~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout~4 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout~4 .lut_mask = 64'h3CC33CC3C33CC33C;
defparam \A_SPW_TOP|SPW|TX|tx_dout~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X51_Y7_N27
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector28~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector28~0_combout  = ( \A_SPW_TOP|SPW|TX|Selector30~2_combout  & ( (!\A_SPW_TOP|SPW|TX|Selector30~0_combout  & \A_SPW_TOP|SPW|TX|tx_data_in [3]) ) ) # ( !\A_SPW_TOP|SPW|TX|Selector30~2_combout  & ( (!\A_SPW_TOP|SPW|TX|Equal0~6_combout 
//  & (((!\A_SPW_TOP|SPW|TX|Selector30~0_combout  & \A_SPW_TOP|SPW|TX|tx_data_in [3])) # (\A_SPW_TOP|tx_data|data_out [3]))) # (\A_SPW_TOP|SPW|TX|Equal0~6_combout  & (((\A_SPW_TOP|SPW|TX|tx_data_in [3])))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|Selector30~0_combout ),
        .datab(!\A_SPW_TOP|tx_data|data_out [3]),
        .datac(!\A_SPW_TOP|SPW|TX|Equal0~6_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|tx_data_in [3]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|Selector30~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector28~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector28~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector28~0 .lut_mask = 64'h30BF30BF00AA00AA;
defparam \A_SPW_TOP|SPW|TX|Selector28~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X54_Y7_N41
dffeas \A_SPW_TOP|SPW|TX|tx_data_in[3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|Selector28~0_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|tx_data_in [3]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_data_in[3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|tx_data_in[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X54_Y7_N39
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector78~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector78~0_combout  = ( \A_SPW_TOP|SPW|TX|tx_data_in_0 [3] & ( (!\A_SPW_TOP|SPW|TX|Selector74~0_combout  & (((\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [3])))) # (\A_SPW_TOP|SPW|TX|Selector74~0_combout  & 
// (((\A_SPW_TOP|SPW|TX|tx_data_in [3])) # (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q ))) ) ) # ( !\A_SPW_TOP|SPW|TX|tx_data_in_0 [3] & ( (!\A_SPW_TOP|SPW|TX|Selector74~0_combout  & (((\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [3])))) # 
// (\A_SPW_TOP|SPW|TX|Selector74~0_combout  & (!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q  & ((\A_SPW_TOP|SPW|TX|tx_data_in [3])))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|Selector74~0_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q ),
        .datac(!\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [3]),
        .datad(!\A_SPW_TOP|SPW|TX|tx_data_in [3]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|tx_data_in_0 [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector78~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector78~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector78~0 .lut_mask = 64'h0A4E0A4E1B5F1B5F;
defparam \A_SPW_TOP|SPW|TX|Selector78~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X54_Y7_N32
dffeas \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|Selector78~0_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [3]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X54_Y7_N54
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector29~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector29~0_combout  = ( \A_SPW_TOP|SPW|TX|Selector30~0_combout  & ( (!\A_SPW_TOP|SPW|TX|Selector30~2_combout  & ((!\A_SPW_TOP|SPW|TX|Equal0~6_combout  & (\A_SPW_TOP|tx_data|data_out [2])) # (\A_SPW_TOP|SPW|TX|Equal0~6_combout  & 
// ((\A_SPW_TOP|SPW|TX|tx_data_in [2]))))) ) ) # ( !\A_SPW_TOP|SPW|TX|Selector30~0_combout  & ( ((!\A_SPW_TOP|SPW|TX|Equal0~6_combout  & (\A_SPW_TOP|tx_data|data_out [2] & !\A_SPW_TOP|SPW|TX|Selector30~2_combout ))) # (\A_SPW_TOP|SPW|TX|tx_data_in [2]) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|Equal0~6_combout ),
        .datab(!\A_SPW_TOP|tx_data|data_out [2]),
        .datac(!\A_SPW_TOP|SPW|TX|Selector30~2_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|tx_data_in [2]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|Selector30~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector29~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector29~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector29~0 .lut_mask = 64'h20FF20FF20702070;
defparam \A_SPW_TOP|SPW|TX|Selector29~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X54_Y7_N47
dffeas \A_SPW_TOP|SPW|TX|tx_data_in[2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|Selector29~0_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|tx_data_in [2]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_data_in[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|tx_data_in[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X54_Y7_N45
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector79~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector79~0_combout  = ( \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [2] & ( (!\A_SPW_TOP|SPW|TX|Selector74~0_combout ) # ((!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q  & ((\A_SPW_TOP|SPW|TX|tx_data_in [2]))) # 
// (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q  & (\A_SPW_TOP|SPW|TX|tx_data_in_0 [2]))) ) ) # ( !\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [2] & ( (\A_SPW_TOP|SPW|TX|Selector74~0_combout  & ((!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q  & 
// ((\A_SPW_TOP|SPW|TX|tx_data_in [2]))) # (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q  & (\A_SPW_TOP|SPW|TX|tx_data_in_0 [2])))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|Selector74~0_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q ),
        .datac(!\A_SPW_TOP|SPW|TX|tx_data_in_0 [2]),
        .datad(!\A_SPW_TOP|SPW|TX|tx_data_in [2]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector79~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector79~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector79~0 .lut_mask = 64'h01450145ABEFABEF;
defparam \A_SPW_TOP|SPW|TX|Selector79~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X54_Y7_N26
dffeas \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|Selector79~0_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [2]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X54_Y7_N36
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector81~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector81~0_combout  = ( \A_SPW_TOP|SPW|TX|tx_data_in_0 [0] & ( (!\A_SPW_TOP|SPW|TX|Selector74~0_combout  & (((\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [0])))) # (\A_SPW_TOP|SPW|TX|Selector74~0_combout  & 
// (((\A_SPW_TOP|SPW|TX|tx_data_in [0])) # (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q ))) ) ) # ( !\A_SPW_TOP|SPW|TX|tx_data_in_0 [0] & ( (!\A_SPW_TOP|SPW|TX|Selector74~0_combout  & (((\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [0])))) # 
// (\A_SPW_TOP|SPW|TX|Selector74~0_combout  & (!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q  & (\A_SPW_TOP|SPW|TX|tx_data_in [0]))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|Selector74~0_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q ),
        .datac(!\A_SPW_TOP|SPW|TX|tx_data_in [0]),
        .datad(!\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [0]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|tx_data_in_0 [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector81~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector81~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector81~0 .lut_mask = 64'h04AE04AE15BF15BF;
defparam \A_SPW_TOP|SPW|TX|Selector81~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X54_Y7_N49
dffeas \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|Selector81~0_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [0]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X54_Y7_N42
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector80~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector80~0_combout  = ( \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [1] & ( (!\A_SPW_TOP|SPW|TX|Selector74~0_combout ) # ((!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q  & ((\A_SPW_TOP|SPW|TX|tx_data_in [1]))) # 
// (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q  & (\A_SPW_TOP|SPW|TX|tx_data_in_0 [1]))) ) ) # ( !\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [1] & ( (\A_SPW_TOP|SPW|TX|Selector74~0_combout  & ((!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q  & 
// ((\A_SPW_TOP|SPW|TX|tx_data_in [1]))) # (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q  & (\A_SPW_TOP|SPW|TX|tx_data_in_0 [1])))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|Selector74~0_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q ),
        .datac(!\A_SPW_TOP|SPW|TX|tx_data_in_0 [1]),
        .datad(!\A_SPW_TOP|SPW|TX|tx_data_in [1]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector80~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector80~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector80~0 .lut_mask = 64'h01450145ABEFABEF;
defparam \A_SPW_TOP|SPW|TX|Selector80~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X54_Y7_N14
dffeas \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|Selector80~0_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [1]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X54_Y7_N48
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout~5 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout~5_combout  = ( \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [1] & ( !\A_SPW_TOP|SPW|TX|tx_dout~4_combout  $ (!\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [3] $ (!\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [2] $ 
// (\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [0]))) ) ) # ( !\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [1] & ( !\A_SPW_TOP|SPW|TX|tx_dout~4_combout  $ (!\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [3] $ (!\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [2] $ 
// (!\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [0]))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|tx_dout~4_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [3]),
        .datac(!\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [2]),
        .datad(!\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [0]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|tx_dout~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout~5 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout~5 .lut_mask = 64'h6996699696699669;
defparam \A_SPW_TOP|SPW|TX|tx_dout~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X56_Y6_N39
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector50~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector50~0_combout  = (!\A_SPW_TOP|SPW|TX|Equal0~6_combout  & (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_c~q  & !\A_SPW_TOP|SPW|TX|Equal0~1_combout ))

        .dataa(!\A_SPW_TOP|SPW|TX|Equal0~6_combout ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_c~q ),
        .datad(!\A_SPW_TOP|SPW|TX|Equal0~1_combout ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector50~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector50~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector50~0 .lut_mask = 64'h0A000A000A000A00;
defparam \A_SPW_TOP|SPW|TX|Selector50~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y18_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_payload~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_payload~1_combout  = ( \u0|hps_0|fpga_interfaces|h2f_WDATA [1] & ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_WDATA [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_014|src_payload~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_payload~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_payload~1 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_payload~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y18_N20
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_014|src_payload~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y22_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout  & ( 
// ((\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [2])) # (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout  & 
// ( (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [2]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [2]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 .lut_mask = 64'h0303030303FF03FF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y22_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_data[81] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_data [81] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout  & ( (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~0_combout ) ) ) 
// # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout  & ( ((\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~0_combout )) # (\u0|mm_interconnect_0|cmd_mux_014|saved_grant 
// [1]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_014|src_data [81]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[81] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[81] .lut_mask = 64'h3F333F330F000F00;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[81] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y22_N41
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_014|src_data [81]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .power_up = "low";
// synopsys translate_on

// Location: FF_X25_Y20_N35
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y20_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_data[86] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_data [86] = ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [0] & ( ((\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [0])) # (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0] & ( (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_014|src_data [86]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[86] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[86] .lut_mask = 64'h005500550F5F0F5F;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[86] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y20_N20
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_014|src_data [86]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X25_Y20_N2
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_014|src_data [87]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X25_Y20_N11
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_014|src_data [88]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y20_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_014|src_data [88] & ( 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_014|src_data [88] & ( 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]))) # (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((\u0|mm_interconnect_0|cmd_mux_014|src_data [87])))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_014|src_data [87]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_014|src_data [88]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .lut_mask = 64'h404F404F40404040;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y20_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  & 
// ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) # 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|cmd_mux_014|src_data [86]))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_014|src_data [86]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .lut_mask = 64'h00000000ACACACAC;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y20_N59
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y20_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  = ( \u0|mm_interconnect_0|cmd_mux_014|src_data [88] & ( 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_014|src_data [88] & ( 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]))) # (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((!\u0|mm_interconnect_0|cmd_mux_014|src_data [87])))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_014|src_data [87]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_014|src_data [88]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .lut_mask = 64'h8F808F8080808080;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y20_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  & 
// ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) # 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((\u0|mm_interconnect_0|cmd_mux_014|src_data [86]))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_014|src_data [86]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .lut_mask = 64'h0000000047474747;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y20_N16
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y20_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout  ) ) # ( !\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout  & ( 
// (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [1]) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout  & 
// ( (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [1]) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout 
//  & ( (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [1]) ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [1]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .lut_mask = 64'h050505050505FFFF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y20_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  = ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) # (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ((!\u0|mm_interconnect_0|cmd_mux_014|src_data [86]))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_014|src_data [86]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .lut_mask = 64'h00000000AAF0AAF0;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y20_N46
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y20_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout  = SUM(( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] 
// ) + ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14  = CARRY(( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) + ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
        .cout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .lut_mask = 64'h0000CCCC00000F0F;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y20_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_data[79] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_data [79] = (!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~2_combout ))) # 
// (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout ) # ((\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~2_combout 
// ))))

        .dataa(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~2_combout ),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_014|src_data [79]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[79] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[79] .lut_mask = 64'h7530753075307530;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[79] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y20_N26
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_014|src_data [79]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y20_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0] = ( \u0|mm_interconnect_0|cmd_mux_014|src_data [79] & ( 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout  & 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0] & !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) 
// # ( !\u0|mm_interconnect_0|cmd_mux_014|src_data [79] & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout  & 
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]) # (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) 
// )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_014|src_data [79]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .lut_mask = 64'h3033303330003000;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y20_N44
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y20_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout  & ( 
// ((\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [0])) # (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout  & 
// ( (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [0]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .lut_mask = 64'h0303030357575757;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y20_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout  = ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  & ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  & ( 
// (((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout  & \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0])) # 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0])) # (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) 
// ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  & ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout  & 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0])) # (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]))) 
// ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  & ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout  & 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0])) # (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]))) 
// ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  & ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout  & 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0])) # (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]))) 
// ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
        .datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 .lut_mask = 64'h04CC04CC04CC37FF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y20_N31
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y20_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout  = SUM(( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) 
// + ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14  ))
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10  = CARRY(( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
        .cout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y20_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_data[80] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_data [80] = (!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~1_combout )))) # 
// (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~0_combout ) # ((\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~1_combout 
// ))))

        .dataa(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~0_combout ),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~1_combout ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_014|src_data [80]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[80] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[80] .lut_mask = 64'h5073507350735073;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[80] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y20_N23
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_014|src_data [80]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y20_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1] = ( \u0|mm_interconnect_0|cmd_mux_014|src_data [80] & ( 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1] & 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_014|src_data [80] & ( 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout  & 
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]) # (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) 
// )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_014|src_data [80]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .lut_mask = 64'h00F300F300C000C0;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y20_N14
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y20_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout  = ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  & 
// ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]) # 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout )))) # (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout )) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  & 
// ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]))) 
// # (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout )) ) ) ) # ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1] & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  & 
// ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]) # 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg 
// [1] & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
        .datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .lut_mask = 64'h00AA0AAA11BB1BBB;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y20_N37
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y20_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout  = SUM(( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg 
// [2] ) + ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10  
// ))
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6  = CARRY(( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + 
// ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
        .cout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y22_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2] = ( \u0|mm_interconnect_0|cmd_mux_014|src_data [81] & ( 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] & 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_014|src_data [81] & ( 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout  & ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg 
// [2]) # (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_014|src_data [81]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .lut_mask = 64'h00F500F500A000A0;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y22_N58
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y22_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] 
// & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout 
// ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] & 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout )))) # (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 .lut_mask = 64'h05350535F5F5F5F5;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y22_N53
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y22_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_data[82] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_data [82] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout  & ( (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ) ) ) 
// # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout  & ( ((\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout )) # (\u0|mm_interconnect_0|cmd_mux_014|saved_grant 
// [0]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_014|src_data [82]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[82] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[82] .lut_mask = 64'h03FF03FF03030303;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[82] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y22_N32
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_014|src_data [82]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .power_up = "low";
// synopsys translate_on

// Location: FF_X23_Y20_N19
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y20_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  & 
// ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) # 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((\u0|mm_interconnect_0|cmd_mux_014|src_data [86]))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_014|src_data [86]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .lut_mask = 64'h0000000053535353;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y20_N56
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y20_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout  = SUM(( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg 
// [3] ) + ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3] ) + ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6  
// ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y22_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout  & ( 
// ((\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [3])) # (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout  & 
// ( (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [3]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [3]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .lut_mask = 64'h0303030303FF03FF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y22_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3] = ( \u0|mm_interconnect_0|cmd_mux_014|src_data [82] & ( 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3] & 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_014|src_data [82] & ( 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout  & ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg 
// [3]) # (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_014|src_data [82]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .lut_mask = 64'h0D0D0D0D08080808;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y22_N28
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y22_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3] 
// & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout 
// ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3] & ( 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3] & 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ))) # (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .lut_mask = 64'h02570257AAFFAAFF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y20_N32
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y19_N45
cyclonev_lcell_comb \u0|timecode_tx_data|always0~0 (
// Equation(s):
// \u0|timecode_tx_data|always0~0_combout  = ( !\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [0] & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [1] & 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_write~combout  & 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [1]),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_write~combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|timecode_tx_data|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|timecode_tx_data|always0~0 .extended_lut = "off";
defparam \u0|timecode_tx_data|always0~0 .lut_mask = 64'h0800080000000000;
defparam \u0|timecode_tx_data|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y18_N8
dffeas \u0|timecode_tx_data|data_out[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|timecode_tx_data|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|timecode_tx_data|data_out [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|timecode_tx_data|data_out[1] .is_wysiwyg = "true";
defparam \u0|timecode_tx_data|data_out[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X55_Y6_N9
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector49~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector49~0_combout  = ( \A_SPW_TOP|SPW|TX|tx_tcode_in [1] & ( \u0|timecode_tx_data|data_out [1] & ( ((!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~5_combout ) # (!\A_SPW_TOP|SPW|TX|Selector50~1_combout )) # 
// (\A_SPW_TOP|SPW|TX|Selector50~0_combout ) ) ) ) # ( !\A_SPW_TOP|SPW|TX|tx_tcode_in [1] & ( \u0|timecode_tx_data|data_out [1] & ( ((!\A_SPW_TOP|SPW|TX|tx_tcode_in~0_combout  & !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~5_combout )) # 
// (\A_SPW_TOP|SPW|TX|Selector50~0_combout ) ) ) ) # ( \A_SPW_TOP|SPW|TX|tx_tcode_in [1] & ( !\u0|timecode_tx_data|data_out [1] & ( (!\A_SPW_TOP|SPW|TX|Selector50~1_combout ) # ((\A_SPW_TOP|SPW|TX|tx_tcode_in~0_combout  & 
// !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~5_combout )) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|tx_tcode_in~0_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|Selector50~0_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~5_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|Selector50~1_combout ),
        .datae(!\A_SPW_TOP|SPW|TX|tx_tcode_in [1]),
        .dataf(!\u0|timecode_tx_data|data_out [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector49~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector49~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector49~0 .lut_mask = 64'h0000FF50B3B3FFF3;
defparam \A_SPW_TOP|SPW|TX|Selector49~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X54_Y6_N32
dffeas \A_SPW_TOP|SPW|TX|tx_tcode_in[1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|Selector49~0_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|tx_tcode_in [1]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_tcode_in[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|tx_tcode_in[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X55_Y6_N51
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~2 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~2_combout  = (!\A_SPW_TOP|SPW|TX|Equal0~3_combout  & ((\A_SPW_TOP|SPW|TX|tx_tcode_in [1]))) # (\A_SPW_TOP|SPW|TX|Equal0~3_combout  & (\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [1]))

        .dataa(!\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [1]),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|TX|tx_tcode_in [1]),
        .datad(!\A_SPW_TOP|SPW|TX|Equal0~3_combout ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~2 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~2 .lut_mask = 64'h0F550F550F550F55;
defparam \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X55_Y6_N53
dffeas \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx[1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~2_combout ),
        .asdata(vcc),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [1]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y18_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_payload~3 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_payload~3_combout  = (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_WDATA [3])

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
        .datac(gnd),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_WDATA [3]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_014|src_payload~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_payload~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_payload~3 .lut_mask = 64'h0033003300330033;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_payload~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y18_N5
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_014|src_payload~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[3] .power_up = "low";
// synopsys translate_on

// Location: FF_X30_Y18_N59
dffeas \u0|timecode_tx_data|data_out[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [3]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|timecode_tx_data|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|timecode_tx_data|data_out [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|timecode_tx_data|data_out[3] .is_wysiwyg = "true";
defparam \u0|timecode_tx_data|data_out[3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X55_Y6_N3
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector47~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector47~0_combout  = ( \A_SPW_TOP|SPW|TX|tx_tcode_in [3] & ( \u0|timecode_tx_data|data_out [3] & ( (!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~5_combout ) # ((!\A_SPW_TOP|SPW|TX|Selector50~1_combout ) # 
// (\A_SPW_TOP|SPW|TX|Selector50~0_combout )) ) ) ) # ( !\A_SPW_TOP|SPW|TX|tx_tcode_in [3] & ( \u0|timecode_tx_data|data_out [3] & ( ((!\A_SPW_TOP|SPW|TX|tx_tcode_in~0_combout  & !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~5_combout )) # 
// (\A_SPW_TOP|SPW|TX|Selector50~0_combout ) ) ) ) # ( \A_SPW_TOP|SPW|TX|tx_tcode_in [3] & ( !\u0|timecode_tx_data|data_out [3] & ( (!\A_SPW_TOP|SPW|TX|Selector50~1_combout ) # ((\A_SPW_TOP|SPW|TX|tx_tcode_in~0_combout  & 
// !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~5_combout )) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|tx_tcode_in~0_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~5_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|Selector50~0_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|Selector50~1_combout ),
        .datae(!\A_SPW_TOP|SPW|TX|tx_tcode_in [3]),
        .dataf(!\u0|timecode_tx_data|data_out [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector47~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector47~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector47~0 .lut_mask = 64'h0000FF448F8FFFCF;
defparam \A_SPW_TOP|SPW|TX|Selector47~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X54_Y6_N41
dffeas \A_SPW_TOP|SPW|TX|tx_tcode_in[3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|Selector47~0_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|tx_tcode_in [3]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_tcode_in[3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|tx_tcode_in[3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X55_Y6_N24
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~0_combout  = ( \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [3] & ( (\A_SPW_TOP|SPW|TX|tx_tcode_in [3]) # (\A_SPW_TOP|SPW|TX|Equal0~3_combout ) ) ) # ( !\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [3] & ( 
// (!\A_SPW_TOP|SPW|TX|Equal0~3_combout  & \A_SPW_TOP|SPW|TX|tx_tcode_in [3]) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|SPW|TX|Equal0~3_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|tx_tcode_in [3]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~0 .lut_mask = 64'h0C0C0C0C3F3F3F3F;
defparam \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X56_Y6_N50
dffeas \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx[3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~0_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [3]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx[3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y18_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_payload~2 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_payload~2_combout  = ( \u0|hps_0|fpga_interfaces|h2f_WDATA [2] & ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_WDATA [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_014|src_payload~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_payload~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_payload~2 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_payload~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y18_N2
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_014|src_payload~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[2] .power_up = "low";
// synopsys translate_on

// Location: FF_X30_Y18_N56
dffeas \u0|timecode_tx_data|data_out[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [2]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|timecode_tx_data|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|timecode_tx_data|data_out [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|timecode_tx_data|data_out[2] .is_wysiwyg = "true";
defparam \u0|timecode_tx_data|data_out[2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X55_Y6_N6
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector48~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector48~0_combout  = ( \A_SPW_TOP|SPW|TX|tx_tcode_in [2] & ( \u0|timecode_tx_data|data_out [2] & ( ((!\A_SPW_TOP|SPW|TX|Selector50~1_combout ) # (!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~5_combout )) # 
// (\A_SPW_TOP|SPW|TX|Selector50~0_combout ) ) ) ) # ( !\A_SPW_TOP|SPW|TX|tx_tcode_in [2] & ( \u0|timecode_tx_data|data_out [2] & ( ((!\A_SPW_TOP|SPW|TX|tx_tcode_in~0_combout  & !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~5_combout )) # 
// (\A_SPW_TOP|SPW|TX|Selector50~0_combout ) ) ) ) # ( \A_SPW_TOP|SPW|TX|tx_tcode_in [2] & ( !\u0|timecode_tx_data|data_out [2] & ( (!\A_SPW_TOP|SPW|TX|Selector50~1_combout ) # ((\A_SPW_TOP|SPW|TX|tx_tcode_in~0_combout  & 
// !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~5_combout )) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|tx_tcode_in~0_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|Selector50~0_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|Selector50~1_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~5_combout ),
        .datae(!\A_SPW_TOP|SPW|TX|tx_tcode_in [2]),
        .dataf(!\u0|timecode_tx_data|data_out [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector48~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector48~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector48~0 .lut_mask = 64'h0000F5F0BB33FFF3;
defparam \A_SPW_TOP|SPW|TX|Selector48~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X54_Y6_N53
dffeas \A_SPW_TOP|SPW|TX|tx_tcode_in[2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|Selector48~0_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|tx_tcode_in [2]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_tcode_in[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|tx_tcode_in[2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X55_Y6_N12
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~1 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~1_combout  = ( \A_SPW_TOP|SPW|TX|tx_tcode_in [2] & ( (!\A_SPW_TOP|SPW|TX|Equal0~3_combout ) # (\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [2]) ) ) # ( !\A_SPW_TOP|SPW|TX|tx_tcode_in [2] & ( 
// (\A_SPW_TOP|SPW|TX|Equal0~3_combout  & \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [2]) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|SPW|TX|Equal0~3_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [2]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|tx_tcode_in [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~1 .lut_mask = 64'h03030303CFCFCFCF;
defparam \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X56_Y6_N17
dffeas \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx[2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~1_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [2]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y18_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_payload~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_payload~0_combout  = (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_WDATA [0])

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_WDATA [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_014|src_payload~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_payload~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_payload~0 .lut_mask = 64'h0303030303030303;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_payload~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y18_N23
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_014|src_payload~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X30_Y18_N11
dffeas \u0|timecode_tx_data|data_out[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [0]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|timecode_tx_data|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|timecode_tx_data|data_out [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|timecode_tx_data|data_out[0] .is_wysiwyg = "true";
defparam \u0|timecode_tx_data|data_out[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X55_Y6_N0
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector50~2 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector50~2_combout  = ( \A_SPW_TOP|SPW|TX|tx_tcode_in [0] & ( \u0|timecode_tx_data|data_out [0] & ( (!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~5_combout ) # ((!\A_SPW_TOP|SPW|TX|Selector50~1_combout ) # 
// (\A_SPW_TOP|SPW|TX|Selector50~0_combout )) ) ) ) # ( !\A_SPW_TOP|SPW|TX|tx_tcode_in [0] & ( \u0|timecode_tx_data|data_out [0] & ( ((!\A_SPW_TOP|SPW|TX|tx_tcode_in~0_combout  & !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~5_combout )) # 
// (\A_SPW_TOP|SPW|TX|Selector50~0_combout ) ) ) ) # ( \A_SPW_TOP|SPW|TX|tx_tcode_in [0] & ( !\u0|timecode_tx_data|data_out [0] & ( (!\A_SPW_TOP|SPW|TX|Selector50~1_combout ) # ((\A_SPW_TOP|SPW|TX|tx_tcode_in~0_combout  & 
// !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~5_combout )) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|tx_tcode_in~0_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~5_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|Selector50~1_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|Selector50~0_combout ),
        .datae(!\A_SPW_TOP|SPW|TX|tx_tcode_in [0]),
        .dataf(!\u0|timecode_tx_data|data_out [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector50~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector50~2 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector50~2 .lut_mask = 64'h0000F4F488FFFCFF;
defparam \A_SPW_TOP|SPW|TX|Selector50~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X54_Y6_N59
dffeas \A_SPW_TOP|SPW|TX|tx_tcode_in[0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|Selector50~2_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|tx_tcode_in [0]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_tcode_in[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|tx_tcode_in[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X56_Y6_N42
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~3 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~3_combout  = ( \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [0] & ( (\A_SPW_TOP|SPW|TX|tx_tcode_in [0]) # (\A_SPW_TOP|SPW|TX|Equal0~3_combout ) ) ) # ( !\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [0] & ( 
// (!\A_SPW_TOP|SPW|TX|Equal0~3_combout  & \A_SPW_TOP|SPW|TX|tx_tcode_in [0]) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|SPW|TX|Equal0~3_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|tx_tcode_in [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~3 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~3 .lut_mask = 64'h0C0C0C0C3F3F3F3F;
defparam \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X56_Y6_N32
dffeas \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx[0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~3_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [0]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y19_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_payload~7 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_payload~7_combout  = ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_WDATA [7] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_WDATA [7]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_014|src_payload~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_payload~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_payload~7 .lut_mask = 64'h000000000000FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_payload~7 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y19_N5
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[7] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_014|src_payload~7_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [7]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[7] .power_up = "low";
// synopsys translate_on

// Location: FF_X30_Y19_N17
dffeas \u0|timecode_tx_data|data_out[7] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [7]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|timecode_tx_data|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|timecode_tx_data|data_out [7]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|timecode_tx_data|data_out[7] .is_wysiwyg = "true";
defparam \u0|timecode_tx_data|data_out[7] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X55_Y6_N36
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector43~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector43~0_combout  = ( \A_SPW_TOP|SPW|TX|tx_tcode_in [7] & ( \u0|timecode_tx_data|data_out [7] & ( ((!\A_SPW_TOP|SPW|TX|Selector50~1_combout ) # (!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~5_combout )) # 
// (\A_SPW_TOP|SPW|TX|Selector50~0_combout ) ) ) ) # ( !\A_SPW_TOP|SPW|TX|tx_tcode_in [7] & ( \u0|timecode_tx_data|data_out [7] & ( ((!\A_SPW_TOP|SPW|TX|tx_tcode_in~0_combout  & !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~5_combout )) # 
// (\A_SPW_TOP|SPW|TX|Selector50~0_combout ) ) ) ) # ( \A_SPW_TOP|SPW|TX|tx_tcode_in [7] & ( !\u0|timecode_tx_data|data_out [7] & ( (!\A_SPW_TOP|SPW|TX|Selector50~1_combout ) # ((\A_SPW_TOP|SPW|TX|tx_tcode_in~0_combout  & 
// !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~5_combout )) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|tx_tcode_in~0_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|Selector50~0_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|Selector50~1_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~5_combout ),
        .datae(!\A_SPW_TOP|SPW|TX|tx_tcode_in [7]),
        .dataf(!\u0|timecode_tx_data|data_out [7]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector43~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector43~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector43~0 .lut_mask = 64'h0000F5F0BB33FFF3;
defparam \A_SPW_TOP|SPW|TX|Selector43~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X54_Y6_N38
dffeas \A_SPW_TOP|SPW|TX|tx_tcode_in[7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|Selector43~0_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|tx_tcode_in [7]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_tcode_in[7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|tx_tcode_in[7] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X55_Y6_N45
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~4 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~4_combout  = ( \A_SPW_TOP|SPW|TX|tx_tcode_in [7] & ( (!\A_SPW_TOP|SPW|TX|Equal0~3_combout ) # (\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [7]) ) ) # ( !\A_SPW_TOP|SPW|TX|tx_tcode_in [7] & ( 
// (\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [7] & \A_SPW_TOP|SPW|TX|Equal0~3_combout ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [7]),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|TX|Equal0~3_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|tx_tcode_in [7]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~4 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~4 .lut_mask = 64'h05050505F5F5F5F5;
defparam \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X56_Y6_N41
dffeas \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx[7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~4_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [7]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx[7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx[7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y19_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_payload~6 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_payload~6_combout  = ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_WDATA [6] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_WDATA [6]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_014|src_payload~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_payload~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_payload~6 .lut_mask = 64'h000000000000FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_payload~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y19_N50
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_014|src_payload~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[6] .power_up = "low";
// synopsys translate_on

// Location: FF_X30_Y19_N8
dffeas \u0|timecode_tx_data|data_out[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [6]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|timecode_tx_data|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|timecode_tx_data|data_out [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|timecode_tx_data|data_out[6] .is_wysiwyg = "true";
defparam \u0|timecode_tx_data|data_out[6] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X55_Y6_N39
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector44~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector44~0_combout  = ( \A_SPW_TOP|SPW|TX|tx_tcode_in [6] & ( \u0|timecode_tx_data|data_out [6] & ( ((!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~5_combout ) # (!\A_SPW_TOP|SPW|TX|Selector50~1_combout )) # 
// (\A_SPW_TOP|SPW|TX|Selector50~0_combout ) ) ) ) # ( !\A_SPW_TOP|SPW|TX|tx_tcode_in [6] & ( \u0|timecode_tx_data|data_out [6] & ( ((!\A_SPW_TOP|SPW|TX|tx_tcode_in~0_combout  & !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~5_combout )) # 
// (\A_SPW_TOP|SPW|TX|Selector50~0_combout ) ) ) ) # ( \A_SPW_TOP|SPW|TX|tx_tcode_in [6] & ( !\u0|timecode_tx_data|data_out [6] & ( (!\A_SPW_TOP|SPW|TX|Selector50~1_combout ) # ((\A_SPW_TOP|SPW|TX|tx_tcode_in~0_combout  & 
// !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~5_combout )) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|tx_tcode_in~0_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|Selector50~0_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~5_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|Selector50~1_combout ),
        .datae(!\A_SPW_TOP|SPW|TX|tx_tcode_in [6]),
        .dataf(!\u0|timecode_tx_data|data_out [6]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector44~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector44~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector44~0 .lut_mask = 64'h0000FF50B3B3FFF3;
defparam \A_SPW_TOP|SPW|TX|Selector44~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X54_Y6_N29
dffeas \A_SPW_TOP|SPW|TX|tx_tcode_in[6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|Selector44~0_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|tx_tcode_in [6]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_tcode_in[6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|tx_tcode_in[6] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X55_Y6_N18
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~5 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~5_combout  = (!\A_SPW_TOP|SPW|TX|Equal0~3_combout  & ((\A_SPW_TOP|SPW|TX|tx_tcode_in [6]))) # (\A_SPW_TOP|SPW|TX|Equal0~3_combout  & (\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [6]))

        .dataa(gnd),
        .datab(!\A_SPW_TOP|SPW|TX|Equal0~3_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [6]),
        .datad(!\A_SPW_TOP|SPW|TX|tx_tcode_in [6]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~5 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~5 .lut_mask = 64'h03CF03CF03CF03CF;
defparam \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X55_Y6_N23
dffeas \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx[6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~5_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [6]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx[6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y18_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_payload~5 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_payload~5_combout  = ( \u0|hps_0|fpga_interfaces|h2f_WDATA [5] & ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_WDATA [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_014|src_payload~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_payload~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_payload~5 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_payload~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y18_N17
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_014|src_payload~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[5] .power_up = "low";
// synopsys translate_on

// Location: FF_X30_Y18_N29
dffeas \u0|timecode_tx_data|data_out[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [5]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|timecode_tx_data|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|timecode_tx_data|data_out [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|timecode_tx_data|data_out[5] .is_wysiwyg = "true";
defparam \u0|timecode_tx_data|data_out[5] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X55_Y6_N54
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector45~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector45~0_combout  = ( \A_SPW_TOP|SPW|TX|tx_tcode_in [5] & ( \u0|timecode_tx_data|data_out [5] & ( (!\A_SPW_TOP|SPW|TX|Selector50~1_combout ) # ((!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~5_combout ) # 
// (\A_SPW_TOP|SPW|TX|Selector50~0_combout )) ) ) ) # ( !\A_SPW_TOP|SPW|TX|tx_tcode_in [5] & ( \u0|timecode_tx_data|data_out [5] & ( ((!\A_SPW_TOP|SPW|TX|tx_tcode_in~0_combout  & !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~5_combout )) # 
// (\A_SPW_TOP|SPW|TX|Selector50~0_combout ) ) ) ) # ( \A_SPW_TOP|SPW|TX|tx_tcode_in [5] & ( !\u0|timecode_tx_data|data_out [5] & ( (!\A_SPW_TOP|SPW|TX|Selector50~1_combout ) # ((\A_SPW_TOP|SPW|TX|tx_tcode_in~0_combout  & 
// !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~5_combout )) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|Selector50~1_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|Selector50~0_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|tx_tcode_in~0_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~5_combout ),
        .datae(!\A_SPW_TOP|SPW|TX|tx_tcode_in [5]),
        .dataf(!\u0|timecode_tx_data|data_out [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector45~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector45~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector45~0 .lut_mask = 64'h0000AFAAF333FFBB;
defparam \A_SPW_TOP|SPW|TX|Selector45~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X54_Y6_N14
dffeas \A_SPW_TOP|SPW|TX|tx_tcode_in[5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|Selector45~0_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|tx_tcode_in [5]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_tcode_in[5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|tx_tcode_in[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X56_Y6_N45
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~6 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~6_combout  = (!\A_SPW_TOP|SPW|TX|Equal0~3_combout  & ((\A_SPW_TOP|SPW|TX|tx_tcode_in [5]))) # (\A_SPW_TOP|SPW|TX|Equal0~3_combout  & (\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [5]))

        .dataa(!\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [5]),
        .datab(!\A_SPW_TOP|SPW|TX|Equal0~3_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|tx_tcode_in [5]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~6 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~6 .lut_mask = 64'h1D1D1D1D1D1D1D1D;
defparam \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X56_Y6_N29
dffeas \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx[5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~6_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [5]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx[5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y18_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_payload~4 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_payload~4_combout  = ( \u0|hps_0|fpga_interfaces|h2f_WDATA [4] & ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_WDATA [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_014|src_payload~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_payload~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_payload~4 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_payload~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y18_N14
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_014|src_payload~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[4] .power_up = "low";
// synopsys translate_on

// Location: FF_X30_Y18_N26
dffeas \u0|timecode_tx_data|data_out[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [4]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|timecode_tx_data|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|timecode_tx_data|data_out [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|timecode_tx_data|data_out[4] .is_wysiwyg = "true";
defparam \u0|timecode_tx_data|data_out[4] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X55_Y6_N57
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector46~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector46~0_combout  = ( \A_SPW_TOP|SPW|TX|tx_tcode_in [4] & ( \u0|timecode_tx_data|data_out [4] & ( (!\A_SPW_TOP|SPW|TX|Selector50~1_combout ) # ((!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~5_combout ) # 
// (\A_SPW_TOP|SPW|TX|Selector50~0_combout )) ) ) ) # ( !\A_SPW_TOP|SPW|TX|tx_tcode_in [4] & ( \u0|timecode_tx_data|data_out [4] & ( ((!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~5_combout  & !\A_SPW_TOP|SPW|TX|tx_tcode_in~0_combout )) # 
// (\A_SPW_TOP|SPW|TX|Selector50~0_combout ) ) ) ) # ( \A_SPW_TOP|SPW|TX|tx_tcode_in [4] & ( !\u0|timecode_tx_data|data_out [4] & ( (!\A_SPW_TOP|SPW|TX|Selector50~1_combout ) # ((!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~5_combout  & 
// \A_SPW_TOP|SPW|TX|tx_tcode_in~0_combout )) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|Selector50~1_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|Selector50~0_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~5_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|tx_tcode_in~0_combout ),
        .datae(!\A_SPW_TOP|SPW|TX|tx_tcode_in [4]),
        .dataf(!\u0|timecode_tx_data|data_out [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector46~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector46~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector46~0 .lut_mask = 64'h0000AAFAF333FBFB;
defparam \A_SPW_TOP|SPW|TX|Selector46~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X54_Y6_N47
dffeas \A_SPW_TOP|SPW|TX|tx_tcode_in[4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|Selector46~0_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|tx_tcode_in [4]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_tcode_in[4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|tx_tcode_in[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X56_Y6_N21
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~7 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~7_combout  = ( \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [4] & ( (\A_SPW_TOP|SPW|TX|Equal0~3_combout ) # (\A_SPW_TOP|SPW|TX|tx_tcode_in [4]) ) ) # ( !\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [4] & ( 
// (\A_SPW_TOP|SPW|TX|tx_tcode_in [4] & !\A_SPW_TOP|SPW|TX|Equal0~3_combout ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|tx_tcode_in [4]),
        .datab(!\A_SPW_TOP|SPW|TX|Equal0~3_combout ),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~7 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~7 .lut_mask = 64'h4444444477777777;
defparam \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~7 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X56_Y6_N20
dffeas \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx[4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~7_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [4]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx[4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx[4] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X55_Y6_N42
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout~7 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout~7_combout  = ( \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [4] & ( !\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [7] $ (!\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [6] $ (!\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [5])) 
// ) ) # ( !\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [4] & ( !\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [7] $ (!\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [6] $ (\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [5])) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [7]),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [6]),
        .datad(!\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [5]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|tx_dout~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout~7 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout~7 .lut_mask = 64'h5AA55AA5A55AA55A;
defparam \A_SPW_TOP|SPW|TX|tx_dout~7 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X55_Y6_N48
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout~8 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout~8_combout  = ( \A_SPW_TOP|SPW|TX|tx_dout~7_combout  & ( !\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [1] $ (!\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [3] $ (!\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [2] $ 
// (\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [0]))) ) ) # ( !\A_SPW_TOP|SPW|TX|tx_dout~7_combout  & ( !\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [1] $ (!\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [3] $ 
// (!\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [2] $ (!\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [0]))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [1]),
        .datab(!\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [3]),
        .datac(!\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [2]),
        .datad(!\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [0]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|tx_dout~7_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|tx_dout~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout~8 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout~8 .lut_mask = 64'h6996699696699669;
defparam \A_SPW_TOP|SPW|TX|tx_dout~8 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X55_Y7_N12
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout~22 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout~22_combout  = ( \A_SPW_TOP|SPW|TX|tx_dout~8_combout  & ( \A_SPW_TOP|SPW|TX|always0~9_combout  & ( ((!\A_SPW_TOP|SPW|TX|always0~7_combout  & (\A_SPW_TOP|SPW|TX|always0~6_combout )) # (\A_SPW_TOP|SPW|TX|always0~7_combout  & 
// ((\A_SPW_TOP|SPW|TX|tx_dout~5_combout )))) # (\A_SPW_TOP|SPW|TX|tx_dout~6_combout ) ) ) ) # ( !\A_SPW_TOP|SPW|TX|tx_dout~8_combout  & ( \A_SPW_TOP|SPW|TX|always0~9_combout  & ( ((\A_SPW_TOP|SPW|TX|tx_dout~5_combout  & \A_SPW_TOP|SPW|TX|always0~7_combout 
// )) # (\A_SPW_TOP|SPW|TX|tx_dout~6_combout ) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|tx_dout~6_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|always0~6_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|tx_dout~5_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|always0~7_combout ),
        .datae(!\A_SPW_TOP|SPW|TX|tx_dout~8_combout ),
        .dataf(!\A_SPW_TOP|SPW|TX|always0~9_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|tx_dout~22_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout~22 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout~22 .lut_mask = 64'h00000000555F775F;
defparam \A_SPW_TOP|SPW|TX|tx_dout~22 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X58_Y7_N6
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector0~2 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector0~2_combout  = ( \A_SPW_TOP|SPW|TX|last_type.TIMEC~q  & ( \A_SPW_TOP|SPW|TX|always0~8_combout  & ( (\A_SPW_TOP|SPW|TX|Equal0~0_combout  & ((!\A_SPW_TOP|SPW|TX|last_type.NULL~q ) # ((!\A_SPW_TOP|SPW|TX|tx_data_in_0 [8]) # 
// (\A_SPW_TOP|SPW|TX|last_type.FCT~q )))) ) ) ) # ( !\A_SPW_TOP|SPW|TX|last_type.TIMEC~q  & ( \A_SPW_TOP|SPW|TX|always0~8_combout  & ( (\A_SPW_TOP|SPW|TX|Equal0~0_combout  & ((!\A_SPW_TOP|SPW|TX|last_type.NULL~q ) # (\A_SPW_TOP|SPW|TX|last_type.FCT~q ))) ) 
// ) ) # ( \A_SPW_TOP|SPW|TX|last_type.TIMEC~q  & ( !\A_SPW_TOP|SPW|TX|always0~8_combout  & ( (!\A_SPW_TOP|SPW|TX|tx_data_in_0 [8] & \A_SPW_TOP|SPW|TX|Equal0~0_combout ) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|last_type.NULL~q ),
        .datab(!\A_SPW_TOP|SPW|TX|tx_data_in_0 [8]),
        .datac(!\A_SPW_TOP|SPW|TX|Equal0~0_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|last_type.FCT~q ),
        .datae(!\A_SPW_TOP|SPW|TX|last_type.TIMEC~q ),
        .dataf(!\A_SPW_TOP|SPW|TX|always0~8_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector0~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector0~2 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector0~2 .lut_mask = 64'h00000C0C0A0F0E0F;
defparam \A_SPW_TOP|SPW|TX|Selector0~2 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X60_Y7_N33
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector0~3 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector0~3_combout  = ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q  & ( \A_SPW_TOP|SPW|TX|tx_data_in_0 [8] & ( !\A_SPW_TOP|SPW|TX|Selector0~2_combout  ) ) ) # ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q  & ( 
// !\A_SPW_TOP|SPW|TX|tx_data_in_0 [8] & ( (!\A_SPW_TOP|SPW|TX|tx_dout~6_combout  & (!\A_SPW_TOP|SPW|TX|Selector0~2_combout  & !\A_SPW_TOP|SPW|TX|always0~7_combout )) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|tx_dout~6_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|Selector0~2_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|always0~7_combout ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q ),
        .dataf(!\A_SPW_TOP|SPW|TX|tx_data_in_0 [8]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector0~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector0~3 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector0~3 .lut_mask = 64'h000080800000CCCC;
defparam \A_SPW_TOP|SPW|TX|Selector0~3 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X55_Y7_N15
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout~24 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout~24_combout  = ( \A_SPW_TOP|SPW|TX|tx_dout~8_combout  & ( \A_SPW_TOP|SPW|TX|always0~8_combout  & ( ((!\A_SPW_TOP|SPW|TX|always0~7_combout  & (\A_SPW_TOP|SPW|TX|always0~6_combout )) # (\A_SPW_TOP|SPW|TX|always0~7_combout  & 
// ((\A_SPW_TOP|SPW|TX|tx_dout~5_combout )))) # (\A_SPW_TOP|SPW|TX|tx_dout~6_combout ) ) ) ) # ( !\A_SPW_TOP|SPW|TX|tx_dout~8_combout  & ( \A_SPW_TOP|SPW|TX|always0~8_combout  & ( ((\A_SPW_TOP|SPW|TX|always0~7_combout  & \A_SPW_TOP|SPW|TX|tx_dout~5_combout 
// )) # (\A_SPW_TOP|SPW|TX|tx_dout~6_combout ) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|tx_dout~6_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|always0~6_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|always0~7_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|tx_dout~5_combout ),
        .datae(!\A_SPW_TOP|SPW|TX|tx_dout~8_combout ),
        .dataf(!\A_SPW_TOP|SPW|TX|always0~8_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|tx_dout~24_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout~24 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout~24 .lut_mask = 64'h00000000555F757F;
defparam \A_SPW_TOP|SPW|TX|tx_dout~24 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X55_Y7_N54
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector0~4 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector0~4_combout  = ( \A_SPW_TOP|SPW|TX|Selector0~3_combout  & ( \A_SPW_TOP|SPW|TX|tx_dout~24_combout  ) ) # ( \A_SPW_TOP|SPW|TX|Selector0~3_combout  & ( !\A_SPW_TOP|SPW|TX|tx_dout~24_combout  & ( (\A_SPW_TOP|SPW|TX|tx_dout~23_combout 
//  & (((\A_SPW_TOP|SPW|TX|tx_dout~21_combout  & !\A_SPW_TOP|SPW|TX|tx_dout~20_combout )) # (\A_SPW_TOP|SPW|TX|tx_dout~22_combout ))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|tx_dout~23_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|tx_dout~21_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|tx_dout~20_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|tx_dout~22_combout ),
        .datae(!\A_SPW_TOP|SPW|TX|Selector0~3_combout ),
        .dataf(!\A_SPW_TOP|SPW|TX|tx_dout~24_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector0~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector0~4 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector0~4 .lut_mask = 64'h000010550000FFFF;
defparam \A_SPW_TOP|SPW|TX|Selector0~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X58_Y7_N33
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector0~1 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector0~1_combout  = ( \A_SPW_TOP|SPW|TX|last_type.NULL~q  & ( (\A_SPW_TOP|SPW|TX|Equal0~0_combout  & (\A_SPW_TOP|SPW|TX|last_type.FCT~q  & \A_SPW_TOP|SPW|TX|Selector63~0_combout )) ) ) # ( !\A_SPW_TOP|SPW|TX|last_type.NULL~q  & ( 
// (\A_SPW_TOP|SPW|TX|Equal0~0_combout  & \A_SPW_TOP|SPW|TX|Selector63~0_combout ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|Equal0~0_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|last_type.FCT~q ),
        .datac(gnd),
        .datad(!\A_SPW_TOP|SPW|TX|Selector63~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|last_type.NULL~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector0~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector0~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector0~1 .lut_mask = 64'h0055005500110011;
defparam \A_SPW_TOP|SPW|TX|Selector0~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X51_Y7_N57
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout~25 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout~25_combout  = ( \A_SPW_TOP|SPW|TX|tx_dout~q  & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & (\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & ((!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]) # 
// (\A_SPW_TOP|SPW|TX|global_counter_transfer [1])))) ) ) # ( !\A_SPW_TOP|SPW|TX|tx_dout~q  & ( ((!\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & ((!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]))) # (\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & 
// (\A_SPW_TOP|SPW|TX|global_counter_transfer [2]))) # (\A_SPW_TOP|SPW|TX|global_counter_transfer [3]) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
        .datab(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
        .datac(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
        .datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|tx_dout~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|tx_dout~25_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout~25 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout~25 .lut_mask = 64'hDF57DF570A020A02;
defparam \A_SPW_TOP|SPW|TX|tx_dout~25 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X55_Y7_N36
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout~26 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout~26_combout  = ( \A_SPW_TOP|SPW|TX|tx_dout~8_combout  & ( \A_SPW_TOP|SPW|TX|tx_dout~5_combout  & ( (!\A_SPW_TOP|SPW|TX|tx_dout~6_combout  & (!\A_SPW_TOP|SPW|TX|always0~6_combout  & (\A_SPW_TOP|SPW|TX|tx_dout~25_combout  & 
// !\A_SPW_TOP|SPW|TX|always0~7_combout ))) ) ) ) # ( !\A_SPW_TOP|SPW|TX|tx_dout~8_combout  & ( \A_SPW_TOP|SPW|TX|tx_dout~5_combout  & ( (!\A_SPW_TOP|SPW|TX|tx_dout~6_combout  & (!\A_SPW_TOP|SPW|TX|always0~7_combout  & ((\A_SPW_TOP|SPW|TX|tx_dout~25_combout 
// ) # (\A_SPW_TOP|SPW|TX|always0~6_combout )))) ) ) ) # ( \A_SPW_TOP|SPW|TX|tx_dout~8_combout  & ( !\A_SPW_TOP|SPW|TX|tx_dout~5_combout  & ( (!\A_SPW_TOP|SPW|TX|tx_dout~6_combout  & (((!\A_SPW_TOP|SPW|TX|always0~6_combout  & 
// \A_SPW_TOP|SPW|TX|tx_dout~25_combout )) # (\A_SPW_TOP|SPW|TX|always0~7_combout ))) ) ) ) # ( !\A_SPW_TOP|SPW|TX|tx_dout~8_combout  & ( !\A_SPW_TOP|SPW|TX|tx_dout~5_combout  & ( (!\A_SPW_TOP|SPW|TX|tx_dout~6_combout  & 
// (((\A_SPW_TOP|SPW|TX|always0~7_combout ) # (\A_SPW_TOP|SPW|TX|tx_dout~25_combout )) # (\A_SPW_TOP|SPW|TX|always0~6_combout ))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|tx_dout~6_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|always0~6_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|tx_dout~25_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|always0~7_combout ),
        .datae(!\A_SPW_TOP|SPW|TX|tx_dout~8_combout ),
        .dataf(!\A_SPW_TOP|SPW|TX|tx_dout~5_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|tx_dout~26_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout~26 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout~26 .lut_mask = 64'h2AAA08AA2A000800;
defparam \A_SPW_TOP|SPW|TX|tx_dout~26 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X54_Y7_N0
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout~27 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout~27_combout  = ( \A_SPW_TOP|SPW|TX|tx_dout~q  & ( ((!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]) # (\A_SPW_TOP|SPW|TX|global_counter_transfer [2])) # (\A_SPW_TOP|SPW|TX|global_counter_transfer [3]) ) ) # ( 
// !\A_SPW_TOP|SPW|TX|tx_dout~q  & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & (\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & (!\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & !\A_SPW_TOP|SPW|TX|global_counter_transfer [1]))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
        .datab(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
        .datac(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
        .datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|tx_dout~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|tx_dout~27_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout~27 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout~27 .lut_mask = 64'h20002000FF5FFF5F;
defparam \A_SPW_TOP|SPW|TX|tx_dout~27 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X55_Y7_N9
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout~28 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout~28_combout  = ( \A_SPW_TOP|SPW|TX|tx_dout~8_combout  & ( \A_SPW_TOP|SPW|TX|tx_dout~27_combout  & ( (!\A_SPW_TOP|SPW|TX|tx_dout~6_combout  & (!\A_SPW_TOP|SPW|TX|tx_dout~5_combout  & \A_SPW_TOP|SPW|TX|always0~7_combout )) ) ) ) # ( 
// !\A_SPW_TOP|SPW|TX|tx_dout~8_combout  & ( \A_SPW_TOP|SPW|TX|tx_dout~27_combout  & ( (!\A_SPW_TOP|SPW|TX|tx_dout~6_combout  & ((!\A_SPW_TOP|SPW|TX|always0~7_combout  & (\A_SPW_TOP|SPW|TX|always0~6_combout )) # (\A_SPW_TOP|SPW|TX|always0~7_combout  & 
// ((!\A_SPW_TOP|SPW|TX|tx_dout~5_combout ))))) ) ) ) # ( \A_SPW_TOP|SPW|TX|tx_dout~8_combout  & ( !\A_SPW_TOP|SPW|TX|tx_dout~27_combout  & ( (!\A_SPW_TOP|SPW|TX|tx_dout~6_combout  & ((!\A_SPW_TOP|SPW|TX|always0~7_combout  & 
// (!\A_SPW_TOP|SPW|TX|always0~6_combout )) # (\A_SPW_TOP|SPW|TX|always0~7_combout  & ((!\A_SPW_TOP|SPW|TX|tx_dout~5_combout ))))) ) ) ) # ( !\A_SPW_TOP|SPW|TX|tx_dout~8_combout  & ( !\A_SPW_TOP|SPW|TX|tx_dout~27_combout  & ( 
// (!\A_SPW_TOP|SPW|TX|tx_dout~6_combout  & ((!\A_SPW_TOP|SPW|TX|tx_dout~5_combout ) # (!\A_SPW_TOP|SPW|TX|always0~7_combout ))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|tx_dout~6_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|always0~6_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|tx_dout~5_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|always0~7_combout ),
        .datae(!\A_SPW_TOP|SPW|TX|tx_dout~8_combout ),
        .dataf(!\A_SPW_TOP|SPW|TX|tx_dout~27_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|tx_dout~28_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout~28 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout~28 .lut_mask = 64'hAAA088A022A000A0;
defparam \A_SPW_TOP|SPW|TX|tx_dout~28 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X55_Y7_N18
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector0~5 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector0~5_combout  = ( !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~0_combout  & ( \A_SPW_TOP|SPW|TX|tx_dout~28_combout  & ( (!\A_SPW_TOP|SPW|TX|tx_dout~26_combout  & (!\A_SPW_TOP|SPW|TX|always0~10_combout  & 
// !\A_SPW_TOP|SPW|TX|always0~11_combout )) ) ) ) # ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~0_combout  & ( !\A_SPW_TOP|SPW|TX|tx_dout~28_combout  & ( (!\A_SPW_TOP|SPW|TX|always0~10_combout  & (!\A_SPW_TOP|SPW|TX|always0~11_combout  & 
// !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~1_combout )) ) ) ) # ( !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~0_combout  & ( !\A_SPW_TOP|SPW|TX|tx_dout~28_combout  & ( (!\A_SPW_TOP|SPW|TX|always0~10_combout  & (!\A_SPW_TOP|SPW|TX|always0~11_combout  & 
// ((!\A_SPW_TOP|SPW|TX|tx_dout~26_combout ) # (!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~1_combout )))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|tx_dout~26_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|always0~10_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|always0~11_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~1_combout ),
        .datae(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~0_combout ),
        .dataf(!\A_SPW_TOP|SPW|TX|tx_dout~28_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector0~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector0~5 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector0~5 .lut_mask = 64'hC080C00080800000;
defparam \A_SPW_TOP|SPW|TX|Selector0~5 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X55_Y6_N15
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|timecode_s~2 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|timecode_s~2_combout  = (!\A_SPW_TOP|SPW|TX|Equal0~3_combout  & ((\A_SPW_TOP|SPW|TX|tx_tcode_in [1]))) # (\A_SPW_TOP|SPW|TX|Equal0~3_combout  & (\A_SPW_TOP|SPW|TX|timecode_s [1]))

        .dataa(gnd),
        .datab(!\A_SPW_TOP|SPW|TX|Equal0~3_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|timecode_s [1]),
        .datad(!\A_SPW_TOP|SPW|TX|tx_tcode_in [1]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|timecode_s~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|timecode_s~2 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|timecode_s~2 .lut_mask = 64'h03CF03CF03CF03CF;
defparam \A_SPW_TOP|SPW|TX|timecode_s~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X56_Y6_N56
dffeas \A_SPW_TOP|SPW|TX|timecode_s[1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|timecode_s~2_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|timecode_s [1]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|timecode_s[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|timecode_s[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X56_Y6_N36
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|timecode_s~1 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|timecode_s~1_combout  = (!\A_SPW_TOP|SPW|TX|Equal0~3_combout  & ((\A_SPW_TOP|SPW|TX|tx_tcode_in [0]))) # (\A_SPW_TOP|SPW|TX|Equal0~3_combout  & (\A_SPW_TOP|SPW|TX|timecode_s [0]))

        .dataa(gnd),
        .datab(!\A_SPW_TOP|SPW|TX|timecode_s [0]),
        .datac(!\A_SPW_TOP|SPW|TX|tx_tcode_in [0]),
        .datad(!\A_SPW_TOP|SPW|TX|Equal0~3_combout ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|timecode_s~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|timecode_s~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|timecode_s~1 .lut_mask = 64'h0F330F330F330F33;
defparam \A_SPW_TOP|SPW|TX|timecode_s~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X56_Y6_N47
dffeas \A_SPW_TOP|SPW|TX|timecode_s[0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|timecode_s~1_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|timecode_s [0]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|timecode_s[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|timecode_s[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X56_Y6_N9
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|timecode_s~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|timecode_s~0_combout  = (!\A_SPW_TOP|SPW|TX|Equal0~3_combout ) # (\A_SPW_TOP|SPW|TX|timecode_s [9])

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|TX|timecode_s [9]),
        .datad(!\A_SPW_TOP|SPW|TX|Equal0~3_combout ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|timecode_s~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|timecode_s~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|timecode_s~0 .lut_mask = 64'hFF0FFF0FFF0FFF0F;
defparam \A_SPW_TOP|SPW|TX|timecode_s~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X56_Y6_N44
dffeas \A_SPW_TOP|SPW|TX|timecode_s[9] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|timecode_s~0_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|timecode_s [9]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|timecode_s[9] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|timecode_s[9] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X56_Y6_N24
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout~10 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout~10_combout  = ( \A_SPW_TOP|SPW|TX|timecode_s [9] & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & (((!\A_SPW_TOP|SPW|TX|global_counter_transfer [0])))) # (\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & 
// ((!\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & ((\A_SPW_TOP|SPW|TX|timecode_s [0]))) # (\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & (\A_SPW_TOP|SPW|TX|timecode_s [1])))) ) ) # ( !\A_SPW_TOP|SPW|TX|timecode_s [9] & ( 
// (\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & ((!\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & ((\A_SPW_TOP|SPW|TX|timecode_s [0]))) # (\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & (\A_SPW_TOP|SPW|TX|timecode_s [1])))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|timecode_s [1]),
        .datab(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
        .datac(!\A_SPW_TOP|SPW|TX|timecode_s [0]),
        .datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|timecode_s [9]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|tx_dout~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout~10 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout~10 .lut_mask = 64'h03110311CF11CF11;
defparam \A_SPW_TOP|SPW|TX|tx_dout~10 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X54_Y6_N36
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|timecode_s~8 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|timecode_s~8_combout  = ( \A_SPW_TOP|SPW|TX|Equal0~3_combout  & ( \A_SPW_TOP|SPW|TX|timecode_s [7] ) ) # ( !\A_SPW_TOP|SPW|TX|Equal0~3_combout  & ( \A_SPW_TOP|SPW|TX|tx_tcode_in [7] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|TX|timecode_s [7]),
        .datad(!\A_SPW_TOP|SPW|TX|tx_tcode_in [7]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|Equal0~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|timecode_s~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|timecode_s~8 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|timecode_s~8 .lut_mask = 64'h00FF00FF0F0F0F0F;
defparam \A_SPW_TOP|SPW|TX|timecode_s~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X55_Y6_N50
dffeas \A_SPW_TOP|SPW|TX|timecode_s[7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|timecode_s~8_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|timecode_s [7]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|timecode_s[7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|timecode_s[7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X54_Y6_N27
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|timecode_s~7 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|timecode_s~7_combout  = ( \A_SPW_TOP|SPW|TX|timecode_s [6] & ( (\A_SPW_TOP|SPW|TX|tx_tcode_in [6]) # (\A_SPW_TOP|SPW|TX|Equal0~3_combout ) ) ) # ( !\A_SPW_TOP|SPW|TX|timecode_s [6] & ( (!\A_SPW_TOP|SPW|TX|Equal0~3_combout  & 
// \A_SPW_TOP|SPW|TX|tx_tcode_in [6]) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|TX|Equal0~3_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|tx_tcode_in [6]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|timecode_s [6]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|timecode_s~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|timecode_s~7 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|timecode_s~7 .lut_mask = 64'h00F000F00FFF0FFF;
defparam \A_SPW_TOP|SPW|TX|timecode_s~7 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X55_Y6_N35
dffeas \A_SPW_TOP|SPW|TX|timecode_s[6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|timecode_s~7_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|timecode_s [6]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|timecode_s[6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|timecode_s[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X54_Y6_N45
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout~12 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout~12_combout  = ( \A_SPW_TOP|SPW|TX|timecode_s [6] & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & ((!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]) # ((\A_SPW_TOP|SPW|TX|timecode_s [7])))) # 
// (\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & (((\A_SPW_TOP|SPW|TX|tx_dout~q )))) ) ) # ( !\A_SPW_TOP|SPW|TX|timecode_s [6] & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & (\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & 
// ((\A_SPW_TOP|SPW|TX|timecode_s [7])))) # (\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & (((\A_SPW_TOP|SPW|TX|tx_dout~q )))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
        .datab(!\A_SPW_TOP|SPW|TX|tx_dout~q ),
        .datac(!\A_SPW_TOP|SPW|TX|timecode_s [7]),
        .datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|timecode_s [6]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|tx_dout~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout~12 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout~12 .lut_mask = 64'h05330533AF33AF33;
defparam \A_SPW_TOP|SPW|TX|tx_dout~12 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X54_Y6_N42
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout~9 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout~9_combout  = (!\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & (!\A_SPW_TOP|SPW|TX|tx_dout~q  & !\A_SPW_TOP|SPW|TX|global_counter_transfer [1]))

        .dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
        .datab(!\A_SPW_TOP|SPW|TX|tx_dout~q ),
        .datac(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|tx_dout~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout~9 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout~9 .lut_mask = 64'h8080808080808080;
defparam \A_SPW_TOP|SPW|TX|tx_dout~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X56_Y6_N18
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|timecode_s~5 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|timecode_s~5_combout  = ( \A_SPW_TOP|SPW|TX|timecode_s [4] & ( (\A_SPW_TOP|SPW|TX|tx_tcode_in [4]) # (\A_SPW_TOP|SPW|TX|Equal0~3_combout ) ) ) # ( !\A_SPW_TOP|SPW|TX|timecode_s [4] & ( (!\A_SPW_TOP|SPW|TX|Equal0~3_combout  & 
// \A_SPW_TOP|SPW|TX|tx_tcode_in [4]) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|SPW|TX|Equal0~3_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|tx_tcode_in [4]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|timecode_s [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|timecode_s~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|timecode_s~5 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|timecode_s~5 .lut_mask = 64'h0C0C0C0C3F3F3F3F;
defparam \A_SPW_TOP|SPW|TX|timecode_s~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X56_Y6_N53
dffeas \A_SPW_TOP|SPW|TX|timecode_s[4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|timecode_s~5_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|timecode_s [4]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|timecode_s[4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|timecode_s[4] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X55_Y6_N27
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|timecode_s~3 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|timecode_s~3_combout  = ( \A_SPW_TOP|SPW|TX|tx_tcode_in [2] & ( (!\A_SPW_TOP|SPW|TX|Equal0~3_combout ) # (\A_SPW_TOP|SPW|TX|timecode_s [2]) ) ) # ( !\A_SPW_TOP|SPW|TX|tx_tcode_in [2] & ( (\A_SPW_TOP|SPW|TX|Equal0~3_combout  & 
// \A_SPW_TOP|SPW|TX|timecode_s [2]) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|SPW|TX|Equal0~3_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|timecode_s [2]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|tx_tcode_in [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|timecode_s~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|timecode_s~3 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|timecode_s~3 .lut_mask = 64'h03030303CFCFCFCF;
defparam \A_SPW_TOP|SPW|TX|timecode_s~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X56_Y6_N59
dffeas \A_SPW_TOP|SPW|TX|timecode_s[2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|timecode_s~3_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|timecode_s [2]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|timecode_s[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|timecode_s[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X56_Y6_N0
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|timecode_s~6 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|timecode_s~6_combout  = ( \A_SPW_TOP|SPW|TX|tx_tcode_in [5] & ( (!\A_SPW_TOP|SPW|TX|Equal0~3_combout ) # (\A_SPW_TOP|SPW|TX|timecode_s [5]) ) ) # ( !\A_SPW_TOP|SPW|TX|tx_tcode_in [5] & ( (\A_SPW_TOP|SPW|TX|timecode_s [5] & 
// \A_SPW_TOP|SPW|TX|Equal0~3_combout ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|TX|timecode_s [5]),
        .datad(!\A_SPW_TOP|SPW|TX|Equal0~3_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|tx_tcode_in [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|timecode_s~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|timecode_s~6 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|timecode_s~6 .lut_mask = 64'h000F000FFF0FFF0F;
defparam \A_SPW_TOP|SPW|TX|timecode_s~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X56_Y6_N13
dffeas \A_SPW_TOP|SPW|TX|timecode_s[5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|timecode_s~6_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|timecode_s [5]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|timecode_s[5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|timecode_s[5] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X55_Y6_N21
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|timecode_s~4 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|timecode_s~4_combout  = ( \A_SPW_TOP|SPW|TX|tx_tcode_in [3] & ( (!\A_SPW_TOP|SPW|TX|Equal0~3_combout ) # (\A_SPW_TOP|SPW|TX|timecode_s [3]) ) ) # ( !\A_SPW_TOP|SPW|TX|tx_tcode_in [3] & ( (\A_SPW_TOP|SPW|TX|Equal0~3_combout  & 
// \A_SPW_TOP|SPW|TX|timecode_s [3]) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|SPW|TX|Equal0~3_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|timecode_s [3]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|tx_tcode_in [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|timecode_s~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|timecode_s~4 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|timecode_s~4 .lut_mask = 64'h03030303CFCFCFCF;
defparam \A_SPW_TOP|SPW|TX|timecode_s~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X56_Y6_N35
dffeas \A_SPW_TOP|SPW|TX|timecode_s[3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|timecode_s~4_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|timecode_s [3]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|timecode_s[3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|timecode_s[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X56_Y6_N12
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout~11 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout~11_combout  = ( \A_SPW_TOP|SPW|TX|timecode_s [5] & ( \A_SPW_TOP|SPW|TX|timecode_s [3] & ( ((!\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & ((\A_SPW_TOP|SPW|TX|timecode_s [2]))) # (\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & 
// (\A_SPW_TOP|SPW|TX|timecode_s [4]))) # (\A_SPW_TOP|SPW|TX|global_counter_transfer [0]) ) ) ) # ( !\A_SPW_TOP|SPW|TX|timecode_s [5] & ( \A_SPW_TOP|SPW|TX|timecode_s [3] & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & 
// (((\A_SPW_TOP|SPW|TX|global_counter_transfer [0]) # (\A_SPW_TOP|SPW|TX|timecode_s [2])))) # (\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & (\A_SPW_TOP|SPW|TX|timecode_s [4] & ((!\A_SPW_TOP|SPW|TX|global_counter_transfer [0])))) ) ) ) # ( 
// \A_SPW_TOP|SPW|TX|timecode_s [5] & ( !\A_SPW_TOP|SPW|TX|timecode_s [3] & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & (((\A_SPW_TOP|SPW|TX|timecode_s [2] & !\A_SPW_TOP|SPW|TX|global_counter_transfer [0])))) # 
// (\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & (((\A_SPW_TOP|SPW|TX|global_counter_transfer [0])) # (\A_SPW_TOP|SPW|TX|timecode_s [4]))) ) ) ) # ( !\A_SPW_TOP|SPW|TX|timecode_s [5] & ( !\A_SPW_TOP|SPW|TX|timecode_s [3] & ( 
// (!\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & ((!\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & ((\A_SPW_TOP|SPW|TX|timecode_s [2]))) # (\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & (\A_SPW_TOP|SPW|TX|timecode_s [4])))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|timecode_s [4]),
        .datab(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
        .datac(!\A_SPW_TOP|SPW|TX|timecode_s [2]),
        .datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
        .datae(!\A_SPW_TOP|SPW|TX|timecode_s [5]),
        .dataf(!\A_SPW_TOP|SPW|TX|timecode_s [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|tx_dout~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout~11 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout~11 .lut_mask = 64'h1D001D331DCC1DFF;
defparam \A_SPW_TOP|SPW|TX|tx_dout~11 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X56_Y6_N54
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout~13 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout~13_combout  = ( \A_SPW_TOP|SPW|TX|global_counter_transfer [3] & ( \A_SPW_TOP|SPW|TX|tx_dout~11_combout  & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]) # (\A_SPW_TOP|SPW|TX|tx_dout~12_combout ) ) ) ) # ( 
// !\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & ( \A_SPW_TOP|SPW|TX|tx_dout~11_combout  & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & ((!\A_SPW_TOP|SPW|TX|tx_dout~9_combout ))) # (\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & 
// (\A_SPW_TOP|SPW|TX|tx_dout~10_combout )) ) ) ) # ( \A_SPW_TOP|SPW|TX|global_counter_transfer [3] & ( !\A_SPW_TOP|SPW|TX|tx_dout~11_combout  & ( (\A_SPW_TOP|SPW|TX|tx_dout~12_combout  & \A_SPW_TOP|SPW|TX|global_counter_transfer [2]) ) ) ) # ( 
// !\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & ( !\A_SPW_TOP|SPW|TX|tx_dout~11_combout  & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & ((!\A_SPW_TOP|SPW|TX|tx_dout~9_combout ))) # (\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & 
// (\A_SPW_TOP|SPW|TX|tx_dout~10_combout )) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|tx_dout~10_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|tx_dout~12_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
        .datad(!\A_SPW_TOP|SPW|TX|tx_dout~9_combout ),
        .datae(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
        .dataf(!\A_SPW_TOP|SPW|TX|tx_dout~11_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|tx_dout~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout~13 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout~13 .lut_mask = 64'hF5050303F505F3F3;
defparam \A_SPW_TOP|SPW|TX|tx_dout~13 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X55_Y7_N6
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector0~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector0~0_combout  = ( \A_SPW_TOP|SPW|TX|tx_dout~8_combout  & ( \A_SPW_TOP|SPW|TX|tx_dout~13_combout  & ( (!\A_SPW_TOP|SPW|TX|tx_dout~6_combout  & (\A_SPW_TOP|SPW|TX|always0~7_combout  & !\A_SPW_TOP|SPW|TX|tx_dout~5_combout )) ) ) ) # 
// ( !\A_SPW_TOP|SPW|TX|tx_dout~8_combout  & ( \A_SPW_TOP|SPW|TX|tx_dout~13_combout  & ( (!\A_SPW_TOP|SPW|TX|tx_dout~6_combout  & ((!\A_SPW_TOP|SPW|TX|always0~7_combout  & (\A_SPW_TOP|SPW|TX|always0~6_combout )) # (\A_SPW_TOP|SPW|TX|always0~7_combout  & 
// ((!\A_SPW_TOP|SPW|TX|tx_dout~5_combout ))))) ) ) ) # ( \A_SPW_TOP|SPW|TX|tx_dout~8_combout  & ( !\A_SPW_TOP|SPW|TX|tx_dout~13_combout  & ( (!\A_SPW_TOP|SPW|TX|tx_dout~6_combout  & ((!\A_SPW_TOP|SPW|TX|always0~7_combout  & 
// (!\A_SPW_TOP|SPW|TX|always0~6_combout )) # (\A_SPW_TOP|SPW|TX|always0~7_combout  & ((!\A_SPW_TOP|SPW|TX|tx_dout~5_combout ))))) ) ) ) # ( !\A_SPW_TOP|SPW|TX|tx_dout~8_combout  & ( !\A_SPW_TOP|SPW|TX|tx_dout~13_combout  & ( 
// (!\A_SPW_TOP|SPW|TX|tx_dout~6_combout  & ((!\A_SPW_TOP|SPW|TX|always0~7_combout ) # (!\A_SPW_TOP|SPW|TX|tx_dout~5_combout ))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|tx_dout~6_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|always0~6_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|always0~7_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|tx_dout~5_combout ),
        .datae(!\A_SPW_TOP|SPW|TX|tx_dout~8_combout ),
        .dataf(!\A_SPW_TOP|SPW|TX|tx_dout~13_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector0~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector0~0 .lut_mask = 64'hAAA08A802A200A00;
defparam \A_SPW_TOP|SPW|TX|Selector0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X54_Y7_N21
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|always0~12 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|always0~12_combout  = ( !\A_SPW_TOP|SPW|TX|tx_data_in [0] & ( (\A_SPW_TOP|SPW|TX|tx_data_in [8] & !\A_SPW_TOP|SPW|TX|tx_data_in [1]) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|tx_data_in [8]),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|TX|tx_data_in [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|tx_data_in [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|always0~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|always0~12 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|always0~12 .lut_mask = 64'h5050505000000000;
defparam \A_SPW_TOP|SPW|TX|always0~12 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X54_Y7_N24
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|always0~13 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|always0~13_combout  = ( \A_SPW_TOP|SPW|TX|tx_data_in [0] & ( (!\A_SPW_TOP|SPW|TX|tx_data_in [1] & \A_SPW_TOP|SPW|TX|tx_data_in [8]) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|tx_data_in [1]),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|TX|tx_data_in [8]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|tx_data_in [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|always0~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|always0~13 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|always0~13 .lut_mask = 64'h000000000A0A0A0A;
defparam \A_SPW_TOP|SPW|TX|always0~13 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X55_Y7_N51
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout~36 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout~36_combout  = ( \A_SPW_TOP|SPW|TX|always0~12_combout  & ( \A_SPW_TOP|SPW|TX|always0~13_combout  & ( (!\A_SPW_TOP|SPW|TX|always0~11_combout  & (!\A_SPW_TOP|SPW|TX|always0~10_combout  & (!\A_SPW_TOP|SPW|TX|always0~6_combout  & 
// !\A_SPW_TOP|SPW|TX|always0~7_combout ))) ) ) ) # ( !\A_SPW_TOP|SPW|TX|always0~12_combout  & ( \A_SPW_TOP|SPW|TX|always0~13_combout  & ( (!\A_SPW_TOP|SPW|TX|always0~11_combout  & !\A_SPW_TOP|SPW|TX|always0~10_combout ) ) ) ) # ( 
// \A_SPW_TOP|SPW|TX|always0~12_combout  & ( !\A_SPW_TOP|SPW|TX|always0~13_combout  & ( (!\A_SPW_TOP|SPW|TX|always0~6_combout  & !\A_SPW_TOP|SPW|TX|always0~7_combout ) ) ) ) # ( !\A_SPW_TOP|SPW|TX|always0~12_combout  & ( !\A_SPW_TOP|SPW|TX|always0~13_combout 
//  ) )

        .dataa(!\A_SPW_TOP|SPW|TX|always0~11_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|always0~10_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|always0~6_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|always0~7_combout ),
        .datae(!\A_SPW_TOP|SPW|TX|always0~12_combout ),
        .dataf(!\A_SPW_TOP|SPW|TX|always0~13_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|tx_dout~36_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout~36 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout~36 .lut_mask = 64'hFFFFF00088888000;
defparam \A_SPW_TOP|SPW|TX|tx_dout~36 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X55_Y7_N30
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout~35 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout~35_combout  = ( \A_SPW_TOP|SPW|TX|tx_dout~8_combout  & ( \A_SPW_TOP|SPW|TX|always0~13_combout  & ( ((!\A_SPW_TOP|SPW|TX|always0~7_combout  & ((\A_SPW_TOP|SPW|TX|always0~6_combout ))) # (\A_SPW_TOP|SPW|TX|always0~7_combout  & 
// (\A_SPW_TOP|SPW|TX|tx_dout~5_combout ))) # (\A_SPW_TOP|SPW|TX|tx_dout~6_combout ) ) ) ) # ( !\A_SPW_TOP|SPW|TX|tx_dout~8_combout  & ( \A_SPW_TOP|SPW|TX|always0~13_combout  & ( ((\A_SPW_TOP|SPW|TX|tx_dout~5_combout  & \A_SPW_TOP|SPW|TX|always0~7_combout )) 
// # (\A_SPW_TOP|SPW|TX|tx_dout~6_combout ) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|tx_dout~5_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|always0~6_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|tx_dout~6_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|always0~7_combout ),
        .datae(!\A_SPW_TOP|SPW|TX|tx_dout~8_combout ),
        .dataf(!\A_SPW_TOP|SPW|TX|always0~13_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|tx_dout~35_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout~35 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout~35 .lut_mask = 64'h000000000F5F3F5F;
defparam \A_SPW_TOP|SPW|TX|tx_dout~35 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X59_Y7_N27
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout~32 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout~32_combout  = ( \A_SPW_TOP|SPW|TX|global_counter_transfer [1] & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & (!\A_SPW_TOP|SPW|TX|tx_data_in [8] & ((!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]) # 
// (!\A_SPW_TOP|SPW|TX|global_counter_transfer [2])))) ) ) # ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & (!\A_SPW_TOP|SPW|TX|tx_data_in [8] & \A_SPW_TOP|SPW|TX|global_counter_transfer [2])) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
        .datab(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
        .datac(!\A_SPW_TOP|SPW|TX|tx_data_in [8]),
        .datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|tx_dout~32_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout~32 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout~32 .lut_mask = 64'h00A000A0A080A080;
defparam \A_SPW_TOP|SPW|TX|tx_dout~32 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X54_Y7_N30
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout~41 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout~41_combout  = ( \A_SPW_TOP|SPW|TX|tx_data_in [4] & ( \A_SPW_TOP|SPW|TX|tx_data_in [0] & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & (\A_SPW_TOP|SPW|TX|global_counter_transfer [2])) # 
// (\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & ((!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]) # ((!\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & \A_SPW_TOP|SPW|TX|tx_data_in [1])))) ) ) ) # ( !\A_SPW_TOP|SPW|TX|tx_data_in [4] & ( 
// \A_SPW_TOP|SPW|TX|tx_data_in [0] & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & (\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & ((!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]) # (\A_SPW_TOP|SPW|TX|tx_data_in [1])))) # 
// (\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & (!\A_SPW_TOP|SPW|TX|global_counter_transfer [1])) ) ) ) # ( \A_SPW_TOP|SPW|TX|tx_data_in [4] & ( !\A_SPW_TOP|SPW|TX|tx_data_in [0] & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & 
// (\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & (\A_SPW_TOP|SPW|TX|tx_data_in [1] & \A_SPW_TOP|SPW|TX|global_counter_transfer [0]))) # (\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & ((!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]) # 
// ((!\A_SPW_TOP|SPW|TX|global_counter_transfer [0])))) ) ) ) # ( !\A_SPW_TOP|SPW|TX|tx_data_in [4] & ( !\A_SPW_TOP|SPW|TX|tx_data_in [0] & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & (\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & 
// (\A_SPW_TOP|SPW|TX|tx_data_in [1] & \A_SPW_TOP|SPW|TX|global_counter_transfer [0]))) # (\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & (!\A_SPW_TOP|SPW|TX|global_counter_transfer [1])) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
        .datab(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
        .datac(!\A_SPW_TOP|SPW|TX|tx_data_in [1]),
        .datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
        .datae(!\A_SPW_TOP|SPW|TX|tx_data_in [4]),
        .dataf(!\A_SPW_TOP|SPW|TX|tx_data_in [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|tx_dout~41_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout~41 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout~41 .lut_mask = 64'h4446554666467746;
defparam \A_SPW_TOP|SPW|TX|tx_dout~41 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X54_Y7_N6
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout~42 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout~42_combout  = ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & (\A_SPW_TOP|SPW|TX|tx_dout~41_combout  & (!\A_SPW_TOP|SPW|TX|tx_data_in [8] & 
// ((\A_SPW_TOP|SPW|TX|global_counter_transfer [1]) # (\A_SPW_TOP|SPW|TX|tx_data_in [2]))))) ) ) # ( \A_SPW_TOP|SPW|TX|global_counter_transfer [0] & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & (\A_SPW_TOP|SPW|TX|tx_dout~41_combout  & 
// (!\A_SPW_TOP|SPW|TX|tx_data_in [8] & ((\A_SPW_TOP|SPW|TX|global_counter_transfer [1]) # (\A_SPW_TOP|SPW|TX|tx_data_in [3]))))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
        .datab(!\A_SPW_TOP|SPW|TX|tx_dout~41_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|tx_data_in [3]),
        .datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
        .datae(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
        .dataf(!\A_SPW_TOP|SPW|TX|tx_data_in [8]),
        .datag(!\A_SPW_TOP|SPW|TX|tx_data_in [2]),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|tx_dout~42_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout~42 .extended_lut = "on";
defparam \A_SPW_TOP|SPW|TX|tx_dout~42 .lut_mask = 64'h0222022200000000;
defparam \A_SPW_TOP|SPW|TX|tx_dout~42 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X54_Y7_N3
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout~30 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout~30_combout  = ( !\A_SPW_TOP|SPW|TX|tx_data_in [8] & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & (\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & (\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & 
// \A_SPW_TOP|SPW|TX|global_counter_transfer [2]))) # (\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & (((!\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & !\A_SPW_TOP|SPW|TX|global_counter_transfer [2])))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
        .datab(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
        .datac(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
        .datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|tx_data_in [8]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|tx_dout~30_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout~30 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout~30 .lut_mask = 64'h5002500200000000;
defparam \A_SPW_TOP|SPW|TX|tx_dout~30 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X51_Y7_N3
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout~29 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout~29_combout  = ( \A_SPW_TOP|SPW|TX|always0~12_combout  & ( \A_SPW_TOP|SPW|TX|always0~13_combout  & ( (!\A_SPW_TOP|SPW|TX|LessThan6~0_combout  & (((!\A_SPW_TOP|SPW|TX|tx_dout~q )))) # (\A_SPW_TOP|SPW|TX|LessThan6~0_combout  & 
// ((!\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & (!\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & !\A_SPW_TOP|SPW|TX|tx_dout~q )) # (\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & (\A_SPW_TOP|SPW|TX|global_counter_transfer [1])))) ) ) ) # ( 
// !\A_SPW_TOP|SPW|TX|always0~12_combout  & ( \A_SPW_TOP|SPW|TX|always0~13_combout  & ( (!\A_SPW_TOP|SPW|TX|LessThan6~0_combout  & (((!\A_SPW_TOP|SPW|TX|tx_dout~q )))) # (\A_SPW_TOP|SPW|TX|LessThan6~0_combout  & ((!\A_SPW_TOP|SPW|TX|global_counter_transfer 
// [0] & (!\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & !\A_SPW_TOP|SPW|TX|tx_dout~q )) # (\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & (\A_SPW_TOP|SPW|TX|global_counter_transfer [1])))) ) ) ) # ( \A_SPW_TOP|SPW|TX|always0~12_combout  & ( 
// !\A_SPW_TOP|SPW|TX|always0~13_combout  & ( (!\A_SPW_TOP|SPW|TX|LessThan6~0_combout  & (((!\A_SPW_TOP|SPW|TX|tx_dout~q )))) # (\A_SPW_TOP|SPW|TX|LessThan6~0_combout  & (!\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & ((!\A_SPW_TOP|SPW|TX|tx_dout~q ) # 
// (\A_SPW_TOP|SPW|TX|global_counter_transfer [1])))) ) ) ) # ( !\A_SPW_TOP|SPW|TX|always0~12_combout  & ( !\A_SPW_TOP|SPW|TX|always0~13_combout  & ( !\A_SPW_TOP|SPW|TX|tx_dout~q  ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
        .datab(!\A_SPW_TOP|SPW|TX|LessThan6~0_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
        .datad(!\A_SPW_TOP|SPW|TX|tx_dout~q ),
        .datae(!\A_SPW_TOP|SPW|TX|always0~12_combout ),
        .dataf(!\A_SPW_TOP|SPW|TX|always0~13_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|tx_dout~29_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout~29 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout~29 .lut_mask = 64'hFF00EE02ED01ED01;
defparam \A_SPW_TOP|SPW|TX|tx_dout~29 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X55_Y7_N42
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout~33 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout~33_combout  = ( \A_SPW_TOP|SPW|TX|always0~13_combout  & ( (!\A_SPW_TOP|SPW|TX|always0~7_combout  & (!\A_SPW_TOP|SPW|TX|always0~6_combout  & ((!\A_SPW_TOP|SPW|TX|Equal0~2_combout ) # (\A_SPW_TOP|SPW|TX|tx_data_in [8])))) ) ) # ( 
// !\A_SPW_TOP|SPW|TX|always0~13_combout  & ( (!\A_SPW_TOP|SPW|TX|Equal0~2_combout ) # (\A_SPW_TOP|SPW|TX|tx_data_in [8]) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|always0~7_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|Equal0~2_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|tx_data_in [8]),
        .datad(!\A_SPW_TOP|SPW|TX|always0~6_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|always0~13_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|tx_dout~33_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout~33 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout~33 .lut_mask = 64'hCFCFCFCF8A008A00;
defparam \A_SPW_TOP|SPW|TX|tx_dout~33 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X53_Y7_N30
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout~40 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout~40_combout  = ( \A_SPW_TOP|SPW|TX|global_counter_transfer [3] & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & (!\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & ((!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]) # 
// (\A_SPW_TOP|SPW|TX|tx_data_in [7])))) ) ) # ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & ( (\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & (\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & \A_SPW_TOP|SPW|TX|global_counter_transfer [1])) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
        .datab(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
        .datac(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
        .datad(!\A_SPW_TOP|SPW|TX|tx_data_in [7]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|tx_dout~40_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout~40 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout~40 .lut_mask = 64'h0101010180A080A0;
defparam \A_SPW_TOP|SPW|TX|tx_dout~40 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X53_Y7_N12
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout~31 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout~31_combout  = ( \A_SPW_TOP|SPW|TX|global_counter_transfer [0] & ( \A_SPW_TOP|SPW|TX|tx_data_in [6] & ( (\A_SPW_TOP|SPW|TX|tx_dout~40_combout  & (!\A_SPW_TOP|SPW|TX|tx_data_in [8] & ((!\A_SPW_TOP|SPW|TX|global_counter_transfer 
// [1]) # (\A_SPW_TOP|SPW|TX|tx_data_in [5])))) ) ) ) # ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & ( \A_SPW_TOP|SPW|TX|tx_data_in [6] & ( (\A_SPW_TOP|SPW|TX|tx_dout~40_combout  & (!\A_SPW_TOP|SPW|TX|tx_data_in [8] & 
// ((!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]) # (\A_SPW_TOP|SPW|TX|tx_data_in [5])))) ) ) ) # ( \A_SPW_TOP|SPW|TX|global_counter_transfer [0] & ( !\A_SPW_TOP|SPW|TX|tx_data_in [6] & ( (\A_SPW_TOP|SPW|TX|tx_dout~40_combout  & 
// (!\A_SPW_TOP|SPW|TX|tx_data_in [8] & ((!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]) # (\A_SPW_TOP|SPW|TX|tx_data_in [5])))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|tx_data_in [5]),
        .datab(!\A_SPW_TOP|SPW|TX|tx_dout~40_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|tx_data_in [8]),
        .datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
        .datae(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
        .dataf(!\A_SPW_TOP|SPW|TX|tx_data_in [6]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|tx_dout~31_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout~31 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout~31 .lut_mask = 64'h0000301030103010;
defparam \A_SPW_TOP|SPW|TX|tx_dout~31 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X54_Y7_N12
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout~34 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout~34_combout  = ( \A_SPW_TOP|SPW|TX|tx_dout~33_combout  & ( \A_SPW_TOP|SPW|TX|tx_dout~31_combout  & ( (!\A_SPW_TOP|SPW|TX|tx_dout~32_combout ) # (\A_SPW_TOP|SPW|TX|tx_dout~42_combout ) ) ) ) # ( \A_SPW_TOP|SPW|TX|tx_dout~33_combout 
//  & ( !\A_SPW_TOP|SPW|TX|tx_dout~31_combout  & ( ((!\A_SPW_TOP|SPW|TX|tx_dout~32_combout  & (!\A_SPW_TOP|SPW|TX|tx_dout~30_combout  & !\A_SPW_TOP|SPW|TX|tx_dout~29_combout ))) # (\A_SPW_TOP|SPW|TX|tx_dout~42_combout ) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|tx_dout~32_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|tx_dout~42_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|tx_dout~30_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|tx_dout~29_combout ),
        .datae(!\A_SPW_TOP|SPW|TX|tx_dout~33_combout ),
        .dataf(!\A_SPW_TOP|SPW|TX|tx_dout~31_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|tx_dout~34_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout~34 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout~34 .lut_mask = 64'h0000B3330000BBBB;
defparam \A_SPW_TOP|SPW|TX|tx_dout~34 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X56_Y5_N48
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector0~9 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector0~9_combout  = ( !\A_SPW_TOP|SPW|TX|tx_dout~6_combout  & ( \A_SPW_TOP|SPW|TX|tx_data_in [8] & ( (!\A_SPW_TOP|SPW|TX|tx_data_in_0 [8] & (\A_SPW_TOP|SPW|TX|always0~7_combout  & \A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q )) ) ) ) 
// # ( !\A_SPW_TOP|SPW|TX|tx_dout~6_combout  & ( !\A_SPW_TOP|SPW|TX|tx_data_in [8] & ( (\A_SPW_TOP|SPW|TX|always0~7_combout  & (((!\A_SPW_TOP|SPW|TX|tx_data_in_0 [8] & \A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q )) # 
// (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q ))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q ),
        .datab(!\A_SPW_TOP|SPW|TX|tx_data_in_0 [8]),
        .datac(!\A_SPW_TOP|SPW|TX|always0~7_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q ),
        .datae(!\A_SPW_TOP|SPW|TX|tx_dout~6_combout ),
        .dataf(!\A_SPW_TOP|SPW|TX|tx_data_in [8]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector0~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector0~9 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector0~9 .lut_mask = 64'h050D0000000C0000;
defparam \A_SPW_TOP|SPW|TX|Selector0~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X56_Y5_N27
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector0~11 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector0~11_combout  = ( !\A_SPW_TOP|SPW|TX|tx_data_in [8] & ( (!\A_SPW_TOP|SPW|TX|always0~7_combout  & (\A_SPW_TOP|SPW|TX|always0~6_combout  & (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q  & !\A_SPW_TOP|SPW|TX|tx_dout~6_combout ))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|always0~7_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|always0~6_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q ),
        .datad(!\A_SPW_TOP|SPW|TX|tx_dout~6_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|tx_data_in [8]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector0~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector0~11 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector0~11 .lut_mask = 64'h0200020000000000;
defparam \A_SPW_TOP|SPW|TX|Selector0~11 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X56_Y5_N24
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector0~10 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector0~10_combout  = ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q  & ( (!\A_SPW_TOP|SPW|TX|always0~7_combout  & (\A_SPW_TOP|SPW|TX|always0~6_combout  & (!\A_SPW_TOP|SPW|TX|tx_data_in_0 [8] & !\A_SPW_TOP|SPW|TX|tx_dout~6_combout ))) 
// ) )

        .dataa(!\A_SPW_TOP|SPW|TX|always0~7_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|always0~6_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|tx_data_in_0 [8]),
        .datad(!\A_SPW_TOP|SPW|TX|tx_dout~6_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector0~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector0~10 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector0~10 .lut_mask = 64'h0000000020002000;
defparam \A_SPW_TOP|SPW|TX|Selector0~10 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X56_Y5_N18
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector0~12 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector0~12_combout  = ( \A_SPW_TOP|SPW|TX|Selector0~11_combout  & ( \A_SPW_TOP|SPW|TX|Selector0~10_combout  & ( (\A_SPW_TOP|SPW|TX|tx_dout~8_combout  & ((!\A_SPW_TOP|SPW|TX|Selector0~9_combout ) # (\A_SPW_TOP|SPW|TX|tx_dout~5_combout 
// ))) ) ) ) # ( !\A_SPW_TOP|SPW|TX|Selector0~11_combout  & ( \A_SPW_TOP|SPW|TX|Selector0~10_combout  & ( (\A_SPW_TOP|SPW|TX|tx_dout~8_combout  & ((!\A_SPW_TOP|SPW|TX|Selector0~9_combout ) # (\A_SPW_TOP|SPW|TX|tx_dout~5_combout ))) ) ) ) # ( 
// \A_SPW_TOP|SPW|TX|Selector0~11_combout  & ( !\A_SPW_TOP|SPW|TX|Selector0~10_combout  & ( (\A_SPW_TOP|SPW|TX|tx_dout~8_combout  & ((!\A_SPW_TOP|SPW|TX|Selector0~9_combout ) # (\A_SPW_TOP|SPW|TX|tx_dout~5_combout ))) ) ) ) # ( 
// !\A_SPW_TOP|SPW|TX|Selector0~11_combout  & ( !\A_SPW_TOP|SPW|TX|Selector0~10_combout  & ( (!\A_SPW_TOP|SPW|TX|Selector0~9_combout ) # (\A_SPW_TOP|SPW|TX|tx_dout~5_combout ) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|Selector0~9_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|tx_dout~8_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|tx_dout~5_combout ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|SPW|TX|Selector0~11_combout ),
        .dataf(!\A_SPW_TOP|SPW|TX|Selector0~10_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector0~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector0~12 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector0~12 .lut_mask = 64'hAFAF232323232323;
defparam \A_SPW_TOP|SPW|TX|Selector0~12 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X60_Y7_N15
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector0~7 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector0~7_combout  = ( \A_SPW_TOP|SPW|TX|always0~11_combout  & ( \A_SPW_TOP|SPW|TX|tx_data_in [8] & ( !\A_SPW_TOP|SPW|TX|always0~12_combout  ) ) ) # ( !\A_SPW_TOP|SPW|TX|always0~11_combout  & ( \A_SPW_TOP|SPW|TX|tx_data_in [8] & ( 
// (!\A_SPW_TOP|SPW|TX|always0~12_combout ) # (!\A_SPW_TOP|SPW|TX|always0~10_combout ) ) ) ) # ( \A_SPW_TOP|SPW|TX|always0~11_combout  & ( !\A_SPW_TOP|SPW|TX|tx_data_in [8] & ( (!\A_SPW_TOP|SPW|TX|always0~12_combout  & !\A_SPW_TOP|SPW|TX|always0~6_combout ) 
// ) ) ) # ( !\A_SPW_TOP|SPW|TX|always0~11_combout  & ( !\A_SPW_TOP|SPW|TX|tx_data_in [8] & ( (!\A_SPW_TOP|SPW|TX|always0~6_combout  & ((!\A_SPW_TOP|SPW|TX|always0~12_combout ) # (!\A_SPW_TOP|SPW|TX|always0~10_combout ))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|always0~12_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|always0~6_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|always0~10_combout ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|SPW|TX|always0~11_combout ),
        .dataf(!\A_SPW_TOP|SPW|TX|tx_data_in [8]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector0~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector0~7 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector0~7 .lut_mask = 64'hC8C88888FAFAAAAA;
defparam \A_SPW_TOP|SPW|TX|Selector0~7 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X60_Y7_N6
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector0~8 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector0~8_combout  = ( \A_SPW_TOP|SPW|TX|always0~7_combout  & ( \A_SPW_TOP|SPW|TX|Selector0~7_combout  & ( (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q  & \A_SPW_TOP|SPW|TX|tx_data_in [8]) ) ) ) # ( !\A_SPW_TOP|SPW|TX|always0~7_combout  
// & ( \A_SPW_TOP|SPW|TX|Selector0~7_combout  & ( (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q  & ((!\A_SPW_TOP|SPW|TX|tx_dout~6_combout ) # (\A_SPW_TOP|SPW|TX|tx_data_in [8]))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|tx_dout~6_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q ),
        .datac(!\A_SPW_TOP|SPW|TX|tx_data_in [8]),
        .datad(gnd),
        .datae(!\A_SPW_TOP|SPW|TX|always0~7_combout ),
        .dataf(!\A_SPW_TOP|SPW|TX|Selector0~7_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector0~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector0~8 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector0~8 .lut_mask = 64'h0000000023230303;
defparam \A_SPW_TOP|SPW|TX|Selector0~8 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X55_Y7_N33
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout~37 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout~37_combout  = ( \A_SPW_TOP|SPW|TX|tx_dout~8_combout  & ( \A_SPW_TOP|SPW|TX|always0~12_combout  & ( ((!\A_SPW_TOP|SPW|TX|always0~7_combout  & ((\A_SPW_TOP|SPW|TX|always0~6_combout ))) # (\A_SPW_TOP|SPW|TX|always0~7_combout  & 
// (\A_SPW_TOP|SPW|TX|tx_dout~5_combout ))) # (\A_SPW_TOP|SPW|TX|tx_dout~6_combout ) ) ) ) # ( !\A_SPW_TOP|SPW|TX|tx_dout~8_combout  & ( \A_SPW_TOP|SPW|TX|always0~12_combout  & ( ((\A_SPW_TOP|SPW|TX|tx_dout~5_combout  & \A_SPW_TOP|SPW|TX|always0~7_combout )) 
// # (\A_SPW_TOP|SPW|TX|tx_dout~6_combout ) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|tx_dout~5_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|always0~6_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|always0~7_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|tx_dout~6_combout ),
        .datae(!\A_SPW_TOP|SPW|TX|tx_dout~8_combout ),
        .dataf(!\A_SPW_TOP|SPW|TX|always0~12_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|tx_dout~37_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout~37 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout~37 .lut_mask = 64'h0000000005FF35FF;
defparam \A_SPW_TOP|SPW|TX|tx_dout~37 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X55_Y7_N0
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector0~13 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector0~13_combout  = ( !\A_SPW_TOP|SPW|TX|Selector0~8_combout  & ( \A_SPW_TOP|SPW|TX|tx_dout~37_combout  & ( \A_SPW_TOP|SPW|TX|Selector0~12_combout  ) ) ) # ( \A_SPW_TOP|SPW|TX|Selector0~8_combout  & ( 
// !\A_SPW_TOP|SPW|TX|tx_dout~37_combout  & ( (\A_SPW_TOP|SPW|TX|Selector0~12_combout  & ((!\A_SPW_TOP|SPW|TX|tx_dout~36_combout ) # ((!\A_SPW_TOP|SPW|TX|tx_dout~35_combout  & !\A_SPW_TOP|SPW|TX|tx_dout~34_combout )))) ) ) ) # ( 
// !\A_SPW_TOP|SPW|TX|Selector0~8_combout  & ( !\A_SPW_TOP|SPW|TX|tx_dout~37_combout  & ( \A_SPW_TOP|SPW|TX|Selector0~12_combout  ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|tx_dout~36_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|tx_dout~35_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|tx_dout~34_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|Selector0~12_combout ),
        .datae(!\A_SPW_TOP|SPW|TX|Selector0~8_combout ),
        .dataf(!\A_SPW_TOP|SPW|TX|tx_dout~37_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector0~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector0~13 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector0~13 .lut_mask = 64'h00FF00EA00FF0000;
defparam \A_SPW_TOP|SPW|TX|Selector0~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X58_Y7_N30
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector0~6 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector0~6_combout  = ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c~q  & ( (!\A_SPW_TOP|SPW|TX|Equal0~0_combout ) # ((!\A_SPW_TOP|SPW|TX|last_type.FCT~q  & \A_SPW_TOP|SPW|TX|last_type.NULL~q )) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|Equal0~0_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|last_type.FCT~q ),
        .datac(!\A_SPW_TOP|SPW|TX|last_type.NULL~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector0~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector0~6 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector0~6 .lut_mask = 64'h00000000AEAEAEAE;
defparam \A_SPW_TOP|SPW|TX|Selector0~6 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X55_Y7_N24
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector0~14 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector0~14_combout  = ( \A_SPW_TOP|SPW|TX|Selector0~13_combout  & ( \A_SPW_TOP|SPW|TX|Selector0~6_combout  & ( (((!\A_SPW_TOP|SPW|TX|Selector0~0_combout ) # (\A_SPW_TOP|SPW|TX|Selector0~5_combout )) # 
// (\A_SPW_TOP|SPW|TX|Selector0~1_combout )) # (\A_SPW_TOP|SPW|TX|Selector0~4_combout ) ) ) ) # ( !\A_SPW_TOP|SPW|TX|Selector0~13_combout  & ( \A_SPW_TOP|SPW|TX|Selector0~6_combout  ) ) # ( \A_SPW_TOP|SPW|TX|Selector0~13_combout  & ( 
// !\A_SPW_TOP|SPW|TX|Selector0~6_combout  & ( ((\A_SPW_TOP|SPW|TX|Selector0~5_combout ) # (\A_SPW_TOP|SPW|TX|Selector0~1_combout )) # (\A_SPW_TOP|SPW|TX|Selector0~4_combout ) ) ) ) # ( !\A_SPW_TOP|SPW|TX|Selector0~13_combout  & ( 
// !\A_SPW_TOP|SPW|TX|Selector0~6_combout  ) )

        .dataa(!\A_SPW_TOP|SPW|TX|Selector0~4_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|Selector0~1_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|Selector0~5_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|Selector0~0_combout ),
        .datae(!\A_SPW_TOP|SPW|TX|Selector0~13_combout ),
        .dataf(!\A_SPW_TOP|SPW|TX|Selector0~6_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector0~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector0~14 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector0~14 .lut_mask = 64'hFFFF7F7FFFFFFF7F;
defparam \A_SPW_TOP|SPW|TX|Selector0~14 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X56_Y7_N38
dffeas \A_SPW_TOP|SPW|TX|tx_dout (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|Selector0~14_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|tx_dout~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|tx_dout .power_up = "low";
// synopsys translate_on

// Location: FF_X53_Y6_N53
dffeas \A_SPW_TOP|SPW|TX|tx_dout_e (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|tx_dout~q ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|tx_dout_e~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout_e .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|tx_dout_e .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X53_Y6_N39
cyclonev_lcell_comb \m_x|always3~0 (
// Equation(s):
// \m_x|always3~0_combout  = LCELL(( \A_SPW_TOP|SPW|TX|tx_dout_e~q  & ( !\A_SPW_TOP|SPW|TX|tx_sout_e~q  ) ) # ( !\A_SPW_TOP|SPW|TX|tx_dout_e~q  & ( \A_SPW_TOP|SPW|TX|tx_sout_e~q  ) ))

        .dataa(!\A_SPW_TOP|SPW|TX|tx_sout_e~q ),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|tx_dout_e~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|always3~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|always3~0 .extended_lut = "off";
defparam \m_x|always3~0 .lut_mask = 64'h55555555AAAAAAAA;
defparam \m_x|always3~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X55_Y5_N42
cyclonev_lcell_comb \m_x|control_r[0]~feeder (
// Equation(s):
// \m_x|control_r[0]~feeder_combout  = ( \m_x|bit_c_0~q  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\m_x|bit_c_0~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|control_r[0]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|control_r[0]~feeder .extended_lut = "off";
defparam \m_x|control_r[0]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \m_x|control_r[0]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X55_Y5_N43
dffeas \m_x|control_r[0] (
        .clk(\m_x|always1~0_combout ),
        .d(\m_x|control_r[0]~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|control_r [0]),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|control_r[0] .is_wysiwyg = "true";
defparam \m_x|control_r[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X55_Y5_N13
dffeas \m_x|control_p_r[0] (
        .clk(\m_x|always2~0_combout ),
        .d(gnd),
        .asdata(\m_x|control_r [0]),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|control_p_r [0]),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|control_p_r[0] .is_wysiwyg = "true";
defparam \m_x|control_p_r[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X53_Y9_N6
cyclonev_lcell_comb \m_x|control~0 (
// Equation(s):
// \m_x|control~0_combout  = (!\m_x|ready_control_p_r~q  & ((\m_x|control [0]))) # (\m_x|ready_control_p_r~q  & (\m_x|control_p_r [0]))

        .dataa(gnd),
        .datab(!\m_x|ready_control_p_r~q ),
        .datac(!\m_x|control_p_r [0]),
        .datad(!\m_x|control [0]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|control~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|control~0 .extended_lut = "off";
defparam \m_x|control~0 .lut_mask = 64'h03CF03CF03CF03CF;
defparam \m_x|control~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X53_Y9_N59
dffeas \m_x|control[0] (
        .clk(!\m_x|always3~0_combout ),
        .d(gnd),
        .asdata(\m_x|control~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(!\m_x|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|control [0]),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|control[0] .is_wysiwyg = "true";
defparam \m_x|control[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X53_Y9_N57
cyclonev_lcell_comb \m_x|control_l_r~0 (
// Equation(s):
// \m_x|control_l_r~0_combout  = ( \m_x|control [0] & ( (\m_x|ready_control_p_r~q ) # (\m_x|control_l_r [0]) ) ) # ( !\m_x|control [0] & ( (\m_x|control_l_r [0] & !\m_x|ready_control_p_r~q ) ) )

        .dataa(!\m_x|control_l_r [0]),
        .datab(gnd),
        .datac(!\m_x|ready_control_p_r~q ),
        .datad(gnd),
        .datae(!\m_x|control [0]),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|control_l_r~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|control_l_r~0 .extended_lut = "off";
defparam \m_x|control_l_r~0 .lut_mask = 64'h50505F5F50505F5F;
defparam \m_x|control_l_r~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X53_Y9_N56
dffeas \m_x|control_l_r[0] (
        .clk(!\m_x|always3~0_combout ),
        .d(gnd),
        .asdata(\m_x|control_l_r~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(!\m_x|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|control_l_r [0]),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|control_l_r[0] .is_wysiwyg = "true";
defparam \m_x|control_l_r[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X53_Y9_N44
dffeas \m_x|info[10] (
        .clk(!\m_x|always3~0_combout ),
        .d(gnd),
        .asdata(\m_x|control_l_r [0]),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\m_x|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|info [10]),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|info[10] .is_wysiwyg = "true";
defparam \m_x|info[10] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y16_N24
cyclonev_lcell_comb \u0|data_info|read_mux_out[10] (
// Equation(s):
// \u0|data_info|read_mux_out [10] = ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & ( 
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & \m_x|info [10]) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datab(gnd),
        .datac(!\m_x|info [10]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|data_info|read_mux_out [10]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|data_info|read_mux_out[10] .extended_lut = "off";
defparam \u0|data_info|read_mux_out[10] .lut_mask = 64'h0A0A0A0A00000000;
defparam \u0|data_info|read_mux_out[10] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y16_N26
dffeas \u0|data_info|readdata[10] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|data_info|read_mux_out [10]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|data_info|readdata [10]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|data_info|readdata[10] .is_wysiwyg = "true";
defparam \u0|data_info|readdata[10] .power_up = "low";
// synopsys translate_on

// Location: FF_X30_Y16_N17
dffeas \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[10] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|data_info|readdata [10]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [10]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[10] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[10] .power_up = "low";
// synopsys translate_on

// Location: FF_X30_Y16_N14
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][10] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~10_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][10]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][10] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][10] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y16_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~10 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~10_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][10]~q  ) ) # ( 
// !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [10] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [10]),
        .datac(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][10]~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~10 .lut_mask = 64'h333333330F0F0F0F;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~10 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y16_N41
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][10] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~10_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][10]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][10] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][10] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y16_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~30 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~30_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout  & ( (!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout  & 
// ((\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][10]~q ))) # (\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout  & (\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [10])) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [10]),
        .datad(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][10]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~30_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~30 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~30 .lut_mask = 64'h0000000005AF05AF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~30 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y37_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_017|src_payload~12 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_017|src_payload~12_combout  = (\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_017|src_payload~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~12 .lut_mask = 64'h000F000F000F000F;
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~12 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y37_N5
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_017|src_payload~12_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y37_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3] = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout  & !\u0|mm_interconnect_0|cmd_mux_017|src_payload~12_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3] & 
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_017|src_payload~12_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .lut_mask = 64'h0A0A0A0A0F000F00;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y37_N53
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .power_up = "low";
// synopsys translate_on

// Location: FF_X25_Y37_N56
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y37_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout  = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  & ( 
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) # 
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((\u0|mm_interconnect_0|cmd_mux_017|src_payload~14_combout ))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_017|src_payload~14_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .lut_mask = 64'h000000000C3F0C3F;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y37_N13
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y37_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout  = SUM(( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3] ) + ( 
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3] ) + ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6  ))

        .dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .lut_mask = 64'h0000AAAA000000FF;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y37_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout  = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3] & ( 
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout  & ( (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # 
// ((\u0|hps_0|fpga_interfaces|h2f_ARADDR [3] & \u0|mm_interconnect_0|cmd_mux_017|saved_grant [1])) ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3] & ( 
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout  & ( (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3])))) # (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|hps_0|fpga_interfaces|h2f_ARADDR [3] & (\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]))) ) ) ) # ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3] & ( 
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout  & ( (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3])))) # (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|hps_0|fpga_interfaces|h2f_ARADDR [3] & (\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]))) ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3] & ( 
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout  & ( (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3])))) # (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|hps_0|fpga_interfaces|h2f_ARADDR [3] & (\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]))) ) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [3]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
        .datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .lut_mask = 64'h0F110F110F11FF11;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y37_N59
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .power_up = "low";
// synopsys translate_on

// Location: FF_X53_Y9_N4
dffeas \m_x|info[9] (
        .clk(!\m_x|always3~0_combout ),
        .d(gnd),
        .asdata(\m_x|control [3]),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\m_x|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|info [9]),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|info[9] .is_wysiwyg = "true";
defparam \m_x|info[9] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y16_N0
cyclonev_lcell_comb \u0|data_info|read_mux_out[9] (
// Equation(s):
// \u0|data_info|read_mux_out [9] = ( \m_x|info [9] & ( (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & 
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\m_x|info [9]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|data_info|read_mux_out [9]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|data_info|read_mux_out[9] .extended_lut = "off";
defparam \u0|data_info|read_mux_out[9] .lut_mask = 64'h0000000088888888;
defparam \u0|data_info|read_mux_out[9] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y16_N2
dffeas \u0|data_info|readdata[9] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|data_info|read_mux_out [9]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|data_info|readdata [9]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|data_info|readdata[9] .is_wysiwyg = "true";
defparam \u0|data_info|readdata[9] .power_up = "low";
// synopsys translate_on

// Location: FF_X30_Y16_N1
dffeas \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[9] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|data_info|readdata [9]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [9]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[9] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[9] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y16_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~9 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~9_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][9]~q  ) ) # ( 
// !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [9] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][9]~q ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [9]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~9 .lut_mask = 64'h0F0F0F0F33333333;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~9 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y16_N31
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][9] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~9_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][9]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][9] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][9] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y16_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~29 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~29_combout  = ( \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [9] & ( (\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout  & 
// ((\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout ) # (\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][9]~q ))) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [9] & ( 
// (\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][9]~q  & (\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout  & !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][9]~q ),
        .datab(!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [9]),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~29_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~29 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~29 .lut_mask = 64'h1010131310101313;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~29 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y30_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout  = ( !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~0_combout  & ( (!\u0|hps_0|fpga_interfaces|h2f_ARLEN [3] & 
// ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~2_combout  & (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~0_combout  & !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1])) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~2_combout  & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~0_combout ) # (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]))))) ) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [3]),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~2_combout ),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~0_combout ),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1 .lut_mask = 64'h00000000A2200000;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y30_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~0_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] & ( (\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~0 .lut_mask = 64'h000000000F000F00;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y30_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~1 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~1_combout  = ( !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & ( (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~1 .lut_mask = 64'h00AA00AA00000000;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y30_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~5 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~5_sumout  = SUM(( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~1_combout  ) + ( VCC ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~10  ))
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~6  = CARRY(( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~1_combout  ) + ( VCC ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~10  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~1_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~10 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~5_sumout ),
        .cout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~6 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~5 .lut_mask = 64'h0000000000000F0F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y30_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~1 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~1_sumout  = SUM(( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~0_combout  ) + ( VCC ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~6  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~6 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~1_sumout ),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~1 .lut_mask = 64'h0000000000000F0F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y30_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~1_sumout  & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout  ) ) # ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~1_sumout  & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout  & ((\u0|hps_0|fpga_interfaces|h2f_ARBURST [0]) # (\u0|hps_0|fpga_interfaces|h2f_ARBURST [1]))) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARBURST [1]),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARBURST [0]),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~1_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0 .lut_mask = 64'h70707070F0F0F0F0;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y22_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_data[82] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_data [82] = ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout  & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout  ) ) 
// ) # ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout  & ( (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout  & ( 
// \u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] ) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_010|src_data [82]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[82] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[82] .lut_mask = 64'h0F0F5F5F00005555;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[82] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y22_N26
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_010|src_data [82]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y22_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3] = ( \u0|mm_interconnect_0|cmd_mux_010|src_data [82] & ( 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3] & 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_010|src_data [82] & ( 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout  & 
// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q 
// ))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_010|src_data [82]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .lut_mask = 64'h00F300F300C000C0;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y22_N38
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y22_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & ( ((\u0|hps_0|fpga_interfaces|h2f_ARADDR [3] & 
// \u0|mm_interconnect_0|cmd_mux_010|saved_grant [1])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [3] 
// & \u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [3]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .lut_mask = 64'h005500550F5F0F5F;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y22_N14
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y20_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_data[86] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_data [86] = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] & ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [0] & ( (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]) # (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]) ) ) ) # 
// ( !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] & ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [0] & ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] & ( !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0] & ( 
// \u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
        .datad(gnd),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_010|src_data [86]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[86] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[86] .lut_mask = 64'h000033330F0F3F3F;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[86] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y22_N29
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_010|src_data [86]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y22_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_data[88] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_data [88] = ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & ( ((\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [2])) # (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & ( (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
        .datac(gnd),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_010|src_data [88]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[88] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[88] .lut_mask = 64'h0033557700335577;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[88] .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y22_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_data[87] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_data [87] = ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & ( ((\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] & \u0|mm_interconnect_0|cmd_mux_010|saved_grant [0])) # (\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]) ) ) # ( 
// !\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] & \u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]) ) )

        .dataa(gnd),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_010|src_data [87]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[87] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[87] .lut_mask = 64'h0303030303FF03FF;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[87] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y22_N29
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_010|src_data [87]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X22_Y22_N32
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_010|src_data [88]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y22_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & ( 
// (!\u0|mm_interconnect_0|cmd_mux_010|src_data [88] & (\u0|mm_interconnect_0|cmd_mux_010|src_data [87] & \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) # ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1])))) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (!\u0|mm_interconnect_0|cmd_mux_010|src_data [88] & (\u0|mm_interconnect_0|cmd_mux_010|src_data [87]))) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_010|src_data [88]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_010|src_data [87]),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .lut_mask = 64'h02F202F202020202;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y22_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout  = (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout 
//  & ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) # 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((\u0|mm_interconnect_0|cmd_mux_010|src_data [86])))))

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_010|src_data [86]),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .lut_mask = 64'h0047004700470047;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y22_N41
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .power_up = "low";
// synopsys translate_on

// Location: FF_X27_Y18_N32
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y22_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ( (!\u0|mm_interconnect_0|cmd_mux_010|src_data [86] & \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] & 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_010|src_data [86]),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .lut_mask = 64'h00F000F000CC00CC;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y22_N31
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y22_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  = ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & 
// ( \u0|mm_interconnect_0|cmd_mux_010|src_data [87] & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]) ) ) ) # ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & 
// ( !\u0|mm_interconnect_0|cmd_mux_010|src_data [87] & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & !\u0|mm_interconnect_0|cmd_mux_010|src_data [88]) ) ) ) # ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & ( !\u0|mm_interconnect_0|cmd_mux_010|src_data [87] & ( 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]))) # 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|cmd_mux_010|src_data [88])) ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_010|src_data [88]),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_010|src_data [87]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .lut_mask = 64'hFC303030CC000000;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y22_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_data[80] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_data [80] = (!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~1_combout )))) # 
// (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~0_combout ) # ((\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~1_combout 
// ))))

        .dataa(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~0_combout ),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~1_combout ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_010|src_data [80]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[80] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[80] .lut_mask = 64'h5073507350735073;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[80] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y22_N59
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_010|src_data [80]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y22_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout  = ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  
// & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ((\u0|mm_interconnect_0|cmd_mux_010|src_data [86]))) ) )

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_010|src_data [86]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .lut_mask = 64'h0000000047474747;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y22_N47
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y22_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_data[79] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_data [79] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout  & ( (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~2_combout ) ) ) 
// # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout  & ( ((\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~2_combout )) # (\u0|mm_interconnect_0|cmd_mux_010|saved_grant 
// [0]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~2_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_010|src_data [79]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[79] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[79] .lut_mask = 64'h7575757530303030;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[79] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y22_N56
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_010|src_data [79]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y22_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  = ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  
// & (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ((!\u0|mm_interconnect_0|cmd_mux_010|src_data [86]))) ) )

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_010|src_data [86]),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .lut_mask = 64'h00000000ACACACAC;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y22_N35
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y22_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout  = SUM(( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly 
// [0] ) + ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14  = CARRY(( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) 
// + ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
        .cout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .lut_mask = 64'h0000F0F000003333;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y22_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0] = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout 
//  & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg 
// [0])) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|cmd_mux_010|src_data [79]))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_010|src_data [79]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .lut_mask = 64'h00000000F3C0F3C0;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y22_N44
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y20_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout  & ( 
// ((\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [0])) # (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout  & 
// ( (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [0]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .lut_mask = 64'h005500550F5F0F5F;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y22_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout  = ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  & ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  & ( 
// (((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0] & \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout )) # 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0])) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) 
// ) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  & ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  & ( 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0] 
// & \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout )) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg 
// [0]))) ) ) ) # ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  & ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  & ( 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0] 
// & \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout )) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg 
// [0]))) ) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  & ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  & ( 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0] 
// & \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout )) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg 
// [0]))) ) ) )

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
        .datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 .lut_mask = 64'h04CC04CC04CC37FF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y22_N19
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y22_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout  = SUM(( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly 
// [1] ) + ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14  ))
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10  = CARRY(( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) 
// + ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 
//  ))

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
        .cout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .lut_mask = 64'h0000F0F000005555;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y22_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1] = ( \u0|mm_interconnect_0|cmd_mux_010|src_data [80] & ( 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1] & 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_010|src_data [80] & ( 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout  & 
// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q 
// ))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_010|src_data [80]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .lut_mask = 64'h00F300F300C000C0;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y22_N17
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y20_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout  & ( 
// ((\u0|hps_0|fpga_interfaces|h2f_ARADDR [1] & \u0|mm_interconnect_0|cmd_mux_010|saved_grant [1])) # (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout  & 
// ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [1] & \u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [1]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .lut_mask = 64'h000F000F333F333F;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y22_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout  = ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout  & ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  ) 
// ) ) # ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout  & ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1] 
// & \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout )) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]) ) 
// ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout  & ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1] 
// & \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout )) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]) ) 
// ) )

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
        .datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .lut_mask = 64'h03FF03FF00005555;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y22_N50
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y22_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout  = SUM(( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly 
// [2] ) + ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10  ))
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6  = CARRY(( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) 
// + ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 
//  ))

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
        .cout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .lut_mask = 64'h0000F0F000005555;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y22_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout  = SUM(( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly 
// [3] ) + ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3] ) + ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6  ))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .lut_mask = 64'h0000F0F000003333;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y22_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout  & 
// ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg 
// [3])) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]))) # 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout 
// )))) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout  & ( 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3])) 
// # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .lut_mask = 64'h0C3F0C3F4C7F4C7F;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y18_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3]~feeder_combout  = ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y18_N53
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y14_N21
cyclonev_lcell_comb \u0|write_data_fifo_tx|readdata[8] (
// Equation(s):
// \u0|write_data_fifo_tx|readdata [8] = ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( \u0|write_data_fifo_tx|data_out [8] & ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] ) ) )

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .dataf(!\u0|write_data_fifo_tx|data_out [8]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|write_data_fifo_tx|readdata [8]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|write_data_fifo_tx|readdata[8] .extended_lut = "off";
defparam \u0|write_data_fifo_tx|readdata[8] .lut_mask = 64'h00000000AAAA0000;
defparam \u0|write_data_fifo_tx|readdata[8] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y14_N23
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre[8] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|write_data_fifo_tx|readdata [8]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [8]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre[8] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre[8] .power_up = "low";
// synopsys translate_on

// Location: FF_X28_Y15_N23
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][8] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][8] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y15_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~8 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~8_combout  = (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1] & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [8])) # 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1] & ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][8]~q )))

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [8]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][8]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~8 .lut_mask = 64'h505F505F505F505F;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~8 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y17_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always0~0_combout  = ( \u0|mm_interconnect_0|rsp_demux_010|src0_valid~0_combout  & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [0]) # 
// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|read~0_combout  & \u0|hps_0|fpga_interfaces|h2f_BREADY [0])) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_010|src0_valid~0_combout  & ( 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [0]) # ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|read~0_combout  & \u0|hps_0|fpga_interfaces|h2f_RREADY [0])) ) )

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [0]),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|read~0_combout ),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_BREADY [0]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_010|src0_valid~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always0~0 .lut_mask = 64'hAAEEAAEEAEAEAEAE;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y15_N35
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][8] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~8_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][8] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][8] .power_up = "low";
// synopsys translate_on

// Location: FF_X27_Y16_N2
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][8] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~8_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][8] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][8] .power_up = "low";
// synopsys translate_on

// Location: FF_X13_Y36_N14
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y36_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_003|src_payload~15 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_003|src_payload~15_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & ( \u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_003|src_payload~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~15 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~15 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y36_N23
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_003|src_payload~15_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y36_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_003|src_payload~16 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_003|src_payload~16_combout  = ( \u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_003|src_payload~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~16 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~16 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y36_N47
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_003|src_payload~16_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y36_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_003|src_payload~15_combout  & ( 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1])) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_003|src_payload~15_combout  & ( 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & 
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]))) # (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((\u0|mm_interconnect_0|cmd_mux_003|src_payload~16_combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_003|src_payload~16_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_003|src_payload~15_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .lut_mask = 64'h083B083B08080808;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y36_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_003|src_payload~14 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_003|src_payload~14_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] & ( \u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_003|src_payload~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~14 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~14 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y36_N14
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_003|src_payload~14_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y36_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout  = (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  & 
// ((!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) # 
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|cmd_mux_003|src_payload~14_combout )))))

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_003|src_payload~14_combout ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .lut_mask = 64'h4540454045404540;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y36_N4
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y34_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_003|src_payload~17 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_003|src_payload~17_combout  = ( \u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~1_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_003|src_payload~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~17 .lut_mask = 64'h000000000000FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~17 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y34_N56
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_003|src_payload~17_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y34_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1] = ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout  & ( 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1])) # 
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|cmd_mux_003|src_payload~17_combout ))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_003|src_payload~17_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .lut_mask = 64'h00000000F3C0F3C0;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y34_N32
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y34_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout  = ( !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( (\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [1] & !\u0|hps_0|fpga_interfaces|h2f_ARSIZE 
// [1])) ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [1]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
        .datad(gnd),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .lut_mask = 64'h0000000010100000;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y36_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  = ( \u0|mm_interconnect_0|cmd_mux_003|src_payload~16_combout  & ( 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1])) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_003|src_payload~16_combout  & ( 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]))) # (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((!\u0|mm_interconnect_0|cmd_mux_003|src_payload~15_combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_003|src_payload~15_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_003|src_payload~16_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .lut_mask = 64'hB380B38080808080;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y36_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  & \u0|mm_interconnect_0|cmd_mux_003|src_payload~14_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  & 
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_003|src_payload~14_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .lut_mask = 64'h1111111105050505;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y36_N25
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y36_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  = ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # 
// ((!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ) # (\u0|mm_interconnect_0|cmd_mux_003|src_payload~14_combout )) ) ) # ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ) # 
// ((\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & \u0|mm_interconnect_0|cmd_mux_003|src_payload~14_combout )) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_003|src_payload~14_combout ),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .lut_mask = 64'hFF03FF03FFCFFFCF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y36_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout  = ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .lut_mask = 64'hFFFFFFFF00000000;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y36_N35
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y36_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_003|src_payload~18 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_003|src_payload~18_combout  = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~2_combout  & ( \u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_003|src_payload~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~18 .lut_mask = 64'h3333333300000000;
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~18 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y36_N50
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_003|src_payload~18_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y36_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0] = ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  & ( 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0])) # 
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|cmd_mux_003|src_payload~18_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_003|src_payload~18_combout ),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .lut_mask = 64'h00000000AAF0AAF0;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y36_N59
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y36_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout  = SUM(( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) + ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14  = CARRY(( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) + ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
        .cout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y36_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  = ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// (((\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0] & (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ))) # 
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0])) ) ) # ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// (\u0|hps_0|fpga_interfaces|h2f_ARADDR [0] & (((!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  & ((\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1])))))) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [0]),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
        .datae(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
        .datag(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .extended_lut = "on";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .lut_mask = 64'h333F0000333F5050;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y36_N7
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y36_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout  = SUM(( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14  ))
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10  = CARRY(( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14  ))

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
        .cout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .lut_mask = 64'h0000AAAA000000FF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y34_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout  & ( 
// ((!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]) # 
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1])))) # (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout 
// ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout  & ( ((!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1])) # (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ) 
// ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .lut_mask = 64'h0CFF0CFF4CFF4CFF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y34_N34
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y36_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout  = SUM(( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10  ))
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6  = CARRY(( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10  ))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
        .cout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .lut_mask = 64'h0000F0F000003333;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y36_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_003|src_payload~13 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_003|src_payload~13_combout  = (\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_003|src_payload~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~13 .lut_mask = 64'h3030303030303030;
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~13 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y36_N53
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_003|src_payload~13_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y36_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2] = ( \u0|mm_interconnect_0|cmd_mux_003|src_payload~13_combout  & ( 
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout  & (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] & 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_003|src_payload~13_combout  & ( 
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout  & ((!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]) # 
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_003|src_payload~13_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .lut_mask = 64'h5055505550005000;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y36_N25
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y36_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( (\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [2]) ) ) ) # ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] ) ) # ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( 
// (\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [2]) ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout  & 
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]) ) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [2]),
        .datae(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .lut_mask = 64'h05050033FFFF0033;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y36_N5
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y36_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_003|src_payload~12 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_003|src_payload~12_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout  & ( \u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_003|src_payload~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~12 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~12 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y36_N44
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_003|src_payload~12_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y36_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3] = ( \u0|mm_interconnect_0|cmd_mux_003|src_payload~12_combout  & ( 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3] & 
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_003|src_payload~12_combout  & ( 
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout  & ((!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]) # 
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_003|src_payload~12_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .lut_mask = 64'h00F300F300C000C0;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y36_N29
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y36_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  & \u0|mm_interconnect_0|cmd_mux_003|src_payload~14_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  & 
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_003|src_payload~14_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .lut_mask = 64'h1111111105050505;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y36_N2
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .power_up = "low";
// synopsys translate_on

// Location: FF_X13_Y36_N1
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y36_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout  = SUM(( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3] ) + ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3] ) + ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6  ))

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .lut_mask = 64'h0000AAAA000000FF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y36_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// \u0|hps_0|fpga_interfaces|h2f_ARADDR [3] & ( \u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// \u0|hps_0|fpga_interfaces|h2f_ARADDR [3] & ( ((\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3] & 
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout )) # (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]) ) ) ) # ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [3] & ( 
// ((\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3] & \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout )) # 
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]) ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
        .datae(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .lut_mask = 64'h0F3F00000F3F5555;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y36_N17
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y2_N36
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|dta_timec_p[8]~feeder (
// Equation(s):
// \A_SPW_TOP|SPW|RX|dta_timec_p[8]~feeder_combout  = ( \A_SPW_TOP|SPW|RX|dta_timec [8] )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|dta_timec [8]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|dta_timec_p[8]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[8]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[8]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[8]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y2_N37
dffeas \A_SPW_TOP|SPW|RX|dta_timec_p[8] (
        .clk(\A_SPW_TOP|SPW|RX|ready_data_p~combout ),
        .d(\A_SPW_TOP|SPW|RX|dta_timec_p[8]~feeder_combout ),
        .asdata(vcc),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|dta_timec_p [8]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[8] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y2_N30
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|rx_data_flag~8 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|rx_data_flag~8_combout  = ( !\A_SPW_TOP|SPW|RX|ready_control_p_r~q  & ( ((!\A_SPW_TOP|SPW|RX|data~0_combout  & (\A_SPW_TOP|SPW|RX|dta_timec_p [8])) # (\A_SPW_TOP|SPW|RX|data~0_combout  & (((\A_SPW_TOP|SPW|RX|rx_data_flag [8]))))) ) ) # ( 
// \A_SPW_TOP|SPW|RX|ready_control_p_r~q  & ( (((\A_SPW_TOP|SPW|RX|control_p_r [2] & (!\A_SPW_TOP|SPW|RX|control_p_r [1] $ (!\A_SPW_TOP|SPW|RX|control_p_r [0])))) # (\A_SPW_TOP|SPW|RX|rx_data_flag [8])) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|control_p_r [1]),
        .datab(!\A_SPW_TOP|SPW|RX|dta_timec_p [8]),
        .datac(!\A_SPW_TOP|SPW|RX|control_p_r [2]),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .datae(!\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),
        .dataf(!\A_SPW_TOP|SPW|RX|control_p_r [0]),
        .datag(!\A_SPW_TOP|SPW|RX|data~0_combout ),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|rx_data_flag~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_data_flag~8 .extended_lut = "on";
defparam \A_SPW_TOP|SPW|RX|rx_data_flag~8 .lut_mask = 64'h303F05FF303F0AFF;
defparam \A_SPW_TOP|SPW|RX|rx_data_flag~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y2_N32
dffeas \A_SPW_TOP|SPW|RX|rx_data_flag[8] (
        .clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(\A_SPW_TOP|SPW|RX|rx_data_flag~8_combout ),
        .asdata(vcc),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(!\A_SPW_TOP|SPW|RX|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_data_flag[8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|rx_data_flag[8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X36_Y9_N51
cyclonev_lcell_comb \A_SPW_TOP|rx_data|wr_ptr[0]~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|wr_ptr[0]~0_combout  = ( !\A_SPW_TOP|rx_data|wr_ptr [0] )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|wr_ptr[0]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|wr_ptr[0]~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|wr_ptr[0]~0 .lut_mask = 64'hFFFFFFFF00000000;
defparam \A_SPW_TOP|rx_data|wr_ptr[0]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X36_Y9_N41
dffeas \A_SPW_TOP|rx_data|wr_ptr[0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|wr_ptr[0]~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|rx_data|state_data_write.10~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|wr_ptr [0]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|wr_ptr[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|wr_ptr[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X36_Y9_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Add1~2 (
// Equation(s):
// \A_SPW_TOP|rx_data|Add1~2_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [0] & ( !\A_SPW_TOP|rx_data|wr_ptr [1] ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [0] & ( \A_SPW_TOP|rx_data|wr_ptr [1] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Add1~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Add1~2 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Add1~2 .lut_mask = 64'h0F0F0F0FF0F0F0F0;
defparam \A_SPW_TOP|rx_data|Add1~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X36_Y9_N59
dffeas \A_SPW_TOP|rx_data|wr_ptr[1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Add1~2_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|rx_data|state_data_write.10~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|wr_ptr [1]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|wr_ptr[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|wr_ptr[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X36_Y9_N9
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Add1~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Add1~1_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [0] & ( !\A_SPW_TOP|rx_data|wr_ptr [1] $ (!\A_SPW_TOP|rx_data|wr_ptr [2]) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [0] & ( \A_SPW_TOP|rx_data|wr_ptr [2] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Add1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Add1~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Add1~1 .lut_mask = 64'h00FF00FF0FF00FF0;
defparam \A_SPW_TOP|rx_data|Add1~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X36_Y9_N47
dffeas \A_SPW_TOP|rx_data|wr_ptr[2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Add1~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|rx_data|state_data_write.10~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|wr_ptr [2]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|wr_ptr[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|wr_ptr[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X36_Y9_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Add1~3 (
// Equation(s):
// \A_SPW_TOP|rx_data|Add1~3_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [1] & ( \A_SPW_TOP|rx_data|wr_ptr [0] & ( !\A_SPW_TOP|rx_data|wr_ptr [3] $ (!\A_SPW_TOP|rx_data|wr_ptr [2]) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [1] & ( \A_SPW_TOP|rx_data|wr_ptr [0] & ( 
// \A_SPW_TOP|rx_data|wr_ptr [3] ) ) ) # ( \A_SPW_TOP|rx_data|wr_ptr [1] & ( !\A_SPW_TOP|rx_data|wr_ptr [0] & ( \A_SPW_TOP|rx_data|wr_ptr [3] ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [1] & ( !\A_SPW_TOP|rx_data|wr_ptr [0] & ( \A_SPW_TOP|rx_data|wr_ptr [3] ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datac(gnd),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Add1~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Add1~3 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Add1~3 .lut_mask = 64'h33333333333333CC;
defparam \A_SPW_TOP|rx_data|Add1~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X36_Y9_N17
dffeas \A_SPW_TOP|rx_data|wr_ptr[3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Add1~3_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|rx_data|state_data_write.10~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|wr_ptr [3]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|wr_ptr[3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|wr_ptr[3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X32_Y9_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Add1~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Add1~0_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [1] & ( !\A_SPW_TOP|rx_data|wr_ptr [4] $ (((!\A_SPW_TOP|rx_data|wr_ptr [3]) # ((!\A_SPW_TOP|rx_data|wr_ptr [0]) # (!\A_SPW_TOP|rx_data|wr_ptr [2])))) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [1] & 
// ( \A_SPW_TOP|rx_data|wr_ptr [4] ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Add1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Add1~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Add1~0 .lut_mask = 64'h00FF00FF01FE01FE;
defparam \A_SPW_TOP|rx_data|Add1~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X36_Y9_N20
dffeas \A_SPW_TOP|rx_data|wr_ptr[4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Add1~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|rx_data|state_data_write.10~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|wr_ptr [4]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|wr_ptr[4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|wr_ptr[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X36_Y9_N21
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Add1~4 (
// Equation(s):
// \A_SPW_TOP|rx_data|Add1~4_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [2] & ( \A_SPW_TOP|rx_data|wr_ptr [3] & ( !\A_SPW_TOP|rx_data|wr_ptr [5] $ (((!\A_SPW_TOP|rx_data|wr_ptr [4]) # ((!\A_SPW_TOP|rx_data|wr_ptr [1]) # (!\A_SPW_TOP|rx_data|wr_ptr [0])))) ) ) ) 
// # ( !\A_SPW_TOP|rx_data|wr_ptr [2] & ( \A_SPW_TOP|rx_data|wr_ptr [3] & ( \A_SPW_TOP|rx_data|wr_ptr [5] ) ) ) # ( \A_SPW_TOP|rx_data|wr_ptr [2] & ( !\A_SPW_TOP|rx_data|wr_ptr [3] & ( \A_SPW_TOP|rx_data|wr_ptr [5] ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [2] & 
// ( !\A_SPW_TOP|rx_data|wr_ptr [3] & ( \A_SPW_TOP|rx_data|wr_ptr [5] ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Add1~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Add1~4 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Add1~4 .lut_mask = 64'h00FF00FF00FF01FE;
defparam \A_SPW_TOP|rx_data|Add1~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X36_Y9_N29
dffeas \A_SPW_TOP|rx_data|wr_ptr[5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Add1~4_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|rx_data|state_data_write.10~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|wr_ptr [5]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|wr_ptr[5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|wr_ptr[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X33_Y4_N51
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Decoder0~52 (
// Equation(s):
// \A_SPW_TOP|rx_data|Decoder0~52_combout  = ( !\A_SPW_TOP|rx_data|wr_ptr [2] & ( \A_SPW_TOP|rx_data|wr_ptr [0] & ( (\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|wr_ptr [3] & (!\A_SPW_TOP|rx_data|wr_ptr [5] & !\A_SPW_TOP|rx_data|wr_ptr [1]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Decoder0~52_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Decoder0~52 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Decoder0~52 .lut_mask = 64'h0000000010000000;
defparam \A_SPW_TOP|rx_data|Decoder0~52 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X33_Y4_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector244~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector244~0_combout  = ( \A_SPW_TOP|rx_data|Decoder0~52_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|rx_data|state_data_write.01~q ) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Decoder0~52_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector244~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector244~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector244~0 .lut_mask = 64'h00000000DDDDDDDD;
defparam \A_SPW_TOP|rx_data|Selector244~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y4_N21
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Decoder0~44 (
// Equation(s):
// \A_SPW_TOP|rx_data|Decoder0~44_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [1] & ( !\A_SPW_TOP|rx_data|wr_ptr [0] & ( (\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|wr_ptr [2] & (!\A_SPW_TOP|rx_data|wr_ptr [5] & !\A_SPW_TOP|rx_data|wr_ptr [4]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Decoder0~44_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Decoder0~44 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Decoder0~44 .lut_mask = 64'h0000100000000000;
defparam \A_SPW_TOP|rx_data|Decoder0~44 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X31_Y4_N15
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector145~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector145~0_combout  = ( \A_SPW_TOP|rx_data|Decoder0~44_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|rx_data|state_data_write.01~q ) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .datab(gnd),
        .datac(gnd),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Decoder0~44_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector145~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector145~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector145~0 .lut_mask = 64'h00000000FF55FF55;
defparam \A_SPW_TOP|rx_data|Selector145~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X32_Y5_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector145~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector145~1_combout  = ( \A_SPW_TOP|rx_data|Selector145~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [8]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux0~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector145~0_combout  & ( \A_SPW_TOP|rx_data|mem[14][8]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .datab(!\A_SPW_TOP|rx_data|mem[14][8]~q ),
        .datac(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(!\A_SPW_TOP|rx_data|Selector145~0_combout ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector145~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector145~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector145~1 .lut_mask = 64'h33330F5533330F55;
defparam \A_SPW_TOP|rx_data|Selector145~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X32_Y5_N11
dffeas \A_SPW_TOP|rx_data|mem[14][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector145~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[14][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[14][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[14][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X33_Y4_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Decoder0~51 (
// Equation(s):
// \A_SPW_TOP|rx_data|Decoder0~51_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [1] & ( !\A_SPW_TOP|rx_data|wr_ptr [5] & ( (\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|wr_ptr [2] & !\A_SPW_TOP|rx_data|wr_ptr [0]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Decoder0~51_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Decoder0~51 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Decoder0~51 .lut_mask = 64'h0000010000000000;
defparam \A_SPW_TOP|rx_data|Decoder0~51 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X33_Y4_N15
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector289~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector289~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.01~q  & ( \A_SPW_TOP|rx_data|Decoder0~51_combout  ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.01~q  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// \A_SPW_TOP|rx_data|Decoder0~51_combout ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(gnd),
        .datad(!\A_SPW_TOP|rx_data|Decoder0~51_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector289~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector289~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector289~0 .lut_mask = 64'h00CC00CC00FF00FF;
defparam \A_SPW_TOP|rx_data|Selector289~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X36_Y9_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector289~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector289~1_combout  = ( \A_SPW_TOP|rx_data|mem[30][8]~q  & ( (!\A_SPW_TOP|rx_data|Selector289~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [8])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux0~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[30][8]~q  & ( (\A_SPW_TOP|rx_data|Selector289~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [8])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux0~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .datad(!\A_SPW_TOP|rx_data|Selector289~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[30][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector289~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector289~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector289~1 .lut_mask = 64'h00470047FF47FF47;
defparam \A_SPW_TOP|rx_data|Selector289~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X35_Y9_N59
dffeas \A_SPW_TOP|rx_data|mem[30][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector289~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[30][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[30][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[30][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y8_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Decoder0~28 (
// Equation(s):
// \A_SPW_TOP|rx_data|Decoder0~28_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [1] & ( !\A_SPW_TOP|rx_data|wr_ptr [5] & ( (\A_SPW_TOP|rx_data|wr_ptr [2] & (!\A_SPW_TOP|rx_data|wr_ptr [3] & (!\A_SPW_TOP|rx_data|wr_ptr [0] & \A_SPW_TOP|rx_data|wr_ptr [4]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Decoder0~28_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Decoder0~28 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Decoder0~28 .lut_mask = 64'h0000004000000000;
defparam \A_SPW_TOP|rx_data|Decoder0~28 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y8_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector217~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector217~0_combout  = (\A_SPW_TOP|rx_data|Decoder0~28_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|rx_data|state_data_write.01~q )))

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Decoder0~28_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector217~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector217~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector217~0 .lut_mask = 64'h0D0D0D0D0D0D0D0D;
defparam \A_SPW_TOP|rx_data|Selector217~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X33_Y7_N9
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector217~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector217~1_combout  = ( \A_SPW_TOP|rx_data|Mux0~20_combout  & ( (!\A_SPW_TOP|rx_data|Selector217~0_combout  & (((\A_SPW_TOP|rx_data|mem[22][8]~q )))) # (\A_SPW_TOP|rx_data|Selector217~0_combout  & (((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [8])) # (\A_SPW_TOP|rx_data|state_data_write.00~q ))) ) ) # ( !\A_SPW_TOP|rx_data|Mux0~20_combout  & ( (!\A_SPW_TOP|rx_data|Selector217~0_combout  & (((\A_SPW_TOP|rx_data|mem[22][8]~q )))) # (\A_SPW_TOP|rx_data|Selector217~0_combout  & 
// (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [8])))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[22][8]~q ),
        .datac(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .datad(!\A_SPW_TOP|rx_data|Selector217~0_combout ),
        .datae(!\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector217~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector217~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector217~1 .lut_mask = 64'h330A335F330A335F;
defparam \A_SPW_TOP|rx_data|Selector217~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X33_Y7_N17
dffeas \A_SPW_TOP|rx_data|mem[22][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector217~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[22][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[22][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[22][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y7_N45
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Decoder0~12 (
// Equation(s):
// \A_SPW_TOP|rx_data|Decoder0~12_combout  = ( !\A_SPW_TOP|rx_data|wr_ptr [5] & ( \A_SPW_TOP|rx_data|wr_ptr [2] & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & (!\A_SPW_TOP|rx_data|wr_ptr [4] & (!\A_SPW_TOP|rx_data|wr_ptr [3] & \A_SPW_TOP|rx_data|wr_ptr [1]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Decoder0~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Decoder0~12 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Decoder0~12 .lut_mask = 64'h0000000000800000;
defparam \A_SPW_TOP|rx_data|Decoder0~12 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X31_Y7_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector73~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector73~0_combout  = (\A_SPW_TOP|rx_data|Decoder0~12_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|rx_data|state_data_write.01~q )))

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .datad(!\A_SPW_TOP|rx_data|Decoder0~12_combout ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector73~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector73~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector73~0 .lut_mask = 64'h00AF00AF00AF00AF;
defparam \A_SPW_TOP|rx_data|Selector73~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X35_Y9_N45
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector73~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector73~1_combout  = ( \A_SPW_TOP|rx_data|Selector73~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [8])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux0~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector73~0_combout  & ( \A_SPW_TOP|rx_data|mem[6][8]~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[6][8]~q ),
        .datad(!\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector73~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector73~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector73~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector73~1 .lut_mask = 64'h0F0F0F0F44774477;
defparam \A_SPW_TOP|rx_data|Selector73~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X35_Y9_N17
dffeas \A_SPW_TOP|rx_data|mem[6][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector73~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[6][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[6][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[6][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X35_Y9_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux0~7 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux0~7_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [3] & ( \A_SPW_TOP|rx_data|mem[6][8]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[14][8]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|mem[30][8]~q ))) ) ) 
// ) # ( !\A_SPW_TOP|rx_data|wr_ptr [3] & ( \A_SPW_TOP|rx_data|mem[6][8]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [4]) # (\A_SPW_TOP|rx_data|mem[22][8]~q ) ) ) ) # ( \A_SPW_TOP|rx_data|wr_ptr [3] & ( !\A_SPW_TOP|rx_data|mem[6][8]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr 
// [4] & (\A_SPW_TOP|rx_data|mem[14][8]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|mem[30][8]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [3] & ( !\A_SPW_TOP|rx_data|mem[6][8]~q  & ( (\A_SPW_TOP|rx_data|wr_ptr [4] & 
// \A_SPW_TOP|rx_data|mem[22][8]~q ) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[14][8]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[30][8]~q ),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datad(!\A_SPW_TOP|rx_data|mem[22][8]~q ),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .dataf(!\A_SPW_TOP|rx_data|mem[6][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux0~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux0~7 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux0~7 .lut_mask = 64'h000F5353F0FF5353;
defparam \A_SPW_TOP|rx_data|Mux0~7 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X32_Y9_N15
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Decoder0~49 (
// Equation(s):
// \A_SPW_TOP|rx_data|Decoder0~49_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [3] & ( \A_SPW_TOP|rx_data|wr_ptr [1] & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|wr_ptr [4] & (!\A_SPW_TOP|rx_data|wr_ptr [0] & !\A_SPW_TOP|rx_data|wr_ptr [5]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Decoder0~49_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Decoder0~49 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Decoder0~49 .lut_mask = 64'h0000000000002000;
defparam \A_SPW_TOP|rx_data|Decoder0~49 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X32_Y9_N33
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector253~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector253~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.01~q  & ( \A_SPW_TOP|rx_data|Decoder0~49_combout  ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.01~q  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// \A_SPW_TOP|rx_data|Decoder0~49_combout ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Decoder0~49_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector253~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector253~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector253~0 .lut_mask = 64'h0C0C0C0C0F0F0F0F;
defparam \A_SPW_TOP|rx_data|Selector253~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y9_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector253~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector253~1_combout  = ( \A_SPW_TOP|rx_data|Selector253~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [8])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux0~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector253~0_combout  & ( \A_SPW_TOP|rx_data|mem[26][8]~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[26][8]~q ),
        .datad(!\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector253~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector253~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector253~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector253~1 .lut_mask = 64'h0F0F0F0F44774477;
defparam \A_SPW_TOP|rx_data|Selector253~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y9_N38
dffeas \A_SPW_TOP|rx_data|mem[26][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector253~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[26][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[26][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[26][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X33_Y4_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Decoder0~24 (
// Equation(s):
// \A_SPW_TOP|rx_data|Decoder0~24_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [1] & ( !\A_SPW_TOP|rx_data|wr_ptr [2] & ( (\A_SPW_TOP|rx_data|wr_ptr [4] & (!\A_SPW_TOP|rx_data|wr_ptr [5] & (!\A_SPW_TOP|rx_data|wr_ptr [0] & !\A_SPW_TOP|rx_data|wr_ptr [3]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Decoder0~24_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Decoder0~24 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Decoder0~24 .lut_mask = 64'h0000400000000000;
defparam \A_SPW_TOP|rx_data|Decoder0~24 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X33_Y4_N21
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector181~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector181~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (\A_SPW_TOP|rx_data|state_data_write.01~q  & \A_SPW_TOP|rx_data|Decoder0~24_combout ) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( 
// \A_SPW_TOP|rx_data|Decoder0~24_combout  ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|rx_data|Decoder0~24_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector181~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector181~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector181~0 .lut_mask = 64'h0F0F0F0F05050505;
defparam \A_SPW_TOP|rx_data|Selector181~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y9_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector181~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector181~1_combout  = ( \A_SPW_TOP|rx_data|mem[18][8]~q  & ( (!\A_SPW_TOP|rx_data|Selector181~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [8])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux0~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[18][8]~q  & ( (\A_SPW_TOP|rx_data|Selector181~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [8])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux0~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Selector181~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[18][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector181~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector181~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector181~1 .lut_mask = 64'h04070407F4F7F4F7;
defparam \A_SPW_TOP|rx_data|Selector181~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y9_N11
dffeas \A_SPW_TOP|rx_data|mem[18][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector181~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[18][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[18][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[18][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y9_N15
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Decoder0~40 (
// Equation(s):
// \A_SPW_TOP|rx_data|Decoder0~40_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [1] & ( !\A_SPW_TOP|rx_data|wr_ptr [5] & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|wr_ptr [3] & (!\A_SPW_TOP|rx_data|wr_ptr [4] & !\A_SPW_TOP|rx_data|wr_ptr [2]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Decoder0~40_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Decoder0~40 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Decoder0~40 .lut_mask = 64'h0000200000000000;
defparam \A_SPW_TOP|rx_data|Decoder0~40 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y9_N57
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector109~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector109~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.01~q  & ( \A_SPW_TOP|rx_data|Decoder0~40_combout  ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.01~q  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// \A_SPW_TOP|rx_data|Decoder0~40_combout ) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|rx_data|Decoder0~40_combout ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector109~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector109~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector109~0 .lut_mask = 64'h0A0A0F0F0A0A0F0F;
defparam \A_SPW_TOP|rx_data|Selector109~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y9_N27
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector109~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector109~1_combout  = ( \A_SPW_TOP|rx_data|mem[10][8]~q  & ( (!\A_SPW_TOP|rx_data|Selector109~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [8])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux0~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[10][8]~q  & ( (\A_SPW_TOP|rx_data|Selector109~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [8])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux0~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .datad(!\A_SPW_TOP|rx_data|Selector109~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[10][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector109~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector109~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector109~1 .lut_mask = 64'h00470047FF47FF47;
defparam \A_SPW_TOP|rx_data|Selector109~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y9_N44
dffeas \A_SPW_TOP|rx_data|mem[10][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector109~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[10][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[10][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[10][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X33_Y4_N27
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Decoder0~8 (
// Equation(s):
// \A_SPW_TOP|rx_data|Decoder0~8_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [1] & ( !\A_SPW_TOP|rx_data|wr_ptr [0] & ( (!\A_SPW_TOP|rx_data|wr_ptr [4] & (!\A_SPW_TOP|rx_data|wr_ptr [3] & (!\A_SPW_TOP|rx_data|wr_ptr [5] & !\A_SPW_TOP|rx_data|wr_ptr [2]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Decoder0~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Decoder0~8 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Decoder0~8 .lut_mask = 64'h0000800000000000;
defparam \A_SPW_TOP|rx_data|Decoder0~8 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X33_Y4_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector37~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector37~0_combout  = (\A_SPW_TOP|rx_data|Decoder0~8_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|rx_data|state_data_write.01~q )))

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Decoder0~8_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector37~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector37~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector37~0 .lut_mask = 64'h0D0D0D0D0D0D0D0D;
defparam \A_SPW_TOP|rx_data|Selector37~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y9_N15
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector37~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector37~1_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector37~0_combout  & ((\A_SPW_TOP|rx_data|mem[2][8]~q ))) # (\A_SPW_TOP|rx_data|Selector37~0_combout  & (\A_SPW_TOP|rx_data|Mux0~20_combout 
// )) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector37~0_combout  & ((\A_SPW_TOP|rx_data|mem[2][8]~q ))) # (\A_SPW_TOP|rx_data|Selector37~0_combout  & (\A_SPW_TOP|SPW|RX|rx_data_flag [8])) ) )

        .dataa(!\A_SPW_TOP|rx_data|Selector37~0_combout ),
        .datab(!\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .datac(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .datad(!\A_SPW_TOP|rx_data|mem[2][8]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector37~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector37~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector37~1 .lut_mask = 64'h05AF05AF11BB11BB;
defparam \A_SPW_TOP|rx_data|Selector37~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y9_N50
dffeas \A_SPW_TOP|rx_data|mem[2][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector37~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[2][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[2][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[2][8] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y9_N45
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux0~5 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux0~5_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [4] & ( \A_SPW_TOP|rx_data|wr_ptr [3] & ( \A_SPW_TOP|rx_data|mem[26][8]~q  ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [4] & ( \A_SPW_TOP|rx_data|wr_ptr [3] & ( \A_SPW_TOP|rx_data|mem[10][8]~q  ) ) 
// ) # ( \A_SPW_TOP|rx_data|wr_ptr [4] & ( !\A_SPW_TOP|rx_data|wr_ptr [3] & ( \A_SPW_TOP|rx_data|mem[18][8]~q  ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [4] & ( !\A_SPW_TOP|rx_data|wr_ptr [3] & ( \A_SPW_TOP|rx_data|mem[2][8]~q  ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[26][8]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[18][8]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[10][8]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[2][8]~q ),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux0~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux0~5 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux0~5 .lut_mask = 64'h00FF33330F0F5555;
defparam \A_SPW_TOP|rx_data|Mux0~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X31_Y7_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Decoder0~10 (
// Equation(s):
// \A_SPW_TOP|rx_data|Decoder0~10_combout  = ( !\A_SPW_TOP|rx_data|wr_ptr [2] & ( \A_SPW_TOP|rx_data|wr_ptr [5] & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & (!\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|wr_ptr [1] & !\A_SPW_TOP|rx_data|wr_ptr [3]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Decoder0~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Decoder0~10 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Decoder0~10 .lut_mask = 64'h0000000008000000;
defparam \A_SPW_TOP|rx_data|Decoder0~10 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y7_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector325~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector325~0_combout  = (\A_SPW_TOP|rx_data|Decoder0~10_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|rx_data|state_data_write.01~q )))

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .datad(!\A_SPW_TOP|rx_data|Decoder0~10_combout ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector325~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector325~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector325~0 .lut_mask = 64'h00AF00AF00AF00AF;
defparam \A_SPW_TOP|rx_data|Selector325~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X36_Y5_N33
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector325~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector325~1_combout  = ( \A_SPW_TOP|rx_data|Mux0~20_combout  & ( (!\A_SPW_TOP|rx_data|Selector325~0_combout  & (((\A_SPW_TOP|rx_data|mem[34][8]~q )))) # (\A_SPW_TOP|rx_data|Selector325~0_combout  & 
// (((\A_SPW_TOP|rx_data|state_data_write.00~q )) # (\A_SPW_TOP|SPW|RX|rx_data_flag [8]))) ) ) # ( !\A_SPW_TOP|rx_data|Mux0~20_combout  & ( (!\A_SPW_TOP|rx_data|Selector325~0_combout  & (((\A_SPW_TOP|rx_data|mem[34][8]~q )))) # 
// (\A_SPW_TOP|rx_data|Selector325~0_combout  & (\A_SPW_TOP|SPW|RX|rx_data_flag [8] & (!\A_SPW_TOP|rx_data|state_data_write.00~q ))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[34][8]~q ),
        .datad(!\A_SPW_TOP|rx_data|Selector325~0_combout ),
        .datae(!\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector325~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector325~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector325~1 .lut_mask = 64'h0F440F770F440F77;
defparam \A_SPW_TOP|rx_data|Selector325~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X36_Y5_N32
dffeas \A_SPW_TOP|rx_data|mem[34][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector325~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[34][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[34][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[34][8] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X32_Y9_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Decoder0~42 (
// Equation(s):
// \A_SPW_TOP|rx_data|Decoder0~42_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [3] & ( \A_SPW_TOP|rx_data|wr_ptr [1] & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & (!\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|wr_ptr [5] & !\A_SPW_TOP|rx_data|wr_ptr [4]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Decoder0~42_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Decoder0~42 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Decoder0~42 .lut_mask = 64'h0000000000000800;
defparam \A_SPW_TOP|rx_data|Decoder0~42 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X33_Y9_N45
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector397~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector397~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( \A_SPW_TOP|rx_data|state_data_write.01~q  & ( \A_SPW_TOP|rx_data|Decoder0~42_combout  ) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( 
// \A_SPW_TOP|rx_data|state_data_write.01~q  & ( \A_SPW_TOP|rx_data|Decoder0~42_combout  ) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( !\A_SPW_TOP|rx_data|state_data_write.01~q  & ( \A_SPW_TOP|rx_data|Decoder0~42_combout  ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|rx_data|Decoder0~42_combout ),
        .datac(gnd),
        .datad(gnd),
        .datae(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector397~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector397~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector397~0 .lut_mask = 64'h3333000033333333;
defparam \A_SPW_TOP|rx_data|Selector397~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y9_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector397~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector397~1_combout  = ( \A_SPW_TOP|rx_data|Selector397~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [8])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux0~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector397~0_combout  & ( \A_SPW_TOP|rx_data|mem[42][8]~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .datab(!\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[42][8]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector397~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector397~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector397~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector397~1 .lut_mask = 64'h00FF00FF53535353;
defparam \A_SPW_TOP|rx_data|Selector397~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y9_N59
dffeas \A_SPW_TOP|rx_data|mem[42][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector397~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[42][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[42][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[42][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y8_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Decoder0~26 (
// Equation(s):
// \A_SPW_TOP|rx_data|Decoder0~26_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [1] & ( !\A_SPW_TOP|rx_data|wr_ptr [3] & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|wr_ptr [5] & (!\A_SPW_TOP|rx_data|wr_ptr [2] & \A_SPW_TOP|rx_data|wr_ptr [4]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Decoder0~26_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Decoder0~26 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Decoder0~26 .lut_mask = 64'h0000002000000000;
defparam \A_SPW_TOP|rx_data|Decoder0~26 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y8_N51
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector469~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector469~0_combout  = ( \A_SPW_TOP|rx_data|Decoder0~26_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|rx_data|state_data_write.01~q ) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Decoder0~26_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector469~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector469~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector469~0 .lut_mask = 64'h00000000F5F5F5F5;
defparam \A_SPW_TOP|rx_data|Selector469~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y9_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector469~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector469~1_combout  = ( \A_SPW_TOP|rx_data|Selector469~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [8])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux0~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector469~0_combout  & ( \A_SPW_TOP|rx_data|mem[50][8]~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .datab(!\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|mem[50][8]~q ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector469~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector469~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector469~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector469~1 .lut_mask = 64'h0F0F0F0F55335533;
defparam \A_SPW_TOP|rx_data|Selector469~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y9_N29
dffeas \A_SPW_TOP|rx_data|mem[50][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector469~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[50][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[50][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[50][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y9_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Decoder0~57 (
// Equation(s):
// \A_SPW_TOP|rx_data|Decoder0~57_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [1] & ( \A_SPW_TOP|rx_data|wr_ptr [5] & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|wr_ptr [4] & (!\A_SPW_TOP|rx_data|wr_ptr [2] & \A_SPW_TOP|rx_data|wr_ptr [3]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Decoder0~57_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Decoder0~57 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Decoder0~57 .lut_mask = 64'h0000000000000020;
defparam \A_SPW_TOP|rx_data|Decoder0~57 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y9_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector541~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector541~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.01~q  & ( \A_SPW_TOP|rx_data|Decoder0~57_combout  ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.01~q  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// \A_SPW_TOP|rx_data|Decoder0~57_combout ) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|rx_data|Decoder0~57_combout ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector541~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector541~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector541~0 .lut_mask = 64'h0A0A0F0F0A0A0F0F;
defparam \A_SPW_TOP|rx_data|Selector541~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y9_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector541~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector541~1_combout  = ( \A_SPW_TOP|rx_data|mem[58][8]~q  & ( (!\A_SPW_TOP|rx_data|Selector541~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [8])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux0~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[58][8]~q  & ( (\A_SPW_TOP|rx_data|Selector541~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [8])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux0~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .datab(!\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector541~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[58][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector541~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector541~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector541~1 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|rx_data|Selector541~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y9_N17
dffeas \A_SPW_TOP|rx_data|mem[58][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector541~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[58][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[58][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[58][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y9_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux0~6 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux0~6_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [4] & ( \A_SPW_TOP|rx_data|mem[58][8]~q  & ( (\A_SPW_TOP|rx_data|wr_ptr [3]) # (\A_SPW_TOP|rx_data|mem[50][8]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [4] & ( \A_SPW_TOP|rx_data|mem[58][8]~q 
//  & ( (!\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|mem[34][8]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [3] & ((\A_SPW_TOP|rx_data|mem[42][8]~q ))) ) ) ) # ( \A_SPW_TOP|rx_data|wr_ptr [4] & ( !\A_SPW_TOP|rx_data|mem[58][8]~q  & ( 
// (\A_SPW_TOP|rx_data|mem[50][8]~q  & !\A_SPW_TOP|rx_data|wr_ptr [3]) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [4] & ( !\A_SPW_TOP|rx_data|mem[58][8]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|mem[34][8]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [3] & 
// ((\A_SPW_TOP|rx_data|mem[42][8]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[34][8]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[42][8]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[50][8]~q ),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .dataf(!\A_SPW_TOP|rx_data|mem[58][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux0~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux0~6 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux0~6 .lut_mask = 64'h55330F0055330FFF;
defparam \A_SPW_TOP|rx_data|Mux0~6 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y9_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Decoder0~46 (
// Equation(s):
// \A_SPW_TOP|rx_data|Decoder0~46_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [1] & ( \A_SPW_TOP|rx_data|wr_ptr [5] & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & (!\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|wr_ptr [2] & \A_SPW_TOP|rx_data|wr_ptr [3]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Decoder0~46_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Decoder0~46 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Decoder0~46 .lut_mask = 64'h0000000000000008;
defparam \A_SPW_TOP|rx_data|Decoder0~46 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y9_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector433~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector433~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.01~q  & ( \A_SPW_TOP|rx_data|Decoder0~46_combout  ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.01~q  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// \A_SPW_TOP|rx_data|Decoder0~46_combout ) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|rx_data|Decoder0~46_combout ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector433~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector433~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector433~0 .lut_mask = 64'h0A0A0F0F0A0A0F0F;
defparam \A_SPW_TOP|rx_data|Selector433~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y9_N57
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector433~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector433~1_combout  = ( \A_SPW_TOP|rx_data|mem[46][8]~q  & ( (!\A_SPW_TOP|rx_data|Selector433~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [8])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux0~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[46][8]~q  & ( (\A_SPW_TOP|rx_data|Selector433~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [8])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux0~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .datad(!\A_SPW_TOP|rx_data|Selector433~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[46][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector433~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector433~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector433~1 .lut_mask = 64'h00470047FF47FF47;
defparam \A_SPW_TOP|rx_data|Selector433~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y9_N35
dffeas \A_SPW_TOP|rx_data|mem[46][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector433~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[46][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[46][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[46][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y4_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Decoder0~14 (
// Equation(s):
// \A_SPW_TOP|rx_data|Decoder0~14_combout  = ( !\A_SPW_TOP|rx_data|wr_ptr [3] & ( \A_SPW_TOP|rx_data|wr_ptr [5] & ( (\A_SPW_TOP|rx_data|wr_ptr [1] & (!\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|wr_ptr [2] & !\A_SPW_TOP|rx_data|wr_ptr [4]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Decoder0~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Decoder0~14 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Decoder0~14 .lut_mask = 64'h0000000004000000;
defparam \A_SPW_TOP|rx_data|Decoder0~14 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y4_N15
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector361~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector361~0_combout  = (\A_SPW_TOP|rx_data|Decoder0~14_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|rx_data|state_data_write.01~q )))

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .datac(!\A_SPW_TOP|rx_data|Decoder0~14_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector361~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector361~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector361~0 .lut_mask = 64'h0B0B0B0B0B0B0B0B;
defparam \A_SPW_TOP|rx_data|Selector361~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X33_Y8_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector361~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector361~1_combout  = ( \A_SPW_TOP|rx_data|Selector361~0_combout  & ( \A_SPW_TOP|SPW|RX|rx_data_flag [8] & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|rx_data|Mux0~20_combout ) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|Selector361~0_combout  & ( \A_SPW_TOP|SPW|RX|rx_data_flag [8] & ( \A_SPW_TOP|rx_data|mem[38][8]~q  ) ) ) # ( \A_SPW_TOP|rx_data|Selector361~0_combout  & ( !\A_SPW_TOP|SPW|RX|rx_data_flag [8] & ( 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & \A_SPW_TOP|rx_data|Mux0~20_combout ) ) ) ) # ( !\A_SPW_TOP|rx_data|Selector361~0_combout  & ( !\A_SPW_TOP|SPW|RX|rx_data_flag [8] & ( \A_SPW_TOP|rx_data|mem[38][8]~q  ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|rx_data|mem[38][8]~q ),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .datae(!\A_SPW_TOP|rx_data|Selector361~0_combout ),
        .dataf(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector361~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector361~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector361~1 .lut_mask = 64'h3333000F3333F0FF;
defparam \A_SPW_TOP|rx_data|Selector361~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X33_Y8_N11
dffeas \A_SPW_TOP|rx_data|mem[38][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector361~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[38][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[38][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[38][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y9_N39
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Decoder0~30 (
// Equation(s):
// \A_SPW_TOP|rx_data|Decoder0~30_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [1] & ( \A_SPW_TOP|rx_data|wr_ptr [5] & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & (!\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|wr_ptr [4] & \A_SPW_TOP|rx_data|wr_ptr [2]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Decoder0~30_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Decoder0~30 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Decoder0~30 .lut_mask = 64'h0000000000000008;
defparam \A_SPW_TOP|rx_data|Decoder0~30 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y9_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector505~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector505~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.01~q  & ( \A_SPW_TOP|rx_data|Decoder0~30_combout  ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.01~q  & ( (\A_SPW_TOP|rx_data|Decoder0~30_combout  & 
// !\A_SPW_TOP|rx_data|state_data_write.00~q ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|rx_data|Decoder0~30_combout ),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector505~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector505~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector505~0 .lut_mask = 64'h3030333330303333;
defparam \A_SPW_TOP|rx_data|Selector505~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y9_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector505~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector505~1_combout  = ( \A_SPW_TOP|rx_data|mem[54][8]~q  & ( (!\A_SPW_TOP|rx_data|Selector505~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [8])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux0~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[54][8]~q  & ( (\A_SPW_TOP|rx_data|Selector505~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [8])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux0~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Selector505~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[54][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector505~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector505~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector505~1 .lut_mask = 64'h04070407F4F7F4F7;
defparam \A_SPW_TOP|rx_data|Selector505~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y9_N14
dffeas \A_SPW_TOP|rx_data|mem[54][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector505~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[54][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[54][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[54][8] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X32_Y9_N9
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Decoder0~59 (
// Equation(s):
// \A_SPW_TOP|rx_data|Decoder0~59_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [2] & ( !\A_SPW_TOP|rx_data|wr_ptr [0] & ( (\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|wr_ptr [4] & \A_SPW_TOP|rx_data|wr_ptr [5]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Decoder0~59_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Decoder0~59 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Decoder0~59 .lut_mask = 64'h0000000100000000;
defparam \A_SPW_TOP|rx_data|Decoder0~59 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X33_Y9_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector577~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector577~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( \A_SPW_TOP|rx_data|state_data_write.01~q  & ( \A_SPW_TOP|rx_data|Decoder0~59_combout  ) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( 
// \A_SPW_TOP|rx_data|state_data_write.01~q  & ( \A_SPW_TOP|rx_data|Decoder0~59_combout  ) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( !\A_SPW_TOP|rx_data|state_data_write.01~q  & ( \A_SPW_TOP|rx_data|Decoder0~59_combout  ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|rx_data|Decoder0~59_combout ),
        .datac(gnd),
        .datad(gnd),
        .datae(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector577~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector577~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector577~0 .lut_mask = 64'h3333000033333333;
defparam \A_SPW_TOP|rx_data|Selector577~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y9_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector577~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector577~1_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector577~0_combout  & ((\A_SPW_TOP|rx_data|mem[62][8]~q ))) # (\A_SPW_TOP|rx_data|Selector577~0_combout  & 
// (\A_SPW_TOP|rx_data|Mux0~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector577~0_combout  & ((\A_SPW_TOP|rx_data|mem[62][8]~q ))) # (\A_SPW_TOP|rx_data|Selector577~0_combout  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [8])) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .datab(!\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector577~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[62][8]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector577~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector577~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector577~1 .lut_mask = 64'h05F505F503F303F3;
defparam \A_SPW_TOP|rx_data|Selector577~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y9_N32
dffeas \A_SPW_TOP|rx_data|mem[62][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector577~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[62][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[62][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[62][8] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y9_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux0~8 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux0~8_combout  = ( \A_SPW_TOP|rx_data|mem[62][8]~q  & ( \A_SPW_TOP|rx_data|wr_ptr [3] & ( (\A_SPW_TOP|rx_data|wr_ptr [4]) # (\A_SPW_TOP|rx_data|mem[46][8]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[62][8]~q  & ( \A_SPW_TOP|rx_data|wr_ptr 
// [3] & ( (\A_SPW_TOP|rx_data|mem[46][8]~q  & !\A_SPW_TOP|rx_data|wr_ptr [4]) ) ) ) # ( \A_SPW_TOP|rx_data|mem[62][8]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [3] & ( (!\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[38][8]~q )) # 
// (\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|mem[54][8]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[62][8]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [3] & ( (!\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[38][8]~q )) # (\A_SPW_TOP|rx_data|wr_ptr 
// [4] & ((\A_SPW_TOP|rx_data|mem[54][8]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[46][8]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[38][8]~q ),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datad(!\A_SPW_TOP|rx_data|mem[54][8]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[62][8]~q ),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux0~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux0~8 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux0~8 .lut_mask = 64'h303F303F50505F5F;
defparam \A_SPW_TOP|rx_data|Mux0~8 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X36_Y9_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux0~9 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux0~9_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [5] & ( \A_SPW_TOP|rx_data|Mux0~8_combout  & ( (\A_SPW_TOP|rx_data|wr_ptr [2]) # (\A_SPW_TOP|rx_data|Mux0~6_combout ) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [5] & ( 
// \A_SPW_TOP|rx_data|Mux0~8_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & ((\A_SPW_TOP|rx_data|Mux0~5_combout ))) # (\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|Mux0~7_combout )) ) ) ) # ( \A_SPW_TOP|rx_data|wr_ptr [5] & ( 
// !\A_SPW_TOP|rx_data|Mux0~8_combout  & ( (\A_SPW_TOP|rx_data|Mux0~6_combout  & !\A_SPW_TOP|rx_data|wr_ptr [2]) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [5] & ( !\A_SPW_TOP|rx_data|Mux0~8_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & 
// ((\A_SPW_TOP|rx_data|Mux0~5_combout ))) # (\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|Mux0~7_combout )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux0~7_combout ),
        .datab(!\A_SPW_TOP|rx_data|Mux0~5_combout ),
        .datac(!\A_SPW_TOP|rx_data|Mux0~6_combout ),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .dataf(!\A_SPW_TOP|rx_data|Mux0~8_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux0~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux0~9 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux0~9 .lut_mask = 64'h33550F0033550FFF;
defparam \A_SPW_TOP|rx_data|Mux0~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X36_Y6_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Decoder0~19 (
// Equation(s):
// \A_SPW_TOP|rx_data|Decoder0~19_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [0] & ( \A_SPW_TOP|rx_data|wr_ptr [5] & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & (!\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|wr_ptr [4] & !\A_SPW_TOP|rx_data|wr_ptr [2]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Decoder0~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Decoder0~19 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Decoder0~19 .lut_mask = 64'h0000000000000800;
defparam \A_SPW_TOP|rx_data|Decoder0~19 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X36_Y6_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector460~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector460~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (\A_SPW_TOP|rx_data|state_data_write.01~q  & \A_SPW_TOP|rx_data|Decoder0~19_combout ) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( 
// \A_SPW_TOP|rx_data|Decoder0~19_combout  ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .datac(!\A_SPW_TOP|rx_data|Decoder0~19_combout ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector460~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector460~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector460~0 .lut_mask = 64'h0F0F03030F0F0303;
defparam \A_SPW_TOP|rx_data|Selector460~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y7_N57
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector460~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector460~1_combout  = ( \A_SPW_TOP|rx_data|mem[49][8]~q  & ( (!\A_SPW_TOP|rx_data|Selector460~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [8]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux0~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[49][8]~q  & ( (\A_SPW_TOP|rx_data|Selector460~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [8]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux0~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector460~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[49][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector460~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector460~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector460~1 .lut_mask = 64'h010B010BF1FBF1FB;
defparam \A_SPW_TOP|rx_data|Selector460~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y7_N35
dffeas \A_SPW_TOP|rx_data|mem[49][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector460~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[49][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[49][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[49][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y7_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Decoder0~21 (
// Equation(s):
// \A_SPW_TOP|rx_data|Decoder0~21_combout  = ( !\A_SPW_TOP|rx_data|wr_ptr [1] & ( \A_SPW_TOP|rx_data|wr_ptr [2] & ( (!\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|wr_ptr [0] & !\A_SPW_TOP|rx_data|wr_ptr [5]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Decoder0~21_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Decoder0~21 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Decoder0~21 .lut_mask = 64'h0000000002000000;
defparam \A_SPW_TOP|rx_data|Decoder0~21 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X32_Y7_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector208~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector208~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (\A_SPW_TOP|rx_data|Decoder0~21_combout  & \A_SPW_TOP|rx_data|state_data_write.01~q ) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( 
// \A_SPW_TOP|rx_data|Decoder0~21_combout  ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|rx_data|Decoder0~21_combout ),
        .datac(gnd),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .datae(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector208~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector208~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector208~0 .lut_mask = 64'h3333003333330033;
defparam \A_SPW_TOP|rx_data|Selector208~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X32_Y7_N57
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector208~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector208~1_combout  = ( \A_SPW_TOP|rx_data|mem[21][8]~q  & ( (!\A_SPW_TOP|rx_data|Selector208~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [8]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux0~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[21][8]~q  & ( (\A_SPW_TOP|rx_data|Selector208~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [8]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux0~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .datac(!\A_SPW_TOP|rx_data|Selector208~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[21][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector208~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector208~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector208~1 .lut_mask = 64'h03050305F3F5F3F5;
defparam \A_SPW_TOP|rx_data|Selector208~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X32_Y7_N29
dffeas \A_SPW_TOP|rx_data|mem[21][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector208~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[21][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[21][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[21][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X35_Y4_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Decoder0~23 (
// Equation(s):
// \A_SPW_TOP|rx_data|Decoder0~23_combout  = ( !\A_SPW_TOP|rx_data|wr_ptr [3] & ( \A_SPW_TOP|rx_data|wr_ptr [5] & ( (\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|wr_ptr [2] & (!\A_SPW_TOP|rx_data|wr_ptr [1] & \A_SPW_TOP|rx_data|wr_ptr [4]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Decoder0~23_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Decoder0~23 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Decoder0~23 .lut_mask = 64'h0000000000100000;
defparam \A_SPW_TOP|rx_data|Decoder0~23 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X35_Y4_N27
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector496~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector496~0_combout  = ( \A_SPW_TOP|rx_data|Decoder0~23_combout  & ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( \A_SPW_TOP|rx_data|state_data_write.01~q  ) ) ) # ( \A_SPW_TOP|rx_data|Decoder0~23_combout  & ( 
// !\A_SPW_TOP|rx_data|state_data_write.00~q  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .datae(!\A_SPW_TOP|rx_data|Decoder0~23_combout ),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector496~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector496~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector496~0 .lut_mask = 64'h0000FFFF000000FF;
defparam \A_SPW_TOP|rx_data|Selector496~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X36_Y7_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector496~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector496~1_combout  = ( \A_SPW_TOP|rx_data|Selector496~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [8]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux0~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector496~0_combout  & ( \A_SPW_TOP|rx_data|mem[53][8]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[53][8]~q ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector496~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector496~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector496~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector496~1 .lut_mask = 64'h0F0F0F0F11DD11DD;
defparam \A_SPW_TOP|rx_data|Selector496~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X36_Y7_N23
dffeas \A_SPW_TOP|rx_data|mem[53][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector496~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[53][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[53][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[53][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y8_N45
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Decoder0~17 (
// Equation(s):
// \A_SPW_TOP|rx_data|Decoder0~17_combout  = ( !\A_SPW_TOP|rx_data|wr_ptr [5] & ( \A_SPW_TOP|rx_data|wr_ptr [4] & ( (\A_SPW_TOP|rx_data|wr_ptr [0] & (!\A_SPW_TOP|rx_data|wr_ptr [3] & (!\A_SPW_TOP|rx_data|wr_ptr [1] & !\A_SPW_TOP|rx_data|wr_ptr [2]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Decoder0~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Decoder0~17 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Decoder0~17 .lut_mask = 64'h0000000040000000;
defparam \A_SPW_TOP|rx_data|Decoder0~17 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y8_N51
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector172~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector172~0_combout  = (\A_SPW_TOP|rx_data|Decoder0~17_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|rx_data|state_data_write.01~q )))

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Decoder0~17_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector172~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector172~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector172~0 .lut_mask = 64'h0D0D0D0D0D0D0D0D;
defparam \A_SPW_TOP|rx_data|Selector172~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X36_Y7_N51
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector172~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector172~1_combout  = ( \A_SPW_TOP|rx_data|Selector172~0_combout  & ( \A_SPW_TOP|rx_data|mem[17][8]~q  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [8]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux0~20_combout )) ) ) ) # ( !\A_SPW_TOP|rx_data|Selector172~0_combout  & ( \A_SPW_TOP|rx_data|mem[17][8]~q  ) ) # ( \A_SPW_TOP|rx_data|Selector172~0_combout  & ( 
// !\A_SPW_TOP|rx_data|mem[17][8]~q  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [8]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux0~20_combout )) ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .datae(!\A_SPW_TOP|rx_data|Selector172~0_combout ),
        .dataf(!\A_SPW_TOP|rx_data|mem[17][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector172~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector172~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector172~1 .lut_mask = 64'h000003F3FFFF03F3;
defparam \A_SPW_TOP|rx_data|Selector172~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X36_Y7_N20
dffeas \A_SPW_TOP|rx_data|mem[17][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector172~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[17][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[17][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[17][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X36_Y7_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux0~12 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux0~12_combout  = ( \A_SPW_TOP|rx_data|mem[53][8]~q  & ( \A_SPW_TOP|rx_data|mem[17][8]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & (((!\A_SPW_TOP|rx_data|wr_ptr [2]) # (\A_SPW_TOP|rx_data|mem[21][8]~q )))) # (\A_SPW_TOP|rx_data|wr_ptr [5] 
// & (((\A_SPW_TOP|rx_data|wr_ptr [2])) # (\A_SPW_TOP|rx_data|mem[49][8]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[53][8]~q  & ( \A_SPW_TOP|rx_data|mem[17][8]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & (((!\A_SPW_TOP|rx_data|wr_ptr [2]) # 
// (\A_SPW_TOP|rx_data|mem[21][8]~q )))) # (\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|mem[49][8]~q  & ((!\A_SPW_TOP|rx_data|wr_ptr [2])))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[53][8]~q  & ( !\A_SPW_TOP|rx_data|mem[17][8]~q  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [5] & (((\A_SPW_TOP|rx_data|mem[21][8]~q  & \A_SPW_TOP|rx_data|wr_ptr [2])))) # (\A_SPW_TOP|rx_data|wr_ptr [5] & (((\A_SPW_TOP|rx_data|wr_ptr [2])) # (\A_SPW_TOP|rx_data|mem[49][8]~q ))) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|mem[53][8]~q  & ( !\A_SPW_TOP|rx_data|mem[17][8]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & (((\A_SPW_TOP|rx_data|mem[21][8]~q  & \A_SPW_TOP|rx_data|wr_ptr [2])))) # (\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|mem[49][8]~q  & 
// ((!\A_SPW_TOP|rx_data|wr_ptr [2])))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datab(!\A_SPW_TOP|rx_data|mem[49][8]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[21][8]~q ),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datae(!\A_SPW_TOP|rx_data|mem[53][8]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[17][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux0~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux0~12 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux0~12 .lut_mask = 64'h110A115FBB0ABB5F;
defparam \A_SPW_TOP|rx_data|Mux0~12 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X32_Y9_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Decoder0~60 (
// Equation(s):
// \A_SPW_TOP|rx_data|Decoder0~60_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [0] & ( !\A_SPW_TOP|rx_data|wr_ptr [2] & ( (\A_SPW_TOP|rx_data|wr_ptr [3] & (!\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|wr_ptr [5] & \A_SPW_TOP|rx_data|wr_ptr [4]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Decoder0~60_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Decoder0~60 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Decoder0~60 .lut_mask = 64'h0000000400000000;
defparam \A_SPW_TOP|rx_data|Decoder0~60 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X32_Y9_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector532~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector532~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (\A_SPW_TOP|rx_data|state_data_write.01~q  & \A_SPW_TOP|rx_data|Decoder0~60_combout ) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( 
// \A_SPW_TOP|rx_data|Decoder0~60_combout  ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|rx_data|Decoder0~60_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector532~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector532~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector532~0 .lut_mask = 64'h0F0F0F0F05050505;
defparam \A_SPW_TOP|rx_data|Selector532~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y7_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector532~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector532~1_combout  = ( \A_SPW_TOP|rx_data|Selector532~0_combout  & ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( \A_SPW_TOP|rx_data|Mux0~20_combout  ) ) ) # ( !\A_SPW_TOP|rx_data|Selector532~0_combout  & ( 
// \A_SPW_TOP|rx_data|state_data_write.00~q  & ( \A_SPW_TOP|rx_data|mem[57][8]~q  ) ) ) # ( \A_SPW_TOP|rx_data|Selector532~0_combout  & ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( \A_SPW_TOP|SPW|RX|rx_data_flag [8] ) ) ) # ( 
// !\A_SPW_TOP|rx_data|Selector532~0_combout  & ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( \A_SPW_TOP|rx_data|mem[57][8]~q  ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .datab(!\A_SPW_TOP|rx_data|mem[57][8]~q ),
        .datac(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .datad(gnd),
        .datae(!\A_SPW_TOP|rx_data|Selector532~0_combout ),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector532~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector532~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector532~1 .lut_mask = 64'h33330F0F33335555;
defparam \A_SPW_TOP|rx_data|Selector532~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y7_N47
dffeas \A_SPW_TOP|rx_data|mem[57][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector532~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[57][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[57][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[57][8] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y7_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Decoder0~62 (
// Equation(s):
// \A_SPW_TOP|rx_data|Decoder0~62_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [0] & ( \A_SPW_TOP|rx_data|wr_ptr [3] & ( (\A_SPW_TOP|rx_data|wr_ptr [4] & (!\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|wr_ptr [2] & \A_SPW_TOP|rx_data|wr_ptr [5]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Decoder0~62_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Decoder0~62 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Decoder0~62 .lut_mask = 64'h0000000000000004;
defparam \A_SPW_TOP|rx_data|Decoder0~62 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y7_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector568~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector568~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( \A_SPW_TOP|rx_data|state_data_write.01~q  & ( \A_SPW_TOP|rx_data|Decoder0~62_combout  ) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( 
// \A_SPW_TOP|rx_data|state_data_write.01~q  & ( \A_SPW_TOP|rx_data|Decoder0~62_combout  ) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( !\A_SPW_TOP|rx_data|state_data_write.01~q  & ( \A_SPW_TOP|rx_data|Decoder0~62_combout  ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|rx_data|Decoder0~62_combout ),
        .datac(gnd),
        .datad(gnd),
        .datae(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector568~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector568~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector568~0 .lut_mask = 64'h3333000033333333;
defparam \A_SPW_TOP|rx_data|Selector568~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y7_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector568~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector568~1_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector568~0_combout  & ((\A_SPW_TOP|rx_data|mem[61][8]~q ))) # (\A_SPW_TOP|rx_data|Selector568~0_combout  & 
// (\A_SPW_TOP|rx_data|Mux0~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector568~0_combout  & ((\A_SPW_TOP|rx_data|mem[61][8]~q ))) # (\A_SPW_TOP|rx_data|Selector568~0_combout  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [8])) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .datab(!\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector568~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[61][8]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector568~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector568~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector568~1 .lut_mask = 64'h05F505F503F303F3;
defparam \A_SPW_TOP|rx_data|Selector568~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y7_N29
dffeas \A_SPW_TOP|rx_data|mem[61][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector568~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[61][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[61][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[61][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X35_Y4_N57
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Decoder0~54 (
// Equation(s):
// \A_SPW_TOP|rx_data|Decoder0~54_combout  = ( !\A_SPW_TOP|rx_data|wr_ptr [5] & ( \A_SPW_TOP|rx_data|wr_ptr [3] & ( (\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|wr_ptr [4] & !\A_SPW_TOP|rx_data|wr_ptr [1]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Decoder0~54_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Decoder0~54 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Decoder0~54 .lut_mask = 64'h0000000001000000;
defparam \A_SPW_TOP|rx_data|Decoder0~54 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X35_Y4_N51
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector280~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector280~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.01~q  & ( \A_SPW_TOP|rx_data|Decoder0~54_combout  ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.01~q  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// \A_SPW_TOP|rx_data|Decoder0~54_combout ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Decoder0~54_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector280~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector280~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector280~0 .lut_mask = 64'h0C0C0C0C0F0F0F0F;
defparam \A_SPW_TOP|rx_data|Selector280~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X32_Y7_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector280~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector280~1_combout  = ( \A_SPW_TOP|rx_data|mem[29][8]~q  & ( (!\A_SPW_TOP|rx_data|Selector280~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [8]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux0~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[29][8]~q  & ( (\A_SPW_TOP|rx_data|Selector280~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [8]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux0~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|Selector280~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[29][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector280~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector280~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector280~1 .lut_mask = 64'h00350035FF35FF35;
defparam \A_SPW_TOP|rx_data|Selector280~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X32_Y7_N44
dffeas \A_SPW_TOP|rx_data|mem[29][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector280~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[29][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[29][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[29][8] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y7_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux0~13 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux0~13_combout  = ( \A_SPW_TOP|rx_data|mem[29][8]~q  & ( \A_SPW_TOP|rx_data|wr_ptr [5] & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|mem[57][8]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [2] & ((\A_SPW_TOP|rx_data|mem[61][8]~q ))) ) 
// ) ) # ( !\A_SPW_TOP|rx_data|mem[29][8]~q  & ( \A_SPW_TOP|rx_data|wr_ptr [5] & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|mem[57][8]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [2] & ((\A_SPW_TOP|rx_data|mem[61][8]~q ))) ) ) ) # ( 
// \A_SPW_TOP|rx_data|mem[29][8]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [5] & ( (\A_SPW_TOP|rx_data|wr_ptr [2]) # (\A_SPW_TOP|rx_data|mem[25][8]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[29][8]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [5] & ( 
// (\A_SPW_TOP|rx_data|mem[25][8]~q  & !\A_SPW_TOP|rx_data|wr_ptr [2]) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[25][8]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[57][8]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[61][8]~q ),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datae(!\A_SPW_TOP|rx_data|mem[29][8]~q ),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux0~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux0~13 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux0~13 .lut_mask = 64'h550055FF330F330F;
defparam \A_SPW_TOP|rx_data|Mux0~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y4_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Decoder0~37 (
// Equation(s):
// \A_SPW_TOP|rx_data|Decoder0~37_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [0] & ( !\A_SPW_TOP|rx_data|wr_ptr [1] & ( (\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|wr_ptr [2] & (!\A_SPW_TOP|rx_data|wr_ptr [4] & !\A_SPW_TOP|rx_data|wr_ptr [5]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Decoder0~37_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Decoder0~37 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Decoder0~37 .lut_mask = 64'h0000100000000000;
defparam \A_SPW_TOP|rx_data|Decoder0~37 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X31_Y4_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector136~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector136~0_combout  = ( \A_SPW_TOP|rx_data|Decoder0~37_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|rx_data|state_data_write.01~q ) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|rx_data|Decoder0~37_combout ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector136~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector136~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector136~0 .lut_mask = 64'h0000AFAF0000AFAF;
defparam \A_SPW_TOP|rx_data|Selector136~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y7_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector136~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector136~1_combout  = ( \A_SPW_TOP|SPW|RX|rx_data_flag [8] & ( \A_SPW_TOP|rx_data|Mux0~20_combout  & ( (\A_SPW_TOP|rx_data|mem[13][8]~q ) # (\A_SPW_TOP|rx_data|Selector136~0_combout ) ) ) ) # ( !\A_SPW_TOP|SPW|RX|rx_data_flag [8] & ( 
// \A_SPW_TOP|rx_data|Mux0~20_combout  & ( (!\A_SPW_TOP|rx_data|Selector136~0_combout  & (\A_SPW_TOP|rx_data|mem[13][8]~q )) # (\A_SPW_TOP|rx_data|Selector136~0_combout  & ((\A_SPW_TOP|rx_data|state_data_write.00~q ))) ) ) ) # ( 
// \A_SPW_TOP|SPW|RX|rx_data_flag [8] & ( !\A_SPW_TOP|rx_data|Mux0~20_combout  & ( (!\A_SPW_TOP|rx_data|Selector136~0_combout  & (\A_SPW_TOP|rx_data|mem[13][8]~q )) # (\A_SPW_TOP|rx_data|Selector136~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q 
// ))) ) ) ) # ( !\A_SPW_TOP|SPW|RX|rx_data_flag [8] & ( !\A_SPW_TOP|rx_data|Mux0~20_combout  & ( (!\A_SPW_TOP|rx_data|Selector136~0_combout  & \A_SPW_TOP|rx_data|mem[13][8]~q ) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Selector136~0_combout ),
        .datab(!\A_SPW_TOP|rx_data|mem[13][8]~q ),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .dataf(!\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector136~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector136~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector136~1 .lut_mask = 64'h2222727227277777;
defparam \A_SPW_TOP|rx_data|Selector136~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y7_N41
dffeas \A_SPW_TOP|rx_data|mem[13][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector136~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[13][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[13][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[13][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X35_Y4_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Decoder0~39 (
// Equation(s):
// \A_SPW_TOP|rx_data|Decoder0~39_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [0] & ( !\A_SPW_TOP|rx_data|wr_ptr [4] & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|wr_ptr [2] & \A_SPW_TOP|rx_data|wr_ptr [5]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Decoder0~39_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Decoder0~39 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Decoder0~39 .lut_mask = 64'h0000000200000000;
defparam \A_SPW_TOP|rx_data|Decoder0~39 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X35_Y4_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector424~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector424~0_combout  = (\A_SPW_TOP|rx_data|Decoder0~39_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|rx_data|state_data_write.01~q )))

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Decoder0~39_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector424~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector424~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector424~0 .lut_mask = 64'h0D0D0D0D0D0D0D0D;
defparam \A_SPW_TOP|rx_data|Selector424~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y7_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector424~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector424~1_combout  = ( \A_SPW_TOP|rx_data|Selector424~0_combout  & ( \A_SPW_TOP|rx_data|mem[45][8]~q  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [8])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux0~20_combout ))) ) ) ) # ( !\A_SPW_TOP|rx_data|Selector424~0_combout  & ( \A_SPW_TOP|rx_data|mem[45][8]~q  ) ) # ( \A_SPW_TOP|rx_data|Selector424~0_combout  & ( 
// !\A_SPW_TOP|rx_data|mem[45][8]~q  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [8])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux0~20_combout ))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .datab(!\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|rx_data|Selector424~0_combout ),
        .dataf(!\A_SPW_TOP|rx_data|mem[45][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector424~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector424~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector424~1 .lut_mask = 64'h00005353FFFF5353;
defparam \A_SPW_TOP|rx_data|Selector424~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y7_N20
dffeas \A_SPW_TOP|rx_data|mem[45][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector424~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[45][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[45][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[45][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y4_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Decoder0~33 (
// Equation(s):
// \A_SPW_TOP|rx_data|Decoder0~33_combout  = ( !\A_SPW_TOP|rx_data|wr_ptr [1] & ( !\A_SPW_TOP|rx_data|wr_ptr [5] & ( (!\A_SPW_TOP|rx_data|wr_ptr [4] & (!\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|wr_ptr [3] & \A_SPW_TOP|rx_data|wr_ptr [0]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Decoder0~33_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Decoder0~33 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Decoder0~33 .lut_mask = 64'h0008000000000000;
defparam \A_SPW_TOP|rx_data|Decoder0~33 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X31_Y4_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector100~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector100~0_combout  = (\A_SPW_TOP|rx_data|Decoder0~33_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|rx_data|state_data_write.01~q )))

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|rx_data|Decoder0~33_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector100~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector100~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector100~0 .lut_mask = 64'h0F050F050F050F05;
defparam \A_SPW_TOP|rx_data|Selector100~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y7_N45
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector100~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector100~1_combout  = ( \A_SPW_TOP|rx_data|Mux0~20_combout  & ( \A_SPW_TOP|rx_data|Selector100~0_combout  & ( (\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|SPW|RX|rx_data_flag [8]) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|Mux0~20_combout  & ( \A_SPW_TOP|rx_data|Selector100~0_combout  & ( (\A_SPW_TOP|SPW|RX|rx_data_flag [8] & !\A_SPW_TOP|rx_data|state_data_write.00~q ) ) ) ) # ( \A_SPW_TOP|rx_data|Mux0~20_combout  & ( 
// !\A_SPW_TOP|rx_data|Selector100~0_combout  & ( \A_SPW_TOP|rx_data|mem[9][8]~q  ) ) ) # ( !\A_SPW_TOP|rx_data|Mux0~20_combout  & ( !\A_SPW_TOP|rx_data|Selector100~0_combout  & ( \A_SPW_TOP|rx_data|mem[9][8]~q  ) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .datab(gnd),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[9][8]~q ),
        .datae(!\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .dataf(!\A_SPW_TOP|rx_data|Selector100~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector100~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector100~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector100~1 .lut_mask = 64'h00FF00FF50505F5F;
defparam \A_SPW_TOP|rx_data|Selector100~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y7_N17
dffeas \A_SPW_TOP|rx_data|mem[9][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector100~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[9][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[9][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[9][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X35_Y4_N39
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Decoder0~35 (
// Equation(s):
// \A_SPW_TOP|rx_data|Decoder0~35_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [5] & ( !\A_SPW_TOP|rx_data|wr_ptr [1] & ( (\A_SPW_TOP|rx_data|wr_ptr [0] & (!\A_SPW_TOP|rx_data|wr_ptr [2] & (!\A_SPW_TOP|rx_data|wr_ptr [4] & \A_SPW_TOP|rx_data|wr_ptr [3]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Decoder0~35_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Decoder0~35 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Decoder0~35 .lut_mask = 64'h0000004000000000;
defparam \A_SPW_TOP|rx_data|Decoder0~35 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X35_Y4_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector388~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector388~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (\A_SPW_TOP|rx_data|Decoder0~35_combout  & \A_SPW_TOP|rx_data|state_data_write.01~q ) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( 
// \A_SPW_TOP|rx_data|Decoder0~35_combout  ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|rx_data|Decoder0~35_combout ),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector388~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector388~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector388~0 .lut_mask = 64'h3333333303030303;
defparam \A_SPW_TOP|rx_data|Selector388~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y7_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector388~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector388~1_combout  = ( \A_SPW_TOP|rx_data|mem[41][8]~q  & ( (!\A_SPW_TOP|rx_data|Selector388~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [8])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux0~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[41][8]~q  & ( (\A_SPW_TOP|rx_data|Selector388~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [8])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux0~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .datab(!\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|Selector388~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[41][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector388~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector388~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector388~1 .lut_mask = 64'h00530053FF53FF53;
defparam \A_SPW_TOP|rx_data|Selector388~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y7_N14
dffeas \A_SPW_TOP|rx_data|mem[41][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector388~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[41][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[41][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[41][8] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y7_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux0~11 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux0~11_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [2] & ( \A_SPW_TOP|rx_data|mem[41][8]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|mem[13][8]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [5] & ((\A_SPW_TOP|rx_data|mem[45][8]~q ))) ) 
// ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [2] & ( \A_SPW_TOP|rx_data|mem[41][8]~q  & ( (\A_SPW_TOP|rx_data|mem[9][8]~q ) # (\A_SPW_TOP|rx_data|wr_ptr [5]) ) ) ) # ( \A_SPW_TOP|rx_data|wr_ptr [2] & ( !\A_SPW_TOP|rx_data|mem[41][8]~q  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|mem[13][8]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [5] & ((\A_SPW_TOP|rx_data|mem[45][8]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [2] & ( !\A_SPW_TOP|rx_data|mem[41][8]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr 
// [5] & \A_SPW_TOP|rx_data|mem[9][8]~q ) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datab(!\A_SPW_TOP|rx_data|mem[13][8]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[45][8]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[9][8]~q ),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .dataf(!\A_SPW_TOP|rx_data|mem[41][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux0~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux0~11 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux0~11 .lut_mask = 64'h00AA272755FF2727;
defparam \A_SPW_TOP|rx_data|Mux0~11 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X33_Y4_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Decoder0~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Decoder0~1_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [0] & ( !\A_SPW_TOP|rx_data|wr_ptr [1] & ( (!\A_SPW_TOP|rx_data|wr_ptr [4] & (!\A_SPW_TOP|rx_data|wr_ptr [3] & (!\A_SPW_TOP|rx_data|wr_ptr [2] & !\A_SPW_TOP|rx_data|wr_ptr [5]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Decoder0~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Decoder0~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Decoder0~1 .lut_mask = 64'h0000800000000000;
defparam \A_SPW_TOP|rx_data|Decoder0~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X33_Y4_N33
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector28~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector28~0_combout  = ( \A_SPW_TOP|rx_data|Decoder0~1_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|rx_data|state_data_write.01~q ) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Decoder0~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector28~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector28~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector28~0 .lut_mask = 64'h00000000DDDDDDDD;
defparam \A_SPW_TOP|rx_data|Selector28~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X36_Y7_N9
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector28~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector28~1_combout  = ( \A_SPW_TOP|SPW|RX|rx_data_flag [8] & ( (!\A_SPW_TOP|rx_data|Selector28~0_combout  & (((\A_SPW_TOP|rx_data|mem[1][8]~q )))) # (\A_SPW_TOP|rx_data|Selector28~0_combout  & 
// ((!\A_SPW_TOP|rx_data|state_data_write.00~q ) # ((\A_SPW_TOP|rx_data|Mux0~20_combout )))) ) ) # ( !\A_SPW_TOP|SPW|RX|rx_data_flag [8] & ( (!\A_SPW_TOP|rx_data|Selector28~0_combout  & (((\A_SPW_TOP|rx_data|mem[1][8]~q )))) # 
// (\A_SPW_TOP|rx_data|Selector28~0_combout  & (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux0~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Selector28~0_combout ),
        .datac(!\A_SPW_TOP|rx_data|mem[1][8]~q ),
        .datad(!\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .datae(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector28~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector28~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector28~1 .lut_mask = 64'h0C1D2E3F0C1D2E3F;
defparam \A_SPW_TOP|rx_data|Selector28~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X36_Y7_N8
dffeas \A_SPW_TOP|rx_data|mem[1][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector28~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[1][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[1][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[1][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y8_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Decoder0~3 (
// Equation(s):
// \A_SPW_TOP|rx_data|Decoder0~3_combout  = ( !\A_SPW_TOP|rx_data|wr_ptr [4] & ( \A_SPW_TOP|rx_data|wr_ptr [5] & ( (\A_SPW_TOP|rx_data|wr_ptr [0] & (!\A_SPW_TOP|rx_data|wr_ptr [3] & (!\A_SPW_TOP|rx_data|wr_ptr [2] & !\A_SPW_TOP|rx_data|wr_ptr [1]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Decoder0~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Decoder0~3 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Decoder0~3 .lut_mask = 64'h0000000040000000;
defparam \A_SPW_TOP|rx_data|Decoder0~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y8_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector316~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector316~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( \A_SPW_TOP|rx_data|Decoder0~3_combout  & ( \A_SPW_TOP|rx_data|state_data_write.01~q  ) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( 
// \A_SPW_TOP|rx_data|Decoder0~3_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .dataf(!\A_SPW_TOP|rx_data|Decoder0~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector316~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector316~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector316~0 .lut_mask = 64'h00000000FFFF0F0F;
defparam \A_SPW_TOP|rx_data|Selector316~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X36_Y7_N15
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector316~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector316~1_combout  = ( \A_SPW_TOP|rx_data|mem[33][8]~q  & ( (!\A_SPW_TOP|rx_data|Selector316~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [8])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux0~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[33][8]~q  & ( (\A_SPW_TOP|rx_data|Selector316~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [8])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux0~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Selector316~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[33][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector316~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector316~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector316~1 .lut_mask = 64'h04070407F4F7F4F7;
defparam \A_SPW_TOP|rx_data|Selector316~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X36_Y7_N35
dffeas \A_SPW_TOP|rx_data|mem[33][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector316~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[33][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[33][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[33][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y7_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Decoder0~7 (
// Equation(s):
// \A_SPW_TOP|rx_data|Decoder0~7_combout  = ( !\A_SPW_TOP|rx_data|wr_ptr [1] & ( \A_SPW_TOP|rx_data|wr_ptr [2] & ( (\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|wr_ptr [5] & (!\A_SPW_TOP|rx_data|wr_ptr [3] & !\A_SPW_TOP|rx_data|wr_ptr [4]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Decoder0~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Decoder0~7 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Decoder0~7 .lut_mask = 64'h0000000010000000;
defparam \A_SPW_TOP|rx_data|Decoder0~7 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X31_Y7_N27
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector352~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector352~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( \A_SPW_TOP|rx_data|Decoder0~7_combout  & ( \A_SPW_TOP|rx_data|state_data_write.01~q  ) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( 
// \A_SPW_TOP|rx_data|Decoder0~7_combout  ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .dataf(!\A_SPW_TOP|rx_data|Decoder0~7_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector352~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector352~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector352~0 .lut_mask = 64'h00000000FFFF5555;
defparam \A_SPW_TOP|rx_data|Selector352~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X36_Y7_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector352~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector352~1_combout  = ( \A_SPW_TOP|rx_data|mem[37][8]~q  & ( (!\A_SPW_TOP|rx_data|Selector352~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [8]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux0~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[37][8]~q  & ( (\A_SPW_TOP|rx_data|Selector352~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [8]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux0~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .datad(!\A_SPW_TOP|rx_data|Selector352~0_combout ),
        .datae(!\A_SPW_TOP|rx_data|mem[37][8]~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector352~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector352~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector352~1 .lut_mask = 64'h001DFF1D001DFF1D;
defparam \A_SPW_TOP|rx_data|Selector352~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X36_Y7_N59
dffeas \A_SPW_TOP|rx_data|mem[37][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector352~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[37][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[37][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[37][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y8_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Decoder0~5 (
// Equation(s):
// \A_SPW_TOP|rx_data|Decoder0~5_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [2] & ( !\A_SPW_TOP|rx_data|wr_ptr [5] & ( (!\A_SPW_TOP|rx_data|wr_ptr [3] & (!\A_SPW_TOP|rx_data|wr_ptr [4] & (!\A_SPW_TOP|rx_data|wr_ptr [1] & \A_SPW_TOP|rx_data|wr_ptr [0]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Decoder0~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Decoder0~5 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Decoder0~5 .lut_mask = 64'h0000008000000000;
defparam \A_SPW_TOP|rx_data|Decoder0~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y8_N27
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector64~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector64~0_combout  = ( \A_SPW_TOP|rx_data|Decoder0~5_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|rx_data|state_data_write.01~q ) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Decoder0~5_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector64~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector64~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector64~0 .lut_mask = 64'h00000000DDDDDDDD;
defparam \A_SPW_TOP|rx_data|Selector64~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X36_Y7_N45
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector64~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector64~1_combout  = ( \A_SPW_TOP|rx_data|Selector64~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [8]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux0~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector64~0_combout  & ( \A_SPW_TOP|rx_data|mem[5][8]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[5][8]~q ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector64~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector64~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector64~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector64~1 .lut_mask = 64'h0F0F0F0F11DD11DD;
defparam \A_SPW_TOP|rx_data|Selector64~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X36_Y7_N41
dffeas \A_SPW_TOP|rx_data|mem[5][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector64~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[5][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[5][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[5][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X36_Y7_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux0~10 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux0~10_combout  = ( \A_SPW_TOP|rx_data|mem[37][8]~q  & ( \A_SPW_TOP|rx_data|mem[5][8]~q  & ( ((!\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|mem[1][8]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [5] & ((\A_SPW_TOP|rx_data|mem[33][8]~q 
// )))) # (\A_SPW_TOP|rx_data|wr_ptr [2]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[37][8]~q  & ( \A_SPW_TOP|rx_data|mem[5][8]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & (((\A_SPW_TOP|rx_data|wr_ptr [2])) # (\A_SPW_TOP|rx_data|mem[1][8]~q ))) # 
// (\A_SPW_TOP|rx_data|wr_ptr [5] & (((\A_SPW_TOP|rx_data|mem[33][8]~q  & !\A_SPW_TOP|rx_data|wr_ptr [2])))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[37][8]~q  & ( !\A_SPW_TOP|rx_data|mem[5][8]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|mem[1][8]~q 
//  & ((!\A_SPW_TOP|rx_data|wr_ptr [2])))) # (\A_SPW_TOP|rx_data|wr_ptr [5] & (((\A_SPW_TOP|rx_data|wr_ptr [2]) # (\A_SPW_TOP|rx_data|mem[33][8]~q )))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[37][8]~q  & ( !\A_SPW_TOP|rx_data|mem[5][8]~q  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [2] & ((!\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|mem[1][8]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [5] & ((\A_SPW_TOP|rx_data|mem[33][8]~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datab(!\A_SPW_TOP|rx_data|mem[1][8]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[33][8]~q ),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datae(!\A_SPW_TOP|rx_data|mem[37][8]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[5][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux0~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux0~10 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux0~10 .lut_mask = 64'h2700275527AA27FF;
defparam \A_SPW_TOP|rx_data|Mux0~10 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X36_Y7_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux0~14 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux0~14_combout  = ( \A_SPW_TOP|rx_data|Mux0~11_combout  & ( \A_SPW_TOP|rx_data|Mux0~10_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [4]) # ((!\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|Mux0~12_combout )) # 
// (\A_SPW_TOP|rx_data|wr_ptr [3] & ((\A_SPW_TOP|rx_data|Mux0~13_combout )))) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux0~11_combout  & ( \A_SPW_TOP|rx_data|Mux0~10_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [3] & ((!\A_SPW_TOP|rx_data|wr_ptr [4]) # 
// ((\A_SPW_TOP|rx_data|Mux0~12_combout )))) # (\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|Mux0~13_combout )))) ) ) ) # ( \A_SPW_TOP|rx_data|Mux0~11_combout  & ( !\A_SPW_TOP|rx_data|Mux0~10_combout  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|Mux0~12_combout ))) # (\A_SPW_TOP|rx_data|wr_ptr [3] & ((!\A_SPW_TOP|rx_data|wr_ptr [4]) # ((\A_SPW_TOP|rx_data|Mux0~13_combout )))) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|Mux0~11_combout  & ( !\A_SPW_TOP|rx_data|Mux0~10_combout  & ( (\A_SPW_TOP|rx_data|wr_ptr [4] & ((!\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|Mux0~12_combout )) # (\A_SPW_TOP|rx_data|wr_ptr [3] & 
// ((\A_SPW_TOP|rx_data|Mux0~13_combout ))))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datac(!\A_SPW_TOP|rx_data|Mux0~12_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux0~13_combout ),
        .datae(!\A_SPW_TOP|rx_data|Mux0~11_combout ),
        .dataf(!\A_SPW_TOP|rx_data|Mux0~10_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux0~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux0~14 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux0~14 .lut_mask = 64'h021346578A9BCEDF;
defparam \A_SPW_TOP|rx_data|Mux0~14 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y8_N33
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Decoder0~56 (
// Equation(s):
// \A_SPW_TOP|rx_data|Decoder0~56_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [3] & ( !\A_SPW_TOP|rx_data|wr_ptr [1] & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|wr_ptr [4] & !\A_SPW_TOP|rx_data|wr_ptr [2]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Decoder0~56_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Decoder0~56 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Decoder0~56 .lut_mask = 64'h0000020000000000;
defparam \A_SPW_TOP|rx_data|Decoder0~56 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y8_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector523~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector523~0_combout  = ( \A_SPW_TOP|rx_data|Decoder0~56_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|rx_data|state_data_write.01~q ) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Decoder0~56_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector523~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector523~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector523~0 .lut_mask = 64'h00000000DDDDDDDD;
defparam \A_SPW_TOP|rx_data|Selector523~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X33_Y7_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector523~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector523~1_combout  = ( \A_SPW_TOP|rx_data|Selector523~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [8])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux0~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector523~0_combout  & ( \A_SPW_TOP|rx_data|mem[56][8]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .datac(!\A_SPW_TOP|rx_data|mem[56][8]~q ),
        .datad(!\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector523~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector523~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector523~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector523~1 .lut_mask = 64'h0F0F0F0F22772277;
defparam \A_SPW_TOP|rx_data|Selector523~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X33_Y7_N32
dffeas \A_SPW_TOP|rx_data|mem[56][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector523~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[56][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[56][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[56][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X33_Y4_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Decoder0~50 (
// Equation(s):
// \A_SPW_TOP|rx_data|Decoder0~50_combout  = ( !\A_SPW_TOP|rx_data|wr_ptr [0] & ( \A_SPW_TOP|rx_data|wr_ptr [2] & ( (\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|wr_ptr [3] & (!\A_SPW_TOP|rx_data|wr_ptr [1] & !\A_SPW_TOP|rx_data|wr_ptr [5]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Decoder0~50_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Decoder0~50 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Decoder0~50 .lut_mask = 64'h0000000010000000;
defparam \A_SPW_TOP|rx_data|Decoder0~50 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X33_Y4_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector271~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector271~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.01~q  & ( \A_SPW_TOP|rx_data|Decoder0~50_combout  ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.01~q  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// \A_SPW_TOP|rx_data|Decoder0~50_combout ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Decoder0~50_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector271~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector271~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector271~0 .lut_mask = 64'h0C0C0C0C0F0F0F0F;
defparam \A_SPW_TOP|rx_data|Selector271~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X33_Y7_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector271~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector271~1_combout  = ( \A_SPW_TOP|rx_data|mem[28][8]~q  & ( (!\A_SPW_TOP|rx_data|Selector271~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [8]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux0~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[28][8]~q  & ( (\A_SPW_TOP|rx_data|Selector271~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [8]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux0~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|Selector271~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[28][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector271~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector271~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector271~1 .lut_mask = 64'h00350035FF35FF35;
defparam \A_SPW_TOP|rx_data|Selector271~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X33_Y7_N8
dffeas \A_SPW_TOP|rx_data|mem[28][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector271~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[28][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[28][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[28][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y9_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Decoder0~48 (
// Equation(s):
// \A_SPW_TOP|rx_data|Decoder0~48_combout  = ( !\A_SPW_TOP|rx_data|wr_ptr [1] & ( !\A_SPW_TOP|rx_data|wr_ptr [5] & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|wr_ptr [4] & (!\A_SPW_TOP|rx_data|wr_ptr [2] & \A_SPW_TOP|rx_data|wr_ptr [3]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Decoder0~48_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Decoder0~48 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Decoder0~48 .lut_mask = 64'h0020000000000000;
defparam \A_SPW_TOP|rx_data|Decoder0~48 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y7_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector235~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector235~0_combout  = (\A_SPW_TOP|rx_data|Decoder0~48_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|rx_data|state_data_write.01~q )))

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Decoder0~48_combout ),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector235~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector235~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector235~0 .lut_mask = 64'h2323232323232323;
defparam \A_SPW_TOP|rx_data|Selector235~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X32_Y7_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector235~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector235~1_combout  = ( \A_SPW_TOP|rx_data|mem[24][8]~q  & ( (!\A_SPW_TOP|rx_data|Selector235~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [8]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux0~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[24][8]~q  & ( (\A_SPW_TOP|rx_data|Selector235~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [8]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux0~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|Selector235~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[24][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector235~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector235~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector235~1 .lut_mask = 64'h00350035FF35FF35;
defparam \A_SPW_TOP|rx_data|Selector235~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X32_Y7_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|mem[24][8]~feeder (
// Equation(s):
// \A_SPW_TOP|rx_data|mem[24][8]~feeder_combout  = ( \A_SPW_TOP|rx_data|Selector235~1_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector235~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|mem[24][8]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[24][8]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|mem[24][8]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|rx_data|mem[24][8]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X32_Y7_N14
dffeas \A_SPW_TOP|rx_data|mem[24][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|rx_data|mem[24][8]~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[24][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[24][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[24][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X33_Y4_N57
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Decoder0~58 (
// Equation(s):
// \A_SPW_TOP|rx_data|Decoder0~58_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [5] & ( !\A_SPW_TOP|rx_data|wr_ptr [1] & ( (\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|wr_ptr [3] & (!\A_SPW_TOP|rx_data|wr_ptr [0] & \A_SPW_TOP|rx_data|wr_ptr [2]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Decoder0~58_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Decoder0~58 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Decoder0~58 .lut_mask = 64'h0000001000000000;
defparam \A_SPW_TOP|rx_data|Decoder0~58 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X33_Y4_N39
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector559~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector559~0_combout  = (\A_SPW_TOP|rx_data|Decoder0~58_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|rx_data|state_data_write.01~q )))

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Decoder0~58_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector559~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector559~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector559~0 .lut_mask = 64'h0D0D0D0D0D0D0D0D;
defparam \A_SPW_TOP|rx_data|Selector559~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X33_Y7_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector559~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector559~1_combout  = ( \A_SPW_TOP|rx_data|mem[60][8]~q  & ( (!\A_SPW_TOP|rx_data|Selector559~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [8])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux0~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[60][8]~q  & ( (\A_SPW_TOP|rx_data|Selector559~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [8])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux0~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .datac(!\A_SPW_TOP|rx_data|Selector559~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[60][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector559~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector559~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector559~1 .lut_mask = 64'h02070207F2F7F2F7;
defparam \A_SPW_TOP|rx_data|Selector559~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X33_Y7_N44
dffeas \A_SPW_TOP|rx_data|mem[60][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector559~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[60][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[60][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[60][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X33_Y7_N33
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux0~3 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux0~3_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [5] & ( \A_SPW_TOP|rx_data|mem[60][8]~q  & ( (\A_SPW_TOP|rx_data|mem[56][8]~q ) # (\A_SPW_TOP|rx_data|wr_ptr [2]) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [5] & ( \A_SPW_TOP|rx_data|mem[60][8]~q 
//  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & ((\A_SPW_TOP|rx_data|mem[24][8]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|mem[28][8]~q )) ) ) ) # ( \A_SPW_TOP|rx_data|wr_ptr [5] & ( !\A_SPW_TOP|rx_data|mem[60][8]~q  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [2] & \A_SPW_TOP|rx_data|mem[56][8]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [5] & ( !\A_SPW_TOP|rx_data|mem[60][8]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & ((\A_SPW_TOP|rx_data|mem[24][8]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [2] 
// & (\A_SPW_TOP|rx_data|mem[28][8]~q )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datab(!\A_SPW_TOP|rx_data|mem[56][8]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[28][8]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[24][8]~q ),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .dataf(!\A_SPW_TOP|rx_data|mem[60][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux0~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux0~3 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux0~3 .lut_mask = 64'h05AF222205AF7777;
defparam \A_SPW_TOP|rx_data|Mux0~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X33_Y4_N9
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Decoder0~20 (
// Equation(s):
// \A_SPW_TOP|rx_data|Decoder0~20_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [2] & ( !\A_SPW_TOP|rx_data|wr_ptr [1] & ( (\A_SPW_TOP|rx_data|wr_ptr [4] & (!\A_SPW_TOP|rx_data|wr_ptr [5] & (!\A_SPW_TOP|rx_data|wr_ptr [3] & !\A_SPW_TOP|rx_data|wr_ptr [0]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Decoder0~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Decoder0~20 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Decoder0~20 .lut_mask = 64'h0000400000000000;
defparam \A_SPW_TOP|rx_data|Decoder0~20 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X33_Y4_N45
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector199~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector199~0_combout  = ( \A_SPW_TOP|rx_data|Decoder0~20_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|rx_data|state_data_write.01~q ) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Decoder0~20_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector199~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector199~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector199~0 .lut_mask = 64'h00000000DDDDDDDD;
defparam \A_SPW_TOP|rx_data|Selector199~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y7_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector199~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector199~1_combout  = ( \A_SPW_TOP|rx_data|Selector199~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [8]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux0~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector199~0_combout  & ( \A_SPW_TOP|rx_data|mem[20][8]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|mem[20][8]~q ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector199~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector199~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector199~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector199~1 .lut_mask = 64'h0F0F0F0F11BB11BB;
defparam \A_SPW_TOP|rx_data|Selector199~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y7_N38
dffeas \A_SPW_TOP|rx_data|mem[20][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector199~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[20][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[20][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[20][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y7_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Decoder0~18 (
// Equation(s):
// \A_SPW_TOP|rx_data|Decoder0~18_combout  = ( !\A_SPW_TOP|rx_data|wr_ptr [3] & ( \A_SPW_TOP|rx_data|wr_ptr [4] & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & (!\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|wr_ptr [5] & !\A_SPW_TOP|rx_data|wr_ptr [2]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Decoder0~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Decoder0~18 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Decoder0~18 .lut_mask = 64'h0000000008000000;
defparam \A_SPW_TOP|rx_data|Decoder0~18 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X31_Y7_N51
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector451~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector451~0_combout  = ( \A_SPW_TOP|rx_data|Decoder0~18_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|rx_data|state_data_write.01~q ) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(gnd),
        .datac(gnd),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Decoder0~18_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector451~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector451~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector451~0 .lut_mask = 64'h00000000AAFFAAFF;
defparam \A_SPW_TOP|rx_data|Selector451~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X32_Y7_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector451~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector451~1_combout  = ( \A_SPW_TOP|SPW|RX|rx_data_flag [8] & ( (!\A_SPW_TOP|rx_data|Selector451~0_combout  & (((\A_SPW_TOP|rx_data|mem[48][8]~q )))) # (\A_SPW_TOP|rx_data|Selector451~0_combout  & 
// (((!\A_SPW_TOP|rx_data|state_data_write.00~q )) # (\A_SPW_TOP|rx_data|Mux0~20_combout ))) ) ) # ( !\A_SPW_TOP|SPW|RX|rx_data_flag [8] & ( (!\A_SPW_TOP|rx_data|Selector451~0_combout  & (((\A_SPW_TOP|rx_data|mem[48][8]~q )))) # 
// (\A_SPW_TOP|rx_data|Selector451~0_combout  & (\A_SPW_TOP|rx_data|Mux0~20_combout  & (\A_SPW_TOP|rx_data|state_data_write.00~q ))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Selector451~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[48][8]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector451~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector451~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector451~1 .lut_mask = 64'h01F101F10DFD0DFD;
defparam \A_SPW_TOP|rx_data|Selector451~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X32_Y7_N47
dffeas \A_SPW_TOP|rx_data|mem[48][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector451~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[48][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[48][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[48][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y6_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Decoder0~16 (
// Equation(s):
// \A_SPW_TOP|rx_data|Decoder0~16_combout  = ( !\A_SPW_TOP|rx_data|wr_ptr [3] & ( !\A_SPW_TOP|rx_data|wr_ptr [0] & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & (!\A_SPW_TOP|rx_data|wr_ptr [2] & (!\A_SPW_TOP|rx_data|wr_ptr [1] & \A_SPW_TOP|rx_data|wr_ptr [4]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Decoder0~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Decoder0~16 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Decoder0~16 .lut_mask = 64'h0080000000000000;
defparam \A_SPW_TOP|rx_data|Decoder0~16 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y6_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector163~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector163~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.01~q  & ( \A_SPW_TOP|rx_data|Decoder0~16_combout  ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.01~q  & ( \A_SPW_TOP|rx_data|Decoder0~16_combout  & ( 
// !\A_SPW_TOP|rx_data|state_data_write.00~q  ) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .dataf(!\A_SPW_TOP|rx_data|Decoder0~16_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector163~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector163~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector163~0 .lut_mask = 64'h00000000AAAAFFFF;
defparam \A_SPW_TOP|rx_data|Selector163~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X32_Y7_N33
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector163~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector163~1_combout  = ( \A_SPW_TOP|SPW|RX|rx_data_flag [8] & ( (!\A_SPW_TOP|rx_data|Selector163~0_combout  & (((\A_SPW_TOP|rx_data|mem[16][8]~q )))) # (\A_SPW_TOP|rx_data|Selector163~0_combout  & 
// (((!\A_SPW_TOP|rx_data|state_data_write.00~q )) # (\A_SPW_TOP|rx_data|Mux0~20_combout ))) ) ) # ( !\A_SPW_TOP|SPW|RX|rx_data_flag [8] & ( (!\A_SPW_TOP|rx_data|Selector163~0_combout  & (((\A_SPW_TOP|rx_data|mem[16][8]~q )))) # 
// (\A_SPW_TOP|rx_data|Selector163~0_combout  & (\A_SPW_TOP|rx_data|Mux0~20_combout  & (\A_SPW_TOP|rx_data|state_data_write.00~q ))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[16][8]~q ),
        .datad(!\A_SPW_TOP|rx_data|Selector163~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector163~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector163~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector163~1 .lut_mask = 64'h0F110F110FDD0FDD;
defparam \A_SPW_TOP|rx_data|Selector163~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X32_Y7_N8
dffeas \A_SPW_TOP|rx_data|mem[16][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector163~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[16][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[16][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[16][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y8_N39
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Decoder0~22 (
// Equation(s):
// \A_SPW_TOP|rx_data|Decoder0~22_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [5] & ( !\A_SPW_TOP|rx_data|wr_ptr [1] & ( (\A_SPW_TOP|rx_data|wr_ptr [2] & (!\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|wr_ptr [4] & !\A_SPW_TOP|rx_data|wr_ptr [0]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Decoder0~22_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Decoder0~22 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Decoder0~22 .lut_mask = 64'h0000040000000000;
defparam \A_SPW_TOP|rx_data|Decoder0~22 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y8_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector487~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector487~0_combout  = ( \A_SPW_TOP|rx_data|Decoder0~22_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|rx_data|state_data_write.01~q ) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Decoder0~22_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector487~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector487~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector487~0 .lut_mask = 64'h00000000DDDDDDDD;
defparam \A_SPW_TOP|rx_data|Selector487~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X33_Y7_N57
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector487~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector487~1_combout  = ( \A_SPW_TOP|rx_data|mem[52][8]~q  & ( (!\A_SPW_TOP|rx_data|Selector487~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [8])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux0~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[52][8]~q  & ( (\A_SPW_TOP|rx_data|Selector487~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [8])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux0~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .datac(!\A_SPW_TOP|rx_data|Selector487~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[52][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector487~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector487~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector487~1 .lut_mask = 64'h02070207F2F7F2F7;
defparam \A_SPW_TOP|rx_data|Selector487~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X33_Y7_N26
dffeas \A_SPW_TOP|rx_data|mem[52][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector487~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[52][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[52][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[52][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X33_Y7_N45
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux0~2 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux0~2_combout  = ( \A_SPW_TOP|rx_data|mem[16][8]~q  & ( \A_SPW_TOP|rx_data|mem[52][8]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & (((!\A_SPW_TOP|rx_data|wr_ptr [2])) # (\A_SPW_TOP|rx_data|mem[20][8]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [5] 
// & (((\A_SPW_TOP|rx_data|wr_ptr [2]) # (\A_SPW_TOP|rx_data|mem[48][8]~q )))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[16][8]~q  & ( \A_SPW_TOP|rx_data|mem[52][8]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|mem[20][8]~q  & 
// ((\A_SPW_TOP|rx_data|wr_ptr [2])))) # (\A_SPW_TOP|rx_data|wr_ptr [5] & (((\A_SPW_TOP|rx_data|wr_ptr [2]) # (\A_SPW_TOP|rx_data|mem[48][8]~q )))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[16][8]~q  & ( !\A_SPW_TOP|rx_data|mem[52][8]~q  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [5] & (((!\A_SPW_TOP|rx_data|wr_ptr [2])) # (\A_SPW_TOP|rx_data|mem[20][8]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [5] & (((\A_SPW_TOP|rx_data|mem[48][8]~q  & !\A_SPW_TOP|rx_data|wr_ptr [2])))) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|mem[16][8]~q  & ( !\A_SPW_TOP|rx_data|mem[52][8]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|mem[20][8]~q  & ((\A_SPW_TOP|rx_data|wr_ptr [2])))) # (\A_SPW_TOP|rx_data|wr_ptr [5] & (((\A_SPW_TOP|rx_data|mem[48][8]~q  & 
// !\A_SPW_TOP|rx_data|wr_ptr [2])))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[20][8]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[48][8]~q ),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datae(!\A_SPW_TOP|rx_data|mem[16][8]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[52][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux0~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux0~2 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux0~2 .lut_mask = 64'h0350F350035FF35F;
defparam \A_SPW_TOP|rx_data|Mux0~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y8_N15
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Decoder0~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Decoder0~0_combout  = ( !\A_SPW_TOP|rx_data|wr_ptr [2] & ( !\A_SPW_TOP|rx_data|wr_ptr [3] & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & (!\A_SPW_TOP|rx_data|wr_ptr [5] & (!\A_SPW_TOP|rx_data|wr_ptr [1] & !\A_SPW_TOP|rx_data|wr_ptr [4]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Decoder0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Decoder0~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Decoder0~0 .lut_mask = 64'h8000000000000000;
defparam \A_SPW_TOP|rx_data|Decoder0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y8_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector19~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector19~0_combout  = ( \A_SPW_TOP|rx_data|Decoder0~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|rx_data|state_data_write.01~q ) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Decoder0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector19~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector19~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector19~0 .lut_mask = 64'h00000000DDDDDDDD;
defparam \A_SPW_TOP|rx_data|Selector19~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X36_Y7_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector19~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector19~1_combout  = ( \A_SPW_TOP|rx_data|Selector19~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [8])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux0~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector19~0_combout  & ( \A_SPW_TOP|rx_data|mem[0][8]~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[0][8]~q ),
        .datad(!\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector19~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector19~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector19~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector19~1 .lut_mask = 64'h0F0F0F0F44774477;
defparam \A_SPW_TOP|rx_data|Selector19~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X36_Y7_N5
dffeas \A_SPW_TOP|rx_data|mem[0][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector19~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[0][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[0][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[0][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y4_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Decoder0~6 (
// Equation(s):
// \A_SPW_TOP|rx_data|Decoder0~6_combout  = ( !\A_SPW_TOP|rx_data|wr_ptr [1] & ( \A_SPW_TOP|rx_data|wr_ptr [5] & ( (!\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|wr_ptr [2] & (!\A_SPW_TOP|rx_data|wr_ptr [3] & !\A_SPW_TOP|rx_data|wr_ptr [0]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Decoder0~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Decoder0~6 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Decoder0~6 .lut_mask = 64'h0000000020000000;
defparam \A_SPW_TOP|rx_data|Decoder0~6 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y4_N33
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector343~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector343~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.01~q  & ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( \A_SPW_TOP|rx_data|Decoder0~6_combout  ) ) ) # ( \A_SPW_TOP|rx_data|state_data_write.01~q  & ( 
// !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( \A_SPW_TOP|rx_data|Decoder0~6_combout  ) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.01~q  & ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( \A_SPW_TOP|rx_data|Decoder0~6_combout  ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|rx_data|Decoder0~6_combout ),
        .datac(gnd),
        .datad(gnd),
        .datae(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector343~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector343~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector343~0 .lut_mask = 64'h3333333300003333;
defparam \A_SPW_TOP|rx_data|Selector343~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X36_Y7_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector343~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector343~1_combout  = ( \A_SPW_TOP|SPW|RX|rx_data_flag [8] & ( (!\A_SPW_TOP|rx_data|Selector343~0_combout  & (((\A_SPW_TOP|rx_data|mem[36][8]~q )))) # (\A_SPW_TOP|rx_data|Selector343~0_combout  & 
// (((!\A_SPW_TOP|rx_data|state_data_write.00~q )) # (\A_SPW_TOP|rx_data|Mux0~20_combout ))) ) ) # ( !\A_SPW_TOP|SPW|RX|rx_data_flag [8] & ( (!\A_SPW_TOP|rx_data|Selector343~0_combout  & (((\A_SPW_TOP|rx_data|mem[36][8]~q )))) # 
// (\A_SPW_TOP|rx_data|Selector343~0_combout  & (\A_SPW_TOP|rx_data|Mux0~20_combout  & (\A_SPW_TOP|rx_data|state_data_write.00~q ))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Selector343~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[36][8]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector343~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector343~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector343~1 .lut_mask = 64'h01F101F10DFD0DFD;
defparam \A_SPW_TOP|rx_data|Selector343~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X36_Y7_N53
dffeas \A_SPW_TOP|rx_data|mem[36][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector343~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[36][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[36][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[36][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y8_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Decoder0~4 (
// Equation(s):
// \A_SPW_TOP|rx_data|Decoder0~4_combout  = ( !\A_SPW_TOP|rx_data|wr_ptr [0] & ( !\A_SPW_TOP|rx_data|wr_ptr [5] & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & (!\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|wr_ptr [2] & !\A_SPW_TOP|rx_data|wr_ptr [4]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Decoder0~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Decoder0~4 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Decoder0~4 .lut_mask = 64'h0800000000000000;
defparam \A_SPW_TOP|rx_data|Decoder0~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y8_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector55~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector55~0_combout  = ( \A_SPW_TOP|rx_data|Decoder0~4_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|rx_data|state_data_write.01~q ) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Decoder0~4_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector55~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector55~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector55~0 .lut_mask = 64'h00000000DDDDDDDD;
defparam \A_SPW_TOP|rx_data|Selector55~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y7_N15
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector55~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector55~1_combout  = ( \A_SPW_TOP|SPW|RX|rx_data_flag [8] & ( \A_SPW_TOP|rx_data|mem[4][8]~q  & ( (!\A_SPW_TOP|rx_data|Selector55~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|rx_data|Mux0~20_combout )) ) 
// ) ) # ( !\A_SPW_TOP|SPW|RX|rx_data_flag [8] & ( \A_SPW_TOP|rx_data|mem[4][8]~q  & ( (!\A_SPW_TOP|rx_data|Selector55~0_combout ) # ((\A_SPW_TOP|rx_data|Mux0~20_combout  & \A_SPW_TOP|rx_data|state_data_write.00~q )) ) ) ) # ( \A_SPW_TOP|SPW|RX|rx_data_flag 
// [8] & ( !\A_SPW_TOP|rx_data|mem[4][8]~q  & ( (\A_SPW_TOP|rx_data|Selector55~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|rx_data|Mux0~20_combout ))) ) ) ) # ( !\A_SPW_TOP|SPW|RX|rx_data_flag [8] & ( 
// !\A_SPW_TOP|rx_data|mem[4][8]~q  & ( (\A_SPW_TOP|rx_data|Selector55~0_combout  & (\A_SPW_TOP|rx_data|Mux0~20_combout  & \A_SPW_TOP|rx_data|state_data_write.00~q )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Selector55~0_combout ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .dataf(!\A_SPW_TOP|rx_data|mem[4][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector55~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector55~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector55~1 .lut_mask = 64'h00055505AAAFFFAF;
defparam \A_SPW_TOP|rx_data|Selector55~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y7_N8
dffeas \A_SPW_TOP|rx_data|mem[4][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector55~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[4][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[4][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[4][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y7_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Decoder0~2 (
// Equation(s):
// \A_SPW_TOP|rx_data|Decoder0~2_combout  = ( !\A_SPW_TOP|rx_data|wr_ptr [4] & ( !\A_SPW_TOP|rx_data|wr_ptr [0] & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|wr_ptr [5] & (!\A_SPW_TOP|rx_data|wr_ptr [2] & !\A_SPW_TOP|rx_data|wr_ptr [3]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Decoder0~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Decoder0~2 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Decoder0~2 .lut_mask = 64'h2000000000000000;
defparam \A_SPW_TOP|rx_data|Decoder0~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y7_N51
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector307~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector307~0_combout  = ( \A_SPW_TOP|rx_data|Decoder0~2_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|rx_data|state_data_write.01~q ) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(gnd),
        .datac(gnd),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Decoder0~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector307~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector307~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector307~0 .lut_mask = 64'h00000000AAFFAAFF;
defparam \A_SPW_TOP|rx_data|Selector307~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X36_Y7_N27
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector307~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector307~1_combout  = ( \A_SPW_TOP|rx_data|mem[32][8]~q  & ( (!\A_SPW_TOP|rx_data|Selector307~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [8]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux0~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[32][8]~q  & ( (\A_SPW_TOP|rx_data|Selector307~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [8]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux0~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Selector307~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[32][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector307~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector307~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector307~1 .lut_mask = 64'h010D010DF1FDF1FD;
defparam \A_SPW_TOP|rx_data|Selector307~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X36_Y7_N50
dffeas \A_SPW_TOP|rx_data|mem[32][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector307~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[32][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[32][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[32][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X36_Y7_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux0~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux0~0_combout  = ( \A_SPW_TOP|rx_data|mem[4][8]~q  & ( \A_SPW_TOP|rx_data|mem[32][8]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & (((\A_SPW_TOP|rx_data|wr_ptr [5])) # (\A_SPW_TOP|rx_data|mem[0][8]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [2] & 
// (((!\A_SPW_TOP|rx_data|wr_ptr [5]) # (\A_SPW_TOP|rx_data|mem[36][8]~q )))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[4][8]~q  & ( \A_SPW_TOP|rx_data|mem[32][8]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & (((\A_SPW_TOP|rx_data|wr_ptr [5])) # 
// (\A_SPW_TOP|rx_data|mem[0][8]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [2] & (((\A_SPW_TOP|rx_data|wr_ptr [5] & \A_SPW_TOP|rx_data|mem[36][8]~q )))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[4][8]~q  & ( !\A_SPW_TOP|rx_data|mem[32][8]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr 
// [2] & (\A_SPW_TOP|rx_data|mem[0][8]~q  & (!\A_SPW_TOP|rx_data|wr_ptr [5]))) # (\A_SPW_TOP|rx_data|wr_ptr [2] & (((!\A_SPW_TOP|rx_data|wr_ptr [5]) # (\A_SPW_TOP|rx_data|mem[36][8]~q )))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[4][8]~q  & ( 
// !\A_SPW_TOP|rx_data|mem[32][8]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|mem[0][8]~q  & (!\A_SPW_TOP|rx_data|wr_ptr [5]))) # (\A_SPW_TOP|rx_data|wr_ptr [2] & (((\A_SPW_TOP|rx_data|wr_ptr [5] & \A_SPW_TOP|rx_data|mem[36][8]~q )))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[0][8]~q ),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datad(!\A_SPW_TOP|rx_data|mem[36][8]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[4][8]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[32][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux0~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux0~0 .lut_mask = 64'h404370734C4F7C7F;
defparam \A_SPW_TOP|rx_data|Mux0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X31_Y7_N39
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Decoder0~32 (
// Equation(s):
// \A_SPW_TOP|rx_data|Decoder0~32_combout  = ( !\A_SPW_TOP|rx_data|wr_ptr [2] & ( !\A_SPW_TOP|rx_data|wr_ptr [0] & ( (\A_SPW_TOP|rx_data|wr_ptr [3] & (!\A_SPW_TOP|rx_data|wr_ptr [4] & (!\A_SPW_TOP|rx_data|wr_ptr [1] & !\A_SPW_TOP|rx_data|wr_ptr [5]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Decoder0~32_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Decoder0~32 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Decoder0~32 .lut_mask = 64'h4000000000000000;
defparam \A_SPW_TOP|rx_data|Decoder0~32 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X32_Y7_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector91~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector91~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.01~q  & ( \A_SPW_TOP|rx_data|Decoder0~32_combout  ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.01~q  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// \A_SPW_TOP|rx_data|Decoder0~32_combout ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Decoder0~32_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector91~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector91~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector91~0 .lut_mask = 64'h0C0C0C0C0F0F0F0F;
defparam \A_SPW_TOP|rx_data|Selector91~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X32_Y7_N21
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector91~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector91~1_combout  = ( \A_SPW_TOP|rx_data|mem[8][8]~q  & ( (!\A_SPW_TOP|rx_data|Selector91~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [8]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux0~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[8][8]~q  & ( (\A_SPW_TOP|rx_data|Selector91~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [8]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux0~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .datac(!\A_SPW_TOP|rx_data|Selector91~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[8][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector91~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector91~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector91~1 .lut_mask = 64'h03050305F3F5F3F5;
defparam \A_SPW_TOP|rx_data|Selector91~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X32_Y7_N53
dffeas \A_SPW_TOP|rx_data|mem[8][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector91~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[8][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[8][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[8][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y7_N33
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Decoder0~34 (
// Equation(s):
// \A_SPW_TOP|rx_data|Decoder0~34_combout  = ( !\A_SPW_TOP|rx_data|wr_ptr [4] & ( \A_SPW_TOP|rx_data|wr_ptr [3] & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & (!\A_SPW_TOP|rx_data|wr_ptr [1] & (!\A_SPW_TOP|rx_data|wr_ptr [2] & \A_SPW_TOP|rx_data|wr_ptr [5]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Decoder0~34_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Decoder0~34 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Decoder0~34 .lut_mask = 64'h0000000000800000;
defparam \A_SPW_TOP|rx_data|Decoder0~34 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y7_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector379~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector379~0_combout  = ( \A_SPW_TOP|rx_data|Decoder0~34_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|rx_data|state_data_write.01~q ) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Decoder0~34_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector379~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector379~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector379~0 .lut_mask = 64'h00000000AFAFAFAF;
defparam \A_SPW_TOP|rx_data|Selector379~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X32_Y7_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector379~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector379~1_combout  = ( \A_SPW_TOP|SPW|RX|rx_data_flag [8] & ( (!\A_SPW_TOP|rx_data|Selector379~0_combout  & (((\A_SPW_TOP|rx_data|mem[40][8]~q )))) # (\A_SPW_TOP|rx_data|Selector379~0_combout  & 
// (((!\A_SPW_TOP|rx_data|state_data_write.00~q )) # (\A_SPW_TOP|rx_data|Mux0~20_combout ))) ) ) # ( !\A_SPW_TOP|SPW|RX|rx_data_flag [8] & ( (!\A_SPW_TOP|rx_data|Selector379~0_combout  & (((\A_SPW_TOP|rx_data|mem[40][8]~q )))) # 
// (\A_SPW_TOP|rx_data|Selector379~0_combout  & (\A_SPW_TOP|rx_data|Mux0~20_combout  & (\A_SPW_TOP|rx_data|state_data_write.00~q ))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[40][8]~q ),
        .datad(!\A_SPW_TOP|rx_data|Selector379~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector379~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector379~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector379~1 .lut_mask = 64'h0F110F110FDD0FDD;
defparam \A_SPW_TOP|rx_data|Selector379~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X32_Y7_N41
dffeas \A_SPW_TOP|rx_data|mem[40][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector379~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[40][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[40][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[40][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y4_N57
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Decoder0~36 (
// Equation(s):
// \A_SPW_TOP|rx_data|Decoder0~36_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [3] & ( !\A_SPW_TOP|rx_data|wr_ptr [5] & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & (!\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|wr_ptr [2] & !\A_SPW_TOP|rx_data|wr_ptr [4]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Decoder0~36_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Decoder0~36 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Decoder0~36 .lut_mask = 64'h0000080000000000;
defparam \A_SPW_TOP|rx_data|Decoder0~36 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y4_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector127~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector127~0_combout  = ( \A_SPW_TOP|rx_data|Decoder0~36_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|rx_data|state_data_write.01~q ) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(gnd),
        .datac(gnd),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Decoder0~36_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector127~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector127~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector127~0 .lut_mask = 64'h00000000AAFFAAFF;
defparam \A_SPW_TOP|rx_data|Selector127~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X33_Y7_N39
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector127~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector127~1_combout  = ( \A_SPW_TOP|rx_data|Selector127~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [8]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux0~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector127~0_combout  & ( \A_SPW_TOP|rx_data|mem[12][8]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[12][8]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector127~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector127~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector127~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector127~1 .lut_mask = 64'h00FF00FF35353535;
defparam \A_SPW_TOP|rx_data|Selector127~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X33_Y7_N23
dffeas \A_SPW_TOP|rx_data|mem[12][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector127~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[12][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[12][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[12][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X36_Y6_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Decoder0~38 (
// Equation(s):
// \A_SPW_TOP|rx_data|Decoder0~38_combout  = ( !\A_SPW_TOP|rx_data|wr_ptr [0] & ( \A_SPW_TOP|rx_data|wr_ptr [5] & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|wr_ptr [3] & (!\A_SPW_TOP|rx_data|wr_ptr [4] & \A_SPW_TOP|rx_data|wr_ptr [2]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Decoder0~38_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Decoder0~38 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Decoder0~38 .lut_mask = 64'h0000000000200000;
defparam \A_SPW_TOP|rx_data|Decoder0~38 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X36_Y6_N51
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector415~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector415~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (\A_SPW_TOP|rx_data|Decoder0~38_combout  & \A_SPW_TOP|rx_data|state_data_write.01~q ) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( 
// \A_SPW_TOP|rx_data|Decoder0~38_combout  ) )

        .dataa(!\A_SPW_TOP|rx_data|Decoder0~38_combout ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector415~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector415~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector415~0 .lut_mask = 64'h5555050555550505;
defparam \A_SPW_TOP|rx_data|Selector415~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X33_Y7_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector415~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector415~1_combout  = ( \A_SPW_TOP|rx_data|Selector415~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [8])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux0~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector415~0_combout  & ( \A_SPW_TOP|rx_data|mem[44][8]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .datac(!\A_SPW_TOP|rx_data|mem[44][8]~q ),
        .datad(!\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector415~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector415~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector415~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector415~1 .lut_mask = 64'h0F0F0F0F22772277;
defparam \A_SPW_TOP|rx_data|Selector415~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X33_Y7_N50
dffeas \A_SPW_TOP|rx_data|mem[44][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector415~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[44][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[44][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[44][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X33_Y7_N27
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux0~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux0~1_combout  = ( \A_SPW_TOP|rx_data|mem[12][8]~q  & ( \A_SPW_TOP|rx_data|mem[44][8]~q  & ( ((!\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|mem[8][8]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [5] & ((\A_SPW_TOP|rx_data|mem[40][8]~q 
// )))) # (\A_SPW_TOP|rx_data|wr_ptr [2]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[12][8]~q  & ( \A_SPW_TOP|rx_data|mem[44][8]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|mem[8][8]~q  & ((!\A_SPW_TOP|rx_data|wr_ptr [2])))) # 
// (\A_SPW_TOP|rx_data|wr_ptr [5] & (((\A_SPW_TOP|rx_data|wr_ptr [2]) # (\A_SPW_TOP|rx_data|mem[40][8]~q )))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[12][8]~q  & ( !\A_SPW_TOP|rx_data|mem[44][8]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & (((\A_SPW_TOP|rx_data|wr_ptr 
// [2])) # (\A_SPW_TOP|rx_data|mem[8][8]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [5] & (((\A_SPW_TOP|rx_data|mem[40][8]~q  & !\A_SPW_TOP|rx_data|wr_ptr [2])))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[12][8]~q  & ( !\A_SPW_TOP|rx_data|mem[44][8]~q  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [2] & ((!\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|mem[8][8]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [5] & ((\A_SPW_TOP|rx_data|mem[40][8]~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[8][8]~q ),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datac(!\A_SPW_TOP|rx_data|mem[40][8]~q ),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datae(!\A_SPW_TOP|rx_data|mem[12][8]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[44][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux0~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux0~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux0~1 .lut_mask = 64'h470047CC473347FF;
defparam \A_SPW_TOP|rx_data|Mux0~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X33_Y7_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux0~4 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux0~4_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [4] & ( \A_SPW_TOP|rx_data|Mux0~1_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [3] & ((\A_SPW_TOP|rx_data|Mux0~2_combout ))) # (\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|Mux0~3_combout 
// )) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [4] & ( \A_SPW_TOP|rx_data|Mux0~1_combout  & ( (\A_SPW_TOP|rx_data|wr_ptr [3]) # (\A_SPW_TOP|rx_data|Mux0~0_combout ) ) ) ) # ( \A_SPW_TOP|rx_data|wr_ptr [4] & ( !\A_SPW_TOP|rx_data|Mux0~1_combout  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [3] & ((\A_SPW_TOP|rx_data|Mux0~2_combout ))) # (\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|Mux0~3_combout )) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [4] & ( !\A_SPW_TOP|rx_data|Mux0~1_combout  & ( 
// (\A_SPW_TOP|rx_data|Mux0~0_combout  & !\A_SPW_TOP|rx_data|wr_ptr [3]) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux0~3_combout ),
        .datab(!\A_SPW_TOP|rx_data|Mux0~2_combout ),
        .datac(!\A_SPW_TOP|rx_data|Mux0~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .dataf(!\A_SPW_TOP|rx_data|Mux0~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux0~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux0~4 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux0~4 .lut_mask = 64'h0F0033550FFF3355;
defparam \A_SPW_TOP|rx_data|Mux0~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y8_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Decoder0~47 (
// Equation(s):
// \A_SPW_TOP|rx_data|Decoder0~47_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [0] & ( \A_SPW_TOP|rx_data|wr_ptr [3] & ( (\A_SPW_TOP|rx_data|wr_ptr [5] & (!\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|wr_ptr [2] & \A_SPW_TOP|rx_data|wr_ptr [1]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Decoder0~47_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Decoder0~47 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Decoder0~47 .lut_mask = 64'h0000000000000004;
defparam \A_SPW_TOP|rx_data|Decoder0~47 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y8_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector442~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector442~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( \A_SPW_TOP|rx_data|Decoder0~47_combout  & ( \A_SPW_TOP|rx_data|state_data_write.01~q  ) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( 
// \A_SPW_TOP|rx_data|Decoder0~47_combout  ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .dataf(!\A_SPW_TOP|rx_data|Decoder0~47_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector442~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector442~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector442~0 .lut_mask = 64'h00000000FFFF5555;
defparam \A_SPW_TOP|rx_data|Selector442~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X36_Y5_N15
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector442~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector442~1_combout  = ( \A_SPW_TOP|rx_data|Selector442~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [8])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux0~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector442~0_combout  & ( \A_SPW_TOP|rx_data|mem[47][8]~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .datab(!\A_SPW_TOP|rx_data|mem[47][8]~q ),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector442~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector442~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector442~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector442~1 .lut_mask = 64'h33333333505F505F;
defparam \A_SPW_TOP|rx_data|Selector442~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X36_Y5_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|mem[47][8]~feeder (
// Equation(s):
// \A_SPW_TOP|rx_data|mem[47][8]~feeder_combout  = ( \A_SPW_TOP|rx_data|Selector442~1_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector442~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|mem[47][8]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[47][8]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|mem[47][8]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|rx_data|mem[47][8]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X36_Y5_N44
dffeas \A_SPW_TOP|rx_data|mem[47][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|rx_data|mem[47][8]~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[47][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[47][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[47][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X36_Y6_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Decoder0~63 (
// Equation(s):
// \A_SPW_TOP|rx_data|Decoder0~63_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [0] & ( \A_SPW_TOP|rx_data|wr_ptr [5] & ( (\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|wr_ptr [4] & \A_SPW_TOP|rx_data|wr_ptr [2]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Decoder0~63_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Decoder0~63 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Decoder0~63 .lut_mask = 64'h0000000000000001;
defparam \A_SPW_TOP|rx_data|Decoder0~63 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X36_Y6_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector586~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector586~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (\A_SPW_TOP|rx_data|Decoder0~63_combout  & \A_SPW_TOP|rx_data|state_data_write.01~q ) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( 
// \A_SPW_TOP|rx_data|Decoder0~63_combout  ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|rx_data|Decoder0~63_combout ),
        .datac(gnd),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .datae(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector586~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector586~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector586~0 .lut_mask = 64'h3333003333330033;
defparam \A_SPW_TOP|rx_data|Selector586~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X35_Y9_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector586~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector586~1_combout  = ( \A_SPW_TOP|rx_data|mem[63][8]~q  & ( (!\A_SPW_TOP|rx_data|Selector586~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [8])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux0~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[63][8]~q  & ( (\A_SPW_TOP|rx_data|Selector586~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [8])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux0~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Selector586~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[63][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector586~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector586~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector586~1 .lut_mask = 64'h04070407F4F7F4F7;
defparam \A_SPW_TOP|rx_data|Selector586~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X35_Y9_N41
dffeas \A_SPW_TOP|rx_data|mem[63][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector586~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[63][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[63][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[63][8] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X32_Y9_N39
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Decoder0~31 (
// Equation(s):
// \A_SPW_TOP|rx_data|Decoder0~31_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [5] & ( !\A_SPW_TOP|rx_data|wr_ptr [3] & ( (\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|wr_ptr [4] & \A_SPW_TOP|rx_data|wr_ptr [2]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Decoder0~31_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Decoder0~31 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Decoder0~31 .lut_mask = 64'h0000000100000000;
defparam \A_SPW_TOP|rx_data|Decoder0~31 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X32_Y9_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector514~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector514~0_combout  = ( \A_SPW_TOP|rx_data|Decoder0~31_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|rx_data|state_data_write.01~q ) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Decoder0~31_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector514~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector514~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector514~0 .lut_mask = 64'h00000000DDDDDDDD;
defparam \A_SPW_TOP|rx_data|Selector514~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X36_Y9_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector514~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector514~1_combout  = ( \A_SPW_TOP|SPW|RX|rx_data_flag [8] & ( (!\A_SPW_TOP|rx_data|Selector514~0_combout  & (\A_SPW_TOP|rx_data|mem[55][8]~q )) # (\A_SPW_TOP|rx_data|Selector514~0_combout  & 
// (((!\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|rx_data|Mux0~20_combout )))) ) ) # ( !\A_SPW_TOP|SPW|RX|rx_data_flag [8] & ( (!\A_SPW_TOP|rx_data|Selector514~0_combout  & (\A_SPW_TOP|rx_data|mem[55][8]~q )) # 
// (\A_SPW_TOP|rx_data|Selector514~0_combout  & (((\A_SPW_TOP|rx_data|state_data_write.00~q  & \A_SPW_TOP|rx_data|Mux0~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[55][8]~q ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .datad(!\A_SPW_TOP|rx_data|Selector514~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector514~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector514~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector514~1 .lut_mask = 64'h5503550355CF55CF;
defparam \A_SPW_TOP|rx_data|Selector514~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X35_Y9_N32
dffeas \A_SPW_TOP|rx_data|mem[55][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector514~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[55][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[55][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[55][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y4_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Decoder0~15 (
// Equation(s):
// \A_SPW_TOP|rx_data|Decoder0~15_combout  = ( !\A_SPW_TOP|rx_data|wr_ptr [3] & ( \A_SPW_TOP|rx_data|wr_ptr [5] & ( (!\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|wr_ptr [1] & \A_SPW_TOP|rx_data|wr_ptr [0]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Decoder0~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Decoder0~15 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Decoder0~15 .lut_mask = 64'h0000000000020000;
defparam \A_SPW_TOP|rx_data|Decoder0~15 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y4_N39
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector370~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector370~0_combout  = (\A_SPW_TOP|rx_data|Decoder0~15_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|rx_data|state_data_write.01~q )))

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .datac(!\A_SPW_TOP|rx_data|Decoder0~15_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector370~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector370~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector370~0 .lut_mask = 64'h0B0B0B0B0B0B0B0B;
defparam \A_SPW_TOP|rx_data|Selector370~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X35_Y9_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector370~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector370~1_combout  = ( \A_SPW_TOP|rx_data|Mux0~20_combout  & ( (!\A_SPW_TOP|rx_data|Selector370~0_combout  & (((\A_SPW_TOP|rx_data|mem[39][8]~q )))) # (\A_SPW_TOP|rx_data|Selector370~0_combout  & 
// (((\A_SPW_TOP|rx_data|state_data_write.00~q )) # (\A_SPW_TOP|SPW|RX|rx_data_flag [8]))) ) ) # ( !\A_SPW_TOP|rx_data|Mux0~20_combout  & ( (!\A_SPW_TOP|rx_data|Selector370~0_combout  & (((\A_SPW_TOP|rx_data|mem[39][8]~q )))) # 
// (\A_SPW_TOP|rx_data|Selector370~0_combout  & (\A_SPW_TOP|SPW|RX|rx_data_flag [8] & (!\A_SPW_TOP|rx_data|state_data_write.00~q ))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[39][8]~q ),
        .datad(!\A_SPW_TOP|rx_data|Selector370~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector370~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector370~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector370~1 .lut_mask = 64'h0F440F440F770F77;
defparam \A_SPW_TOP|rx_data|Selector370~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X35_Y9_N23
dffeas \A_SPW_TOP|rx_data|mem[39][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector370~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[39][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[39][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[39][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X35_Y9_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux0~18 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux0~18_combout  = ( \A_SPW_TOP|rx_data|mem[39][8]~q  & ( \A_SPW_TOP|rx_data|wr_ptr [4] & ( (!\A_SPW_TOP|rx_data|wr_ptr [3] & ((\A_SPW_TOP|rx_data|mem[55][8]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|mem[63][8]~q )) ) 
// ) ) # ( !\A_SPW_TOP|rx_data|mem[39][8]~q  & ( \A_SPW_TOP|rx_data|wr_ptr [4] & ( (!\A_SPW_TOP|rx_data|wr_ptr [3] & ((\A_SPW_TOP|rx_data|mem[55][8]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|mem[63][8]~q )) ) ) ) # ( 
// \A_SPW_TOP|rx_data|mem[39][8]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [4] & ( (!\A_SPW_TOP|rx_data|wr_ptr [3]) # (\A_SPW_TOP|rx_data|mem[47][8]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[39][8]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [4] & ( 
// (\A_SPW_TOP|rx_data|mem[47][8]~q  & \A_SPW_TOP|rx_data|wr_ptr [3]) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[47][8]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[63][8]~q ),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datad(!\A_SPW_TOP|rx_data|mem[55][8]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[39][8]~q ),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux0~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux0~18 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux0~18 .lut_mask = 64'h0505F5F503F303F3;
defparam \A_SPW_TOP|rx_data|Mux0~18 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X33_Y4_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Decoder0~29 (
// Equation(s):
// \A_SPW_TOP|rx_data|Decoder0~29_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [2] & ( !\A_SPW_TOP|rx_data|wr_ptr [5] & ( (\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|wr_ptr [1] & (!\A_SPW_TOP|rx_data|wr_ptr [3] & \A_SPW_TOP|rx_data|wr_ptr [4]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Decoder0~29_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Decoder0~29 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Decoder0~29 .lut_mask = 64'h0000001000000000;
defparam \A_SPW_TOP|rx_data|Decoder0~29 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X33_Y4_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector226~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector226~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.01~q  & ( \A_SPW_TOP|rx_data|Decoder0~29_combout  ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.01~q  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// \A_SPW_TOP|rx_data|Decoder0~29_combout ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Decoder0~29_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector226~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector226~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector226~0 .lut_mask = 64'h0C0C0C0C0F0F0F0F;
defparam \A_SPW_TOP|rx_data|Selector226~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X33_Y8_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector226~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector226~1_combout  = ( \A_SPW_TOP|rx_data|mem[23][8]~q  & ( \A_SPW_TOP|SPW|RX|rx_data_flag [8] & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q ) # ((!\A_SPW_TOP|rx_data|Selector226~0_combout ) # (\A_SPW_TOP|rx_data|Mux0~20_combout )) 
// ) ) ) # ( !\A_SPW_TOP|rx_data|mem[23][8]~q  & ( \A_SPW_TOP|SPW|RX|rx_data_flag [8] & ( (\A_SPW_TOP|rx_data|Selector226~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|rx_data|Mux0~20_combout ))) ) ) ) # ( 
// \A_SPW_TOP|rx_data|mem[23][8]~q  & ( !\A_SPW_TOP|SPW|RX|rx_data_flag [8] & ( (!\A_SPW_TOP|rx_data|Selector226~0_combout ) # ((\A_SPW_TOP|rx_data|state_data_write.00~q  & \A_SPW_TOP|rx_data|Mux0~20_combout )) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[23][8]~q  & ( 
// !\A_SPW_TOP|SPW|RX|rx_data_flag [8] & ( (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux0~20_combout  & \A_SPW_TOP|rx_data|Selector226~0_combout )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector226~0_combout ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|rx_data|mem[23][8]~q ),
        .dataf(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector226~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector226~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector226~1 .lut_mask = 64'h0101F1F10B0BFBFB;
defparam \A_SPW_TOP|rx_data|Selector226~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X33_Y8_N23
dffeas \A_SPW_TOP|rx_data|mem[23][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector226~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[23][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[23][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[23][8] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X32_Y9_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Decoder0~55 (
// Equation(s):
// \A_SPW_TOP|rx_data|Decoder0~55_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [3] & ( !\A_SPW_TOP|rx_data|wr_ptr [5] & ( (\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|wr_ptr [2] & \A_SPW_TOP|rx_data|wr_ptr [4]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Decoder0~55_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Decoder0~55 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Decoder0~55 .lut_mask = 64'h0000000100000000;
defparam \A_SPW_TOP|rx_data|Decoder0~55 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X32_Y9_N27
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector298~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector298~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.01~q  & ( \A_SPW_TOP|rx_data|Decoder0~55_combout  ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.01~q  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// \A_SPW_TOP|rx_data|Decoder0~55_combout ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|Decoder0~55_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector298~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector298~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector298~0 .lut_mask = 64'h00F000F000FF00FF;
defparam \A_SPW_TOP|rx_data|Selector298~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X32_Y9_N57
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector298~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector298~1_combout  = ( \A_SPW_TOP|rx_data|mem[31][8]~q  & ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector298~0_combout ) # (\A_SPW_TOP|rx_data|Mux0~20_combout ) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|mem[31][8]~q  & ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (\A_SPW_TOP|rx_data|Selector298~0_combout  & \A_SPW_TOP|rx_data|Mux0~20_combout ) ) ) ) # ( \A_SPW_TOP|rx_data|mem[31][8]~q  & ( !\A_SPW_TOP|rx_data|state_data_write.00~q  
// & ( (!\A_SPW_TOP|rx_data|Selector298~0_combout ) # (\A_SPW_TOP|SPW|RX|rx_data_flag [8]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[31][8]~q  & ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( (\A_SPW_TOP|rx_data|Selector298~0_combout  & 
// \A_SPW_TOP|SPW|RX|rx_data_flag [8]) ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|rx_data|Selector298~0_combout ),
        .datac(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .datad(!\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .datae(!\A_SPW_TOP|rx_data|mem[31][8]~q ),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector298~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector298~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector298~1 .lut_mask = 64'h0303CFCF0033CCFF;
defparam \A_SPW_TOP|rx_data|Selector298~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X35_Y9_N29
dffeas \A_SPW_TOP|rx_data|mem[31][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector298~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[31][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[31][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[31][8] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y7_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Decoder0~45 (
// Equation(s):
// \A_SPW_TOP|rx_data|Decoder0~45_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [0] & ( \A_SPW_TOP|rx_data|wr_ptr [3] & ( (!\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|wr_ptr [2] & !\A_SPW_TOP|rx_data|wr_ptr [5]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Decoder0~45_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Decoder0~45 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Decoder0~45 .lut_mask = 64'h0000000000000200;
defparam \A_SPW_TOP|rx_data|Decoder0~45 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y7_N51
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector154~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector154~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( \A_SPW_TOP|rx_data|state_data_write.01~q  & ( \A_SPW_TOP|rx_data|Decoder0~45_combout  ) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( 
// \A_SPW_TOP|rx_data|state_data_write.01~q  & ( \A_SPW_TOP|rx_data|Decoder0~45_combout  ) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( !\A_SPW_TOP|rx_data|state_data_write.01~q  & ( \A_SPW_TOP|rx_data|Decoder0~45_combout  ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Decoder0~45_combout ),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector154~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector154~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector154~0 .lut_mask = 64'h5555000055555555;
defparam \A_SPW_TOP|rx_data|Selector154~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X36_Y9_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector154~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector154~1_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( \A_SPW_TOP|rx_data|mem[15][8]~q  & ( (!\A_SPW_TOP|rx_data|Selector154~0_combout ) # (\A_SPW_TOP|rx_data|Mux0~20_combout ) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( \A_SPW_TOP|rx_data|mem[15][8]~q  & ( (!\A_SPW_TOP|rx_data|Selector154~0_combout ) # (\A_SPW_TOP|SPW|RX|rx_data_flag [8]) ) ) ) # ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( 
// !\A_SPW_TOP|rx_data|mem[15][8]~q  & ( (\A_SPW_TOP|rx_data|Mux0~20_combout  & \A_SPW_TOP|rx_data|Selector154~0_combout ) ) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( !\A_SPW_TOP|rx_data|mem[15][8]~q  & ( 
// (\A_SPW_TOP|rx_data|Selector154~0_combout  & \A_SPW_TOP|SPW|RX|rx_data_flag [8]) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .datab(!\A_SPW_TOP|rx_data|Selector154~0_combout ),
        .datac(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .datad(gnd),
        .datae(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[15][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector154~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector154~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector154~1 .lut_mask = 64'h03031111CFCFDDDD;
defparam \A_SPW_TOP|rx_data|Selector154~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X35_Y9_N11
dffeas \A_SPW_TOP|rx_data|mem[15][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector154~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[15][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[15][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[15][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y4_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Decoder0~13 (
// Equation(s):
// \A_SPW_TOP|rx_data|Decoder0~13_combout  = ( !\A_SPW_TOP|rx_data|wr_ptr [3] & ( !\A_SPW_TOP|rx_data|wr_ptr [5] & ( (!\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|wr_ptr [1] & \A_SPW_TOP|rx_data|wr_ptr [0]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Decoder0~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Decoder0~13 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Decoder0~13 .lut_mask = 64'h0002000000000000;
defparam \A_SPW_TOP|rx_data|Decoder0~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y4_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector82~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector82~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.01~q  & ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( \A_SPW_TOP|rx_data|Decoder0~13_combout  ) ) ) # ( \A_SPW_TOP|rx_data|state_data_write.01~q  & ( 
// !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( \A_SPW_TOP|rx_data|Decoder0~13_combout  ) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.01~q  & ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( \A_SPW_TOP|rx_data|Decoder0~13_combout  ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|rx_data|Decoder0~13_combout ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector82~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector82~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector82~0 .lut_mask = 64'h0F0F0F0F00000F0F;
defparam \A_SPW_TOP|rx_data|Selector82~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X35_Y9_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector82~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector82~1_combout  = ( \A_SPW_TOP|rx_data|Selector82~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [8])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux0~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector82~0_combout  & ( \A_SPW_TOP|rx_data|mem[7][8]~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[7][8]~q ),
        .datad(!\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector82~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector82~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector82~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector82~1 .lut_mask = 64'h0F0F0F0F44774477;
defparam \A_SPW_TOP|rx_data|Selector82~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X35_Y9_N53
dffeas \A_SPW_TOP|rx_data|mem[7][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector82~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[7][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[7][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[7][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X35_Y9_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux0~17 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux0~17_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [3] & ( \A_SPW_TOP|rx_data|mem[7][8]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|mem[15][8]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[31][8]~q )) ) 
// ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [3] & ( \A_SPW_TOP|rx_data|mem[7][8]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [4]) # (\A_SPW_TOP|rx_data|mem[23][8]~q ) ) ) ) # ( \A_SPW_TOP|rx_data|wr_ptr [3] & ( !\A_SPW_TOP|rx_data|mem[7][8]~q  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|mem[15][8]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[31][8]~q )) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [3] & ( !\A_SPW_TOP|rx_data|mem[7][8]~q  & ( 
// (\A_SPW_TOP|rx_data|mem[23][8]~q  & \A_SPW_TOP|rx_data|wr_ptr [4]) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[23][8]~q ),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datac(!\A_SPW_TOP|rx_data|mem[31][8]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[15][8]~q ),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .dataf(!\A_SPW_TOP|rx_data|mem[7][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux0~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux0~17 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux0~17 .lut_mask = 64'h111103CFDDDD03CF;
defparam \A_SPW_TOP|rx_data|Mux0~17 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y6_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Decoder0~9 (
// Equation(s):
// \A_SPW_TOP|rx_data|Decoder0~9_combout  = ( !\A_SPW_TOP|rx_data|wr_ptr [3] & ( \A_SPW_TOP|rx_data|wr_ptr [0] & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & (!\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|wr_ptr [1] & !\A_SPW_TOP|rx_data|wr_ptr [4]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Decoder0~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Decoder0~9 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Decoder0~9 .lut_mask = 64'h0000000008000000;
defparam \A_SPW_TOP|rx_data|Decoder0~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y6_N39
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector46~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector46~0_combout  = ( \A_SPW_TOP|rx_data|Decoder0~9_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|rx_data|state_data_write.01~q ) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Decoder0~9_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector46~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector46~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector46~0 .lut_mask = 64'h00000000AFAFAFAF;
defparam \A_SPW_TOP|rx_data|Selector46~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y9_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector46~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector46~1_combout  = ( \A_SPW_TOP|rx_data|mem[3][8]~q  & ( (!\A_SPW_TOP|rx_data|Selector46~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [8])) # (\A_SPW_TOP|rx_data|state_data_write.00~q 
//  & ((\A_SPW_TOP|rx_data|Mux0~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[3][8]~q  & ( (\A_SPW_TOP|rx_data|Selector46~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [8])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux0~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Selector46~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[3][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector46~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector46~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector46~1 .lut_mask = 64'h04070407F4F7F4F7;
defparam \A_SPW_TOP|rx_data|Selector46~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y9_N8
dffeas \A_SPW_TOP|rx_data|mem[3][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector46~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[3][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[3][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[3][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X35_Y4_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Decoder0~41 (
// Equation(s):
// \A_SPW_TOP|rx_data|Decoder0~41_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [1] & ( !\A_SPW_TOP|rx_data|wr_ptr [5] & ( (\A_SPW_TOP|rx_data|wr_ptr [0] & (!\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|wr_ptr [3] & !\A_SPW_TOP|rx_data|wr_ptr [4]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Decoder0~41_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Decoder0~41 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Decoder0~41 .lut_mask = 64'h0000040000000000;
defparam \A_SPW_TOP|rx_data|Decoder0~41 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X35_Y4_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector118~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector118~0_combout  = ( \A_SPW_TOP|rx_data|Decoder0~41_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|rx_data|state_data_write.01~q ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|rx_data|Decoder0~41_combout ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector118~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector118~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector118~0 .lut_mask = 64'h0000CFCF0000CFCF;
defparam \A_SPW_TOP|rx_data|Selector118~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y9_N21
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector118~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector118~1_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( \A_SPW_TOP|rx_data|mem[11][8]~q  & ( (!\A_SPW_TOP|rx_data|Selector118~0_combout ) # (\A_SPW_TOP|rx_data|Mux0~20_combout ) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( \A_SPW_TOP|rx_data|mem[11][8]~q  & ( (!\A_SPW_TOP|rx_data|Selector118~0_combout ) # (\A_SPW_TOP|SPW|RX|rx_data_flag [8]) ) ) ) # ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( 
// !\A_SPW_TOP|rx_data|mem[11][8]~q  & ( (\A_SPW_TOP|rx_data|Selector118~0_combout  & \A_SPW_TOP|rx_data|Mux0~20_combout ) ) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( !\A_SPW_TOP|rx_data|mem[11][8]~q  & ( 
// (\A_SPW_TOP|rx_data|Selector118~0_combout  & \A_SPW_TOP|SPW|RX|rx_data_flag [8]) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Selector118~0_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .datac(!\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[11][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector118~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector118~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector118~1 .lut_mask = 64'h11110505BBBBAFAF;
defparam \A_SPW_TOP|rx_data|Selector118~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y9_N20
dffeas \A_SPW_TOP|rx_data|mem[11][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector118~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[11][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[11][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[11][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X35_Y4_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Decoder0~53 (
// Equation(s):
// \A_SPW_TOP|rx_data|Decoder0~53_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [3] & ( !\A_SPW_TOP|rx_data|wr_ptr [5] & ( (\A_SPW_TOP|rx_data|wr_ptr [0] & (!\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|wr_ptr [1] & \A_SPW_TOP|rx_data|wr_ptr [4]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Decoder0~53_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Decoder0~53 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Decoder0~53 .lut_mask = 64'h0000000400000000;
defparam \A_SPW_TOP|rx_data|Decoder0~53 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X35_Y4_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector262~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector262~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (\A_SPW_TOP|rx_data|Decoder0~53_combout  & \A_SPW_TOP|rx_data|state_data_write.01~q ) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( 
// \A_SPW_TOP|rx_data|Decoder0~53_combout  ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|rx_data|Decoder0~53_combout ),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector262~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector262~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector262~0 .lut_mask = 64'h3333333303030303;
defparam \A_SPW_TOP|rx_data|Selector262~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y9_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector262~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector262~1_combout  = ( \A_SPW_TOP|rx_data|Mux0~20_combout  & ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (\A_SPW_TOP|rx_data|mem[27][8]~q ) # (\A_SPW_TOP|rx_data|Selector262~0_combout ) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|Mux0~20_combout  & ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector262~0_combout  & \A_SPW_TOP|rx_data|mem[27][8]~q ) ) ) ) # ( \A_SPW_TOP|rx_data|Mux0~20_combout  & ( 
// !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector262~0_combout  & ((\A_SPW_TOP|rx_data|mem[27][8]~q ))) # (\A_SPW_TOP|rx_data|Selector262~0_combout  & (\A_SPW_TOP|SPW|RX|rx_data_flag [8])) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|Mux0~20_combout  & ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector262~0_combout  & ((\A_SPW_TOP|rx_data|mem[27][8]~q ))) # (\A_SPW_TOP|rx_data|Selector262~0_combout  & (\A_SPW_TOP|SPW|RX|rx_data_flag 
// [8])) ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|rx_data|Selector262~0_combout ),
        .datac(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .datad(!\A_SPW_TOP|rx_data|mem[27][8]~q ),
        .datae(!\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector262~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector262~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector262~1 .lut_mask = 64'h03CF03CF00CC33FF;
defparam \A_SPW_TOP|rx_data|Selector262~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y9_N41
dffeas \A_SPW_TOP|rx_data|mem[27][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector262~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[27][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[27][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[27][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y7_N21
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Decoder0~25 (
// Equation(s):
// \A_SPW_TOP|rx_data|Decoder0~25_combout  = ( !\A_SPW_TOP|rx_data|wr_ptr [2] & ( \A_SPW_TOP|rx_data|wr_ptr [1] & ( (!\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|wr_ptr [4] & (!\A_SPW_TOP|rx_data|wr_ptr [5] & \A_SPW_TOP|rx_data|wr_ptr [0]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Decoder0~25_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Decoder0~25 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Decoder0~25 .lut_mask = 64'h0000000000200000;
defparam \A_SPW_TOP|rx_data|Decoder0~25 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X32_Y7_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector190~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector190~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (\A_SPW_TOP|rx_data|state_data_write.01~q  & \A_SPW_TOP|rx_data|Decoder0~25_combout ) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( 
// \A_SPW_TOP|rx_data|Decoder0~25_combout  ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .datac(!\A_SPW_TOP|rx_data|Decoder0~25_combout ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector190~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector190~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector190~0 .lut_mask = 64'h0F0F03030F0F0303;
defparam \A_SPW_TOP|rx_data|Selector190~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y9_N45
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector190~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector190~1_combout  = ( \A_SPW_TOP|rx_data|mem[19][8]~q  & ( (!\A_SPW_TOP|rx_data|Selector190~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [8])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux0~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[19][8]~q  & ( (\A_SPW_TOP|rx_data|Selector190~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [8])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux0~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .datab(!\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector190~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[19][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector190~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector190~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector190~1 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|rx_data|Selector190~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y9_N35
dffeas \A_SPW_TOP|rx_data|mem[19][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector190~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[19][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[19][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[19][8] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y9_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux0~15 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux0~15_combout  = ( \A_SPW_TOP|rx_data|mem[19][8]~q  & ( \A_SPW_TOP|rx_data|wr_ptr [3] & ( (!\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[11][8]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|mem[27][8]~q ))) ) 
// ) ) # ( !\A_SPW_TOP|rx_data|mem[19][8]~q  & ( \A_SPW_TOP|rx_data|wr_ptr [3] & ( (!\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[11][8]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|mem[27][8]~q ))) ) ) ) # ( 
// \A_SPW_TOP|rx_data|mem[19][8]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [3] & ( (\A_SPW_TOP|rx_data|mem[3][8]~q ) # (\A_SPW_TOP|rx_data|wr_ptr [4]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[19][8]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [3] & ( (!\A_SPW_TOP|rx_data|wr_ptr [4] 
// & \A_SPW_TOP|rx_data|mem[3][8]~q ) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datab(!\A_SPW_TOP|rx_data|mem[3][8]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[11][8]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[27][8]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[19][8]~q ),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux0~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux0~15 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux0~15 .lut_mask = 64'h222277770A5F0A5F;
defparam \A_SPW_TOP|rx_data|Mux0~15 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X35_Y4_N33
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Decoder0~27 (
// Equation(s):
// \A_SPW_TOP|rx_data|Decoder0~27_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [5] & ( !\A_SPW_TOP|rx_data|wr_ptr [3] & ( (\A_SPW_TOP|rx_data|wr_ptr [0] & (!\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|wr_ptr [4] & \A_SPW_TOP|rx_data|wr_ptr [1]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Decoder0~27_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Decoder0~27 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Decoder0~27 .lut_mask = 64'h0000000400000000;
defparam \A_SPW_TOP|rx_data|Decoder0~27 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X35_Y4_N45
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector478~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector478~0_combout  = ( \A_SPW_TOP|rx_data|Decoder0~27_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|rx_data|state_data_write.01~q ) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Decoder0~27_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector478~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector478~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector478~0 .lut_mask = 64'h00000000DDDDDDDD;
defparam \A_SPW_TOP|rx_data|Selector478~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y9_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector478~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector478~1_combout  = ( \A_SPW_TOP|rx_data|mem[51][8]~q  & ( (!\A_SPW_TOP|rx_data|Selector478~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [8])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux0~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[51][8]~q  & ( (\A_SPW_TOP|rx_data|Selector478~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [8])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux0~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .datab(!\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector478~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[51][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector478~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector478~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector478~1 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|rx_data|Selector478~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y9_N53
dffeas \A_SPW_TOP|rx_data|mem[51][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector478~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[51][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[51][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[51][8] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X32_Y9_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Decoder0~61 (
// Equation(s):
// \A_SPW_TOP|rx_data|Decoder0~61_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [0] & ( !\A_SPW_TOP|rx_data|wr_ptr [2] & ( (\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|wr_ptr [5] & \A_SPW_TOP|rx_data|wr_ptr [4]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Decoder0~61_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Decoder0~61 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Decoder0~61 .lut_mask = 64'h0000000100000000;
defparam \A_SPW_TOP|rx_data|Decoder0~61 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X32_Y9_N51
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector550~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector550~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.01~q  & ( \A_SPW_TOP|rx_data|Decoder0~61_combout  ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.01~q  & ( (\A_SPW_TOP|rx_data|Decoder0~61_combout  & 
// !\A_SPW_TOP|rx_data|state_data_write.00~q ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|rx_data|Decoder0~61_combout ),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector550~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector550~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector550~0 .lut_mask = 64'h3030303033333333;
defparam \A_SPW_TOP|rx_data|Selector550~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X32_Y9_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector550~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector550~1_combout  = ( \A_SPW_TOP|rx_data|mem[59][8]~q  & ( (!\A_SPW_TOP|rx_data|Selector550~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [8]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux0~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[59][8]~q  & ( (\A_SPW_TOP|rx_data|Selector550~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [8]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux0~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Selector550~0_combout ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[59][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector550~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector550~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector550~1 .lut_mask = 64'h01450145ABEFABEF;
defparam \A_SPW_TOP|rx_data|Selector550~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y9_N47
dffeas \A_SPW_TOP|rx_data|mem[59][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector550~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[59][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[59][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[59][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y4_N39
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Decoder0~43 (
// Equation(s):
// \A_SPW_TOP|rx_data|Decoder0~43_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [3] & ( \A_SPW_TOP|rx_data|wr_ptr [5] & ( (\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|wr_ptr [0] & (!\A_SPW_TOP|rx_data|wr_ptr [2] & !\A_SPW_TOP|rx_data|wr_ptr [4]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Decoder0~43_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Decoder0~43 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Decoder0~43 .lut_mask = 64'h0000000000001000;
defparam \A_SPW_TOP|rx_data|Decoder0~43 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y4_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector406~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector406~0_combout  = ( \A_SPW_TOP|rx_data|Decoder0~43_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|rx_data|state_data_write.01~q ) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(gnd),
        .datac(gnd),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Decoder0~43_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector406~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector406~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector406~0 .lut_mask = 64'h00000000AAFFAAFF;
defparam \A_SPW_TOP|rx_data|Selector406~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y9_N39
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector406~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector406~1_combout  = ( \A_SPW_TOP|rx_data|mem[43][8]~q  & ( (!\A_SPW_TOP|rx_data|Selector406~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [8])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux0~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[43][8]~q  & ( (\A_SPW_TOP|rx_data|Selector406~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [8])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux0~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .datab(!\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector406~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[43][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector406~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector406~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector406~1 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|rx_data|Selector406~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y9_N11
dffeas \A_SPW_TOP|rx_data|mem[43][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector406~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[43][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[43][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[43][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y7_N9
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Decoder0~11 (
// Equation(s):
// \A_SPW_TOP|rx_data|Decoder0~11_combout  = ( !\A_SPW_TOP|rx_data|wr_ptr [2] & ( \A_SPW_TOP|rx_data|wr_ptr [1] & ( (\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|wr_ptr [5] & (!\A_SPW_TOP|rx_data|wr_ptr [4] & !\A_SPW_TOP|rx_data|wr_ptr [3]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Decoder0~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Decoder0~11 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Decoder0~11 .lut_mask = 64'h0000000010000000;
defparam \A_SPW_TOP|rx_data|Decoder0~11 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X31_Y7_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector334~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector334~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.01~q  & ( \A_SPW_TOP|rx_data|Decoder0~11_combout  ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.01~q  & ( \A_SPW_TOP|rx_data|Decoder0~11_combout  & ( 
// !\A_SPW_TOP|rx_data|state_data_write.00~q  ) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\A_SPW_TOP|rx_data|state_data_write.01~q ),
        .dataf(!\A_SPW_TOP|rx_data|Decoder0~11_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector334~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector334~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector334~0 .lut_mask = 64'h00000000AAAAFFFF;
defparam \A_SPW_TOP|rx_data|Selector334~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y7_N21
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector334~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector334~1_combout  = ( \A_SPW_TOP|SPW|RX|rx_data_flag [8] & ( (!\A_SPW_TOP|rx_data|Selector334~0_combout  & (((\A_SPW_TOP|rx_data|mem[35][8]~q )))) # (\A_SPW_TOP|rx_data|Selector334~0_combout  & 
// ((!\A_SPW_TOP|rx_data|state_data_write.00~q ) # ((\A_SPW_TOP|rx_data|Mux0~20_combout )))) ) ) # ( !\A_SPW_TOP|SPW|RX|rx_data_flag [8] & ( (!\A_SPW_TOP|rx_data|Selector334~0_combout  & (((\A_SPW_TOP|rx_data|mem[35][8]~q )))) # 
// (\A_SPW_TOP|rx_data|Selector334~0_combout  & (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux0~20_combout ))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector334~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[35][8]~q ),
        .datae(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector334~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector334~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector334~1 .lut_mask = 64'h01F10BFB01F10BFB;
defparam \A_SPW_TOP|rx_data|Selector334~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y7_N26
dffeas \A_SPW_TOP|rx_data|mem[35][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector334~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[35][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[35][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[35][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y9_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux0~16 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux0~16_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [3] & ( \A_SPW_TOP|rx_data|mem[35][8]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|mem[43][8]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[59][8]~q )) ) 
// ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [3] & ( \A_SPW_TOP|rx_data|mem[35][8]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [4]) # (\A_SPW_TOP|rx_data|mem[51][8]~q ) ) ) ) # ( \A_SPW_TOP|rx_data|wr_ptr [3] & ( !\A_SPW_TOP|rx_data|mem[35][8]~q  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|mem[43][8]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[59][8]~q )) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [3] & ( !\A_SPW_TOP|rx_data|mem[35][8]~q  & ( 
// (\A_SPW_TOP|rx_data|mem[51][8]~q  & \A_SPW_TOP|rx_data|wr_ptr [4]) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[51][8]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[59][8]~q ),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datad(!\A_SPW_TOP|rx_data|mem[43][8]~q ),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .dataf(!\A_SPW_TOP|rx_data|mem[35][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux0~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux0~16 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux0~16 .lut_mask = 64'h050503F3F5F503F3;
defparam \A_SPW_TOP|rx_data|Mux0~16 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X36_Y9_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux0~19 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux0~19_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [2] & ( \A_SPW_TOP|rx_data|Mux0~16_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & ((\A_SPW_TOP|rx_data|Mux0~17_combout ))) # (\A_SPW_TOP|rx_data|wr_ptr [5] & 
// (\A_SPW_TOP|rx_data|Mux0~18_combout )) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [2] & ( \A_SPW_TOP|rx_data|Mux0~16_combout  & ( (\A_SPW_TOP|rx_data|Mux0~15_combout ) # (\A_SPW_TOP|rx_data|wr_ptr [5]) ) ) ) # ( \A_SPW_TOP|rx_data|wr_ptr [2] & ( 
// !\A_SPW_TOP|rx_data|Mux0~16_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & ((\A_SPW_TOP|rx_data|Mux0~17_combout ))) # (\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|Mux0~18_combout )) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [2] & ( 
// !\A_SPW_TOP|rx_data|Mux0~16_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & \A_SPW_TOP|rx_data|Mux0~15_combout ) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datab(!\A_SPW_TOP|rx_data|Mux0~18_combout ),
        .datac(!\A_SPW_TOP|rx_data|Mux0~17_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux0~15_combout ),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .dataf(!\A_SPW_TOP|rx_data|Mux0~16_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux0~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux0~19 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux0~19 .lut_mask = 64'h00AA1B1B55FF1B1B;
defparam \A_SPW_TOP|rx_data|Mux0~19 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X36_Y9_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux0~20 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux0~20_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [1] & ( \A_SPW_TOP|rx_data|wr_ptr [0] & ( \A_SPW_TOP|rx_data|Mux0~19_combout  ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [1] & ( \A_SPW_TOP|rx_data|wr_ptr [0] & ( 
// \A_SPW_TOP|rx_data|Mux0~14_combout  ) ) ) # ( \A_SPW_TOP|rx_data|wr_ptr [1] & ( !\A_SPW_TOP|rx_data|wr_ptr [0] & ( \A_SPW_TOP|rx_data|Mux0~9_combout  ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [1] & ( !\A_SPW_TOP|rx_data|wr_ptr [0] & ( 
// \A_SPW_TOP|rx_data|Mux0~4_combout  ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux0~9_combout ),
        .datab(!\A_SPW_TOP|rx_data|Mux0~14_combout ),
        .datac(!\A_SPW_TOP|rx_data|Mux0~4_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux0~19_combout ),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux0~20 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux0~20 .lut_mask = 64'h0F0F5555333300FF;
defparam \A_SPW_TOP|rx_data|Mux0~20 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y7_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector244~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector244~1_combout  = ( \A_SPW_TOP|rx_data|Mux0~20_combout  & ( \A_SPW_TOP|rx_data|mem[25][8]~q  & ( ((!\A_SPW_TOP|rx_data|Selector244~0_combout ) # (\A_SPW_TOP|rx_data|state_data_write.00~q )) # (\A_SPW_TOP|SPW|RX|rx_data_flag [8]) 
// ) ) ) # ( !\A_SPW_TOP|rx_data|Mux0~20_combout  & ( \A_SPW_TOP|rx_data|mem[25][8]~q  & ( (!\A_SPW_TOP|rx_data|Selector244~0_combout ) # ((\A_SPW_TOP|SPW|RX|rx_data_flag [8] & !\A_SPW_TOP|rx_data|state_data_write.00~q )) ) ) ) # ( 
// \A_SPW_TOP|rx_data|Mux0~20_combout  & ( !\A_SPW_TOP|rx_data|mem[25][8]~q  & ( (\A_SPW_TOP|rx_data|Selector244~0_combout  & ((\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|SPW|RX|rx_data_flag [8]))) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux0~20_combout  
// & ( !\A_SPW_TOP|rx_data|mem[25][8]~q  & ( (\A_SPW_TOP|SPW|RX|rx_data_flag [8] & (!\A_SPW_TOP|rx_data|state_data_write.00~q  & \A_SPW_TOP|rx_data|Selector244~0_combout )) ) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Selector244~0_combout ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|rx_data|Mux0~20_combout ),
        .dataf(!\A_SPW_TOP|rx_data|mem[25][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector244~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector244~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector244~1 .lut_mask = 64'h04040707F4F4F7F7;
defparam \A_SPW_TOP|rx_data|Selector244~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y7_N53
dffeas \A_SPW_TOP|rx_data|mem[25][8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector244~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[25][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[25][8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[25][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X35_Y7_N9
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Add9~21 (
// Equation(s):
// \A_SPW_TOP|rx_data|Add9~21_sumout  = SUM(( \A_SPW_TOP|rx_data|rd_ptr [3] ) + ( GND ) + ( \A_SPW_TOP|rx_data|Add9~10  ))
// \A_SPW_TOP|rx_data|Add9~22  = CARRY(( \A_SPW_TOP|rx_data|rd_ptr [3] ) + ( GND ) + ( \A_SPW_TOP|rx_data|Add9~10  ))

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [3]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\A_SPW_TOP|rx_data|Add9~10 ),
        .sharein(gnd),
        .combout(),
        .sumout(\A_SPW_TOP|rx_data|Add9~21_sumout ),
        .cout(\A_SPW_TOP|rx_data|Add9~22 ),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Add9~21 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Add9~21 .lut_mask = 64'h0000FFFF00005555;
defparam \A_SPW_TOP|rx_data|Add9~21 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X35_Y7_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|rd_ptr[3]~feeder (
// Equation(s):
// \A_SPW_TOP|rx_data|rd_ptr[3]~feeder_combout  = ( \A_SPW_TOP|rx_data|Add9~21_sumout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Add9~21_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|rd_ptr[3]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|rd_ptr[3]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|rd_ptr[3]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|rx_data|rd_ptr[3]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X35_Y7_N26
dffeas \A_SPW_TOP|rx_data|rd_ptr[3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|rx_data|rd_ptr[3]~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(!\A_SPW_TOP|rx_data|state_data_read.00~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|rd_ptr [3]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|rd_ptr[3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|rd_ptr[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X35_Y7_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Add9~17 (
// Equation(s):
// \A_SPW_TOP|rx_data|Add9~17_sumout  = SUM(( \A_SPW_TOP|rx_data|rd_ptr [4] ) + ( GND ) + ( \A_SPW_TOP|rx_data|Add9~22  ))
// \A_SPW_TOP|rx_data|Add9~18  = CARRY(( \A_SPW_TOP|rx_data|rd_ptr [4] ) + ( GND ) + ( \A_SPW_TOP|rx_data|Add9~22  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [4]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\A_SPW_TOP|rx_data|Add9~22 ),
        .sharein(gnd),
        .combout(),
        .sumout(\A_SPW_TOP|rx_data|Add9~17_sumout ),
        .cout(\A_SPW_TOP|rx_data|Add9~18 ),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Add9~17 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Add9~17 .lut_mask = 64'h0000FFFF00000F0F;
defparam \A_SPW_TOP|rx_data|Add9~17 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X35_Y7_N50
dffeas \A_SPW_TOP|rx_data|rd_ptr[4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Add9~17_sumout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(!\A_SPW_TOP|rx_data|state_data_read.00~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|rd_ptr [4]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|rd_ptr[4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|rd_ptr[4] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y7_N9
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux9~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux9~1_combout  = ( \A_SPW_TOP|rx_data|rd_ptr [4] & ( \A_SPW_TOP|rx_data|rd_ptr [3] & ( \A_SPW_TOP|rx_data|mem[25][8]~q  ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [4] & ( \A_SPW_TOP|rx_data|rd_ptr [3] & ( \A_SPW_TOP|rx_data|mem[9][8]~q  ) ) 
// ) # ( \A_SPW_TOP|rx_data|rd_ptr [4] & ( !\A_SPW_TOP|rx_data|rd_ptr [3] & ( \A_SPW_TOP|rx_data|mem[17][8]~q  ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [4] & ( !\A_SPW_TOP|rx_data|rd_ptr [3] & ( \A_SPW_TOP|rx_data|mem[1][8]~q  ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[25][8]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[9][8]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[1][8]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[17][8]~q ),
        .datae(!\A_SPW_TOP|rx_data|rd_ptr [4]),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux9~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux9~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux9~1 .lut_mask = 64'h0F0F00FF33335555;
defparam \A_SPW_TOP|rx_data|Mux9~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y7_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux9~3 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux9~3_combout  = ( \A_SPW_TOP|rx_data|mem[57][8]~q  & ( \A_SPW_TOP|rx_data|mem[41][8]~q  & ( ((!\A_SPW_TOP|rx_data|rd_ptr [4] & (\A_SPW_TOP|rx_data|mem[33][8]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [4] & ((\A_SPW_TOP|rx_data|mem[49][8]~q 
// )))) # (\A_SPW_TOP|rx_data|rd_ptr [3]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[57][8]~q  & ( \A_SPW_TOP|rx_data|mem[41][8]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [3] & ((!\A_SPW_TOP|rx_data|rd_ptr [4] & (\A_SPW_TOP|rx_data|mem[33][8]~q )) # 
// (\A_SPW_TOP|rx_data|rd_ptr [4] & ((\A_SPW_TOP|rx_data|mem[49][8]~q ))))) # (\A_SPW_TOP|rx_data|rd_ptr [3] & (((!\A_SPW_TOP|rx_data|rd_ptr [4])))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[57][8]~q  & ( !\A_SPW_TOP|rx_data|mem[41][8]~q  & ( 
// (!\A_SPW_TOP|rx_data|rd_ptr [3] & ((!\A_SPW_TOP|rx_data|rd_ptr [4] & (\A_SPW_TOP|rx_data|mem[33][8]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [4] & ((\A_SPW_TOP|rx_data|mem[49][8]~q ))))) # (\A_SPW_TOP|rx_data|rd_ptr [3] & (((\A_SPW_TOP|rx_data|rd_ptr [4])))) ) ) 
// ) # ( !\A_SPW_TOP|rx_data|mem[57][8]~q  & ( !\A_SPW_TOP|rx_data|mem[41][8]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [3] & ((!\A_SPW_TOP|rx_data|rd_ptr [4] & (\A_SPW_TOP|rx_data|mem[33][8]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [4] & ((\A_SPW_TOP|rx_data|mem[49][8]~q 
// ))))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[33][8]~q ),
        .datab(!\A_SPW_TOP|rx_data|rd_ptr [3]),
        .datac(!\A_SPW_TOP|rx_data|mem[49][8]~q ),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [4]),
        .datae(!\A_SPW_TOP|rx_data|mem[57][8]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[41][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux9~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux9~3 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux9~3 .lut_mask = 64'h440C443F770C773F;
defparam \A_SPW_TOP|rx_data|Mux9~3 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X32_Y7_N9
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux9~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux9~0_combout  = ( \A_SPW_TOP|rx_data|mem[0][8]~q  & ( \A_SPW_TOP|rx_data|mem[8][8]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [4]) # ((!\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|mem[16][8]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [3] & 
// ((\A_SPW_TOP|rx_data|mem[24][8]~q )))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[0][8]~q  & ( \A_SPW_TOP|rx_data|mem[8][8]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|mem[16][8]~q  & ((\A_SPW_TOP|rx_data|rd_ptr [4])))) # 
// (\A_SPW_TOP|rx_data|rd_ptr [3] & (((!\A_SPW_TOP|rx_data|rd_ptr [4]) # (\A_SPW_TOP|rx_data|mem[24][8]~q )))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[0][8]~q  & ( !\A_SPW_TOP|rx_data|mem[8][8]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [3] & (((!\A_SPW_TOP|rx_data|rd_ptr 
// [4])) # (\A_SPW_TOP|rx_data|mem[16][8]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [3] & (((\A_SPW_TOP|rx_data|mem[24][8]~q  & \A_SPW_TOP|rx_data|rd_ptr [4])))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[0][8]~q  & ( !\A_SPW_TOP|rx_data|mem[8][8]~q  & ( 
// (\A_SPW_TOP|rx_data|rd_ptr [4] & ((!\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|mem[16][8]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [3] & ((\A_SPW_TOP|rx_data|mem[24][8]~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [3]),
        .datab(!\A_SPW_TOP|rx_data|mem[16][8]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[24][8]~q ),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [4]),
        .datae(!\A_SPW_TOP|rx_data|mem[0][8]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[8][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux9~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux9~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux9~0 .lut_mask = 64'h0027AA275527FF27;
defparam \A_SPW_TOP|rx_data|Mux9~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X35_Y7_N15
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Add9~5 (
// Equation(s):
// \A_SPW_TOP|rx_data|Add9~5_sumout  = SUM(( \A_SPW_TOP|rx_data|rd_ptr [5] ) + ( GND ) + ( \A_SPW_TOP|rx_data|Add9~18  ))

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\A_SPW_TOP|rx_data|Add9~18 ),
        .sharein(gnd),
        .combout(),
        .sumout(\A_SPW_TOP|rx_data|Add9~5_sumout ),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Add9~5 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Add9~5 .lut_mask = 64'h0000FFFF00005555;
defparam \A_SPW_TOP|rx_data|Add9~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X35_Y7_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|rd_ptr[5]~feeder (
// Equation(s):
// \A_SPW_TOP|rx_data|rd_ptr[5]~feeder_combout  = ( \A_SPW_TOP|rx_data|Add9~5_sumout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Add9~5_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|rd_ptr[5]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|rd_ptr[5]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|rd_ptr[5]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|rx_data|rd_ptr[5]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X35_Y7_N56
dffeas \A_SPW_TOP|rx_data|rd_ptr[5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|rx_data|rd_ptr[5]~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(!\A_SPW_TOP|rx_data|state_data_read.00~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|rd_ptr [5]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|rd_ptr[5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|rd_ptr[5] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X32_Y7_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux9~2 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux9~2_combout  = ( \A_SPW_TOP|rx_data|rd_ptr [4] & ( \A_SPW_TOP|rx_data|mem[56][8]~q  & ( (\A_SPW_TOP|rx_data|mem[48][8]~q ) # (\A_SPW_TOP|rx_data|rd_ptr [3]) ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [4] & ( \A_SPW_TOP|rx_data|mem[56][8]~q 
//  & ( (!\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|mem[32][8]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [3] & ((\A_SPW_TOP|rx_data|mem[40][8]~q ))) ) ) ) # ( \A_SPW_TOP|rx_data|rd_ptr [4] & ( !\A_SPW_TOP|rx_data|mem[56][8]~q  & ( 
// (!\A_SPW_TOP|rx_data|rd_ptr [3] & \A_SPW_TOP|rx_data|mem[48][8]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [4] & ( !\A_SPW_TOP|rx_data|mem[56][8]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|mem[32][8]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [3] & 
// ((\A_SPW_TOP|rx_data|mem[40][8]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [3]),
        .datab(!\A_SPW_TOP|rx_data|mem[48][8]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[32][8]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[40][8]~q ),
        .datae(!\A_SPW_TOP|rx_data|rd_ptr [4]),
        .dataf(!\A_SPW_TOP|rx_data|mem[56][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux9~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux9~2 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux9~2 .lut_mask = 64'h0A5F22220A5F7777;
defparam \A_SPW_TOP|rx_data|Mux9~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X35_Y7_N51
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux9~4 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux9~4_combout  = ( \A_SPW_TOP|rx_data|rd_ptr [5] & ( \A_SPW_TOP|rx_data|Mux9~2_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [0]) # (\A_SPW_TOP|rx_data|Mux9~3_combout ) ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [5] & ( 
// \A_SPW_TOP|rx_data|Mux9~2_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & ((\A_SPW_TOP|rx_data|Mux9~0_combout ))) # (\A_SPW_TOP|rx_data|rd_ptr [0] & (\A_SPW_TOP|rx_data|Mux9~1_combout )) ) ) ) # ( \A_SPW_TOP|rx_data|rd_ptr [5] & ( 
// !\A_SPW_TOP|rx_data|Mux9~2_combout  & ( (\A_SPW_TOP|rx_data|rd_ptr [0] & \A_SPW_TOP|rx_data|Mux9~3_combout ) ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [5] & ( !\A_SPW_TOP|rx_data|Mux9~2_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & 
// ((\A_SPW_TOP|rx_data|Mux9~0_combout ))) # (\A_SPW_TOP|rx_data|rd_ptr [0] & (\A_SPW_TOP|rx_data|Mux9~1_combout )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .datab(!\A_SPW_TOP|rx_data|Mux9~1_combout ),
        .datac(!\A_SPW_TOP|rx_data|Mux9~3_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux9~0_combout ),
        .datae(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .dataf(!\A_SPW_TOP|rx_data|Mux9~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux9~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux9~4 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux9~4 .lut_mask = 64'h11BB050511BBAFAF;
defparam \A_SPW_TOP|rx_data|Mux9~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X35_Y9_N33
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux9~16 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux9~16_combout  = ( \A_SPW_TOP|rx_data|mem[23][8]~q  & ( \A_SPW_TOP|rx_data|mem[55][8]~q  & ( ((!\A_SPW_TOP|rx_data|rd_ptr [5] & ((\A_SPW_TOP|rx_data|mem[22][8]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [5] & (\A_SPW_TOP|rx_data|mem[54][8]~q 
// ))) # (\A_SPW_TOP|rx_data|rd_ptr [0]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[23][8]~q  & ( \A_SPW_TOP|rx_data|mem[55][8]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & ((!\A_SPW_TOP|rx_data|rd_ptr [5] & ((\A_SPW_TOP|rx_data|mem[22][8]~q ))) # 
// (\A_SPW_TOP|rx_data|rd_ptr [5] & (\A_SPW_TOP|rx_data|mem[54][8]~q )))) # (\A_SPW_TOP|rx_data|rd_ptr [0] & (((\A_SPW_TOP|rx_data|rd_ptr [5])))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[23][8]~q  & ( !\A_SPW_TOP|rx_data|mem[55][8]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr 
// [0] & ((!\A_SPW_TOP|rx_data|rd_ptr [5] & ((\A_SPW_TOP|rx_data|mem[22][8]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [5] & (\A_SPW_TOP|rx_data|mem[54][8]~q )))) # (\A_SPW_TOP|rx_data|rd_ptr [0] & (((!\A_SPW_TOP|rx_data|rd_ptr [5])))) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|mem[23][8]~q  & ( !\A_SPW_TOP|rx_data|mem[55][8]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & ((!\A_SPW_TOP|rx_data|rd_ptr [5] & ((\A_SPW_TOP|rx_data|mem[22][8]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [5] & (\A_SPW_TOP|rx_data|mem[54][8]~q )))) 
// ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[54][8]~q ),
        .datab(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .datac(!\A_SPW_TOP|rx_data|mem[22][8]~q ),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .datae(!\A_SPW_TOP|rx_data|mem[23][8]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[55][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux9~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux9~16 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux9~16 .lut_mask = 64'h0C443F440C773F77;
defparam \A_SPW_TOP|rx_data|Mux9~16 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X35_Y9_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux9~17 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux9~17_combout  = ( \A_SPW_TOP|rx_data|mem[14][8]~q  & ( \A_SPW_TOP|rx_data|mem[47][8]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [5] & (((!\A_SPW_TOP|rx_data|rd_ptr [0]) # (\A_SPW_TOP|rx_data|mem[15][8]~q )))) # (\A_SPW_TOP|rx_data|rd_ptr [5] 
// & (((\A_SPW_TOP|rx_data|rd_ptr [0])) # (\A_SPW_TOP|rx_data|mem[46][8]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[14][8]~q  & ( \A_SPW_TOP|rx_data|mem[47][8]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [5] & (((\A_SPW_TOP|rx_data|rd_ptr [0] & 
// \A_SPW_TOP|rx_data|mem[15][8]~q )))) # (\A_SPW_TOP|rx_data|rd_ptr [5] & (((\A_SPW_TOP|rx_data|rd_ptr [0])) # (\A_SPW_TOP|rx_data|mem[46][8]~q ))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[14][8]~q  & ( !\A_SPW_TOP|rx_data|mem[47][8]~q  & ( 
// (!\A_SPW_TOP|rx_data|rd_ptr [5] & (((!\A_SPW_TOP|rx_data|rd_ptr [0]) # (\A_SPW_TOP|rx_data|mem[15][8]~q )))) # (\A_SPW_TOP|rx_data|rd_ptr [5] & (\A_SPW_TOP|rx_data|mem[46][8]~q  & (!\A_SPW_TOP|rx_data|rd_ptr [0]))) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|mem[14][8]~q  & ( !\A_SPW_TOP|rx_data|mem[47][8]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [5] & (((\A_SPW_TOP|rx_data|rd_ptr [0] & \A_SPW_TOP|rx_data|mem[15][8]~q )))) # (\A_SPW_TOP|rx_data|rd_ptr [5] & (\A_SPW_TOP|rx_data|mem[46][8]~q  & 
// (!\A_SPW_TOP|rx_data|rd_ptr [0]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .datab(!\A_SPW_TOP|rx_data|mem[46][8]~q ),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .datad(!\A_SPW_TOP|rx_data|mem[15][8]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[14][8]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[47][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux9~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux9~17 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux9~17 .lut_mask = 64'h101AB0BA151FB5BF;
defparam \A_SPW_TOP|rx_data|Mux9~17 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X35_Y9_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux9~15 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux9~15_combout  = ( \A_SPW_TOP|rx_data|mem[39][8]~q  & ( \A_SPW_TOP|rx_data|rd_ptr [5] & ( (\A_SPW_TOP|rx_data|mem[38][8]~q ) # (\A_SPW_TOP|rx_data|rd_ptr [0]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[39][8]~q  & ( \A_SPW_TOP|rx_data|rd_ptr 
// [5] & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & \A_SPW_TOP|rx_data|mem[38][8]~q ) ) ) ) # ( \A_SPW_TOP|rx_data|mem[39][8]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [5] & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & ((\A_SPW_TOP|rx_data|mem[6][8]~q ))) # 
// (\A_SPW_TOP|rx_data|rd_ptr [0] & (\A_SPW_TOP|rx_data|mem[7][8]~q )) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[39][8]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [5] & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & ((\A_SPW_TOP|rx_data|mem[6][8]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [0] 
// & (\A_SPW_TOP|rx_data|mem[7][8]~q )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .datab(!\A_SPW_TOP|rx_data|mem[38][8]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[7][8]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[6][8]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[39][8]~q ),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux9~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux9~15 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux9~15 .lut_mask = 64'h05AF05AF22227777;
defparam \A_SPW_TOP|rx_data|Mux9~15 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X35_Y9_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux9~18 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux9~18_combout  = ( \A_SPW_TOP|rx_data|rd_ptr [0] & ( \A_SPW_TOP|rx_data|mem[63][8]~q  & ( (\A_SPW_TOP|rx_data|rd_ptr [5]) # (\A_SPW_TOP|rx_data|mem[31][8]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [0] & ( 
// \A_SPW_TOP|rx_data|mem[63][8]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [5] & (\A_SPW_TOP|rx_data|mem[30][8]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [5] & ((\A_SPW_TOP|rx_data|mem[62][8]~q ))) ) ) ) # ( \A_SPW_TOP|rx_data|rd_ptr [0] & ( 
// !\A_SPW_TOP|rx_data|mem[63][8]~q  & ( (\A_SPW_TOP|rx_data|mem[31][8]~q  & !\A_SPW_TOP|rx_data|rd_ptr [5]) ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [0] & ( !\A_SPW_TOP|rx_data|mem[63][8]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [5] & (\A_SPW_TOP|rx_data|mem[30][8]~q 
// )) # (\A_SPW_TOP|rx_data|rd_ptr [5] & ((\A_SPW_TOP|rx_data|mem[62][8]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[31][8]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[30][8]~q ),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .datad(!\A_SPW_TOP|rx_data|mem[62][8]~q ),
        .datae(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .dataf(!\A_SPW_TOP|rx_data|mem[63][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux9~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux9~18 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux9~18 .lut_mask = 64'h303F5050303F5F5F;
defparam \A_SPW_TOP|rx_data|Mux9~18 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X35_Y9_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux9~19 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux9~19_combout  = ( \A_SPW_TOP|rx_data|Mux9~15_combout  & ( \A_SPW_TOP|rx_data|Mux9~18_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & (((!\A_SPW_TOP|rx_data|rd_ptr [3]) # (\A_SPW_TOP|rx_data|Mux9~17_combout )))) # 
// (\A_SPW_TOP|rx_data|rd_ptr [4] & (((\A_SPW_TOP|rx_data|rd_ptr [3])) # (\A_SPW_TOP|rx_data|Mux9~16_combout ))) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux9~15_combout  & ( \A_SPW_TOP|rx_data|Mux9~18_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & 
// (((\A_SPW_TOP|rx_data|Mux9~17_combout  & \A_SPW_TOP|rx_data|rd_ptr [3])))) # (\A_SPW_TOP|rx_data|rd_ptr [4] & (((\A_SPW_TOP|rx_data|rd_ptr [3])) # (\A_SPW_TOP|rx_data|Mux9~16_combout ))) ) ) ) # ( \A_SPW_TOP|rx_data|Mux9~15_combout  & ( 
// !\A_SPW_TOP|rx_data|Mux9~18_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & (((!\A_SPW_TOP|rx_data|rd_ptr [3]) # (\A_SPW_TOP|rx_data|Mux9~17_combout )))) # (\A_SPW_TOP|rx_data|rd_ptr [4] & (\A_SPW_TOP|rx_data|Mux9~16_combout  & ((!\A_SPW_TOP|rx_data|rd_ptr 
// [3])))) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux9~15_combout  & ( !\A_SPW_TOP|rx_data|Mux9~18_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & (((\A_SPW_TOP|rx_data|Mux9~17_combout  & \A_SPW_TOP|rx_data|rd_ptr [3])))) # (\A_SPW_TOP|rx_data|rd_ptr [4] & 
// (\A_SPW_TOP|rx_data|Mux9~16_combout  & ((!\A_SPW_TOP|rx_data|rd_ptr [3])))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux9~16_combout ),
        .datab(!\A_SPW_TOP|rx_data|rd_ptr [4]),
        .datac(!\A_SPW_TOP|rx_data|Mux9~17_combout ),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [3]),
        .datae(!\A_SPW_TOP|rx_data|Mux9~15_combout ),
        .dataf(!\A_SPW_TOP|rx_data|Mux9~18_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux9~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux9~19 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux9~19 .lut_mask = 64'h110CDD0C113FDD3F;
defparam \A_SPW_TOP|rx_data|Mux9~19 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X35_Y7_N39
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux9~11 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux9~11_combout  = ( \A_SPW_TOP|rx_data|mem[13][8]~q  & ( \A_SPW_TOP|rx_data|rd_ptr [4] & ( (!\A_SPW_TOP|rx_data|rd_ptr [3] & ((\A_SPW_TOP|rx_data|mem[21][8]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|mem[29][8]~q )) ) 
// ) ) # ( !\A_SPW_TOP|rx_data|mem[13][8]~q  & ( \A_SPW_TOP|rx_data|rd_ptr [4] & ( (!\A_SPW_TOP|rx_data|rd_ptr [3] & ((\A_SPW_TOP|rx_data|mem[21][8]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|mem[29][8]~q )) ) ) ) # ( 
// \A_SPW_TOP|rx_data|mem[13][8]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [4] & ( (\A_SPW_TOP|rx_data|rd_ptr [3]) # (\A_SPW_TOP|rx_data|mem[5][8]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[13][8]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [4] & ( (\A_SPW_TOP|rx_data|mem[5][8]~q  
// & !\A_SPW_TOP|rx_data|rd_ptr [3]) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[29][8]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[5][8]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[21][8]~q ),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [3]),
        .datae(!\A_SPW_TOP|rx_data|mem[13][8]~q ),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux9~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux9~11 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux9~11 .lut_mask = 64'h330033FF0F550F55;
defparam \A_SPW_TOP|rx_data|Mux9~11 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X33_Y7_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux9~12 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux9~12_combout  = ( \A_SPW_TOP|rx_data|rd_ptr [4] & ( \A_SPW_TOP|rx_data|mem[44][8]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|mem[52][8]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [3] & ((\A_SPW_TOP|rx_data|mem[60][8]~q ))) ) 
// ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [4] & ( \A_SPW_TOP|rx_data|mem[44][8]~q  & ( (\A_SPW_TOP|rx_data|mem[36][8]~q ) # (\A_SPW_TOP|rx_data|rd_ptr [3]) ) ) ) # ( \A_SPW_TOP|rx_data|rd_ptr [4] & ( !\A_SPW_TOP|rx_data|mem[44][8]~q  & ( 
// (!\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|mem[52][8]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [3] & ((\A_SPW_TOP|rx_data|mem[60][8]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [4] & ( !\A_SPW_TOP|rx_data|mem[44][8]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr 
// [3] & \A_SPW_TOP|rx_data|mem[36][8]~q ) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[52][8]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[60][8]~q ),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [3]),
        .datad(!\A_SPW_TOP|rx_data|mem[36][8]~q ),
        .datae(!\A_SPW_TOP|rx_data|rd_ptr [4]),
        .dataf(!\A_SPW_TOP|rx_data|mem[44][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux9~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux9~12 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux9~12 .lut_mask = 64'h00F053530FFF5353;
defparam \A_SPW_TOP|rx_data|Mux9~12 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X35_Y7_N33
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux9~13 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux9~13_combout  = ( \A_SPW_TOP|rx_data|mem[37][8]~q  & ( \A_SPW_TOP|rx_data|rd_ptr [4] & ( (!\A_SPW_TOP|rx_data|rd_ptr [3] & ((\A_SPW_TOP|rx_data|mem[53][8]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|mem[61][8]~q )) ) 
// ) ) # ( !\A_SPW_TOP|rx_data|mem[37][8]~q  & ( \A_SPW_TOP|rx_data|rd_ptr [4] & ( (!\A_SPW_TOP|rx_data|rd_ptr [3] & ((\A_SPW_TOP|rx_data|mem[53][8]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|mem[61][8]~q )) ) ) ) # ( 
// \A_SPW_TOP|rx_data|mem[37][8]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [4] & ( (!\A_SPW_TOP|rx_data|rd_ptr [3]) # (\A_SPW_TOP|rx_data|mem[45][8]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[37][8]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [4] & ( (\A_SPW_TOP|rx_data|rd_ptr [3] 
// & \A_SPW_TOP|rx_data|mem[45][8]~q ) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [3]),
        .datab(!\A_SPW_TOP|rx_data|mem[61][8]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[45][8]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[53][8]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[37][8]~q ),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux9~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux9~13 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux9~13 .lut_mask = 64'h0505AFAF11BB11BB;
defparam \A_SPW_TOP|rx_data|Mux9~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X33_Y7_N51
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux9~10 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux9~10_combout  = ( \A_SPW_TOP|rx_data|rd_ptr [4] & ( \A_SPW_TOP|rx_data|rd_ptr [3] & ( \A_SPW_TOP|rx_data|mem[28][8]~q  ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [4] & ( \A_SPW_TOP|rx_data|rd_ptr [3] & ( \A_SPW_TOP|rx_data|mem[12][8]~q  ) 
// ) ) # ( \A_SPW_TOP|rx_data|rd_ptr [4] & ( !\A_SPW_TOP|rx_data|rd_ptr [3] & ( \A_SPW_TOP|rx_data|mem[20][8]~q  ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [4] & ( !\A_SPW_TOP|rx_data|rd_ptr [3] & ( \A_SPW_TOP|rx_data|mem[4][8]~q  ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[20][8]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[28][8]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[4][8]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[12][8]~q ),
        .datae(!\A_SPW_TOP|rx_data|rd_ptr [4]),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux9~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux9~10 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux9~10 .lut_mask = 64'h0F0F555500FF3333;
defparam \A_SPW_TOP|rx_data|Mux9~10 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X35_Y7_N21
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux9~14 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux9~14_combout  = ( \A_SPW_TOP|rx_data|Mux9~10_combout  & ( \A_SPW_TOP|rx_data|rd_ptr [0] & ( (!\A_SPW_TOP|rx_data|rd_ptr [5] & (\A_SPW_TOP|rx_data|Mux9~11_combout )) # (\A_SPW_TOP|rx_data|rd_ptr [5] & 
// ((\A_SPW_TOP|rx_data|Mux9~13_combout ))) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux9~10_combout  & ( \A_SPW_TOP|rx_data|rd_ptr [0] & ( (!\A_SPW_TOP|rx_data|rd_ptr [5] & (\A_SPW_TOP|rx_data|Mux9~11_combout )) # (\A_SPW_TOP|rx_data|rd_ptr [5] & 
// ((\A_SPW_TOP|rx_data|Mux9~13_combout ))) ) ) ) # ( \A_SPW_TOP|rx_data|Mux9~10_combout  & ( !\A_SPW_TOP|rx_data|rd_ptr [0] & ( (!\A_SPW_TOP|rx_data|rd_ptr [5]) # (\A_SPW_TOP|rx_data|Mux9~12_combout ) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux9~10_combout  & ( 
// !\A_SPW_TOP|rx_data|rd_ptr [0] & ( (\A_SPW_TOP|rx_data|rd_ptr [5] & \A_SPW_TOP|rx_data|Mux9~12_combout ) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .datab(!\A_SPW_TOP|rx_data|Mux9~11_combout ),
        .datac(!\A_SPW_TOP|rx_data|Mux9~12_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux9~13_combout ),
        .datae(!\A_SPW_TOP|rx_data|Mux9~10_combout ),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux9~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux9~14 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux9~14 .lut_mask = 64'h0505AFAF22772277;
defparam \A_SPW_TOP|rx_data|Mux9~14 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y9_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux9~7 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux9~7_combout  = ( \A_SPW_TOP|rx_data|mem[11][8]~q  & ( \A_SPW_TOP|rx_data|rd_ptr [5] & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & (\A_SPW_TOP|rx_data|mem[42][8]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [0] & ((\A_SPW_TOP|rx_data|mem[43][8]~q ))) ) 
// ) ) # ( !\A_SPW_TOP|rx_data|mem[11][8]~q  & ( \A_SPW_TOP|rx_data|rd_ptr [5] & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & (\A_SPW_TOP|rx_data|mem[42][8]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [0] & ((\A_SPW_TOP|rx_data|mem[43][8]~q ))) ) ) ) # ( 
// \A_SPW_TOP|rx_data|mem[11][8]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [5] & ( (\A_SPW_TOP|rx_data|mem[10][8]~q ) # (\A_SPW_TOP|rx_data|rd_ptr [0]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[11][8]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [5] & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] 
// & \A_SPW_TOP|rx_data|mem[10][8]~q ) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .datab(!\A_SPW_TOP|rx_data|mem[42][8]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[10][8]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[43][8]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[11][8]~q ),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux9~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux9~7 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux9~7 .lut_mask = 64'h0A0A5F5F22772277;
defparam \A_SPW_TOP|rx_data|Mux9~7 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y9_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux9~5 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux9~5_combout  = ( \A_SPW_TOP|rx_data|rd_ptr [0] & ( \A_SPW_TOP|rx_data|mem[2][8]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [5] & ((\A_SPW_TOP|rx_data|mem[3][8]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [5] & (\A_SPW_TOP|rx_data|mem[35][8]~q )) ) ) 
// ) # ( !\A_SPW_TOP|rx_data|rd_ptr [0] & ( \A_SPW_TOP|rx_data|mem[2][8]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [5]) # (\A_SPW_TOP|rx_data|mem[34][8]~q ) ) ) ) # ( \A_SPW_TOP|rx_data|rd_ptr [0] & ( !\A_SPW_TOP|rx_data|mem[2][8]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr 
// [5] & ((\A_SPW_TOP|rx_data|mem[3][8]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [5] & (\A_SPW_TOP|rx_data|mem[35][8]~q )) ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [0] & ( !\A_SPW_TOP|rx_data|mem[2][8]~q  & ( (\A_SPW_TOP|rx_data|mem[34][8]~q  & 
// \A_SPW_TOP|rx_data|rd_ptr [5]) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[34][8]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[35][8]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[3][8]~q ),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .datae(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .dataf(!\A_SPW_TOP|rx_data|mem[2][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux9~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux9~5 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux9~5 .lut_mask = 64'h00550F33FF550F33;
defparam \A_SPW_TOP|rx_data|Mux9~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y9_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux9~6 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux9~6_combout  = ( \A_SPW_TOP|rx_data|mem[50][8]~q  & ( \A_SPW_TOP|rx_data|mem[19][8]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & (((\A_SPW_TOP|rx_data|rd_ptr [5]) # (\A_SPW_TOP|rx_data|mem[18][8]~q )))) # (\A_SPW_TOP|rx_data|rd_ptr [0] & 
// (((!\A_SPW_TOP|rx_data|rd_ptr [5])) # (\A_SPW_TOP|rx_data|mem[51][8]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[50][8]~q  & ( \A_SPW_TOP|rx_data|mem[19][8]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & (((\A_SPW_TOP|rx_data|mem[18][8]~q  & 
// !\A_SPW_TOP|rx_data|rd_ptr [5])))) # (\A_SPW_TOP|rx_data|rd_ptr [0] & (((!\A_SPW_TOP|rx_data|rd_ptr [5])) # (\A_SPW_TOP|rx_data|mem[51][8]~q ))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[50][8]~q  & ( !\A_SPW_TOP|rx_data|mem[19][8]~q  & ( 
// (!\A_SPW_TOP|rx_data|rd_ptr [0] & (((\A_SPW_TOP|rx_data|rd_ptr [5]) # (\A_SPW_TOP|rx_data|mem[18][8]~q )))) # (\A_SPW_TOP|rx_data|rd_ptr [0] & (\A_SPW_TOP|rx_data|mem[51][8]~q  & ((\A_SPW_TOP|rx_data|rd_ptr [5])))) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|mem[50][8]~q  & ( !\A_SPW_TOP|rx_data|mem[19][8]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & (((\A_SPW_TOP|rx_data|mem[18][8]~q  & !\A_SPW_TOP|rx_data|rd_ptr [5])))) # (\A_SPW_TOP|rx_data|rd_ptr [0] & (\A_SPW_TOP|rx_data|mem[51][8]~q  & 
// ((\A_SPW_TOP|rx_data|rd_ptr [5])))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[51][8]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[18][8]~q ),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .datae(!\A_SPW_TOP|rx_data|mem[50][8]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[19][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux9~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux9~6 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux9~6 .lut_mask = 64'h300530F53F053FF5;
defparam \A_SPW_TOP|rx_data|Mux9~6 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y9_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux9~8 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux9~8_combout  = ( \A_SPW_TOP|rx_data|mem[27][8]~q  & ( \A_SPW_TOP|rx_data|mem[58][8]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & (((\A_SPW_TOP|rx_data|rd_ptr [5]) # (\A_SPW_TOP|rx_data|mem[26][8]~q )))) # (\A_SPW_TOP|rx_data|rd_ptr [0] & 
// (((!\A_SPW_TOP|rx_data|rd_ptr [5])) # (\A_SPW_TOP|rx_data|mem[59][8]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[27][8]~q  & ( \A_SPW_TOP|rx_data|mem[58][8]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & (((\A_SPW_TOP|rx_data|rd_ptr [5]) # 
// (\A_SPW_TOP|rx_data|mem[26][8]~q )))) # (\A_SPW_TOP|rx_data|rd_ptr [0] & (\A_SPW_TOP|rx_data|mem[59][8]~q  & ((\A_SPW_TOP|rx_data|rd_ptr [5])))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[27][8]~q  & ( !\A_SPW_TOP|rx_data|mem[58][8]~q  & ( 
// (!\A_SPW_TOP|rx_data|rd_ptr [0] & (((\A_SPW_TOP|rx_data|mem[26][8]~q  & !\A_SPW_TOP|rx_data|rd_ptr [5])))) # (\A_SPW_TOP|rx_data|rd_ptr [0] & (((!\A_SPW_TOP|rx_data|rd_ptr [5])) # (\A_SPW_TOP|rx_data|mem[59][8]~q ))) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|mem[27][8]~q  & ( !\A_SPW_TOP|rx_data|mem[58][8]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & (((\A_SPW_TOP|rx_data|mem[26][8]~q  & !\A_SPW_TOP|rx_data|rd_ptr [5])))) # (\A_SPW_TOP|rx_data|rd_ptr [0] & (\A_SPW_TOP|rx_data|mem[59][8]~q  & 
// ((\A_SPW_TOP|rx_data|rd_ptr [5])))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .datab(!\A_SPW_TOP|rx_data|mem[59][8]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[26][8]~q ),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .datae(!\A_SPW_TOP|rx_data|mem[27][8]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[58][8]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux9~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux9~8 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux9~8 .lut_mask = 64'h0A115F110ABB5FBB;
defparam \A_SPW_TOP|rx_data|Mux9~8 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y9_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux9~9 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux9~9_combout  = ( \A_SPW_TOP|rx_data|Mux9~6_combout  & ( \A_SPW_TOP|rx_data|Mux9~8_combout  & ( ((!\A_SPW_TOP|rx_data|rd_ptr [3] & ((\A_SPW_TOP|rx_data|Mux9~5_combout ))) # (\A_SPW_TOP|rx_data|rd_ptr [3] & 
// (\A_SPW_TOP|rx_data|Mux9~7_combout ))) # (\A_SPW_TOP|rx_data|rd_ptr [4]) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux9~6_combout  & ( \A_SPW_TOP|rx_data|Mux9~8_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [3] & (((\A_SPW_TOP|rx_data|Mux9~5_combout  & 
// !\A_SPW_TOP|rx_data|rd_ptr [4])))) # (\A_SPW_TOP|rx_data|rd_ptr [3] & (((\A_SPW_TOP|rx_data|rd_ptr [4])) # (\A_SPW_TOP|rx_data|Mux9~7_combout ))) ) ) ) # ( \A_SPW_TOP|rx_data|Mux9~6_combout  & ( !\A_SPW_TOP|rx_data|Mux9~8_combout  & ( 
// (!\A_SPW_TOP|rx_data|rd_ptr [3] & (((\A_SPW_TOP|rx_data|rd_ptr [4]) # (\A_SPW_TOP|rx_data|Mux9~5_combout )))) # (\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|Mux9~7_combout  & ((!\A_SPW_TOP|rx_data|rd_ptr [4])))) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|Mux9~6_combout  & ( !\A_SPW_TOP|rx_data|Mux9~8_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & ((!\A_SPW_TOP|rx_data|rd_ptr [3] & ((\A_SPW_TOP|rx_data|Mux9~5_combout ))) # (\A_SPW_TOP|rx_data|rd_ptr [3] & 
// (\A_SPW_TOP|rx_data|Mux9~7_combout )))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [3]),
        .datab(!\A_SPW_TOP|rx_data|Mux9~7_combout ),
        .datac(!\A_SPW_TOP|rx_data|Mux9~5_combout ),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [4]),
        .datae(!\A_SPW_TOP|rx_data|Mux9~6_combout ),
        .dataf(!\A_SPW_TOP|rx_data|Mux9~8_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux9~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux9~9 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux9~9 .lut_mask = 64'h1B001BAA1B551BFF;
defparam \A_SPW_TOP|rx_data|Mux9~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X35_Y7_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux9~20 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux9~20_combout  = ( \A_SPW_TOP|rx_data|Mux9~9_combout  & ( \A_SPW_TOP|rx_data|rd_ptr [2] & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & ((\A_SPW_TOP|rx_data|Mux9~14_combout ))) # (\A_SPW_TOP|rx_data|rd_ptr [1] & 
// (\A_SPW_TOP|rx_data|Mux9~19_combout )) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux9~9_combout  & ( \A_SPW_TOP|rx_data|rd_ptr [2] & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & ((\A_SPW_TOP|rx_data|Mux9~14_combout ))) # (\A_SPW_TOP|rx_data|rd_ptr [1] & 
// (\A_SPW_TOP|rx_data|Mux9~19_combout )) ) ) ) # ( \A_SPW_TOP|rx_data|Mux9~9_combout  & ( !\A_SPW_TOP|rx_data|rd_ptr [2] & ( (\A_SPW_TOP|rx_data|rd_ptr [1]) # (\A_SPW_TOP|rx_data|Mux9~4_combout ) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux9~9_combout  & ( 
// !\A_SPW_TOP|rx_data|rd_ptr [2] & ( (\A_SPW_TOP|rx_data|Mux9~4_combout  & !\A_SPW_TOP|rx_data|rd_ptr [1]) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux9~4_combout ),
        .datab(!\A_SPW_TOP|rx_data|Mux9~19_combout ),
        .datac(!\A_SPW_TOP|rx_data|Mux9~14_combout ),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datae(!\A_SPW_TOP|rx_data|Mux9~9_combout ),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux9~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux9~20 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux9~20 .lut_mask = 64'h550055FF0F330F33;
defparam \A_SPW_TOP|rx_data|Mux9~20 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y7_N58
dffeas \A_SPW_TOP|rx_data|data_out[8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Mux9~20_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|data_out [8]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|data_out[8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|data_out[8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y16_N30
cyclonev_lcell_comb \u0|data_flag_rx|read_mux_out[8] (
// Equation(s):
// \u0|data_flag_rx|read_mux_out [8] = ( \A_SPW_TOP|rx_data|data_out [8] & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|data_out [8]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|data_flag_rx|read_mux_out [8]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|data_flag_rx|read_mux_out[8] .extended_lut = "off";
defparam \u0|data_flag_rx|read_mux_out[8] .lut_mask = 64'h0000000088888888;
defparam \u0|data_flag_rx|read_mux_out[8] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y16_N32
dffeas \u0|data_flag_rx|readdata[8] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|data_flag_rx|read_mux_out [8]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|data_flag_rx|readdata [8]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|data_flag_rx|readdata[8] .is_wysiwyg = "true";
defparam \u0|data_flag_rx|readdata[8] .power_up = "low";
// synopsys translate_on

// Location: FF_X23_Y16_N56
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre[8] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|data_flag_rx|readdata [8]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [8]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre[8] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre[8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y16_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~8 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~8_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][8]~q  ) ) # ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [8] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][8]~q ),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [8]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~8 .lut_mask = 64'h00FF00FF0F0F0F0F;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~8 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y34_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always0~0_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|read~0_combout  ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|read~0_combout  & ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [0] ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [0]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|read~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always0~0 .lut_mask = 64'hAAAAAAAAFFFFFFFF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y16_N7
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][8] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][8] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y34_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg [0] & ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [0] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0 .lut_mask = 64'h00000000F0F0F0F0;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X53_Y9_N41
dffeas \m_x|info[8] (
        .clk(!\m_x|always3~0_combout ),
        .d(gnd),
        .asdata(\m_x|control [2]),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\m_x|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|info [8]),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|info[8] .is_wysiwyg = "true";
defparam \m_x|info[8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y16_N3
cyclonev_lcell_comb \u0|data_info|read_mux_out[8] (
// Equation(s):
// \u0|data_info|read_mux_out [8] = ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & ( 
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & \m_x|info [8]) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datab(gnd),
        .datac(!\m_x|info [8]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|data_info|read_mux_out [8]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|data_info|read_mux_out[8] .extended_lut = "off";
defparam \u0|data_info|read_mux_out[8] .lut_mask = 64'h0A0A0A0A00000000;
defparam \u0|data_info|read_mux_out[8] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y16_N5
dffeas \u0|data_info|readdata[8] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|data_info|read_mux_out [8]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|data_info|readdata [8]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|data_info|readdata[8] .is_wysiwyg = "true";
defparam \u0|data_info|readdata[8] .power_up = "low";
// synopsys translate_on

// Location: FF_X30_Y16_N53
dffeas \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[8] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|data_info|readdata [8]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [8]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[8] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[8] .power_up = "low";
// synopsys translate_on

// Location: FF_X30_Y16_N56
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][8] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][8] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y16_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~8 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~8_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][8]~q  ) ) # ( 
// !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [8] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [8]),
        .datad(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][8]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~8 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y16_N37
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][8] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~8_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][8]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][8] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y16_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[8]~83 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[8]~83_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout  & ( (!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout  & 
// ((\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][8]~q ))) # (\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout  & (\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [8])) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [8]),
        .datab(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][8]~q ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[8]~83_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[8]~83 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[8]~83 .lut_mask = 64'h0000000035353535;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[8]~83 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y16_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[8]~84 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[8]~84_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [8] & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[8]~83_combout  & ( 
// ((!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][8]~q  & !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout )) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout ) ) ) ) # ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [8] & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[8]~83_combout  & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][8]~q ) # 
// ((\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout ) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][8]~q ),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout ),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [8]),
        .dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[8]~83_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[8]~84_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[8]~84 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[8]~84 .lut_mask = 64'hBFBF8F8F00000000;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[8]~84 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y15_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[8]~85 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[8]~85_combout  = ( \u0|mm_interconnect_0|rsp_mux_001|src_data[8]~84_combout  & ( (\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout  & 
// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout  & ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][8]~q ))) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout  & 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [8])))) ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[8]~84_combout  )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [8]),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout ),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][8]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[8]~84_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[8]~85_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[8]~85 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[8]~85 .lut_mask = 64'hFFFFFFFF01510151;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[8]~85 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y30_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|LessThan18~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|LessThan18~0_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARLEN [0] & ( \u0|hps_0|fpga_interfaces|h2f_ARLEN [1] & ( (!\u0|hps_0|fpga_interfaces|h2f_ARLEN [3] & (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & 
// (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] $ (!\u0|hps_0|fpga_interfaces|h2f_ARLEN [2])))) # (\u0|hps_0|fpga_interfaces|h2f_ARLEN [3] & (\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & (\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]))) ) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0] & ( \u0|hps_0|fpga_interfaces|h2f_ARLEN [1] & ( (!\u0|hps_0|fpga_interfaces|h2f_ARLEN [3] & (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] $ 
// (!\u0|hps_0|fpga_interfaces|h2f_ARLEN [2])))) # (\u0|hps_0|fpga_interfaces|h2f_ARLEN [3] & (\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & (\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]))) ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_ARLEN [0] & ( 
// !\u0|hps_0|fpga_interfaces|h2f_ARLEN [1] & ( (!\u0|hps_0|fpga_interfaces|h2f_ARLEN [3] & (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] & (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] $ (!\u0|hps_0|fpga_interfaces|h2f_ARLEN [2])))) # 
// (\u0|hps_0|fpga_interfaces|h2f_ARLEN [3] & (\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & (\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]))) ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0] & ( !\u0|hps_0|fpga_interfaces|h2f_ARLEN [1] & ( 
// (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & (!\u0|hps_0|fpga_interfaces|h2f_ARLEN [3] & (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] & \u0|hps_0|fpga_interfaces|h2f_ARLEN [2]))) # (\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & 
// (\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] & ((!\u0|hps_0|fpga_interfaces|h2f_ARLEN [2]) # (\u0|hps_0|fpga_interfaces|h2f_ARLEN [3])))) ) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [3]),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [2]),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|LessThan18~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|LessThan18~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|LessThan18~0 .lut_mask = 64'h0381218109810981;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|LessThan18~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y30_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout  & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|LessThan18~0_combout ) # 
// ((!\u0|hps_0|fpga_interfaces|h2f_ARBURST [1] & (!\u0|hps_0|fpga_interfaces|h2f_ARBURST [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~5_sumout ))) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout  & ( 
// (!\u0|hps_0|fpga_interfaces|h2f_ARBURST [1] & (!\u0|hps_0|fpga_interfaces|h2f_ARBURST [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~5_sumout )) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARBURST [1]),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARBURST [0]),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|LessThan18~0_combout ),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~5_sumout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0 .lut_mask = 64'h88008800F8F0F8F0;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y18_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_data[81] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_data [81] = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout  & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~0_combout  & ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] ) ) 
// ) # ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout  & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~0_combout  & ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] ) ) ) # ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout  & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~0_combout  & ( (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]) # (\u0|mm_interconnect_0|cmd_mux_010|saved_grant 
// [1]) ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout ),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_010|src_data [81]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[81] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[81] .lut_mask = 64'h3F3F0F0F33330000;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[81] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y18_N35
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_010|src_data [81]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y18_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2] = ( \u0|mm_interconnect_0|cmd_mux_010|src_data [81] & ( 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] & (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_010|src_data [81] & ( 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout  & 
// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q 
// ))) ) )

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_010|src_data [81]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .lut_mask = 64'h0B0B0B0B08080808;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y18_N35
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y20_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout  & ( 
// ((\u0|hps_0|fpga_interfaces|h2f_ARADDR [2] & \u0|mm_interconnect_0|cmd_mux_010|saved_grant [1])) # (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout  & 
// ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [2] & \u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [2]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 .lut_mask = 64'h000F000F333F333F;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y18_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout  & 
// ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg 
// [2])) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]))) # 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout 
// )))) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout  & ( 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2])) 
// # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 .lut_mask = 64'h0C3F0C3F4C7F4C7F;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y18_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2]~feeder_combout  = ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y18_N26
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y14_N9
cyclonev_lcell_comb \u0|write_data_fifo_tx|readdata[7] (
// Equation(s):
// \u0|write_data_fifo_tx|readdata [7] = ( \u0|write_data_fifo_tx|data_out [7] & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]) ) )

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|write_data_fifo_tx|data_out [7]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|write_data_fifo_tx|readdata [7]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|write_data_fifo_tx|readdata[7] .extended_lut = "off";
defparam \u0|write_data_fifo_tx|readdata[7] .lut_mask = 64'h0000000088888888;
defparam \u0|write_data_fifo_tx|readdata[7] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y14_N11
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre[7] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|write_data_fifo_tx|readdata [7]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [7]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre[7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre[7] .power_up = "low";
// synopsys translate_on

// Location: FF_X28_Y15_N59
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][7] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~7_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y15_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~7 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~7_combout  = (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1] & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [7])) # 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1] & ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][7]~q )))

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [7]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][7]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~7 .lut_mask = 64'h505F505F505F505F;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~7 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y15_N17
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][7] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~7_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y15_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~79 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~79_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [7] & ( (\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout  & 
// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][7]~q ) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout ))) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [7] & ( 
// (\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout  & (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout  & \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][7]~q )) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout ),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][7]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [7]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[7]~79_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~79 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~79 .lut_mask = 64'h0044004411551155;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~79 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X53_Y9_N37
dffeas \m_x|info[7] (
        .clk(!\m_x|always3~0_combout ),
        .d(gnd),
        .asdata(\m_x|control [1]),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\m_x|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|info [7]),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|info[7] .is_wysiwyg = "true";
defparam \m_x|info[7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y16_N27
cyclonev_lcell_comb \u0|data_info|read_mux_out[7] (
// Equation(s):
// \u0|data_info|read_mux_out [7] = ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & ( 
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & \m_x|info [7]) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datab(gnd),
        .datac(!\m_x|info [7]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|data_info|read_mux_out [7]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|data_info|read_mux_out[7] .extended_lut = "off";
defparam \u0|data_info|read_mux_out[7] .lut_mask = 64'h0A0A0A0A00000000;
defparam \u0|data_info|read_mux_out[7] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y16_N29
dffeas \u0|data_info|readdata[7] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|data_info|read_mux_out [7]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|data_info|readdata [7]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|data_info|readdata[7] .is_wysiwyg = "true";
defparam \u0|data_info|readdata[7] .power_up = "low";
// synopsys translate_on

// Location: FF_X30_Y16_N28
dffeas \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[7] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|data_info|readdata [7]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [7]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y18_N45
cyclonev_lcell_comb \u0|timecode_tx_data|readdata[7] (
// Equation(s):
// \u0|timecode_tx_data|readdata [7] = ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & \u0|timecode_tx_data|data_out [7]) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datab(gnd),
        .datac(!\u0|timecode_tx_data|data_out [7]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|timecode_tx_data|readdata [7]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|timecode_tx_data|readdata[7] .extended_lut = "off";
defparam \u0|timecode_tx_data|readdata[7] .lut_mask = 64'h0A0A0A0A00000000;
defparam \u0|timecode_tx_data|readdata[7] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y18_N47
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre[7] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|timecode_tx_data|readdata [7]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [7]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre[7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre[7] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y18_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|read~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|read~0_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][129]~q  & ( ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0] & 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0]) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][129]~q  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0] & !\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0]) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|read~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|read~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|read~0 .lut_mask = 64'hF000F000F555F555;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|read~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y18_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|read~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|read~1_combout  = ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|read~0_combout  & ( \u0|mm_interconnect_0|rsp_demux_014|WideOr0~0_combout  ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_014|WideOr0~0_combout ),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|read~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|read~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|read~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|read~1 .lut_mask = 64'h5555555500000000;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|read~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y18_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[1]~1_combout  = ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|read~1_combout  & ( ((\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0] & 
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|read~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[1]~1 .lut_mask = 64'h03FF03FF00000000;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[1]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y18_N14
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X25_Y18_N44
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][7] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~7_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][7] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y18_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~7 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~7_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [7] & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1]) # 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][7]~q ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [7] & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][7]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][7]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [7]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~7 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~7 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y18_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|always0~0_combout  = ( \u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ( \u0|hps_0|fpga_interfaces|h2f_BREADY [0] & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|read~0_combout ) # 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0]) ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ( \u0|hps_0|fpga_interfaces|h2f_BREADY [0] & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0]) # 
// ((\u0|mm_interconnect_0|rsp_demux_014|src0_valid~0_combout  & !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|read~0_combout )) ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ( !\u0|hps_0|fpga_interfaces|h2f_BREADY [0] & ( 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0]) # ((!\u0|mm_interconnect_0|rsp_demux_014|src0_valid~0_combout  & !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|read~0_combout )) ) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ( !\u0|hps_0|fpga_interfaces|h2f_BREADY [0] & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0] ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_014|src0_valid~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|read~0_combout ),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0]),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_BREADY [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|always0~0 .lut_mask = 64'hFF00FF88FF44FFCC;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y18_N25
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][7] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~7_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][7] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y18_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~80 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~80_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][7]~q  & ( (\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout  & 
// (((!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0]) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [7]))) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][7]~q  & ( (\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout  & (\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [7] & 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0]))) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [7]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[7]~80_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~80 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~80 .lut_mask = 64'h0100010051555155;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~80 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y2_N24
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|rx_data_flag~0 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|rx_data_flag~0_combout  = ( \A_SPW_TOP|SPW|RX|control_p_r [0] & ( (\A_SPW_TOP|SPW|RX|ready_control_p_r~q  & ((!\A_SPW_TOP|SPW|RX|control_p_r [2]) # (\A_SPW_TOP|SPW|RX|control_p_r [1]))) ) ) # ( !\A_SPW_TOP|SPW|RX|control_p_r [0] & ( 
// (\A_SPW_TOP|SPW|RX|ready_control_p_r~q  & ((!\A_SPW_TOP|SPW|RX|control_p_r [2]) # (!\A_SPW_TOP|SPW|RX|control_p_r [1]))) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),
        .datac(!\A_SPW_TOP|SPW|RX|control_p_r [2]),
        .datad(!\A_SPW_TOP|SPW|RX|control_p_r [1]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|control_p_r [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|rx_data_flag~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_data_flag~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|rx_data_flag~0 .lut_mask = 64'h3330333030333033;
defparam \A_SPW_TOP|SPW|RX|rx_data_flag~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y2_N27
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|rx_data_flag~7 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|rx_data_flag~7_combout  = ( \A_SPW_TOP|SPW|RX|rx_data_flag~0_combout  & ( ((!\A_SPW_TOP|SPW|RX|ready_control_p_r~q  & (\A_SPW_TOP|SPW|RX|dta_timec_p [7] & !\A_SPW_TOP|SPW|RX|data~0_combout ))) # (\A_SPW_TOP|SPW|RX|rx_data_flag [7]) ) ) # 
// ( !\A_SPW_TOP|SPW|RX|rx_data_flag~0_combout  & ( (!\A_SPW_TOP|SPW|RX|ready_control_p_r~q  & ((!\A_SPW_TOP|SPW|RX|data~0_combout  & ((\A_SPW_TOP|SPW|RX|dta_timec_p [7]))) # (\A_SPW_TOP|SPW|RX|data~0_combout  & (\A_SPW_TOP|SPW|RX|rx_data_flag [7])))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .datab(!\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),
        .datac(!\A_SPW_TOP|SPW|RX|dta_timec_p [7]),
        .datad(!\A_SPW_TOP|SPW|RX|data~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|rx_data_flag~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|rx_data_flag~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_data_flag~7 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|rx_data_flag~7 .lut_mask = 64'h0C440C445D555D55;
defparam \A_SPW_TOP|SPW|RX|rx_data_flag~7 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y2_N50
dffeas \A_SPW_TOP|SPW|RX|rx_data_flag[7] (
        .clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|RX|rx_data_flag~7_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(!\A_SPW_TOP|SPW|RX|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_data_flag[7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|rx_data_flag[7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y3_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector371~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector371~0_combout  = ( \A_SPW_TOP|rx_data|mem[39][7]~q  & ( (!\A_SPW_TOP|rx_data|Selector370~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [7]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux1~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[39][7]~q  & ( (\A_SPW_TOP|rx_data|Selector370~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [7]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux1~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .datac(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .datad(!\A_SPW_TOP|rx_data|Selector370~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[39][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector371~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector371~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector371~0 .lut_mask = 64'h001B001BFF1BFF1B;
defparam \A_SPW_TOP|rx_data|Selector371~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y3_N26
dffeas \A_SPW_TOP|rx_data|mem[39][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector371~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[39][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[39][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[39][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y3_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector344~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector344~0_combout  = ( \A_SPW_TOP|rx_data|mem[36][7]~q  & ( (!\A_SPW_TOP|rx_data|Selector343~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [7]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux1~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[36][7]~q  & ( (\A_SPW_TOP|rx_data|Selector343~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [7]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux1~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector343~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[36][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector344~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector344~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector344~0 .lut_mask = 64'h010B010BF1FBF1FB;
defparam \A_SPW_TOP|rx_data|Selector344~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y3_N8
dffeas \A_SPW_TOP|rx_data|mem[36][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector344~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[36][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[36][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[36][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y3_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector362~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector362~0_combout  = ( \A_SPW_TOP|rx_data|mem[38][7]~q  & ( (!\A_SPW_TOP|rx_data|Selector361~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [7]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux1~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[38][7]~q  & ( (\A_SPW_TOP|rx_data|Selector361~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [7]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux1~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector361~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[38][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector362~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector362~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector362~0 .lut_mask = 64'h010B010BF1FBF1FB;
defparam \A_SPW_TOP|rx_data|Selector362~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y3_N50
dffeas \A_SPW_TOP|rx_data|mem[38][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector362~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[38][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[38][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[38][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y3_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector353~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector353~0_combout  = ( \A_SPW_TOP|SPW|RX|rx_data_flag [7] & ( (!\A_SPW_TOP|rx_data|Selector352~0_combout  & (((\A_SPW_TOP|rx_data|mem[37][7]~q )))) # (\A_SPW_TOP|rx_data|Selector352~0_combout  & 
// ((!\A_SPW_TOP|rx_data|state_data_write.00~q ) # ((\A_SPW_TOP|rx_data|Mux1~20_combout )))) ) ) # ( !\A_SPW_TOP|SPW|RX|rx_data_flag [7] & ( (!\A_SPW_TOP|rx_data|Selector352~0_combout  & (((\A_SPW_TOP|rx_data|mem[37][7]~q )))) # 
// (\A_SPW_TOP|rx_data|Selector352~0_combout  & (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux1~20_combout ))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector352~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[37][7]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector353~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector353~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector353~0 .lut_mask = 64'h01F101F10BFB0BFB;
defparam \A_SPW_TOP|rx_data|Selector353~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y3_N38
dffeas \A_SPW_TOP|rx_data|mem[37][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector353~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[37][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[37][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[37][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y3_N51
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux1~12 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux1~12_combout  = ( \A_SPW_TOP|rx_data|mem[37][7]~q  & ( \A_SPW_TOP|rx_data|wr_ptr [0] & ( (!\A_SPW_TOP|rx_data|wr_ptr [1]) # (\A_SPW_TOP|rx_data|mem[39][7]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[37][7]~q  & ( \A_SPW_TOP|rx_data|wr_ptr 
// [0] & ( (\A_SPW_TOP|rx_data|mem[39][7]~q  & \A_SPW_TOP|rx_data|wr_ptr [1]) ) ) ) # ( \A_SPW_TOP|rx_data|mem[37][7]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [0] & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|mem[36][7]~q )) # (\A_SPW_TOP|rx_data|wr_ptr 
// [1] & ((\A_SPW_TOP|rx_data|mem[38][7]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[37][7]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [0] & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|mem[36][7]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [1] & 
// ((\A_SPW_TOP|rx_data|mem[38][7]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[39][7]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[36][7]~q ),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datad(!\A_SPW_TOP|rx_data|mem[38][7]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[37][7]~q ),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux1~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux1~12 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux1~12 .lut_mask = 64'h303F303F0505F5F5;
defparam \A_SPW_TOP|rx_data|Mux1~12 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y3_N15
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector65~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector65~0_combout  = ( \A_SPW_TOP|rx_data|Selector64~0_combout  & ( \A_SPW_TOP|rx_data|mem[5][7]~q  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [7])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  
// & ((\A_SPW_TOP|rx_data|Mux1~20_combout ))) ) ) ) # ( !\A_SPW_TOP|rx_data|Selector64~0_combout  & ( \A_SPW_TOP|rx_data|mem[5][7]~q  ) ) # ( \A_SPW_TOP|rx_data|Selector64~0_combout  & ( !\A_SPW_TOP|rx_data|mem[5][7]~q  & ( 
// (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [7])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux1~20_combout ))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .datac(!\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|rx_data|Selector64~0_combout ),
        .dataf(!\A_SPW_TOP|rx_data|mem[5][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector65~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector65~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector65~0 .lut_mask = 64'h00002727FFFF2727;
defparam \A_SPW_TOP|rx_data|Selector65~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y3_N11
dffeas \A_SPW_TOP|rx_data|mem[5][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector65~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[5][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[5][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[5][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X36_Y3_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector56~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector56~0_combout  = ( \A_SPW_TOP|SPW|RX|rx_data_flag [7] & ( (!\A_SPW_TOP|rx_data|Selector55~0_combout  & (((\A_SPW_TOP|rx_data|mem[4][7]~q )))) # (\A_SPW_TOP|rx_data|Selector55~0_combout  & 
// ((!\A_SPW_TOP|rx_data|state_data_write.00~q ) # ((\A_SPW_TOP|rx_data|Mux1~20_combout )))) ) ) # ( !\A_SPW_TOP|SPW|RX|rx_data_flag [7] & ( (!\A_SPW_TOP|rx_data|Selector55~0_combout  & (((\A_SPW_TOP|rx_data|mem[4][7]~q )))) # 
// (\A_SPW_TOP|rx_data|Selector55~0_combout  & (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux1~20_combout ))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|mem[4][7]~q ),
        .datad(!\A_SPW_TOP|rx_data|Selector55~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector56~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector56~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector56~0 .lut_mask = 64'h0F110F110FBB0FBB;
defparam \A_SPW_TOP|rx_data|Selector56~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X36_Y3_N23
dffeas \A_SPW_TOP|rx_data|mem[4][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector56~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[4][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[4][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[4][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y3_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector83~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector83~0_combout  = ( \A_SPW_TOP|rx_data|mem[7][7]~q  & ( (!\A_SPW_TOP|rx_data|Selector82~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [7])) # (\A_SPW_TOP|rx_data|state_data_write.00~q 
//  & ((\A_SPW_TOP|rx_data|Mux1~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[7][7]~q  & ( (\A_SPW_TOP|rx_data|Selector82~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [7])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux1~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .datac(!\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .datad(!\A_SPW_TOP|rx_data|Selector82~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[7][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector83~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector83~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector83~0 .lut_mask = 64'h00270027FF27FF27;
defparam \A_SPW_TOP|rx_data|Selector83~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y3_N32
dffeas \A_SPW_TOP|rx_data|mem[7][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector83~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[7][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[7][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[7][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y3_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector74~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector74~0_combout  = ( \A_SPW_TOP|rx_data|mem[6][7]~q  & ( (!\A_SPW_TOP|rx_data|Selector73~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [7])) # (\A_SPW_TOP|rx_data|state_data_write.00~q 
//  & ((\A_SPW_TOP|rx_data|Mux1~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[6][7]~q  & ( (\A_SPW_TOP|rx_data|Selector73~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [7])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux1~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .datac(!\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .datad(!\A_SPW_TOP|rx_data|Selector73~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[6][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector74~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector74~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector74~0 .lut_mask = 64'h00270027FF27FF27;
defparam \A_SPW_TOP|rx_data|Selector74~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y3_N11
dffeas \A_SPW_TOP|rx_data|mem[6][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector74~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[6][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[6][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[6][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y3_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux1~10 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux1~10_combout  = ( \A_SPW_TOP|rx_data|mem[7][7]~q  & ( \A_SPW_TOP|rx_data|mem[6][7]~q  & ( ((!\A_SPW_TOP|rx_data|wr_ptr [0] & ((\A_SPW_TOP|rx_data|mem[4][7]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|mem[5][7]~q ))) 
// # (\A_SPW_TOP|rx_data|wr_ptr [1]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[7][7]~q  & ( \A_SPW_TOP|rx_data|mem[6][7]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & ((!\A_SPW_TOP|rx_data|wr_ptr [0] & ((\A_SPW_TOP|rx_data|mem[4][7]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [0] 
// & (\A_SPW_TOP|rx_data|mem[5][7]~q )))) # (\A_SPW_TOP|rx_data|wr_ptr [1] & (((!\A_SPW_TOP|rx_data|wr_ptr [0])))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[7][7]~q  & ( !\A_SPW_TOP|rx_data|mem[6][7]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & 
// ((!\A_SPW_TOP|rx_data|wr_ptr [0] & ((\A_SPW_TOP|rx_data|mem[4][7]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|mem[5][7]~q )))) # (\A_SPW_TOP|rx_data|wr_ptr [1] & (((\A_SPW_TOP|rx_data|wr_ptr [0])))) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|mem[7][7]~q  & ( !\A_SPW_TOP|rx_data|mem[6][7]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & ((!\A_SPW_TOP|rx_data|wr_ptr [0] & ((\A_SPW_TOP|rx_data|mem[4][7]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|mem[5][7]~q )))) ) ) 
// )

        .dataa(!\A_SPW_TOP|rx_data|mem[5][7]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[4][7]~q ),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datae(!\A_SPW_TOP|rx_data|mem[7][7]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[6][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux1~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux1~10 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux1~10 .lut_mask = 64'h3050305F3F503F5F;
defparam \A_SPW_TOP|rx_data|Mux1~10 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y4_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector416~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector416~0_combout  = ( \A_SPW_TOP|rx_data|Selector415~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [7]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux1~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector415~0_combout  & ( \A_SPW_TOP|rx_data|mem[44][7]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .datac(!\A_SPW_TOP|rx_data|mem[44][7]~q ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector415~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector416~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector416~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector416~0 .lut_mask = 64'h0F0F0F0F33553355;
defparam \A_SPW_TOP|rx_data|Selector416~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y4_N38
dffeas \A_SPW_TOP|rx_data|mem[44][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector416~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[44][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[44][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[44][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y4_N45
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector425~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector425~0_combout  = ( \A_SPW_TOP|rx_data|Selector424~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [7]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux1~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector424~0_combout  & ( \A_SPW_TOP|rx_data|mem[45][7]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .datac(!\A_SPW_TOP|rx_data|mem[45][7]~q ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector424~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector425~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector425~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector425~0 .lut_mask = 64'h0F0F0F0F33553355;
defparam \A_SPW_TOP|rx_data|Selector425~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y4_N17
dffeas \A_SPW_TOP|rx_data|mem[45][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector425~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[45][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[45][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[45][7] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X32_Y4_N27
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector434~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector434~0_combout  = ( \A_SPW_TOP|rx_data|mem[46][7]~q  & ( (!\A_SPW_TOP|rx_data|Selector433~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [7]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux1~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[46][7]~q  & ( (\A_SPW_TOP|rx_data|Selector433~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [7]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux1~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .datad(!\A_SPW_TOP|rx_data|Selector433~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[46][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector434~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector434~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector434~0 .lut_mask = 64'h001D001DFF1DFF1D;
defparam \A_SPW_TOP|rx_data|Selector434~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X32_Y4_N53
dffeas \A_SPW_TOP|rx_data|mem[46][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector434~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[46][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[46][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[46][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y4_N57
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector443~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector443~0_combout  = ( \A_SPW_TOP|rx_data|mem[47][7]~q  & ( (!\A_SPW_TOP|rx_data|Selector442~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [7]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux1~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[47][7]~q  & ( (\A_SPW_TOP|rx_data|Selector442~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [7]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux1~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .datac(!\A_SPW_TOP|rx_data|Selector442~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[47][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector443~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector443~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector443~0 .lut_mask = 64'h03050305F3F5F3F5;
defparam \A_SPW_TOP|rx_data|Selector443~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y4_N35
dffeas \A_SPW_TOP|rx_data|mem[47][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector443~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[47][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[47][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[47][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y4_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux1~13 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux1~13_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [0] & ( \A_SPW_TOP|rx_data|mem[47][7]~q  & ( (\A_SPW_TOP|rx_data|wr_ptr [1]) # (\A_SPW_TOP|rx_data|mem[45][7]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [0] & ( 
// \A_SPW_TOP|rx_data|mem[47][7]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|mem[44][7]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [1] & ((\A_SPW_TOP|rx_data|mem[46][7]~q ))) ) ) ) # ( \A_SPW_TOP|rx_data|wr_ptr [0] & ( 
// !\A_SPW_TOP|rx_data|mem[47][7]~q  & ( (\A_SPW_TOP|rx_data|mem[45][7]~q  & !\A_SPW_TOP|rx_data|wr_ptr [1]) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [0] & ( !\A_SPW_TOP|rx_data|mem[47][7]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|mem[44][7]~q 
// )) # (\A_SPW_TOP|rx_data|wr_ptr [1] & ((\A_SPW_TOP|rx_data|mem[46][7]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[44][7]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[45][7]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[46][7]~q ),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .dataf(!\A_SPW_TOP|rx_data|mem[47][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux1~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux1~13 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux1~13 .lut_mask = 64'h550F3300550F33FF;
defparam \A_SPW_TOP|rx_data|Mux1~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X31_Y4_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector146~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector146~0_combout  = ( \A_SPW_TOP|rx_data|Selector145~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [7]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux1~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector145~0_combout  & ( \A_SPW_TOP|rx_data|mem[14][7]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .datac(!\A_SPW_TOP|rx_data|mem[14][7]~q ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector145~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector146~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector146~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector146~0 .lut_mask = 64'h0F0F0F0F33553355;
defparam \A_SPW_TOP|rx_data|Selector146~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y4_N23
dffeas \A_SPW_TOP|rx_data|mem[14][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector146~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[14][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[14][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[14][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y4_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector137~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector137~0_combout  = ( \A_SPW_TOP|rx_data|Selector136~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [7]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux1~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector136~0_combout  & ( \A_SPW_TOP|rx_data|mem[13][7]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .datac(!\A_SPW_TOP|rx_data|mem[13][7]~q ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector136~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector137~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector137~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector137~0 .lut_mask = 64'h0F0F0F0F33553355;
defparam \A_SPW_TOP|rx_data|Selector137~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y4_N29
dffeas \A_SPW_TOP|rx_data|mem[13][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector137~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[13][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[13][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[13][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y4_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector128~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector128~0_combout  = ( \A_SPW_TOP|rx_data|Selector127~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [7]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux1~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector127~0_combout  & ( \A_SPW_TOP|rx_data|mem[12][7]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .datac(!\A_SPW_TOP|rx_data|mem[12][7]~q ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector127~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector128~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector128~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector128~0 .lut_mask = 64'h0F0F0F0F33553355;
defparam \A_SPW_TOP|rx_data|Selector128~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y4_N53
dffeas \A_SPW_TOP|rx_data|mem[12][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector128~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[12][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[12][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[12][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y4_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector155~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector155~0_combout  = ( \A_SPW_TOP|rx_data|mem[15][7]~q  & ( (!\A_SPW_TOP|rx_data|Selector154~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [7]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux1~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[15][7]~q  & ( (\A_SPW_TOP|rx_data|Selector154~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [7]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux1~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .datac(!\A_SPW_TOP|rx_data|Selector154~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[15][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector155~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector155~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector155~0 .lut_mask = 64'h03050305F3F5F3F5;
defparam \A_SPW_TOP|rx_data|Selector155~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y4_N26
dffeas \A_SPW_TOP|rx_data|mem[15][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector155~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[15][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[15][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[15][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y4_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux1~11 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux1~11_combout  = ( \A_SPW_TOP|rx_data|mem[15][7]~q  & ( \A_SPW_TOP|rx_data|wr_ptr [1] & ( (\A_SPW_TOP|rx_data|wr_ptr [0]) # (\A_SPW_TOP|rx_data|mem[14][7]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[15][7]~q  & ( \A_SPW_TOP|rx_data|wr_ptr 
// [1] & ( (\A_SPW_TOP|rx_data|mem[14][7]~q  & !\A_SPW_TOP|rx_data|wr_ptr [0]) ) ) ) # ( \A_SPW_TOP|rx_data|mem[15][7]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [1] & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & ((\A_SPW_TOP|rx_data|mem[12][7]~q ))) # 
// (\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|mem[13][7]~q )) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[15][7]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [1] & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & ((\A_SPW_TOP|rx_data|mem[12][7]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr 
// [0] & (\A_SPW_TOP|rx_data|mem[13][7]~q )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[14][7]~q ),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datac(!\A_SPW_TOP|rx_data|mem[13][7]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[12][7]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[15][7]~q ),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux1~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux1~11 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux1~11 .lut_mask = 64'h03CF03CF44447777;
defparam \A_SPW_TOP|rx_data|Mux1~11 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y3_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux1~14 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux1~14_combout  = ( \A_SPW_TOP|rx_data|Mux1~13_combout  & ( \A_SPW_TOP|rx_data|Mux1~11_combout  & ( ((!\A_SPW_TOP|rx_data|wr_ptr [5] & ((\A_SPW_TOP|rx_data|Mux1~10_combout ))) # (\A_SPW_TOP|rx_data|wr_ptr [5] & 
// (\A_SPW_TOP|rx_data|Mux1~12_combout ))) # (\A_SPW_TOP|rx_data|wr_ptr [3]) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux1~13_combout  & ( \A_SPW_TOP|rx_data|Mux1~11_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [3] & ((!\A_SPW_TOP|rx_data|wr_ptr [5] & 
// ((\A_SPW_TOP|rx_data|Mux1~10_combout ))) # (\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|Mux1~12_combout )))) # (\A_SPW_TOP|rx_data|wr_ptr [3] & (((!\A_SPW_TOP|rx_data|wr_ptr [5])))) ) ) ) # ( \A_SPW_TOP|rx_data|Mux1~13_combout  & ( 
// !\A_SPW_TOP|rx_data|Mux1~11_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [3] & ((!\A_SPW_TOP|rx_data|wr_ptr [5] & ((\A_SPW_TOP|rx_data|Mux1~10_combout ))) # (\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|Mux1~12_combout )))) # (\A_SPW_TOP|rx_data|wr_ptr 
// [3] & (((\A_SPW_TOP|rx_data|wr_ptr [5])))) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux1~13_combout  & ( !\A_SPW_TOP|rx_data|Mux1~11_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [3] & ((!\A_SPW_TOP|rx_data|wr_ptr [5] & ((\A_SPW_TOP|rx_data|Mux1~10_combout ))) # 
// (\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|Mux1~12_combout )))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datab(!\A_SPW_TOP|rx_data|Mux1~12_combout ),
        .datac(!\A_SPW_TOP|rx_data|Mux1~10_combout ),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datae(!\A_SPW_TOP|rx_data|Mux1~13_combout ),
        .dataf(!\A_SPW_TOP|rx_data|Mux1~11_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux1~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux1~14 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux1~14 .lut_mask = 64'h0A220A775F225F77;
defparam \A_SPW_TOP|rx_data|Mux1~14 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X35_Y3_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector533~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector533~0_combout  = ( \A_SPW_TOP|rx_data|Mux1~20_combout  & ( \A_SPW_TOP|SPW|RX|rx_data_flag [7] & ( (\A_SPW_TOP|rx_data|mem[57][7]~q ) # (\A_SPW_TOP|rx_data|Selector532~0_combout ) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux1~20_combout  & 
// ( \A_SPW_TOP|SPW|RX|rx_data_flag [7] & ( (!\A_SPW_TOP|rx_data|Selector532~0_combout  & ((\A_SPW_TOP|rx_data|mem[57][7]~q ))) # (\A_SPW_TOP|rx_data|Selector532~0_combout  & (!\A_SPW_TOP|rx_data|state_data_write.00~q )) ) ) ) # ( 
// \A_SPW_TOP|rx_data|Mux1~20_combout  & ( !\A_SPW_TOP|SPW|RX|rx_data_flag [7] & ( (!\A_SPW_TOP|rx_data|Selector532~0_combout  & ((\A_SPW_TOP|rx_data|mem[57][7]~q ))) # (\A_SPW_TOP|rx_data|Selector532~0_combout  & (\A_SPW_TOP|rx_data|state_data_write.00~q )) 
// ) ) ) # ( !\A_SPW_TOP|rx_data|Mux1~20_combout  & ( !\A_SPW_TOP|SPW|RX|rx_data_flag [7] & ( (!\A_SPW_TOP|rx_data|Selector532~0_combout  & \A_SPW_TOP|rx_data|mem[57][7]~q ) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Selector532~0_combout ),
        .datac(!\A_SPW_TOP|rx_data|mem[57][7]~q ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .dataf(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector533~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector533~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector533~0 .lut_mask = 64'h0C0C1D1D2E2E3F3F;
defparam \A_SPW_TOP|rx_data|Selector533~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X33_Y3_N8
dffeas \A_SPW_TOP|rx_data|mem[57][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector533~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[57][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[57][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[57][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X36_Y3_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector551~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector551~0_combout  = ( \A_SPW_TOP|rx_data|mem[59][7]~q  & ( (!\A_SPW_TOP|rx_data|Selector550~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [7]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux1~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[59][7]~q  & ( (\A_SPW_TOP|rx_data|Selector550~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [7]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux1~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector550~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[59][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector551~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector551~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector551~0 .lut_mask = 64'h010B010BF1FBF1FB;
defparam \A_SPW_TOP|rx_data|Selector551~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X36_Y3_N53
dffeas \A_SPW_TOP|rx_data|mem[59][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector551~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[59][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[59][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[59][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y3_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector542~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector542~0_combout  = ( \A_SPW_TOP|rx_data|Selector541~0_combout  & ( \A_SPW_TOP|SPW|RX|rx_data_flag [7] & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|rx_data|Mux1~20_combout ) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|Selector541~0_combout  & ( \A_SPW_TOP|SPW|RX|rx_data_flag [7] & ( \A_SPW_TOP|rx_data|mem[58][7]~q  ) ) ) # ( \A_SPW_TOP|rx_data|Selector541~0_combout  & ( !\A_SPW_TOP|SPW|RX|rx_data_flag [7] & ( (\A_SPW_TOP|rx_data|Mux1~20_combout  & 
// \A_SPW_TOP|rx_data|state_data_write.00~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|Selector541~0_combout  & ( !\A_SPW_TOP|SPW|RX|rx_data_flag [7] & ( \A_SPW_TOP|rx_data|mem[58][7]~q  ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[58][7]~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|rx_data|Selector541~0_combout ),
        .dataf(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector542~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector542~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector542~0 .lut_mask = 64'h555503035555F3F3;
defparam \A_SPW_TOP|rx_data|Selector542~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y3_N17
dffeas \A_SPW_TOP|rx_data|mem[58][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector542~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[58][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[58][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[58][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y4_N21
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector524~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector524~0_combout  = ( \A_SPW_TOP|rx_data|Selector523~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [7]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux1~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector523~0_combout  & ( \A_SPW_TOP|rx_data|mem[56][7]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .datac(!\A_SPW_TOP|rx_data|mem[56][7]~q ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector523~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector524~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector524~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector524~0 .lut_mask = 64'h0F0F0F0F33553355;
defparam \A_SPW_TOP|rx_data|Selector524~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y4_N41
dffeas \A_SPW_TOP|rx_data|mem[56][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector524~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[56][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[56][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[56][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X35_Y3_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux1~8 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux1~8_combout  = ( \A_SPW_TOP|rx_data|mem[56][7]~q  & ( \A_SPW_TOP|rx_data|wr_ptr [1] & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & ((\A_SPW_TOP|rx_data|mem[58][7]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|mem[59][7]~q )) ) 
// ) ) # ( !\A_SPW_TOP|rx_data|mem[56][7]~q  & ( \A_SPW_TOP|rx_data|wr_ptr [1] & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & ((\A_SPW_TOP|rx_data|mem[58][7]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|mem[59][7]~q )) ) ) ) # ( 
// \A_SPW_TOP|rx_data|mem[56][7]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [1] & ( (!\A_SPW_TOP|rx_data|wr_ptr [0]) # (\A_SPW_TOP|rx_data|mem[57][7]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[56][7]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [1] & ( 
// (\A_SPW_TOP|rx_data|mem[57][7]~q  & \A_SPW_TOP|rx_data|wr_ptr [0]) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[57][7]~q ),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datac(!\A_SPW_TOP|rx_data|mem[59][7]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[58][7]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[56][7]~q ),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux1~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux1~8 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux1~8 .lut_mask = 64'h1111DDDD03CF03CF;
defparam \A_SPW_TOP|rx_data|Mux1~8 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X35_Y5_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector236~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector236~0_combout  = ( \A_SPW_TOP|rx_data|Selector235~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [7])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux1~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector235~0_combout  & ( \A_SPW_TOP|rx_data|mem[24][7]~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .datab(!\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|mem[24][7]~q ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector235~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector236~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector236~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector236~0 .lut_mask = 64'h0F0F0F0F55335533;
defparam \A_SPW_TOP|rx_data|Selector236~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X35_Y5_N35
dffeas \A_SPW_TOP|rx_data|mem[24][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector236~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[24][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[24][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[24][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X35_Y5_N27
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector254~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector254~0_combout  = ( \A_SPW_TOP|rx_data|Selector253~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [7])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux1~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector253~0_combout  & ( \A_SPW_TOP|rx_data|mem[26][7]~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .datab(!\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[26][7]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector253~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector254~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector254~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector254~0 .lut_mask = 64'h00FF00FF53535353;
defparam \A_SPW_TOP|rx_data|Selector254~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X35_Y5_N23
dffeas \A_SPW_TOP|rx_data|mem[26][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector254~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[26][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[26][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[26][7] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X32_Y4_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector245~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector245~0_combout  = ( \A_SPW_TOP|rx_data|mem[25][7]~q  & ( (!\A_SPW_TOP|rx_data|Selector244~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [7]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux1~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[25][7]~q  & ( (\A_SPW_TOP|rx_data|Selector244~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [7]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux1~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .datac(!\A_SPW_TOP|rx_data|Selector244~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[25][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector245~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector245~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector245~0 .lut_mask = 64'h03050305F3F5F3F5;
defparam \A_SPW_TOP|rx_data|Selector245~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X32_Y4_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|mem[25][7]~feeder (
// Equation(s):
// \A_SPW_TOP|rx_data|mem[25][7]~feeder_combout  = ( \A_SPW_TOP|rx_data|Selector245~0_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector245~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|mem[25][7]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[25][7]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|mem[25][7]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|rx_data|mem[25][7]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X32_Y4_N44
dffeas \A_SPW_TOP|rx_data|mem[25][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|rx_data|mem[25][7]~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[25][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[25][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[25][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y3_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector263~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector263~0_combout  = ( \A_SPW_TOP|rx_data|mem[27][7]~q  & ( (!\A_SPW_TOP|rx_data|Selector262~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [7])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux1~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[27][7]~q  & ( (\A_SPW_TOP|rx_data|Selector262~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [7])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux1~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .datac(!\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .datad(!\A_SPW_TOP|rx_data|Selector262~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[27][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector263~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector263~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector263~0 .lut_mask = 64'h00270027FF27FF27;
defparam \A_SPW_TOP|rx_data|Selector263~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y3_N26
dffeas \A_SPW_TOP|rx_data|mem[27][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector263~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[27][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[27][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[27][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X35_Y3_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux1~6 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux1~6_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [0] & ( \A_SPW_TOP|rx_data|mem[27][7]~q  & ( (\A_SPW_TOP|rx_data|wr_ptr [1]) # (\A_SPW_TOP|rx_data|mem[25][7]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [0] & ( \A_SPW_TOP|rx_data|mem[27][7]~q 
//  & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|mem[24][7]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [1] & ((\A_SPW_TOP|rx_data|mem[26][7]~q ))) ) ) ) # ( \A_SPW_TOP|rx_data|wr_ptr [0] & ( !\A_SPW_TOP|rx_data|mem[27][7]~q  & ( 
// (\A_SPW_TOP|rx_data|mem[25][7]~q  & !\A_SPW_TOP|rx_data|wr_ptr [1]) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [0] & ( !\A_SPW_TOP|rx_data|mem[27][7]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|mem[24][7]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [1] & 
// ((\A_SPW_TOP|rx_data|mem[26][7]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[24][7]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[26][7]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[25][7]~q ),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .dataf(!\A_SPW_TOP|rx_data|mem[27][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux1~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux1~6 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux1~6 .lut_mask = 64'h55330F0055330FFF;
defparam \A_SPW_TOP|rx_data|Mux1~6 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X33_Y3_N21
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector164~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector164~0_combout  = ( \A_SPW_TOP|rx_data|mem[16][7]~q  & ( (!\A_SPW_TOP|rx_data|Selector163~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [7]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux1~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[16][7]~q  & ( (\A_SPW_TOP|rx_data|Selector163~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [7]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux1~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector163~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[16][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector164~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector164~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector164~0 .lut_mask = 64'h010B010BF1FBF1FB;
defparam \A_SPW_TOP|rx_data|Selector164~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X33_Y3_N17
dffeas \A_SPW_TOP|rx_data|mem[16][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector164~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[16][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[16][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[16][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X33_Y3_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector182~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector182~0_combout  = ( \A_SPW_TOP|rx_data|Selector181~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [7]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux1~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector181~0_combout  & ( \A_SPW_TOP|rx_data|mem[18][7]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .datac(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .datad(!\A_SPW_TOP|rx_data|mem[18][7]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector181~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector182~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector182~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector182~0 .lut_mask = 64'h00FF00FF1B1B1B1B;
defparam \A_SPW_TOP|rx_data|Selector182~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X33_Y3_N29
dffeas \A_SPW_TOP|rx_data|mem[18][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector182~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[18][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[18][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[18][7] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X32_Y4_N33
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector173~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector173~0_combout  = ( \A_SPW_TOP|rx_data|Selector172~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [7]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux1~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector172~0_combout  & ( \A_SPW_TOP|rx_data|mem[17][7]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[17][7]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector172~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector173~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector173~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector173~0 .lut_mask = 64'h00FF00FF35353535;
defparam \A_SPW_TOP|rx_data|Selector173~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X32_Y4_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|mem[17][7]~feeder (
// Equation(s):
// \A_SPW_TOP|rx_data|mem[17][7]~feeder_combout  = ( \A_SPW_TOP|rx_data|Selector173~0_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector173~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|mem[17][7]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[17][7]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|mem[17][7]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|rx_data|mem[17][7]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X32_Y4_N2
dffeas \A_SPW_TOP|rx_data|mem[17][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|rx_data|mem[17][7]~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[17][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[17][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[17][7] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X32_Y3_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector191~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector191~0_combout  = ( \A_SPW_TOP|rx_data|Selector190~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [7])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux1~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector190~0_combout  & ( \A_SPW_TOP|rx_data|mem[19][7]~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[19][7]~q ),
        .datad(!\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector190~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector191~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector191~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector191~0 .lut_mask = 64'h0F0F0F0F44774477;
defparam \A_SPW_TOP|rx_data|Selector191~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X33_Y3_N47
dffeas \A_SPW_TOP|rx_data|mem[19][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector191~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[19][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[19][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[19][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X33_Y3_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux1~5 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux1~5_combout  = ( \A_SPW_TOP|rx_data|mem[19][7]~q  & ( \A_SPW_TOP|rx_data|wr_ptr [1] & ( (\A_SPW_TOP|rx_data|mem[18][7]~q ) # (\A_SPW_TOP|rx_data|wr_ptr [0]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[19][7]~q  & ( \A_SPW_TOP|rx_data|wr_ptr 
// [1] & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & \A_SPW_TOP|rx_data|mem[18][7]~q ) ) ) ) # ( \A_SPW_TOP|rx_data|mem[19][7]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [1] & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|mem[16][7]~q )) # 
// (\A_SPW_TOP|rx_data|wr_ptr [0] & ((\A_SPW_TOP|rx_data|mem[17][7]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[19][7]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [1] & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|mem[16][7]~q )) # (\A_SPW_TOP|rx_data|wr_ptr 
// [0] & ((\A_SPW_TOP|rx_data|mem[17][7]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datab(!\A_SPW_TOP|rx_data|mem[16][7]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[18][7]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[17][7]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[19][7]~q ),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux1~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux1~5 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux1~5 .lut_mask = 64'h227722770A0A5F5F;
defparam \A_SPW_TOP|rx_data|Mux1~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X33_Y3_N39
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector461~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector461~0_combout  = ( \A_SPW_TOP|rx_data|mem[49][7]~q  & ( (!\A_SPW_TOP|rx_data|Selector460~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [7]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux1~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[49][7]~q  & ( (\A_SPW_TOP|rx_data|Selector460~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [7]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux1~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector460~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[49][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector461~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector461~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector461~0 .lut_mask = 64'h010B010BF1FBF1FB;
defparam \A_SPW_TOP|rx_data|Selector461~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X33_Y3_N26
dffeas \A_SPW_TOP|rx_data|mem[49][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector461~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[49][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[49][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[49][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X33_Y3_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector470~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector470~0_combout  = ( \A_SPW_TOP|rx_data|mem[50][7]~q  & ( (!\A_SPW_TOP|rx_data|Selector469~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [7]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux1~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[50][7]~q  & ( (\A_SPW_TOP|rx_data|Selector469~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [7]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux1~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector469~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[50][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector470~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector470~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector470~0 .lut_mask = 64'h010B010BF1FBF1FB;
defparam \A_SPW_TOP|rx_data|Selector470~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X33_Y3_N44
dffeas \A_SPW_TOP|rx_data|mem[50][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector470~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[50][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[50][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[50][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y3_N39
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector452~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector452~0_combout  = ( \A_SPW_TOP|rx_data|Selector451~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [7])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux1~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector451~0_combout  & ( \A_SPW_TOP|rx_data|mem[48][7]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .datac(!\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[48][7]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector451~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector452~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector452~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector452~0 .lut_mask = 64'h00FF00FF27272727;
defparam \A_SPW_TOP|rx_data|Selector452~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y3_N5
dffeas \A_SPW_TOP|rx_data|mem[48][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector452~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[48][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[48][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[48][7] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X32_Y3_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector479~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector479~0_combout  = ( \A_SPW_TOP|rx_data|mem[51][7]~q  & ( (!\A_SPW_TOP|rx_data|Selector478~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [7])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux1~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[51][7]~q  & ( (\A_SPW_TOP|rx_data|Selector478~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [7])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux1~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .datab(!\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector478~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[51][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector479~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector479~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector479~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|rx_data|Selector479~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X33_Y3_N32
dffeas \A_SPW_TOP|rx_data|mem[51][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector479~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[51][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[51][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[51][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X33_Y3_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux1~7 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux1~7_combout  = ( \A_SPW_TOP|rx_data|mem[51][7]~q  & ( \A_SPW_TOP|rx_data|wr_ptr [0] & ( (\A_SPW_TOP|rx_data|wr_ptr [1]) # (\A_SPW_TOP|rx_data|mem[49][7]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[51][7]~q  & ( \A_SPW_TOP|rx_data|wr_ptr 
// [0] & ( (\A_SPW_TOP|rx_data|mem[49][7]~q  & !\A_SPW_TOP|rx_data|wr_ptr [1]) ) ) ) # ( \A_SPW_TOP|rx_data|mem[51][7]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [0] & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & ((\A_SPW_TOP|rx_data|mem[48][7]~q ))) # 
// (\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|mem[50][7]~q )) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[51][7]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [0] & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & ((\A_SPW_TOP|rx_data|mem[48][7]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr 
// [1] & (\A_SPW_TOP|rx_data|mem[50][7]~q )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[49][7]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[50][7]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[48][7]~q ),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datae(!\A_SPW_TOP|rx_data|mem[51][7]~q ),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux1~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux1~7 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux1~7 .lut_mask = 64'h0F330F33550055FF;
defparam \A_SPW_TOP|rx_data|Mux1~7 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X33_Y3_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux1~9 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux1~9_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [5] & ( \A_SPW_TOP|rx_data|Mux1~7_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [3]) # (\A_SPW_TOP|rx_data|Mux1~8_combout ) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [5] & ( 
// \A_SPW_TOP|rx_data|Mux1~7_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [3] & ((\A_SPW_TOP|rx_data|Mux1~5_combout ))) # (\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|Mux1~6_combout )) ) ) ) # ( \A_SPW_TOP|rx_data|wr_ptr [5] & ( 
// !\A_SPW_TOP|rx_data|Mux1~7_combout  & ( (\A_SPW_TOP|rx_data|Mux1~8_combout  & \A_SPW_TOP|rx_data|wr_ptr [3]) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [5] & ( !\A_SPW_TOP|rx_data|Mux1~7_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [3] & 
// ((\A_SPW_TOP|rx_data|Mux1~5_combout ))) # (\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|Mux1~6_combout )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux1~8_combout ),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datac(!\A_SPW_TOP|rx_data|Mux1~6_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux1~5_combout ),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .dataf(!\A_SPW_TOP|rx_data|Mux1~7_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux1~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux1~9 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux1~9 .lut_mask = 64'h03CF111103CFDDDD;
defparam \A_SPW_TOP|rx_data|Mux1~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X36_Y3_N15
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector281~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector281~0_combout  = ( \A_SPW_TOP|rx_data|mem[29][7]~q  & ( (!\A_SPW_TOP|rx_data|Selector280~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [7]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux1~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[29][7]~q  & ( (\A_SPW_TOP|rx_data|Selector280~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [7]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux1~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector280~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[29][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector281~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector281~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector281~0 .lut_mask = 64'h010B010BF1FBF1FB;
defparam \A_SPW_TOP|rx_data|Selector281~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X36_Y3_N8
dffeas \A_SPW_TOP|rx_data|mem[29][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector281~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[29][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[29][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[29][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X36_Y3_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector569~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector569~0_combout  = ( \A_SPW_TOP|rx_data|mem[61][7]~q  & ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector568~0_combout ) # (\A_SPW_TOP|rx_data|Mux1~20_combout ) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|mem[61][7]~q  & ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (\A_SPW_TOP|rx_data|Mux1~20_combout  & \A_SPW_TOP|rx_data|Selector568~0_combout ) ) ) ) # ( \A_SPW_TOP|rx_data|mem[61][7]~q  & ( !\A_SPW_TOP|rx_data|state_data_write.00~q  
// & ( (!\A_SPW_TOP|rx_data|Selector568~0_combout ) # (\A_SPW_TOP|SPW|RX|rx_data_flag [7]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[61][7]~q  & ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( (\A_SPW_TOP|SPW|RX|rx_data_flag [7] & 
// \A_SPW_TOP|rx_data|Selector568~0_combout ) ) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .datab(!\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .datac(gnd),
        .datad(!\A_SPW_TOP|rx_data|Selector568~0_combout ),
        .datae(!\A_SPW_TOP|rx_data|mem[61][7]~q ),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector569~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector569~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector569~0 .lut_mask = 64'h0055FF550033FF33;
defparam \A_SPW_TOP|rx_data|Selector569~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X36_Y3_N29
dffeas \A_SPW_TOP|rx_data|mem[61][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector569~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[61][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[61][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[61][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X36_Y3_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector299~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector299~0_combout  = ( \A_SPW_TOP|rx_data|Selector298~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [7]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux1~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector298~0_combout  & ( \A_SPW_TOP|rx_data|mem[31][7]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .datac(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .datad(!\A_SPW_TOP|rx_data|mem[31][7]~q ),
        .datae(!\A_SPW_TOP|rx_data|Selector298~0_combout ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector299~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector299~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector299~0 .lut_mask = 64'h00FF1B1B00FF1B1B;
defparam \A_SPW_TOP|rx_data|Selector299~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X36_Y3_N59
dffeas \A_SPW_TOP|rx_data|mem[31][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector299~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[31][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[31][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[31][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X36_Y3_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector587~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector587~0_combout  = ( \A_SPW_TOP|rx_data|Selector586~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [7])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux1~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector586~0_combout  & ( \A_SPW_TOP|rx_data|mem[63][7]~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .datab(!\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[63][7]~q ),
        .datae(!\A_SPW_TOP|rx_data|Selector586~0_combout ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector587~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector587~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector587~0 .lut_mask = 64'h00FF535300FF5353;
defparam \A_SPW_TOP|rx_data|Selector587~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X36_Y3_N41
dffeas \A_SPW_TOP|rx_data|mem[63][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector587~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[63][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[63][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[63][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X35_Y3_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux1~18 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux1~18_combout  = ( \A_SPW_TOP|rx_data|mem[31][7]~q  & ( \A_SPW_TOP|rx_data|mem[63][7]~q  & ( ((!\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|mem[29][7]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [5] & ((\A_SPW_TOP|rx_data|mem[61][7]~q 
// )))) # (\A_SPW_TOP|rx_data|wr_ptr [1]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[31][7]~q  & ( \A_SPW_TOP|rx_data|mem[63][7]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|mem[29][7]~q  & ((!\A_SPW_TOP|rx_data|wr_ptr [1])))) # 
// (\A_SPW_TOP|rx_data|wr_ptr [5] & (((\A_SPW_TOP|rx_data|wr_ptr [1]) # (\A_SPW_TOP|rx_data|mem[61][7]~q )))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[31][7]~q  & ( !\A_SPW_TOP|rx_data|mem[63][7]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & (((\A_SPW_TOP|rx_data|wr_ptr 
// [1])) # (\A_SPW_TOP|rx_data|mem[29][7]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [5] & (((\A_SPW_TOP|rx_data|mem[61][7]~q  & !\A_SPW_TOP|rx_data|wr_ptr [1])))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[31][7]~q  & ( !\A_SPW_TOP|rx_data|mem[63][7]~q  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [1] & ((!\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|mem[29][7]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [5] & ((\A_SPW_TOP|rx_data|mem[61][7]~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[29][7]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[61][7]~q ),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datae(!\A_SPW_TOP|rx_data|mem[31][7]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[63][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux1~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux1~18 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux1~18 .lut_mask = 64'h530053F0530F53FF;
defparam \A_SPW_TOP|rx_data|Mux1~18 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X32_Y3_N51
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector209~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector209~0_combout  = ( \A_SPW_TOP|rx_data|Selector208~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [7])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux1~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector208~0_combout  & ( \A_SPW_TOP|rx_data|mem[21][7]~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .datab(!\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|mem[21][7]~q ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector208~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector209~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector209~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector209~0 .lut_mask = 64'h0F0F0F0F55335533;
defparam \A_SPW_TOP|rx_data|Selector209~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y3_N20
dffeas \A_SPW_TOP|rx_data|mem[21][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector209~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[21][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[21][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[21][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y3_N57
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector227~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector227~0_combout  = ( \A_SPW_TOP|rx_data|Selector226~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [7])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux1~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector226~0_combout  & ( \A_SPW_TOP|rx_data|mem[23][7]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .datac(!\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[23][7]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector226~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector227~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector227~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector227~0 .lut_mask = 64'h00FF00FF27272727;
defparam \A_SPW_TOP|rx_data|Selector227~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y3_N2
dffeas \A_SPW_TOP|rx_data|mem[23][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector227~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[23][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[23][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[23][7] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X32_Y3_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector497~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector497~0_combout  = ( \A_SPW_TOP|rx_data|Selector496~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [7])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux1~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector496~0_combout  & ( \A_SPW_TOP|rx_data|mem[53][7]~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .datab(!\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|mem[53][7]~q ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector496~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector497~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector497~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector497~0 .lut_mask = 64'h0F0F0F0F55335533;
defparam \A_SPW_TOP|rx_data|Selector497~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y3_N8
dffeas \A_SPW_TOP|rx_data|mem[53][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector497~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[53][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[53][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[53][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y3_N27
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux1~17 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux1~17_combout  = ( \A_SPW_TOP|rx_data|mem[23][7]~q  & ( \A_SPW_TOP|rx_data|mem[53][7]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & (((\A_SPW_TOP|rx_data|mem[21][7]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [1]))) # (\A_SPW_TOP|rx_data|wr_ptr [5] 
// & ((!\A_SPW_TOP|rx_data|wr_ptr [1]) # ((\A_SPW_TOP|rx_data|mem[55][7]~q )))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[23][7]~q  & ( \A_SPW_TOP|rx_data|mem[53][7]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & (!\A_SPW_TOP|rx_data|wr_ptr [1] & 
// ((\A_SPW_TOP|rx_data|mem[21][7]~q )))) # (\A_SPW_TOP|rx_data|wr_ptr [5] & ((!\A_SPW_TOP|rx_data|wr_ptr [1]) # ((\A_SPW_TOP|rx_data|mem[55][7]~q )))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[23][7]~q  & ( !\A_SPW_TOP|rx_data|mem[53][7]~q  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [5] & (((\A_SPW_TOP|rx_data|mem[21][7]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [1]))) # (\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|mem[55][7]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[23][7]~q 
//  & ( !\A_SPW_TOP|rx_data|mem[53][7]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & (!\A_SPW_TOP|rx_data|wr_ptr [1] & ((\A_SPW_TOP|rx_data|mem[21][7]~q )))) # (\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|mem[55][7]~q ))) 
// ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datac(!\A_SPW_TOP|rx_data|mem[55][7]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[21][7]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[23][7]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[53][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux1~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux1~17 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux1~17 .lut_mask = 64'h018923AB45CD67EF;
defparam \A_SPW_TOP|rx_data|Mux1~17 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X33_Y3_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector488~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector488~0_combout  = ( \A_SPW_TOP|rx_data|Selector487~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [7]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux1~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector487~0_combout  & ( \A_SPW_TOP|rx_data|mem[52][7]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|mem[52][7]~q ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector487~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector488~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector488~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector488~0 .lut_mask = 64'h0F0F0F0F11BB11BB;
defparam \A_SPW_TOP|rx_data|Selector488~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X33_Y3_N50
dffeas \A_SPW_TOP|rx_data|mem[52][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector488~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[52][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[52][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[52][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X33_Y3_N57
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector506~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector506~0_combout  = ( \A_SPW_TOP|rx_data|mem[54][7]~q  & ( (!\A_SPW_TOP|rx_data|Selector505~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [7]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux1~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[54][7]~q  & ( (\A_SPW_TOP|rx_data|Selector505~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [7]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux1~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector505~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[54][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector506~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector506~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector506~0 .lut_mask = 64'h010B010BF1FBF1FB;
defparam \A_SPW_TOP|rx_data|Selector506~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X33_Y3_N11
dffeas \A_SPW_TOP|rx_data|mem[54][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector506~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[54][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[54][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[54][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X33_Y3_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector200~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector200~0_combout  = ( \A_SPW_TOP|rx_data|Selector199~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [7]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux1~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector199~0_combout  & ( \A_SPW_TOP|rx_data|mem[20][7]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|mem[20][7]~q ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector199~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector200~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector200~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector200~0 .lut_mask = 64'h0F0F0F0F11BB11BB;
defparam \A_SPW_TOP|rx_data|Selector200~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X33_Y3_N53
dffeas \A_SPW_TOP|rx_data|mem[20][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector200~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[20][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[20][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[20][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X33_Y3_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector218~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector218~0_combout  = ( \A_SPW_TOP|SPW|RX|rx_data_flag [7] & ( (!\A_SPW_TOP|rx_data|Selector217~0_combout  & (((\A_SPW_TOP|rx_data|mem[22][7]~q )))) # (\A_SPW_TOP|rx_data|Selector217~0_combout  & 
// ((!\A_SPW_TOP|rx_data|state_data_write.00~q ) # ((\A_SPW_TOP|rx_data|Mux1~20_combout )))) ) ) # ( !\A_SPW_TOP|SPW|RX|rx_data_flag [7] & ( (!\A_SPW_TOP|rx_data|Selector217~0_combout  & (((\A_SPW_TOP|rx_data|mem[22][7]~q )))) # 
// (\A_SPW_TOP|rx_data|Selector217~0_combout  & (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux1~20_combout ))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|mem[22][7]~q ),
        .datad(!\A_SPW_TOP|rx_data|Selector217~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector218~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector218~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector218~0 .lut_mask = 64'h0F110F110FBB0FBB;
defparam \A_SPW_TOP|rx_data|Selector218~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X33_Y3_N35
dffeas \A_SPW_TOP|rx_data|mem[22][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector218~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[22][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[22][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[22][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X33_Y3_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux1~15 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux1~15_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [5] & ( \A_SPW_TOP|rx_data|mem[22][7]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|mem[52][7]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [1] & ((\A_SPW_TOP|rx_data|mem[54][7]~q ))) ) 
// ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [5] & ( \A_SPW_TOP|rx_data|mem[22][7]~q  & ( (\A_SPW_TOP|rx_data|wr_ptr [1]) # (\A_SPW_TOP|rx_data|mem[20][7]~q ) ) ) ) # ( \A_SPW_TOP|rx_data|wr_ptr [5] & ( !\A_SPW_TOP|rx_data|mem[22][7]~q  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|mem[52][7]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [1] & ((\A_SPW_TOP|rx_data|mem[54][7]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [5] & ( !\A_SPW_TOP|rx_data|mem[22][7]~q  & ( 
// (\A_SPW_TOP|rx_data|mem[20][7]~q  & !\A_SPW_TOP|rx_data|wr_ptr [1]) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[52][7]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[54][7]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[20][7]~q ),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .dataf(!\A_SPW_TOP|rx_data|mem[22][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux1~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux1~15 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux1~15 .lut_mask = 64'h0F0055330FFF5533;
defparam \A_SPW_TOP|rx_data|Mux1~15 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X35_Y3_N51
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector578~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector578~0_combout  = ( \A_SPW_TOP|rx_data|Selector577~0_combout  & ( \A_SPW_TOP|SPW|RX|rx_data_flag [7] & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|rx_data|Mux1~20_combout ) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|Selector577~0_combout  & ( \A_SPW_TOP|SPW|RX|rx_data_flag [7] & ( \A_SPW_TOP|rx_data|mem[62][7]~q  ) ) ) # ( \A_SPW_TOP|rx_data|Selector577~0_combout  & ( !\A_SPW_TOP|SPW|RX|rx_data_flag [7] & ( (\A_SPW_TOP|rx_data|Mux1~20_combout  & 
// \A_SPW_TOP|rx_data|state_data_write.00~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|Selector577~0_combout  & ( !\A_SPW_TOP|SPW|RX|rx_data_flag [7] & ( \A_SPW_TOP|rx_data|mem[62][7]~q  ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[62][7]~q ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(!\A_SPW_TOP|rx_data|Selector577~0_combout ),
        .dataf(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector578~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector578~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector578~0 .lut_mask = 64'h5555000F5555FF0F;
defparam \A_SPW_TOP|rx_data|Selector578~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X33_Y3_N14
dffeas \A_SPW_TOP|rx_data|mem[62][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector578~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[62][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[62][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[62][7] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X32_Y3_N9
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector272~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector272~0_combout  = ( \A_SPW_TOP|rx_data|mem[28][7]~q  & ( (!\A_SPW_TOP|rx_data|Selector271~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [7])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux1~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[28][7]~q  & ( (\A_SPW_TOP|rx_data|Selector271~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [7])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux1~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Selector271~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[28][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector272~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector272~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector272~0 .lut_mask = 64'h04070407F4F7F4F7;
defparam \A_SPW_TOP|rx_data|Selector272~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y3_N47
dffeas \A_SPW_TOP|rx_data|mem[28][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector272~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[28][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[28][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[28][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X36_Y3_N27
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector290~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector290~0_combout  = ( \A_SPW_TOP|SPW|RX|rx_data_flag [7] & ( \A_SPW_TOP|rx_data|mem[30][7]~q  & ( ((!\A_SPW_TOP|rx_data|Selector289~0_combout ) # (!\A_SPW_TOP|rx_data|state_data_write.00~q )) # (\A_SPW_TOP|rx_data|Mux1~20_combout ) 
// ) ) ) # ( !\A_SPW_TOP|SPW|RX|rx_data_flag [7] & ( \A_SPW_TOP|rx_data|mem[30][7]~q  & ( (!\A_SPW_TOP|rx_data|Selector289~0_combout ) # ((\A_SPW_TOP|rx_data|Mux1~20_combout  & \A_SPW_TOP|rx_data|state_data_write.00~q )) ) ) ) # ( 
// \A_SPW_TOP|SPW|RX|rx_data_flag [7] & ( !\A_SPW_TOP|rx_data|mem[30][7]~q  & ( (\A_SPW_TOP|rx_data|Selector289~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|rx_data|Mux1~20_combout ))) ) ) ) # ( !\A_SPW_TOP|SPW|RX|rx_data_flag [7] 
// & ( !\A_SPW_TOP|rx_data|mem[30][7]~q  & ( (\A_SPW_TOP|rx_data|Mux1~20_combout  & (\A_SPW_TOP|rx_data|Selector289~0_combout  & \A_SPW_TOP|rx_data|state_data_write.00~q )) ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector289~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .dataf(!\A_SPW_TOP|rx_data|mem[30][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector290~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector290~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector290~0 .lut_mask = 64'h00030F03F0F3FFF3;
defparam \A_SPW_TOP|rx_data|Selector290~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X36_Y3_N11
dffeas \A_SPW_TOP|rx_data|mem[30][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector290~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[30][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[30][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[30][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X36_Y3_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector560~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector560~0_combout  = ( \A_SPW_TOP|rx_data|mem[60][7]~q  & ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector559~0_combout ) # (\A_SPW_TOP|rx_data|Mux1~20_combout ) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|mem[60][7]~q  & ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (\A_SPW_TOP|rx_data|Mux1~20_combout  & \A_SPW_TOP|rx_data|Selector559~0_combout ) ) ) ) # ( \A_SPW_TOP|rx_data|mem[60][7]~q  & ( !\A_SPW_TOP|rx_data|state_data_write.00~q  
// & ( (!\A_SPW_TOP|rx_data|Selector559~0_combout ) # (\A_SPW_TOP|SPW|RX|rx_data_flag [7]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[60][7]~q  & ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( (\A_SPW_TOP|SPW|RX|rx_data_flag [7] & 
// \A_SPW_TOP|rx_data|Selector559~0_combout ) ) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .datab(!\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .datac(gnd),
        .datad(!\A_SPW_TOP|rx_data|Selector559~0_combout ),
        .datae(!\A_SPW_TOP|rx_data|mem[60][7]~q ),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector560~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector560~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector560~0 .lut_mask = 64'h0055FF550033FF33;
defparam \A_SPW_TOP|rx_data|Selector560~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X36_Y3_N47
dffeas \A_SPW_TOP|rx_data|mem[60][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector560~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[60][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[60][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[60][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X35_Y3_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux1~16 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux1~16_combout  = ( \A_SPW_TOP|rx_data|mem[30][7]~q  & ( \A_SPW_TOP|rx_data|mem[60][7]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & (((\A_SPW_TOP|rx_data|mem[28][7]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [1]))) # (\A_SPW_TOP|rx_data|wr_ptr [5] 
// & ((!\A_SPW_TOP|rx_data|wr_ptr [1]) # ((\A_SPW_TOP|rx_data|mem[62][7]~q )))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[30][7]~q  & ( \A_SPW_TOP|rx_data|mem[60][7]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & (!\A_SPW_TOP|rx_data|wr_ptr [1] & 
// ((\A_SPW_TOP|rx_data|mem[28][7]~q )))) # (\A_SPW_TOP|rx_data|wr_ptr [5] & ((!\A_SPW_TOP|rx_data|wr_ptr [1]) # ((\A_SPW_TOP|rx_data|mem[62][7]~q )))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[30][7]~q  & ( !\A_SPW_TOP|rx_data|mem[60][7]~q  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [5] & (((\A_SPW_TOP|rx_data|mem[28][7]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [1]))) # (\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|mem[62][7]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[30][7]~q 
//  & ( !\A_SPW_TOP|rx_data|mem[60][7]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & (!\A_SPW_TOP|rx_data|wr_ptr [1] & ((\A_SPW_TOP|rx_data|mem[28][7]~q )))) # (\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|mem[62][7]~q ))) 
// ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datac(!\A_SPW_TOP|rx_data|mem[62][7]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[28][7]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[30][7]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[60][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux1~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux1~16 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux1~16 .lut_mask = 64'h018923AB45CD67EF;
defparam \A_SPW_TOP|rx_data|Mux1~16 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y3_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux1~19 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux1~19_combout  = ( \A_SPW_TOP|rx_data|Mux1~15_combout  & ( \A_SPW_TOP|rx_data|Mux1~16_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [0]) # ((!\A_SPW_TOP|rx_data|wr_ptr [3] & ((\A_SPW_TOP|rx_data|Mux1~17_combout ))) # 
// (\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|Mux1~18_combout ))) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux1~15_combout  & ( \A_SPW_TOP|rx_data|Mux1~16_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|wr_ptr [0] & 
// ((\A_SPW_TOP|rx_data|Mux1~17_combout )))) # (\A_SPW_TOP|rx_data|wr_ptr [3] & ((!\A_SPW_TOP|rx_data|wr_ptr [0]) # ((\A_SPW_TOP|rx_data|Mux1~18_combout )))) ) ) ) # ( \A_SPW_TOP|rx_data|Mux1~15_combout  & ( !\A_SPW_TOP|rx_data|Mux1~16_combout  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [3] & ((!\A_SPW_TOP|rx_data|wr_ptr [0]) # ((\A_SPW_TOP|rx_data|Mux1~17_combout )))) # (\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|Mux1~18_combout ))) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|Mux1~15_combout  & ( !\A_SPW_TOP|rx_data|Mux1~16_combout  & ( (\A_SPW_TOP|rx_data|wr_ptr [0] & ((!\A_SPW_TOP|rx_data|wr_ptr [3] & ((\A_SPW_TOP|rx_data|Mux1~17_combout ))) # (\A_SPW_TOP|rx_data|wr_ptr [3] & 
// (\A_SPW_TOP|rx_data|Mux1~18_combout )))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datac(!\A_SPW_TOP|rx_data|Mux1~18_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux1~17_combout ),
        .datae(!\A_SPW_TOP|rx_data|Mux1~15_combout ),
        .dataf(!\A_SPW_TOP|rx_data|Mux1~16_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux1~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux1~19 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux1~19 .lut_mask = 64'h012389AB4567CDEF;
defparam \A_SPW_TOP|rx_data|Mux1~19 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y4_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector398~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector398~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector397~0_combout  & ((\A_SPW_TOP|rx_data|mem[42][7]~q ))) # (\A_SPW_TOP|rx_data|Selector397~0_combout  & 
// (\A_SPW_TOP|rx_data|Mux1~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector397~0_combout  & ((\A_SPW_TOP|rx_data|mem[42][7]~q ))) # (\A_SPW_TOP|rx_data|Selector397~0_combout  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [7])) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .datac(!\A_SPW_TOP|rx_data|mem[42][7]~q ),
        .datad(!\A_SPW_TOP|rx_data|Selector397~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector398~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector398~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector398~0 .lut_mask = 64'h0F330F330F550F55;
defparam \A_SPW_TOP|rx_data|Selector398~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y4_N29
dffeas \A_SPW_TOP|rx_data|mem[42][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector398~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[42][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[42][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[42][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y4_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector380~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector380~0_combout  = ( \A_SPW_TOP|rx_data|Selector379~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [7]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux1~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector379~0_combout  & ( \A_SPW_TOP|rx_data|mem[40][7]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .datac(!\A_SPW_TOP|rx_data|mem[40][7]~q ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector379~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector380~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector380~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector380~0 .lut_mask = 64'h0F0F0F0F33553355;
defparam \A_SPW_TOP|rx_data|Selector380~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y4_N11
dffeas \A_SPW_TOP|rx_data|mem[40][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector380~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[40][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[40][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[40][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y4_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector407~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector407~0_combout  = ( \A_SPW_TOP|rx_data|mem[43][7]~q  & ( (!\A_SPW_TOP|rx_data|Selector406~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [7]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux1~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[43][7]~q  & ( (\A_SPW_TOP|rx_data|Selector406~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [7]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux1~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .datac(!\A_SPW_TOP|rx_data|Selector406~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[43][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector407~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector407~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector407~0 .lut_mask = 64'h03050305F3F5F3F5;
defparam \A_SPW_TOP|rx_data|Selector407~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y4_N14
dffeas \A_SPW_TOP|rx_data|mem[43][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector407~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[43][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[43][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[43][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y4_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector389~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector389~0_combout  = ( \A_SPW_TOP|rx_data|mem[41][7]~q  & ( (!\A_SPW_TOP|rx_data|Selector388~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [7]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux1~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[41][7]~q  & ( (\A_SPW_TOP|rx_data|Selector388~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [7]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux1~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .datac(!\A_SPW_TOP|rx_data|Selector388~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[41][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector389~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector389~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector389~0 .lut_mask = 64'h03050305F3F5F3F5;
defparam \A_SPW_TOP|rx_data|Selector389~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y4_N20
dffeas \A_SPW_TOP|rx_data|mem[41][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector389~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[41][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[41][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[41][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y4_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux1~3 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux1~3_combout  = ( \A_SPW_TOP|rx_data|mem[41][7]~q  & ( \A_SPW_TOP|rx_data|wr_ptr [1] & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|mem[42][7]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [0] & ((\A_SPW_TOP|rx_data|mem[43][7]~q ))) ) 
// ) ) # ( !\A_SPW_TOP|rx_data|mem[41][7]~q  & ( \A_SPW_TOP|rx_data|wr_ptr [1] & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|mem[42][7]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [0] & ((\A_SPW_TOP|rx_data|mem[43][7]~q ))) ) ) ) # ( 
// \A_SPW_TOP|rx_data|mem[41][7]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [1] & ( (\A_SPW_TOP|rx_data|wr_ptr [0]) # (\A_SPW_TOP|rx_data|mem[40][7]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[41][7]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [1] & ( 
// (\A_SPW_TOP|rx_data|mem[40][7]~q  & !\A_SPW_TOP|rx_data|wr_ptr [0]) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[42][7]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[40][7]~q ),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datad(!\A_SPW_TOP|rx_data|mem[43][7]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[41][7]~q ),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux1~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux1~3 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux1~3 .lut_mask = 64'h30303F3F505F505F;
defparam \A_SPW_TOP|rx_data|Mux1~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X31_Y4_N51
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector110~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector110~0_combout  = ( \A_SPW_TOP|rx_data|mem[10][7]~q  & ( (!\A_SPW_TOP|rx_data|Selector109~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [7]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux1~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[10][7]~q  & ( (\A_SPW_TOP|rx_data|Selector109~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [7]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux1~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .datac(!\A_SPW_TOP|rx_data|Selector109~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[10][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector110~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector110~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector110~0 .lut_mask = 64'h03050305F3F5F3F5;
defparam \A_SPW_TOP|rx_data|Selector110~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y4_N41
dffeas \A_SPW_TOP|rx_data|mem[10][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector110~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[10][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[10][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[10][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y4_N57
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector92~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector92~0_combout  = ( \A_SPW_TOP|rx_data|mem[8][7]~q  & ( (!\A_SPW_TOP|rx_data|Selector91~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [7]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux1~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[8][7]~q  & ( (\A_SPW_TOP|rx_data|Selector91~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [7]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux1~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .datac(!\A_SPW_TOP|rx_data|Selector91~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[8][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector92~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector92~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector92~0 .lut_mask = 64'h03050305F3F5F3F5;
defparam \A_SPW_TOP|rx_data|Selector92~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y4_N35
dffeas \A_SPW_TOP|rx_data|mem[8][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector92~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[8][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[8][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[8][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y4_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector119~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector119~0_combout  = ( \A_SPW_TOP|rx_data|mem[11][7]~q  & ( (!\A_SPW_TOP|rx_data|Selector118~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [7]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux1~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[11][7]~q  & ( (\A_SPW_TOP|rx_data|Selector118~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [7]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux1~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|Selector118~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[11][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector119~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector119~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector119~0 .lut_mask = 64'h00350035FF35FF35;
defparam \A_SPW_TOP|rx_data|Selector119~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y4_N44
dffeas \A_SPW_TOP|rx_data|mem[11][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector119~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[11][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[11][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[11][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y4_N9
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector101~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector101~0_combout  = ( \A_SPW_TOP|rx_data|mem[9][7]~q  & ( (!\A_SPW_TOP|rx_data|Selector100~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [7]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux1~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[9][7]~q  & ( (\A_SPW_TOP|rx_data|Selector100~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [7]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux1~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .datac(!\A_SPW_TOP|rx_data|Selector100~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[9][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector101~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector101~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector101~0 .lut_mask = 64'h03050305F3F5F3F5;
defparam \A_SPW_TOP|rx_data|Selector101~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y4_N17
dffeas \A_SPW_TOP|rx_data|mem[9][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector101~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[9][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[9][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[9][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y4_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux1~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux1~1_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [1] & ( \A_SPW_TOP|rx_data|mem[9][7]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|mem[10][7]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [0] & ((\A_SPW_TOP|rx_data|mem[11][7]~q ))) ) ) 
// ) # ( !\A_SPW_TOP|rx_data|wr_ptr [1] & ( \A_SPW_TOP|rx_data|mem[9][7]~q  & ( (\A_SPW_TOP|rx_data|mem[8][7]~q ) # (\A_SPW_TOP|rx_data|wr_ptr [0]) ) ) ) # ( \A_SPW_TOP|rx_data|wr_ptr [1] & ( !\A_SPW_TOP|rx_data|mem[9][7]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr 
// [0] & (\A_SPW_TOP|rx_data|mem[10][7]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [0] & ((\A_SPW_TOP|rx_data|mem[11][7]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [1] & ( !\A_SPW_TOP|rx_data|mem[9][7]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & 
// \A_SPW_TOP|rx_data|mem[8][7]~q ) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datab(!\A_SPW_TOP|rx_data|mem[10][7]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[8][7]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[11][7]~q ),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .dataf(!\A_SPW_TOP|rx_data|mem[9][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux1~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux1~1 .lut_mask = 64'h0A0A22775F5F2277;
defparam \A_SPW_TOP|rx_data|Mux1~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X31_Y3_N51
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector47~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector47~0_combout  = ( \A_SPW_TOP|rx_data|Selector46~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [7])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux1~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector46~0_combout  & ( \A_SPW_TOP|rx_data|mem[3][7]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .datac(!\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[3][7]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector46~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector47~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector47~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector47~0 .lut_mask = 64'h00FF00FF27272727;
defparam \A_SPW_TOP|rx_data|Selector47~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y3_N29
dffeas \A_SPW_TOP|rx_data|mem[3][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector47~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[3][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[3][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[3][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X36_Y3_N33
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector38~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector38~0_combout  = ( \A_SPW_TOP|rx_data|mem[2][7]~q  & ( (!\A_SPW_TOP|rx_data|Selector37~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [7]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux1~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[2][7]~q  & ( (\A_SPW_TOP|rx_data|Selector37~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [7]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux1~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .datac(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .datad(!\A_SPW_TOP|rx_data|Selector37~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[2][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector38~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector38~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector38~0 .lut_mask = 64'h001B001BFF1BFF1B;
defparam \A_SPW_TOP|rx_data|Selector38~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X36_Y3_N26
dffeas \A_SPW_TOP|rx_data|mem[2][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector38~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[2][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[2][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[2][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y3_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector20~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector20~0_combout  = ( \A_SPW_TOP|rx_data|Selector19~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [7]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux1~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector19~0_combout  & ( \A_SPW_TOP|rx_data|mem[0][7]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|mem[0][7]~q ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .datae(!\A_SPW_TOP|rx_data|Selector19~0_combout ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector20~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector20~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector20~0 .lut_mask = 64'h0F0F11BB0F0F11BB;
defparam \A_SPW_TOP|rx_data|Selector20~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y3_N23
dffeas \A_SPW_TOP|rx_data|mem[0][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector20~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[0][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[0][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[0][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y3_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector29~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector29~0_combout  = ( \A_SPW_TOP|rx_data|Selector28~0_combout  & ( \A_SPW_TOP|rx_data|mem[1][7]~q  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [7]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q 
//  & (\A_SPW_TOP|rx_data|Mux1~20_combout )) ) ) ) # ( !\A_SPW_TOP|rx_data|Selector28~0_combout  & ( \A_SPW_TOP|rx_data|mem[1][7]~q  ) ) # ( \A_SPW_TOP|rx_data|Selector28~0_combout  & ( !\A_SPW_TOP|rx_data|mem[1][7]~q  & ( 
// (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [7]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux1~20_combout )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|rx_data|Selector28~0_combout ),
        .dataf(!\A_SPW_TOP|rx_data|mem[1][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector29~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector29~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector29~0 .lut_mask = 64'h00003535FFFF3535;
defparam \A_SPW_TOP|rx_data|Selector29~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y3_N35
dffeas \A_SPW_TOP|rx_data|mem[1][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector29~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[1][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[1][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[1][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y3_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux1~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux1~0_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [0] & ( \A_SPW_TOP|rx_data|mem[1][7]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [1]) # (\A_SPW_TOP|rx_data|mem[3][7]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [0] & ( \A_SPW_TOP|rx_data|mem[1][7]~q  
// & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & ((\A_SPW_TOP|rx_data|mem[0][7]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|mem[2][7]~q )) ) ) ) # ( \A_SPW_TOP|rx_data|wr_ptr [0] & ( !\A_SPW_TOP|rx_data|mem[1][7]~q  & ( 
// (\A_SPW_TOP|rx_data|mem[3][7]~q  & \A_SPW_TOP|rx_data|wr_ptr [1]) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [0] & ( !\A_SPW_TOP|rx_data|mem[1][7]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & ((\A_SPW_TOP|rx_data|mem[0][7]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [1] & 
// (\A_SPW_TOP|rx_data|mem[2][7]~q )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[3][7]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[2][7]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[0][7]~q ),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .dataf(!\A_SPW_TOP|rx_data|mem[1][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux1~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux1~0 .lut_mask = 64'h0F3300550F33FF55;
defparam \A_SPW_TOP|rx_data|Mux1~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y3_N57
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector335~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector335~0_combout  = ( \A_SPW_TOP|rx_data|mem[35][7]~q  & ( (!\A_SPW_TOP|rx_data|Selector334~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [7]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux1~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[35][7]~q  & ( (\A_SPW_TOP|rx_data|Selector334~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [7]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux1~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector334~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[35][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector335~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector335~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector335~0 .lut_mask = 64'h010B010BF1FBF1FB;
defparam \A_SPW_TOP|rx_data|Selector335~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y3_N14
dffeas \A_SPW_TOP|rx_data|mem[35][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector335~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[35][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[35][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[35][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y3_N21
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector308~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector308~0_combout  = ( \A_SPW_TOP|rx_data|Selector307~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [7])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux1~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector307~0_combout  & ( \A_SPW_TOP|rx_data|mem[32][7]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .datac(!\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[32][7]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector307~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector308~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector308~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector308~0 .lut_mask = 64'h00FF00FF27272727;
defparam \A_SPW_TOP|rx_data|Selector308~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y3_N47
dffeas \A_SPW_TOP|rx_data|mem[32][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector308~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[32][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[32][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[32][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y3_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector326~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector326~0_combout  = ( \A_SPW_TOP|rx_data|Mux1~20_combout  & ( (!\A_SPW_TOP|rx_data|Selector325~0_combout  & (((\A_SPW_TOP|rx_data|mem[34][7]~q )))) # (\A_SPW_TOP|rx_data|Selector325~0_combout  & (((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [7])) # (\A_SPW_TOP|rx_data|state_data_write.00~q ))) ) ) # ( !\A_SPW_TOP|rx_data|Mux1~20_combout  & ( (!\A_SPW_TOP|rx_data|Selector325~0_combout  & (((\A_SPW_TOP|rx_data|mem[34][7]~q )))) # (\A_SPW_TOP|rx_data|Selector325~0_combout  & 
// (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [7]))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .datac(!\A_SPW_TOP|rx_data|mem[34][7]~q ),
        .datad(!\A_SPW_TOP|rx_data|Selector325~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector326~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector326~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector326~0 .lut_mask = 64'h0F220F220F770F77;
defparam \A_SPW_TOP|rx_data|Selector326~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y3_N53
dffeas \A_SPW_TOP|rx_data|mem[34][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector326~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[34][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[34][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[34][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y3_N33
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector317~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector317~0_combout  = ( \A_SPW_TOP|rx_data|Selector316~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [7]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux1~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector316~0_combout  & ( \A_SPW_TOP|rx_data|mem[33][7]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|mem[33][7]~q ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector316~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector317~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector317~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector317~0 .lut_mask = 64'h0F0F0F0F11BB11BB;
defparam \A_SPW_TOP|rx_data|Selector317~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y3_N41
dffeas \A_SPW_TOP|rx_data|mem[33][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector317~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[33][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[33][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[33][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y3_N39
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux1~2 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux1~2_combout  = ( \A_SPW_TOP|rx_data|mem[33][7]~q  & ( \A_SPW_TOP|rx_data|wr_ptr [0] & ( (!\A_SPW_TOP|rx_data|wr_ptr [1]) # (\A_SPW_TOP|rx_data|mem[35][7]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[33][7]~q  & ( \A_SPW_TOP|rx_data|wr_ptr 
// [0] & ( (\A_SPW_TOP|rx_data|wr_ptr [1] & \A_SPW_TOP|rx_data|mem[35][7]~q ) ) ) ) # ( \A_SPW_TOP|rx_data|mem[33][7]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [0] & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|mem[32][7]~q )) # (\A_SPW_TOP|rx_data|wr_ptr 
// [1] & ((\A_SPW_TOP|rx_data|mem[34][7]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[33][7]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [0] & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|mem[32][7]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [1] & 
// ((\A_SPW_TOP|rx_data|mem[34][7]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datab(!\A_SPW_TOP|rx_data|mem[35][7]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[32][7]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[34][7]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[33][7]~q ),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux1~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux1~2 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux1~2 .lut_mask = 64'h0A5F0A5F1111BBBB;
defparam \A_SPW_TOP|rx_data|Mux1~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y3_N51
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux1~4 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux1~4_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [5] & ( \A_SPW_TOP|rx_data|wr_ptr [3] & ( \A_SPW_TOP|rx_data|Mux1~3_combout  ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [5] & ( \A_SPW_TOP|rx_data|wr_ptr [3] & ( \A_SPW_TOP|rx_data|Mux1~1_combout  
// ) ) ) # ( \A_SPW_TOP|rx_data|wr_ptr [5] & ( !\A_SPW_TOP|rx_data|wr_ptr [3] & ( \A_SPW_TOP|rx_data|Mux1~2_combout  ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [5] & ( !\A_SPW_TOP|rx_data|wr_ptr [3] & ( \A_SPW_TOP|rx_data|Mux1~0_combout  ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux1~3_combout ),
        .datab(!\A_SPW_TOP|rx_data|Mux1~1_combout ),
        .datac(!\A_SPW_TOP|rx_data|Mux1~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux1~2_combout ),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux1~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux1~4 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux1~4 .lut_mask = 64'h0F0F00FF33335555;
defparam \A_SPW_TOP|rx_data|Mux1~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y3_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux1~20 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux1~20_combout  = ( \A_SPW_TOP|rx_data|Mux1~19_combout  & ( \A_SPW_TOP|rx_data|Mux1~4_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & (((!\A_SPW_TOP|rx_data|wr_ptr [4]) # (\A_SPW_TOP|rx_data|Mux1~9_combout )))) # 
// (\A_SPW_TOP|rx_data|wr_ptr [2] & (((\A_SPW_TOP|rx_data|wr_ptr [4])) # (\A_SPW_TOP|rx_data|Mux1~14_combout ))) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux1~19_combout  & ( \A_SPW_TOP|rx_data|Mux1~4_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & 
// (((!\A_SPW_TOP|rx_data|wr_ptr [4]) # (\A_SPW_TOP|rx_data|Mux1~9_combout )))) # (\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|Mux1~14_combout  & ((!\A_SPW_TOP|rx_data|wr_ptr [4])))) ) ) ) # ( \A_SPW_TOP|rx_data|Mux1~19_combout  & ( 
// !\A_SPW_TOP|rx_data|Mux1~4_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & (((\A_SPW_TOP|rx_data|Mux1~9_combout  & \A_SPW_TOP|rx_data|wr_ptr [4])))) # (\A_SPW_TOP|rx_data|wr_ptr [2] & (((\A_SPW_TOP|rx_data|wr_ptr [4])) # (\A_SPW_TOP|rx_data|Mux1~14_combout 
// ))) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux1~19_combout  & ( !\A_SPW_TOP|rx_data|Mux1~4_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & (((\A_SPW_TOP|rx_data|Mux1~9_combout  & \A_SPW_TOP|rx_data|wr_ptr [4])))) # (\A_SPW_TOP|rx_data|wr_ptr [2] & 
// (\A_SPW_TOP|rx_data|Mux1~14_combout  & ((!\A_SPW_TOP|rx_data|wr_ptr [4])))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux1~14_combout ),
        .datab(!\A_SPW_TOP|rx_data|Mux1~9_combout ),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datae(!\A_SPW_TOP|rx_data|Mux1~19_combout ),
        .dataf(!\A_SPW_TOP|rx_data|Mux1~4_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux1~20 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux1~20 .lut_mask = 64'h0530053FF530F53F;
defparam \A_SPW_TOP|rx_data|Mux1~20 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X32_Y3_N33
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector515~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector515~0_combout  = ( \A_SPW_TOP|rx_data|mem[55][7]~q  & ( (!\A_SPW_TOP|rx_data|Selector514~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [7])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux1~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[55][7]~q  & ( (\A_SPW_TOP|rx_data|Selector514~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [7])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux1~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
        .datab(!\A_SPW_TOP|rx_data|Mux1~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector514~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[55][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector515~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector515~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector515~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|rx_data|Selector515~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y3_N17
dffeas \A_SPW_TOP|rx_data|mem[55][7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector515~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[55][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[55][7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[55][7] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X32_Y3_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux10~16 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux10~16_combout  = ( \A_SPW_TOP|rx_data|mem[53][7]~q  & ( \A_SPW_TOP|rx_data|mem[49][7]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [1]) # ((!\A_SPW_TOP|rx_data|rd_ptr [2] & ((\A_SPW_TOP|rx_data|mem[51][7]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [2] 
// & (\A_SPW_TOP|rx_data|mem[55][7]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[53][7]~q  & ( \A_SPW_TOP|rx_data|mem[49][7]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [2] & (((!\A_SPW_TOP|rx_data|rd_ptr [1]) # (\A_SPW_TOP|rx_data|mem[51][7]~q )))) # 
// (\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|mem[55][7]~q  & ((\A_SPW_TOP|rx_data|rd_ptr [1])))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[53][7]~q  & ( !\A_SPW_TOP|rx_data|mem[49][7]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [2] & 
// (((\A_SPW_TOP|rx_data|mem[51][7]~q  & \A_SPW_TOP|rx_data|rd_ptr [1])))) # (\A_SPW_TOP|rx_data|rd_ptr [2] & (((!\A_SPW_TOP|rx_data|rd_ptr [1])) # (\A_SPW_TOP|rx_data|mem[55][7]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[53][7]~q  & ( 
// !\A_SPW_TOP|rx_data|mem[49][7]~q  & ( (\A_SPW_TOP|rx_data|rd_ptr [1] & ((!\A_SPW_TOP|rx_data|rd_ptr [2] & ((\A_SPW_TOP|rx_data|mem[51][7]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|mem[55][7]~q )))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datab(!\A_SPW_TOP|rx_data|mem[55][7]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[51][7]~q ),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datae(!\A_SPW_TOP|rx_data|mem[53][7]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[49][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux10~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux10~16 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux10~16 .lut_mask = 64'h001B551BAA1BFF1B;
defparam \A_SPW_TOP|rx_data|Mux10~16 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y3_N27
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux10~15 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux10~15_combout  = ( \A_SPW_TOP|rx_data|rd_ptr [2] & ( \A_SPW_TOP|rx_data|mem[39][7]~q  & ( (\A_SPW_TOP|rx_data|rd_ptr [1]) # (\A_SPW_TOP|rx_data|mem[37][7]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [2] & ( 
// \A_SPW_TOP|rx_data|mem[39][7]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & ((\A_SPW_TOP|rx_data|mem[33][7]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|mem[35][7]~q )) ) ) ) # ( \A_SPW_TOP|rx_data|rd_ptr [2] & ( 
// !\A_SPW_TOP|rx_data|mem[39][7]~q  & ( (\A_SPW_TOP|rx_data|mem[37][7]~q  & !\A_SPW_TOP|rx_data|rd_ptr [1]) ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [2] & ( !\A_SPW_TOP|rx_data|mem[39][7]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & 
// ((\A_SPW_TOP|rx_data|mem[33][7]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|mem[35][7]~q )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[37][7]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[35][7]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[33][7]~q ),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datae(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .dataf(!\A_SPW_TOP|rx_data|mem[39][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux10~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux10~15 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux10~15 .lut_mask = 64'h0F3355000F3355FF;
defparam \A_SPW_TOP|rx_data|Mux10~15 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y4_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux10~17 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux10~17_combout  = ( \A_SPW_TOP|rx_data|mem[41][7]~q  & ( \A_SPW_TOP|rx_data|mem[45][7]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [1]) # ((!\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|mem[43][7]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [2] & 
// ((\A_SPW_TOP|rx_data|mem[47][7]~q )))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[41][7]~q  & ( \A_SPW_TOP|rx_data|mem[45][7]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & (((\A_SPW_TOP|rx_data|rd_ptr [2])))) # (\A_SPW_TOP|rx_data|rd_ptr [1] & 
// ((!\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|mem[43][7]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [2] & ((\A_SPW_TOP|rx_data|mem[47][7]~q ))))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[41][7]~q  & ( !\A_SPW_TOP|rx_data|mem[45][7]~q  & ( 
// (!\A_SPW_TOP|rx_data|rd_ptr [1] & (((!\A_SPW_TOP|rx_data|rd_ptr [2])))) # (\A_SPW_TOP|rx_data|rd_ptr [1] & ((!\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|mem[43][7]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [2] & ((\A_SPW_TOP|rx_data|mem[47][7]~q ))))) ) 
// ) ) # ( !\A_SPW_TOP|rx_data|mem[41][7]~q  & ( !\A_SPW_TOP|rx_data|mem[45][7]~q  & ( (\A_SPW_TOP|rx_data|rd_ptr [1] & ((!\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|mem[43][7]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [2] & 
// ((\A_SPW_TOP|rx_data|mem[47][7]~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datab(!\A_SPW_TOP|rx_data|mem[43][7]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[47][7]~q ),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datae(!\A_SPW_TOP|rx_data|mem[41][7]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[45][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux10~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux10~17 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux10~17 .lut_mask = 64'h1105BB0511AFBBAF;
defparam \A_SPW_TOP|rx_data|Mux10~17 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X35_Y3_N27
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux10~18 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux10~18_combout  = ( \A_SPW_TOP|rx_data|rd_ptr [1] & ( \A_SPW_TOP|rx_data|mem[59][7]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [2]) # (\A_SPW_TOP|rx_data|mem[63][7]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [1] & ( 
// \A_SPW_TOP|rx_data|mem[59][7]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [2] & ((\A_SPW_TOP|rx_data|mem[57][7]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|mem[61][7]~q )) ) ) ) # ( \A_SPW_TOP|rx_data|rd_ptr [1] & ( 
// !\A_SPW_TOP|rx_data|mem[59][7]~q  & ( (\A_SPW_TOP|rx_data|mem[63][7]~q  & \A_SPW_TOP|rx_data|rd_ptr [2]) ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [1] & ( !\A_SPW_TOP|rx_data|mem[59][7]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [2] & ((\A_SPW_TOP|rx_data|mem[57][7]~q 
// ))) # (\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|mem[61][7]~q )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[63][7]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[61][7]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[57][7]~q ),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datae(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .dataf(!\A_SPW_TOP|rx_data|mem[59][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux10~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux10~18 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux10~18 .lut_mask = 64'h0F3300550F33FF55;
defparam \A_SPW_TOP|rx_data|Mux10~18 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X32_Y3_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux10~19 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux10~19_combout  = ( \A_SPW_TOP|rx_data|Mux10~18_combout  & ( \A_SPW_TOP|rx_data|rd_ptr [3] & ( (\A_SPW_TOP|rx_data|rd_ptr [4]) # (\A_SPW_TOP|rx_data|Mux10~17_combout ) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux10~18_combout  & ( 
// \A_SPW_TOP|rx_data|rd_ptr [3] & ( (\A_SPW_TOP|rx_data|Mux10~17_combout  & !\A_SPW_TOP|rx_data|rd_ptr [4]) ) ) ) # ( \A_SPW_TOP|rx_data|Mux10~18_combout  & ( !\A_SPW_TOP|rx_data|rd_ptr [3] & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & 
// ((\A_SPW_TOP|rx_data|Mux10~15_combout ))) # (\A_SPW_TOP|rx_data|rd_ptr [4] & (\A_SPW_TOP|rx_data|Mux10~16_combout )) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux10~18_combout  & ( !\A_SPW_TOP|rx_data|rd_ptr [3] & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & 
// ((\A_SPW_TOP|rx_data|Mux10~15_combout ))) # (\A_SPW_TOP|rx_data|rd_ptr [4] & (\A_SPW_TOP|rx_data|Mux10~16_combout )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux10~16_combout ),
        .datab(!\A_SPW_TOP|rx_data|Mux10~15_combout ),
        .datac(!\A_SPW_TOP|rx_data|Mux10~17_combout ),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [4]),
        .datae(!\A_SPW_TOP|rx_data|Mux10~18_combout ),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux10~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux10~19 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux10~19 .lut_mask = 64'h335533550F000FFF;
defparam \A_SPW_TOP|rx_data|Mux10~19 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X35_Y3_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux10~3 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux10~3_combout  = ( \A_SPW_TOP|rx_data|mem[30][7]~q  & ( \A_SPW_TOP|rx_data|mem[24][7]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [2] & (((!\A_SPW_TOP|rx_data|rd_ptr [1]) # (\A_SPW_TOP|rx_data|mem[26][7]~q )))) # (\A_SPW_TOP|rx_data|rd_ptr [2] 
// & (((\A_SPW_TOP|rx_data|rd_ptr [1])) # (\A_SPW_TOP|rx_data|mem[28][7]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[30][7]~q  & ( \A_SPW_TOP|rx_data|mem[24][7]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [2] & (((!\A_SPW_TOP|rx_data|rd_ptr [1]) # 
// (\A_SPW_TOP|rx_data|mem[26][7]~q )))) # (\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|mem[28][7]~q  & (!\A_SPW_TOP|rx_data|rd_ptr [1]))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[30][7]~q  & ( !\A_SPW_TOP|rx_data|mem[24][7]~q  & ( 
// (!\A_SPW_TOP|rx_data|rd_ptr [2] & (((\A_SPW_TOP|rx_data|rd_ptr [1] & \A_SPW_TOP|rx_data|mem[26][7]~q )))) # (\A_SPW_TOP|rx_data|rd_ptr [2] & (((\A_SPW_TOP|rx_data|rd_ptr [1])) # (\A_SPW_TOP|rx_data|mem[28][7]~q ))) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|mem[30][7]~q  & ( !\A_SPW_TOP|rx_data|mem[24][7]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [2] & (((\A_SPW_TOP|rx_data|rd_ptr [1] & \A_SPW_TOP|rx_data|mem[26][7]~q )))) # (\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|mem[28][7]~q  & 
// (!\A_SPW_TOP|rx_data|rd_ptr [1]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datab(!\A_SPW_TOP|rx_data|mem[28][7]~q ),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datad(!\A_SPW_TOP|rx_data|mem[26][7]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[30][7]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[24][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux10~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux10~3 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux10~3 .lut_mask = 64'h101A151FB0BAB5BF;
defparam \A_SPW_TOP|rx_data|Mux10~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X31_Y4_N45
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux10~2 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux10~2_combout  = ( \A_SPW_TOP|rx_data|mem[14][7]~q  & ( \A_SPW_TOP|rx_data|mem[10][7]~q  & ( ((!\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|mem[8][7]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [2] & ((\A_SPW_TOP|rx_data|mem[12][7]~q 
// )))) # (\A_SPW_TOP|rx_data|rd_ptr [1]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[14][7]~q  & ( \A_SPW_TOP|rx_data|mem[10][7]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & ((!\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|mem[8][7]~q )) # 
// (\A_SPW_TOP|rx_data|rd_ptr [2] & ((\A_SPW_TOP|rx_data|mem[12][7]~q ))))) # (\A_SPW_TOP|rx_data|rd_ptr [1] & (((!\A_SPW_TOP|rx_data|rd_ptr [2])))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[14][7]~q  & ( !\A_SPW_TOP|rx_data|mem[10][7]~q  & ( 
// (!\A_SPW_TOP|rx_data|rd_ptr [1] & ((!\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|mem[8][7]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [2] & ((\A_SPW_TOP|rx_data|mem[12][7]~q ))))) # (\A_SPW_TOP|rx_data|rd_ptr [1] & (((\A_SPW_TOP|rx_data|rd_ptr [2])))) ) ) 
// ) # ( !\A_SPW_TOP|rx_data|mem[14][7]~q  & ( !\A_SPW_TOP|rx_data|mem[10][7]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & ((!\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|mem[8][7]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [2] & ((\A_SPW_TOP|rx_data|mem[12][7]~q 
// ))))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[8][7]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[12][7]~q ),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datae(!\A_SPW_TOP|rx_data|mem[14][7]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[10][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux10~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux10~2 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux10~2 .lut_mask = 64'h5030503F5F305F3F;
defparam \A_SPW_TOP|rx_data|Mux10~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X31_Y3_N21
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux10~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux10~0_combout  = ( \A_SPW_TOP|rx_data|mem[0][7]~q  & ( \A_SPW_TOP|rx_data|mem[4][7]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [1]) # ((!\A_SPW_TOP|rx_data|rd_ptr [2] & ((\A_SPW_TOP|rx_data|mem[2][7]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [2] & 
// (\A_SPW_TOP|rx_data|mem[6][7]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[0][7]~q  & ( \A_SPW_TOP|rx_data|mem[4][7]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & (((\A_SPW_TOP|rx_data|rd_ptr [2])))) # (\A_SPW_TOP|rx_data|rd_ptr [1] & ((!\A_SPW_TOP|rx_data|rd_ptr 
// [2] & ((\A_SPW_TOP|rx_data|mem[2][7]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|mem[6][7]~q )))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[0][7]~q  & ( !\A_SPW_TOP|rx_data|mem[4][7]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & 
// (((!\A_SPW_TOP|rx_data|rd_ptr [2])))) # (\A_SPW_TOP|rx_data|rd_ptr [1] & ((!\A_SPW_TOP|rx_data|rd_ptr [2] & ((\A_SPW_TOP|rx_data|mem[2][7]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|mem[6][7]~q )))) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|mem[0][7]~q  & ( !\A_SPW_TOP|rx_data|mem[4][7]~q  & ( (\A_SPW_TOP|rx_data|rd_ptr [1] & ((!\A_SPW_TOP|rx_data|rd_ptr [2] & ((\A_SPW_TOP|rx_data|mem[2][7]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|mem[6][7]~q )))) ) ) 
// )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datab(!\A_SPW_TOP|rx_data|mem[6][7]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[2][7]~q ),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datae(!\A_SPW_TOP|rx_data|mem[0][7]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[4][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux10~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux10~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux10~0 .lut_mask = 64'h0511AF1105BBAFBB;
defparam \A_SPW_TOP|rx_data|Mux10~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X33_Y3_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux10~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux10~1_combout  = ( \A_SPW_TOP|rx_data|mem[18][7]~q  & ( \A_SPW_TOP|rx_data|rd_ptr [2] & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|mem[20][7]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [1] & ((\A_SPW_TOP|rx_data|mem[22][7]~q ))) ) 
// ) ) # ( !\A_SPW_TOP|rx_data|mem[18][7]~q  & ( \A_SPW_TOP|rx_data|rd_ptr [2] & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|mem[20][7]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [1] & ((\A_SPW_TOP|rx_data|mem[22][7]~q ))) ) ) ) # ( 
// \A_SPW_TOP|rx_data|mem[18][7]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [2] & ( (\A_SPW_TOP|rx_data|rd_ptr [1]) # (\A_SPW_TOP|rx_data|mem[16][7]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[18][7]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [2] & ( 
// (\A_SPW_TOP|rx_data|mem[16][7]~q  & !\A_SPW_TOP|rx_data|rd_ptr [1]) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[20][7]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[16][7]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[22][7]~q ),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datae(!\A_SPW_TOP|rx_data|mem[18][7]~q ),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux10~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux10~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux10~1 .lut_mask = 64'h330033FF550F550F;
defparam \A_SPW_TOP|rx_data|Mux10~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X32_Y3_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux10~4 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux10~4_combout  = ( \A_SPW_TOP|rx_data|Mux10~1_combout  & ( \A_SPW_TOP|rx_data|rd_ptr [3] & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & ((\A_SPW_TOP|rx_data|Mux10~2_combout ))) # (\A_SPW_TOP|rx_data|rd_ptr [4] & 
// (\A_SPW_TOP|rx_data|Mux10~3_combout )) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux10~1_combout  & ( \A_SPW_TOP|rx_data|rd_ptr [3] & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & ((\A_SPW_TOP|rx_data|Mux10~2_combout ))) # (\A_SPW_TOP|rx_data|rd_ptr [4] & 
// (\A_SPW_TOP|rx_data|Mux10~3_combout )) ) ) ) # ( \A_SPW_TOP|rx_data|Mux10~1_combout  & ( !\A_SPW_TOP|rx_data|rd_ptr [3] & ( (\A_SPW_TOP|rx_data|rd_ptr [4]) # (\A_SPW_TOP|rx_data|Mux10~0_combout ) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux10~1_combout  & ( 
// !\A_SPW_TOP|rx_data|rd_ptr [3] & ( (\A_SPW_TOP|rx_data|Mux10~0_combout  & !\A_SPW_TOP|rx_data|rd_ptr [4]) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux10~3_combout ),
        .datab(!\A_SPW_TOP|rx_data|Mux10~2_combout ),
        .datac(!\A_SPW_TOP|rx_data|Mux10~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [4]),
        .datae(!\A_SPW_TOP|rx_data|Mux10~1_combout ),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux10~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux10~4 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux10~4 .lut_mask = 64'h0F000FFF33553355;
defparam \A_SPW_TOP|rx_data|Mux10~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X35_Y3_N33
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux10~8 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux10~8_combout  = ( \A_SPW_TOP|rx_data|mem[56][7]~q  & ( \A_SPW_TOP|rx_data|rd_ptr [2] & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|mem[60][7]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [1] & ((\A_SPW_TOP|rx_data|mem[62][7]~q ))) ) 
// ) ) # ( !\A_SPW_TOP|rx_data|mem[56][7]~q  & ( \A_SPW_TOP|rx_data|rd_ptr [2] & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|mem[60][7]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [1] & ((\A_SPW_TOP|rx_data|mem[62][7]~q ))) ) ) ) # ( 
// \A_SPW_TOP|rx_data|mem[56][7]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [2] & ( (!\A_SPW_TOP|rx_data|rd_ptr [1]) # (\A_SPW_TOP|rx_data|mem[58][7]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[56][7]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [2] & ( 
// (\A_SPW_TOP|rx_data|mem[58][7]~q  & \A_SPW_TOP|rx_data|rd_ptr [1]) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[60][7]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[58][7]~q ),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datad(!\A_SPW_TOP|rx_data|mem[62][7]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[56][7]~q ),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux10~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux10~8 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux10~8 .lut_mask = 64'h0303F3F3505F505F;
defparam \A_SPW_TOP|rx_data|Mux10~8 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y3_N9
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux10~5 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux10~5_combout  = ( \A_SPW_TOP|rx_data|rd_ptr [2] & ( \A_SPW_TOP|rx_data|rd_ptr [1] & ( \A_SPW_TOP|rx_data|mem[38][7]~q  ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [2] & ( \A_SPW_TOP|rx_data|rd_ptr [1] & ( \A_SPW_TOP|rx_data|mem[34][7]~q  ) 
// ) ) # ( \A_SPW_TOP|rx_data|rd_ptr [2] & ( !\A_SPW_TOP|rx_data|rd_ptr [1] & ( \A_SPW_TOP|rx_data|mem[36][7]~q  ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [2] & ( !\A_SPW_TOP|rx_data|rd_ptr [1] & ( \A_SPW_TOP|rx_data|mem[32][7]~q  ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[34][7]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[32][7]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[36][7]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[38][7]~q ),
        .datae(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux10~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux10~5 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux10~5 .lut_mask = 64'h33330F0F555500FF;
defparam \A_SPW_TOP|rx_data|Mux10~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y4_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux10~7 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux10~7_combout  = ( \A_SPW_TOP|rx_data|mem[44][7]~q  & ( \A_SPW_TOP|rx_data|mem[46][7]~q  & ( ((!\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|mem[40][7]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [1] & ((\A_SPW_TOP|rx_data|mem[42][7]~q 
// )))) # (\A_SPW_TOP|rx_data|rd_ptr [2]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[44][7]~q  & ( \A_SPW_TOP|rx_data|mem[46][7]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|mem[40][7]~q  & ((!\A_SPW_TOP|rx_data|rd_ptr [2])))) # 
// (\A_SPW_TOP|rx_data|rd_ptr [1] & (((\A_SPW_TOP|rx_data|rd_ptr [2]) # (\A_SPW_TOP|rx_data|mem[42][7]~q )))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[44][7]~q  & ( !\A_SPW_TOP|rx_data|mem[46][7]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & (((\A_SPW_TOP|rx_data|rd_ptr 
// [2])) # (\A_SPW_TOP|rx_data|mem[40][7]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [1] & (((\A_SPW_TOP|rx_data|mem[42][7]~q  & !\A_SPW_TOP|rx_data|rd_ptr [2])))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[44][7]~q  & ( !\A_SPW_TOP|rx_data|mem[46][7]~q  & ( 
// (!\A_SPW_TOP|rx_data|rd_ptr [2] & ((!\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|mem[40][7]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [1] & ((\A_SPW_TOP|rx_data|mem[42][7]~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datab(!\A_SPW_TOP|rx_data|mem[40][7]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[42][7]~q ),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datae(!\A_SPW_TOP|rx_data|mem[44][7]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[46][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux10~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux10~7 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux10~7 .lut_mask = 64'h270027AA275527FF;
defparam \A_SPW_TOP|rx_data|Mux10~7 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X33_Y3_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux10~6 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux10~6_combout  = ( \A_SPW_TOP|rx_data|mem[52][7]~q  & ( \A_SPW_TOP|rx_data|mem[54][7]~q  & ( ((!\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|mem[48][7]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [1] & ((\A_SPW_TOP|rx_data|mem[50][7]~q 
// )))) # (\A_SPW_TOP|rx_data|rd_ptr [2]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[52][7]~q  & ( \A_SPW_TOP|rx_data|mem[54][7]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [2] & ((!\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|mem[48][7]~q )) # 
// (\A_SPW_TOP|rx_data|rd_ptr [1] & ((\A_SPW_TOP|rx_data|mem[50][7]~q ))))) # (\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|rd_ptr [1])) ) ) ) # ( \A_SPW_TOP|rx_data|mem[52][7]~q  & ( !\A_SPW_TOP|rx_data|mem[54][7]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr 
// [2] & ((!\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|mem[48][7]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [1] & ((\A_SPW_TOP|rx_data|mem[50][7]~q ))))) # (\A_SPW_TOP|rx_data|rd_ptr [2] & (!\A_SPW_TOP|rx_data|rd_ptr [1])) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|mem[52][7]~q  & ( !\A_SPW_TOP|rx_data|mem[54][7]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [2] & ((!\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|mem[48][7]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [1] & ((\A_SPW_TOP|rx_data|mem[50][7]~q ))))) 
// ) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datab(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datac(!\A_SPW_TOP|rx_data|mem[48][7]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[50][7]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[52][7]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[54][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux10~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux10~6 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux10~6 .lut_mask = 64'h082A4C6E193B5D7F;
defparam \A_SPW_TOP|rx_data|Mux10~6 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X32_Y3_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux10~9 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux10~9_combout  = ( \A_SPW_TOP|rx_data|Mux10~6_combout  & ( \A_SPW_TOP|rx_data|rd_ptr [3] & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & ((\A_SPW_TOP|rx_data|Mux10~7_combout ))) # (\A_SPW_TOP|rx_data|rd_ptr [4] & 
// (\A_SPW_TOP|rx_data|Mux10~8_combout )) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux10~6_combout  & ( \A_SPW_TOP|rx_data|rd_ptr [3] & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & ((\A_SPW_TOP|rx_data|Mux10~7_combout ))) # (\A_SPW_TOP|rx_data|rd_ptr [4] & 
// (\A_SPW_TOP|rx_data|Mux10~8_combout )) ) ) ) # ( \A_SPW_TOP|rx_data|Mux10~6_combout  & ( !\A_SPW_TOP|rx_data|rd_ptr [3] & ( (\A_SPW_TOP|rx_data|rd_ptr [4]) # (\A_SPW_TOP|rx_data|Mux10~5_combout ) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux10~6_combout  & ( 
// !\A_SPW_TOP|rx_data|rd_ptr [3] & ( (\A_SPW_TOP|rx_data|Mux10~5_combout  & !\A_SPW_TOP|rx_data|rd_ptr [4]) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux10~8_combout ),
        .datab(!\A_SPW_TOP|rx_data|Mux10~5_combout ),
        .datac(!\A_SPW_TOP|rx_data|Mux10~7_combout ),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [4]),
        .datae(!\A_SPW_TOP|rx_data|Mux10~6_combout ),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux10~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux10~9 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux10~9 .lut_mask = 64'h330033FF0F550F55;
defparam \A_SPW_TOP|rx_data|Mux10~9 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X32_Y3_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux10~11 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux10~11_combout  = ( \A_SPW_TOP|rx_data|mem[23][7]~q  & ( \A_SPW_TOP|rx_data|mem[19][7]~q  & ( ((!\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|mem[17][7]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [2] & ((\A_SPW_TOP|rx_data|mem[21][7]~q 
// )))) # (\A_SPW_TOP|rx_data|rd_ptr [1]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[23][7]~q  & ( \A_SPW_TOP|rx_data|mem[19][7]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [2] & (((\A_SPW_TOP|rx_data|rd_ptr [1])) # (\A_SPW_TOP|rx_data|mem[17][7]~q ))) # 
// (\A_SPW_TOP|rx_data|rd_ptr [2] & (((\A_SPW_TOP|rx_data|mem[21][7]~q  & !\A_SPW_TOP|rx_data|rd_ptr [1])))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[23][7]~q  & ( !\A_SPW_TOP|rx_data|mem[19][7]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [2] & 
// (\A_SPW_TOP|rx_data|mem[17][7]~q  & ((!\A_SPW_TOP|rx_data|rd_ptr [1])))) # (\A_SPW_TOP|rx_data|rd_ptr [2] & (((\A_SPW_TOP|rx_data|rd_ptr [1]) # (\A_SPW_TOP|rx_data|mem[21][7]~q )))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[23][7]~q  & ( 
// !\A_SPW_TOP|rx_data|mem[19][7]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & ((!\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|mem[17][7]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [2] & ((\A_SPW_TOP|rx_data|mem[21][7]~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[17][7]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[21][7]~q ),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datae(!\A_SPW_TOP|rx_data|mem[23][7]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[19][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux10~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux10~11 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux10~11 .lut_mask = 64'h5300530F53F053FF;
defparam \A_SPW_TOP|rx_data|Mux10~11 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X31_Y4_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux10~12 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux10~12_combout  = ( \A_SPW_TOP|rx_data|mem[13][7]~q  & ( \A_SPW_TOP|rx_data|mem[11][7]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & (((\A_SPW_TOP|rx_data|mem[9][7]~q ) # (\A_SPW_TOP|rx_data|rd_ptr [2])))) # (\A_SPW_TOP|rx_data|rd_ptr [1] 
// & (((!\A_SPW_TOP|rx_data|rd_ptr [2])) # (\A_SPW_TOP|rx_data|mem[15][7]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[13][7]~q  & ( \A_SPW_TOP|rx_data|mem[11][7]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & (((!\A_SPW_TOP|rx_data|rd_ptr [2] & 
// \A_SPW_TOP|rx_data|mem[9][7]~q )))) # (\A_SPW_TOP|rx_data|rd_ptr [1] & (((!\A_SPW_TOP|rx_data|rd_ptr [2])) # (\A_SPW_TOP|rx_data|mem[15][7]~q ))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[13][7]~q  & ( !\A_SPW_TOP|rx_data|mem[11][7]~q  & ( 
// (!\A_SPW_TOP|rx_data|rd_ptr [1] & (((\A_SPW_TOP|rx_data|mem[9][7]~q ) # (\A_SPW_TOP|rx_data|rd_ptr [2])))) # (\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|mem[15][7]~q  & (\A_SPW_TOP|rx_data|rd_ptr [2]))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[13][7]~q  
// & ( !\A_SPW_TOP|rx_data|mem[11][7]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & (((!\A_SPW_TOP|rx_data|rd_ptr [2] & \A_SPW_TOP|rx_data|mem[9][7]~q )))) # (\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|mem[15][7]~q  & (\A_SPW_TOP|rx_data|rd_ptr [2]))) ) 
// ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[15][7]~q ),
        .datab(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datad(!\A_SPW_TOP|rx_data|mem[9][7]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[13][7]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[11][7]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux10~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux10~12 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux10~12 .lut_mask = 64'h01C10DCD31F13DFD;
defparam \A_SPW_TOP|rx_data|Mux10~12 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X31_Y3_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux10~10 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux10~10_combout  = ( \A_SPW_TOP|rx_data|mem[3][7]~q  & ( \A_SPW_TOP|rx_data|rd_ptr [2] & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|mem[5][7]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [1] & ((\A_SPW_TOP|rx_data|mem[7][7]~q ))) ) ) 
// ) # ( !\A_SPW_TOP|rx_data|mem[3][7]~q  & ( \A_SPW_TOP|rx_data|rd_ptr [2] & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|mem[5][7]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [1] & ((\A_SPW_TOP|rx_data|mem[7][7]~q ))) ) ) ) # ( 
// \A_SPW_TOP|rx_data|mem[3][7]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [2] & ( (\A_SPW_TOP|rx_data|rd_ptr [1]) # (\A_SPW_TOP|rx_data|mem[1][7]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[3][7]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [2] & ( (\A_SPW_TOP|rx_data|mem[1][7]~q  & 
// !\A_SPW_TOP|rx_data|rd_ptr [1]) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[1][7]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[5][7]~q ),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datad(!\A_SPW_TOP|rx_data|mem[7][7]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[3][7]~q ),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux10~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux10~10 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux10~10 .lut_mask = 64'h50505F5F303F303F;
defparam \A_SPW_TOP|rx_data|Mux10~10 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X35_Y3_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux10~13 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux10~13_combout  = ( \A_SPW_TOP|rx_data|mem[31][7]~q  & ( \A_SPW_TOP|rx_data|rd_ptr [2] & ( (\A_SPW_TOP|rx_data|rd_ptr [1]) # (\A_SPW_TOP|rx_data|mem[29][7]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[31][7]~q  & ( \A_SPW_TOP|rx_data|rd_ptr 
// [2] & ( (\A_SPW_TOP|rx_data|mem[29][7]~q  & !\A_SPW_TOP|rx_data|rd_ptr [1]) ) ) ) # ( \A_SPW_TOP|rx_data|mem[31][7]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [2] & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|mem[25][7]~q )) # 
// (\A_SPW_TOP|rx_data|rd_ptr [1] & ((\A_SPW_TOP|rx_data|mem[27][7]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[31][7]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [2] & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|mem[25][7]~q )) # (\A_SPW_TOP|rx_data|rd_ptr 
// [1] & ((\A_SPW_TOP|rx_data|mem[27][7]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[25][7]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[27][7]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[29][7]~q ),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datae(!\A_SPW_TOP|rx_data|mem[31][7]~q ),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux10~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux10~13 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux10~13 .lut_mask = 64'h553355330F000FFF;
defparam \A_SPW_TOP|rx_data|Mux10~13 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X32_Y3_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux10~14 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux10~14_combout  = ( \A_SPW_TOP|rx_data|Mux10~13_combout  & ( \A_SPW_TOP|rx_data|rd_ptr [3] & ( (\A_SPW_TOP|rx_data|rd_ptr [4]) # (\A_SPW_TOP|rx_data|Mux10~12_combout ) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux10~13_combout  & ( 
// \A_SPW_TOP|rx_data|rd_ptr [3] & ( (\A_SPW_TOP|rx_data|Mux10~12_combout  & !\A_SPW_TOP|rx_data|rd_ptr [4]) ) ) ) # ( \A_SPW_TOP|rx_data|Mux10~13_combout  & ( !\A_SPW_TOP|rx_data|rd_ptr [3] & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & 
// ((\A_SPW_TOP|rx_data|Mux10~10_combout ))) # (\A_SPW_TOP|rx_data|rd_ptr [4] & (\A_SPW_TOP|rx_data|Mux10~11_combout )) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux10~13_combout  & ( !\A_SPW_TOP|rx_data|rd_ptr [3] & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & 
// ((\A_SPW_TOP|rx_data|Mux10~10_combout ))) # (\A_SPW_TOP|rx_data|rd_ptr [4] & (\A_SPW_TOP|rx_data|Mux10~11_combout )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux10~11_combout ),
        .datab(!\A_SPW_TOP|rx_data|Mux10~12_combout ),
        .datac(!\A_SPW_TOP|rx_data|Mux10~10_combout ),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [4]),
        .datae(!\A_SPW_TOP|rx_data|Mux10~13_combout ),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux10~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux10~14 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux10~14 .lut_mask = 64'h0F550F55330033FF;
defparam \A_SPW_TOP|rx_data|Mux10~14 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X32_Y3_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux10~20 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux10~20_combout  = ( \A_SPW_TOP|rx_data|Mux10~14_combout  & ( \A_SPW_TOP|rx_data|rd_ptr [0] & ( (!\A_SPW_TOP|rx_data|rd_ptr [5]) # (\A_SPW_TOP|rx_data|Mux10~19_combout ) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux10~14_combout  & ( 
// \A_SPW_TOP|rx_data|rd_ptr [0] & ( (\A_SPW_TOP|rx_data|Mux10~19_combout  & \A_SPW_TOP|rx_data|rd_ptr [5]) ) ) ) # ( \A_SPW_TOP|rx_data|Mux10~14_combout  & ( !\A_SPW_TOP|rx_data|rd_ptr [0] & ( (!\A_SPW_TOP|rx_data|rd_ptr [5] & 
// (\A_SPW_TOP|rx_data|Mux10~4_combout )) # (\A_SPW_TOP|rx_data|rd_ptr [5] & ((\A_SPW_TOP|rx_data|Mux10~9_combout ))) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux10~14_combout  & ( !\A_SPW_TOP|rx_data|rd_ptr [0] & ( (!\A_SPW_TOP|rx_data|rd_ptr [5] & 
// (\A_SPW_TOP|rx_data|Mux10~4_combout )) # (\A_SPW_TOP|rx_data|rd_ptr [5] & ((\A_SPW_TOP|rx_data|Mux10~9_combout ))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux10~19_combout ),
        .datab(!\A_SPW_TOP|rx_data|Mux10~4_combout ),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .datad(!\A_SPW_TOP|rx_data|Mux10~9_combout ),
        .datae(!\A_SPW_TOP|rx_data|Mux10~14_combout ),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux10~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux10~20 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux10~20 .lut_mask = 64'h303F303F0505F5F5;
defparam \A_SPW_TOP|rx_data|Mux10~20 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y3_N43
dffeas \A_SPW_TOP|rx_data|data_out[7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Mux10~20_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|data_out [7]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|data_out[7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|data_out[7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y16_N0
cyclonev_lcell_comb \u0|data_flag_rx|read_mux_out[7] (
// Equation(s):
// \u0|data_flag_rx|read_mux_out [7] = ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & \A_SPW_TOP|rx_data|data_out [7]) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datab(gnd),
        .datac(!\A_SPW_TOP|rx_data|data_out [7]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|data_flag_rx|read_mux_out [7]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|data_flag_rx|read_mux_out[7] .extended_lut = "off";
defparam \u0|data_flag_rx|read_mux_out[7] .lut_mask = 64'h0A0A0A0A00000000;
defparam \u0|data_flag_rx|read_mux_out[7] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y16_N2
dffeas \u0|data_flag_rx|readdata[7] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|data_flag_rx|read_mux_out [7]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|data_flag_rx|readdata [7]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|data_flag_rx|readdata[7] .is_wysiwyg = "true";
defparam \u0|data_flag_rx|readdata[7] .power_up = "low";
// synopsys translate_on

// Location: FF_X23_Y16_N13
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre[7] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|data_flag_rx|readdata [7]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [7]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre[7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre[7] .power_up = "low";
// synopsys translate_on

// Location: FF_X27_Y16_N29
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][7] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~7_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y16_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~7 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~7_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][7]~q  ) ) # ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [7] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [7]),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][7]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~7 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~7 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y16_N11
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][7] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~7_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][7] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y20_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_001|src_payload~12 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_001|src_payload~12_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout  & ( \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_001|src_payload~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~12 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~12 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y20_N50
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_001|src_payload~12_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .power_up = "low";
// synopsys translate_on

// Location: FF_X14_Y20_N19
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y20_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_001|src_payload~14 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_001|src_payload~14_combout  = ( \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_001|src_payload~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~14 .lut_mask = 64'h000000000000FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~14 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y20_N14
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_001|src_payload~14_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y20_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_001|src_payload~15 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_001|src_payload~15_combout  = ( \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] ) )

        .dataa(gnd),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_001|src_payload~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~15 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~15 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y20_N20
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_001|src_payload~15_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y20_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_001|src_payload~16 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_001|src_payload~16_combout  = (\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1])

        .dataa(gnd),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_001|src_payload~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~16 .lut_mask = 64'h0303030303030303;
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~16 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y20_N17
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_001|src_payload~16_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y20_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_001|src_payload~15_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1])) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_001|src_payload~15_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & 
// ((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1])))) # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((\u0|mm_interconnect_0|cmd_mux_001|src_payload~16_combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_001|src_payload~16_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_001|src_payload~15_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .lut_mask = 64'h038B038B00880088;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y20_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) # 
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((\u0|mm_interconnect_0|cmd_mux_001|src_payload~14_combout ))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_001|src_payload~14_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .lut_mask = 64'h000000000C3F0C3F;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y20_N49
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y20_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) # 
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|cmd_mux_001|src_payload~14_combout ))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_001|src_payload~14_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .lut_mask = 64'h00000000F3C0F3C0;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y20_N37
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y20_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_001|src_payload~13 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_001|src_payload~13_combout  = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout  & ( \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_001|src_payload~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~13 .lut_mask = 64'h0F0F0F0F00000000;
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~13 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y20_N44
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_001|src_payload~13_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y20_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_001|src_payload~17 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_001|src_payload~17_combout  = (\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~1_combout )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~1_combout ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_001|src_payload~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~17 .lut_mask = 64'h000F000F000F000F;
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~17 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y20_N47
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_001|src_payload~17_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y20_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  = ( \u0|mm_interconnect_0|cmd_mux_001|src_payload~15_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1])) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_001|src_payload~15_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & 
// ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1])))) # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((!\u0|mm_interconnect_0|cmd_mux_001|src_payload~16_combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_001|src_payload~16_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_001|src_payload~15_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .lut_mask = 64'hB830B83088008800;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y20_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) # 
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((\u0|mm_interconnect_0|cmd_mux_001|src_payload~14_combout ))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_001|src_payload~14_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .lut_mask = 64'h000000000C3F0C3F;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y20_N7
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y20_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  = ( 
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ) # 
// (\u0|mm_interconnect_0|cmd_mux_001|src_payload~14_combout ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ) # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_001|src_payload~14_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .lut_mask = 64'hFF33FF33FF0FFF0F;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y20_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout  = ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .lut_mask = 64'hFFFFFFFF00000000;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y20_N29
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y20_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_001|src_payload~18 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_001|src_payload~18_combout  = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~2_combout  & ( \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_001|src_payload~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~18 .lut_mask = 64'h3333333300000000;
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~18 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y20_N53
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_001|src_payload~18_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y20_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0] = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0] & ( 
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  & 
// !\u0|mm_interconnect_0|cmd_mux_001|src_payload~18_combout )) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0] & ( 
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  & ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # 
// (!\u0|mm_interconnect_0|cmd_mux_001|src_payload~18_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_001|src_payload~18_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .lut_mask = 64'h0F0A0F0A05000500;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y20_N59
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y20_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout  = SUM(( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) + ( 
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14  = CARRY(( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) + ( 
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
        .cout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y20_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  = ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// (((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0] & (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ))) # 
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0])) ) ) # ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// (\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & (((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  & ((\u0|hps_0|fpga_interfaces|h2f_ARADDR [0])))))) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
        .datae(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [0]),
        .datag(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .extended_lut = "on";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .lut_mask = 64'h333F0000333F5050;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y20_N7
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y20_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout  = SUM(( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + ( 
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14  ))
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10  = CARRY(( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + ( 
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
        .cout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y20_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// (\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [1]))) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .lut_mask = 64'h0000000000400040;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y20_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1] = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]))) # 
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|cmd_mux_001|src_payload~17_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_001|src_payload~17_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .lut_mask = 64'h00000000CACACACA;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y20_N26
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y20_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1] & ( 
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ) ) ) # 
// ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1] & ( ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1] & \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ))) # 
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .lut_mask = 64'h02FF02FFAAFFAAFF;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y20_N16
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y20_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout  = SUM(( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + ( 
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10  ))
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6  = CARRY(( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + ( 
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10  ))

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
        .cout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .lut_mask = 64'h0000AAAA00000F0F;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y20_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2] = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] & ( 
// (!\u0|mm_interconnect_0|cmd_mux_001|src_payload~13_combout  & (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout )) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] & ( 
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout  & ((!\u0|mm_interconnect_0|cmd_mux_001|src_payload~13_combout ) # 
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_001|src_payload~13_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .lut_mask = 64'h00FC00FC000C000C;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y20_N13
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y20_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout  & ( 
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # 
// ((\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [2])) ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout  & ( 
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # 
// ((\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [2])) ) ) ) # ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout  & ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2])))) # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & ((\u0|hps_0|fpga_interfaces|h2f_ARADDR [2])))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout  & ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [2])) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [2]),
        .datae(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .lut_mask = 64'h00110A1BAABBAABB;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y20_N1
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y20_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout  = SUM(( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3] ) + ( 
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3] ) + ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y20_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3] = ( \u0|mm_interconnect_0|cmd_mux_001|src_payload~12_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3] & 
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_001|src_payload~12_combout  & ( 
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout  & ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]) # 
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_001|src_payload~12_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .lut_mask = 64'h00F500F500A000A0;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y20_N56
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y20_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [3] & ( 
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [3] & ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( ((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3] & 
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout )) # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]) ) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_ARADDR [3] & ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// ((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3] & \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout )) # 
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [3]),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .lut_mask = 64'h1F1F1F1F000000FF;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y20_N23
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .power_up = "low";
// synopsys translate_on

// Location: FF_X14_Y20_N5
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y3_N21
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|timecode~0 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|timecode~0_combout  = ( \A_SPW_TOP|SPW|RX|ready_data_p_r~q  & ( (\A_SPW_TOP|SPW|RX|control [1] & (!\A_SPW_TOP|SPW|RX|ready_control_p_r~q  & (\A_SPW_TOP|SPW|RX|control [0] & \A_SPW_TOP|SPW|RX|control [2]))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|control [1]),
        .datab(!\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),
        .datac(!\A_SPW_TOP|SPW|RX|control [0]),
        .datad(!\A_SPW_TOP|SPW|RX|control [2]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|ready_data_p_r~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|timecode~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|timecode~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|timecode~0 .lut_mask = 64'h0000000000040004;
defparam \A_SPW_TOP|SPW|RX|timecode~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y2_N3
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|timecode~8 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|timecode~8_combout  = ( \A_SPW_TOP|SPW|RX|timecode [7] & ( (!\A_SPW_TOP|SPW|RX|timecode~0_combout ) # (\A_SPW_TOP|SPW|RX|dta_timec_p [7]) ) ) # ( !\A_SPW_TOP|SPW|RX|timecode [7] & ( (\A_SPW_TOP|SPW|RX|dta_timec_p [7] & 
// \A_SPW_TOP|SPW|RX|timecode~0_combout ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|RX|dta_timec_p [7]),
        .datad(!\A_SPW_TOP|SPW|RX|timecode~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|timecode [7]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|timecode~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|timecode~8 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|timecode~8 .lut_mask = 64'h000F000FFF0FFF0F;
defparam \A_SPW_TOP|SPW|RX|timecode~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y2_N56
dffeas \A_SPW_TOP|SPW|RX|timecode[7] (
        .clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|RX|timecode~8_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(!\A_SPW_TOP|SPW|RX|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|timecode [7]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|timecode[7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|timecode[7] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y14_N39
cyclonev_lcell_comb \u0|timecode_rx|read_mux_out[7] (
// Equation(s):
// \u0|timecode_rx|read_mux_out [7] = ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & ( \A_SPW_TOP|SPW|RX|timecode [7] & ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .dataf(!\A_SPW_TOP|SPW|RX|timecode [7]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|timecode_rx|read_mux_out [7]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|timecode_rx|read_mux_out[7] .extended_lut = "off";
defparam \u0|timecode_rx|read_mux_out[7] .lut_mask = 64'h00000000F0F00000;
defparam \u0|timecode_rx|read_mux_out[7] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y14_N40
dffeas \u0|timecode_rx|readdata[7] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|timecode_rx|read_mux_out [7]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|timecode_rx|readdata [7]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|timecode_rx|readdata[7] .is_wysiwyg = "true";
defparam \u0|timecode_rx|readdata[7] .power_up = "low";
// synopsys translate_on

// Location: FF_X25_Y16_N22
dffeas \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[7] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|timecode_rx|readdata [7]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [7]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[7] .power_up = "low";
// synopsys translate_on

// Location: FF_X25_Y16_N47
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][7] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~7_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][7] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y16_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~7 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~7_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [7] & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1]) # 
// (\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][7]~q ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [7] & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][7]~q ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][7]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [7]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~7 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~7 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y21_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|always0~0_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|read~0_combout  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0] )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|read~0_combout ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0]),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|always0~0 .lut_mask = 64'hFFFF0F0FFFFF0F0F;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y16_N8
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][7] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~7_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][7] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y16_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~81 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~81_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0] & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout  & 
// ((!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0] & (\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [7])) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0] & 
// ((\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][7]~q ))))) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0] & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][7]~q  & 
// !\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [7]),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0]),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][7]~q ),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[7]~81_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~81 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~81 .lut_mask = 64'h0F000F0047004700;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~81 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y16_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~82 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~82_combout  = ( \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~81_combout  ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[7]~81_combout  & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout  & 
// ((!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout  & ((\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][7]~q ))) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout  & 
// (\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [7])))) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout ),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout ),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [7]),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][7]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[7]~81_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[7]~82_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~82 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~82 .lut_mask = 64'h028A028AFFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~82 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y16_N20
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][7] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~7_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y16_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~7 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~7_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][7]~q  ) ) # ( 
// !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [7] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [7]),
        .datad(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][7]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~7 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~7 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y16_N56
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][7] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~7_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][7]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y16_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~206 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~206_combout  = ( !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout  & ( ((((\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout  & 
// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][7]~q )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[7]~82_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[7]~80_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[7]~79_combout ) 
// ) ) # ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout  & ( ((((\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout  & \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [7])) # 
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[7]~82_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[7]~80_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[7]~79_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ),
        .datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[7]~79_combout ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [7]),
        .datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[7]~80_combout ),
        .datae(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout ),
        .dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[7]~82_combout ),
        .datag(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][7]~q ),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[7]~206_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~206 .extended_lut = "on";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~206 .lut_mask = 64'h37FF37FFFFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~206 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y17_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_payload~6 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_payload~6_combout  = ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_WDATA [6] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_WDATA [6]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_010|src_payload~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_payload~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_payload~6 .lut_mask = 64'h0000000000FF00FF;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_payload~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y17_N4
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_010|src_payload~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[6] .power_up = "low";
// synopsys translate_on

// Location: FF_X30_Y15_N53
dffeas \u0|write_data_fifo_tx|data_out[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [6]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|write_data_fifo_tx|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|write_data_fifo_tx|data_out [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|write_data_fifo_tx|data_out[6] .is_wysiwyg = "true";
defparam \u0|write_data_fifo_tx|data_out[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y15_N6
cyclonev_lcell_comb \u0|write_data_fifo_tx|readdata[6] (
// Equation(s):
// \u0|write_data_fifo_tx|readdata [6] = ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( (\u0|write_data_fifo_tx|data_out [6] & 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]) ) )

        .dataa(!\u0|write_data_fifo_tx|data_out [6]),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|write_data_fifo_tx|readdata [6]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|write_data_fifo_tx|readdata[6] .extended_lut = "off";
defparam \u0|write_data_fifo_tx|readdata[6] .lut_mask = 64'h4444000044440000;
defparam \u0|write_data_fifo_tx|readdata[6] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y15_N8
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|write_data_fifo_tx|readdata [6]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y15_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~6 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~6_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][6]~q  ) ) # ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [6] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][6]~q ),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [6]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~6 .lut_mask = 64'h00FF00FF0F0F0F0F;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y15_N13
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y15_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~75 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~75_combout  = ( \u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout  & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout  & 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][6]~q )) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout  & ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [6]))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][6]~q ),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [6]),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[6]~75_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~75 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~75 .lut_mask = 64'h00000000330F330F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~75 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X53_Y9_N16
dffeas \m_x|info[6] (
        .clk(!\m_x|always3~0_combout ),
        .d(gnd),
        .asdata(\m_x|control [0]),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\m_x|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|info [6]),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|info[6] .is_wysiwyg = "true";
defparam \m_x|info[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y13_N54
cyclonev_lcell_comb \u0|data_info|read_mux_out[6] (
// Equation(s):
// \u0|data_info|read_mux_out [6] = ( \m_x|info [6] & ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( 
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datac(gnd),
        .datad(gnd),
        .datae(!\m_x|info [6]),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|data_info|read_mux_out [6]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|data_info|read_mux_out[6] .extended_lut = "off";
defparam \u0|data_info|read_mux_out[6] .lut_mask = 64'h0000CCCC00000000;
defparam \u0|data_info|read_mux_out[6] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y13_N55
dffeas \u0|data_info|readdata[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|data_info|read_mux_out [6]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|data_info|readdata [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|data_info|readdata[6] .is_wysiwyg = "true";
defparam \u0|data_info|readdata[6] .power_up = "low";
// synopsys translate_on

// Location: FF_X31_Y13_N2
dffeas \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|data_info|readdata [6]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y2_N30
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|rx_data_flag~6 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|rx_data_flag~6_combout  = ( \A_SPW_TOP|SPW|RX|ready_control_p_r~q  & ( (\A_SPW_TOP|SPW|RX|rx_data_flag [6] & \A_SPW_TOP|SPW|RX|rx_data_flag~0_combout ) ) ) # ( !\A_SPW_TOP|SPW|RX|ready_control_p_r~q  & ( 
// (!\A_SPW_TOP|SPW|RX|data~0_combout  & (((\A_SPW_TOP|SPW|RX|rx_data_flag [6] & \A_SPW_TOP|SPW|RX|rx_data_flag~0_combout )) # (\A_SPW_TOP|SPW|RX|dta_timec_p [6]))) # (\A_SPW_TOP|SPW|RX|data~0_combout  & (\A_SPW_TOP|SPW|RX|rx_data_flag [6])) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .datab(!\A_SPW_TOP|SPW|RX|data~0_combout ),
        .datac(!\A_SPW_TOP|SPW|RX|dta_timec_p [6]),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag~0_combout ),
        .datae(!\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|rx_data_flag~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_data_flag~6 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|rx_data_flag~6 .lut_mask = 64'h1D5D00551D5D0055;
defparam \A_SPW_TOP|SPW|RX|rx_data_flag~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y2_N35
dffeas \A_SPW_TOP|SPW|RX|rx_data_flag[6] (
        .clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|RX|rx_data_flag~6_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(!\A_SPW_TOP|SPW|RX|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_data_flag[6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|rx_data_flag[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y3_N21
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector507~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector507~0_combout  = ( \A_SPW_TOP|rx_data|Selector505~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [6])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux2~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector505~0_combout  & ( \A_SPW_TOP|rx_data|mem[54][6]~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[54][6]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector505~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector507~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector507~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector507~0 .lut_mask = 64'h00FF00FF47474747;
defparam \A_SPW_TOP|rx_data|Selector507~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y3_N2
dffeas \A_SPW_TOP|rx_data|mem[54][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector507~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[54][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[54][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[54][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y3_N57
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector363~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector363~0_combout  = ( \A_SPW_TOP|rx_data|Selector361~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [6])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux2~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector361~0_combout  & ( \A_SPW_TOP|rx_data|mem[38][6]~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[38][6]~q ),
        .datad(!\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector361~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector363~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector363~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector363~0 .lut_mask = 64'h0F0F0F0F44774477;
defparam \A_SPW_TOP|rx_data|Selector363~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y3_N47
dffeas \A_SPW_TOP|rx_data|mem[38][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector363~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[38][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[38][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[38][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y3_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector471~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector471~0_combout  = ( \A_SPW_TOP|rx_data|Selector469~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [6])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux2~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector469~0_combout  & ( \A_SPW_TOP|rx_data|mem[50][6]~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[50][6]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector469~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector471~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector471~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector471~0 .lut_mask = 64'h00FF00FF47474747;
defparam \A_SPW_TOP|rx_data|Selector471~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y3_N29
dffeas \A_SPW_TOP|rx_data|mem[50][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector471~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[50][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[50][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[50][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y3_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector327~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector327~0_combout  = ( \A_SPW_TOP|rx_data|mem[34][6]~q  & ( (!\A_SPW_TOP|rx_data|Selector325~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [6]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux2~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[34][6]~q  & ( (\A_SPW_TOP|rx_data|Selector325~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [6]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux2~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector325~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[34][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector327~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector327~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector327~0 .lut_mask = 64'h010B010BF1FBF1FB;
defparam \A_SPW_TOP|rx_data|Selector327~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y3_N53
dffeas \A_SPW_TOP|rx_data|mem[34][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector327~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[34][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[34][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[34][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y3_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux2~12 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux2~12_combout  = ( \A_SPW_TOP|rx_data|mem[50][6]~q  & ( \A_SPW_TOP|rx_data|mem[34][6]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2]) # ((!\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|mem[38][6]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [4] 
// & (\A_SPW_TOP|rx_data|mem[54][6]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[50][6]~q  & ( \A_SPW_TOP|rx_data|mem[34][6]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & (((!\A_SPW_TOP|rx_data|wr_ptr [4])))) # (\A_SPW_TOP|rx_data|wr_ptr [2] & 
// ((!\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|mem[38][6]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[54][6]~q )))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[50][6]~q  & ( !\A_SPW_TOP|rx_data|mem[34][6]~q  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [2] & (((\A_SPW_TOP|rx_data|wr_ptr [4])))) # (\A_SPW_TOP|rx_data|wr_ptr [2] & ((!\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|mem[38][6]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[54][6]~q )))) ) ) 
// ) # ( !\A_SPW_TOP|rx_data|mem[50][6]~q  & ( !\A_SPW_TOP|rx_data|mem[34][6]~q  & ( (\A_SPW_TOP|rx_data|wr_ptr [2] & ((!\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|mem[38][6]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[54][6]~q 
// )))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[54][6]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[38][6]~q ),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datae(!\A_SPW_TOP|rx_data|mem[50][6]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[34][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux2~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux2~12 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux2~12 .lut_mask = 64'h030503F5F305F3F5;
defparam \A_SPW_TOP|rx_data|Mux2~12 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y3_N39
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector309~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector309~0_combout  = ( \A_SPW_TOP|rx_data|Selector307~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [6])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux2~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector307~0_combout  & ( \A_SPW_TOP|rx_data|mem[32][6]~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .datab(!\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|mem[32][6]~q ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector307~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector309~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector309~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector309~0 .lut_mask = 64'h0F0F0F0F55335533;
defparam \A_SPW_TOP|rx_data|Selector309~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y3_N44
dffeas \A_SPW_TOP|rx_data|mem[32][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector309~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[32][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[32][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[32][6] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y3_N57
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector345~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector345~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector343~0_combout  & ((\A_SPW_TOP|rx_data|mem[36][6]~q ))) # (\A_SPW_TOP|rx_data|Selector343~0_combout  & 
// (\A_SPW_TOP|rx_data|Mux2~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector343~0_combout  & ((\A_SPW_TOP|rx_data|mem[36][6]~q ))) # (\A_SPW_TOP|rx_data|Selector343~0_combout  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [6])) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .datab(!\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector343~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[36][6]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector345~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector345~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector345~0 .lut_mask = 64'h05F505F503F303F3;
defparam \A_SPW_TOP|rx_data|Selector345~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y3_N23
dffeas \A_SPW_TOP|rx_data|mem[36][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector345~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[36][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[36][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[36][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y3_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector489~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector489~0_combout  = ( \A_SPW_TOP|rx_data|Selector487~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [6]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux2~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector487~0_combout  & ( \A_SPW_TOP|rx_data|mem[52][6]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .datac(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .datad(!\A_SPW_TOP|rx_data|mem[52][6]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector487~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector489~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector489~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector489~0 .lut_mask = 64'h00FF00FF1B1B1B1B;
defparam \A_SPW_TOP|rx_data|Selector489~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y3_N38
dffeas \A_SPW_TOP|rx_data|mem[52][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector489~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[52][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[52][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[52][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y3_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector453~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector453~0_combout  = ( \A_SPW_TOP|rx_data|mem[48][6]~q  & ( (!\A_SPW_TOP|rx_data|Selector451~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [6]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux2~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[48][6]~q  & ( (\A_SPW_TOP|rx_data|Selector451~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [6]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux2~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .datac(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .datad(!\A_SPW_TOP|rx_data|Selector451~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[48][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector453~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector453~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector453~0 .lut_mask = 64'h001B001BFF1BFF1B;
defparam \A_SPW_TOP|rx_data|Selector453~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y3_N20
dffeas \A_SPW_TOP|rx_data|mem[48][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector453~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[48][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[48][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[48][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y3_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux2~10 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux2~10_combout  = ( \A_SPW_TOP|rx_data|mem[52][6]~q  & ( \A_SPW_TOP|rx_data|mem[48][6]~q  & ( ((!\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|mem[32][6]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [2] & ((\A_SPW_TOP|rx_data|mem[36][6]~q 
// )))) # (\A_SPW_TOP|rx_data|wr_ptr [4]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[52][6]~q  & ( \A_SPW_TOP|rx_data|mem[48][6]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [4] & ((!\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|mem[32][6]~q )) # 
// (\A_SPW_TOP|rx_data|wr_ptr [2] & ((\A_SPW_TOP|rx_data|mem[36][6]~q ))))) # (\A_SPW_TOP|rx_data|wr_ptr [4] & (((!\A_SPW_TOP|rx_data|wr_ptr [2])))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[52][6]~q  & ( !\A_SPW_TOP|rx_data|mem[48][6]~q  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [4] & ((!\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|mem[32][6]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [2] & ((\A_SPW_TOP|rx_data|mem[36][6]~q ))))) # (\A_SPW_TOP|rx_data|wr_ptr [4] & (((\A_SPW_TOP|rx_data|wr_ptr [2])))) ) ) 
// ) # ( !\A_SPW_TOP|rx_data|mem[52][6]~q  & ( !\A_SPW_TOP|rx_data|mem[48][6]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [4] & ((!\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|mem[32][6]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [2] & ((\A_SPW_TOP|rx_data|mem[36][6]~q 
// ))))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datab(!\A_SPW_TOP|rx_data|mem[32][6]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[36][6]~q ),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datae(!\A_SPW_TOP|rx_data|mem[52][6]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[48][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux2~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux2~10 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux2~10 .lut_mask = 64'h220A225F770A775F;
defparam \A_SPW_TOP|rx_data|Mux2~10 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y3_N9
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector462~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector462~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector460~0_combout  & ((\A_SPW_TOP|rx_data|mem[49][6]~q ))) # (\A_SPW_TOP|rx_data|Selector460~0_combout  & 
// (\A_SPW_TOP|rx_data|Mux2~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector460~0_combout  & ((\A_SPW_TOP|rx_data|mem[49][6]~q ))) # (\A_SPW_TOP|rx_data|Selector460~0_combout  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [6])) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .datab(!\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|mem[49][6]~q ),
        .datad(!\A_SPW_TOP|rx_data|Selector460~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector462~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector462~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector462~0 .lut_mask = 64'h0F550F550F330F33;
defparam \A_SPW_TOP|rx_data|Selector462~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y3_N53
dffeas \A_SPW_TOP|rx_data|mem[49][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector462~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[49][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[49][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[49][6] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y3_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector318~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector318~0_combout  = ( \A_SPW_TOP|rx_data|mem[33][6]~q  & ( (!\A_SPW_TOP|rx_data|Selector316~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [6])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux2~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[33][6]~q  & ( (\A_SPW_TOP|rx_data|Selector316~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [6])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux2~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .datab(!\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector316~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[33][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector318~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector318~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector318~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|rx_data|Selector318~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y3_N41
dffeas \A_SPW_TOP|rx_data|mem[33][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector318~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[33][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[33][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[33][6] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y3_N45
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector498~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector498~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector496~0_combout  & ((\A_SPW_TOP|rx_data|mem[53][6]~q ))) # (\A_SPW_TOP|rx_data|Selector496~0_combout  & 
// (\A_SPW_TOP|rx_data|Mux2~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector496~0_combout  & ((\A_SPW_TOP|rx_data|mem[53][6]~q ))) # (\A_SPW_TOP|rx_data|Selector496~0_combout  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [6])) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .datab(!\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector496~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[53][6]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector498~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector498~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector498~0 .lut_mask = 64'h05F505F503F303F3;
defparam \A_SPW_TOP|rx_data|Selector498~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y3_N29
dffeas \A_SPW_TOP|rx_data|mem[53][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector498~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[53][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[53][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[53][6] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y3_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector354~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector354~0_combout  = ( \A_SPW_TOP|rx_data|mem[37][6]~q  & ( (!\A_SPW_TOP|rx_data|Selector352~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [6])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux2~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[37][6]~q  & ( (\A_SPW_TOP|rx_data|Selector352~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [6])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux2~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .datab(!\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector352~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[37][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector354~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector354~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector354~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|rx_data|Selector354~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y3_N17
dffeas \A_SPW_TOP|rx_data|mem[37][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector354~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[37][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[37][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[37][6] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y3_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux2~11 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux2~11_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [2] & ( \A_SPW_TOP|rx_data|mem[37][6]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [4]) # (\A_SPW_TOP|rx_data|mem[53][6]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [2] & ( 
// \A_SPW_TOP|rx_data|mem[37][6]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|mem[33][6]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[49][6]~q )) ) ) ) # ( \A_SPW_TOP|rx_data|wr_ptr [2] & ( 
// !\A_SPW_TOP|rx_data|mem[37][6]~q  & ( (\A_SPW_TOP|rx_data|wr_ptr [4] & \A_SPW_TOP|rx_data|mem[53][6]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [2] & ( !\A_SPW_TOP|rx_data|mem[37][6]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|mem[33][6]~q 
// ))) # (\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[49][6]~q )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[49][6]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[33][6]~q ),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datad(!\A_SPW_TOP|rx_data|mem[53][6]~q ),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .dataf(!\A_SPW_TOP|rx_data|mem[37][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux2~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux2~11 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux2~11 .lut_mask = 64'h3535000F3535F0FF;
defparam \A_SPW_TOP|rx_data|Mux2~11 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y3_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector336~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector336~0_combout  = ( \A_SPW_TOP|rx_data|Selector334~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [6])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux2~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector334~0_combout  & ( \A_SPW_TOP|rx_data|mem[35][6]~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[35][6]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector334~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector336~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector336~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector336~0 .lut_mask = 64'h00FF00FF47474747;
defparam \A_SPW_TOP|rx_data|Selector336~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y3_N38
dffeas \A_SPW_TOP|rx_data|mem[35][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector336~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[35][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[35][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[35][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y3_N39
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector480~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector480~0_combout  = ( \A_SPW_TOP|rx_data|Selector478~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [6])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux2~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector478~0_combout  & ( \A_SPW_TOP|rx_data|mem[51][6]~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[51][6]~q ),
        .datad(!\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector478~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector480~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector480~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector480~0 .lut_mask = 64'h0F0F0F0F44774477;
defparam \A_SPW_TOP|rx_data|Selector480~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y3_N44
dffeas \A_SPW_TOP|rx_data|mem[51][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector480~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[51][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[51][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[51][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y3_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector372~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector372~0_combout  = ( \A_SPW_TOP|rx_data|Selector370~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [6])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux2~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector370~0_combout  & ( \A_SPW_TOP|rx_data|mem[39][6]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .datac(!\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[39][6]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector370~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector372~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector372~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector372~0 .lut_mask = 64'h00FF00FF27272727;
defparam \A_SPW_TOP|rx_data|Selector372~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y3_N27
cyclonev_lcell_comb \A_SPW_TOP|rx_data|mem[39][6]~feeder (
// Equation(s):
// \A_SPW_TOP|rx_data|mem[39][6]~feeder_combout  = ( \A_SPW_TOP|rx_data|Selector372~0_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector372~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|mem[39][6]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[39][6]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|mem[39][6]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|rx_data|mem[39][6]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y3_N29
dffeas \A_SPW_TOP|rx_data|mem[39][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|rx_data|mem[39][6]~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[39][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[39][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[39][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y3_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector516~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector516~0_combout  = ( \A_SPW_TOP|SPW|RX|rx_data_flag [6] & ( \A_SPW_TOP|rx_data|mem[55][6]~q  & ( ((!\A_SPW_TOP|rx_data|Selector514~0_combout ) # (!\A_SPW_TOP|rx_data|state_data_write.00~q )) # (\A_SPW_TOP|rx_data|Mux2~20_combout ) 
// ) ) ) # ( !\A_SPW_TOP|SPW|RX|rx_data_flag [6] & ( \A_SPW_TOP|rx_data|mem[55][6]~q  & ( (!\A_SPW_TOP|rx_data|Selector514~0_combout ) # ((\A_SPW_TOP|rx_data|Mux2~20_combout  & \A_SPW_TOP|rx_data|state_data_write.00~q )) ) ) ) # ( 
// \A_SPW_TOP|SPW|RX|rx_data_flag [6] & ( !\A_SPW_TOP|rx_data|mem[55][6]~q  & ( (\A_SPW_TOP|rx_data|Selector514~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|rx_data|Mux2~20_combout ))) ) ) ) # ( !\A_SPW_TOP|SPW|RX|rx_data_flag [6] 
// & ( !\A_SPW_TOP|rx_data|mem[55][6]~q  & ( (\A_SPW_TOP|rx_data|Mux2~20_combout  & (\A_SPW_TOP|rx_data|Selector514~0_combout  & \A_SPW_TOP|rx_data|state_data_write.00~q )) ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector514~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .dataf(!\A_SPW_TOP|rx_data|mem[55][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector516~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector516~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector516~0 .lut_mask = 64'h00030F03F0F3FFF3;
defparam \A_SPW_TOP|rx_data|Selector516~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y3_N26
dffeas \A_SPW_TOP|rx_data|mem[55][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector516~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[55][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[55][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[55][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y3_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux2~13 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux2~13_combout  = ( \A_SPW_TOP|rx_data|mem[55][6]~q  & ( \A_SPW_TOP|rx_data|wr_ptr [4] & ( (\A_SPW_TOP|rx_data|wr_ptr [2]) # (\A_SPW_TOP|rx_data|mem[51][6]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[55][6]~q  & ( \A_SPW_TOP|rx_data|wr_ptr 
// [4] & ( (\A_SPW_TOP|rx_data|mem[51][6]~q  & !\A_SPW_TOP|rx_data|wr_ptr [2]) ) ) ) # ( \A_SPW_TOP|rx_data|mem[55][6]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [4] & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|mem[35][6]~q )) # 
// (\A_SPW_TOP|rx_data|wr_ptr [2] & ((\A_SPW_TOP|rx_data|mem[39][6]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[55][6]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [4] & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|mem[35][6]~q )) # (\A_SPW_TOP|rx_data|wr_ptr 
// [2] & ((\A_SPW_TOP|rx_data|mem[39][6]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[35][6]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[51][6]~q ),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datad(!\A_SPW_TOP|rx_data|mem[39][6]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[55][6]~q ),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux2~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux2~13 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux2~13 .lut_mask = 64'h505F505F30303F3F;
defparam \A_SPW_TOP|rx_data|Mux2~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y3_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux2~14 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux2~14_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [1] & ( \A_SPW_TOP|rx_data|Mux2~13_combout  & ( (\A_SPW_TOP|rx_data|wr_ptr [0]) # (\A_SPW_TOP|rx_data|Mux2~12_combout ) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [1] & ( 
// \A_SPW_TOP|rx_data|Mux2~13_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|Mux2~10_combout )) # (\A_SPW_TOP|rx_data|wr_ptr [0] & ((\A_SPW_TOP|rx_data|Mux2~11_combout ))) ) ) ) # ( \A_SPW_TOP|rx_data|wr_ptr [1] & ( 
// !\A_SPW_TOP|rx_data|Mux2~13_combout  & ( (\A_SPW_TOP|rx_data|Mux2~12_combout  & !\A_SPW_TOP|rx_data|wr_ptr [0]) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [1] & ( !\A_SPW_TOP|rx_data|Mux2~13_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & 
// (\A_SPW_TOP|rx_data|Mux2~10_combout )) # (\A_SPW_TOP|rx_data|wr_ptr [0] & ((\A_SPW_TOP|rx_data|Mux2~11_combout ))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux2~12_combout ),
        .datab(!\A_SPW_TOP|rx_data|Mux2~10_combout ),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datad(!\A_SPW_TOP|rx_data|Mux2~11_combout ),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .dataf(!\A_SPW_TOP|rx_data|Mux2~13_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux2~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux2~14 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux2~14 .lut_mask = 64'h303F5050303F5F5F;
defparam \A_SPW_TOP|rx_data|Mux2~14 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y3_N57
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector111~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector111~0_combout  = ( \A_SPW_TOP|rx_data|mem[10][6]~q  & ( (!\A_SPW_TOP|rx_data|Selector109~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [6])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux2~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[10][6]~q  & ( (\A_SPW_TOP|rx_data|Selector109~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [6])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux2~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .datac(!\A_SPW_TOP|rx_data|Selector109~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[10][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector111~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector111~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector111~0 .lut_mask = 64'h02070207F2F7F2F7;
defparam \A_SPW_TOP|rx_data|Selector111~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y3_N35
dffeas \A_SPW_TOP|rx_data|mem[10][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector111~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[10][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[10][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[10][6] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y3_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector156~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector156~0_combout  = ( \A_SPW_TOP|rx_data|Selector154~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [6])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux2~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector154~0_combout  & ( \A_SPW_TOP|rx_data|mem[15][6]~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .datab(!\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|mem[15][6]~q ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector154~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector156~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector156~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector156~0 .lut_mask = 64'h0F0F0F0F55335533;
defparam \A_SPW_TOP|rx_data|Selector156~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y3_N32
dffeas \A_SPW_TOP|rx_data|mem[15][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector156~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[15][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[15][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[15][6] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y3_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector120~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector120~0_combout  = ( \A_SPW_TOP|rx_data|Selector118~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [6])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux2~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector118~0_combout  & ( \A_SPW_TOP|rx_data|mem[11][6]~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .datab(!\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|mem[11][6]~q ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector118~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector120~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector120~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector120~0 .lut_mask = 64'h0F0F0F0F55335533;
defparam \A_SPW_TOP|rx_data|Selector120~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y3_N50
dffeas \A_SPW_TOP|rx_data|mem[11][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector120~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[11][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[11][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[11][6] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y3_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector147~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector147~0_combout  = ( \A_SPW_TOP|rx_data|Selector145~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [6])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux2~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector145~0_combout  & ( \A_SPW_TOP|rx_data|mem[14][6]~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .datab(!\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|mem[14][6]~q ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector145~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector147~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector147~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector147~0 .lut_mask = 64'h0F0F0F0F55335533;
defparam \A_SPW_TOP|rx_data|Selector147~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y3_N11
dffeas \A_SPW_TOP|rx_data|mem[14][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector147~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[14][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[14][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[14][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y3_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux2~7 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux2~7_combout  = ( \A_SPW_TOP|rx_data|mem[14][6]~q  & ( \A_SPW_TOP|rx_data|wr_ptr [0] & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & ((\A_SPW_TOP|rx_data|mem[11][6]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|mem[15][6]~q )) ) 
// ) ) # ( !\A_SPW_TOP|rx_data|mem[14][6]~q  & ( \A_SPW_TOP|rx_data|wr_ptr [0] & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & ((\A_SPW_TOP|rx_data|mem[11][6]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|mem[15][6]~q )) ) ) ) # ( 
// \A_SPW_TOP|rx_data|mem[14][6]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [0] & ( (\A_SPW_TOP|rx_data|wr_ptr [2]) # (\A_SPW_TOP|rx_data|mem[10][6]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[14][6]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [0] & ( 
// (\A_SPW_TOP|rx_data|mem[10][6]~q  & !\A_SPW_TOP|rx_data|wr_ptr [2]) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[10][6]~q ),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datac(!\A_SPW_TOP|rx_data|mem[15][6]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[11][6]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[14][6]~q ),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux2~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux2~7 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux2~7 .lut_mask = 64'h4444777703CF03CF;
defparam \A_SPW_TOP|rx_data|Mux2~7 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y3_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector300~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector300~0_combout  = ( \A_SPW_TOP|rx_data|Mux2~20_combout  & ( (!\A_SPW_TOP|rx_data|Selector298~0_combout  & (((\A_SPW_TOP|rx_data|mem[31][6]~q )))) # (\A_SPW_TOP|rx_data|Selector298~0_combout  & (((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [6])) # (\A_SPW_TOP|rx_data|state_data_write.00~q ))) ) ) # ( !\A_SPW_TOP|rx_data|Mux2~20_combout  & ( (!\A_SPW_TOP|rx_data|Selector298~0_combout  & (((\A_SPW_TOP|rx_data|mem[31][6]~q )))) # (\A_SPW_TOP|rx_data|Selector298~0_combout  & 
// (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [6]))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .datac(!\A_SPW_TOP|rx_data|Selector298~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[31][6]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector300~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector300~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector300~0 .lut_mask = 64'h02F202F207F707F7;
defparam \A_SPW_TOP|rx_data|Selector300~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y3_N5
dffeas \A_SPW_TOP|rx_data|mem[31][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector300~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[31][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[31][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[31][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y3_N21
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector264~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector264~0_combout  = ( \A_SPW_TOP|rx_data|Mux2~20_combout  & ( (!\A_SPW_TOP|rx_data|Selector262~0_combout  & (((\A_SPW_TOP|rx_data|mem[27][6]~q )))) # (\A_SPW_TOP|rx_data|Selector262~0_combout  & (((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [6])) # (\A_SPW_TOP|rx_data|state_data_write.00~q ))) ) ) # ( !\A_SPW_TOP|rx_data|Mux2~20_combout  & ( (!\A_SPW_TOP|rx_data|Selector262~0_combout  & (((\A_SPW_TOP|rx_data|mem[27][6]~q )))) # (\A_SPW_TOP|rx_data|Selector262~0_combout  & 
// (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [6]))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .datac(!\A_SPW_TOP|rx_data|Selector262~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[27][6]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector264~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector264~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector264~0 .lut_mask = 64'h02F202F207F707F7;
defparam \A_SPW_TOP|rx_data|Selector264~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y3_N47
dffeas \A_SPW_TOP|rx_data|mem[27][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector264~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[27][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[27][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[27][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y3_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector255~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector255~0_combout  = ( \A_SPW_TOP|rx_data|mem[26][6]~q  & ( (!\A_SPW_TOP|rx_data|Selector253~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [6])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux2~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[26][6]~q  & ( (\A_SPW_TOP|rx_data|Selector253~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [6])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux2~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .datac(!\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .datad(!\A_SPW_TOP|rx_data|Selector253~0_combout ),
        .datae(!\A_SPW_TOP|rx_data|mem[26][6]~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector255~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector255~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector255~0 .lut_mask = 64'h0027FF270027FF27;
defparam \A_SPW_TOP|rx_data|Selector255~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y3_N59
dffeas \A_SPW_TOP|rx_data|mem[26][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector255~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[26][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[26][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[26][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y3_N39
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector291~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector291~0_combout  = ( \A_SPW_TOP|rx_data|mem[30][6]~q  & ( (!\A_SPW_TOP|rx_data|Selector289~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [6]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux2~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[30][6]~q  & ( (\A_SPW_TOP|rx_data|Selector289~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [6]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux2~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|Selector289~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[30][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector291~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector291~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector291~0 .lut_mask = 64'h00350035FF35FF35;
defparam \A_SPW_TOP|rx_data|Selector291~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y3_N35
dffeas \A_SPW_TOP|rx_data|mem[30][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector291~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[30][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[30][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[30][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y3_N9
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux2~8 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux2~8_combout  = ( \A_SPW_TOP|rx_data|mem[26][6]~q  & ( \A_SPW_TOP|rx_data|mem[30][6]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [0]) # ((!\A_SPW_TOP|rx_data|wr_ptr [2] & ((\A_SPW_TOP|rx_data|mem[27][6]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [2] & 
// (\A_SPW_TOP|rx_data|mem[31][6]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[26][6]~q  & ( \A_SPW_TOP|rx_data|mem[30][6]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & (((\A_SPW_TOP|rx_data|mem[27][6]~q  & \A_SPW_TOP|rx_data|wr_ptr [0])))) # 
// (\A_SPW_TOP|rx_data|wr_ptr [2] & (((!\A_SPW_TOP|rx_data|wr_ptr [0])) # (\A_SPW_TOP|rx_data|mem[31][6]~q ))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[26][6]~q  & ( !\A_SPW_TOP|rx_data|mem[30][6]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & 
// (((!\A_SPW_TOP|rx_data|wr_ptr [0]) # (\A_SPW_TOP|rx_data|mem[27][6]~q )))) # (\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|mem[31][6]~q  & ((\A_SPW_TOP|rx_data|wr_ptr [0])))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[26][6]~q  & ( 
// !\A_SPW_TOP|rx_data|mem[30][6]~q  & ( (\A_SPW_TOP|rx_data|wr_ptr [0] & ((!\A_SPW_TOP|rx_data|wr_ptr [2] & ((\A_SPW_TOP|rx_data|mem[27][6]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|mem[31][6]~q )))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[31][6]~q ),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datac(!\A_SPW_TOP|rx_data|mem[27][6]~q ),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datae(!\A_SPW_TOP|rx_data|mem[26][6]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[30][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux2~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux2~8 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux2~8 .lut_mask = 64'h001DCC1D331DFF1D;
defparam \A_SPW_TOP|rx_data|Mux2~8 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y3_N51
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector273~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector273~0_combout  = ( \A_SPW_TOP|rx_data|Selector271~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [6]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux2~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector271~0_combout  & ( \A_SPW_TOP|rx_data|mem[28][6]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[28][6]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector271~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector273~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector273~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector273~0 .lut_mask = 64'h00FF00FF35353535;
defparam \A_SPW_TOP|rx_data|Selector273~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y3_N29
dffeas \A_SPW_TOP|rx_data|mem[28][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector273~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[28][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[28][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[28][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y3_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector237~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector237~0_combout  = ( \A_SPW_TOP|rx_data|mem[24][6]~q  & ( (!\A_SPW_TOP|rx_data|Selector235~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [6]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux2~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[24][6]~q  & ( (\A_SPW_TOP|rx_data|Selector235~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [6]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux2~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .datac(!\A_SPW_TOP|rx_data|Selector235~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[24][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector237~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector237~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector237~0 .lut_mask = 64'h03050305F3F5F3F5;
defparam \A_SPW_TOP|rx_data|Selector237~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y3_N17
dffeas \A_SPW_TOP|rx_data|mem[24][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector237~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[24][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[24][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[24][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y3_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector246~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector246~0_combout  = ( \A_SPW_TOP|rx_data|Selector244~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [6])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux2~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector244~0_combout  & ( \A_SPW_TOP|rx_data|mem[25][6]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .datac(!\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[25][6]~q ),
        .datae(!\A_SPW_TOP|rx_data|Selector244~0_combout ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector246~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector246~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector246~0 .lut_mask = 64'h00FF272700FF2727;
defparam \A_SPW_TOP|rx_data|Selector246~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y3_N8
dffeas \A_SPW_TOP|rx_data|mem[25][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector246~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[25][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[25][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[25][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y3_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux2~6 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux2~6_combout  = ( \A_SPW_TOP|rx_data|mem[29][6]~q  & ( \A_SPW_TOP|rx_data|mem[25][6]~q  & ( ((!\A_SPW_TOP|rx_data|wr_ptr [2] & ((\A_SPW_TOP|rx_data|mem[24][6]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|mem[28][6]~q 
// ))) # (\A_SPW_TOP|rx_data|wr_ptr [0]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[29][6]~q  & ( \A_SPW_TOP|rx_data|mem[25][6]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & (((\A_SPW_TOP|rx_data|mem[24][6]~q ) # (\A_SPW_TOP|rx_data|wr_ptr [0])))) # 
// (\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|mem[28][6]~q  & (!\A_SPW_TOP|rx_data|wr_ptr [0]))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[29][6]~q  & ( !\A_SPW_TOP|rx_data|mem[25][6]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & (((!\A_SPW_TOP|rx_data|wr_ptr 
// [0] & \A_SPW_TOP|rx_data|mem[24][6]~q )))) # (\A_SPW_TOP|rx_data|wr_ptr [2] & (((\A_SPW_TOP|rx_data|wr_ptr [0])) # (\A_SPW_TOP|rx_data|mem[28][6]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[29][6]~q  & ( !\A_SPW_TOP|rx_data|mem[25][6]~q  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [0] & ((!\A_SPW_TOP|rx_data|wr_ptr [2] & ((\A_SPW_TOP|rx_data|mem[24][6]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|mem[28][6]~q )))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[28][6]~q ),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datad(!\A_SPW_TOP|rx_data|mem[24][6]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[29][6]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[25][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux2~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux2~6 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux2~6 .lut_mask = 64'h10D013D31CDC1FDF;
defparam \A_SPW_TOP|rx_data|Mux2~6 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y3_N27
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector138~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector138~0_combout  = ( \A_SPW_TOP|rx_data|mem[13][6]~q  & ( (!\A_SPW_TOP|rx_data|Selector136~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [6])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux2~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[13][6]~q  & ( (\A_SPW_TOP|rx_data|Selector136~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [6])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux2~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .datab(!\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|Selector136~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[13][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector138~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector138~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector138~0 .lut_mask = 64'h00530053FF53FF53;
defparam \A_SPW_TOP|rx_data|Selector138~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y3_N8
dffeas \A_SPW_TOP|rx_data|mem[13][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector138~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[13][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[13][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[13][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y3_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector129~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector129~0_combout  = ( \A_SPW_TOP|rx_data|Selector127~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [6])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux2~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector127~0_combout  & ( \A_SPW_TOP|rx_data|mem[12][6]~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .datab(!\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[12][6]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector127~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector129~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector129~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector129~0 .lut_mask = 64'h00FF00FF53535353;
defparam \A_SPW_TOP|rx_data|Selector129~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y3_N47
dffeas \A_SPW_TOP|rx_data|mem[12][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector129~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[12][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[12][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[12][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y3_N15
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector93~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector93~0_combout  = ( \A_SPW_TOP|SPW|RX|rx_data_flag [6] & ( (!\A_SPW_TOP|rx_data|Selector91~0_combout  & (((\A_SPW_TOP|rx_data|mem[8][6]~q )))) # (\A_SPW_TOP|rx_data|Selector91~0_combout  & 
// (((!\A_SPW_TOP|rx_data|state_data_write.00~q )) # (\A_SPW_TOP|rx_data|Mux2~20_combout ))) ) ) # ( !\A_SPW_TOP|SPW|RX|rx_data_flag [6] & ( (!\A_SPW_TOP|rx_data|Selector91~0_combout  & (((\A_SPW_TOP|rx_data|mem[8][6]~q )))) # 
// (\A_SPW_TOP|rx_data|Selector91~0_combout  & (\A_SPW_TOP|rx_data|Mux2~20_combout  & ((\A_SPW_TOP|rx_data|state_data_write.00~q )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Selector91~0_combout ),
        .datab(!\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|mem[8][6]~q ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector93~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector93~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector93~0 .lut_mask = 64'h0A1B5F1B0A1B5F1B;
defparam \A_SPW_TOP|rx_data|Selector93~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y3_N14
dffeas \A_SPW_TOP|rx_data|mem[8][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector93~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[8][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[8][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[8][6] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y3_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector102~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector102~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector100~0_combout  & ((\A_SPW_TOP|rx_data|mem[9][6]~q ))) # (\A_SPW_TOP|rx_data|Selector100~0_combout  & 
// (\A_SPW_TOP|rx_data|Mux2~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector100~0_combout  & ((\A_SPW_TOP|rx_data|mem[9][6]~q ))) # (\A_SPW_TOP|rx_data|Selector100~0_combout  & (\A_SPW_TOP|SPW|RX|rx_data_flag 
// [6])) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .datab(!\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector100~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[9][6]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector102~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector102~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector102~0 .lut_mask = 64'h05F505F503F303F3;
defparam \A_SPW_TOP|rx_data|Selector102~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y3_N38
dffeas \A_SPW_TOP|rx_data|mem[9][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector102~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[9][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[9][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[9][6] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y3_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux2~5 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux2~5_combout  = ( \A_SPW_TOP|rx_data|mem[9][6]~q  & ( \A_SPW_TOP|rx_data|wr_ptr [0] & ( (!\A_SPW_TOP|rx_data|wr_ptr [2]) # (\A_SPW_TOP|rx_data|mem[13][6]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[9][6]~q  & ( \A_SPW_TOP|rx_data|wr_ptr [0] 
// & ( (\A_SPW_TOP|rx_data|wr_ptr [2] & \A_SPW_TOP|rx_data|mem[13][6]~q ) ) ) ) # ( \A_SPW_TOP|rx_data|mem[9][6]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [0] & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & ((\A_SPW_TOP|rx_data|mem[8][6]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [2] 
// & (\A_SPW_TOP|rx_data|mem[12][6]~q )) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[9][6]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [0] & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & ((\A_SPW_TOP|rx_data|mem[8][6]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [2] & 
// (\A_SPW_TOP|rx_data|mem[12][6]~q )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datab(!\A_SPW_TOP|rx_data|mem[13][6]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[12][6]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[8][6]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[9][6]~q ),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux2~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux2~5 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux2~5 .lut_mask = 64'h05AF05AF1111BBBB;
defparam \A_SPW_TOP|rx_data|Mux2~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y3_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux2~9 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux2~9_combout  = ( \A_SPW_TOP|rx_data|Mux2~5_combout  & ( \A_SPW_TOP|rx_data|wr_ptr [4] & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & ((\A_SPW_TOP|rx_data|Mux2~6_combout ))) # (\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|Mux2~8_combout 
// )) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux2~5_combout  & ( \A_SPW_TOP|rx_data|wr_ptr [4] & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & ((\A_SPW_TOP|rx_data|Mux2~6_combout ))) # (\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|Mux2~8_combout )) ) ) ) # ( 
// \A_SPW_TOP|rx_data|Mux2~5_combout  & ( !\A_SPW_TOP|rx_data|wr_ptr [4] & ( (!\A_SPW_TOP|rx_data|wr_ptr [1]) # (\A_SPW_TOP|rx_data|Mux2~7_combout ) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux2~5_combout  & ( !\A_SPW_TOP|rx_data|wr_ptr [4] & ( 
// (\A_SPW_TOP|rx_data|Mux2~7_combout  & \A_SPW_TOP|rx_data|wr_ptr [1]) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux2~7_combout ),
        .datab(!\A_SPW_TOP|rx_data|Mux2~8_combout ),
        .datac(!\A_SPW_TOP|rx_data|Mux2~6_combout ),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datae(!\A_SPW_TOP|rx_data|Mux2~5_combout ),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux2~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux2~9 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux2~9 .lut_mask = 64'h0055FF550F330F33;
defparam \A_SPW_TOP|rx_data|Mux2~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y3_N57
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector48~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector48~0_combout  = ( \A_SPW_TOP|rx_data|mem[3][6]~q  & ( (!\A_SPW_TOP|rx_data|Selector46~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [6]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux2~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[3][6]~q  & ( (\A_SPW_TOP|rx_data|Selector46~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [6]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux2~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector46~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[3][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector48~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector48~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector48~0 .lut_mask = 64'h010B010BF1FBF1FB;
defparam \A_SPW_TOP|rx_data|Selector48~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y3_N17
dffeas \A_SPW_TOP|rx_data|mem[3][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector48~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[3][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[3][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[3][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y3_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector228~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector228~0_combout  = ( \A_SPW_TOP|SPW|RX|rx_data_flag [6] & ( (!\A_SPW_TOP|rx_data|Selector226~0_combout  & (((\A_SPW_TOP|rx_data|mem[23][6]~q )))) # (\A_SPW_TOP|rx_data|Selector226~0_combout  & 
// (((!\A_SPW_TOP|rx_data|state_data_write.00~q )) # (\A_SPW_TOP|rx_data|Mux2~20_combout ))) ) ) # ( !\A_SPW_TOP|SPW|RX|rx_data_flag [6] & ( (!\A_SPW_TOP|rx_data|Selector226~0_combout  & (((\A_SPW_TOP|rx_data|mem[23][6]~q )))) # 
// (\A_SPW_TOP|rx_data|Selector226~0_combout  & (\A_SPW_TOP|rx_data|Mux2~20_combout  & (\A_SPW_TOP|rx_data|state_data_write.00~q ))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Selector226~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[23][6]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector228~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector228~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector228~0 .lut_mask = 64'h01F101F10DFD0DFD;
defparam \A_SPW_TOP|rx_data|Selector228~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y3_N41
dffeas \A_SPW_TOP|rx_data|mem[23][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector228~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[23][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[23][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[23][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y3_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector192~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector192~0_combout  = ( \A_SPW_TOP|SPW|RX|rx_data_flag [6] & ( \A_SPW_TOP|rx_data|Selector190~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|rx_data|Mux2~20_combout ) ) ) ) # ( 
// !\A_SPW_TOP|SPW|RX|rx_data_flag [6] & ( \A_SPW_TOP|rx_data|Selector190~0_combout  & ( (\A_SPW_TOP|rx_data|state_data_write.00~q  & \A_SPW_TOP|rx_data|Mux2~20_combout ) ) ) ) # ( \A_SPW_TOP|SPW|RX|rx_data_flag [6] & ( 
// !\A_SPW_TOP|rx_data|Selector190~0_combout  & ( \A_SPW_TOP|rx_data|mem[19][6]~q  ) ) ) # ( !\A_SPW_TOP|SPW|RX|rx_data_flag [6] & ( !\A_SPW_TOP|rx_data|Selector190~0_combout  & ( \A_SPW_TOP|rx_data|mem[19][6]~q  ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[19][6]~q ),
        .datad(!\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .datae(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .dataf(!\A_SPW_TOP|rx_data|Selector190~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector192~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector192~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector192~0 .lut_mask = 64'h0F0F0F0F0033CCFF;
defparam \A_SPW_TOP|rx_data|Selector192~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y3_N11
dffeas \A_SPW_TOP|rx_data|mem[19][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector192~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[19][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[19][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[19][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y3_N27
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector84~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector84~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( \A_SPW_TOP|rx_data|mem[7][6]~q  & ( (!\A_SPW_TOP|rx_data|Selector82~0_combout ) # (\A_SPW_TOP|rx_data|Mux2~20_combout ) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( \A_SPW_TOP|rx_data|mem[7][6]~q  & ( (!\A_SPW_TOP|rx_data|Selector82~0_combout ) # (\A_SPW_TOP|SPW|RX|rx_data_flag [6]) ) ) ) # ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( !\A_SPW_TOP|rx_data|mem[7][6]~q  
// & ( (\A_SPW_TOP|rx_data|Selector82~0_combout  & \A_SPW_TOP|rx_data|Mux2~20_combout ) ) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( !\A_SPW_TOP|rx_data|mem[7][6]~q  & ( (\A_SPW_TOP|rx_data|Selector82~0_combout  & \A_SPW_TOP|SPW|RX|rx_data_flag 
// [6]) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Selector82~0_combout ),
        .datab(!\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .datac(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .datad(gnd),
        .datae(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[7][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector84~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector84~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector84~0 .lut_mask = 64'h05051111AFAFBBBB;
defparam \A_SPW_TOP|rx_data|Selector84~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y3_N53
dffeas \A_SPW_TOP|rx_data|mem[7][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector84~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[7][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[7][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[7][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y3_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux2~3 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux2~3_combout  = ( \A_SPW_TOP|rx_data|mem[19][6]~q  & ( \A_SPW_TOP|rx_data|mem[7][6]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [4] & (((\A_SPW_TOP|rx_data|wr_ptr [2])) # (\A_SPW_TOP|rx_data|mem[3][6]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [4] & 
// (((!\A_SPW_TOP|rx_data|wr_ptr [2]) # (\A_SPW_TOP|rx_data|mem[23][6]~q )))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[19][6]~q  & ( \A_SPW_TOP|rx_data|mem[7][6]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [4] & (((\A_SPW_TOP|rx_data|wr_ptr [2])) # 
// (\A_SPW_TOP|rx_data|mem[3][6]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [4] & (((\A_SPW_TOP|rx_data|mem[23][6]~q  & \A_SPW_TOP|rx_data|wr_ptr [2])))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[19][6]~q  & ( !\A_SPW_TOP|rx_data|mem[7][6]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr 
// [4] & (\A_SPW_TOP|rx_data|mem[3][6]~q  & ((!\A_SPW_TOP|rx_data|wr_ptr [2])))) # (\A_SPW_TOP|rx_data|wr_ptr [4] & (((!\A_SPW_TOP|rx_data|wr_ptr [2]) # (\A_SPW_TOP|rx_data|mem[23][6]~q )))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[19][6]~q  & ( 
// !\A_SPW_TOP|rx_data|mem[7][6]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[3][6]~q  & ((!\A_SPW_TOP|rx_data|wr_ptr [2])))) # (\A_SPW_TOP|rx_data|wr_ptr [4] & (((\A_SPW_TOP|rx_data|mem[23][6]~q  & \A_SPW_TOP|rx_data|wr_ptr [2])))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[3][6]~q ),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datac(!\A_SPW_TOP|rx_data|mem[23][6]~q ),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datae(!\A_SPW_TOP|rx_data|mem[19][6]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[7][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux2~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux2~3 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux2~3 .lut_mask = 64'h4403770344CF77CF;
defparam \A_SPW_TOP|rx_data|Mux2~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y3_N27
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector66~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector66~0_combout  = ( \A_SPW_TOP|rx_data|Selector64~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [6]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux2~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector64~0_combout  & ( \A_SPW_TOP|rx_data|mem[5][6]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .datac(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .datad(!\A_SPW_TOP|rx_data|mem[5][6]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector64~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector66~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector66~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector66~0 .lut_mask = 64'h00FF00FF1B1B1B1B;
defparam \A_SPW_TOP|rx_data|Selector66~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y3_N23
dffeas \A_SPW_TOP|rx_data|mem[5][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector66~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[5][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[5][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[5][6] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y3_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector30~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector30~0_combout  = ( \A_SPW_TOP|rx_data|Selector28~0_combout  & ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( \A_SPW_TOP|rx_data|Mux2~20_combout  ) ) ) # ( !\A_SPW_TOP|rx_data|Selector28~0_combout  & ( 
// \A_SPW_TOP|rx_data|state_data_write.00~q  & ( \A_SPW_TOP|rx_data|mem[1][6]~q  ) ) ) # ( \A_SPW_TOP|rx_data|Selector28~0_combout  & ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( \A_SPW_TOP|SPW|RX|rx_data_flag [6] ) ) ) # ( 
// !\A_SPW_TOP|rx_data|Selector28~0_combout  & ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( \A_SPW_TOP|rx_data|mem[1][6]~q  ) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .datab(gnd),
        .datac(!\A_SPW_TOP|rx_data|mem[1][6]~q ),
        .datad(!\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .datae(!\A_SPW_TOP|rx_data|Selector28~0_combout ),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector30~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector30~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector30~0 .lut_mask = 64'h0F0F55550F0F00FF;
defparam \A_SPW_TOP|rx_data|Selector30~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y3_N35
dffeas \A_SPW_TOP|rx_data|mem[1][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector30~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[1][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[1][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[1][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y3_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector210~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector210~0_combout  = ( \A_SPW_TOP|rx_data|mem[21][6]~q  & ( (!\A_SPW_TOP|rx_data|Selector208~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [6]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux2~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[21][6]~q  & ( (\A_SPW_TOP|rx_data|Selector208~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [6]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux2~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector208~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[21][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector210~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector210~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector210~0 .lut_mask = 64'h010B010BF1FBF1FB;
defparam \A_SPW_TOP|rx_data|Selector210~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y3_N14
dffeas \A_SPW_TOP|rx_data|mem[21][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector210~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[21][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[21][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[21][6] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y3_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector174~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector174~0_combout  = ( \A_SPW_TOP|rx_data|mem[17][6]~q  & ( (!\A_SPW_TOP|rx_data|Selector172~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [6])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux2~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[17][6]~q  & ( (\A_SPW_TOP|rx_data|Selector172~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [6])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux2~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .datab(!\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|Selector172~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[17][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector174~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector174~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector174~0 .lut_mask = 64'h00530053FF53FF53;
defparam \A_SPW_TOP|rx_data|Selector174~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y3_N35
dffeas \A_SPW_TOP|rx_data|mem[17][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector174~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[17][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[17][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[17][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y3_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux2~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux2~1_combout  = ( \A_SPW_TOP|rx_data|mem[21][6]~q  & ( \A_SPW_TOP|rx_data|mem[17][6]~q  & ( ((!\A_SPW_TOP|rx_data|wr_ptr [2] & ((\A_SPW_TOP|rx_data|mem[1][6]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|mem[5][6]~q ))) 
// # (\A_SPW_TOP|rx_data|wr_ptr [4]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[21][6]~q  & ( \A_SPW_TOP|rx_data|mem[17][6]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & (((\A_SPW_TOP|rx_data|mem[1][6]~q ) # (\A_SPW_TOP|rx_data|wr_ptr [4])))) # (\A_SPW_TOP|rx_data|wr_ptr 
// [2] & (\A_SPW_TOP|rx_data|mem[5][6]~q  & (!\A_SPW_TOP|rx_data|wr_ptr [4]))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[21][6]~q  & ( !\A_SPW_TOP|rx_data|mem[17][6]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & (((!\A_SPW_TOP|rx_data|wr_ptr [4] & 
// \A_SPW_TOP|rx_data|mem[1][6]~q )))) # (\A_SPW_TOP|rx_data|wr_ptr [2] & (((\A_SPW_TOP|rx_data|wr_ptr [4])) # (\A_SPW_TOP|rx_data|mem[5][6]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[21][6]~q  & ( !\A_SPW_TOP|rx_data|mem[17][6]~q  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [4] & ((!\A_SPW_TOP|rx_data|wr_ptr [2] & ((\A_SPW_TOP|rx_data|mem[1][6]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|mem[5][6]~q )))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[5][6]~q ),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datad(!\A_SPW_TOP|rx_data|mem[1][6]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[21][6]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[17][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux2~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux2~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux2~1 .lut_mask = 64'h10D013D31CDC1FDF;
defparam \A_SPW_TOP|rx_data|Mux2~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y3_N45
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector21~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector21~0_combout  = ( \A_SPW_TOP|rx_data|mem[0][6]~q  & ( (!\A_SPW_TOP|rx_data|Selector19~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [6])) # (\A_SPW_TOP|rx_data|state_data_write.00~q 
//  & ((\A_SPW_TOP|rx_data|Mux2~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[0][6]~q  & ( (\A_SPW_TOP|rx_data|Selector19~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [6])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux2~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .datac(!\A_SPW_TOP|rx_data|Selector19~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[0][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector21~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector21~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector21~0 .lut_mask = 64'h02070207F2F7F2F7;
defparam \A_SPW_TOP|rx_data|Selector21~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y3_N26
dffeas \A_SPW_TOP|rx_data|mem[0][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector21~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[0][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[0][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[0][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y3_N45
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector201~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector201~0_combout  = ( \A_SPW_TOP|rx_data|mem[20][6]~q  & ( (!\A_SPW_TOP|rx_data|Selector199~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [6]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux2~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[20][6]~q  & ( (\A_SPW_TOP|rx_data|Selector199~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [6]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux2~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector199~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[20][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector201~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector201~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector201~0 .lut_mask = 64'h010B010BF1FBF1FB;
defparam \A_SPW_TOP|rx_data|Selector201~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y3_N50
dffeas \A_SPW_TOP|rx_data|mem[20][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector201~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[20][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[20][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[20][6] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y3_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector57~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector57~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector55~0_combout  & ((\A_SPW_TOP|rx_data|mem[4][6]~q ))) # (\A_SPW_TOP|rx_data|Selector55~0_combout  & (\A_SPW_TOP|rx_data|Mux2~20_combout 
// )) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector55~0_combout  & ((\A_SPW_TOP|rx_data|mem[4][6]~q ))) # (\A_SPW_TOP|rx_data|Selector55~0_combout  & (\A_SPW_TOP|SPW|RX|rx_data_flag [6])) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .datab(!\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|mem[4][6]~q ),
        .datad(!\A_SPW_TOP|rx_data|Selector55~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector57~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector57~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector57~0 .lut_mask = 64'h0F550F550F330F33;
defparam \A_SPW_TOP|rx_data|Selector57~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y3_N11
dffeas \A_SPW_TOP|rx_data|mem[4][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector57~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[4][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[4][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[4][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y3_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector165~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector165~0_combout  = ( \A_SPW_TOP|rx_data|mem[16][6]~q  & ( (!\A_SPW_TOP|rx_data|Selector163~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [6])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux2~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[16][6]~q  & ( (\A_SPW_TOP|rx_data|Selector163~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [6])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux2~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .datab(!\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|Selector163~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[16][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector165~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector165~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector165~0 .lut_mask = 64'h00530053FF53FF53;
defparam \A_SPW_TOP|rx_data|Selector165~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y3_N32
dffeas \A_SPW_TOP|rx_data|mem[16][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector165~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[16][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[16][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[16][6] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y3_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux2~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux2~0_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [2] & ( \A_SPW_TOP|rx_data|mem[16][6]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|mem[4][6]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[20][6]~q )) ) ) 
// ) # ( !\A_SPW_TOP|rx_data|wr_ptr [2] & ( \A_SPW_TOP|rx_data|mem[16][6]~q  & ( (\A_SPW_TOP|rx_data|mem[0][6]~q ) # (\A_SPW_TOP|rx_data|wr_ptr [4]) ) ) ) # ( \A_SPW_TOP|rx_data|wr_ptr [2] & ( !\A_SPW_TOP|rx_data|mem[16][6]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr 
// [4] & ((\A_SPW_TOP|rx_data|mem[4][6]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[20][6]~q )) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [2] & ( !\A_SPW_TOP|rx_data|mem[16][6]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [4] & 
// \A_SPW_TOP|rx_data|mem[0][6]~q ) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datab(!\A_SPW_TOP|rx_data|mem[0][6]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[20][6]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[4][6]~q ),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .dataf(!\A_SPW_TOP|rx_data|mem[16][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux2~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux2~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux2~0 .lut_mask = 64'h222205AF777705AF;
defparam \A_SPW_TOP|rx_data|Mux2~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y3_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector75~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector75~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( \A_SPW_TOP|rx_data|mem[6][6]~q  & ( (!\A_SPW_TOP|rx_data|Selector73~0_combout ) # (\A_SPW_TOP|rx_data|Mux2~20_combout ) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( \A_SPW_TOP|rx_data|mem[6][6]~q  & ( (!\A_SPW_TOP|rx_data|Selector73~0_combout ) # (\A_SPW_TOP|SPW|RX|rx_data_flag [6]) ) ) ) # ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( !\A_SPW_TOP|rx_data|mem[6][6]~q  
// & ( (\A_SPW_TOP|rx_data|Mux2~20_combout  & \A_SPW_TOP|rx_data|Selector73~0_combout ) ) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( !\A_SPW_TOP|rx_data|mem[6][6]~q  & ( (\A_SPW_TOP|rx_data|Selector73~0_combout  & \A_SPW_TOP|SPW|RX|rx_data_flag 
// [6]) ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector73~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .datae(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[6][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector75~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector75~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector75~0 .lut_mask = 64'h000F0303F0FFF3F3;
defparam \A_SPW_TOP|rx_data|Selector75~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y3_N35
dffeas \A_SPW_TOP|rx_data|mem[6][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector75~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[6][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[6][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[6][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y3_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector219~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector219~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector217~0_combout  & (\A_SPW_TOP|rx_data|mem[22][6]~q )) # (\A_SPW_TOP|rx_data|Selector217~0_combout  & 
// ((\A_SPW_TOP|rx_data|Mux2~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector217~0_combout  & ((\A_SPW_TOP|rx_data|mem[22][6]~q ))) # (\A_SPW_TOP|rx_data|Selector217~0_combout  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [6])) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .datab(!\A_SPW_TOP|rx_data|mem[22][6]~q ),
        .datac(!\A_SPW_TOP|rx_data|Selector217~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector219~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector219~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector219~0 .lut_mask = 64'h35353535303F303F;
defparam \A_SPW_TOP|rx_data|Selector219~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y3_N14
dffeas \A_SPW_TOP|rx_data|mem[22][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector219~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[22][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[22][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[22][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y3_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector39~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector39~0_combout  = ( \A_SPW_TOP|rx_data|mem[2][6]~q  & ( (!\A_SPW_TOP|rx_data|Selector37~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [6]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux2~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[2][6]~q  & ( (\A_SPW_TOP|rx_data|Selector37~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [6]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux2~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .datac(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .datad(!\A_SPW_TOP|rx_data|Selector37~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[2][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector39~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector39~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector39~0 .lut_mask = 64'h001B001BFF1BFF1B;
defparam \A_SPW_TOP|rx_data|Selector39~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y3_N41
dffeas \A_SPW_TOP|rx_data|mem[2][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector39~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[2][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[2][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[2][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y3_N57
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector183~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector183~0_combout  = ( \A_SPW_TOP|rx_data|Selector181~0_combout  & ( \A_SPW_TOP|SPW|RX|rx_data_flag [6] & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|rx_data|Mux2~20_combout ) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|Selector181~0_combout  & ( \A_SPW_TOP|SPW|RX|rx_data_flag [6] & ( \A_SPW_TOP|rx_data|mem[18][6]~q  ) ) ) # ( \A_SPW_TOP|rx_data|Selector181~0_combout  & ( !\A_SPW_TOP|SPW|RX|rx_data_flag [6] & ( (\A_SPW_TOP|rx_data|Mux2~20_combout  & 
// \A_SPW_TOP|rx_data|state_data_write.00~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|Selector181~0_combout  & ( !\A_SPW_TOP|SPW|RX|rx_data_flag [6] & ( \A_SPW_TOP|rx_data|mem[18][6]~q  ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[18][6]~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|rx_data|Selector181~0_combout ),
        .dataf(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector183~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector183~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector183~0 .lut_mask = 64'h555503035555F3F3;
defparam \A_SPW_TOP|rx_data|Selector183~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y3_N17
dffeas \A_SPW_TOP|rx_data|mem[18][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector183~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[18][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[18][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[18][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y3_N51
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux2~2 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux2~2_combout  = ( \A_SPW_TOP|rx_data|mem[18][6]~q  & ( \A_SPW_TOP|rx_data|wr_ptr [2] & ( (!\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[6][6]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|mem[22][6]~q ))) ) ) 
// ) # ( !\A_SPW_TOP|rx_data|mem[18][6]~q  & ( \A_SPW_TOP|rx_data|wr_ptr [2] & ( (!\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[6][6]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|mem[22][6]~q ))) ) ) ) # ( 
// \A_SPW_TOP|rx_data|mem[18][6]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [2] & ( (\A_SPW_TOP|rx_data|mem[2][6]~q ) # (\A_SPW_TOP|rx_data|wr_ptr [4]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[18][6]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [2] & ( (!\A_SPW_TOP|rx_data|wr_ptr [4] 
// & \A_SPW_TOP|rx_data|mem[2][6]~q ) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[6][6]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[22][6]~q ),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datad(!\A_SPW_TOP|rx_data|mem[2][6]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[18][6]~q ),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux2~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux2~2 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux2~2 .lut_mask = 64'h00F00FFF53535353;
defparam \A_SPW_TOP|rx_data|Mux2~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y3_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux2~4 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux2~4_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [1] & ( \A_SPW_TOP|rx_data|Mux2~2_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [0]) # (\A_SPW_TOP|rx_data|Mux2~3_combout ) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [1] & ( 
// \A_SPW_TOP|rx_data|Mux2~2_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & ((\A_SPW_TOP|rx_data|Mux2~0_combout ))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|Mux2~1_combout )) ) ) ) # ( \A_SPW_TOP|rx_data|wr_ptr [1] & ( 
// !\A_SPW_TOP|rx_data|Mux2~2_combout  & ( (\A_SPW_TOP|rx_data|Mux2~3_combout  & \A_SPW_TOP|rx_data|wr_ptr [0]) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [1] & ( !\A_SPW_TOP|rx_data|Mux2~2_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & 
// ((\A_SPW_TOP|rx_data|Mux2~0_combout ))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|Mux2~1_combout )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux2~3_combout ),
        .datab(!\A_SPW_TOP|rx_data|Mux2~1_combout ),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datad(!\A_SPW_TOP|rx_data|Mux2~0_combout ),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .dataf(!\A_SPW_TOP|rx_data|Mux2~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux2~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux2~4 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux2~4 .lut_mask = 64'h03F3050503F3F5F5;
defparam \A_SPW_TOP|rx_data|Mux2~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y3_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector525~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector525~0_combout  = ( \A_SPW_TOP|SPW|RX|rx_data_flag [6] & ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector523~0_combout  & (\A_SPW_TOP|rx_data|mem[56][6]~q )) # 
// (\A_SPW_TOP|rx_data|Selector523~0_combout  & ((\A_SPW_TOP|rx_data|Mux2~20_combout ))) ) ) ) # ( !\A_SPW_TOP|SPW|RX|rx_data_flag [6] & ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector523~0_combout  & 
// (\A_SPW_TOP|rx_data|mem[56][6]~q )) # (\A_SPW_TOP|rx_data|Selector523~0_combout  & ((\A_SPW_TOP|rx_data|Mux2~20_combout ))) ) ) ) # ( \A_SPW_TOP|SPW|RX|rx_data_flag [6] & ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( 
// (\A_SPW_TOP|rx_data|Selector523~0_combout ) # (\A_SPW_TOP|rx_data|mem[56][6]~q ) ) ) ) # ( !\A_SPW_TOP|SPW|RX|rx_data_flag [6] & ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( (\A_SPW_TOP|rx_data|mem[56][6]~q  & !\A_SPW_TOP|rx_data|Selector523~0_combout 
// ) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[56][6]~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector523~0_combout ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector525~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector525~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector525~0 .lut_mask = 64'h50505F5F53535353;
defparam \A_SPW_TOP|rx_data|Selector525~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y3_N5
dffeas \A_SPW_TOP|rx_data|mem[56][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector525~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[56][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[56][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[56][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y3_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector381~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector381~0_combout  = ( \A_SPW_TOP|rx_data|mem[40][6]~q  & ( (!\A_SPW_TOP|rx_data|Selector379~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [6])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux2~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[40][6]~q  & ( (\A_SPW_TOP|rx_data|Selector379~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [6])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux2~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .datac(!\A_SPW_TOP|rx_data|Selector379~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[40][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector381~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector381~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector381~0 .lut_mask = 64'h02070207F2F7F2F7;
defparam \A_SPW_TOP|rx_data|Selector381~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y3_N41
dffeas \A_SPW_TOP|rx_data|mem[40][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector381~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[40][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[40][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[40][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y3_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector399~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector399~0_combout  = ( \A_SPW_TOP|rx_data|Selector397~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [6])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux2~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector397~0_combout  & ( \A_SPW_TOP|rx_data|mem[42][6]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .datac(!\A_SPW_TOP|rx_data|mem[42][6]~q ),
        .datad(!\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector397~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector399~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector399~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector399~0 .lut_mask = 64'h0F0F0F0F22772277;
defparam \A_SPW_TOP|rx_data|Selector399~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y3_N38
dffeas \A_SPW_TOP|rx_data|mem[42][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector399~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[42][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[42][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[42][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y3_N9
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector543~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector543~0_combout  = ( \A_SPW_TOP|rx_data|mem[58][6]~q  & ( (!\A_SPW_TOP|rx_data|Selector541~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [6])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux2~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[58][6]~q  & ( (\A_SPW_TOP|rx_data|Selector541~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [6])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux2~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .datac(!\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .datad(!\A_SPW_TOP|rx_data|Selector541~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[58][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector543~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector543~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector543~0 .lut_mask = 64'h00270027FF27FF27;
defparam \A_SPW_TOP|rx_data|Selector543~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y3_N32
dffeas \A_SPW_TOP|rx_data|mem[58][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector543~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[58][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[58][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[58][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y3_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux2~15 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux2~15_combout  = ( \A_SPW_TOP|rx_data|mem[58][6]~q  & ( \A_SPW_TOP|rx_data|wr_ptr [1] & ( (\A_SPW_TOP|rx_data|wr_ptr [4]) # (\A_SPW_TOP|rx_data|mem[42][6]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[58][6]~q  & ( \A_SPW_TOP|rx_data|wr_ptr 
// [1] & ( (\A_SPW_TOP|rx_data|mem[42][6]~q  & !\A_SPW_TOP|rx_data|wr_ptr [4]) ) ) ) # ( \A_SPW_TOP|rx_data|mem[58][6]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [1] & ( (!\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|mem[40][6]~q ))) # 
// (\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[56][6]~q )) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[58][6]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [1] & ( (!\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|mem[40][6]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr 
// [4] & (\A_SPW_TOP|rx_data|mem[56][6]~q )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[56][6]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[40][6]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[42][6]~q ),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datae(!\A_SPW_TOP|rx_data|mem[58][6]~q ),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux2~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux2~15 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux2~15 .lut_mask = 64'h335533550F000FFF;
defparam \A_SPW_TOP|rx_data|Mux2~15 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y3_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector570~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector570~0_combout  = ( \A_SPW_TOP|rx_data|mem[61][6]~q  & ( (!\A_SPW_TOP|rx_data|Selector568~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [6]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux2~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[61][6]~q  & ( (\A_SPW_TOP|rx_data|Selector568~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [6]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux2~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector568~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[61][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector570~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector570~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector570~0 .lut_mask = 64'h010B010BF1FBF1FB;
defparam \A_SPW_TOP|rx_data|Selector570~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y3_N20
dffeas \A_SPW_TOP|rx_data|mem[61][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector570~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[61][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[61][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[61][6] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y3_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector426~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector426~0_combout  = ( \A_SPW_TOP|rx_data|mem[45][6]~q  & ( (!\A_SPW_TOP|rx_data|Selector424~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [6])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux2~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[45][6]~q  & ( (\A_SPW_TOP|rx_data|Selector424~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [6])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux2~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .datab(!\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector424~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[45][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector426~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector426~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector426~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|rx_data|Selector426~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y3_N17
dffeas \A_SPW_TOP|rx_data|mem[45][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector426~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[45][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[45][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[45][6] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y3_N57
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector444~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector444~0_combout  = ( \A_SPW_TOP|rx_data|mem[47][6]~q  & ( (!\A_SPW_TOP|rx_data|Selector442~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [6])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux2~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[47][6]~q  & ( (\A_SPW_TOP|rx_data|Selector442~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [6])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux2~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .datab(!\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|Selector442~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[47][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector444~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector444~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector444~0 .lut_mask = 64'h00530053FF53FF53;
defparam \A_SPW_TOP|rx_data|Selector444~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y3_N53
dffeas \A_SPW_TOP|rx_data|mem[47][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector444~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[47][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[47][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[47][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y3_N57
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector588~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector588~0_combout  = ( \A_SPW_TOP|rx_data|mem[63][6]~q  & ( (!\A_SPW_TOP|rx_data|Selector586~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [6])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux2~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[63][6]~q  & ( (\A_SPW_TOP|rx_data|Selector586~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [6])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux2~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .datab(!\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector586~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[63][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector588~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector588~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector588~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|rx_data|Selector588~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y3_N53
dffeas \A_SPW_TOP|rx_data|mem[63][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector588~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[63][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[63][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[63][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y3_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux2~18 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux2~18_combout  = ( \A_SPW_TOP|rx_data|mem[47][6]~q  & ( \A_SPW_TOP|rx_data|mem[63][6]~q  & ( ((!\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|mem[45][6]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[61][6]~q 
// ))) # (\A_SPW_TOP|rx_data|wr_ptr [1]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[47][6]~q  & ( \A_SPW_TOP|rx_data|mem[63][6]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & ((!\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|mem[45][6]~q ))) # 
// (\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[61][6]~q )))) # (\A_SPW_TOP|rx_data|wr_ptr [1] & (((\A_SPW_TOP|rx_data|wr_ptr [4])))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[47][6]~q  & ( !\A_SPW_TOP|rx_data|mem[63][6]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr 
// [1] & ((!\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|mem[45][6]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[61][6]~q )))) # (\A_SPW_TOP|rx_data|wr_ptr [1] & (((!\A_SPW_TOP|rx_data|wr_ptr [4])))) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|mem[47][6]~q  & ( !\A_SPW_TOP|rx_data|mem[63][6]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & ((!\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|mem[45][6]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[61][6]~q )))) 
// ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datab(!\A_SPW_TOP|rx_data|mem[61][6]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[45][6]~q ),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datae(!\A_SPW_TOP|rx_data|mem[47][6]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[63][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux2~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux2~18 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux2~18 .lut_mask = 64'h0A225F220A775F77;
defparam \A_SPW_TOP|rx_data|Mux2~18 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y3_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector390~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector390~0_combout  = ( \A_SPW_TOP|rx_data|Selector388~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [6])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux2~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector388~0_combout  & ( \A_SPW_TOP|rx_data|mem[41][6]~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .datab(!\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[41][6]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector388~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector390~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector390~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector390~0 .lut_mask = 64'h00FF00FF53535353;
defparam \A_SPW_TOP|rx_data|Selector390~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y3_N23
dffeas \A_SPW_TOP|rx_data|mem[41][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector390~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[41][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[41][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[41][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y3_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector408~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector408~0_combout  = ( \A_SPW_TOP|rx_data|mem[43][6]~q  & ( (!\A_SPW_TOP|rx_data|Selector406~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [6])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux2~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[43][6]~q  & ( (\A_SPW_TOP|rx_data|Selector406~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [6])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux2~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .datab(!\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector406~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[43][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector408~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector408~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector408~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|rx_data|Selector408~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y3_N11
dffeas \A_SPW_TOP|rx_data|mem[43][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector408~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[43][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[43][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[43][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y3_N51
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector534~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector534~0_combout  = ( \A_SPW_TOP|rx_data|Selector532~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [6]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux2~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector532~0_combout  & ( \A_SPW_TOP|rx_data|mem[57][6]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .datac(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .datad(!\A_SPW_TOP|rx_data|mem[57][6]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector532~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector534~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector534~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector534~0 .lut_mask = 64'h00FF00FF1B1B1B1B;
defparam \A_SPW_TOP|rx_data|Selector534~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y3_N23
dffeas \A_SPW_TOP|rx_data|mem[57][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector534~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[57][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[57][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[57][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y3_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector552~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector552~0_combout  = ( \A_SPW_TOP|rx_data|mem[59][6]~q  & ( (!\A_SPW_TOP|rx_data|Selector550~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [6])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux2~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[59][6]~q  & ( (\A_SPW_TOP|rx_data|Selector550~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [6])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux2~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .datab(!\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|Selector550~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[59][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector552~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector552~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector552~0 .lut_mask = 64'h00530053FF53FF53;
defparam \A_SPW_TOP|rx_data|Selector552~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y3_N35
dffeas \A_SPW_TOP|rx_data|mem[59][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector552~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[59][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[59][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[59][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y3_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux2~16 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux2~16_combout  = ( \A_SPW_TOP|rx_data|mem[57][6]~q  & ( \A_SPW_TOP|rx_data|mem[59][6]~q  & ( ((!\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|mem[41][6]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [1] & ((\A_SPW_TOP|rx_data|mem[43][6]~q 
// )))) # (\A_SPW_TOP|rx_data|wr_ptr [4]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[57][6]~q  & ( \A_SPW_TOP|rx_data|mem[59][6]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|mem[41][6]~q  & ((!\A_SPW_TOP|rx_data|wr_ptr [4])))) # 
// (\A_SPW_TOP|rx_data|wr_ptr [1] & (((\A_SPW_TOP|rx_data|wr_ptr [4]) # (\A_SPW_TOP|rx_data|mem[43][6]~q )))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[57][6]~q  & ( !\A_SPW_TOP|rx_data|mem[59][6]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & (((\A_SPW_TOP|rx_data|wr_ptr 
// [4])) # (\A_SPW_TOP|rx_data|mem[41][6]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [1] & (((\A_SPW_TOP|rx_data|mem[43][6]~q  & !\A_SPW_TOP|rx_data|wr_ptr [4])))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[57][6]~q  & ( !\A_SPW_TOP|rx_data|mem[59][6]~q  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [4] & ((!\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|mem[41][6]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [1] & ((\A_SPW_TOP|rx_data|mem[43][6]~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[41][6]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[43][6]~q ),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datae(!\A_SPW_TOP|rx_data|mem[57][6]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[59][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux2~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux2~16 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux2~16 .lut_mask = 64'h530053F0530F53FF;
defparam \A_SPW_TOP|rx_data|Mux2~16 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y3_N45
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector561~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector561~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector559~0_combout  & ((\A_SPW_TOP|rx_data|mem[60][6]~q ))) # (\A_SPW_TOP|rx_data|Selector559~0_combout  & 
// (\A_SPW_TOP|rx_data|Mux2~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector559~0_combout  & ((\A_SPW_TOP|rx_data|mem[60][6]~q ))) # (\A_SPW_TOP|rx_data|Selector559~0_combout  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [6])) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .datab(!\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector559~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[60][6]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector561~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector561~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector561~0 .lut_mask = 64'h05F505F503F303F3;
defparam \A_SPW_TOP|rx_data|Selector561~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y3_N23
dffeas \A_SPW_TOP|rx_data|mem[60][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector561~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[60][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[60][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[60][6] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y3_N9
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector435~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector435~0_combout  = ( \A_SPW_TOP|SPW|RX|rx_data_flag [6] & ( (!\A_SPW_TOP|rx_data|Selector433~0_combout  & (((\A_SPW_TOP|rx_data|mem[46][6]~q )))) # (\A_SPW_TOP|rx_data|Selector433~0_combout  & 
// (((!\A_SPW_TOP|rx_data|state_data_write.00~q )) # (\A_SPW_TOP|rx_data|Mux2~20_combout ))) ) ) # ( !\A_SPW_TOP|SPW|RX|rx_data_flag [6] & ( (!\A_SPW_TOP|rx_data|Selector433~0_combout  & (((\A_SPW_TOP|rx_data|mem[46][6]~q )))) # 
// (\A_SPW_TOP|rx_data|Selector433~0_combout  & (\A_SPW_TOP|rx_data|Mux2~20_combout  & (\A_SPW_TOP|rx_data|state_data_write.00~q ))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Selector433~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[46][6]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector435~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector435~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector435~0 .lut_mask = 64'h01F101F10DFD0DFD;
defparam \A_SPW_TOP|rx_data|Selector435~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y3_N20
dffeas \A_SPW_TOP|rx_data|mem[46][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector435~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[46][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[46][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[46][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y3_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector579~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector579~0_combout  = ( \A_SPW_TOP|rx_data|mem[62][6]~q  & ( (!\A_SPW_TOP|rx_data|Selector577~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [6])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux2~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[62][6]~q  & ( (\A_SPW_TOP|rx_data|Selector577~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [6])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux2~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .datab(!\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector577~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[62][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector579~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector579~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector579~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|rx_data|Selector579~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y3_N32
dffeas \A_SPW_TOP|rx_data|mem[62][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector579~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[62][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[62][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[62][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y3_N27
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector417~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector417~0_combout  = ( \A_SPW_TOP|rx_data|mem[44][6]~q  & ( (!\A_SPW_TOP|rx_data|Selector415~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [6])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux2~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[44][6]~q  & ( (\A_SPW_TOP|rx_data|Selector415~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [6])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux2~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .datab(!\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector415~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[44][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector417~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector417~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector417~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|rx_data|Selector417~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y3_N17
dffeas \A_SPW_TOP|rx_data|mem[44][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector417~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[44][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[44][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[44][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y3_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux2~17 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux2~17_combout  = ( \A_SPW_TOP|rx_data|mem[62][6]~q  & ( \A_SPW_TOP|rx_data|mem[44][6]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & (((!\A_SPW_TOP|rx_data|wr_ptr [4])) # (\A_SPW_TOP|rx_data|mem[60][6]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [1] 
// & (((\A_SPW_TOP|rx_data|wr_ptr [4]) # (\A_SPW_TOP|rx_data|mem[46][6]~q )))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[62][6]~q  & ( \A_SPW_TOP|rx_data|mem[44][6]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & (((!\A_SPW_TOP|rx_data|wr_ptr [4])) # 
// (\A_SPW_TOP|rx_data|mem[60][6]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [1] & (((\A_SPW_TOP|rx_data|mem[46][6]~q  & !\A_SPW_TOP|rx_data|wr_ptr [4])))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[62][6]~q  & ( !\A_SPW_TOP|rx_data|mem[44][6]~q  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|mem[60][6]~q  & ((\A_SPW_TOP|rx_data|wr_ptr [4])))) # (\A_SPW_TOP|rx_data|wr_ptr [1] & (((\A_SPW_TOP|rx_data|wr_ptr [4]) # (\A_SPW_TOP|rx_data|mem[46][6]~q )))) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|mem[62][6]~q  & ( !\A_SPW_TOP|rx_data|mem[44][6]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|mem[60][6]~q  & ((\A_SPW_TOP|rx_data|wr_ptr [4])))) # (\A_SPW_TOP|rx_data|wr_ptr [1] & (((\A_SPW_TOP|rx_data|mem[46][6]~q  & 
// !\A_SPW_TOP|rx_data|wr_ptr [4])))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[60][6]~q ),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datac(!\A_SPW_TOP|rx_data|mem[46][6]~q ),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datae(!\A_SPW_TOP|rx_data|mem[62][6]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[44][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux2~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux2~17 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux2~17 .lut_mask = 64'h03440377CF44CF77;
defparam \A_SPW_TOP|rx_data|Mux2~17 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y3_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux2~19 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux2~19_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [2] & ( \A_SPW_TOP|rx_data|Mux2~17_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [0]) # (\A_SPW_TOP|rx_data|Mux2~18_combout ) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [2] & ( 
// \A_SPW_TOP|rx_data|Mux2~17_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|Mux2~15_combout )) # (\A_SPW_TOP|rx_data|wr_ptr [0] & ((\A_SPW_TOP|rx_data|Mux2~16_combout ))) ) ) ) # ( \A_SPW_TOP|rx_data|wr_ptr [2] & ( 
// !\A_SPW_TOP|rx_data|Mux2~17_combout  & ( (\A_SPW_TOP|rx_data|Mux2~18_combout  & \A_SPW_TOP|rx_data|wr_ptr [0]) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [2] & ( !\A_SPW_TOP|rx_data|Mux2~17_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & 
// (\A_SPW_TOP|rx_data|Mux2~15_combout )) # (\A_SPW_TOP|rx_data|wr_ptr [0] & ((\A_SPW_TOP|rx_data|Mux2~16_combout ))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux2~15_combout ),
        .datab(!\A_SPW_TOP|rx_data|Mux2~18_combout ),
        .datac(!\A_SPW_TOP|rx_data|Mux2~16_combout ),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .dataf(!\A_SPW_TOP|rx_data|Mux2~17_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux2~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux2~19 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux2~19 .lut_mask = 64'h550F0033550FFF33;
defparam \A_SPW_TOP|rx_data|Mux2~19 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y3_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux2~20 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux2~20_combout  = ( \A_SPW_TOP|rx_data|Mux2~19_combout  & ( \A_SPW_TOP|rx_data|wr_ptr [5] & ( (\A_SPW_TOP|rx_data|wr_ptr [3]) # (\A_SPW_TOP|rx_data|Mux2~14_combout ) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux2~19_combout  & ( 
// \A_SPW_TOP|rx_data|wr_ptr [5] & ( (\A_SPW_TOP|rx_data|Mux2~14_combout  & !\A_SPW_TOP|rx_data|wr_ptr [3]) ) ) ) # ( \A_SPW_TOP|rx_data|Mux2~19_combout  & ( !\A_SPW_TOP|rx_data|wr_ptr [5] & ( (!\A_SPW_TOP|rx_data|wr_ptr [3] & 
// ((\A_SPW_TOP|rx_data|Mux2~4_combout ))) # (\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|Mux2~9_combout )) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux2~19_combout  & ( !\A_SPW_TOP|rx_data|wr_ptr [5] & ( (!\A_SPW_TOP|rx_data|wr_ptr [3] & 
// ((\A_SPW_TOP|rx_data|Mux2~4_combout ))) # (\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|Mux2~9_combout )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux2~14_combout ),
        .datab(!\A_SPW_TOP|rx_data|Mux2~9_combout ),
        .datac(!\A_SPW_TOP|rx_data|Mux2~4_combout ),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datae(!\A_SPW_TOP|rx_data|Mux2~19_combout ),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux2~20 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux2~20 .lut_mask = 64'h0F330F33550055FF;
defparam \A_SPW_TOP|rx_data|Mux2~20 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y3_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector282~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector282~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector280~0_combout  & ((\A_SPW_TOP|rx_data|mem[29][6]~q ))) # (\A_SPW_TOP|rx_data|Selector280~0_combout  & 
// (\A_SPW_TOP|rx_data|Mux2~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector280~0_combout  & ((\A_SPW_TOP|rx_data|mem[29][6]~q ))) # (\A_SPW_TOP|rx_data|Selector280~0_combout  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [6])) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux2~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
        .datac(!\A_SPW_TOP|rx_data|Selector280~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[29][6]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector282~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector282~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector282~0 .lut_mask = 64'h03F303F305F505F5;
defparam \A_SPW_TOP|rx_data|Selector282~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y3_N56
dffeas \A_SPW_TOP|rx_data|mem[29][6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector282~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[29][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[29][6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[29][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y3_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux11~15 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux11~15_combout  = ( \A_SPW_TOP|rx_data|mem[28][6]~q  & ( \A_SPW_TOP|rx_data|rd_ptr [2] & ( (!\A_SPW_TOP|rx_data|rd_ptr [0]) # (\A_SPW_TOP|rx_data|mem[29][6]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[28][6]~q  & ( \A_SPW_TOP|rx_data|rd_ptr 
// [2] & ( (\A_SPW_TOP|rx_data|mem[29][6]~q  & \A_SPW_TOP|rx_data|rd_ptr [0]) ) ) ) # ( \A_SPW_TOP|rx_data|mem[28][6]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [2] & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & ((\A_SPW_TOP|rx_data|mem[24][6]~q ))) # 
// (\A_SPW_TOP|rx_data|rd_ptr [0] & (\A_SPW_TOP|rx_data|mem[25][6]~q )) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[28][6]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [2] & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & ((\A_SPW_TOP|rx_data|mem[24][6]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr 
// [0] & (\A_SPW_TOP|rx_data|mem[25][6]~q )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[29][6]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[25][6]~q ),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .datad(!\A_SPW_TOP|rx_data|mem[24][6]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[28][6]~q ),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux11~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux11~15 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux11~15 .lut_mask = 64'h03F303F30505F5F5;
defparam \A_SPW_TOP|rx_data|Mux11~15 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y3_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux11~17 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux11~17_combout  = ( \A_SPW_TOP|rx_data|mem[31][6]~q  & ( \A_SPW_TOP|rx_data|mem[30][6]~q  & ( ((!\A_SPW_TOP|rx_data|rd_ptr [0] & (\A_SPW_TOP|rx_data|mem[26][6]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [0] & ((\A_SPW_TOP|rx_data|mem[27][6]~q 
// )))) # (\A_SPW_TOP|rx_data|rd_ptr [2]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[31][6]~q  & ( \A_SPW_TOP|rx_data|mem[30][6]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & (((\A_SPW_TOP|rx_data|rd_ptr [2])) # (\A_SPW_TOP|rx_data|mem[26][6]~q ))) # 
// (\A_SPW_TOP|rx_data|rd_ptr [0] & (((!\A_SPW_TOP|rx_data|rd_ptr [2] & \A_SPW_TOP|rx_data|mem[27][6]~q )))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[31][6]~q  & ( !\A_SPW_TOP|rx_data|mem[30][6]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & 
// (\A_SPW_TOP|rx_data|mem[26][6]~q  & (!\A_SPW_TOP|rx_data|rd_ptr [2]))) # (\A_SPW_TOP|rx_data|rd_ptr [0] & (((\A_SPW_TOP|rx_data|mem[27][6]~q ) # (\A_SPW_TOP|rx_data|rd_ptr [2])))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[31][6]~q  & ( 
// !\A_SPW_TOP|rx_data|mem[30][6]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [2] & ((!\A_SPW_TOP|rx_data|rd_ptr [0] & (\A_SPW_TOP|rx_data|mem[26][6]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [0] & ((\A_SPW_TOP|rx_data|mem[27][6]~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .datab(!\A_SPW_TOP|rx_data|mem[26][6]~q ),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datad(!\A_SPW_TOP|rx_data|mem[27][6]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[31][6]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[30][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux11~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux11~17 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux11~17 .lut_mask = 64'h207025752A7A2F7F;
defparam \A_SPW_TOP|rx_data|Mux11~17 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y3_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux11~16 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux11~16_combout  = ( \A_SPW_TOP|rx_data|mem[56][6]~q  & ( \A_SPW_TOP|rx_data|rd_ptr [0] & ( (!\A_SPW_TOP|rx_data|rd_ptr [2] & ((\A_SPW_TOP|rx_data|mem[57][6]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|mem[61][6]~q )) 
// ) ) ) # ( !\A_SPW_TOP|rx_data|mem[56][6]~q  & ( \A_SPW_TOP|rx_data|rd_ptr [0] & ( (!\A_SPW_TOP|rx_data|rd_ptr [2] & ((\A_SPW_TOP|rx_data|mem[57][6]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|mem[61][6]~q )) ) ) ) # ( 
// \A_SPW_TOP|rx_data|mem[56][6]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [0] & ( (!\A_SPW_TOP|rx_data|rd_ptr [2]) # (\A_SPW_TOP|rx_data|mem[60][6]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[56][6]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [0] & ( 
// (\A_SPW_TOP|rx_data|mem[60][6]~q  & \A_SPW_TOP|rx_data|rd_ptr [2]) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[60][6]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[61][6]~q ),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datad(!\A_SPW_TOP|rx_data|mem[57][6]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[56][6]~q ),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux11~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux11~16 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux11~16 .lut_mask = 64'h0505F5F503F303F3;
defparam \A_SPW_TOP|rx_data|Mux11~16 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y3_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux11~18 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux11~18_combout  = ( \A_SPW_TOP|rx_data|rd_ptr [0] & ( \A_SPW_TOP|rx_data|rd_ptr [2] & ( \A_SPW_TOP|rx_data|mem[63][6]~q  ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [0] & ( \A_SPW_TOP|rx_data|rd_ptr [2] & ( \A_SPW_TOP|rx_data|mem[62][6]~q  ) 
// ) ) # ( \A_SPW_TOP|rx_data|rd_ptr [0] & ( !\A_SPW_TOP|rx_data|rd_ptr [2] & ( \A_SPW_TOP|rx_data|mem[59][6]~q  ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [0] & ( !\A_SPW_TOP|rx_data|rd_ptr [2] & ( \A_SPW_TOP|rx_data|mem[58][6]~q  ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[63][6]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[62][6]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[59][6]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[58][6]~q ),
        .datae(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux11~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux11~18 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux11~18 .lut_mask = 64'h00FF0F0F33335555;
defparam \A_SPW_TOP|rx_data|Mux11~18 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y3_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux11~19 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux11~19_combout  = ( \A_SPW_TOP|rx_data|rd_ptr [1] & ( \A_SPW_TOP|rx_data|Mux11~18_combout  & ( (\A_SPW_TOP|rx_data|Mux11~17_combout ) # (\A_SPW_TOP|rx_data|rd_ptr [5]) ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [1] & ( 
// \A_SPW_TOP|rx_data|Mux11~18_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [5] & (\A_SPW_TOP|rx_data|Mux11~15_combout )) # (\A_SPW_TOP|rx_data|rd_ptr [5] & ((\A_SPW_TOP|rx_data|Mux11~16_combout ))) ) ) ) # ( \A_SPW_TOP|rx_data|rd_ptr [1] & ( 
// !\A_SPW_TOP|rx_data|Mux11~18_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [5] & \A_SPW_TOP|rx_data|Mux11~17_combout ) ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [1] & ( !\A_SPW_TOP|rx_data|Mux11~18_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [5] & 
// (\A_SPW_TOP|rx_data|Mux11~15_combout )) # (\A_SPW_TOP|rx_data|rd_ptr [5] & ((\A_SPW_TOP|rx_data|Mux11~16_combout ))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .datab(!\A_SPW_TOP|rx_data|Mux11~15_combout ),
        .datac(!\A_SPW_TOP|rx_data|Mux11~17_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux11~16_combout ),
        .datae(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .dataf(!\A_SPW_TOP|rx_data|Mux11~18_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux11~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux11~19 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux11~19 .lut_mask = 64'h22770A0A22775F5F;
defparam \A_SPW_TOP|rx_data|Mux11~19 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y3_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux11~2 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux11~2_combout  = ( \A_SPW_TOP|rx_data|mem[35][6]~q  & ( \A_SPW_TOP|rx_data|rd_ptr [0] & ( (\A_SPW_TOP|rx_data|mem[3][6]~q ) # (\A_SPW_TOP|rx_data|rd_ptr [5]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[35][6]~q  & ( \A_SPW_TOP|rx_data|rd_ptr 
// [0] & ( (!\A_SPW_TOP|rx_data|rd_ptr [5] & \A_SPW_TOP|rx_data|mem[3][6]~q ) ) ) ) # ( \A_SPW_TOP|rx_data|mem[35][6]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [0] & ( (!\A_SPW_TOP|rx_data|rd_ptr [5] & ((\A_SPW_TOP|rx_data|mem[2][6]~q ))) # 
// (\A_SPW_TOP|rx_data|rd_ptr [5] & (\A_SPW_TOP|rx_data|mem[34][6]~q )) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[35][6]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [0] & ( (!\A_SPW_TOP|rx_data|rd_ptr [5] & ((\A_SPW_TOP|rx_data|mem[2][6]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [5] 
// & (\A_SPW_TOP|rx_data|mem[34][6]~q )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[34][6]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[2][6]~q ),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .datad(!\A_SPW_TOP|rx_data|mem[3][6]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[35][6]~q ),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux11~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux11~2 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux11~2 .lut_mask = 64'h3535353500F00FFF;
defparam \A_SPW_TOP|rx_data|Mux11~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y3_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux11~3 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux11~3_combout  = ( \A_SPW_TOP|rx_data|rd_ptr [5] & ( \A_SPW_TOP|rx_data|rd_ptr [0] & ( \A_SPW_TOP|rx_data|mem[39][6]~q  ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [5] & ( \A_SPW_TOP|rx_data|rd_ptr [0] & ( \A_SPW_TOP|rx_data|mem[7][6]~q  ) ) 
// ) # ( \A_SPW_TOP|rx_data|rd_ptr [5] & ( !\A_SPW_TOP|rx_data|rd_ptr [0] & ( \A_SPW_TOP|rx_data|mem[38][6]~q  ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [5] & ( !\A_SPW_TOP|rx_data|rd_ptr [0] & ( \A_SPW_TOP|rx_data|mem[6][6]~q  ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[7][6]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[38][6]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[6][6]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[39][6]~q ),
        .datae(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux11~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux11~3 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux11~3 .lut_mask = 64'h0F0F3333555500FF;
defparam \A_SPW_TOP|rx_data|Mux11~3 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y3_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux11~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux11~1_combout  = ( \A_SPW_TOP|rx_data|rd_ptr [5] & ( \A_SPW_TOP|rx_data|mem[37][6]~q  & ( (\A_SPW_TOP|rx_data|rd_ptr [0]) # (\A_SPW_TOP|rx_data|mem[36][6]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [5] & ( 
// \A_SPW_TOP|rx_data|mem[37][6]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & ((\A_SPW_TOP|rx_data|mem[4][6]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [0] & (\A_SPW_TOP|rx_data|mem[5][6]~q )) ) ) ) # ( \A_SPW_TOP|rx_data|rd_ptr [5] & ( !\A_SPW_TOP|rx_data|mem[37][6]~q  
// & ( (\A_SPW_TOP|rx_data|mem[36][6]~q  & !\A_SPW_TOP|rx_data|rd_ptr [0]) ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [5] & ( !\A_SPW_TOP|rx_data|mem[37][6]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & ((\A_SPW_TOP|rx_data|mem[4][6]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr 
// [0] & (\A_SPW_TOP|rx_data|mem[5][6]~q )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[36][6]~q ),
        .datab(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .datac(!\A_SPW_TOP|rx_data|mem[5][6]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[4][6]~q ),
        .datae(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .dataf(!\A_SPW_TOP|rx_data|mem[37][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux11~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux11~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux11~1 .lut_mask = 64'h03CF444403CF7777;
defparam \A_SPW_TOP|rx_data|Mux11~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y3_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux11~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux11~0_combout  = ( \A_SPW_TOP|rx_data|rd_ptr [5] & ( \A_SPW_TOP|rx_data|rd_ptr [0] & ( \A_SPW_TOP|rx_data|mem[33][6]~q  ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [5] & ( \A_SPW_TOP|rx_data|rd_ptr [0] & ( \A_SPW_TOP|rx_data|mem[1][6]~q  ) ) 
// ) # ( \A_SPW_TOP|rx_data|rd_ptr [5] & ( !\A_SPW_TOP|rx_data|rd_ptr [0] & ( \A_SPW_TOP|rx_data|mem[32][6]~q  ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [5] & ( !\A_SPW_TOP|rx_data|rd_ptr [0] & ( \A_SPW_TOP|rx_data|mem[0][6]~q  ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[1][6]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[33][6]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[32][6]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[0][6]~q ),
        .datae(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux11~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux11~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux11~0 .lut_mask = 64'h00FF0F0F55553333;
defparam \A_SPW_TOP|rx_data|Mux11~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y3_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux11~4 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux11~4_combout  = ( \A_SPW_TOP|rx_data|rd_ptr [1] & ( \A_SPW_TOP|rx_data|Mux11~0_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|Mux11~2_combout )) # (\A_SPW_TOP|rx_data|rd_ptr [2] & 
// ((\A_SPW_TOP|rx_data|Mux11~3_combout ))) ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [1] & ( \A_SPW_TOP|rx_data|Mux11~0_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [2]) # (\A_SPW_TOP|rx_data|Mux11~1_combout ) ) ) ) # ( \A_SPW_TOP|rx_data|rd_ptr [1] & ( 
// !\A_SPW_TOP|rx_data|Mux11~0_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|Mux11~2_combout )) # (\A_SPW_TOP|rx_data|rd_ptr [2] & ((\A_SPW_TOP|rx_data|Mux11~3_combout ))) ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [1] & ( 
// !\A_SPW_TOP|rx_data|Mux11~0_combout  & ( (\A_SPW_TOP|rx_data|rd_ptr [2] & \A_SPW_TOP|rx_data|Mux11~1_combout ) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux11~2_combout ),
        .datab(!\A_SPW_TOP|rx_data|Mux11~3_combout ),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datad(!\A_SPW_TOP|rx_data|Mux11~1_combout ),
        .datae(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .dataf(!\A_SPW_TOP|rx_data|Mux11~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux11~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux11~4 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux11~4 .lut_mask = 64'h000F5353F0FF5353;
defparam \A_SPW_TOP|rx_data|Mux11~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y3_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux11~10 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux11~10_combout  = ( \A_SPW_TOP|rx_data|mem[42][6]~q  & ( \A_SPW_TOP|rx_data|mem[8][6]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & (((!\A_SPW_TOP|rx_data|rd_ptr [5])) # (\A_SPW_TOP|rx_data|mem[40][6]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [1] 
// & (((\A_SPW_TOP|rx_data|rd_ptr [5]) # (\A_SPW_TOP|rx_data|mem[10][6]~q )))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[42][6]~q  & ( \A_SPW_TOP|rx_data|mem[8][6]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & (((!\A_SPW_TOP|rx_data|rd_ptr [5])) # 
// (\A_SPW_TOP|rx_data|mem[40][6]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [1] & (((\A_SPW_TOP|rx_data|mem[10][6]~q  & !\A_SPW_TOP|rx_data|rd_ptr [5])))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[42][6]~q  & ( !\A_SPW_TOP|rx_data|mem[8][6]~q  & ( 
// (!\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|mem[40][6]~q  & ((\A_SPW_TOP|rx_data|rd_ptr [5])))) # (\A_SPW_TOP|rx_data|rd_ptr [1] & (((\A_SPW_TOP|rx_data|rd_ptr [5]) # (\A_SPW_TOP|rx_data|mem[10][6]~q )))) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|mem[42][6]~q  & ( !\A_SPW_TOP|rx_data|mem[8][6]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|mem[40][6]~q  & ((\A_SPW_TOP|rx_data|rd_ptr [5])))) # (\A_SPW_TOP|rx_data|rd_ptr [1] & (((\A_SPW_TOP|rx_data|mem[10][6]~q  & 
// !\A_SPW_TOP|rx_data|rd_ptr [5])))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datab(!\A_SPW_TOP|rx_data|mem[40][6]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[10][6]~q ),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .datae(!\A_SPW_TOP|rx_data|mem[42][6]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[8][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux11~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux11~10 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux11~10 .lut_mask = 64'h05220577AF22AF77;
defparam \A_SPW_TOP|rx_data|Mux11~10 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y3_N39
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux11~12 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux11~12_combout  = ( \A_SPW_TOP|rx_data|mem[14][6]~q  & ( \A_SPW_TOP|rx_data|mem[12][6]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [5]) # ((!\A_SPW_TOP|rx_data|rd_ptr [1] & ((\A_SPW_TOP|rx_data|mem[44][6]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [1] 
// & (\A_SPW_TOP|rx_data|mem[46][6]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[14][6]~q  & ( \A_SPW_TOP|rx_data|mem[12][6]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & (((!\A_SPW_TOP|rx_data|rd_ptr [5]) # (\A_SPW_TOP|rx_data|mem[44][6]~q )))) # 
// (\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|mem[46][6]~q  & ((\A_SPW_TOP|rx_data|rd_ptr [5])))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[14][6]~q  & ( !\A_SPW_TOP|rx_data|mem[12][6]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & 
// (((\A_SPW_TOP|rx_data|mem[44][6]~q  & \A_SPW_TOP|rx_data|rd_ptr [5])))) # (\A_SPW_TOP|rx_data|rd_ptr [1] & (((!\A_SPW_TOP|rx_data|rd_ptr [5])) # (\A_SPW_TOP|rx_data|mem[46][6]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[14][6]~q  & ( 
// !\A_SPW_TOP|rx_data|mem[12][6]~q  & ( (\A_SPW_TOP|rx_data|rd_ptr [5] & ((!\A_SPW_TOP|rx_data|rd_ptr [1] & ((\A_SPW_TOP|rx_data|mem[44][6]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|mem[46][6]~q )))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[46][6]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[44][6]~q ),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .datae(!\A_SPW_TOP|rx_data|mem[14][6]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[12][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux11~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux11~12 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux11~12 .lut_mask = 64'h00350F35F035FF35;
defparam \A_SPW_TOP|rx_data|Mux11~12 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y3_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux11~11 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux11~11_combout  = ( \A_SPW_TOP|rx_data|mem[11][6]~q  & ( \A_SPW_TOP|rx_data|rd_ptr [5] & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|mem[41][6]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [1] & ((\A_SPW_TOP|rx_data|mem[43][6]~q ))) 
// ) ) ) # ( !\A_SPW_TOP|rx_data|mem[11][6]~q  & ( \A_SPW_TOP|rx_data|rd_ptr [5] & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|mem[41][6]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [1] & ((\A_SPW_TOP|rx_data|mem[43][6]~q ))) ) ) ) # ( 
// \A_SPW_TOP|rx_data|mem[11][6]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [5] & ( (\A_SPW_TOP|rx_data|rd_ptr [1]) # (\A_SPW_TOP|rx_data|mem[9][6]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[11][6]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [5] & ( (\A_SPW_TOP|rx_data|mem[9][6]~q  
// & !\A_SPW_TOP|rx_data|rd_ptr [1]) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[9][6]~q ),
        .datab(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datac(!\A_SPW_TOP|rx_data|mem[41][6]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[43][6]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[11][6]~q ),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux11~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux11~11 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux11~11 .lut_mask = 64'h444477770C3F0C3F;
defparam \A_SPW_TOP|rx_data|Mux11~11 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y3_N33
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux11~13 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux11~13_combout  = ( \A_SPW_TOP|rx_data|rd_ptr [1] & ( \A_SPW_TOP|rx_data|mem[13][6]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [5] & ((\A_SPW_TOP|rx_data|mem[15][6]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [5] & (\A_SPW_TOP|rx_data|mem[47][6]~q )) 
// ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [1] & ( \A_SPW_TOP|rx_data|mem[13][6]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [5]) # (\A_SPW_TOP|rx_data|mem[45][6]~q ) ) ) ) # ( \A_SPW_TOP|rx_data|rd_ptr [1] & ( !\A_SPW_TOP|rx_data|mem[13][6]~q  & ( 
// (!\A_SPW_TOP|rx_data|rd_ptr [5] & ((\A_SPW_TOP|rx_data|mem[15][6]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [5] & (\A_SPW_TOP|rx_data|mem[47][6]~q )) ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [1] & ( !\A_SPW_TOP|rx_data|mem[13][6]~q  & ( 
// (\A_SPW_TOP|rx_data|mem[45][6]~q  & \A_SPW_TOP|rx_data|rd_ptr [5]) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[47][6]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[45][6]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[15][6]~q ),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .datae(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .dataf(!\A_SPW_TOP|rx_data|mem[13][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux11~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux11~13 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux11~13 .lut_mask = 64'h00330F55FF330F55;
defparam \A_SPW_TOP|rx_data|Mux11~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X36_Y3_N57
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux11~14 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux11~14_combout  = ( \A_SPW_TOP|rx_data|Mux11~11_combout  & ( \A_SPW_TOP|rx_data|Mux11~13_combout  & ( ((!\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|Mux11~10_combout )) # (\A_SPW_TOP|rx_data|rd_ptr [2] & 
// ((\A_SPW_TOP|rx_data|Mux11~12_combout )))) # (\A_SPW_TOP|rx_data|rd_ptr [0]) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux11~11_combout  & ( \A_SPW_TOP|rx_data|Mux11~13_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & ((!\A_SPW_TOP|rx_data|rd_ptr [2] & 
// (\A_SPW_TOP|rx_data|Mux11~10_combout )) # (\A_SPW_TOP|rx_data|rd_ptr [2] & ((\A_SPW_TOP|rx_data|Mux11~12_combout ))))) # (\A_SPW_TOP|rx_data|rd_ptr [0] & (((\A_SPW_TOP|rx_data|rd_ptr [2])))) ) ) ) # ( \A_SPW_TOP|rx_data|Mux11~11_combout  & ( 
// !\A_SPW_TOP|rx_data|Mux11~13_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & ((!\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|Mux11~10_combout )) # (\A_SPW_TOP|rx_data|rd_ptr [2] & ((\A_SPW_TOP|rx_data|Mux11~12_combout ))))) # 
// (\A_SPW_TOP|rx_data|rd_ptr [0] & (((!\A_SPW_TOP|rx_data|rd_ptr [2])))) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux11~11_combout  & ( !\A_SPW_TOP|rx_data|Mux11~13_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & ((!\A_SPW_TOP|rx_data|rd_ptr [2] & 
// (\A_SPW_TOP|rx_data|Mux11~10_combout )) # (\A_SPW_TOP|rx_data|rd_ptr [2] & ((\A_SPW_TOP|rx_data|Mux11~12_combout ))))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .datab(!\A_SPW_TOP|rx_data|Mux11~10_combout ),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datad(!\A_SPW_TOP|rx_data|Mux11~12_combout ),
        .datae(!\A_SPW_TOP|rx_data|Mux11~11_combout ),
        .dataf(!\A_SPW_TOP|rx_data|Mux11~13_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux11~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux11~14 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux11~14 .lut_mask = 64'h202A707A252F757F;
defparam \A_SPW_TOP|rx_data|Mux11~14 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y3_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux11~8 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux11~8_combout  = ( \A_SPW_TOP|rx_data|mem[22][6]~q  & ( \A_SPW_TOP|rx_data|rd_ptr [0] & ( (!\A_SPW_TOP|rx_data|rd_ptr [5] & ((\A_SPW_TOP|rx_data|mem[23][6]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [5] & (\A_SPW_TOP|rx_data|mem[55][6]~q )) ) 
// ) ) # ( !\A_SPW_TOP|rx_data|mem[22][6]~q  & ( \A_SPW_TOP|rx_data|rd_ptr [0] & ( (!\A_SPW_TOP|rx_data|rd_ptr [5] & ((\A_SPW_TOP|rx_data|mem[23][6]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [5] & (\A_SPW_TOP|rx_data|mem[55][6]~q )) ) ) ) # ( 
// \A_SPW_TOP|rx_data|mem[22][6]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [0] & ( (!\A_SPW_TOP|rx_data|rd_ptr [5]) # (\A_SPW_TOP|rx_data|mem[54][6]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[22][6]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [0] & ( 
// (\A_SPW_TOP|rx_data|mem[54][6]~q  & \A_SPW_TOP|rx_data|rd_ptr [5]) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[55][6]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[23][6]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[54][6]~q ),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .datae(!\A_SPW_TOP|rx_data|mem[22][6]~q ),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux11~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux11~8 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux11~8 .lut_mask = 64'h000FFF0F33553355;
defparam \A_SPW_TOP|rx_data|Mux11~8 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y3_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux11~6 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux11~6_combout  = ( \A_SPW_TOP|rx_data|mem[52][6]~q  & ( \A_SPW_TOP|rx_data|rd_ptr [5] & ( (!\A_SPW_TOP|rx_data|rd_ptr [0]) # (\A_SPW_TOP|rx_data|mem[53][6]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[52][6]~q  & ( \A_SPW_TOP|rx_data|rd_ptr 
// [5] & ( (\A_SPW_TOP|rx_data|mem[53][6]~q  & \A_SPW_TOP|rx_data|rd_ptr [0]) ) ) ) # ( \A_SPW_TOP|rx_data|mem[52][6]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [5] & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & (\A_SPW_TOP|rx_data|mem[20][6]~q )) # (\A_SPW_TOP|rx_data|rd_ptr 
// [0] & ((\A_SPW_TOP|rx_data|mem[21][6]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[52][6]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [5] & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & (\A_SPW_TOP|rx_data|mem[20][6]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [0] & 
// ((\A_SPW_TOP|rx_data|mem[21][6]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[20][6]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[21][6]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[53][6]~q ),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .datae(!\A_SPW_TOP|rx_data|mem[52][6]~q ),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux11~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux11~6 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux11~6 .lut_mask = 64'h55335533000FFF0F;
defparam \A_SPW_TOP|rx_data|Mux11~6 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y3_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux11~7 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux11~7_combout  = ( \A_SPW_TOP|rx_data|rd_ptr [5] & ( \A_SPW_TOP|rx_data|mem[51][6]~q  & ( (\A_SPW_TOP|rx_data|rd_ptr [0]) # (\A_SPW_TOP|rx_data|mem[50][6]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [5] & ( 
// \A_SPW_TOP|rx_data|mem[51][6]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & (\A_SPW_TOP|rx_data|mem[18][6]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [0] & ((\A_SPW_TOP|rx_data|mem[19][6]~q ))) ) ) ) # ( \A_SPW_TOP|rx_data|rd_ptr [5] & ( 
// !\A_SPW_TOP|rx_data|mem[51][6]~q  & ( (\A_SPW_TOP|rx_data|mem[50][6]~q  & !\A_SPW_TOP|rx_data|rd_ptr [0]) ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [5] & ( !\A_SPW_TOP|rx_data|mem[51][6]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & (\A_SPW_TOP|rx_data|mem[18][6]~q 
// )) # (\A_SPW_TOP|rx_data|rd_ptr [0] & ((\A_SPW_TOP|rx_data|mem[19][6]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[50][6]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[18][6]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[19][6]~q ),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .datae(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .dataf(!\A_SPW_TOP|rx_data|mem[51][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux11~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux11~7 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux11~7 .lut_mask = 64'h330F5500330F55FF;
defparam \A_SPW_TOP|rx_data|Mux11~7 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y3_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux11~5 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux11~5_combout  = ( \A_SPW_TOP|rx_data|rd_ptr [0] & ( \A_SPW_TOP|rx_data|rd_ptr [5] & ( \A_SPW_TOP|rx_data|mem[49][6]~q  ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [0] & ( \A_SPW_TOP|rx_data|rd_ptr [5] & ( \A_SPW_TOP|rx_data|mem[48][6]~q  ) 
// ) ) # ( \A_SPW_TOP|rx_data|rd_ptr [0] & ( !\A_SPW_TOP|rx_data|rd_ptr [5] & ( \A_SPW_TOP|rx_data|mem[17][6]~q  ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [0] & ( !\A_SPW_TOP|rx_data|rd_ptr [5] & ( \A_SPW_TOP|rx_data|mem[16][6]~q  ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[48][6]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[49][6]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[17][6]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[16][6]~q ),
        .datae(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux11~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux11~5 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux11~5 .lut_mask = 64'h00FF0F0F55553333;
defparam \A_SPW_TOP|rx_data|Mux11~5 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y3_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux11~9 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux11~9_combout  = ( \A_SPW_TOP|rx_data|Mux11~7_combout  & ( \A_SPW_TOP|rx_data|Mux11~5_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [2]) # ((!\A_SPW_TOP|rx_data|rd_ptr [1] & ((\A_SPW_TOP|rx_data|Mux11~6_combout ))) # 
// (\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|Mux11~8_combout ))) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux11~7_combout  & ( \A_SPW_TOP|rx_data|Mux11~5_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [2] & (!\A_SPW_TOP|rx_data|rd_ptr [1])) # 
// (\A_SPW_TOP|rx_data|rd_ptr [2] & ((!\A_SPW_TOP|rx_data|rd_ptr [1] & ((\A_SPW_TOP|rx_data|Mux11~6_combout ))) # (\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|Mux11~8_combout )))) ) ) ) # ( \A_SPW_TOP|rx_data|Mux11~7_combout  & ( 
// !\A_SPW_TOP|rx_data|Mux11~5_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|rd_ptr [1])) # (\A_SPW_TOP|rx_data|rd_ptr [2] & ((!\A_SPW_TOP|rx_data|rd_ptr [1] & ((\A_SPW_TOP|rx_data|Mux11~6_combout ))) # (\A_SPW_TOP|rx_data|rd_ptr [1] & 
// (\A_SPW_TOP|rx_data|Mux11~8_combout )))) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux11~7_combout  & ( !\A_SPW_TOP|rx_data|Mux11~5_combout  & ( (\A_SPW_TOP|rx_data|rd_ptr [2] & ((!\A_SPW_TOP|rx_data|rd_ptr [1] & ((\A_SPW_TOP|rx_data|Mux11~6_combout ))) # 
// (\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|Mux11~8_combout )))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datab(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datac(!\A_SPW_TOP|rx_data|Mux11~8_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux11~6_combout ),
        .datae(!\A_SPW_TOP|rx_data|Mux11~7_combout ),
        .dataf(!\A_SPW_TOP|rx_data|Mux11~5_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux11~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux11~9 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux11~9 .lut_mask = 64'h0145236789CDABEF;
defparam \A_SPW_TOP|rx_data|Mux11~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X36_Y3_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux11~20 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux11~20_combout  = ( \A_SPW_TOP|rx_data|Mux11~9_combout  & ( \A_SPW_TOP|rx_data|rd_ptr [3] & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & ((\A_SPW_TOP|rx_data|Mux11~14_combout ))) # (\A_SPW_TOP|rx_data|rd_ptr [4] & 
// (\A_SPW_TOP|rx_data|Mux11~19_combout )) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux11~9_combout  & ( \A_SPW_TOP|rx_data|rd_ptr [3] & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & ((\A_SPW_TOP|rx_data|Mux11~14_combout ))) # (\A_SPW_TOP|rx_data|rd_ptr [4] & 
// (\A_SPW_TOP|rx_data|Mux11~19_combout )) ) ) ) # ( \A_SPW_TOP|rx_data|Mux11~9_combout  & ( !\A_SPW_TOP|rx_data|rd_ptr [3] & ( (\A_SPW_TOP|rx_data|Mux11~4_combout ) # (\A_SPW_TOP|rx_data|rd_ptr [4]) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux11~9_combout  & ( 
// !\A_SPW_TOP|rx_data|rd_ptr [3] & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & \A_SPW_TOP|rx_data|Mux11~4_combout ) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [4]),
        .datab(!\A_SPW_TOP|rx_data|Mux11~19_combout ),
        .datac(!\A_SPW_TOP|rx_data|Mux11~4_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux11~14_combout ),
        .datae(!\A_SPW_TOP|rx_data|Mux11~9_combout ),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux11~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux11~20 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux11~20 .lut_mask = 64'h0A0A5F5F11BB11BB;
defparam \A_SPW_TOP|rx_data|Mux11~20 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X36_Y3_N43
dffeas \A_SPW_TOP|rx_data|data_out[6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|rx_data|Mux11~20_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|data_out [6]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|data_out[6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|data_out[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y16_N3
cyclonev_lcell_comb \u0|data_flag_rx|read_mux_out[6] (
// Equation(s):
// \u0|data_flag_rx|read_mux_out [6] = ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & \A_SPW_TOP|rx_data|data_out [6]) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datab(gnd),
        .datac(!\A_SPW_TOP|rx_data|data_out [6]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|data_flag_rx|read_mux_out [6]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|data_flag_rx|read_mux_out[6] .extended_lut = "off";
defparam \u0|data_flag_rx|read_mux_out[6] .lut_mask = 64'h0A0A0A0A00000000;
defparam \u0|data_flag_rx|read_mux_out[6] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y16_N5
dffeas \u0|data_flag_rx|readdata[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|data_flag_rx|read_mux_out [6]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|data_flag_rx|readdata [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|data_flag_rx|readdata[6] .is_wysiwyg = "true";
defparam \u0|data_flag_rx|readdata[6] .power_up = "low";
// synopsys translate_on

// Location: FF_X23_Y16_N4
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|data_flag_rx|readdata [6]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre[6] .power_up = "low";
// synopsys translate_on

// Location: FF_X27_Y16_N59
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y16_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~6 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~6_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][6]~q  & ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1] ) ) # ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][6]~q  & ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [6] ) ) ) # ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][6]~q  & ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [6] ) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [6]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][6]~q ),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~6 .lut_mask = 64'h555555550000FFFF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y16_N32
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~6_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y2_N21
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|timecode~7 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|timecode~7_combout  = ( \A_SPW_TOP|SPW|RX|dta_timec_p [6] & ( (\A_SPW_TOP|SPW|RX|timecode [6]) # (\A_SPW_TOP|SPW|RX|timecode~0_combout ) ) ) # ( !\A_SPW_TOP|SPW|RX|dta_timec_p [6] & ( (!\A_SPW_TOP|SPW|RX|timecode~0_combout  & 
// \A_SPW_TOP|SPW|RX|timecode [6]) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|timecode~0_combout ),
        .datab(gnd),
        .datac(gnd),
        .datad(!\A_SPW_TOP|SPW|RX|timecode [6]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|dta_timec_p [6]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|timecode~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|timecode~7 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|timecode~7 .lut_mask = 64'h00AA00AA55FF55FF;
defparam \A_SPW_TOP|SPW|RX|timecode~7 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y2_N56
dffeas \A_SPW_TOP|SPW|RX|timecode[6] (
        .clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|RX|timecode~7_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(!\A_SPW_TOP|SPW|RX|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|timecode [6]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|timecode[6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|timecode[6] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y14_N27
cyclonev_lcell_comb \u0|timecode_rx|read_mux_out[6] (
// Equation(s):
// \u0|timecode_rx|read_mux_out [6] = ( \A_SPW_TOP|SPW|RX|timecode [6] & ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\A_SPW_TOP|SPW|RX|timecode [6]),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|timecode_rx|read_mux_out [6]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|timecode_rx|read_mux_out[6] .extended_lut = "off";
defparam \u0|timecode_rx|read_mux_out[6] .lut_mask = 64'h0000AAAA00000000;
defparam \u0|timecode_rx|read_mux_out[6] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y14_N28
dffeas \u0|timecode_rx|readdata[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|timecode_rx|read_mux_out [6]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|timecode_rx|readdata [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|timecode_rx|readdata[6] .is_wysiwyg = "true";
defparam \u0|timecode_rx|readdata[6] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y16_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[6]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[6]~feeder_combout  = \u0|timecode_rx|readdata [6]

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|timecode_rx|readdata [6]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[6]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[6]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[6]~feeder .lut_mask = 64'h0F0F0F0F0F0F0F0F;
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[6]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y16_N55
dffeas \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[6]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[6] .power_up = "low";
// synopsys translate_on

// Location: FF_X25_Y16_N17
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~6_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][6] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y16_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~6 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~6_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][6]~q  & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1]) # 
// (\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [6]) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][6]~q  & ( (\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [6] & 
// !\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [6]),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][6]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~6 .lut_mask = 64'h303030303F3F3F3F;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y16_N11
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~6_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][6] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y16_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~77 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~77_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0] & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout  & 
// ((!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0] & (\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [6])) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0] & 
// ((\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][6]~q ))))) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0] & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout  & 
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][6]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [6]),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0]),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][6]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[6]~77_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~77 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~77 .lut_mask = 64'h00AA00AA202A202A;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~77 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y16_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~78 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~78_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout  & ( ((\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [6] & 
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[6]~77_combout ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout  & ( 
// ((\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][6]~q  & !\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[6]~77_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [6]),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][6]~q ),
        .datac(!\u0|mm_interconnect_0|rsp_mux_001|src_data[6]~77_combout ),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[6]~78_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~78 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~78 .lut_mask = 64'h3F0F3F0F5F0F5F0F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~78 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y18_N42
cyclonev_lcell_comb \u0|timecode_tx_data|readdata[6] (
// Equation(s):
// \u0|timecode_tx_data|readdata [6] = ( \u0|timecode_tx_data|data_out [6] & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|timecode_tx_data|data_out [6]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|timecode_tx_data|readdata [6]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|timecode_tx_data|readdata[6] .extended_lut = "off";
defparam \u0|timecode_tx_data|readdata[6] .lut_mask = 64'h0000000088888888;
defparam \u0|timecode_tx_data|readdata[6] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y18_N44
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|timecode_tx_data|readdata [6]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre[6] .power_up = "low";
// synopsys translate_on

// Location: FF_X28_Y16_N59
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y16_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~6 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~6_combout  = (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1] & (\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [6])) # 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1] & ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][6]~q )))

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [6]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][6]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~6 .lut_mask = 64'h505F505F505F505F;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y16_N20
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~6_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y16_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~76 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~76_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0] & ( (\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout  & 
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0] & (\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [6])) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0] & 
// ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][6]~q ))))) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0] & ( (\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout  & 
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][6]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [6]),
        .datab(!\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][6]~q ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[6]~76_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~76 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~76 .lut_mask = 64'h0303030311031103;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~76 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y16_N32
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y16_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~6 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~6_combout  = ( \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [6] & ( (!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1]) # 
// (\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][6]~q ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [6] & ( (\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][6]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][6]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [6]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~6 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y16_N2
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~6_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][6]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y16_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~210 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~210_combout  = ( !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout  & ( ((((\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout  & 
// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][6]~q )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[6]~76_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[6]~78_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[6]~75_combout ) 
// ) ) # ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout  & ( ((((\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout  & \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [6])) # 
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[6]~76_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[6]~78_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[6]~75_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ),
        .datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[6]~75_combout ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [6]),
        .datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[6]~78_combout ),
        .datae(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout ),
        .dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[6]~76_combout ),
        .datag(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][6]~q ),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[6]~210_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~210 .extended_lut = "on";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~210 .lut_mask = 64'h37FF37FFFFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~210 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y26_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARLEN [2] & ( \u0|hps_0|fpga_interfaces|h2f_ARLEN [1] & ( !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0] ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARLEN [2] & ( 
// \u0|hps_0|fpga_interfaces|h2f_ARLEN [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARLEN [0] ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_ARLEN [2] & ( !\u0|hps_0|fpga_interfaces|h2f_ARLEN [1] ) )

        .dataa(gnd),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [2]),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2 .lut_mask = 64'h0000FFFF3333CCCC;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y18_N2
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y20_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~4_combout  & ( 
// (!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0] & \u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~4_combout  & ( ((!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0] & 
// \u0|mm_interconnect_0|cmd_mux_010|saved_grant [1])) # (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~4_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 .lut_mask = 64'h0FAF0FAF00AA00AA;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y18_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout  = ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout  & ( 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) 
// ) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout  & ( 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) ) 
// ) ) # ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout  & ( 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) 
// ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout  & ( 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) 
// ) )

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 .lut_mask = 64'h5050A0A05F5FAFAF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y18_N41
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y20_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3_combout  & ( 
// ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout  & \u0|mm_interconnect_0|cmd_mux_010|saved_grant [1])) # (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]) ) ) # ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3_combout  & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout  & \u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5 .lut_mask = 64'h000F000F333F333F;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y18_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout  = ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])) # 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout ))) ) ) ) # ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])) # 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout ))) ) ) ) # ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) 
// # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout ) ) ) ) # ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout  & 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout ),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6 .lut_mask = 64'h000FFF0FCC0F330F;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y18_N56
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y18_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg 
// [2] & ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] ) ) # ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] $ 
// (((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))) ) )

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .lut_mask = 64'hAA5AAA5AAAAAAAAA;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y18_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout  & ( 
// \u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ) # 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout  & ( 
// \u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout )))) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout  & (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]))) ) ) ) # ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout  & ( 
// !\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout )))) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout  & (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]))) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout  & ( 
// !\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout )))) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout  & (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]))) ) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout ),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .lut_mask = 64'hF011F011F011F0FF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y22_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~0_combout  & ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout  & ( (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]) # (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]) ) ) ) # ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~0_combout  & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout  & ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] ) ) ) # ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~0_combout  & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout  & ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~0_combout ),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .lut_mask = 64'h0000555533337777;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y20_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout  & ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~1_combout  & ( (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]) # (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]) ) ) ) # ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout  & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~1_combout  & ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] ) ) ) # ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout  & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~1_combout  & ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 .lut_mask = 64'h00000F0F33333F3F;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y18_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  = ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg 
// [2] & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .lut_mask = 64'h0C000C0000000000;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y18_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout  = ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ) ) ) ) # ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ) ) ) ) # ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ) ) ) ) # ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ) ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 .lut_mask = 64'h0303CFCFCFCF0303;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y18_N53
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .power_up = "low";
// synopsys translate_on

// Location: FF_X19_Y18_N26
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y18_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout  = ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] $ 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6])))) # 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout )) ) ) # ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]))) # 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 .lut_mask = 64'h11DD11DDD11DD11D;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y18_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout  = ( !\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & ( 
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout  ) ) # ( !\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout  & ( !\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .lut_mask = 64'hF0F00000FFFF0000;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y18_N29
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y18_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_data[35] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_data [35] = ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] ) # ( !\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & ( (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_WSTRB 
// [3]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [3]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_010|src_data [35]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[35] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[35] .lut_mask = 64'h0303FFFF0303FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[35] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y18_N56
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_010|src_data [35]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y18_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_data[34] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_data [34] = ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] ) # ( !\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_WSTRB [2] & \u0|mm_interconnect_0|cmd_mux_010|saved_grant 
// [0]) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [2]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_010|src_data [34]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[34] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[34] .lut_mask = 64'h0505FFFF0505FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[34] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y18_N17
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_010|src_data [34]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y18_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_data[32] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_data [32] = ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] ) # ( !\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_WSTRB [0] & \u0|mm_interconnect_0|cmd_mux_010|saved_grant 
// [0]) ) )

        .dataa(gnd),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [0]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_010|src_data [32]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[32] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[32] .lut_mask = 64'h0303FFFF0303FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[32] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y18_N11
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_010|src_data [32]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y18_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~2_combout  = ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & ( 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~2 .lut_mask = 64'hC000C00000000000;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y22_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout  = ( !\u0|mm_interconnect_0|cmd_mux_010|src_data [87] & ( !\u0|mm_interconnect_0|cmd_mux_010|src_data [88] ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_010|src_data [88]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_010|src_data [87]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .lut_mask = 64'hAAAAAAAA00000000;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y22_N26
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y18_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~3 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~3_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~0_combout  & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~2_combout  & 
// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|local_write~0_combout  $ (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [0])))) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~2_combout  & 
// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ) # (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|local_write~0_combout  $ 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [0])))) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~0_combout  & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~2_combout  & 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ) ) )

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~2_combout ),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|local_write~0_combout ),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~3 .lut_mask = 64'h444444444FF44FF4;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y18_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  = ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & 
// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~3_combout  & (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q )) # 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~3_combout  & ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))))) # 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q )) ) )

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~3_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .lut_mask = 64'h00000000AACAAACA;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y23_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_payload[0] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_payload [0] = ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & ( (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]) # (\u0|hps_0|fpga_interfaces|h2f_WLAST [0]) ) ) # ( 
// !\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_WLAST [0]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_010|src_payload [0]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_payload[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_payload[0] .lut_mask = 64'h00FF00FF0FFF0FFF;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_payload[0] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y23_N8
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_010|src_payload [0]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y18_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q  & ( 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) # 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h000000003F3F3F3F;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y23_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_valid~0_combout  = ( \u0|mm_interconnect_0|router|Equal14~0_combout  & ( \u0|mm_interconnect_0|router|Equal7~1_combout  & ( 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout  & (\u0|mm_interconnect_0|cmd_demux|src10_valid~0_combout  & (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout  & 
// \u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]))) ) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout ),
        .datab(!\u0|mm_interconnect_0|cmd_demux|src10_valid~0_combout ),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
        .datae(!\u0|mm_interconnect_0|router|Equal14~0_combout ),
        .dataf(!\u0|mm_interconnect_0|router|Equal7~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_010|src_valid~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_valid~0 .lut_mask = 64'h0000000000000010;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_valid~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y31_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal16~0 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal16~0_combout  = ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & \u0|mm_interconnect_0|router_001|Equal3~0_combout ) ) )

        .dataa(gnd),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),
        .datac(!\u0|mm_interconnect_0|router_001|Equal3~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router_001|Equal16~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal16~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal16~0 .lut_mask = 64'h0303030300000000;
defparam \u0|mm_interconnect_0|router_001|Equal16~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y31_N44
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[10] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|router_001|Equal16~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [10]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[10] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[10] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y31_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|src10_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|src10_valid~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q  & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [10] & 
// \u0|hps_0|fpga_interfaces|h2f_ARVALID [0]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q  & ( \u0|hps_0|fpga_interfaces|h2f_ARVALID [0] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [10]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux_001|src10_valid~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|src10_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|src10_valid~0 .lut_mask = 64'h00FF00FF000F000F;
defparam \u0|mm_interconnect_0|cmd_demux_001|src10_valid~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y31_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_valid~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_valid~1_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & ( (\u0|mm_interconnect_0|cmd_demux_001|src10_valid~0_combout  & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & 
// (\u0|mm_interconnect_0|router_001|Equal3~0_combout  & \u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]))) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_demux_001|src10_valid~0_combout ),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),
        .datac(!\u0|mm_interconnect_0|router_001|Equal3~0_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_010|src_valid~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_valid~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_valid~1 .lut_mask = 64'h0000000000040004;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_valid~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y23_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout  = ( \u0|mm_interconnect_0|cmd_mux_010|src_valid~1_combout  & ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  ) ) # ( !\u0|mm_interconnect_0|cmd_mux_010|src_valid~1_combout  & ( (!\u0|mm_interconnect_0|cmd_mux_010|src_valid~0_combout ) # 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_010|src_valid~0_combout ),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_010|src_valid~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .lut_mask = 64'hFFF0FFF0FF00FF00;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y18_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  = ( !\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & ( (((!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout  & \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q 
// )))) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & ( 
// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout  & (((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ) 
// # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) # 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout )))) # 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
        .datae(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datag(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .extended_lut = "on";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .lut_mask = 64'h5555F755F555FF55;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y18_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout  = ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout  & ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  & ( 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout  & 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout  & 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout  & 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ))) ) ) ) # ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout  & ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  ) ) # ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout  & ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  ) )

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ),
        .datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout ),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .lut_mask = 64'hFFFFFFFF20000000;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y18_N14
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y18_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~1_combout  & ( 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ))) 
// # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q 
// )) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~1_combout  & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q )) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .lut_mask = 64'h0A5F0A5F1B1B1B1B;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y18_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18_combout  = ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & ( 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) # 
// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ) # (((!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & !\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1])) # 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ))) ) ) # ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q 
//  & ( ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ) # 
// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout 
// )))) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
        .datag(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18 .extended_lut = "on";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18 .lut_mask = 64'hFFECFF00FFFFFF03;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y18_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1_combout  = ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1 .lut_mask = 64'hFFFFFFFF00000000;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y18_N56
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y18_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout  = ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  
// & ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .lut_mask = 64'hF0F0F0F000000000;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y18_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout  & ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q 
//  & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & \u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]))) # 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ) ) ) # ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout  & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  
// & ( ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & \u0|mm_interconnect_0|cmd_mux_010|saved_grant [0])) # 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ) ) ) # ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout  & ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  
// & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & \u0|mm_interconnect_0|cmd_mux_010|saved_grant [0])) ) ) ) # ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout  & ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout 
//  & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & \u0|mm_interconnect_0|cmd_mux_010|saved_grant [0])) ) ) )

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .lut_mask = 64'h0202020203FF02FF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y18_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout  = ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout  & ( 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout  & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout 
//  & !\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16 .lut_mask = 64'h0300030000000000;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y18_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout  = ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) # 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ))) ) ) ) # ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .lut_mask = 64'h0303070700000000;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y18_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  = ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & ( 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .lut_mask = 64'h000F000F00000000;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y17_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  & ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout  ) ) # ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  & ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout  & ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout  ) ) ) # ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  
// & ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout  ) ) # ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout  & ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout  & ( 
// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout  & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout  & 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ))) # 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout ),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),
        .datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17 .lut_mask = 64'h5755FFFF5555FFFF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y17_N38
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y18_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  = ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( 
// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) ) ) # ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q 
// ) # ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~1_combout  & ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))))) ) )

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~1_combout ),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .extended_lut = "on";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .lut_mask = 64'h0C00F0F00C00F5F5;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y18_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  = ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & ( 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) # 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'h000000000AAA0AAA;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y23_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout  = ( \u0|mm_interconnect_0|cmd_mux_010|src_valid~1_combout  & ( 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout 
// ) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ))) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_010|src_valid~1_combout  & ( 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & (\u0|mm_interconnect_0|cmd_mux_010|src_valid~0_combout  & 
// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) # 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_010|src_valid~0_combout ),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_010|src_valid~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h0105010511551155;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y18_N38
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";
// synopsys translate_on

// Location: FF_X22_Y18_N59
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y18_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_read~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_read~0_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & 
// ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_read~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_read~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_read~0 .lut_mask = 64'h000F000F0F0F0F0F;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_read~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y18_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg~0_combout  = ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0_combout  & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_read~0_combout ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_read~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg~0 .lut_mask = 64'h00CC00CC00000000;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y18_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg~1_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg~0_combout  & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~4_combout  
// ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~4_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg~1 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y17_N59
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y17_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used[1]~1_combout  = ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|read~1_combout  & ( ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg [0] & 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg [0]),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [0]),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|read~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used[1]~1 .lut_mask = 64'h03FF03FF00000000;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used[1]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y17_N32
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y14_N45
cyclonev_lcell_comb \u0|write_data_fifo_tx|readdata[5] (
// Equation(s):
// \u0|write_data_fifo_tx|readdata [5] = ( \u0|write_data_fifo_tx|data_out [5] & ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datad(gnd),
        .datae(!\u0|write_data_fifo_tx|data_out [5]),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|write_data_fifo_tx|readdata [5]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|write_data_fifo_tx|readdata[5] .extended_lut = "off";
defparam \u0|write_data_fifo_tx|readdata[5] .lut_mask = 64'h0000F0F000000000;
defparam \u0|write_data_fifo_tx|readdata[5] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y14_N47
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|write_data_fifo_tx|readdata [5]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y15_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~5 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~5_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [5] & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1]) # 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][5]~q ) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [5] & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][5]~q  & 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1]) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][5]~q ),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~5 .lut_mask = 64'h000F000FFF0FFF0F;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y15_N32
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y15_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~66 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~66_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [5] & ( (\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout  & 
// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout ) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][5]~q ))) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [5] & ( 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][5]~q  & (\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout  & !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout )) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][5]~q ),
        .datac(!\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~66_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~66 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~66 .lut_mask = 64'h03000300030F030F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~66 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y32_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_021|src_payload~12 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_021|src_payload~12_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout  & ( \u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_021|src_payload~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~12 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~12 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y32_N20
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_021|src_payload~12_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y32_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_021|src_payload~14 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_021|src_payload~14_combout  = (\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] & \u0|mm_interconnect_0|cmd_mux_021|saved_grant [1])

        .dataa(gnd),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_021|src_payload~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~14 .lut_mask = 64'h0303030303030303;
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~14 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y32_N53
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_021|src_payload~14_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y32_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_021|src_payload~15 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_021|src_payload~15_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & ( \u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_021|src_payload~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~15 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~15 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y32_N5
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_021|src_payload~15_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y32_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_021|src_payload~16 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_021|src_payload~16_combout  = (\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & \u0|mm_interconnect_0|cmd_mux_021|saved_grant [1])

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_021|src_payload~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~16 .lut_mask = 64'h000F000F000F000F;
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~16 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y32_N59
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_021|src_payload~16_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y32_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_021|src_payload~15_combout  & ( 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1])) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_021|src_payload~15_combout  & ( 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]))) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((\u0|mm_interconnect_0|cmd_mux_021|src_payload~16_combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_021|src_payload~16_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_021|src_payload~15_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .lut_mask = 64'h083B083B08080808;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y32_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout  = ( \u0|mm_interconnect_0|cmd_mux_021|src_payload~14_combout  & ( 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  & ((\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]))) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_021|src_payload~14_combout  & ( 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_021|src_payload~14_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .lut_mask = 64'h0044004400770077;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y32_N17
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .power_up = "low";
// synopsys translate_on

// Location: FF_X30_Y32_N1
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y32_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout  = ( \u0|mm_interconnect_0|cmd_mux_021|src_payload~14_combout  & ( 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] & 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_021|src_payload~14_combout  & ( 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]) # 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_021|src_payload~14_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .lut_mask = 64'h00F300F300C000C0;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y32_N8
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y34_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_021|src_payload~13 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_021|src_payload~13_combout  = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout  & ( \u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_021|src_payload~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~13 .lut_mask = 64'h0F0F0F0F00000000;
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~13 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y34_N50
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_021|src_payload~13_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y34_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2] = ( \u0|mm_interconnect_0|cmd_mux_021|src_payload~13_combout  & ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout  & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] 
// & !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_021|src_payload~13_combout  & ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout  & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]) 
// # (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_021|src_payload~13_combout ),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .lut_mask = 64'h00000000BBBB8888;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y34_N37
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y32_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  = ( \u0|mm_interconnect_0|cmd_mux_021|src_payload~15_combout  & ( 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1])) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_021|src_payload~15_combout  & ( 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]))) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((!\u0|mm_interconnect_0|cmd_mux_021|src_payload~16_combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_021|src_payload~16_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_021|src_payload~15_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .lut_mask = 64'hB380B38080808080;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y32_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  & ( 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]))) # 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|cmd_mux_021|src_payload~14_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_021|src_payload~14_combout ),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .lut_mask = 64'h000000001D1D1D1D;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y32_N25
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y32_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [1] & ( (\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] & 
// (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]))) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .lut_mask = 64'h0000000004000400;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y32_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_021|src_payload~17 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_021|src_payload~17_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~1_combout  & ( \u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_021|src_payload~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~17 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~17 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y32_N14
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_021|src_payload~17_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y32_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1] = ( \u0|mm_interconnect_0|cmd_mux_021|src_payload~17_combout  & ( 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1] & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_021|src_payload~17_combout  & ( 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout  & 
// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_021|src_payload~17_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .lut_mask = 64'h00CF00CF00C000C0;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y32_N44
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y32_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_021|src_payload~18 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_021|src_payload~18_combout  = ( \u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~2_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~2_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_021|src_payload~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~18 .lut_mask = 64'h00000000F0F0F0F0;
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~18 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y32_N23
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_021|src_payload~18_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y32_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0] = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  & ( 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0])) # 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|cmd_mux_021|src_payload~18_combout ))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_021|src_payload~18_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .lut_mask = 64'h00000000F3C0F3C0;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y32_N14
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y32_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  = ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] & ( ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout )) # (\u0|mm_interconnect_0|cmd_mux_021|src_payload~14_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ) # 
// ((\u0|mm_interconnect_0|cmd_mux_021|src_payload~14_combout  & \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_021|src_payload~14_combout ),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .lut_mask = 64'hF1F1F1F1FDFDFDFD;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y32_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout  = ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .lut_mask = 64'hFFFFFFFF00000000;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y32_N56
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y32_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout  = SUM(( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) 
// + ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14  = CARRY(( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) + ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
        .cout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .lut_mask = 64'h0000F0F000003333;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y32_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  = ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  
// & ( (((\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0] & ((\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout )))) 
// # (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0])) ) ) # ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  
// & ( (\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] & (((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [0]))))) 
// ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [0]),
        .datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
        .datag(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .extended_lut = "on";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .lut_mask = 64'h333300503F3F0050;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y32_N43
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y32_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout  = SUM(( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + 
// ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14  ))
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10  = CARRY(( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
        .cout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y32_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  
// & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout  ) ) # ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( (((\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1] & 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout )) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1])) # 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .lut_mask = 64'h5F7F5F7F55555555;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y32_N46
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y32_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout  = SUM(( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + 
// ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10  ))
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6  = CARRY(( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10  ))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
        .cout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .lut_mask = 64'h0000CCCC00000F0F;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y34_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout  & ( 
// \u0|hps_0|fpga_interfaces|h2f_ARADDR [2] & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2])) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg 
// [2]))) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1])))) ) ) ) # ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout  & ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [2] & ( 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2])) # 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]))) ) ) ) # ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout  & ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [2] & ( 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]) # 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]))) ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout  
// & ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [2] & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
        .datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .lut_mask = 64'h30307070303F707F;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y32_N29
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y32_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout  = SUM(( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3] ) + 
// ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3] ) + ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y32_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3] = ( \u0|mm_interconnect_0|cmd_mux_021|src_payload~12_combout  & ( 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3] & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_021|src_payload~12_combout  & ( 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout  & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]) 
// # (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_021|src_payload~12_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .lut_mask = 64'h00BB00BB00880088;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y32_N10
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y32_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3] & 
// ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [3] & \u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]) ) ) ) # ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3] & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// (\u0|hps_0|fpga_interfaces|h2f_ARADDR [3] & \u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]) ) ) ) # ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3] & ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3] & ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3] & 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [3]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
        .datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .lut_mask = 64'h0055FFFF03030303;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y32_N59
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .power_up = "low";
// synopsys translate_on

// Location: FF_X30_Y32_N5
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y14_N24
cyclonev_lcell_comb \u0|counter_rx_fifo|read_mux_out[5]~5 (
// Equation(s):
// \u0|counter_rx_fifo|read_mux_out[5]~5_combout  = ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & ( (\A_SPW_TOP|rx_data|counter [5] & 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|rx_data|counter [5]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|counter_rx_fifo|read_mux_out[5]~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|counter_rx_fifo|read_mux_out[5]~5 .extended_lut = "off";
defparam \u0|counter_rx_fifo|read_mux_out[5]~5 .lut_mask = 64'h3300330000000000;
defparam \u0|counter_rx_fifo|read_mux_out[5]~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y14_N26
dffeas \u0|counter_rx_fifo|readdata[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|counter_rx_fifo|read_mux_out[5]~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|counter_rx_fifo|readdata [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|counter_rx_fifo|readdata[5] .is_wysiwyg = "true";
defparam \u0|counter_rx_fifo|readdata[5] .power_up = "low";
// synopsys translate_on

// Location: FF_X31_Y15_N53
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|counter_rx_fifo|readdata [5]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre[5] .power_up = "low";
// synopsys translate_on

// Location: FF_X31_Y15_N44
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y15_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~5 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~5_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][5]~q  ) ) # ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [5] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [5]),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][5]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~5 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X31_Y15_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|always0~0_combout  = (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0]) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|read~0_combout )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|read~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|always0~0 .lut_mask = 64'hF5F5F5F5F5F5F5F5;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y15_N35
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~5_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y15_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~68 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~68_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0] & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout  & 
// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0] & ((\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [5]))) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0] & 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][5]~q )))) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0] & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][5]~q  & 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][5]~q ),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0]),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [5]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~68_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~68 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~68 .lut_mask = 64'h5050505010D010D0;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~68 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y18_N51
cyclonev_lcell_comb \u0|timecode_tx_data|readdata[5] (
// Equation(s):
// \u0|timecode_tx_data|readdata [5] = ( \u0|timecode_tx_data|data_out [5] & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|timecode_tx_data|data_out [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|timecode_tx_data|readdata [5]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|timecode_tx_data|readdata[5] .extended_lut = "off";
defparam \u0|timecode_tx_data|readdata[5] .lut_mask = 64'h00000000A0A0A0A0;
defparam \u0|timecode_tx_data|readdata[5] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y18_N53
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|timecode_tx_data|readdata [5]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre[5] .power_up = "low";
// synopsys translate_on

// Location: FF_X28_Y16_N43
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~5_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y16_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~5 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~5_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][5]~q  & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [5]) # 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][5]~q  & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [5]) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [5]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~5 .lut_mask = 64'h00F000F00FFF0FFF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y16_N32
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y16_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~67 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~67_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0] & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0] & 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [5])) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0] & ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][5]~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][5]~q  ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [5]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][5]~q ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~67_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~67 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~67 .lut_mask = 64'h0F0F0F0F550F550F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~67 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y16_N20
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y2_N45
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|timecode~6 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|timecode~6_combout  = ( \A_SPW_TOP|SPW|RX|timecode~0_combout  & ( \A_SPW_TOP|SPW|RX|timecode [5] & ( \A_SPW_TOP|SPW|RX|dta_timec_p [5] ) ) ) # ( !\A_SPW_TOP|SPW|RX|timecode~0_combout  & ( \A_SPW_TOP|SPW|RX|timecode [5] ) ) # ( 
// \A_SPW_TOP|SPW|RX|timecode~0_combout  & ( !\A_SPW_TOP|SPW|RX|timecode [5] & ( \A_SPW_TOP|SPW|RX|dta_timec_p [5] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|RX|dta_timec_p [5]),
        .datad(gnd),
        .datae(!\A_SPW_TOP|SPW|RX|timecode~0_combout ),
        .dataf(!\A_SPW_TOP|SPW|RX|timecode [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|timecode~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|timecode~6 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|timecode~6 .lut_mask = 64'h00000F0FFFFF0F0F;
defparam \A_SPW_TOP|SPW|RX|timecode~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y2_N44
dffeas \A_SPW_TOP|SPW|RX|timecode[5] (
        .clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|RX|timecode~6_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(!\A_SPW_TOP|SPW|RX|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|timecode [5]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|timecode[5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|timecode[5] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y14_N18
cyclonev_lcell_comb \u0|timecode_rx|read_mux_out[5] (
// Equation(s):
// \u0|timecode_rx|read_mux_out [5] = ( \A_SPW_TOP|SPW|RX|timecode [5] & ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datad(gnd),
        .datae(!\A_SPW_TOP|SPW|RX|timecode [5]),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|timecode_rx|read_mux_out [5]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|timecode_rx|read_mux_out[5] .extended_lut = "off";
defparam \u0|timecode_rx|read_mux_out[5] .lut_mask = 64'h0000F0F000000000;
defparam \u0|timecode_rx|read_mux_out[5] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y14_N19
dffeas \u0|timecode_rx|readdata[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|timecode_rx|read_mux_out [5]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|timecode_rx|readdata [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|timecode_rx|readdata[5] .is_wysiwyg = "true";
defparam \u0|timecode_rx|readdata[5] .power_up = "low";
// synopsys translate_on

// Location: FF_X25_Y16_N13
dffeas \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|timecode_rx|readdata [5]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[5] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y16_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~5 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~5_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [5] & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1]) # 
// (\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][5]~q ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [5] & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][5]~q ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][5]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~5 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y16_N53
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~5_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][5] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y16_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~69 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~69_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0] & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0] & 
// ((\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [5]))) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0] & (\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][5]~q )) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][5]~q  ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][5]~q ),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0]),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [5]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~69_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~69 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~69 .lut_mask = 64'h555555551D1D1D1D;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~69 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y2_N12
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|rx_data_flag~5 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|rx_data_flag~5_combout  = ( \A_SPW_TOP|SPW|RX|ready_control_p_r~q  & ( (\A_SPW_TOP|SPW|RX|rx_data_flag~0_combout  & \A_SPW_TOP|SPW|RX|rx_data_flag [5]) ) ) # ( !\A_SPW_TOP|SPW|RX|ready_control_p_r~q  & ( 
// (!\A_SPW_TOP|SPW|RX|data~0_combout  & (((\A_SPW_TOP|SPW|RX|rx_data_flag~0_combout  & \A_SPW_TOP|SPW|RX|rx_data_flag [5])) # (\A_SPW_TOP|SPW|RX|dta_timec_p [5]))) # (\A_SPW_TOP|SPW|RX|data~0_combout  & (((\A_SPW_TOP|SPW|RX|rx_data_flag [5])))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|data~0_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag~0_combout ),
        .datac(!\A_SPW_TOP|SPW|RX|dta_timec_p [5]),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datae(!\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|rx_data_flag~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_data_flag~5 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|rx_data_flag~5 .lut_mask = 64'h0A7F00330A7F0033;
defparam \A_SPW_TOP|SPW|RX|rx_data_flag~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y2_N17
dffeas \A_SPW_TOP|SPW|RX|rx_data_flag[5] (
        .clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|RX|rx_data_flag~5_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(!\A_SPW_TOP|SPW|RX|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_data_flag[5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|rx_data_flag[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X35_Y8_N33
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector481~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector481~0_combout  = ( \A_SPW_TOP|rx_data|Selector478~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [5])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux3~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector478~0_combout  & ( \A_SPW_TOP|rx_data|mem[51][5]~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datab(!\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[51][5]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector478~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector481~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector481~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector481~0 .lut_mask = 64'h00FF00FF53535353;
defparam \A_SPW_TOP|rx_data|Selector481~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X33_Y8_N26
dffeas \A_SPW_TOP|rx_data|mem[51][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector481~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[51][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[51][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[51][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X33_Y8_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector517~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector517~0_combout  = ( \A_SPW_TOP|rx_data|mem[55][5]~q  & ( (!\A_SPW_TOP|rx_data|Selector514~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [5])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux3~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[55][5]~q  & ( (\A_SPW_TOP|rx_data|Selector514~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [5])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux3~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datab(!\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|Selector514~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[55][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector517~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector517~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector517~0 .lut_mask = 64'h00530053FF53FF53;
defparam \A_SPW_TOP|rx_data|Selector517~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X33_Y8_N35
dffeas \A_SPW_TOP|rx_data|mem[55][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector517~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[55][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[55][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[55][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X33_Y8_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector553~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector553~0_combout  = ( \A_SPW_TOP|rx_data|mem[59][5]~q  & ( (!\A_SPW_TOP|rx_data|Selector550~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [5]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux3~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[59][5]~q  & ( (\A_SPW_TOP|rx_data|Selector550~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [5]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux3~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector550~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[59][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector553~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector553~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector553~0 .lut_mask = 64'h010B010BF1FBF1FB;
defparam \A_SPW_TOP|rx_data|Selector553~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X33_Y8_N32
dffeas \A_SPW_TOP|rx_data|mem[59][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector553~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[59][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[59][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[59][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X33_Y8_N15
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector589~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector589~0_combout  = ( \A_SPW_TOP|rx_data|mem[63][5]~q  & ( (!\A_SPW_TOP|rx_data|Selector586~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [5]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux3~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[63][5]~q  & ( (\A_SPW_TOP|rx_data|Selector586~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [5]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux3~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector586~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[63][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector589~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector589~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector589~0 .lut_mask = 64'h010B010BF1FBF1FB;
defparam \A_SPW_TOP|rx_data|Selector589~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X33_Y8_N50
dffeas \A_SPW_TOP|rx_data|mem[63][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector589~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[63][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[63][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[63][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X33_Y8_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux3~18 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux3~18_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [2] & ( \A_SPW_TOP|rx_data|mem[63][5]~q  & ( (\A_SPW_TOP|rx_data|mem[55][5]~q ) # (\A_SPW_TOP|rx_data|wr_ptr [3]) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [2] & ( 
// \A_SPW_TOP|rx_data|mem[63][5]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|mem[51][5]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [3] & ((\A_SPW_TOP|rx_data|mem[59][5]~q ))) ) ) ) # ( \A_SPW_TOP|rx_data|wr_ptr [2] & ( 
// !\A_SPW_TOP|rx_data|mem[63][5]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [3] & \A_SPW_TOP|rx_data|mem[55][5]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [2] & ( !\A_SPW_TOP|rx_data|mem[63][5]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|mem[51][5]~q 
// )) # (\A_SPW_TOP|rx_data|wr_ptr [3] & ((\A_SPW_TOP|rx_data|mem[59][5]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[51][5]~q ),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datac(!\A_SPW_TOP|rx_data|mem[55][5]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[59][5]~q ),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .dataf(!\A_SPW_TOP|rx_data|mem[63][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux3~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux3~18 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux3~18 .lut_mask = 64'h44770C0C44773F3F;
defparam \A_SPW_TOP|rx_data|Mux3~18 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X33_Y8_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector337~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector337~0_combout  = ( \A_SPW_TOP|rx_data|Selector334~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [5]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux3~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector334~0_combout  & ( \A_SPW_TOP|rx_data|mem[35][5]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|mem[35][5]~q ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector334~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector337~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector337~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector337~0 .lut_mask = 64'h0F0F0F0F11BB11BB;
defparam \A_SPW_TOP|rx_data|Selector337~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X33_Y8_N53
dffeas \A_SPW_TOP|rx_data|mem[35][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector337~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[35][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[35][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[35][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X33_Y8_N45
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector445~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector445~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector442~0_combout  & ((\A_SPW_TOP|rx_data|mem[47][5]~q ))) # (\A_SPW_TOP|rx_data|Selector442~0_combout  & 
// (\A_SPW_TOP|rx_data|Mux3~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector442~0_combout  & ((\A_SPW_TOP|rx_data|mem[47][5]~q ))) # (\A_SPW_TOP|rx_data|Selector442~0_combout  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [5])) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datab(!\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector442~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[47][5]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector445~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector445~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector445~0 .lut_mask = 64'h05F505F503F303F3;
defparam \A_SPW_TOP|rx_data|Selector445~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X33_Y8_N59
dffeas \A_SPW_TOP|rx_data|mem[47][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector445~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[47][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[47][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[47][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X33_Y8_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector409~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector409~0_combout  = ( \A_SPW_TOP|rx_data|Selector406~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [5]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux3~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector406~0_combout  & ( \A_SPW_TOP|rx_data|mem[43][5]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .datac(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datad(!\A_SPW_TOP|rx_data|mem[43][5]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector406~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector409~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector409~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector409~0 .lut_mask = 64'h00FF00FF1B1B1B1B;
defparam \A_SPW_TOP|rx_data|Selector409~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X33_Y8_N29
dffeas \A_SPW_TOP|rx_data|mem[43][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector409~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[43][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[43][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[43][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X33_Y8_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector373~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector373~0_combout  = ( \A_SPW_TOP|rx_data|mem[39][5]~q  & ( (!\A_SPW_TOP|rx_data|Selector370~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [5]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux3~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[39][5]~q  & ( (\A_SPW_TOP|rx_data|Selector370~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [5]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux3~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector370~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[39][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector373~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector373~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector373~0 .lut_mask = 64'h010B010BF1FBF1FB;
defparam \A_SPW_TOP|rx_data|Selector373~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X33_Y8_N20
dffeas \A_SPW_TOP|rx_data|mem[39][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector373~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[39][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[39][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[39][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X33_Y8_N33
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux3~16 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux3~16_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [2] & ( \A_SPW_TOP|rx_data|mem[39][5]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [3]) # (\A_SPW_TOP|rx_data|mem[47][5]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [2] & ( 
// \A_SPW_TOP|rx_data|mem[39][5]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|mem[35][5]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [3] & ((\A_SPW_TOP|rx_data|mem[43][5]~q ))) ) ) ) # ( \A_SPW_TOP|rx_data|wr_ptr [2] & ( 
// !\A_SPW_TOP|rx_data|mem[39][5]~q  & ( (\A_SPW_TOP|rx_data|mem[47][5]~q  & \A_SPW_TOP|rx_data|wr_ptr [3]) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [2] & ( !\A_SPW_TOP|rx_data|mem[39][5]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|mem[35][5]~q 
// )) # (\A_SPW_TOP|rx_data|wr_ptr [3] & ((\A_SPW_TOP|rx_data|mem[43][5]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[35][5]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[47][5]~q ),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datad(!\A_SPW_TOP|rx_data|mem[43][5]~q ),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .dataf(!\A_SPW_TOP|rx_data|mem[39][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux3~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux3~16 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux3~16 .lut_mask = 64'h505F0303505FF3F3;
defparam \A_SPW_TOP|rx_data|Mux3~16 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X32_Y8_N15
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector265~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector265~0_combout  = ( \A_SPW_TOP|rx_data|mem[27][5]~q  & ( (!\A_SPW_TOP|rx_data|Selector262~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [5]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux3~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[27][5]~q  & ( (\A_SPW_TOP|rx_data|Selector262~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [5]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux3~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .datab(!\A_SPW_TOP|rx_data|Selector262~0_combout ),
        .datac(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[27][5]~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector265~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector265~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector265~0 .lut_mask = 64'h0311CFDD0311CFDD;
defparam \A_SPW_TOP|rx_data|Selector265~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X32_Y8_N23
dffeas \A_SPW_TOP|rx_data|mem[27][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector265~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[27][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[27][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[27][5] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X32_Y8_N51
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector193~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector193~0_combout  = ( \A_SPW_TOP|rx_data|mem[19][5]~q  & ( (!\A_SPW_TOP|rx_data|Selector190~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [5]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux3~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[19][5]~q  & ( (\A_SPW_TOP|rx_data|Selector190~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [5]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux3~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datac(!\A_SPW_TOP|rx_data|Selector190~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[19][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector193~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector193~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector193~0 .lut_mask = 64'h03050305F3F5F3F5;
defparam \A_SPW_TOP|rx_data|Selector193~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X32_Y8_N35
dffeas \A_SPW_TOP|rx_data|mem[19][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector193~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[19][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[19][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[19][5] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X32_Y8_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector301~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector301~0_combout  = ( \A_SPW_TOP|rx_data|Selector298~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [5]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux3~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector298~0_combout  & ( \A_SPW_TOP|rx_data|mem[31][5]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datac(!\A_SPW_TOP|rx_data|mem[31][5]~q ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector298~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector301~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector301~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector301~0 .lut_mask = 64'h0F0F0F0F33553355;
defparam \A_SPW_TOP|rx_data|Selector301~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X32_Y8_N26
dffeas \A_SPW_TOP|rx_data|mem[31][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector301~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[31][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[31][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[31][5] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X32_Y8_N9
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector229~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector229~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector226~0_combout  & ((\A_SPW_TOP|rx_data|mem[23][5]~q ))) # (\A_SPW_TOP|rx_data|Selector226~0_combout  & 
// (\A_SPW_TOP|rx_data|Mux3~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector226~0_combout  & ((\A_SPW_TOP|rx_data|mem[23][5]~q ))) # (\A_SPW_TOP|rx_data|Selector226~0_combout  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [5])) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datac(!\A_SPW_TOP|rx_data|mem[23][5]~q ),
        .datad(!\A_SPW_TOP|rx_data|Selector226~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector229~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector229~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector229~0 .lut_mask = 64'h0F330F330F550F55;
defparam \A_SPW_TOP|rx_data|Selector229~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X32_Y8_N14
dffeas \A_SPW_TOP|rx_data|mem[23][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector229~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[23][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[23][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[23][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y8_N21
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux3~17 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux3~17_combout  = ( \A_SPW_TOP|rx_data|mem[31][5]~q  & ( \A_SPW_TOP|rx_data|mem[23][5]~q  & ( ((!\A_SPW_TOP|rx_data|wr_ptr [3] & ((\A_SPW_TOP|rx_data|mem[19][5]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|mem[27][5]~q 
// ))) # (\A_SPW_TOP|rx_data|wr_ptr [2]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[31][5]~q  & ( \A_SPW_TOP|rx_data|mem[23][5]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [3] & (((\A_SPW_TOP|rx_data|mem[19][5]~q ) # (\A_SPW_TOP|rx_data|wr_ptr [2])))) # 
// (\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|mem[27][5]~q  & (!\A_SPW_TOP|rx_data|wr_ptr [2]))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[31][5]~q  & ( !\A_SPW_TOP|rx_data|mem[23][5]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [3] & (((!\A_SPW_TOP|rx_data|wr_ptr 
// [2] & \A_SPW_TOP|rx_data|mem[19][5]~q )))) # (\A_SPW_TOP|rx_data|wr_ptr [3] & (((\A_SPW_TOP|rx_data|wr_ptr [2])) # (\A_SPW_TOP|rx_data|mem[27][5]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[31][5]~q  & ( !\A_SPW_TOP|rx_data|mem[23][5]~q  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [2] & ((!\A_SPW_TOP|rx_data|wr_ptr [3] & ((\A_SPW_TOP|rx_data|mem[19][5]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|mem[27][5]~q )))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[27][5]~q ),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datad(!\A_SPW_TOP|rx_data|mem[19][5]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[31][5]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[23][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux3~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux3~17 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux3~17 .lut_mask = 64'h10D013D31CDC1FDF;
defparam \A_SPW_TOP|rx_data|Mux3~17 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X31_Y8_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector121~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector121~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector118~0_combout  & ((\A_SPW_TOP|rx_data|mem[11][5]~q ))) # (\A_SPW_TOP|rx_data|Selector118~0_combout  & 
// (\A_SPW_TOP|rx_data|Mux3~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector118~0_combout  & ((\A_SPW_TOP|rx_data|mem[11][5]~q ))) # (\A_SPW_TOP|rx_data|Selector118~0_combout  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [5])) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datab(!\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector118~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[11][5]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector121~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector121~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector121~0 .lut_mask = 64'h05F505F503F303F3;
defparam \A_SPW_TOP|rx_data|Selector121~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X32_Y8_N29
dffeas \A_SPW_TOP|rx_data|mem[11][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector121~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[11][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[11][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[11][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y8_N9
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector85~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector85~0_combout  = ( \A_SPW_TOP|rx_data|Selector82~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [5])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux3~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector82~0_combout  & ( \A_SPW_TOP|rx_data|mem[7][5]~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datab(!\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[7][5]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector82~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector85~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector85~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector85~0 .lut_mask = 64'h00FF00FF53535353;
defparam \A_SPW_TOP|rx_data|Selector85~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X32_Y8_N17
dffeas \A_SPW_TOP|rx_data|mem[7][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector85~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[7][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[7][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[7][5] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X32_Y8_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector157~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector157~0_combout  = ( \A_SPW_TOP|rx_data|Selector154~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [5]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux3~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector154~0_combout  & ( \A_SPW_TOP|rx_data|mem[15][5]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[15][5]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector154~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector157~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector157~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector157~0 .lut_mask = 64'h00FF00FF35353535;
defparam \A_SPW_TOP|rx_data|Selector157~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X32_Y8_N5
dffeas \A_SPW_TOP|rx_data|mem[15][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector157~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[15][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[15][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[15][5] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X32_Y8_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector49~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector49~0_combout  = ( \A_SPW_TOP|rx_data|Selector46~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [5])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux3~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector46~0_combout  & ( \A_SPW_TOP|rx_data|mem[3][5]~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datab(!\A_SPW_TOP|rx_data|mem[3][5]~q ),
        .datac(!\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector46~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector49~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector49~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector49~0 .lut_mask = 64'h33333333550F550F;
defparam \A_SPW_TOP|rx_data|Selector49~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X32_Y8_N47
dffeas \A_SPW_TOP|rx_data|mem[3][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector49~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[3][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[3][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[3][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y8_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux3~15 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux3~15_combout  = ( \A_SPW_TOP|rx_data|mem[15][5]~q  & ( \A_SPW_TOP|rx_data|mem[3][5]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [3] & (((!\A_SPW_TOP|rx_data|wr_ptr [2]) # (\A_SPW_TOP|rx_data|mem[7][5]~q )))) # (\A_SPW_TOP|rx_data|wr_ptr [3] & 
// (((\A_SPW_TOP|rx_data|wr_ptr [2])) # (\A_SPW_TOP|rx_data|mem[11][5]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[15][5]~q  & ( \A_SPW_TOP|rx_data|mem[3][5]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [3] & (((!\A_SPW_TOP|rx_data|wr_ptr [2]) # 
// (\A_SPW_TOP|rx_data|mem[7][5]~q )))) # (\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|mem[11][5]~q  & ((!\A_SPW_TOP|rx_data|wr_ptr [2])))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[15][5]~q  & ( !\A_SPW_TOP|rx_data|mem[3][5]~q  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [3] & (((\A_SPW_TOP|rx_data|mem[7][5]~q  & \A_SPW_TOP|rx_data|wr_ptr [2])))) # (\A_SPW_TOP|rx_data|wr_ptr [3] & (((\A_SPW_TOP|rx_data|wr_ptr [2])) # (\A_SPW_TOP|rx_data|mem[11][5]~q ))) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|mem[15][5]~q  & ( !\A_SPW_TOP|rx_data|mem[3][5]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [3] & (((\A_SPW_TOP|rx_data|mem[7][5]~q  & \A_SPW_TOP|rx_data|wr_ptr [2])))) # (\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|mem[11][5]~q  & 
// ((!\A_SPW_TOP|rx_data|wr_ptr [2])))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[11][5]~q ),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datac(!\A_SPW_TOP|rx_data|mem[7][5]~q ),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datae(!\A_SPW_TOP|rx_data|mem[15][5]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[3][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux3~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux3~15 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux3~15 .lut_mask = 64'h110C113FDD0CDD3F;
defparam \A_SPW_TOP|rx_data|Mux3~15 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y8_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux3~19 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux3~19_combout  = ( \A_SPW_TOP|rx_data|Mux3~17_combout  & ( \A_SPW_TOP|rx_data|Mux3~15_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [5]) # ((!\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|Mux3~16_combout ))) # 
// (\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|Mux3~18_combout ))) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux3~17_combout  & ( \A_SPW_TOP|rx_data|Mux3~15_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & (((!\A_SPW_TOP|rx_data|wr_ptr [4])))) # 
// (\A_SPW_TOP|rx_data|wr_ptr [5] & ((!\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|Mux3~16_combout ))) # (\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|Mux3~18_combout )))) ) ) ) # ( \A_SPW_TOP|rx_data|Mux3~17_combout  & ( 
// !\A_SPW_TOP|rx_data|Mux3~15_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & (((\A_SPW_TOP|rx_data|wr_ptr [4])))) # (\A_SPW_TOP|rx_data|wr_ptr [5] & ((!\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|Mux3~16_combout ))) # (\A_SPW_TOP|rx_data|wr_ptr [4] 
// & (\A_SPW_TOP|rx_data|Mux3~18_combout )))) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux3~17_combout  & ( !\A_SPW_TOP|rx_data|Mux3~15_combout  & ( (\A_SPW_TOP|rx_data|wr_ptr [5] & ((!\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|Mux3~16_combout ))) # 
// (\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|Mux3~18_combout )))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux3~18_combout ),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datac(!\A_SPW_TOP|rx_data|Mux3~16_combout ),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datae(!\A_SPW_TOP|rx_data|Mux3~17_combout ),
        .dataf(!\A_SPW_TOP|rx_data|Mux3~15_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux3~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux3~19 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux3~19 .lut_mask = 64'h031103DDCF11CFDD;
defparam \A_SPW_TOP|rx_data|Mux3~19 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X36_Y3_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector58~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector58~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector55~0_combout  & ((\A_SPW_TOP|rx_data|mem[4][5]~q ))) # (\A_SPW_TOP|rx_data|Selector55~0_combout  & (\A_SPW_TOP|rx_data|Mux3~20_combout 
// )) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector55~0_combout  & ((\A_SPW_TOP|rx_data|mem[4][5]~q ))) # (\A_SPW_TOP|rx_data|Selector55~0_combout  & (\A_SPW_TOP|SPW|RX|rx_data_flag [5])) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datac(!\A_SPW_TOP|rx_data|Selector55~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[4][5]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector58~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector58~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector58~0 .lut_mask = 64'h03F303F305F505F5;
defparam \A_SPW_TOP|rx_data|Selector58~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X36_Y3_N38
dffeas \A_SPW_TOP|rx_data|mem[4][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector58~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[4][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[4][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[4][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X33_Y5_N9
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector346~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector346~0_combout  = ( \A_SPW_TOP|rx_data|mem[36][5]~q  & ( (!\A_SPW_TOP|rx_data|Selector343~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [5]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux3~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[36][5]~q  & ( (\A_SPW_TOP|rx_data|Selector343~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [5]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux3~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Selector343~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[36][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector346~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector346~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector346~0 .lut_mask = 64'h010D010DF1FDF1FD;
defparam \A_SPW_TOP|rx_data|Selector346~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X33_Y5_N14
dffeas \A_SPW_TOP|rx_data|mem[36][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector346~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[36][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[36][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[36][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X36_Y3_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector130~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector130~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector127~0_combout  & ((\A_SPW_TOP|rx_data|mem[12][5]~q ))) # (\A_SPW_TOP|rx_data|Selector127~0_combout  & 
// (\A_SPW_TOP|rx_data|Mux3~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector127~0_combout  & ((\A_SPW_TOP|rx_data|mem[12][5]~q ))) # (\A_SPW_TOP|rx_data|Selector127~0_combout  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [5])) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datac(!\A_SPW_TOP|rx_data|Selector127~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[12][5]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector130~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector130~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector130~0 .lut_mask = 64'h03F303F305F505F5;
defparam \A_SPW_TOP|rx_data|Selector130~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X36_Y3_N56
dffeas \A_SPW_TOP|rx_data|mem[12][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector130~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[12][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[12][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[12][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X33_Y5_N57
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector418~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector418~0_combout  = ( \A_SPW_TOP|rx_data|mem[44][5]~q  & ( (!\A_SPW_TOP|rx_data|Selector415~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [5]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux3~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[44][5]~q  & ( (\A_SPW_TOP|rx_data|Selector415~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [5]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux3~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Selector415~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[44][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector418~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector418~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector418~0 .lut_mask = 64'h010D010DF1FDF1FD;
defparam \A_SPW_TOP|rx_data|Selector418~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X33_Y5_N50
dffeas \A_SPW_TOP|rx_data|mem[44][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector418~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[44][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[44][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[44][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X33_Y5_N45
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux3~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux3~1_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [3] & ( \A_SPW_TOP|rx_data|mem[44][5]~q  & ( (\A_SPW_TOP|rx_data|wr_ptr [5]) # (\A_SPW_TOP|rx_data|mem[12][5]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [3] & ( \A_SPW_TOP|rx_data|mem[44][5]~q 
//  & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|mem[4][5]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [5] & ((\A_SPW_TOP|rx_data|mem[36][5]~q ))) ) ) ) # ( \A_SPW_TOP|rx_data|wr_ptr [3] & ( !\A_SPW_TOP|rx_data|mem[44][5]~q  & ( 
// (\A_SPW_TOP|rx_data|mem[12][5]~q  & !\A_SPW_TOP|rx_data|wr_ptr [5]) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [3] & ( !\A_SPW_TOP|rx_data|mem[44][5]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|mem[4][5]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [5] & 
// ((\A_SPW_TOP|rx_data|mem[36][5]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[4][5]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[36][5]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[12][5]~q ),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .dataf(!\A_SPW_TOP|rx_data|mem[44][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux3~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux3~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux3~1 .lut_mask = 64'h55330F0055330FFF;
defparam \A_SPW_TOP|rx_data|Mux3~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X33_Y5_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector274~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector274~0_combout  = ( \A_SPW_TOP|rx_data|mem[28][5]~q  & ( (!\A_SPW_TOP|rx_data|Selector271~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [5]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux3~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[28][5]~q  & ( (\A_SPW_TOP|rx_data|Selector271~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [5]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux3~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Selector271~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[28][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector274~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector274~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector274~0 .lut_mask = 64'h010D010DF1FDF1FD;
defparam \A_SPW_TOP|rx_data|Selector274~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X33_Y5_N26
dffeas \A_SPW_TOP|rx_data|mem[28][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector274~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[28][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[28][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[28][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X33_Y5_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector202~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector202~0_combout  = ( \A_SPW_TOP|rx_data|mem[20][5]~q  & ( (!\A_SPW_TOP|rx_data|Selector199~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [5]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux3~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[20][5]~q  & ( (\A_SPW_TOP|rx_data|Selector199~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [5]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux3~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Selector199~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[20][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector202~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector202~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector202~0 .lut_mask = 64'h010D010DF1FDF1FD;
defparam \A_SPW_TOP|rx_data|Selector202~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X33_Y5_N44
dffeas \A_SPW_TOP|rx_data|mem[20][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector202~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[20][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[20][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[20][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X33_Y5_N39
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector562~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector562~0_combout  = ( \A_SPW_TOP|rx_data|Selector559~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [5]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux3~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector559~0_combout  & ( \A_SPW_TOP|rx_data|mem[60][5]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datad(!\A_SPW_TOP|rx_data|mem[60][5]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector559~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector562~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector562~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector562~0 .lut_mask = 64'h00FF00FF1D1D1D1D;
defparam \A_SPW_TOP|rx_data|Selector562~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X33_Y5_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|mem[60][5]~feeder (
// Equation(s):
// \A_SPW_TOP|rx_data|mem[60][5]~feeder_combout  = ( \A_SPW_TOP|rx_data|Selector562~0_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector562~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|mem[60][5]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[60][5]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|mem[60][5]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|rx_data|mem[60][5]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X33_Y5_N2
dffeas \A_SPW_TOP|rx_data|mem[60][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|rx_data|mem[60][5]~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[60][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[60][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[60][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X33_Y5_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector490~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector490~0_combout  = ( \A_SPW_TOP|rx_data|mem[52][5]~q  & ( (!\A_SPW_TOP|rx_data|Selector487~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [5]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux3~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[52][5]~q  & ( (\A_SPW_TOP|rx_data|Selector487~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [5]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux3~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Selector487~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[52][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector490~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector490~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector490~0 .lut_mask = 64'h010D010DF1FDF1FD;
defparam \A_SPW_TOP|rx_data|Selector490~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X33_Y5_N32
dffeas \A_SPW_TOP|rx_data|mem[52][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector490~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[52][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[52][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[52][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X33_Y5_N27
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux3~3 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux3~3_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [5] & ( \A_SPW_TOP|rx_data|mem[52][5]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [3]) # (\A_SPW_TOP|rx_data|mem[60][5]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [5] & ( 
// \A_SPW_TOP|rx_data|mem[52][5]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [3] & ((\A_SPW_TOP|rx_data|mem[20][5]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|mem[28][5]~q )) ) ) ) # ( \A_SPW_TOP|rx_data|wr_ptr [5] & ( 
// !\A_SPW_TOP|rx_data|mem[52][5]~q  & ( (\A_SPW_TOP|rx_data|wr_ptr [3] & \A_SPW_TOP|rx_data|mem[60][5]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [5] & ( !\A_SPW_TOP|rx_data|mem[52][5]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [3] & ((\A_SPW_TOP|rx_data|mem[20][5]~q 
// ))) # (\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|mem[28][5]~q )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[28][5]~q ),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datac(!\A_SPW_TOP|rx_data|mem[20][5]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[60][5]~q ),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .dataf(!\A_SPW_TOP|rx_data|mem[52][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux3~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux3~3 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux3~3 .lut_mask = 64'h1D1D00331D1DCCFF;
defparam \A_SPW_TOP|rx_data|Mux3~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y7_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector454~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector454~0_combout  = ( \A_SPW_TOP|rx_data|Selector451~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [5])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux3~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector451~0_combout  & ( \A_SPW_TOP|rx_data|mem[48][5]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datac(!\A_SPW_TOP|rx_data|mem[48][5]~q ),
        .datad(!\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector451~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector454~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector454~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector454~0 .lut_mask = 64'h0F0F0F0F22772277;
defparam \A_SPW_TOP|rx_data|Selector454~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y7_N8
dffeas \A_SPW_TOP|rx_data|mem[48][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector454~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[48][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[48][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[48][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y7_N39
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector526~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector526~0_combout  = ( \A_SPW_TOP|rx_data|Selector523~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [5])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux3~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector523~0_combout  & ( \A_SPW_TOP|rx_data|mem[56][5]~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datab(!\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|mem[56][5]~q ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector523~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector526~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector526~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector526~0 .lut_mask = 64'h0F0F0F0F55335533;
defparam \A_SPW_TOP|rx_data|Selector526~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y7_N14
dffeas \A_SPW_TOP|rx_data|mem[56][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector526~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[56][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[56][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[56][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y7_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector238~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector238~0_combout  = ( \A_SPW_TOP|rx_data|mem[24][5]~q  & ( (!\A_SPW_TOP|rx_data|Selector235~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [5])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux3~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[24][5]~q  & ( (\A_SPW_TOP|rx_data|Selector235~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [5])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux3~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datab(!\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector235~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[24][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector238~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector238~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector238~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|rx_data|Selector238~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y7_N20
dffeas \A_SPW_TOP|rx_data|mem[24][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector238~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[24][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[24][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[24][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y7_N27
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector166~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector166~0_combout  = ( \A_SPW_TOP|rx_data|mem[16][5]~q  & ( (!\A_SPW_TOP|rx_data|Selector163~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [5])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux3~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[16][5]~q  & ( (\A_SPW_TOP|rx_data|Selector163~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [5])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux3~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datab(!\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector163~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[16][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector166~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector166~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector166~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|rx_data|Selector166~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y7_N32
dffeas \A_SPW_TOP|rx_data|mem[16][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector166~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[16][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[16][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[16][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y7_N33
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux3~2 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux3~2_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [3] & ( \A_SPW_TOP|rx_data|mem[16][5]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & ((\A_SPW_TOP|rx_data|mem[24][5]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|mem[56][5]~q )) ) 
// ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [3] & ( \A_SPW_TOP|rx_data|mem[16][5]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [5]) # (\A_SPW_TOP|rx_data|mem[48][5]~q ) ) ) ) # ( \A_SPW_TOP|rx_data|wr_ptr [3] & ( !\A_SPW_TOP|rx_data|mem[16][5]~q  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [5] & ((\A_SPW_TOP|rx_data|mem[24][5]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|mem[56][5]~q )) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [3] & ( !\A_SPW_TOP|rx_data|mem[16][5]~q  & ( (\A_SPW_TOP|rx_data|wr_ptr 
// [5] & \A_SPW_TOP|rx_data|mem[48][5]~q ) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datab(!\A_SPW_TOP|rx_data|mem[48][5]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[56][5]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[24][5]~q ),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .dataf(!\A_SPW_TOP|rx_data|mem[16][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux3~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux3~2 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux3~2 .lut_mask = 64'h111105AFBBBB05AF;
defparam \A_SPW_TOP|rx_data|Mux3~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y7_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector310~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector310~0_combout  = ( \A_SPW_TOP|rx_data|mem[32][5]~q  & ( (!\A_SPW_TOP|rx_data|Selector307~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [5])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux3~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[32][5]~q  & ( (\A_SPW_TOP|rx_data|Selector307~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [5])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux3~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datab(!\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector307~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[32][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector310~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector310~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector310~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|rx_data|Selector310~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y7_N35
dffeas \A_SPW_TOP|rx_data|mem[32][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector310~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[32][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[32][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[32][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y7_N57
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector382~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector382~0_combout  = ( \A_SPW_TOP|SPW|RX|rx_data_flag [5] & ( (!\A_SPW_TOP|rx_data|Selector379~0_combout  & (((\A_SPW_TOP|rx_data|mem[40][5]~q )))) # (\A_SPW_TOP|rx_data|Selector379~0_combout  & 
// ((!\A_SPW_TOP|rx_data|state_data_write.00~q ) # ((\A_SPW_TOP|rx_data|Mux3~20_combout )))) ) ) # ( !\A_SPW_TOP|SPW|RX|rx_data_flag [5] & ( (!\A_SPW_TOP|rx_data|Selector379~0_combout  & (((\A_SPW_TOP|rx_data|mem[40][5]~q )))) # 
// (\A_SPW_TOP|rx_data|Selector379~0_combout  & (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux3~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[40][5]~q ),
        .datac(!\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .datad(!\A_SPW_TOP|rx_data|Selector379~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector382~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector382~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector382~0 .lut_mask = 64'h3305330533AF33AF;
defparam \A_SPW_TOP|rx_data|Selector382~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y7_N44
dffeas \A_SPW_TOP|rx_data|mem[40][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector382~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[40][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[40][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[40][5] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X32_Y5_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector94~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector94~0_combout  = ( \A_SPW_TOP|rx_data|Selector91~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [5])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux3~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector91~0_combout  & ( \A_SPW_TOP|rx_data|mem[8][5]~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datab(!\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|mem[8][5]~q ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector91~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector94~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector94~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector94~0 .lut_mask = 64'h0F0F0F0F55335533;
defparam \A_SPW_TOP|rx_data|Selector94~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X32_Y5_N59
dffeas \A_SPW_TOP|rx_data|mem[8][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector94~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[8][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[8][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[8][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X33_Y5_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector22~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector22~0_combout  = ( \A_SPW_TOP|rx_data|Selector19~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [5]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux3~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector19~0_combout  & ( \A_SPW_TOP|rx_data|mem[0][5]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datac(!\A_SPW_TOP|rx_data|mem[0][5]~q ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector19~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector22~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector22~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector22~0 .lut_mask = 64'h0F0F0F0F33553355;
defparam \A_SPW_TOP|rx_data|Selector22~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X33_Y5_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|mem[0][5]~feeder (
// Equation(s):
// \A_SPW_TOP|rx_data|mem[0][5]~feeder_combout  = ( \A_SPW_TOP|rx_data|Selector22~0_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector22~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|mem[0][5]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[0][5]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|mem[0][5]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|rx_data|mem[0][5]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X33_Y5_N5
dffeas \A_SPW_TOP|rx_data|mem[0][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|rx_data|mem[0][5]~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[0][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[0][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[0][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y7_N15
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux3~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux3~0_combout  = ( \A_SPW_TOP|rx_data|mem[0][5]~q  & ( \A_SPW_TOP|rx_data|wr_ptr [5] & ( (!\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|mem[32][5]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [3] & ((\A_SPW_TOP|rx_data|mem[40][5]~q ))) ) ) 
// ) # ( !\A_SPW_TOP|rx_data|mem[0][5]~q  & ( \A_SPW_TOP|rx_data|wr_ptr [5] & ( (!\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|mem[32][5]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [3] & ((\A_SPW_TOP|rx_data|mem[40][5]~q ))) ) ) ) # ( 
// \A_SPW_TOP|rx_data|mem[0][5]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [5] & ( (!\A_SPW_TOP|rx_data|wr_ptr [3]) # (\A_SPW_TOP|rx_data|mem[8][5]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[0][5]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [5] & ( (\A_SPW_TOP|rx_data|wr_ptr [3] & 
// \A_SPW_TOP|rx_data|mem[8][5]~q ) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[32][5]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[40][5]~q ),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datad(!\A_SPW_TOP|rx_data|mem[8][5]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[0][5]~q ),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux3~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux3~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux3~0 .lut_mask = 64'h000FF0FF53535353;
defparam \A_SPW_TOP|rx_data|Mux3~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X31_Y7_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux3~4 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux3~4_combout  = ( \A_SPW_TOP|rx_data|Mux3~2_combout  & ( \A_SPW_TOP|rx_data|Mux3~0_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2]) # ((!\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|Mux3~1_combout )) # (\A_SPW_TOP|rx_data|wr_ptr 
// [4] & ((\A_SPW_TOP|rx_data|Mux3~3_combout )))) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux3~2_combout  & ( \A_SPW_TOP|rx_data|Mux3~0_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & (((!\A_SPW_TOP|rx_data|wr_ptr [4])))) # (\A_SPW_TOP|rx_data|wr_ptr [2] & 
// ((!\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|Mux3~1_combout )) # (\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|Mux3~3_combout ))))) ) ) ) # ( \A_SPW_TOP|rx_data|Mux3~2_combout  & ( !\A_SPW_TOP|rx_data|Mux3~0_combout  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [2] & (((\A_SPW_TOP|rx_data|wr_ptr [4])))) # (\A_SPW_TOP|rx_data|wr_ptr [2] & ((!\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|Mux3~1_combout )) # (\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|Mux3~3_combout ))))) 
// ) ) ) # ( !\A_SPW_TOP|rx_data|Mux3~2_combout  & ( !\A_SPW_TOP|rx_data|Mux3~0_combout  & ( (\A_SPW_TOP|rx_data|wr_ptr [2] & ((!\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|Mux3~1_combout )) # (\A_SPW_TOP|rx_data|wr_ptr [4] & 
// ((\A_SPW_TOP|rx_data|Mux3~3_combout ))))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datab(!\A_SPW_TOP|rx_data|Mux3~1_combout ),
        .datac(!\A_SPW_TOP|rx_data|Mux3~3_combout ),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datae(!\A_SPW_TOP|rx_data|Mux3~2_combout ),
        .dataf(!\A_SPW_TOP|rx_data|Mux3~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux3~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux3~4 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux3~4 .lut_mask = 64'h110511AFBB05BBAF;
defparam \A_SPW_TOP|rx_data|Mux3~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y8_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector436~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector436~0_combout  = ( \A_SPW_TOP|rx_data|Selector433~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [5])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux3~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector433~0_combout  & ( \A_SPW_TOP|rx_data|mem[46][5]~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datab(!\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|mem[46][5]~q ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector433~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector436~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector436~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector436~0 .lut_mask = 64'h0F0F0F0F55335533;
defparam \A_SPW_TOP|rx_data|Selector436~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y8_N35
dffeas \A_SPW_TOP|rx_data|mem[46][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector436~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[46][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[46][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[46][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y8_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector76~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector76~0_combout  = ( \A_SPW_TOP|rx_data|mem[6][5]~q  & ( (!\A_SPW_TOP|rx_data|Selector73~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [5])) # (\A_SPW_TOP|rx_data|state_data_write.00~q 
//  & ((\A_SPW_TOP|rx_data|Mux3~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[6][5]~q  & ( (\A_SPW_TOP|rx_data|Selector73~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [5])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux3~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datab(!\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|Selector73~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[6][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector76~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector76~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector76~0 .lut_mask = 64'h00530053FF53FF53;
defparam \A_SPW_TOP|rx_data|Selector76~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y8_N14
dffeas \A_SPW_TOP|rx_data|mem[6][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector76~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[6][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[6][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[6][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y8_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector148~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector148~0_combout  = ( \A_SPW_TOP|rx_data|Selector145~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [5])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux3~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector145~0_combout  & ( \A_SPW_TOP|rx_data|mem[14][5]~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datab(!\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|mem[14][5]~q ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector145~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector148~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector148~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector148~0 .lut_mask = 64'h0F0F0F0F55335533;
defparam \A_SPW_TOP|rx_data|Selector148~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y8_N59
dffeas \A_SPW_TOP|rx_data|mem[14][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector148~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[14][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[14][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[14][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y8_N45
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector364~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector364~0_combout  = ( \A_SPW_TOP|rx_data|mem[38][5]~q  & ( (!\A_SPW_TOP|rx_data|Selector361~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [5])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux3~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[38][5]~q  & ( (\A_SPW_TOP|rx_data|Selector361~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [5])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux3~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datab(!\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector361~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[38][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector364~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector364~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector364~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|rx_data|Selector364~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y8_N26
dffeas \A_SPW_TOP|rx_data|mem[38][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector364~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[38][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[38][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[38][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y8_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux3~11 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux3~11_combout  = ( \A_SPW_TOP|rx_data|mem[14][5]~q  & ( \A_SPW_TOP|rx_data|mem[38][5]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [3] & (((\A_SPW_TOP|rx_data|mem[6][5]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [5]))) # (\A_SPW_TOP|rx_data|wr_ptr [3] & 
// ((!\A_SPW_TOP|rx_data|wr_ptr [5]) # ((\A_SPW_TOP|rx_data|mem[46][5]~q )))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[14][5]~q  & ( \A_SPW_TOP|rx_data|mem[38][5]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [3] & (((\A_SPW_TOP|rx_data|mem[6][5]~q )) # 
// (\A_SPW_TOP|rx_data|wr_ptr [5]))) # (\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|mem[46][5]~q ))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[14][5]~q  & ( !\A_SPW_TOP|rx_data|mem[38][5]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [3] 
// & (!\A_SPW_TOP|rx_data|wr_ptr [5] & ((\A_SPW_TOP|rx_data|mem[6][5]~q )))) # (\A_SPW_TOP|rx_data|wr_ptr [3] & ((!\A_SPW_TOP|rx_data|wr_ptr [5]) # ((\A_SPW_TOP|rx_data|mem[46][5]~q )))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[14][5]~q  & ( 
// !\A_SPW_TOP|rx_data|mem[38][5]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [3] & (!\A_SPW_TOP|rx_data|wr_ptr [5] & ((\A_SPW_TOP|rx_data|mem[6][5]~q )))) # (\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|mem[46][5]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datac(!\A_SPW_TOP|rx_data|mem[46][5]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[6][5]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[14][5]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[38][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux3~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux3~11 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux3~11 .lut_mask = 64'h018945CD23AB67EF;
defparam \A_SPW_TOP|rx_data|Mux3~11 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X35_Y8_N15
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector184~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector184~0_combout  = ( \A_SPW_TOP|rx_data|Selector181~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [5])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux3~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector181~0_combout  & ( \A_SPW_TOP|rx_data|mem[18][5]~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datab(!\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[18][5]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector181~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector184~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector184~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector184~0 .lut_mask = 64'h00FF00FF53535353;
defparam \A_SPW_TOP|rx_data|Selector184~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X35_Y8_N23
dffeas \A_SPW_TOP|rx_data|mem[18][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector184~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[18][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[18][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[18][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X35_Y8_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector256~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector256~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector253~0_combout  & ((\A_SPW_TOP|rx_data|mem[26][5]~q ))) # (\A_SPW_TOP|rx_data|Selector253~0_combout  & 
// (\A_SPW_TOP|rx_data|Mux3~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector253~0_combout  & ((\A_SPW_TOP|rx_data|mem[26][5]~q ))) # (\A_SPW_TOP|rx_data|Selector253~0_combout  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [5])) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datab(!\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector253~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[26][5]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector256~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector256~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector256~0 .lut_mask = 64'h05F505F503F303F3;
defparam \A_SPW_TOP|rx_data|Selector256~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X35_Y8_N59
dffeas \A_SPW_TOP|rx_data|mem[26][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector256~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[26][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[26][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[26][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X33_Y8_N39
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector472~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector472~0_combout  = ( \A_SPW_TOP|rx_data|Selector469~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [5]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux3~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector469~0_combout  & ( \A_SPW_TOP|rx_data|mem[50][5]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|mem[50][5]~q ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector469~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector472~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector472~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector472~0 .lut_mask = 64'h0F0F0F0F11BB11BB;
defparam \A_SPW_TOP|rx_data|Selector472~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X33_Y8_N56
dffeas \A_SPW_TOP|rx_data|mem[50][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector472~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[50][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[50][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[50][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X35_Y8_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector544~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector544~0_combout  = ( \A_SPW_TOP|rx_data|Selector541~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [5])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux3~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector541~0_combout  & ( \A_SPW_TOP|rx_data|mem[58][5]~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datab(!\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|mem[58][5]~q ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector541~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector544~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector544~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector544~0 .lut_mask = 64'h0F0F0F0F55335533;
defparam \A_SPW_TOP|rx_data|Selector544~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X35_Y8_N26
dffeas \A_SPW_TOP|rx_data|mem[58][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector544~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[58][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[58][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[58][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X35_Y8_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux3~12 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux3~12_combout  = ( \A_SPW_TOP|rx_data|mem[58][5]~q  & ( \A_SPW_TOP|rx_data|wr_ptr [3] & ( (\A_SPW_TOP|rx_data|wr_ptr [5]) # (\A_SPW_TOP|rx_data|mem[26][5]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[58][5]~q  & ( \A_SPW_TOP|rx_data|wr_ptr 
// [3] & ( (\A_SPW_TOP|rx_data|mem[26][5]~q  & !\A_SPW_TOP|rx_data|wr_ptr [5]) ) ) ) # ( \A_SPW_TOP|rx_data|mem[58][5]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [3] & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|mem[18][5]~q )) # 
// (\A_SPW_TOP|rx_data|wr_ptr [5] & ((\A_SPW_TOP|rx_data|mem[50][5]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[58][5]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [3] & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|mem[18][5]~q )) # (\A_SPW_TOP|rx_data|wr_ptr 
// [5] & ((\A_SPW_TOP|rx_data|mem[50][5]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[18][5]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[26][5]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[50][5]~q ),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datae(!\A_SPW_TOP|rx_data|mem[58][5]~q ),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux3~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux3~12 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux3~12 .lut_mask = 64'h550F550F330033FF;
defparam \A_SPW_TOP|rx_data|Mux3~12 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y8_N39
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector220~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector220~0_combout  = ( \A_SPW_TOP|rx_data|Selector217~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [5])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux3~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector217~0_combout  & ( \A_SPW_TOP|rx_data|mem[22][5]~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datab(!\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[22][5]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector217~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector220~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector220~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector220~0 .lut_mask = 64'h00FF00FF53535353;
defparam \A_SPW_TOP|rx_data|Selector220~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y8_N23
dffeas \A_SPW_TOP|rx_data|mem[22][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector220~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[22][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[22][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[22][5] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X32_Y8_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector292~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector292~0_combout  = ( \A_SPW_TOP|rx_data|mem[30][5]~q  & ( (!\A_SPW_TOP|rx_data|Selector289~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [5]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux3~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[30][5]~q  & ( (\A_SPW_TOP|rx_data|Selector289~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [5]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux3~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datac(!\A_SPW_TOP|rx_data|Selector289~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[30][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector292~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector292~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector292~0 .lut_mask = 64'h03050305F3F5F3F5;
defparam \A_SPW_TOP|rx_data|Selector292~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X32_Y8_N56
dffeas \A_SPW_TOP|rx_data|mem[30][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector292~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[30][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[30][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[30][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y8_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector508~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector508~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector505~0_combout  & ((\A_SPW_TOP|rx_data|mem[54][5]~q ))) # (\A_SPW_TOP|rx_data|Selector505~0_combout  & 
// (\A_SPW_TOP|rx_data|Mux3~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector505~0_combout  & ((\A_SPW_TOP|rx_data|mem[54][5]~q ))) # (\A_SPW_TOP|rx_data|Selector505~0_combout  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [5])) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datab(!\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector505~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[54][5]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector508~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector508~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector508~0 .lut_mask = 64'h05F505F503F303F3;
defparam \A_SPW_TOP|rx_data|Selector508~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y8_N29
dffeas \A_SPW_TOP|rx_data|mem[54][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector508~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[54][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[54][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[54][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X35_Y8_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector580~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector580~0_combout  = ( \A_SPW_TOP|rx_data|mem[62][5]~q  & ( \A_SPW_TOP|SPW|RX|rx_data_flag [5] & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q ) # ((!\A_SPW_TOP|rx_data|Selector577~0_combout ) # (\A_SPW_TOP|rx_data|Mux3~20_combout )) 
// ) ) ) # ( !\A_SPW_TOP|rx_data|mem[62][5]~q  & ( \A_SPW_TOP|SPW|RX|rx_data_flag [5] & ( (\A_SPW_TOP|rx_data|Selector577~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|rx_data|Mux3~20_combout ))) ) ) ) # ( 
// \A_SPW_TOP|rx_data|mem[62][5]~q  & ( !\A_SPW_TOP|SPW|RX|rx_data_flag [5] & ( (!\A_SPW_TOP|rx_data|Selector577~0_combout ) # ((\A_SPW_TOP|rx_data|state_data_write.00~q  & \A_SPW_TOP|rx_data|Mux3~20_combout )) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[62][5]~q  & ( 
// !\A_SPW_TOP|SPW|RX|rx_data_flag [5] & ( (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux3~20_combout  & \A_SPW_TOP|rx_data|Selector577~0_combout )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector577~0_combout ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|rx_data|mem[62][5]~q ),
        .dataf(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector580~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector580~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector580~0 .lut_mask = 64'h0101F1F10B0BFBFB;
defparam \A_SPW_TOP|rx_data|Selector580~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X35_Y8_N47
dffeas \A_SPW_TOP|rx_data|mem[62][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector580~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[62][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[62][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[62][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y8_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux3~13 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux3~13_combout  = ( \A_SPW_TOP|rx_data|mem[62][5]~q  & ( \A_SPW_TOP|rx_data|wr_ptr [3] & ( (\A_SPW_TOP|rx_data|wr_ptr [5]) # (\A_SPW_TOP|rx_data|mem[30][5]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[62][5]~q  & ( \A_SPW_TOP|rx_data|wr_ptr 
// [3] & ( (\A_SPW_TOP|rx_data|mem[30][5]~q  & !\A_SPW_TOP|rx_data|wr_ptr [5]) ) ) ) # ( \A_SPW_TOP|rx_data|mem[62][5]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [3] & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|mem[22][5]~q )) # 
// (\A_SPW_TOP|rx_data|wr_ptr [5] & ((\A_SPW_TOP|rx_data|mem[54][5]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[62][5]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [3] & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|mem[22][5]~q )) # (\A_SPW_TOP|rx_data|wr_ptr 
// [5] & ((\A_SPW_TOP|rx_data|mem[54][5]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[22][5]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[30][5]~q ),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datad(!\A_SPW_TOP|rx_data|mem[54][5]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[62][5]~q ),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux3~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux3~13 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux3~13 .lut_mask = 64'h505F505F30303F3F;
defparam \A_SPW_TOP|rx_data|Mux3~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X31_Y8_N51
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector40~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector40~0_combout  = ( \A_SPW_TOP|rx_data|Selector37~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [5])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux3~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector37~0_combout  & ( \A_SPW_TOP|rx_data|mem[2][5]~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datab(!\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|mem[2][5]~q ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector37~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector40~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector40~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector40~0 .lut_mask = 64'h0F0F0F0F55335533;
defparam \A_SPW_TOP|rx_data|Selector40~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X32_Y8_N59
dffeas \A_SPW_TOP|rx_data|mem[2][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector40~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[2][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[2][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[2][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y7_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector328~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector328~0_combout  = ( \A_SPW_TOP|rx_data|mem[34][5]~q  & ( (!\A_SPW_TOP|rx_data|Selector325~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [5])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux3~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[34][5]~q  & ( (\A_SPW_TOP|rx_data|Selector325~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [5])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux3~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datac(!\A_SPW_TOP|rx_data|Selector325~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[34][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector328~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector328~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector328~0 .lut_mask = 64'h02070207F2F7F2F7;
defparam \A_SPW_TOP|rx_data|Selector328~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y7_N11
dffeas \A_SPW_TOP|rx_data|mem[34][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector328~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[34][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[34][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[34][5] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X32_Y8_N39
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector400~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector400~0_combout  = ( \A_SPW_TOP|rx_data|Selector397~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [5]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux3~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector397~0_combout  & ( \A_SPW_TOP|rx_data|mem[42][5]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[42][5]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector397~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector400~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector400~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector400~0 .lut_mask = 64'h00FF00FF35353535;
defparam \A_SPW_TOP|rx_data|Selector400~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X32_Y8_N2
dffeas \A_SPW_TOP|rx_data|mem[42][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector400~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[42][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[42][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[42][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y8_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector112~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector112~0_combout  = ( \A_SPW_TOP|rx_data|Selector109~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [5])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux3~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector109~0_combout  & ( \A_SPW_TOP|rx_data|mem[10][5]~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datab(!\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|mem[10][5]~q ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector109~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector112~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector112~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector112~0 .lut_mask = 64'h0F0F0F0F55335533;
defparam \A_SPW_TOP|rx_data|Selector112~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y8_N11
dffeas \A_SPW_TOP|rx_data|mem[10][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector112~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[10][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[10][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[10][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y8_N45
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux3~10 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux3~10_combout  = ( \A_SPW_TOP|rx_data|mem[42][5]~q  & ( \A_SPW_TOP|rx_data|mem[10][5]~q  & ( ((!\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|mem[2][5]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [5] & ((\A_SPW_TOP|rx_data|mem[34][5]~q 
// )))) # (\A_SPW_TOP|rx_data|wr_ptr [3]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[42][5]~q  & ( \A_SPW_TOP|rx_data|mem[10][5]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & (((\A_SPW_TOP|rx_data|mem[2][5]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [3]))) # 
// (\A_SPW_TOP|rx_data|wr_ptr [5] & (!\A_SPW_TOP|rx_data|wr_ptr [3] & ((\A_SPW_TOP|rx_data|mem[34][5]~q )))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[42][5]~q  & ( !\A_SPW_TOP|rx_data|mem[10][5]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & (!\A_SPW_TOP|rx_data|wr_ptr 
// [3] & (\A_SPW_TOP|rx_data|mem[2][5]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [5] & (((\A_SPW_TOP|rx_data|mem[34][5]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [3]))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[42][5]~q  & ( !\A_SPW_TOP|rx_data|mem[10][5]~q  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [3] & ((!\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|mem[2][5]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [5] & ((\A_SPW_TOP|rx_data|mem[34][5]~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datac(!\A_SPW_TOP|rx_data|mem[2][5]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[34][5]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[42][5]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[10][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux3~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux3~10 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux3~10 .lut_mask = 64'h084C195D2A6E3B7F;
defparam \A_SPW_TOP|rx_data|Mux3~10 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y8_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux3~14 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux3~14_combout  = ( \A_SPW_TOP|rx_data|Mux3~13_combout  & ( \A_SPW_TOP|rx_data|Mux3~10_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & (((!\A_SPW_TOP|rx_data|wr_ptr [4]) # (\A_SPW_TOP|rx_data|Mux3~12_combout )))) # 
// (\A_SPW_TOP|rx_data|wr_ptr [2] & (((\A_SPW_TOP|rx_data|wr_ptr [4])) # (\A_SPW_TOP|rx_data|Mux3~11_combout ))) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux3~13_combout  & ( \A_SPW_TOP|rx_data|Mux3~10_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & 
// (((!\A_SPW_TOP|rx_data|wr_ptr [4]) # (\A_SPW_TOP|rx_data|Mux3~12_combout )))) # (\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|Mux3~11_combout  & ((!\A_SPW_TOP|rx_data|wr_ptr [4])))) ) ) ) # ( \A_SPW_TOP|rx_data|Mux3~13_combout  & ( 
// !\A_SPW_TOP|rx_data|Mux3~10_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & (((\A_SPW_TOP|rx_data|Mux3~12_combout  & \A_SPW_TOP|rx_data|wr_ptr [4])))) # (\A_SPW_TOP|rx_data|wr_ptr [2] & (((\A_SPW_TOP|rx_data|wr_ptr [4])) # 
// (\A_SPW_TOP|rx_data|Mux3~11_combout ))) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux3~13_combout  & ( !\A_SPW_TOP|rx_data|Mux3~10_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & (((\A_SPW_TOP|rx_data|Mux3~12_combout  & \A_SPW_TOP|rx_data|wr_ptr [4])))) # 
// (\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|Mux3~11_combout  & ((!\A_SPW_TOP|rx_data|wr_ptr [4])))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux3~11_combout ),
        .datab(!\A_SPW_TOP|rx_data|Mux3~12_combout ),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datae(!\A_SPW_TOP|rx_data|Mux3~13_combout ),
        .dataf(!\A_SPW_TOP|rx_data|Mux3~10_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux3~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux3~14 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux3~14 .lut_mask = 64'h0530053FF530F53F;
defparam \A_SPW_TOP|rx_data|Mux3~14 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X32_Y5_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector319~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector319~0_combout  = ( \A_SPW_TOP|rx_data|Selector316~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [5])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux3~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector316~0_combout  & ( \A_SPW_TOP|rx_data|mem[33][5]~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datab(!\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|mem[33][5]~q ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector316~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector319~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector319~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector319~0 .lut_mask = 64'h0F0F0F0F55335533;
defparam \A_SPW_TOP|rx_data|Selector319~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X32_Y5_N23
dffeas \A_SPW_TOP|rx_data|mem[33][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector319~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[33][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[33][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[33][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X35_Y5_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector31~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector31~0_combout  = ( \A_SPW_TOP|rx_data|mem[1][5]~q  & ( (!\A_SPW_TOP|rx_data|Selector28~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [5]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux3~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[1][5]~q  & ( (\A_SPW_TOP|rx_data|Selector28~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [5]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux3~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Selector28~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[1][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector31~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector31~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector31~0 .lut_mask = 64'h010D010DF1FDF1FD;
defparam \A_SPW_TOP|rx_data|Selector31~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X35_Y5_N41
dffeas \A_SPW_TOP|rx_data|mem[1][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector31~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[1][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[1][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[1][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X35_Y5_N57
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector391~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector391~0_combout  = ( \A_SPW_TOP|rx_data|Selector388~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [5]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux3~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector388~0_combout  & ( \A_SPW_TOP|rx_data|mem[41][5]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[41][5]~q ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector388~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector391~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector391~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector391~0 .lut_mask = 64'h0F0F0F0F11DD11DD;
defparam \A_SPW_TOP|rx_data|Selector391~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X35_Y5_N8
dffeas \A_SPW_TOP|rx_data|mem[41][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector391~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[41][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[41][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[41][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X35_Y5_N9
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux3~5 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux3~5_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [5] & ( \A_SPW_TOP|rx_data|wr_ptr [3] & ( \A_SPW_TOP|rx_data|mem[41][5]~q  ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [5] & ( \A_SPW_TOP|rx_data|wr_ptr [3] & ( \A_SPW_TOP|rx_data|mem[9][5]~q  ) ) 
// ) # ( \A_SPW_TOP|rx_data|wr_ptr [5] & ( !\A_SPW_TOP|rx_data|wr_ptr [3] & ( \A_SPW_TOP|rx_data|mem[33][5]~q  ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [5] & ( !\A_SPW_TOP|rx_data|wr_ptr [3] & ( \A_SPW_TOP|rx_data|mem[1][5]~q  ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[33][5]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[1][5]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[41][5]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[9][5]~q ),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux3~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux3~5 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux3~5 .lut_mask = 64'h3333555500FF0F0F;
defparam \A_SPW_TOP|rx_data|Mux3~5 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X32_Y5_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector283~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector283~0_combout  = ( \A_SPW_TOP|rx_data|mem[29][5]~q  & ( (!\A_SPW_TOP|rx_data|Selector280~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [5])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux3~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[29][5]~q  & ( (\A_SPW_TOP|rx_data|Selector280~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [5])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux3~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datab(!\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector280~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[29][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector283~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector283~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector283~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|rx_data|Selector283~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X32_Y5_N50
dffeas \A_SPW_TOP|rx_data|mem[29][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector283~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[29][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[29][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[29][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X33_Y5_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector571~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector571~0_combout  = ( \A_SPW_TOP|rx_data|Mux3~20_combout  & ( \A_SPW_TOP|rx_data|Selector568~0_combout  & ( (\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|SPW|RX|rx_data_flag [5]) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|Mux3~20_combout  & ( \A_SPW_TOP|rx_data|Selector568~0_combout  & ( (\A_SPW_TOP|SPW|RX|rx_data_flag [5] & !\A_SPW_TOP|rx_data|state_data_write.00~q ) ) ) ) # ( \A_SPW_TOP|rx_data|Mux3~20_combout  & ( 
// !\A_SPW_TOP|rx_data|Selector568~0_combout  & ( \A_SPW_TOP|rx_data|mem[61][5]~q  ) ) ) # ( !\A_SPW_TOP|rx_data|Mux3~20_combout  & ( !\A_SPW_TOP|rx_data|Selector568~0_combout  & ( \A_SPW_TOP|rx_data|mem[61][5]~q  ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datac(!\A_SPW_TOP|rx_data|mem[61][5]~q ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(!\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .dataf(!\A_SPW_TOP|rx_data|Selector568~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector571~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector571~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector571~0 .lut_mask = 64'h0F0F0F0F330033FF;
defparam \A_SPW_TOP|rx_data|Selector571~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X33_Y5_N35
dffeas \A_SPW_TOP|rx_data|mem[61][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector571~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[61][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[61][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[61][5] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X32_Y5_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector499~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector499~0_combout  = ( \A_SPW_TOP|rx_data|mem[53][5]~q  & ( (!\A_SPW_TOP|rx_data|Selector496~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [5])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux3~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[53][5]~q  & ( (\A_SPW_TOP|rx_data|Selector496~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [5])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux3~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datab(!\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector496~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[53][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector499~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector499~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector499~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|rx_data|Selector499~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X32_Y5_N14
dffeas \A_SPW_TOP|rx_data|mem[53][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector499~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[53][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[53][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[53][5] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X32_Y5_N33
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector211~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector211~0_combout  = ( \A_SPW_TOP|rx_data|mem[21][5]~q  & ( (!\A_SPW_TOP|rx_data|Selector208~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [5])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux3~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[21][5]~q  & ( (\A_SPW_TOP|rx_data|Selector208~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [5])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux3~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datab(!\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|Selector208~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[21][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector211~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector211~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector211~0 .lut_mask = 64'h00530053FF53FF53;
defparam \A_SPW_TOP|rx_data|Selector211~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X32_Y5_N53
dffeas \A_SPW_TOP|rx_data|mem[21][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector211~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[21][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[21][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[21][5] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X32_Y5_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux3~8 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux3~8_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [5] & ( \A_SPW_TOP|rx_data|mem[21][5]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [3] & ((\A_SPW_TOP|rx_data|mem[53][5]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|mem[61][5]~q )) ) 
// ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [5] & ( \A_SPW_TOP|rx_data|mem[21][5]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [3]) # (\A_SPW_TOP|rx_data|mem[29][5]~q ) ) ) ) # ( \A_SPW_TOP|rx_data|wr_ptr [5] & ( !\A_SPW_TOP|rx_data|mem[21][5]~q  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [3] & ((\A_SPW_TOP|rx_data|mem[53][5]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|mem[61][5]~q )) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [5] & ( !\A_SPW_TOP|rx_data|mem[21][5]~q  & ( 
// (\A_SPW_TOP|rx_data|mem[29][5]~q  & \A_SPW_TOP|rx_data|wr_ptr [3]) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[29][5]~q ),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datac(!\A_SPW_TOP|rx_data|mem[61][5]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[53][5]~q ),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .dataf(!\A_SPW_TOP|rx_data|mem[21][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux3~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux3~8 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux3~8 .lut_mask = 64'h111103CFDDDD03CF;
defparam \A_SPW_TOP|rx_data|Mux3~8 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X33_Y5_N21
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector67~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector67~0_combout  = ( \A_SPW_TOP|rx_data|mem[5][5]~q  & ( (!\A_SPW_TOP|rx_data|Selector64~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [5]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux3~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[5][5]~q  & ( (\A_SPW_TOP|rx_data|Selector64~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [5]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux3~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|Selector64~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[5][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector67~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector67~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector67~0 .lut_mask = 64'h00350035FF35FF35;
defparam \A_SPW_TOP|rx_data|Selector67~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X33_Y5_N17
dffeas \A_SPW_TOP|rx_data|mem[5][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector67~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[5][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[5][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[5][5] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X32_Y5_N45
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector139~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector139~0_combout  = ( \A_SPW_TOP|rx_data|mem[13][5]~q  & ( (!\A_SPW_TOP|rx_data|Selector136~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [5])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux3~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[13][5]~q  & ( (\A_SPW_TOP|rx_data|Selector136~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [5])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux3~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datab(!\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector136~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[13][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector139~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector139~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector139~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|rx_data|Selector139~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X32_Y5_N41
dffeas \A_SPW_TOP|rx_data|mem[13][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector139~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[13][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[13][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[13][5] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X32_Y5_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector355~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector355~0_combout  = ( \A_SPW_TOP|rx_data|Selector352~0_combout  & ( \A_SPW_TOP|SPW|RX|rx_data_flag [5] & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|rx_data|Mux3~20_combout ) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|Selector352~0_combout  & ( \A_SPW_TOP|SPW|RX|rx_data_flag [5] & ( \A_SPW_TOP|rx_data|mem[37][5]~q  ) ) ) # ( \A_SPW_TOP|rx_data|Selector352~0_combout  & ( !\A_SPW_TOP|SPW|RX|rx_data_flag [5] & ( 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & \A_SPW_TOP|rx_data|Mux3~20_combout ) ) ) ) # ( !\A_SPW_TOP|rx_data|Selector352~0_combout  & ( !\A_SPW_TOP|SPW|RX|rx_data_flag [5] & ( \A_SPW_TOP|rx_data|mem[37][5]~q  ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[37][5]~q ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(gnd),
        .datad(!\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .datae(!\A_SPW_TOP|rx_data|Selector352~0_combout ),
        .dataf(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector355~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector355~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector355~0 .lut_mask = 64'h555500335555CCFF;
defparam \A_SPW_TOP|rx_data|Selector355~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X32_Y5_N29
dffeas \A_SPW_TOP|rx_data|mem[37][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector355~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[37][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[37][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[37][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y5_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector427~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector427~0_combout  = ( \A_SPW_TOP|rx_data|mem[45][5]~q  & ( (!\A_SPW_TOP|rx_data|Selector424~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [5])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux3~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[45][5]~q  & ( (\A_SPW_TOP|rx_data|Selector424~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [5])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux3~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datac(!\A_SPW_TOP|rx_data|Selector424~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[45][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector427~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector427~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector427~0 .lut_mask = 64'h02070207F2F7F2F7;
defparam \A_SPW_TOP|rx_data|Selector427~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y5_N50
dffeas \A_SPW_TOP|rx_data|mem[45][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector427~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[45][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[45][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[45][5] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X32_Y5_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux3~6 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux3~6_combout  = ( \A_SPW_TOP|rx_data|mem[37][5]~q  & ( \A_SPW_TOP|rx_data|mem[45][5]~q  & ( ((!\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|mem[5][5]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [3] & ((\A_SPW_TOP|rx_data|mem[13][5]~q 
// )))) # (\A_SPW_TOP|rx_data|wr_ptr [5]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[37][5]~q  & ( \A_SPW_TOP|rx_data|mem[45][5]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & ((!\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|mem[5][5]~q )) # 
// (\A_SPW_TOP|rx_data|wr_ptr [3] & ((\A_SPW_TOP|rx_data|mem[13][5]~q ))))) # (\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|wr_ptr [3])) ) ) ) # ( \A_SPW_TOP|rx_data|mem[37][5]~q  & ( !\A_SPW_TOP|rx_data|mem[45][5]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr 
// [5] & ((!\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|mem[5][5]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [3] & ((\A_SPW_TOP|rx_data|mem[13][5]~q ))))) # (\A_SPW_TOP|rx_data|wr_ptr [5] & (!\A_SPW_TOP|rx_data|wr_ptr [3])) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|mem[37][5]~q  & ( !\A_SPW_TOP|rx_data|mem[45][5]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & ((!\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|mem[5][5]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [3] & ((\A_SPW_TOP|rx_data|mem[13][5]~q ))))) 
// ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datac(!\A_SPW_TOP|rx_data|mem[5][5]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[13][5]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[37][5]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[45][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux3~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux3~6 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux3~6 .lut_mask = 64'h082A4C6E193B5D7F;
defparam \A_SPW_TOP|rx_data|Mux3~6 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X31_Y5_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector175~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector175~0_combout  = ( \A_SPW_TOP|rx_data|Selector172~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [5])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux3~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector172~0_combout  & ( \A_SPW_TOP|rx_data|mem[17][5]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datac(!\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[17][5]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector172~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector175~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector175~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector175~0 .lut_mask = 64'h00FF00FF27272727;
defparam \A_SPW_TOP|rx_data|Selector175~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y5_N29
dffeas \A_SPW_TOP|rx_data|mem[17][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector175~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[17][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[17][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[17][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X35_Y5_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector247~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector247~0_combout  = ( \A_SPW_TOP|rx_data|Selector244~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [5]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux3~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector244~0_combout  & ( \A_SPW_TOP|rx_data|mem[25][5]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[25][5]~q ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector244~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector247~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector247~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector247~0 .lut_mask = 64'h0F0F0F0F11DD11DD;
defparam \A_SPW_TOP|rx_data|Selector247~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X35_Y5_N38
dffeas \A_SPW_TOP|rx_data|mem[25][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector247~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[25][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[25][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[25][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X35_Y5_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector463~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector463~0_combout  = ( \A_SPW_TOP|rx_data|mem[49][5]~q  & ( (!\A_SPW_TOP|rx_data|Selector460~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [5]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux3~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[49][5]~q  & ( (\A_SPW_TOP|rx_data|Selector460~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [5]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux3~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Selector460~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[49][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector463~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector463~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector463~0 .lut_mask = 64'h010D010DF1FDF1FD;
defparam \A_SPW_TOP|rx_data|Selector463~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X35_Y5_N17
dffeas \A_SPW_TOP|rx_data|mem[49][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector463~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[49][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[49][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[49][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X35_Y5_N45
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector535~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector535~0_combout  = ( \A_SPW_TOP|rx_data|mem[57][5]~q  & ( (!\A_SPW_TOP|rx_data|Selector532~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [5]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux3~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[57][5]~q  & ( (\A_SPW_TOP|rx_data|Selector532~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [5]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux3~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Selector532~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[57][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector535~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector535~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector535~0 .lut_mask = 64'h010D010DF1FDF1FD;
defparam \A_SPW_TOP|rx_data|Selector535~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X35_Y5_N32
dffeas \A_SPW_TOP|rx_data|mem[57][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector535~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[57][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[57][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[57][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X35_Y5_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux3~7 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux3~7_combout  = ( \A_SPW_TOP|rx_data|mem[57][5]~q  & ( \A_SPW_TOP|rx_data|wr_ptr [3] & ( (\A_SPW_TOP|rx_data|mem[25][5]~q ) # (\A_SPW_TOP|rx_data|wr_ptr [5]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[57][5]~q  & ( \A_SPW_TOP|rx_data|wr_ptr 
// [3] & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & \A_SPW_TOP|rx_data|mem[25][5]~q ) ) ) ) # ( \A_SPW_TOP|rx_data|mem[57][5]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [3] & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|mem[17][5]~q )) # 
// (\A_SPW_TOP|rx_data|wr_ptr [5] & ((\A_SPW_TOP|rx_data|mem[49][5]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[57][5]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [3] & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|mem[17][5]~q )) # (\A_SPW_TOP|rx_data|wr_ptr 
// [5] & ((\A_SPW_TOP|rx_data|mem[49][5]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datab(!\A_SPW_TOP|rx_data|mem[17][5]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[25][5]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[49][5]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[57][5]~q ),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux3~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux3~7 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux3~7 .lut_mask = 64'h227722770A0A5F5F;
defparam \A_SPW_TOP|rx_data|Mux3~7 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X35_Y5_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux3~9 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux3~9_combout  = ( \A_SPW_TOP|rx_data|Mux3~6_combout  & ( \A_SPW_TOP|rx_data|Mux3~7_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [4] & (((\A_SPW_TOP|rx_data|wr_ptr [2])) # (\A_SPW_TOP|rx_data|Mux3~5_combout ))) # (\A_SPW_TOP|rx_data|wr_ptr 
// [4] & (((!\A_SPW_TOP|rx_data|wr_ptr [2]) # (\A_SPW_TOP|rx_data|Mux3~8_combout )))) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux3~6_combout  & ( \A_SPW_TOP|rx_data|Mux3~7_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|Mux3~5_combout  & 
// (!\A_SPW_TOP|rx_data|wr_ptr [2]))) # (\A_SPW_TOP|rx_data|wr_ptr [4] & (((!\A_SPW_TOP|rx_data|wr_ptr [2]) # (\A_SPW_TOP|rx_data|Mux3~8_combout )))) ) ) ) # ( \A_SPW_TOP|rx_data|Mux3~6_combout  & ( !\A_SPW_TOP|rx_data|Mux3~7_combout  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [4] & (((\A_SPW_TOP|rx_data|wr_ptr [2])) # (\A_SPW_TOP|rx_data|Mux3~5_combout ))) # (\A_SPW_TOP|rx_data|wr_ptr [4] & (((\A_SPW_TOP|rx_data|wr_ptr [2] & \A_SPW_TOP|rx_data|Mux3~8_combout )))) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|Mux3~6_combout  & ( !\A_SPW_TOP|rx_data|Mux3~7_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|Mux3~5_combout  & (!\A_SPW_TOP|rx_data|wr_ptr [2]))) # (\A_SPW_TOP|rx_data|wr_ptr [4] & (((\A_SPW_TOP|rx_data|wr_ptr [2] 
// & \A_SPW_TOP|rx_data|Mux3~8_combout )))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datab(!\A_SPW_TOP|rx_data|Mux3~5_combout ),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datad(!\A_SPW_TOP|rx_data|Mux3~8_combout ),
        .datae(!\A_SPW_TOP|rx_data|Mux3~6_combout ),
        .dataf(!\A_SPW_TOP|rx_data|Mux3~7_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux3~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux3~9 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux3~9 .lut_mask = 64'h20252A2F70757A7F;
defparam \A_SPW_TOP|rx_data|Mux3~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y8_N15
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux3~20 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux3~20_combout  = ( \A_SPW_TOP|rx_data|Mux3~9_combout  & ( \A_SPW_TOP|rx_data|wr_ptr [0] & ( (!\A_SPW_TOP|rx_data|wr_ptr [1]) # (\A_SPW_TOP|rx_data|Mux3~19_combout ) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux3~9_combout  & ( 
// \A_SPW_TOP|rx_data|wr_ptr [0] & ( (\A_SPW_TOP|rx_data|Mux3~19_combout  & \A_SPW_TOP|rx_data|wr_ptr [1]) ) ) ) # ( \A_SPW_TOP|rx_data|Mux3~9_combout  & ( !\A_SPW_TOP|rx_data|wr_ptr [0] & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & 
// (\A_SPW_TOP|rx_data|Mux3~4_combout )) # (\A_SPW_TOP|rx_data|wr_ptr [1] & ((\A_SPW_TOP|rx_data|Mux3~14_combout ))) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux3~9_combout  & ( !\A_SPW_TOP|rx_data|wr_ptr [0] & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & 
// (\A_SPW_TOP|rx_data|Mux3~4_combout )) # (\A_SPW_TOP|rx_data|wr_ptr [1] & ((\A_SPW_TOP|rx_data|Mux3~14_combout ))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux3~19_combout ),
        .datab(!\A_SPW_TOP|rx_data|Mux3~4_combout ),
        .datac(!\A_SPW_TOP|rx_data|Mux3~14_combout ),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datae(!\A_SPW_TOP|rx_data|Mux3~9_combout ),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux3~20 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux3~20 .lut_mask = 64'h330F330F0055FF55;
defparam \A_SPW_TOP|rx_data|Mux3~20 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X35_Y5_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector103~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector103~0_combout  = ( \A_SPW_TOP|rx_data|mem[9][5]~q  & ( (!\A_SPW_TOP|rx_data|Selector100~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [5]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux3~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[9][5]~q  & ( (\A_SPW_TOP|rx_data|Selector100~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [5]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux3~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux3~20_combout ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
        .datad(!\A_SPW_TOP|rx_data|Selector100~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[9][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector103~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector103~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector103~0 .lut_mask = 64'h001D001DFF1DFF1D;
defparam \A_SPW_TOP|rx_data|Selector103~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X35_Y5_N53
dffeas \A_SPW_TOP|rx_data|mem[9][5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector103~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[9][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[9][5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[9][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X35_Y5_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux12~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux12~1_combout  = ( \A_SPW_TOP|rx_data|mem[25][5]~q  & ( \A_SPW_TOP|rx_data|rd_ptr [4] & ( (\A_SPW_TOP|rx_data|mem[17][5]~q ) # (\A_SPW_TOP|rx_data|rd_ptr [3]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[25][5]~q  & ( \A_SPW_TOP|rx_data|rd_ptr 
// [4] & ( (!\A_SPW_TOP|rx_data|rd_ptr [3] & \A_SPW_TOP|rx_data|mem[17][5]~q ) ) ) ) # ( \A_SPW_TOP|rx_data|mem[25][5]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [4] & ( (!\A_SPW_TOP|rx_data|rd_ptr [3] & ((\A_SPW_TOP|rx_data|mem[1][5]~q ))) # 
// (\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|mem[9][5]~q )) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[25][5]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [4] & ( (!\A_SPW_TOP|rx_data|rd_ptr [3] & ((\A_SPW_TOP|rx_data|mem[1][5]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [3] 
// & (\A_SPW_TOP|rx_data|mem[9][5]~q )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[9][5]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[1][5]~q ),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [3]),
        .datad(!\A_SPW_TOP|rx_data|mem[17][5]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[25][5]~q ),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux12~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux12~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux12~1 .lut_mask = 64'h3535353500F00FFF;
defparam \A_SPW_TOP|rx_data|Mux12~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X35_Y5_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux12~3 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux12~3_combout  = ( \A_SPW_TOP|rx_data|mem[33][5]~q  & ( \A_SPW_TOP|rx_data|mem[57][5]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [3] & (((!\A_SPW_TOP|rx_data|rd_ptr [4]) # (\A_SPW_TOP|rx_data|mem[49][5]~q )))) # (\A_SPW_TOP|rx_data|rd_ptr [3] 
// & (((\A_SPW_TOP|rx_data|rd_ptr [4])) # (\A_SPW_TOP|rx_data|mem[41][5]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[33][5]~q  & ( \A_SPW_TOP|rx_data|mem[57][5]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [3] & (((\A_SPW_TOP|rx_data|rd_ptr [4] & 
// \A_SPW_TOP|rx_data|mem[49][5]~q )))) # (\A_SPW_TOP|rx_data|rd_ptr [3] & (((\A_SPW_TOP|rx_data|rd_ptr [4])) # (\A_SPW_TOP|rx_data|mem[41][5]~q ))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[33][5]~q  & ( !\A_SPW_TOP|rx_data|mem[57][5]~q  & ( 
// (!\A_SPW_TOP|rx_data|rd_ptr [3] & (((!\A_SPW_TOP|rx_data|rd_ptr [4]) # (\A_SPW_TOP|rx_data|mem[49][5]~q )))) # (\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|mem[41][5]~q  & (!\A_SPW_TOP|rx_data|rd_ptr [4]))) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|mem[33][5]~q  & ( !\A_SPW_TOP|rx_data|mem[57][5]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [3] & (((\A_SPW_TOP|rx_data|rd_ptr [4] & \A_SPW_TOP|rx_data|mem[49][5]~q )))) # (\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|mem[41][5]~q  & 
// (!\A_SPW_TOP|rx_data|rd_ptr [4]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [3]),
        .datab(!\A_SPW_TOP|rx_data|mem[41][5]~q ),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [4]),
        .datad(!\A_SPW_TOP|rx_data|mem[49][5]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[33][5]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[57][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux12~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux12~3 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux12~3 .lut_mask = 64'h101AB0BA151FB5BF;
defparam \A_SPW_TOP|rx_data|Mux12~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y7_N21
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux12~2 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux12~2_combout  = ( \A_SPW_TOP|rx_data|rd_ptr [4] & ( \A_SPW_TOP|rx_data|mem[40][5]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [3] & ((\A_SPW_TOP|rx_data|mem[48][5]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|mem[56][5]~q )) ) 
// ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [4] & ( \A_SPW_TOP|rx_data|mem[40][5]~q  & ( (\A_SPW_TOP|rx_data|mem[32][5]~q ) # (\A_SPW_TOP|rx_data|rd_ptr [3]) ) ) ) # ( \A_SPW_TOP|rx_data|rd_ptr [4] & ( !\A_SPW_TOP|rx_data|mem[40][5]~q  & ( 
// (!\A_SPW_TOP|rx_data|rd_ptr [3] & ((\A_SPW_TOP|rx_data|mem[48][5]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|mem[56][5]~q )) ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [4] & ( !\A_SPW_TOP|rx_data|mem[40][5]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr 
// [3] & \A_SPW_TOP|rx_data|mem[32][5]~q ) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [3]),
        .datab(!\A_SPW_TOP|rx_data|mem[56][5]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[48][5]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[32][5]~q ),
        .datae(!\A_SPW_TOP|rx_data|rd_ptr [4]),
        .dataf(!\A_SPW_TOP|rx_data|mem[40][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux12~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux12~2 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux12~2 .lut_mask = 64'h00AA1B1B55FF1B1B;
defparam \A_SPW_TOP|rx_data|Mux12~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y7_N45
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux12~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux12~0_combout  = ( \A_SPW_TOP|rx_data|mem[0][5]~q  & ( \A_SPW_TOP|rx_data|rd_ptr [3] & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & (\A_SPW_TOP|rx_data|mem[8][5]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [4] & ((\A_SPW_TOP|rx_data|mem[24][5]~q ))) ) ) 
// ) # ( !\A_SPW_TOP|rx_data|mem[0][5]~q  & ( \A_SPW_TOP|rx_data|rd_ptr [3] & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & (\A_SPW_TOP|rx_data|mem[8][5]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [4] & ((\A_SPW_TOP|rx_data|mem[24][5]~q ))) ) ) ) # ( 
// \A_SPW_TOP|rx_data|mem[0][5]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [3] & ( (!\A_SPW_TOP|rx_data|rd_ptr [4]) # (\A_SPW_TOP|rx_data|mem[16][5]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[0][5]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [3] & ( (\A_SPW_TOP|rx_data|rd_ptr [4] & 
// \A_SPW_TOP|rx_data|mem[16][5]~q ) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [4]),
        .datab(!\A_SPW_TOP|rx_data|mem[16][5]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[8][5]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[24][5]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[0][5]~q ),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux12~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux12~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux12~0 .lut_mask = 64'h1111BBBB0A5F0A5F;
defparam \A_SPW_TOP|rx_data|Mux12~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X35_Y5_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux12~4 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux12~4_combout  = ( \A_SPW_TOP|rx_data|Mux12~0_combout  & ( \A_SPW_TOP|rx_data|rd_ptr [0] & ( (!\A_SPW_TOP|rx_data|rd_ptr [5] & (\A_SPW_TOP|rx_data|Mux12~1_combout )) # (\A_SPW_TOP|rx_data|rd_ptr [5] & 
// ((\A_SPW_TOP|rx_data|Mux12~3_combout ))) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux12~0_combout  & ( \A_SPW_TOP|rx_data|rd_ptr [0] & ( (!\A_SPW_TOP|rx_data|rd_ptr [5] & (\A_SPW_TOP|rx_data|Mux12~1_combout )) # (\A_SPW_TOP|rx_data|rd_ptr [5] & 
// ((\A_SPW_TOP|rx_data|Mux12~3_combout ))) ) ) ) # ( \A_SPW_TOP|rx_data|Mux12~0_combout  & ( !\A_SPW_TOP|rx_data|rd_ptr [0] & ( (!\A_SPW_TOP|rx_data|rd_ptr [5]) # (\A_SPW_TOP|rx_data|Mux12~2_combout ) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux12~0_combout  & ( 
// !\A_SPW_TOP|rx_data|rd_ptr [0] & ( (\A_SPW_TOP|rx_data|rd_ptr [5] & \A_SPW_TOP|rx_data|Mux12~2_combout ) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux12~1_combout ),
        .datab(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .datac(!\A_SPW_TOP|rx_data|Mux12~3_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux12~2_combout ),
        .datae(!\A_SPW_TOP|rx_data|Mux12~0_combout ),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux12~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux12~4 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux12~4 .lut_mask = 64'h0033CCFF47474747;
defparam \A_SPW_TOP|rx_data|Mux12~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X31_Y8_N39
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux12~17 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux12~17_combout  = ( \A_SPW_TOP|rx_data|mem[54][5]~q  & ( \A_SPW_TOP|rx_data|mem[38][5]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [3]) # ((!\A_SPW_TOP|rx_data|rd_ptr [4] & ((\A_SPW_TOP|rx_data|mem[46][5]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [4] 
// & (\A_SPW_TOP|rx_data|mem[62][5]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[54][5]~q  & ( \A_SPW_TOP|rx_data|mem[38][5]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & ((!\A_SPW_TOP|rx_data|rd_ptr [3]) # ((\A_SPW_TOP|rx_data|mem[46][5]~q )))) # 
// (\A_SPW_TOP|rx_data|rd_ptr [4] & (\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|mem[62][5]~q ))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[54][5]~q  & ( !\A_SPW_TOP|rx_data|mem[38][5]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & (\A_SPW_TOP|rx_data|rd_ptr [3] & 
// ((\A_SPW_TOP|rx_data|mem[46][5]~q )))) # (\A_SPW_TOP|rx_data|rd_ptr [4] & ((!\A_SPW_TOP|rx_data|rd_ptr [3]) # ((\A_SPW_TOP|rx_data|mem[62][5]~q )))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[54][5]~q  & ( !\A_SPW_TOP|rx_data|mem[38][5]~q  & ( 
// (\A_SPW_TOP|rx_data|rd_ptr [3] & ((!\A_SPW_TOP|rx_data|rd_ptr [4] & ((\A_SPW_TOP|rx_data|mem[46][5]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [4] & (\A_SPW_TOP|rx_data|mem[62][5]~q )))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [4]),
        .datab(!\A_SPW_TOP|rx_data|rd_ptr [3]),
        .datac(!\A_SPW_TOP|rx_data|mem[62][5]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[46][5]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[54][5]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[38][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux12~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux12~17 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux12~17 .lut_mask = 64'h0123456789ABCDEF;
defparam \A_SPW_TOP|rx_data|Mux12~17 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X33_Y8_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux12~18 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux12~18_combout  = ( \A_SPW_TOP|rx_data|mem[39][5]~q  & ( \A_SPW_TOP|rx_data|mem[63][5]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & (((!\A_SPW_TOP|rx_data|rd_ptr [3]) # (\A_SPW_TOP|rx_data|mem[47][5]~q )))) # (\A_SPW_TOP|rx_data|rd_ptr 
// [4] & (((\A_SPW_TOP|rx_data|rd_ptr [3])) # (\A_SPW_TOP|rx_data|mem[55][5]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[39][5]~q  & ( \A_SPW_TOP|rx_data|mem[63][5]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & (((\A_SPW_TOP|rx_data|mem[47][5]~q  & 
// \A_SPW_TOP|rx_data|rd_ptr [3])))) # (\A_SPW_TOP|rx_data|rd_ptr [4] & (((\A_SPW_TOP|rx_data|rd_ptr [3])) # (\A_SPW_TOP|rx_data|mem[55][5]~q ))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[39][5]~q  & ( !\A_SPW_TOP|rx_data|mem[63][5]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr 
// [4] & (((!\A_SPW_TOP|rx_data|rd_ptr [3]) # (\A_SPW_TOP|rx_data|mem[47][5]~q )))) # (\A_SPW_TOP|rx_data|rd_ptr [4] & (\A_SPW_TOP|rx_data|mem[55][5]~q  & ((!\A_SPW_TOP|rx_data|rd_ptr [3])))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[39][5]~q  & ( 
// !\A_SPW_TOP|rx_data|mem[63][5]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & (((\A_SPW_TOP|rx_data|mem[47][5]~q  & \A_SPW_TOP|rx_data|rd_ptr [3])))) # (\A_SPW_TOP|rx_data|rd_ptr [4] & (\A_SPW_TOP|rx_data|mem[55][5]~q  & ((!\A_SPW_TOP|rx_data|rd_ptr [3])))) ) ) 
// )

        .dataa(!\A_SPW_TOP|rx_data|mem[55][5]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[47][5]~q ),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [4]),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [3]),
        .datae(!\A_SPW_TOP|rx_data|mem[39][5]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[63][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux12~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux12~18 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux12~18 .lut_mask = 64'h0530F530053FF53F;
defparam \A_SPW_TOP|rx_data|Mux12~18 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X32_Y8_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux12~16 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux12~16_combout  = ( \A_SPW_TOP|rx_data|mem[31][5]~q  & ( \A_SPW_TOP|rx_data|mem[7][5]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & (((!\A_SPW_TOP|rx_data|rd_ptr [3])) # (\A_SPW_TOP|rx_data|mem[15][5]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [4] 
// & (((\A_SPW_TOP|rx_data|rd_ptr [3]) # (\A_SPW_TOP|rx_data|mem[23][5]~q )))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[31][5]~q  & ( \A_SPW_TOP|rx_data|mem[7][5]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & (((!\A_SPW_TOP|rx_data|rd_ptr [3])) # 
// (\A_SPW_TOP|rx_data|mem[15][5]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [4] & (((\A_SPW_TOP|rx_data|mem[23][5]~q  & !\A_SPW_TOP|rx_data|rd_ptr [3])))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[31][5]~q  & ( !\A_SPW_TOP|rx_data|mem[7][5]~q  & ( 
// (!\A_SPW_TOP|rx_data|rd_ptr [4] & (\A_SPW_TOP|rx_data|mem[15][5]~q  & ((\A_SPW_TOP|rx_data|rd_ptr [3])))) # (\A_SPW_TOP|rx_data|rd_ptr [4] & (((\A_SPW_TOP|rx_data|rd_ptr [3]) # (\A_SPW_TOP|rx_data|mem[23][5]~q )))) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|mem[31][5]~q  & ( !\A_SPW_TOP|rx_data|mem[7][5]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & (\A_SPW_TOP|rx_data|mem[15][5]~q  & ((\A_SPW_TOP|rx_data|rd_ptr [3])))) # (\A_SPW_TOP|rx_data|rd_ptr [4] & (((\A_SPW_TOP|rx_data|mem[23][5]~q  & 
// !\A_SPW_TOP|rx_data|rd_ptr [3])))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[15][5]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[23][5]~q ),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [4]),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [3]),
        .datae(!\A_SPW_TOP|rx_data|mem[31][5]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[7][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux12~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux12~16 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux12~16 .lut_mask = 64'h0350035FF350F35F;
defparam \A_SPW_TOP|rx_data|Mux12~16 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X31_Y8_N15
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux12~15 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux12~15_combout  = ( \A_SPW_TOP|rx_data|rd_ptr [4] & ( \A_SPW_TOP|rx_data|mem[6][5]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|mem[22][5]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [3] & ((\A_SPW_TOP|rx_data|mem[30][5]~q ))) ) 
// ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [4] & ( \A_SPW_TOP|rx_data|mem[6][5]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [3]) # (\A_SPW_TOP|rx_data|mem[14][5]~q ) ) ) ) # ( \A_SPW_TOP|rx_data|rd_ptr [4] & ( !\A_SPW_TOP|rx_data|mem[6][5]~q  & ( 
// (!\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|mem[22][5]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [3] & ((\A_SPW_TOP|rx_data|mem[30][5]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [4] & ( !\A_SPW_TOP|rx_data|mem[6][5]~q  & ( (\A_SPW_TOP|rx_data|rd_ptr [3] 
// & \A_SPW_TOP|rx_data|mem[14][5]~q ) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[22][5]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[30][5]~q ),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [3]),
        .datad(!\A_SPW_TOP|rx_data|mem[14][5]~q ),
        .datae(!\A_SPW_TOP|rx_data|rd_ptr [4]),
        .dataf(!\A_SPW_TOP|rx_data|mem[6][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux12~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux12~15 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux12~15 .lut_mask = 64'h000F5353F0FF5353;
defparam \A_SPW_TOP|rx_data|Mux12~15 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X32_Y8_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux12~19 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux12~19_combout  = ( \A_SPW_TOP|rx_data|Mux12~16_combout  & ( \A_SPW_TOP|rx_data|Mux12~15_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [5]) # ((!\A_SPW_TOP|rx_data|rd_ptr [0] & (\A_SPW_TOP|rx_data|Mux12~17_combout )) # 
// (\A_SPW_TOP|rx_data|rd_ptr [0] & ((\A_SPW_TOP|rx_data|Mux12~18_combout )))) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux12~16_combout  & ( \A_SPW_TOP|rx_data|Mux12~15_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & (((!\A_SPW_TOP|rx_data|rd_ptr [5])) # 
// (\A_SPW_TOP|rx_data|Mux12~17_combout ))) # (\A_SPW_TOP|rx_data|rd_ptr [0] & (((\A_SPW_TOP|rx_data|rd_ptr [5] & \A_SPW_TOP|rx_data|Mux12~18_combout )))) ) ) ) # ( \A_SPW_TOP|rx_data|Mux12~16_combout  & ( !\A_SPW_TOP|rx_data|Mux12~15_combout  & ( 
// (!\A_SPW_TOP|rx_data|rd_ptr [0] & (\A_SPW_TOP|rx_data|Mux12~17_combout  & (\A_SPW_TOP|rx_data|rd_ptr [5]))) # (\A_SPW_TOP|rx_data|rd_ptr [0] & (((!\A_SPW_TOP|rx_data|rd_ptr [5]) # (\A_SPW_TOP|rx_data|Mux12~18_combout )))) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|Mux12~16_combout  & ( !\A_SPW_TOP|rx_data|Mux12~15_combout  & ( (\A_SPW_TOP|rx_data|rd_ptr [5] & ((!\A_SPW_TOP|rx_data|rd_ptr [0] & (\A_SPW_TOP|rx_data|Mux12~17_combout )) # (\A_SPW_TOP|rx_data|rd_ptr [0] & 
// ((\A_SPW_TOP|rx_data|Mux12~18_combout ))))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux12~17_combout ),
        .datab(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .datad(!\A_SPW_TOP|rx_data|Mux12~18_combout ),
        .datae(!\A_SPW_TOP|rx_data|Mux12~16_combout ),
        .dataf(!\A_SPW_TOP|rx_data|Mux12~15_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux12~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux12~19 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux12~19 .lut_mask = 64'h04073437C4C7F4F7;
defparam \A_SPW_TOP|rx_data|Mux12~19 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X32_Y5_N15
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux12~11 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux12~11_combout  = ( \A_SPW_TOP|rx_data|mem[5][5]~q  & ( \A_SPW_TOP|rx_data|rd_ptr [3] & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & ((\A_SPW_TOP|rx_data|mem[13][5]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [4] & (\A_SPW_TOP|rx_data|mem[29][5]~q )) ) 
// ) ) # ( !\A_SPW_TOP|rx_data|mem[5][5]~q  & ( \A_SPW_TOP|rx_data|rd_ptr [3] & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & ((\A_SPW_TOP|rx_data|mem[13][5]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [4] & (\A_SPW_TOP|rx_data|mem[29][5]~q )) ) ) ) # ( 
// \A_SPW_TOP|rx_data|mem[5][5]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [3] & ( (!\A_SPW_TOP|rx_data|rd_ptr [4]) # (\A_SPW_TOP|rx_data|mem[21][5]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[5][5]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [3] & ( (\A_SPW_TOP|rx_data|rd_ptr [4] & 
// \A_SPW_TOP|rx_data|mem[21][5]~q ) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[29][5]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[13][5]~q ),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [4]),
        .datad(!\A_SPW_TOP|rx_data|mem[21][5]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[5][5]~q ),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux12~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux12~11 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux12~11 .lut_mask = 64'h000FF0FF35353535;
defparam \A_SPW_TOP|rx_data|Mux12~11 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X33_Y5_N33
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux12~10 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux12~10_combout  = ( \A_SPW_TOP|rx_data|mem[12][5]~q  & ( \A_SPW_TOP|rx_data|mem[4][5]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [4]) # ((!\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|mem[20][5]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [3] & 
// ((\A_SPW_TOP|rx_data|mem[28][5]~q )))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[12][5]~q  & ( \A_SPW_TOP|rx_data|mem[4][5]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [3] & (((!\A_SPW_TOP|rx_data|rd_ptr [4])) # (\A_SPW_TOP|rx_data|mem[20][5]~q ))) # 
// (\A_SPW_TOP|rx_data|rd_ptr [3] & (((\A_SPW_TOP|rx_data|rd_ptr [4] & \A_SPW_TOP|rx_data|mem[28][5]~q )))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[12][5]~q  & ( !\A_SPW_TOP|rx_data|mem[4][5]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|mem[20][5]~q 
//  & (\A_SPW_TOP|rx_data|rd_ptr [4]))) # (\A_SPW_TOP|rx_data|rd_ptr [3] & (((!\A_SPW_TOP|rx_data|rd_ptr [4]) # (\A_SPW_TOP|rx_data|mem[28][5]~q )))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[12][5]~q  & ( !\A_SPW_TOP|rx_data|mem[4][5]~q  & ( 
// (\A_SPW_TOP|rx_data|rd_ptr [4] & ((!\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|mem[20][5]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [3] & ((\A_SPW_TOP|rx_data|mem[28][5]~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [3]),
        .datab(!\A_SPW_TOP|rx_data|mem[20][5]~q ),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [4]),
        .datad(!\A_SPW_TOP|rx_data|mem[28][5]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[12][5]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[4][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux12~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux12~10 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux12~10 .lut_mask = 64'h02075257A2A7F2F7;
defparam \A_SPW_TOP|rx_data|Mux12~10 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X33_Y5_N51
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux12~12 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux12~12_combout  = ( \A_SPW_TOP|rx_data|mem[60][5]~q  & ( \A_SPW_TOP|rx_data|mem[36][5]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [3] & (((!\A_SPW_TOP|rx_data|rd_ptr [4])) # (\A_SPW_TOP|rx_data|mem[52][5]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr 
// [3] & (((\A_SPW_TOP|rx_data|mem[44][5]~q ) # (\A_SPW_TOP|rx_data|rd_ptr [4])))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[60][5]~q  & ( \A_SPW_TOP|rx_data|mem[36][5]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [3] & (((!\A_SPW_TOP|rx_data|rd_ptr [4])) # 
// (\A_SPW_TOP|rx_data|mem[52][5]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [3] & (((!\A_SPW_TOP|rx_data|rd_ptr [4] & \A_SPW_TOP|rx_data|mem[44][5]~q )))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[60][5]~q  & ( !\A_SPW_TOP|rx_data|mem[36][5]~q  & ( 
// (!\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|mem[52][5]~q  & (\A_SPW_TOP|rx_data|rd_ptr [4]))) # (\A_SPW_TOP|rx_data|rd_ptr [3] & (((\A_SPW_TOP|rx_data|mem[44][5]~q ) # (\A_SPW_TOP|rx_data|rd_ptr [4])))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[60][5]~q 
//  & ( !\A_SPW_TOP|rx_data|mem[36][5]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|mem[52][5]~q  & (\A_SPW_TOP|rx_data|rd_ptr [4]))) # (\A_SPW_TOP|rx_data|rd_ptr [3] & (((!\A_SPW_TOP|rx_data|rd_ptr [4] & \A_SPW_TOP|rx_data|mem[44][5]~q )))) 
// ) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [3]),
        .datab(!\A_SPW_TOP|rx_data|mem[52][5]~q ),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [4]),
        .datad(!\A_SPW_TOP|rx_data|mem[44][5]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[60][5]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[36][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux12~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux12~12 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux12~12 .lut_mask = 64'h02520757A2F2A7F7;
defparam \A_SPW_TOP|rx_data|Mux12~12 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X32_Y5_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux12~13 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux12~13_combout  = ( \A_SPW_TOP|rx_data|mem[37][5]~q  & ( \A_SPW_TOP|rx_data|mem[53][5]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [3]) # ((!\A_SPW_TOP|rx_data|rd_ptr [4] & (\A_SPW_TOP|rx_data|mem[45][5]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [4] & 
// ((\A_SPW_TOP|rx_data|mem[61][5]~q )))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[37][5]~q  & ( \A_SPW_TOP|rx_data|mem[53][5]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & (\A_SPW_TOP|rx_data|mem[45][5]~q  & ((\A_SPW_TOP|rx_data|rd_ptr [3])))) # 
// (\A_SPW_TOP|rx_data|rd_ptr [4] & (((!\A_SPW_TOP|rx_data|rd_ptr [3]) # (\A_SPW_TOP|rx_data|mem[61][5]~q )))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[37][5]~q  & ( !\A_SPW_TOP|rx_data|mem[53][5]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & 
// (((!\A_SPW_TOP|rx_data|rd_ptr [3])) # (\A_SPW_TOP|rx_data|mem[45][5]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [4] & (((\A_SPW_TOP|rx_data|mem[61][5]~q  & \A_SPW_TOP|rx_data|rd_ptr [3])))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[37][5]~q  & ( 
// !\A_SPW_TOP|rx_data|mem[53][5]~q  & ( (\A_SPW_TOP|rx_data|rd_ptr [3] & ((!\A_SPW_TOP|rx_data|rd_ptr [4] & (\A_SPW_TOP|rx_data|mem[45][5]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [4] & ((\A_SPW_TOP|rx_data|mem[61][5]~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[45][5]~q ),
        .datab(!\A_SPW_TOP|rx_data|rd_ptr [4]),
        .datac(!\A_SPW_TOP|rx_data|mem[61][5]~q ),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [3]),
        .datae(!\A_SPW_TOP|rx_data|mem[37][5]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[53][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux12~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux12~13 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux12~13 .lut_mask = 64'h0047CC473347FF47;
defparam \A_SPW_TOP|rx_data|Mux12~13 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X32_Y5_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux12~14 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux12~14_combout  = ( \A_SPW_TOP|rx_data|Mux12~12_combout  & ( \A_SPW_TOP|rx_data|Mux12~13_combout  & ( ((!\A_SPW_TOP|rx_data|rd_ptr [0] & ((\A_SPW_TOP|rx_data|Mux12~10_combout ))) # (\A_SPW_TOP|rx_data|rd_ptr [0] & 
// (\A_SPW_TOP|rx_data|Mux12~11_combout ))) # (\A_SPW_TOP|rx_data|rd_ptr [5]) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux12~12_combout  & ( \A_SPW_TOP|rx_data|Mux12~13_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & (((!\A_SPW_TOP|rx_data|rd_ptr [5] & 
// \A_SPW_TOP|rx_data|Mux12~10_combout )))) # (\A_SPW_TOP|rx_data|rd_ptr [0] & (((\A_SPW_TOP|rx_data|rd_ptr [5])) # (\A_SPW_TOP|rx_data|Mux12~11_combout ))) ) ) ) # ( \A_SPW_TOP|rx_data|Mux12~12_combout  & ( !\A_SPW_TOP|rx_data|Mux12~13_combout  & ( 
// (!\A_SPW_TOP|rx_data|rd_ptr [0] & (((\A_SPW_TOP|rx_data|Mux12~10_combout ) # (\A_SPW_TOP|rx_data|rd_ptr [5])))) # (\A_SPW_TOP|rx_data|rd_ptr [0] & (\A_SPW_TOP|rx_data|Mux12~11_combout  & (!\A_SPW_TOP|rx_data|rd_ptr [5]))) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|Mux12~12_combout  & ( !\A_SPW_TOP|rx_data|Mux12~13_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [5] & ((!\A_SPW_TOP|rx_data|rd_ptr [0] & ((\A_SPW_TOP|rx_data|Mux12~10_combout ))) # (\A_SPW_TOP|rx_data|rd_ptr [0] & 
// (\A_SPW_TOP|rx_data|Mux12~11_combout )))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .datab(!\A_SPW_TOP|rx_data|Mux12~11_combout ),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .datad(!\A_SPW_TOP|rx_data|Mux12~10_combout ),
        .datae(!\A_SPW_TOP|rx_data|Mux12~12_combout ),
        .dataf(!\A_SPW_TOP|rx_data|Mux12~13_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux12~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux12~14 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux12~14 .lut_mask = 64'h10B01ABA15B51FBF;
defparam \A_SPW_TOP|rx_data|Mux12~14 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X33_Y8_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux12~8 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux12~8_combout  = ( \A_SPW_TOP|rx_data|mem[51][5]~q  & ( \A_SPW_TOP|rx_data|mem[35][5]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [3]) # ((!\A_SPW_TOP|rx_data|rd_ptr [4] & (\A_SPW_TOP|rx_data|mem[43][5]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [4] & 
// ((\A_SPW_TOP|rx_data|mem[59][5]~q )))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[51][5]~q  & ( \A_SPW_TOP|rx_data|mem[35][5]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & (((!\A_SPW_TOP|rx_data|rd_ptr [3])) # (\A_SPW_TOP|rx_data|mem[43][5]~q ))) # 
// (\A_SPW_TOP|rx_data|rd_ptr [4] & (((\A_SPW_TOP|rx_data|mem[59][5]~q  & \A_SPW_TOP|rx_data|rd_ptr [3])))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[51][5]~q  & ( !\A_SPW_TOP|rx_data|mem[35][5]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & 
// (\A_SPW_TOP|rx_data|mem[43][5]~q  & ((\A_SPW_TOP|rx_data|rd_ptr [3])))) # (\A_SPW_TOP|rx_data|rd_ptr [4] & (((!\A_SPW_TOP|rx_data|rd_ptr [3]) # (\A_SPW_TOP|rx_data|mem[59][5]~q )))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[51][5]~q  & ( 
// !\A_SPW_TOP|rx_data|mem[35][5]~q  & ( (\A_SPW_TOP|rx_data|rd_ptr [3] & ((!\A_SPW_TOP|rx_data|rd_ptr [4] & (\A_SPW_TOP|rx_data|mem[43][5]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [4] & ((\A_SPW_TOP|rx_data|mem[59][5]~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[43][5]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[59][5]~q ),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [4]),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [3]),
        .datae(!\A_SPW_TOP|rx_data|mem[51][5]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[35][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux12~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux12~8 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux12~8 .lut_mask = 64'h00530F53F053FF53;
defparam \A_SPW_TOP|rx_data|Mux12~8 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X32_Y8_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux12~6 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux12~6_combout  = ( \A_SPW_TOP|rx_data|mem[27][5]~q  & ( \A_SPW_TOP|rx_data|mem[19][5]~q  & ( ((!\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|mem[3][5]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [3] & ((\A_SPW_TOP|rx_data|mem[11][5]~q 
// )))) # (\A_SPW_TOP|rx_data|rd_ptr [4]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[27][5]~q  & ( \A_SPW_TOP|rx_data|mem[19][5]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & ((!\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|mem[3][5]~q )) # 
// (\A_SPW_TOP|rx_data|rd_ptr [3] & ((\A_SPW_TOP|rx_data|mem[11][5]~q ))))) # (\A_SPW_TOP|rx_data|rd_ptr [4] & (((!\A_SPW_TOP|rx_data|rd_ptr [3])))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[27][5]~q  & ( !\A_SPW_TOP|rx_data|mem[19][5]~q  & ( 
// (!\A_SPW_TOP|rx_data|rd_ptr [4] & ((!\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|mem[3][5]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [3] & ((\A_SPW_TOP|rx_data|mem[11][5]~q ))))) # (\A_SPW_TOP|rx_data|rd_ptr [4] & (((\A_SPW_TOP|rx_data|rd_ptr [3])))) ) ) 
// ) # ( !\A_SPW_TOP|rx_data|mem[27][5]~q  & ( !\A_SPW_TOP|rx_data|mem[19][5]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & ((!\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|mem[3][5]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [3] & ((\A_SPW_TOP|rx_data|mem[11][5]~q 
// ))))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [4]),
        .datab(!\A_SPW_TOP|rx_data|mem[3][5]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[11][5]~q ),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [3]),
        .datae(!\A_SPW_TOP|rx_data|mem[27][5]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[19][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux12~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux12~6 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux12~6 .lut_mask = 64'h220A225F770A775F;
defparam \A_SPW_TOP|rx_data|Mux12~6 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X31_Y8_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux12~5 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux12~5_combout  = ( \A_SPW_TOP|rx_data|mem[26][5]~q  & ( \A_SPW_TOP|rx_data|mem[10][5]~q  & ( ((!\A_SPW_TOP|rx_data|rd_ptr [4] & (\A_SPW_TOP|rx_data|mem[2][5]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [4] & ((\A_SPW_TOP|rx_data|mem[18][5]~q 
// )))) # (\A_SPW_TOP|rx_data|rd_ptr [3]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[26][5]~q  & ( \A_SPW_TOP|rx_data|mem[10][5]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & (((\A_SPW_TOP|rx_data|rd_ptr [3])) # (\A_SPW_TOP|rx_data|mem[2][5]~q ))) # 
// (\A_SPW_TOP|rx_data|rd_ptr [4] & (((\A_SPW_TOP|rx_data|mem[18][5]~q  & !\A_SPW_TOP|rx_data|rd_ptr [3])))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[26][5]~q  & ( !\A_SPW_TOP|rx_data|mem[10][5]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & 
// (\A_SPW_TOP|rx_data|mem[2][5]~q  & ((!\A_SPW_TOP|rx_data|rd_ptr [3])))) # (\A_SPW_TOP|rx_data|rd_ptr [4] & (((\A_SPW_TOP|rx_data|rd_ptr [3]) # (\A_SPW_TOP|rx_data|mem[18][5]~q )))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[26][5]~q  & ( 
// !\A_SPW_TOP|rx_data|mem[10][5]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [3] & ((!\A_SPW_TOP|rx_data|rd_ptr [4] & (\A_SPW_TOP|rx_data|mem[2][5]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [4] & ((\A_SPW_TOP|rx_data|mem[18][5]~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [4]),
        .datab(!\A_SPW_TOP|rx_data|mem[2][5]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[18][5]~q ),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [3]),
        .datae(!\A_SPW_TOP|rx_data|mem[26][5]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[10][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux12~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux12~5 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux12~5 .lut_mask = 64'h2700275527AA27FF;
defparam \A_SPW_TOP|rx_data|Mux12~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X31_Y8_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux12~7 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux12~7_combout  = ( \A_SPW_TOP|rx_data|mem[42][5]~q  & ( \A_SPW_TOP|rx_data|mem[58][5]~q  & ( ((!\A_SPW_TOP|rx_data|rd_ptr [4] & ((\A_SPW_TOP|rx_data|mem[34][5]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [4] & (\A_SPW_TOP|rx_data|mem[50][5]~q 
// ))) # (\A_SPW_TOP|rx_data|rd_ptr [3]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[42][5]~q  & ( \A_SPW_TOP|rx_data|mem[58][5]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & (((\A_SPW_TOP|rx_data|mem[34][5]~q  & !\A_SPW_TOP|rx_data|rd_ptr [3])))) # 
// (\A_SPW_TOP|rx_data|rd_ptr [4] & (((\A_SPW_TOP|rx_data|rd_ptr [3])) # (\A_SPW_TOP|rx_data|mem[50][5]~q ))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[42][5]~q  & ( !\A_SPW_TOP|rx_data|mem[58][5]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & (((\A_SPW_TOP|rx_data|rd_ptr 
// [3]) # (\A_SPW_TOP|rx_data|mem[34][5]~q )))) # (\A_SPW_TOP|rx_data|rd_ptr [4] & (\A_SPW_TOP|rx_data|mem[50][5]~q  & ((!\A_SPW_TOP|rx_data|rd_ptr [3])))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[42][5]~q  & ( !\A_SPW_TOP|rx_data|mem[58][5]~q  & ( 
// (!\A_SPW_TOP|rx_data|rd_ptr [3] & ((!\A_SPW_TOP|rx_data|rd_ptr [4] & ((\A_SPW_TOP|rx_data|mem[34][5]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [4] & (\A_SPW_TOP|rx_data|mem[50][5]~q )))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [4]),
        .datab(!\A_SPW_TOP|rx_data|mem[50][5]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[34][5]~q ),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [3]),
        .datae(!\A_SPW_TOP|rx_data|mem[42][5]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[58][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux12~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux12~7 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux12~7 .lut_mask = 64'h1B001BAA1B551BFF;
defparam \A_SPW_TOP|rx_data|Mux12~7 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X32_Y8_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux12~9 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux12~9_combout  = ( \A_SPW_TOP|rx_data|rd_ptr [5] & ( \A_SPW_TOP|rx_data|Mux12~7_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [0]) # (\A_SPW_TOP|rx_data|Mux12~8_combout ) ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [5] & ( 
// \A_SPW_TOP|rx_data|Mux12~7_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & ((\A_SPW_TOP|rx_data|Mux12~5_combout ))) # (\A_SPW_TOP|rx_data|rd_ptr [0] & (\A_SPW_TOP|rx_data|Mux12~6_combout )) ) ) ) # ( \A_SPW_TOP|rx_data|rd_ptr [5] & ( 
// !\A_SPW_TOP|rx_data|Mux12~7_combout  & ( (\A_SPW_TOP|rx_data|Mux12~8_combout  & \A_SPW_TOP|rx_data|rd_ptr [0]) ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [5] & ( !\A_SPW_TOP|rx_data|Mux12~7_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & 
// ((\A_SPW_TOP|rx_data|Mux12~5_combout ))) # (\A_SPW_TOP|rx_data|rd_ptr [0] & (\A_SPW_TOP|rx_data|Mux12~6_combout )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux12~8_combout ),
        .datab(!\A_SPW_TOP|rx_data|Mux12~6_combout ),
        .datac(!\A_SPW_TOP|rx_data|Mux12~5_combout ),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .datae(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .dataf(!\A_SPW_TOP|rx_data|Mux12~7_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux12~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux12~9 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux12~9 .lut_mask = 64'h0F3300550F33FF55;
defparam \A_SPW_TOP|rx_data|Mux12~9 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X32_Y8_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux12~20 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux12~20_combout  = ( \A_SPW_TOP|rx_data|Mux12~14_combout  & ( \A_SPW_TOP|rx_data|Mux12~9_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [2] & (((\A_SPW_TOP|rx_data|Mux12~4_combout )) # (\A_SPW_TOP|rx_data|rd_ptr [1]))) # 
// (\A_SPW_TOP|rx_data|rd_ptr [2] & ((!\A_SPW_TOP|rx_data|rd_ptr [1]) # ((\A_SPW_TOP|rx_data|Mux12~19_combout )))) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux12~14_combout  & ( \A_SPW_TOP|rx_data|Mux12~9_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [2] & 
// (((\A_SPW_TOP|rx_data|Mux12~4_combout )) # (\A_SPW_TOP|rx_data|rd_ptr [1]))) # (\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|rd_ptr [1] & ((\A_SPW_TOP|rx_data|Mux12~19_combout )))) ) ) ) # ( \A_SPW_TOP|rx_data|Mux12~14_combout  & ( 
// !\A_SPW_TOP|rx_data|Mux12~9_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [2] & (!\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|Mux12~4_combout ))) # (\A_SPW_TOP|rx_data|rd_ptr [2] & ((!\A_SPW_TOP|rx_data|rd_ptr [1]) # 
// ((\A_SPW_TOP|rx_data|Mux12~19_combout )))) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux12~14_combout  & ( !\A_SPW_TOP|rx_data|Mux12~9_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [2] & (!\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|Mux12~4_combout ))) # 
// (\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|rd_ptr [1] & ((\A_SPW_TOP|rx_data|Mux12~19_combout )))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datab(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datac(!\A_SPW_TOP|rx_data|Mux12~4_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux12~19_combout ),
        .datae(!\A_SPW_TOP|rx_data|Mux12~14_combout ),
        .dataf(!\A_SPW_TOP|rx_data|Mux12~9_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux12~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux12~20 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux12~20 .lut_mask = 64'h08194C5D2A3B6E7F;
defparam \A_SPW_TOP|rx_data|Mux12~20 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X32_Y8_N20
dffeas \A_SPW_TOP|rx_data|data_out[5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|rx_data|Mux12~20_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|data_out [5]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|data_out[5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|data_out[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y16_N42
cyclonev_lcell_comb \u0|data_flag_rx|read_mux_out[5] (
// Equation(s):
// \u0|data_flag_rx|read_mux_out [5] = ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( \A_SPW_TOP|rx_data|data_out [5] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|rx_data|data_out [5]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|data_flag_rx|read_mux_out [5]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|data_flag_rx|read_mux_out[5] .extended_lut = "off";
defparam \u0|data_flag_rx|read_mux_out[5] .lut_mask = 64'h0F0F000000000000;
defparam \u0|data_flag_rx|read_mux_out[5] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y16_N44
dffeas \u0|data_flag_rx|readdata[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|data_flag_rx|read_mux_out [5]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|data_flag_rx|readdata [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|data_flag_rx|readdata[5] .is_wysiwyg = "true";
defparam \u0|data_flag_rx|readdata[5] .power_up = "low";
// synopsys translate_on

// Location: FF_X23_Y16_N43
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|data_flag_rx|readdata [5]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre[5] .power_up = "low";
// synopsys translate_on

// Location: FF_X27_Y16_N23
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y16_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~5 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~5_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][5]~q  & ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1] ) ) # ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][5]~q  & ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [5] ) ) ) # ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][5]~q  & ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [5] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [5]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][5]~q ),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~5 .lut_mask = 64'h0F0F0F0F0000FFFF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y16_N47
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~5_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y16_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~70 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~70_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][5]~q  & ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout  & ( 
// (\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [5] & !\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout ) ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][5]~q  & ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout  & ( (\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [5] & !\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout ) ) ) ) # ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][5]~q  & ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout  & ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout  ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [5]),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout ),
        .datae(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][5]~q ),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~70_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~70 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~70 .lut_mask = 64'h0000FF000F000F00;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~70 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y35_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|read~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|read~0_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][129]~q  & 
// (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0]) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0])))) ) ) # ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0]) # 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0]))) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0]),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0]),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|read~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|read~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|read~0 .lut_mask = 64'h0077007700700070;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|read~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y15_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[1]~1_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0] & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|read~0_combout  & 
// ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [1]) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0]))) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0] & ( 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|read~0_combout  & \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [1]) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|read~0_combout ),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[1]~1 .lut_mask = 64'h00F000F050F050F0;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[1]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y15_N41
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y34_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_020|src_payload~13 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_020|src_payload~13_combout  = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout  & ( \u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_020|src_payload~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~13 .lut_mask = 64'h3333333300000000;
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~13 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y34_N59
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_020|src_payload~13_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y34_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2] = ( \u0|mm_interconnect_0|cmd_mux_020|src_payload~13_combout  & ( 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] & 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_020|src_payload~13_combout  & ( 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout  & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]) 
// # (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_020|src_payload~13_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .lut_mask = 64'h00F500F500A000A0;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y34_N17
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .power_up = "low";
// synopsys translate_on

// Location: FF_X25_Y34_N38
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y34_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_020|src_payload~14 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_020|src_payload~14_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] & ( \u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_020|src_payload~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~14 .lut_mask = 64'h000000000000FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~14 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y34_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0]~feeder_combout  = ( \u0|mm_interconnect_0|cmd_mux_020|src_payload~14_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_020|src_payload~14_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y34_N20
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y34_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_020|src_payload~15 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_020|src_payload~15_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & ( \u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_020|src_payload~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~15 .lut_mask = 64'h000000000000FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~15 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y34_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_020|src_payload~16 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_020|src_payload~16_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & ( \u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_020|src_payload~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~16 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~16 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y34_N50
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_020|src_payload~16_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X23_Y34_N35
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_020|src_payload~15_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y34_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// (!\u0|mm_interconnect_0|cmd_mux_020|src_payload~15_combout  & \u0|mm_interconnect_0|cmd_mux_020|src_payload~16_combout ) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_020|src_payload~15_combout ),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_020|src_payload~16_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .lut_mask = 64'h3030303000AA00AA;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y34_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  & ( 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]))) # 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|cmd_mux_020|src_payload~14_combout )) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_020|src_payload~14_combout ),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .lut_mask = 64'h00000000F0CCF0CC;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y34_N38
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y34_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & ( (!\u0|mm_interconnect_0|cmd_mux_020|src_payload~15_combout  & (!\u0|mm_interconnect_0|cmd_mux_020|src_payload~16_combout  & 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & ( (!\u0|mm_interconnect_0|cmd_mux_020|src_payload~15_combout  & (!\u0|mm_interconnect_0|cmd_mux_020|src_payload~16_combout  & 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) ) # ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & ( (!\u0|mm_interconnect_0|cmd_mux_020|src_payload~15_combout  & (!\u0|mm_interconnect_0|cmd_mux_020|src_payload~16_combout  & 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # 
// ((!\u0|mm_interconnect_0|cmd_mux_020|src_payload~15_combout  & !\u0|mm_interconnect_0|cmd_mux_020|src_payload~16_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_020|src_payload~15_combout ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_020|src_payload~16_combout ),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .lut_mask = 64'hF8F8080808080808;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y34_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  & ( 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) # 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((\u0|mm_interconnect_0|cmd_mux_020|src_payload~14_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_020|src_payload~14_combout ),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .lut_mask = 64'h0000000053535353;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y34_N41
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y34_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  = ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]))) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|cmd_mux_020|src_payload~14_combout )) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_020|src_payload~14_combout ),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .lut_mask = 64'hFFFFFFFF0F330F33;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y34_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout  = ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .lut_mask = 64'hFFFFFFFF00000000;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y34_N35
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y34_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout  = SUM(( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) 
// + ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14  = CARRY(( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) + ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
        .cout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y34_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_020|src_payload~18 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_020|src_payload~18_combout  = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~2_combout  & ( \u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_020|src_payload~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~18 .lut_mask = 64'h3333333300000000;
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~18 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y34_N56
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_020|src_payload~18_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y34_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0] = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  & ( 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0])) # 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|cmd_mux_020|src_payload~18_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_020|src_payload~18_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .lut_mask = 64'h00000000F5A0F5A0;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y34_N13
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y34_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  = ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  
// & ( ((((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout  & \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0])) # 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]))) ) ) # ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ( ((\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [0])))) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [0]),
        .datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
        .datag(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .extended_lut = "on";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .lut_mask = 64'h05050030FFFF0030;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y34_N43
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y34_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout  = SUM(( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + 
// ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14  ))
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10  = CARRY(( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14  ))

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
        .cout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .lut_mask = 64'h0000AAAA00000F0F;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y34_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_020|src_payload~17 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_020|src_payload~17_combout  = (\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~1_combout )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~1_combout ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_020|src_payload~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~17 .lut_mask = 64'h0033003300330033;
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~17 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y34_N23
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_020|src_payload~17_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y34_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1] = ( \u0|mm_interconnect_0|cmd_mux_020|src_payload~17_combout  & ( 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1] & 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_020|src_payload~17_combout  & ( 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout  & 
// ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_020|src_payload~17_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .lut_mask = 64'h00F500F500A000A0;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y34_N32
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y34_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout  = ( !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & ( \u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & ( 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [1] & !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1])) ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [1]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .lut_mask = 64'h0000000003000000;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y34_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout  = ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout  ) # ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout  & ( 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout  & 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1])) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]))) ) 
// )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .lut_mask = 64'h0A2A0A2AFFFFFFFF;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y34_N28
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y34_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout  = SUM(( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + 
// ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10  ))
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6  = CARRY(( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
        .cout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .lut_mask = 64'h0000FF0000000F0F;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y34_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout  = ( \u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout  & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg 
// [2])))) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [2])) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout  & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]))) 
// ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout  & ( 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]))) # 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [2])) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout  & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]) ) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [2]),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
        .datae(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .lut_mask = 64'h00F005F530F035F5;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y34_N41
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y34_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_020|src_payload~12 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_020|src_payload~12_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout  & ( \u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_020|src_payload~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~12 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~12 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y34_N20
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_020|src_payload~12_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y34_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3] = ( \u0|mm_interconnect_0|cmd_mux_020|src_payload~12_combout  & ( 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3] & 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_020|src_payload~12_combout  & ( 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout  & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]) 
// # (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_020|src_payload~12_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .lut_mask = 64'h00F500F500A000A0;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y34_N26
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .power_up = "low";
// synopsys translate_on

// Location: FF_X25_Y34_N50
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y34_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  & ( 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) # 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((\u0|mm_interconnect_0|cmd_mux_020|src_payload~14_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_020|src_payload~14_combout ),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .lut_mask = 64'h0000000053535353;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y34_N28
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y34_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout  = SUM(( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3] 
// ) + ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3] ) + ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6  ))

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .lut_mask = 64'h0000AAAA000000FF;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y34_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout  & ( (\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [3]) ) ) ) # ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout  & ( 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]) ) ) 
// ) # ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout  & ( 
// (\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [3]) ) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout  & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3] ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [3]),
        .datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .lut_mask = 64'h0F0F00335F5F0033;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y34_N53
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y14_N57
cyclonev_lcell_comb \u0|counter_tx_fifo|read_mux_out[5]~5 (
// Equation(s):
// \u0|counter_tx_fifo|read_mux_out[5]~5_combout  = ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( (\A_SPW_TOP|tx_data|counter [5] & 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|tx_data|counter [5]),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|counter_tx_fifo|read_mux_out[5]~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|counter_tx_fifo|read_mux_out[5]~5 .extended_lut = "off";
defparam \u0|counter_tx_fifo|read_mux_out[5]~5 .lut_mask = 64'h0F000F0000000000;
defparam \u0|counter_tx_fifo|read_mux_out[5]~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y14_N58
dffeas \u0|counter_tx_fifo|readdata[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|counter_tx_fifo|read_mux_out[5]~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|counter_tx_fifo|readdata [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|counter_tx_fifo|readdata[5] .is_wysiwyg = "true";
defparam \u0|counter_tx_fifo|readdata[5] .power_up = "low";
// synopsys translate_on

// Location: FF_X27_Y15_N20
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|counter_tx_fifo|readdata [5]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre[5] .power_up = "low";
// synopsys translate_on

// Location: FF_X27_Y15_N10
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~5_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y15_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~5 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~5_combout  = (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [1] & (\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [5])) # 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [1] & ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][5]~q )))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [5]),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][5]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~5 .lut_mask = 64'h0C3F0C3F0C3F0C3F;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y15_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|always0~0_combout  = (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0]) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|read~0_combout )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|read~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|always0~0 .lut_mask = 64'hAFAFAFAFAFAFAFAF;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y15_N46
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~5_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y15_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~72 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~72_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0] & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0] & 
// ((\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [5]))) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0] & (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][5]~q )) ) ) # ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][5]~q  ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][5]~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [5]),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~72_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~72 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~72 .lut_mask = 64'h555555550F550F55;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~72 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X54_Y5_N2
dffeas \m_x|bit_d_0 (
        .clk(!\m_x|always3~0_combout ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|tx_dout_e~q ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|bit_d_0~q ),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|bit_d_0 .is_wysiwyg = "true";
defparam \m_x|bit_d_0 .power_up = "low";
// synopsys translate_on

// Location: FF_X54_Y5_N59
dffeas \m_x|bit_d_2 (
        .clk(!\m_x|always3~0_combout ),
        .d(gnd),
        .asdata(\m_x|bit_d_0~q ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|bit_d_2~q ),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|bit_d_2 .is_wysiwyg = "true";
defparam \m_x|bit_d_2 .power_up = "low";
// synopsys translate_on

// Location: FF_X53_Y5_N32
dffeas \m_x|bit_d_4 (
        .clk(!\m_x|always3~0_combout ),
        .d(gnd),
        .asdata(\m_x|bit_d_2~q ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|bit_d_4~q ),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|bit_d_4 .is_wysiwyg = "true";
defparam \m_x|bit_d_4 .power_up = "low";
// synopsys translate_on

// Location: FF_X53_Y5_N56
dffeas \m_x|bit_d_6 (
        .clk(!\m_x|always3~0_combout ),
        .d(gnd),
        .asdata(\m_x|bit_d_4~q ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|bit_d_6~q ),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|bit_d_6 .is_wysiwyg = "true";
defparam \m_x|bit_d_6 .power_up = "low";
// synopsys translate_on

// Location: FF_X54_Y5_N40
dffeas \m_x|bit_d_8 (
        .clk(!\m_x|always3~0_combout ),
        .d(gnd),
        .asdata(\m_x|bit_d_6~q ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|bit_d_8~q ),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|bit_d_8 .is_wysiwyg = "true";
defparam \m_x|bit_d_8 .power_up = "low";
// synopsys translate_on

// Location: FF_X53_Y5_N38
dffeas \m_x|dta_timec[8] (
        .clk(\m_x|ready_data~combout ),
        .d(gnd),
        .asdata(\m_x|bit_d_8~q ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|dta_timec [8]),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|dta_timec[8] .is_wysiwyg = "true";
defparam \m_x|dta_timec[8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X51_Y5_N42
cyclonev_lcell_comb \m_x|bit_d_1~feeder (
// Equation(s):
// \m_x|bit_d_1~feeder_combout  = ( \A_SPW_TOP|SPW|TX|tx_dout_e~q  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|tx_dout_e~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|bit_d_1~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|bit_d_1~feeder .extended_lut = "off";
defparam \m_x|bit_d_1~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \m_x|bit_d_1~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X51_Y5_N44
dffeas \m_x|bit_d_1 (
        .clk(\m_x|always3~0_combout ),
        .d(\m_x|bit_d_1~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|bit_d_1~q ),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|bit_d_1 .is_wysiwyg = "true";
defparam \m_x|bit_d_1 .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X51_Y5_N33
cyclonev_lcell_comb \m_x|bit_d_3~feeder (
// Equation(s):
// \m_x|bit_d_3~feeder_combout  = ( \m_x|bit_d_1~q  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\m_x|bit_d_1~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|bit_d_3~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|bit_d_3~feeder .extended_lut = "off";
defparam \m_x|bit_d_3~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \m_x|bit_d_3~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X51_Y5_N35
dffeas \m_x|bit_d_3 (
        .clk(\m_x|always3~0_combout ),
        .d(\m_x|bit_d_3~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|bit_d_3~q ),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|bit_d_3 .is_wysiwyg = "true";
defparam \m_x|bit_d_3 .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X51_Y5_N6
cyclonev_lcell_comb \m_x|bit_d_5~feeder (
// Equation(s):
// \m_x|bit_d_5~feeder_combout  = ( \m_x|bit_d_3~q  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\m_x|bit_d_3~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|bit_d_5~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|bit_d_5~feeder .extended_lut = "off";
defparam \m_x|bit_d_5~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \m_x|bit_d_5~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X51_Y5_N8
dffeas \m_x|bit_d_5 (
        .clk(\m_x|always3~0_combout ),
        .d(\m_x|bit_d_5~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|bit_d_5~q ),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|bit_d_5 .is_wysiwyg = "true";
defparam \m_x|bit_d_5 .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X51_Y5_N51
cyclonev_lcell_comb \m_x|bit_d_7~feeder (
// Equation(s):
// \m_x|bit_d_7~feeder_combout  = ( \m_x|bit_d_5~q  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\m_x|bit_d_5~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|bit_d_7~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|bit_d_7~feeder .extended_lut = "off";
defparam \m_x|bit_d_7~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \m_x|bit_d_7~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X51_Y5_N53
dffeas \m_x|bit_d_7 (
        .clk(\m_x|always3~0_combout ),
        .d(\m_x|bit_d_7~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|bit_d_7~q ),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|bit_d_7 .is_wysiwyg = "true";
defparam \m_x|bit_d_7 .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X51_Y5_N54
cyclonev_lcell_comb \m_x|bit_d_9~feeder (
// Equation(s):
// \m_x|bit_d_9~feeder_combout  = ( \m_x|bit_d_7~q  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\m_x|bit_d_7~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|bit_d_9~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|bit_d_9~feeder .extended_lut = "off";
defparam \m_x|bit_d_9~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \m_x|bit_d_9~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X51_Y5_N55
dffeas \m_x|bit_d_9 (
        .clk(\m_x|always3~0_combout ),
        .d(\m_x|bit_d_9~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|bit_d_9~q ),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|bit_d_9 .is_wysiwyg = "true";
defparam \m_x|bit_d_9 .power_up = "low";
// synopsys translate_on

// Location: FF_X53_Y5_N17
dffeas \m_x|parity_rec_d (
        .clk(\m_x|ready_data~combout ),
        .d(gnd),
        .asdata(\m_x|bit_d_9~q ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|parity_rec_d~q ),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|parity_rec_d .is_wysiwyg = "true";
defparam \m_x|parity_rec_d .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X53_Y5_N42
cyclonev_lcell_comb \m_x|always16~0 (
// Equation(s):
// \m_x|always16~0_combout  = !\m_x|dta_timec [8] $ (!\m_x|parity_rec_d~q )

        .dataa(!\m_x|dta_timec [8]),
        .datab(!\m_x|parity_rec_d~q ),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|always16~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|always16~0 .extended_lut = "off";
defparam \m_x|always16~0 .lut_mask = 64'h6666666666666666;
defparam \m_x|always16~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X54_Y9_N21
cyclonev_lcell_comb \m_x|rx_got_time_code~0 (
// Equation(s):
// \m_x|rx_got_time_code~0_combout  = ( \m_x|control [1] & ( (\m_x|control [0] & \m_x|control [2]) ) )

        .dataa(!\m_x|control [0]),
        .datab(gnd),
        .datac(!\m_x|control [2]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\m_x|control [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|rx_got_time_code~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|rx_got_time_code~0 .extended_lut = "off";
defparam \m_x|rx_got_time_code~0 .lut_mask = 64'h0000000005050505;
defparam \m_x|rx_got_time_code~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X54_Y9_N39
cyclonev_lcell_comb \m_x|last_is_data~0 (
// Equation(s):
// \m_x|last_is_data~0_combout  = ( !\m_x|ready_control_p_r~q  & ( (!\m_x|ready_data_p_r~q  & ((\m_x|last_is_data~q ))) # (\m_x|ready_data_p_r~q  & (!\m_x|rx_got_time_code~0_combout )) ) )

        .dataa(!\m_x|rx_got_time_code~0_combout ),
        .datab(!\m_x|last_is_data~q ),
        .datac(!\m_x|ready_data_p_r~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\m_x|ready_control_p_r~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|last_is_data~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|last_is_data~0 .extended_lut = "off";
defparam \m_x|last_is_data~0 .lut_mask = 64'h3A3A3A3A00000000;
defparam \m_x|last_is_data~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X54_Y9_N32
dffeas \m_x|last_is_data (
        .clk(!\m_x|always3~0_combout ),
        .d(gnd),
        .asdata(\m_x|last_is_data~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(!\m_x|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|last_is_data~q ),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|last_is_data .is_wysiwyg = "true";
defparam \m_x|last_is_data .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X54_Y9_N45
cyclonev_lcell_comb \m_x|last_is_control~0 (
// Equation(s):
// \m_x|last_is_control~0_combout  = ( \m_x|last_is_control~q  & ( (!\m_x|ready_data_p_r~q ) # (\m_x|ready_control_p_r~q ) ) ) # ( !\m_x|last_is_control~q  & ( \m_x|ready_control_p_r~q  ) )

        .dataa(!\m_x|ready_control_p_r~q ),
        .datab(gnd),
        .datac(!\m_x|ready_data_p_r~q ),
        .datad(gnd),
        .datae(!\m_x|last_is_control~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|last_is_control~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|last_is_control~0 .extended_lut = "off";
defparam \m_x|last_is_control~0 .lut_mask = 64'h5555F5F55555F5F5;
defparam \m_x|last_is_control~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X54_Y9_N20
dffeas \m_x|last_is_control (
        .clk(!\m_x|always3~0_combout ),
        .d(gnd),
        .asdata(\m_x|last_is_control~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(!\m_x|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|last_is_control~q ),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|last_is_control .is_wysiwyg = "true";
defparam \m_x|last_is_control .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X54_Y9_N48
cyclonev_lcell_comb \m_x|rx_error_d~1 (
// Equation(s):
// \m_x|rx_error_d~1_combout  = ( !\m_x|last_is_control~q  & ( \m_x|last_is_data~q  ) )

        .dataa(gnd),
        .datab(!\m_x|last_is_data~q ),
        .datac(gnd),
        .datad(gnd),
        .datae(!\m_x|last_is_control~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|rx_error_d~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|rx_error_d~1 .extended_lut = "off";
defparam \m_x|rx_error_d~1 .lut_mask = 64'h3333000033330000;
defparam \m_x|rx_error_d~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X51_Y5_N24
cyclonev_lcell_comb \m_x|dta_timec[0]~feeder (
// Equation(s):
// \m_x|dta_timec[0]~feeder_combout  = ( \m_x|bit_d_7~q  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\m_x|bit_d_7~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|dta_timec[0]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|dta_timec[0]~feeder .extended_lut = "off";
defparam \m_x|dta_timec[0]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \m_x|dta_timec[0]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X51_Y5_N26
dffeas \m_x|dta_timec[0] (
        .clk(\m_x|ready_data~combout ),
        .d(\m_x|dta_timec[0]~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|dta_timec [0]),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|dta_timec[0] .is_wysiwyg = "true";
defparam \m_x|dta_timec[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y5_N27
cyclonev_lcell_comb \m_x|dta_timec_p[0]~feeder (
// Equation(s):
// \m_x|dta_timec_p[0]~feeder_combout  = ( \m_x|dta_timec [0] )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\m_x|dta_timec [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|dta_timec_p[0]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|dta_timec_p[0]~feeder .extended_lut = "off";
defparam \m_x|dta_timec_p[0]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \m_x|dta_timec_p[0]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y5_N28
dffeas \m_x|dta_timec_p[0] (
        .clk(\m_x|ready_data_p~combout ),
        .d(\m_x|dta_timec_p[0]~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|dta_timec_p [0]),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|dta_timec_p[0] .is_wysiwyg = "true";
defparam \m_x|dta_timec_p[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X54_Y9_N57
cyclonev_lcell_comb \m_x|data~0 (
// Equation(s):
// \m_x|data~0_combout  = ( \m_x|control [2] & ( \m_x|control [1] & ( (!\m_x|ready_control_p_r~q  & (\m_x|ready_data_p_r~q  & !\m_x|control [0])) ) ) ) # ( !\m_x|control [2] & ( \m_x|control [1] & ( (!\m_x|ready_control_p_r~q  & \m_x|ready_data_p_r~q ) ) ) ) 
// # ( \m_x|control [2] & ( !\m_x|control [1] & ( (!\m_x|ready_control_p_r~q  & \m_x|ready_data_p_r~q ) ) ) ) # ( !\m_x|control [2] & ( !\m_x|control [1] & ( (!\m_x|ready_control_p_r~q  & \m_x|ready_data_p_r~q ) ) ) )

        .dataa(!\m_x|ready_control_p_r~q ),
        .datab(!\m_x|ready_data_p_r~q ),
        .datac(gnd),
        .datad(!\m_x|control [0]),
        .datae(!\m_x|control [2]),
        .dataf(!\m_x|control [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|data~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|data~0 .extended_lut = "off";
defparam \m_x|data~0 .lut_mask = 64'h2222222222222200;
defparam \m_x|data~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y5_N33
cyclonev_lcell_comb \m_x|data~8 (
// Equation(s):
// \m_x|data~8_combout  = ( \m_x|data~0_combout  & ( \m_x|dta_timec_p [0] ) ) # ( !\m_x|data~0_combout  & ( \m_x|data [0] ) )

        .dataa(gnd),
        .datab(!\m_x|dta_timec_p [0]),
        .datac(!\m_x|data [0]),
        .datad(gnd),
        .datae(!\m_x|data~0_combout ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|data~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|data~8 .extended_lut = "off";
defparam \m_x|data~8 .lut_mask = 64'h0F0F33330F0F3333;
defparam \m_x|data~8 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y5_N18
cyclonev_lcell_comb \m_x|data[0]~feeder (
// Equation(s):
// \m_x|data[0]~feeder_combout  = \m_x|data~8_combout 

        .dataa(gnd),
        .datab(gnd),
        .datac(!\m_x|data~8_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|data[0]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|data[0]~feeder .extended_lut = "off";
defparam \m_x|data[0]~feeder .lut_mask = 64'h0F0F0F0F0F0F0F0F;
defparam \m_x|data[0]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y5_N19
dffeas \m_x|data[0] (
        .clk(!\m_x|always3~0_combout ),
        .d(\m_x|data[0]~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(!\m_x|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|data [0]),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|data[0] .is_wysiwyg = "true";
defparam \m_x|data[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X53_Y5_N40
dffeas \m_x|dta_timec[1] (
        .clk(\m_x|ready_data~combout ),
        .d(gnd),
        .asdata(\m_x|bit_d_6~q ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|dta_timec [1]),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|dta_timec[1] .is_wysiwyg = "true";
defparam \m_x|dta_timec[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X50_Y5_N4
dffeas \m_x|dta_timec_p[1] (
        .clk(\m_x|ready_data_p~combout ),
        .d(gnd),
        .asdata(\m_x|dta_timec [1]),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|dta_timec_p [1]),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|dta_timec_p[1] .is_wysiwyg = "true";
defparam \m_x|dta_timec_p[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y5_N36
cyclonev_lcell_comb \m_x|data~7 (
// Equation(s):
// \m_x|data~7_combout  = ( \m_x|data~0_combout  & ( \m_x|data [1] & ( \m_x|dta_timec_p [1] ) ) ) # ( !\m_x|data~0_combout  & ( \m_x|data [1] ) ) # ( \m_x|data~0_combout  & ( !\m_x|data [1] & ( \m_x|dta_timec_p [1] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\m_x|dta_timec_p [1]),
        .datad(gnd),
        .datae(!\m_x|data~0_combout ),
        .dataf(!\m_x|data [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|data~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|data~7 .extended_lut = "off";
defparam \m_x|data~7 .lut_mask = 64'h00000F0FFFFF0F0F;
defparam \m_x|data~7 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y5_N14
dffeas \m_x|data[1] (
        .clk(!\m_x|always3~0_combout ),
        .d(gnd),
        .asdata(\m_x|data~7_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(!\m_x|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|data [1]),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|data[1] .is_wysiwyg = "true";
defparam \m_x|data[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y5_N15
cyclonev_lcell_comb \m_x|always17~1 (
// Equation(s):
// \m_x|always17~1_combout  = ( \m_x|data [1] & ( !\m_x|data [0] ) ) # ( !\m_x|data [1] & ( \m_x|data [0] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\m_x|data [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\m_x|data [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|always17~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|always17~1 .extended_lut = "off";
defparam \m_x|always17~1 .lut_mask = 64'h0F0F0F0FF0F0F0F0;
defparam \m_x|always17~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X53_Y5_N45
cyclonev_lcell_comb \m_x|rx_error_d~0 (
// Equation(s):
// \m_x|rx_error_d~0_combout  = ( \m_x|control [0] & ( (\m_x|last_is_control~q  & (!\m_x|dta_timec [8] $ (!\m_x|parity_rec_d~q  $ (\m_x|control [1])))) ) ) # ( !\m_x|control [0] & ( (\m_x|last_is_control~q  & (!\m_x|dta_timec [8] $ (!\m_x|parity_rec_d~q  $ 
// (!\m_x|control [1])))) ) )

        .dataa(!\m_x|dta_timec [8]),
        .datab(!\m_x|parity_rec_d~q ),
        .datac(!\m_x|control [1]),
        .datad(!\m_x|last_is_control~q ),
        .datae(gnd),
        .dataf(!\m_x|control [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|rx_error_d~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|rx_error_d~0 .extended_lut = "off";
defparam \m_x|rx_error_d~0 .lut_mask = 64'h0096009600690069;
defparam \m_x|rx_error_d~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X53_Y5_N22
dffeas \m_x|dta_timec[7] (
        .clk(\m_x|ready_data~combout ),
        .d(gnd),
        .asdata(\m_x|bit_d_0~q ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|dta_timec [7]),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|dta_timec[7] .is_wysiwyg = "true";
defparam \m_x|dta_timec[7] .power_up = "low";
// synopsys translate_on

// Location: FF_X56_Y5_N31
dffeas \m_x|dta_timec_p[7] (
        .clk(\m_x|ready_data_p~combout ),
        .d(gnd),
        .asdata(\m_x|dta_timec [7]),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|dta_timec_p [7]),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|dta_timec_p[7] .is_wysiwyg = "true";
defparam \m_x|dta_timec_p[7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X54_Y9_N27
cyclonev_lcell_comb \m_x|data~1 (
// Equation(s):
// \m_x|data~1_combout  = ( \m_x|data~0_combout  & ( \m_x|dta_timec_p [7] ) ) # ( !\m_x|data~0_combout  & ( \m_x|data [7] ) )

        .dataa(!\m_x|data [7]),
        .datab(gnd),
        .datac(!\m_x|dta_timec_p [7]),
        .datad(gnd),
        .datae(!\m_x|data~0_combout ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|data~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|data~1 .extended_lut = "off";
defparam \m_x|data~1 .lut_mask = 64'h55550F0F55550F0F;
defparam \m_x|data~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X54_Y9_N26
dffeas \m_x|data[7] (
        .clk(!\m_x|always3~0_combout ),
        .d(gnd),
        .asdata(\m_x|data~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(!\m_x|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|data [7]),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|data[7] .is_wysiwyg = "true";
defparam \m_x|data[7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X51_Y5_N39
cyclonev_lcell_comb \m_x|dta_timec[4]~feeder (
// Equation(s):
// \m_x|dta_timec[4]~feeder_combout  = ( \m_x|bit_d_3~q  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\m_x|bit_d_3~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|dta_timec[4]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|dta_timec[4]~feeder .extended_lut = "off";
defparam \m_x|dta_timec[4]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \m_x|dta_timec[4]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X51_Y5_N41
dffeas \m_x|dta_timec[4] (
        .clk(\m_x|ready_data~combout ),
        .d(\m_x|dta_timec[4]~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|dta_timec [4]),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|dta_timec[4] .is_wysiwyg = "true";
defparam \m_x|dta_timec[4] .power_up = "low";
// synopsys translate_on

// Location: FF_X50_Y5_N32
dffeas \m_x|dta_timec_p[4] (
        .clk(\m_x|ready_data_p~combout ),
        .d(gnd),
        .asdata(\m_x|dta_timec [4]),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|dta_timec_p [4]),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|dta_timec_p[4] .is_wysiwyg = "true";
defparam \m_x|dta_timec_p[4] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y5_N0
cyclonev_lcell_comb \m_x|data~4 (
// Equation(s):
// \m_x|data~4_combout  = ( \m_x|dta_timec_p [4] & ( (\m_x|data [4]) # (\m_x|data~0_combout ) ) ) # ( !\m_x|dta_timec_p [4] & ( (!\m_x|data~0_combout  & \m_x|data [4]) ) )

        .dataa(!\m_x|data~0_combout ),
        .datab(gnd),
        .datac(gnd),
        .datad(!\m_x|data [4]),
        .datae(gnd),
        .dataf(!\m_x|dta_timec_p [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|data~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|data~4 .extended_lut = "off";
defparam \m_x|data~4 .lut_mask = 64'h00AA00AA55FF55FF;
defparam \m_x|data~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y5_N47
dffeas \m_x|data[4] (
        .clk(!\m_x|always3~0_combout ),
        .d(gnd),
        .asdata(\m_x|data~4_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(!\m_x|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|data [4]),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|data[4] .is_wysiwyg = "true";
defparam \m_x|data[4] .power_up = "low";
// synopsys translate_on

// Location: FF_X53_Y5_N4
dffeas \m_x|dta_timec[5] (
        .clk(\m_x|ready_data~combout ),
        .d(gnd),
        .asdata(\m_x|bit_d_2~q ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|dta_timec [5]),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|dta_timec[5] .is_wysiwyg = "true";
defparam \m_x|dta_timec[5] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y5_N48
cyclonev_lcell_comb \m_x|dta_timec_p[5]~feeder (
// Equation(s):
// \m_x|dta_timec_p[5]~feeder_combout  = ( \m_x|dta_timec [5] )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\m_x|dta_timec [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|dta_timec_p[5]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|dta_timec_p[5]~feeder .extended_lut = "off";
defparam \m_x|dta_timec_p[5]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \m_x|dta_timec_p[5]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y5_N50
dffeas \m_x|dta_timec_p[5] (
        .clk(\m_x|ready_data_p~combout ),
        .d(\m_x|dta_timec_p[5]~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|dta_timec_p [5]),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|dta_timec_p[5] .is_wysiwyg = "true";
defparam \m_x|dta_timec_p[5] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y5_N21
cyclonev_lcell_comb \m_x|data~3 (
// Equation(s):
// \m_x|data~3_combout  = ( \m_x|dta_timec_p [5] & ( (\m_x|data~0_combout ) # (\m_x|data [5]) ) ) # ( !\m_x|dta_timec_p [5] & ( (\m_x|data [5] & !\m_x|data~0_combout ) ) )

        .dataa(!\m_x|data [5]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\m_x|data~0_combout ),
        .datae(gnd),
        .dataf(!\m_x|dta_timec_p [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|data~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|data~3 .extended_lut = "off";
defparam \m_x|data~3 .lut_mask = 64'h5500550055FF55FF;
defparam \m_x|data~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y5_N20
dffeas \m_x|data[5] (
        .clk(!\m_x|always3~0_combout ),
        .d(gnd),
        .asdata(\m_x|data~3_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(!\m_x|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|data [5]),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|data[5] .is_wysiwyg = "true";
defparam \m_x|data[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X53_Y5_N0
cyclonev_lcell_comb \m_x|dta_timec[3]~feeder (
// Equation(s):
// \m_x|dta_timec[3]~feeder_combout  = ( \m_x|bit_d_4~q  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\m_x|bit_d_4~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|dta_timec[3]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|dta_timec[3]~feeder .extended_lut = "off";
defparam \m_x|dta_timec[3]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \m_x|dta_timec[3]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X53_Y5_N1
dffeas \m_x|dta_timec[3] (
        .clk(\m_x|ready_data~combout ),
        .d(\m_x|dta_timec[3]~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|dta_timec [3]),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|dta_timec[3] .is_wysiwyg = "true";
defparam \m_x|dta_timec[3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y5_N51
cyclonev_lcell_comb \m_x|dta_timec_p[3]~feeder (
// Equation(s):
// \m_x|dta_timec_p[3]~feeder_combout  = ( \m_x|dta_timec [3] )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\m_x|dta_timec [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|dta_timec_p[3]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|dta_timec_p[3]~feeder .extended_lut = "off";
defparam \m_x|dta_timec_p[3]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \m_x|dta_timec_p[3]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y5_N53
dffeas \m_x|dta_timec_p[3] (
        .clk(\m_x|ready_data_p~combout ),
        .d(\m_x|dta_timec_p[3]~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|dta_timec_p [3]),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|dta_timec_p[3] .is_wysiwyg = "true";
defparam \m_x|dta_timec_p[3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y5_N54
cyclonev_lcell_comb \m_x|data~5 (
// Equation(s):
// \m_x|data~5_combout  = ( \m_x|data~0_combout  & ( \m_x|dta_timec_p [3] ) ) # ( !\m_x|data~0_combout  & ( \m_x|data [3] ) )

        .dataa(gnd),
        .datab(!\m_x|data [3]),
        .datac(!\m_x|dta_timec_p [3]),
        .datad(gnd),
        .datae(!\m_x|data~0_combout ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|data~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|data~5 .extended_lut = "off";
defparam \m_x|data~5 .lut_mask = 64'h33330F0F33330F0F;
defparam \m_x|data~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y5_N11
dffeas \m_x|data[3] (
        .clk(!\m_x|always3~0_combout ),
        .d(gnd),
        .asdata(\m_x|data~5_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(!\m_x|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|data [3]),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|data[3] .is_wysiwyg = "true";
defparam \m_x|data[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X51_Y5_N18
cyclonev_lcell_comb \m_x|dta_timec[2]~feeder (
// Equation(s):
// \m_x|dta_timec[2]~feeder_combout  = ( \m_x|bit_d_5~q  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\m_x|bit_d_5~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|dta_timec[2]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|dta_timec[2]~feeder .extended_lut = "off";
defparam \m_x|dta_timec[2]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \m_x|dta_timec[2]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X51_Y5_N19
dffeas \m_x|dta_timec[2] (
        .clk(\m_x|ready_data~combout ),
        .d(\m_x|dta_timec[2]~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|dta_timec [2]),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|dta_timec[2] .is_wysiwyg = "true";
defparam \m_x|dta_timec[2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y5_N24
cyclonev_lcell_comb \m_x|dta_timec_p[2]~feeder (
// Equation(s):
// \m_x|dta_timec_p[2]~feeder_combout  = ( \m_x|dta_timec [2] )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\m_x|dta_timec [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|dta_timec_p[2]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|dta_timec_p[2]~feeder .extended_lut = "off";
defparam \m_x|dta_timec_p[2]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \m_x|dta_timec_p[2]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y5_N26
dffeas \m_x|dta_timec_p[2] (
        .clk(\m_x|ready_data_p~combout ),
        .d(\m_x|dta_timec_p[2]~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|dta_timec_p [2]),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|dta_timec_p[2] .is_wysiwyg = "true";
defparam \m_x|dta_timec_p[2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y5_N42
cyclonev_lcell_comb \m_x|data~6 (
// Equation(s):
// \m_x|data~6_combout  = ( \m_x|data~0_combout  & ( \m_x|dta_timec_p [2] ) ) # ( !\m_x|data~0_combout  & ( \m_x|data [2] ) )

        .dataa(gnd),
        .datab(!\m_x|data [2]),
        .datac(!\m_x|dta_timec_p [2]),
        .datad(gnd),
        .datae(!\m_x|data~0_combout ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|data~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|data~6 .extended_lut = "off";
defparam \m_x|data~6 .lut_mask = 64'h33330F0F33330F0F;
defparam \m_x|data~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y5_N59
dffeas \m_x|data[2] (
        .clk(!\m_x|always3~0_combout ),
        .d(gnd),
        .asdata(\m_x|data~6_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(!\m_x|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|data [2]),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|data[2] .is_wysiwyg = "true";
defparam \m_x|data[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X51_Y5_N3
cyclonev_lcell_comb \m_x|dta_timec[6]~feeder (
// Equation(s):
// \m_x|dta_timec[6]~feeder_combout  = ( \m_x|bit_d_1~q  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\m_x|bit_d_1~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|dta_timec[6]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|dta_timec[6]~feeder .extended_lut = "off";
defparam \m_x|dta_timec[6]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \m_x|dta_timec[6]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X51_Y5_N5
dffeas \m_x|dta_timec[6] (
        .clk(\m_x|ready_data~combout ),
        .d(\m_x|dta_timec[6]~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|dta_timec [6]),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|dta_timec[6] .is_wysiwyg = "true";
defparam \m_x|dta_timec[6] .power_up = "low";
// synopsys translate_on

// Location: FF_X50_Y5_N41
dffeas \m_x|dta_timec_p[6] (
        .clk(\m_x|ready_data_p~combout ),
        .d(gnd),
        .asdata(\m_x|dta_timec [6]),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|dta_timec_p [6]),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|dta_timec_p[6] .is_wysiwyg = "true";
defparam \m_x|dta_timec_p[6] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y5_N3
cyclonev_lcell_comb \m_x|data~2 (
// Equation(s):
// \m_x|data~2_combout  = ( \m_x|data [6] & ( (!\m_x|data~0_combout ) # (\m_x|dta_timec_p [6]) ) ) # ( !\m_x|data [6] & ( (\m_x|data~0_combout  & \m_x|dta_timec_p [6]) ) )

        .dataa(!\m_x|data~0_combout ),
        .datab(gnd),
        .datac(!\m_x|dta_timec_p [6]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\m_x|data [6]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|data~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|data~2 .extended_lut = "off";
defparam \m_x|data~2 .lut_mask = 64'h05050505AFAFAFAF;
defparam \m_x|data~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y5_N17
dffeas \m_x|data[6] (
        .clk(!\m_x|always3~0_combout ),
        .d(gnd),
        .asdata(\m_x|data~2_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(!\m_x|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|data [6]),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|data[6] .is_wysiwyg = "true";
defparam \m_x|data[6] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y5_N6
cyclonev_lcell_comb \m_x|always17~0 (
// Equation(s):
// \m_x|always17~0_combout  = ( \m_x|data [2] & ( \m_x|data [6] & ( !\m_x|data [7] $ (!\m_x|data [4] $ (!\m_x|data [5] $ (!\m_x|data [3]))) ) ) ) # ( !\m_x|data [2] & ( \m_x|data [6] & ( !\m_x|data [7] $ (!\m_x|data [4] $ (!\m_x|data [5] $ (\m_x|data [3]))) 
// ) ) ) # ( \m_x|data [2] & ( !\m_x|data [6] & ( !\m_x|data [7] $ (!\m_x|data [4] $ (!\m_x|data [5] $ (\m_x|data [3]))) ) ) ) # ( !\m_x|data [2] & ( !\m_x|data [6] & ( !\m_x|data [7] $ (!\m_x|data [4] $ (!\m_x|data [5] $ (!\m_x|data [3]))) ) ) )

        .dataa(!\m_x|data [7]),
        .datab(!\m_x|data [4]),
        .datac(!\m_x|data [5]),
        .datad(!\m_x|data [3]),
        .datae(!\m_x|data [2]),
        .dataf(!\m_x|data [6]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|always17~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|always17~0 .extended_lut = "off";
defparam \m_x|always17~0 .lut_mask = 64'h6996966996696996;
defparam \m_x|always17~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X53_Y5_N12
cyclonev_lcell_comb \m_x|rx_error_d~2 (
// Equation(s):
// \m_x|rx_error_d~2_combout  = ( \m_x|rx_error_d~0_combout  & ( \m_x|always17~0_combout  ) ) # ( !\m_x|rx_error_d~0_combout  & ( \m_x|always17~0_combout  & ( ((\m_x|rx_error_d~1_combout  & (!\m_x|always16~0_combout  $ (!\m_x|always17~1_combout )))) # 
// (\m_x|rx_error_d~q ) ) ) ) # ( \m_x|rx_error_d~0_combout  & ( !\m_x|always17~0_combout  ) ) # ( !\m_x|rx_error_d~0_combout  & ( !\m_x|always17~0_combout  & ( ((\m_x|rx_error_d~1_combout  & (!\m_x|always16~0_combout  $ (\m_x|always17~1_combout )))) # 
// (\m_x|rx_error_d~q ) ) ) )

        .dataa(!\m_x|rx_error_d~q ),
        .datab(!\m_x|always16~0_combout ),
        .datac(!\m_x|rx_error_d~1_combout ),
        .datad(!\m_x|always17~1_combout ),
        .datae(!\m_x|rx_error_d~0_combout ),
        .dataf(!\m_x|always17~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|rx_error_d~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|rx_error_d~2 .extended_lut = "off";
defparam \m_x|rx_error_d~2 .lut_mask = 64'h5D57FFFF575DFFFF;
defparam \m_x|rx_error_d~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X56_Y5_N39
cyclonev_lcell_comb \m_x|rx_error_d~feeder (
// Equation(s):
// \m_x|rx_error_d~feeder_combout  = ( \m_x|rx_error_d~2_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\m_x|rx_error_d~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|rx_error_d~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|rx_error_d~feeder .extended_lut = "off";
defparam \m_x|rx_error_d~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \m_x|rx_error_d~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X56_Y5_N41
dffeas \m_x|rx_error_d (
        .clk(\m_x|ready_data_p~combout ),
        .d(\m_x|rx_error_d~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|rx_error_d~q ),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|rx_error_d .is_wysiwyg = "true";
defparam \m_x|rx_error_d .power_up = "low";
// synopsys translate_on

// Location: FF_X55_Y5_N23
dffeas \m_x|parity_rec_c (
        .clk(\m_x|always1~0_combout ),
        .d(gnd),
        .asdata(\m_x|bit_c_3~q ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|parity_rec_c~q ),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|parity_rec_c .is_wysiwyg = "true";
defparam \m_x|parity_rec_c .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X53_Y5_N51
cyclonev_lcell_comb \m_x|always17~2 (
// Equation(s):
// \m_x|always17~2_combout  = ( \m_x|control_r [2] & ( !\m_x|parity_rec_c~q  ) ) # ( !\m_x|control_r [2] & ( \m_x|parity_rec_c~q  ) )

        .dataa(!\m_x|parity_rec_c~q ),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\m_x|control_r [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|always17~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|always17~2 .extended_lut = "off";
defparam \m_x|always17~2 .lut_mask = 64'h55555555AAAAAAAA;
defparam \m_x|always17~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X53_Y5_N48
cyclonev_lcell_comb \m_x|rx_error_c~0 (
// Equation(s):
// \m_x|rx_error_c~0_combout  = ( \m_x|control [1] & ( (\m_x|last_is_control~q  & (!\m_x|parity_rec_c~q  $ (!\m_x|control_r [2] $ (\m_x|control [0])))) ) ) # ( !\m_x|control [1] & ( (\m_x|last_is_control~q  & (!\m_x|parity_rec_c~q  $ (!\m_x|control_r [2] $ 
// (!\m_x|control [0])))) ) )

        .dataa(!\m_x|parity_rec_c~q ),
        .datab(!\m_x|control_r [2]),
        .datac(!\m_x|control [0]),
        .datad(!\m_x|last_is_control~q ),
        .datae(gnd),
        .dataf(!\m_x|control [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|rx_error_c~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|rx_error_c~0 .extended_lut = "off";
defparam \m_x|rx_error_c~0 .lut_mask = 64'h0096009600690069;
defparam \m_x|rx_error_c~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X53_Y5_N18
cyclonev_lcell_comb \m_x|rx_error_c~1 (
// Equation(s):
// \m_x|rx_error_c~1_combout  = ( \m_x|rx_error_d~1_combout  & ( \m_x|always17~1_combout  & ( ((!\m_x|always17~2_combout  $ (!\m_x|always17~0_combout )) # (\m_x|rx_error_c~0_combout )) # (\m_x|rx_error_c~q ) ) ) ) # ( !\m_x|rx_error_d~1_combout  & ( 
// \m_x|always17~1_combout  & ( (\m_x|rx_error_c~0_combout ) # (\m_x|rx_error_c~q ) ) ) ) # ( \m_x|rx_error_d~1_combout  & ( !\m_x|always17~1_combout  & ( ((!\m_x|always17~2_combout  $ (\m_x|always17~0_combout )) # (\m_x|rx_error_c~0_combout )) # 
// (\m_x|rx_error_c~q ) ) ) ) # ( !\m_x|rx_error_d~1_combout  & ( !\m_x|always17~1_combout  & ( (\m_x|rx_error_c~0_combout ) # (\m_x|rx_error_c~q ) ) ) )

        .dataa(!\m_x|rx_error_c~q ),
        .datab(!\m_x|always17~2_combout ),
        .datac(!\m_x|rx_error_c~0_combout ),
        .datad(!\m_x|always17~0_combout ),
        .datae(!\m_x|rx_error_d~1_combout ),
        .dataf(!\m_x|always17~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|rx_error_c~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|rx_error_c~1 .extended_lut = "off";
defparam \m_x|rx_error_c~1 .lut_mask = 64'h5F5FDF7F5F5F7FDF;
defparam \m_x|rx_error_c~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X55_Y5_N39
cyclonev_lcell_comb \m_x|rx_error_c~feeder (
// Equation(s):
// \m_x|rx_error_c~feeder_combout  = ( \m_x|rx_error_c~1_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\m_x|rx_error_c~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|rx_error_c~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|rx_error_c~feeder .extended_lut = "off";
defparam \m_x|rx_error_c~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \m_x|rx_error_c~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X55_Y5_N41
dffeas \m_x|rx_error_c (
        .clk(\m_x|always2~0_combout ),
        .d(\m_x|rx_error_c~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|rx_error_c~q ),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|rx_error_c .is_wysiwyg = "true";
defparam \m_x|rx_error_c .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X53_Y9_N0
cyclonev_lcell_comb \m_x|rx_error (
// Equation(s):
// \m_x|rx_error~combout  = ( \m_x|rx_error_c~q  ) # ( !\m_x|rx_error_c~q  & ( \m_x|rx_error_d~q  ) )

        .dataa(gnd),
        .datab(!\m_x|rx_error_d~q ),
        .datac(gnd),
        .datad(gnd),
        .datae(!\m_x|rx_error_c~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|rx_error~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|rx_error .extended_lut = "off";
defparam \m_x|rx_error .lut_mask = 64'h3333FFFF3333FFFF;
defparam \m_x|rx_error .shared_arith = "off";
// synopsys translate_on

// Location: FF_X53_Y9_N1
dffeas \m_x|info[5] (
        .clk(!\m_x|always3~0_combout ),
        .d(\m_x|rx_error~combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\m_x|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|info [5]),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|info[5] .is_wysiwyg = "true";
defparam \m_x|info[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y13_N51
cyclonev_lcell_comb \u0|data_info|read_mux_out[5] (
// Equation(s):
// \u0|data_info|read_mux_out [5] = ( \m_x|info [5] & ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( 
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datad(gnd),
        .datae(!\m_x|info [5]),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|data_info|read_mux_out [5]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|data_info|read_mux_out[5] .extended_lut = "off";
defparam \u0|data_info|read_mux_out[5] .lut_mask = 64'h0000F0F000000000;
defparam \u0|data_info|read_mux_out[5] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y13_N52
dffeas \u0|data_info|readdata[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|data_info|read_mux_out [5]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|data_info|readdata [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|data_info|readdata[5] .is_wysiwyg = "true";
defparam \u0|data_info|readdata[5] .power_up = "low";
// synopsys translate_on

// Location: FF_X31_Y13_N50
dffeas \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|data_info|readdata [5]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[5] .power_up = "low";
// synopsys translate_on

// Location: FF_X30_Y16_N47
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y16_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~5 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~5_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][5]~q  ) ) # ( 
// !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [5] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [5]),
        .datad(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][5]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~5 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y16_N11
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~5_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][5]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y16_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~71 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~71_combout  = ( \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [5] & ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][5]~q  & ( 
// \u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout  ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [5] & ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][5]~q  & ( 
// (\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout  & !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout ) ) ) ) # ( \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [5] & ( 
// !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][5]~q  & ( (\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout  & \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout ) ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [5]),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][5]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~71_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~71 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~71 .lut_mask = 64'h0000030330303333;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~71 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y15_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~73 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~73_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout  & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~71_combout  & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~70_combout  & 
// ((!\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~69_combout ) # (\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ))) ) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout  & ( 
// !\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~71_combout  & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~70_combout  & (!\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~72_combout  & ((!\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~69_combout ) # 
// (\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout )))) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ),
        .datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~69_combout ),
        .datac(!\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~70_combout ),
        .datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~72_combout ),
        .datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ),
        .dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~71_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~73_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~73 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~73 .lut_mask = 64'hD000D0D000000000;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~73 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X31_Y15_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~74 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~74_combout  = ( \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~73_combout  & ( (((\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout  & \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~67_combout )) # 
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~68_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~66_combout ) ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~73_combout  )

        .dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~66_combout ),
        .datab(!\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout ),
        .datac(!\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~68_combout ),
        .datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~67_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~73_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~74_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~74 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~74 .lut_mask = 64'hFFFFFFFF5F7F5F7F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~74 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y31_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal2~0 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal2~0_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [15] & ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [13] & !\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [13]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [15]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router_001|Equal2~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal2~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal2~0 .lut_mask = 64'h000000000F000F00;
defparam \u0|mm_interconnect_0|router_001|Equal2~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y31_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal10~0 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal10~0_combout  = ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & ( (\u0|mm_interconnect_0|router_001|Equal1~0_combout  & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & 
// (\u0|mm_interconnect_0|router_001|Equal2~0_combout  & \u0|mm_interconnect_0|router_001|Equal1~1_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),
        .datac(!\u0|mm_interconnect_0|router_001|Equal2~0_combout ),
        .datad(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router_001|Equal10~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal10~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal10~0 .lut_mask = 64'h0000000000010000;
defparam \u0|mm_interconnect_0|router_001|Equal10~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y31_N32
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[20] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|router_001|Equal10~0_combout ),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [20]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[20] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[20] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y31_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_020|last_cycle~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q  & ( (\u0|mm_interconnect_0|router_001|Equal10~0_combout  & 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [20] & \u0|hps_0|fpga_interfaces|h2f_ARVALID [0])) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q  & ( 
// (\u0|mm_interconnect_0|router_001|Equal10~0_combout  & \u0|hps_0|fpga_interfaces|h2f_ARVALID [0]) ) )

        .dataa(!\u0|mm_interconnect_0|router_001|Equal10~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [20]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_020|last_cycle~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_020|last_cycle~0 .lut_mask = 64'h0055005500050005;
defparam \u0|mm_interconnect_0|cmd_mux_020|last_cycle~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y33_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_020|packet_in_progress~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_020|packet_in_progress~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_020|packet_in_progress~q  & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  ) 
// ) # ( !\u0|mm_interconnect_0|cmd_mux_020|packet_in_progress~q  & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  & ( (\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & 
// \u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout ) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_020|packet_in_progress~q  & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  & 
// ( (!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]) # (!\u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout ),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_020|packet_in_progress~q ),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_020|packet_in_progress~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_020|packet_in_progress~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_020|packet_in_progress~0 .lut_mask = 64'h0000EEEE1111FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_020|packet_in_progress~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y33_N49
dffeas \u0|mm_interconnect_0|cmd_mux_020|packet_in_progress (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_020|packet_in_progress~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_020|packet_in_progress~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_020|packet_in_progress .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_020|packet_in_progress .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y33_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_020|update_grant~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_020|update_grant~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout  & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  & ( 
// (!\u0|mm_interconnect_0|cmd_mux_020|packet_in_progress~q  & !\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout  & ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  & ( !\u0|mm_interconnect_0|cmd_mux_020|packet_in_progress~q  ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout  & 
// ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  & ( (!\u0|mm_interconnect_0|cmd_mux_020|packet_in_progress~q ) # (\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]) ) ) ) # ( 
// !\u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout  & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  & ( !\u0|mm_interconnect_0|cmd_mux_020|packet_in_progress~q  ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_020|packet_in_progress~q ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout ),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_020|update_grant~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_020|update_grant~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_020|update_grant~0 .lut_mask = 64'hCCCCCFCFCCCCC0C0;
defparam \u0|mm_interconnect_0|cmd_mux_020|update_grant~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y33_N2
dffeas \u0|mm_interconnect_0|cmd_mux_020|saved_grant[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|cmd_mux_020|update_grant~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_020|saved_grant[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_020|saved_grant[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X23_Y35_N58
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y35_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~0_combout  = ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & ((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]) # 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]))) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~0 .lut_mask = 64'h050F050F00000000;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y35_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg~0_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override~q  & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~0_combout  & 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter [0] & !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout )) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~0_combout ),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter [0]),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg~0 .lut_mask = 64'h0000000003000300;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y35_N29
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y35_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[0]~0_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|read~0_combout  & ( ((\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0] & 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|read~0_combout  & ( 
// ((\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [1])) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0]) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|read~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h50FF50FF0F5F0F5F;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y35_N20
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y14_N15
cyclonev_lcell_comb \u0|counter_tx_fifo|read_mux_out[4]~4 (
// Equation(s):
// \u0|counter_tx_fifo|read_mux_out[4]~4_combout  = ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( \A_SPW_TOP|tx_data|counter [4] ) ) )

        .dataa(!\A_SPW_TOP|tx_data|counter [4]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|counter_tx_fifo|read_mux_out[4]~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|counter_tx_fifo|read_mux_out[4]~4 .extended_lut = "off";
defparam \u0|counter_tx_fifo|read_mux_out[4]~4 .lut_mask = 64'h5555000000000000;
defparam \u0|counter_tx_fifo|read_mux_out[4]~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y14_N16
dffeas \u0|counter_tx_fifo|readdata[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|counter_tx_fifo|read_mux_out[4]~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|counter_tx_fifo|readdata [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|counter_tx_fifo|readdata[4] .is_wysiwyg = "true";
defparam \u0|counter_tx_fifo|readdata[4] .power_up = "low";
// synopsys translate_on

// Location: FF_X27_Y15_N8
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|counter_tx_fifo|readdata [4]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre[4] .power_up = "low";
// synopsys translate_on

// Location: FF_X27_Y15_N29
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~4_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y15_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~4 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~4_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [4] & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [1]) # 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][4]~q ) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [4] & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][4]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][4]~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~4 .lut_mask = 64'h03030303CFCFCFCF;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y15_N5
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~4_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y15_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~64 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~64_combout  = ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout  & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0] & ( 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0] & (\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [4])) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0] & 
// ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][4]~q ))) ) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout  & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0] & ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][4]~q  ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0]),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [4]),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][4]~q ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~64_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~64 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~64 .lut_mask = 64'h0F0F000027270000;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~64 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y15_N33
cyclonev_lcell_comb \u0|write_data_fifo_tx|readdata[4] (
// Equation(s):
// \u0|write_data_fifo_tx|readdata [4] = ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & \u0|write_data_fifo_tx|data_out [4]) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datad(!\u0|write_data_fifo_tx|data_out [4]),
        .datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|write_data_fifo_tx|readdata [4]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|write_data_fifo_tx|readdata[4] .extended_lut = "off";
defparam \u0|write_data_fifo_tx|readdata[4] .lut_mask = 64'h00F0000000F00000;
defparam \u0|write_data_fifo_tx|readdata[4] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y15_N35
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|write_data_fifo_tx|readdata [4]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y36_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_019|src_payload~12 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_019|src_payload~12_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout  & ( \u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_019|src_payload~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~12 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~12 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y36_N29
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_019|src_payload~12_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y36_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3] = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout  & ( 
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]))) # 
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|cmd_mux_019|src_payload~12_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_019|src_payload~12_combout ),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .lut_mask = 64'h00000000E4E4E4E4;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y36_N44
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y36_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_019|src_payload~14 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_019|src_payload~14_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] & ( \u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_019|src_payload~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~14 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~14 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y36_N17
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_019|src_payload~14_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y36_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_019|src_payload~16 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_019|src_payload~16_combout  = (\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1])

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_019|src_payload~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~16 .lut_mask = 64'h000F000F000F000F;
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~16 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y36_N14
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_019|src_payload~16_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y36_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_019|src_payload~15 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_019|src_payload~15_combout  = (\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & \u0|mm_interconnect_0|cmd_mux_019|saved_grant [1])

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_019|src_payload~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~15 .lut_mask = 64'h1111111111111111;
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~15 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y36_N2
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_019|src_payload~15_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y36_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  = ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// \u0|mm_interconnect_0|cmd_mux_019|src_payload~15_combout  & ( (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & 
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]) ) ) ) # ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// !\u0|mm_interconnect_0|cmd_mux_019|src_payload~15_combout  & ( \u0|mm_interconnect_0|cmd_mux_019|src_payload~16_combout  ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// !\u0|mm_interconnect_0|cmd_mux_019|src_payload~15_combout  & ( (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & 
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]) ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_019|src_payload~16_combout ),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_019|src_payload~15_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .lut_mask = 64'h3030555530300000;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y36_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  & ( 
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) # 
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((\u0|mm_interconnect_0|cmd_mux_019|src_payload~14_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_019|src_payload~14_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .lut_mask = 64'h0000000027272727;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y36_N40
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .power_up = "low";
// synopsys translate_on

// Location: FF_X30_Y36_N14
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y36_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_019|src_payload~13 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_019|src_payload~13_combout  = ( \u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout  ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout ),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_019|src_payload~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~13 .lut_mask = 64'h00000000AAAAAAAA;
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~13 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y36_N59
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_019|src_payload~13_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y36_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2] = ( \u0|mm_interconnect_0|cmd_mux_019|src_payload~13_combout  & ( 
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] & 
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_019|src_payload~13_combout  & ( 
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout  & ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]) # 
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_019|src_payload~13_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .lut_mask = 64'h00F500F500A000A0;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y36_N46
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y36_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  & ( 
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]))) # 
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|cmd_mux_019|src_payload~14_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_019|src_payload~14_combout ),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .lut_mask = 64'h00000000CACACACA;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y36_N55
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y36_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_019|src_payload~17 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_019|src_payload~17_combout  = (\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~1_combout )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~1_combout ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_019|src_payload~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~17 .lut_mask = 64'h0033003300330033;
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~17 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y36_N44
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_019|src_payload~17_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y36_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1] = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout  & ( 
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1])) # 
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|cmd_mux_019|src_payload~17_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_019|src_payload~17_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .lut_mask = 64'h00000000F5A0F5A0;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y36_N23
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y36_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & (\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [1] & !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]))) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [1]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .lut_mask = 64'h0000000002000200;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y36_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & ( 
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & ( (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (!\u0|mm_interconnect_0|cmd_mux_019|src_payload~15_combout  & !\u0|mm_interconnect_0|cmd_mux_019|src_payload~16_combout )) ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & ( 
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & ( (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (!\u0|mm_interconnect_0|cmd_mux_019|src_payload~15_combout  & !\u0|mm_interconnect_0|cmd_mux_019|src_payload~16_combout )) ) ) ) # ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & ( 
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & ( (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (!\u0|mm_interconnect_0|cmd_mux_019|src_payload~15_combout  & !\u0|mm_interconnect_0|cmd_mux_019|src_payload~16_combout )) ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & ( 
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # 
// ((!\u0|mm_interconnect_0|cmd_mux_019|src_payload~15_combout  & !\u0|mm_interconnect_0|cmd_mux_019|src_payload~16_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_019|src_payload~15_combout ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_019|src_payload~16_combout ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .lut_mask = 64'hEAEA404040404040;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y36_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  & ( 
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) # 
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((\u0|mm_interconnect_0|cmd_mux_019|src_payload~14_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_019|src_payload~14_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .lut_mask = 64'h0000000027272727;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y36_N37
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y36_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  = ( 
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ((\u0|mm_interconnect_0|cmd_mux_019|src_payload~14_combout ))) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_019|src_payload~14_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .lut_mask = 64'hFFFFFFFF0A5F0A5F;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y36_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout  = ( 
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .lut_mask = 64'hFFFFFFFF00000000;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y36_N20
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y36_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout  = SUM(( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) + ( 
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14  = CARRY(( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) + ( 
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
        .cout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y36_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_019|src_payload~18 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_019|src_payload~18_combout  = (\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~2_combout )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~2_combout ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_019|src_payload~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~18 .lut_mask = 64'h3300330033003300;
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~18 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y36_N26
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_019|src_payload~18_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y36_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0] = ( \u0|mm_interconnect_0|cmd_mux_019|src_payload~18_combout  & ( 
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  & 
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0])) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_019|src_payload~18_combout  & ( 
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  & ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]) # 
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_019|src_payload~18_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .lut_mask = 64'h0F050F050A000A00;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y36_N22
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y36_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  = ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// ((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout  & (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]))) # 
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]) ) ) # ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// (((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  & (\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [0])))) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
        .datae(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [0]),
        .datag(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .extended_lut = "on";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .lut_mask = 64'h37370000373700F0;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y36_N37
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y36_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout  = SUM(( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + ( 
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14  ))
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10  = CARRY(( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + ( 
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14  ))

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
        .cout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .lut_mask = 64'h0000AAAA000000FF;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y36_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout  & ( 
// ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]) # 
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1])))) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ) ) ) # 
// ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout  & ( ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1])) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .lut_mask = 64'h0AFF0AFF2AFF2AFF;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y36_N19
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y36_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout  = SUM(( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + ( 
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10  ))
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6  = CARRY(( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + ( 
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10  ))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
        .cout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .lut_mask = 64'h0000F0F000003333;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y36_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( 
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout  & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # 
// ((\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [2])) ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( 
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout  & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2])))) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [2]))) ) ) ) # ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( 
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout  & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # 
// ((\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [2])) ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( 
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout  & ( (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [2])) ) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [2]),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .datae(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .lut_mask = 64'h0101ABAB01ABABAB;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y36_N32
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y36_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout  = SUM(( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3] ) + ( 
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3] ) + ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6  ))

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .lut_mask = 64'h0000AAAA00000F0F;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y36_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [3] & ( 
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout  & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3])))) # 
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1])) ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [3] & ( 
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout  & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]))) ) ) ) # ( 
// \u0|hps_0|fpga_interfaces|h2f_ARADDR [3] & ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout  & ( 
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]))) # 
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1])) ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [3] & ( 
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout  & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]) ) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [3]),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .lut_mask = 64'h00AA11BB0AAA1BBB;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y36_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3]~feeder_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y36_N53
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .power_up = "low";
// synopsys translate_on

// Location: FF_X30_Y36_N17
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y14_N3
cyclonev_lcell_comb \u0|fsm_info|read_mux_out[4]~4 (
// Equation(s):
// \u0|fsm_info|read_mux_out[4]~4_combout  = ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & ( (\A_SPW_TOP|SPW|FSM|state_fsm.run~q  & 
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|state_fsm.run~q ),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|fsm_info|read_mux_out[4]~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|fsm_info|read_mux_out[4]~4 .extended_lut = "off";
defparam \u0|fsm_info|read_mux_out[4]~4 .lut_mask = 64'h5500550000000000;
defparam \u0|fsm_info|read_mux_out[4]~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y14_N5
dffeas \u0|fsm_info|readdata[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|fsm_info|read_mux_out[4]~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|fsm_info|readdata [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|fsm_info|readdata[4] .is_wysiwyg = "true";
defparam \u0|fsm_info|readdata[4] .power_up = "low";
// synopsys translate_on

// Location: FF_X31_Y14_N29
dffeas \u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|fsm_info|readdata [4]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre[4] .power_up = "low";
// synopsys translate_on

// Location: FF_X25_Y15_N1
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~4_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][4] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y15_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~4 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~4_combout  = (!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [1] & (\u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre [4])) # 
// (\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [1] & ((\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][4]~q )))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre [4]),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][4]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~4 .lut_mask = 64'h0C3F0C3F0C3F0C3F;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~4 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y15_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|always0~0_combout  = (!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0]) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|read~0_combout )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|read~0_combout ),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|always0~0 .lut_mask = 64'hF3F3F3F3F3F3F3F3;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y15_N11
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~4_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][4] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y15_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~63 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~63_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0] & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout  & 
// ((!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0] & (\u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre [4])) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0] & 
// ((\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][4]~q ))))) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0] & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout  & 
// \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][4]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre [4]),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0]),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout ),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][4]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~63_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~63 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~63 .lut_mask = 64'h00F000F040704070;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~63 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X31_Y14_N48
cyclonev_lcell_comb \u0|counter_rx_fifo|read_mux_out[4]~4 (
// Equation(s):
// \u0|counter_rx_fifo|read_mux_out[4]~4_combout  = ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & \A_SPW_TOP|rx_data|counter [4]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datac(!\A_SPW_TOP|rx_data|counter [4]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|counter_rx_fifo|read_mux_out[4]~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|counter_rx_fifo|read_mux_out[4]~4 .extended_lut = "off";
defparam \u0|counter_rx_fifo|read_mux_out[4]~4 .lut_mask = 64'h0C0C0C0C00000000;
defparam \u0|counter_rx_fifo|read_mux_out[4]~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y14_N49
dffeas \u0|counter_rx_fifo|readdata[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|counter_rx_fifo|read_mux_out[4]~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|counter_rx_fifo|readdata [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|counter_rx_fifo|readdata[4] .is_wysiwyg = "true";
defparam \u0|counter_rx_fifo|readdata[4] .power_up = "low";
// synopsys translate_on

// Location: FF_X31_Y15_N56
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|counter_rx_fifo|readdata [4]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre[4] .power_up = "low";
// synopsys translate_on

// Location: FF_X31_Y15_N50
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y15_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~4 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~4_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][4]~q  ) ) # ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [4] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [4]),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][4]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~4 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y15_N41
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~4_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y15_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~65 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~65_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][4]~q  & 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout  & 
// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0] & ((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][4]~q ))) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0] & 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [4])))) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [4]),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][4]~q ),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0]),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~65_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~65 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~65 .lut_mask = 64'h3500350033003300;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~65 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y15_N47
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y15_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~4 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~4_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [4] & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1]) # 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][4]~q ) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [4] & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][4]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][4]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~4 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y15_N38
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~4_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y15_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~218 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~218_combout  = ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout  & ( ((((\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout  & 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][4]~q )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~65_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~63_combout )) # 
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~64_combout ) ) ) # ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout  & ( ((((\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout  & 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [4])) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~65_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~63_combout )) # 
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~64_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ),
        .datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~64_combout ),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [4]),
        .datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~63_combout ),
        .datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout ),
        .dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~65_combout ),
        .datag(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][4]~q ),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~218_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~218 .extended_lut = "on";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~218 .lut_mask = 64'h37FF37FFFFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~218 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X51_Y9_N15
cyclonev_lcell_comb \m_x|always0~0 (
// Equation(s):
// \m_x|always0~0_combout  = ( \A_SPW_TOP|SPW|TX|tx_dout_e~q  ) # ( !\A_SPW_TOP|SPW|TX|tx_dout_e~q  & ( \A_SPW_TOP|SPW|TX|tx_sout_e~q  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|TX|tx_sout_e~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|tx_dout_e~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|always0~0 .extended_lut = "off";
defparam \m_x|always0~0 .lut_mask = 64'h0F0F0F0FFFFFFFFF;
defparam \m_x|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X51_Y9_N16
dffeas \m_x|info[4] (
        .clk(!\m_x|always3~0_combout ),
        .d(\m_x|always0~0_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\m_x|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|info [4]),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|info[4] .is_wysiwyg = "true";
defparam \m_x|info[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y13_N33
cyclonev_lcell_comb \u0|data_info|read_mux_out[4] (
// Equation(s):
// \u0|data_info|read_mux_out [4] = ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( (\m_x|info [4] & 
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]) ) )

        .dataa(!\m_x|info [4]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|data_info|read_mux_out [4]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|data_info|read_mux_out[4] .extended_lut = "off";
defparam \u0|data_info|read_mux_out[4] .lut_mask = 64'h5050505000000000;
defparam \u0|data_info|read_mux_out[4] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y13_N34
dffeas \u0|data_info|readdata[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|data_info|read_mux_out [4]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|data_info|readdata [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|data_info|readdata[4] .is_wysiwyg = "true";
defparam \u0|data_info|readdata[4] .power_up = "low";
// synopsys translate_on

// Location: FF_X28_Y16_N2
dffeas \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|data_info|readdata [4]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[4] .power_up = "low";
// synopsys translate_on

// Location: FF_X28_Y16_N56
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~4_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y18_N36
cyclonev_lcell_comb \u0|timecode_tx_data|readdata[4] (
// Equation(s):
// \u0|timecode_tx_data|readdata [4] = ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & \u0|timecode_tx_data|data_out [4]) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datab(gnd),
        .datac(!\u0|timecode_tx_data|data_out [4]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|timecode_tx_data|readdata [4]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|timecode_tx_data|readdata[4] .extended_lut = "off";
defparam \u0|timecode_tx_data|readdata[4] .lut_mask = 64'h0A0A0A0A00000000;
defparam \u0|timecode_tx_data|readdata[4] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y18_N38
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|timecode_tx_data|readdata [4]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y16_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~4 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~4_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [4] & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1]) # 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][4]~q ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [4] & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][4]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][4]~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~4 .lut_mask = 64'h03030303CFCFCFCF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y16_N35
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~4_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y16_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~58 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~58_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [4] & ( (\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout  & 
// (((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0] & \u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][4]~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [4] & ( (\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout  & (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][4]~q  & 
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0]) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0])))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0]),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0]),
        .datac(!\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][4]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~58_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~58 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~58 .lut_mask = 64'h000D000D020F020F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~58 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y17_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux|src1_valid (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux|src1_valid~combout  = ( !\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout  & ( !\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_demux|src1_valid~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux|src1_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux|src1_valid .lut_mask = 64'hFF00FF0000000000;
defparam \u0|mm_interconnect_0|rsp_demux|src1_valid .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y2_N39
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|timecode~5 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|timecode~5_combout  = ( \A_SPW_TOP|SPW|RX|timecode~0_combout  & ( \A_SPW_TOP|SPW|RX|dta_timec_p [4] ) ) # ( !\A_SPW_TOP|SPW|RX|timecode~0_combout  & ( \A_SPW_TOP|SPW|RX|dta_timec_p [4] & ( \A_SPW_TOP|SPW|RX|timecode [4] ) ) ) # ( 
// !\A_SPW_TOP|SPW|RX|timecode~0_combout  & ( !\A_SPW_TOP|SPW|RX|dta_timec_p [4] & ( \A_SPW_TOP|SPW|RX|timecode [4] ) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|timecode [4]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\A_SPW_TOP|SPW|RX|timecode~0_combout ),
        .dataf(!\A_SPW_TOP|SPW|RX|dta_timec_p [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|timecode~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|timecode~5 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|timecode~5 .lut_mask = 64'h555500005555FFFF;
defparam \A_SPW_TOP|SPW|RX|timecode~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y2_N59
dffeas \A_SPW_TOP|SPW|RX|timecode[4] (
        .clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|RX|timecode~5_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(!\A_SPW_TOP|SPW|RX|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|timecode [4]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|timecode[4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|timecode[4] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y14_N42
cyclonev_lcell_comb \u0|timecode_rx|read_mux_out[4] (
// Equation(s):
// \u0|timecode_rx|read_mux_out [4] = ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( \A_SPW_TOP|SPW|RX|timecode [4] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|RX|timecode [4]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|timecode_rx|read_mux_out [4]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|timecode_rx|read_mux_out[4] .extended_lut = "off";
defparam \u0|timecode_rx|read_mux_out[4] .lut_mask = 64'h0F0F000000000000;
defparam \u0|timecode_rx|read_mux_out[4] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y14_N44
dffeas \u0|timecode_rx|readdata[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|timecode_rx|read_mux_out [4]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|timecode_rx|readdata [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|timecode_rx|readdata[4] .is_wysiwyg = "true";
defparam \u0|timecode_rx|readdata[4] .power_up = "low";
// synopsys translate_on

// Location: FF_X25_Y16_N56
dffeas \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|timecode_rx|readdata [4]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[4] .power_up = "low";
// synopsys translate_on

// Location: FF_X25_Y16_N59
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~4_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][4] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y16_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~4 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~4_combout  = (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1] & ((\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [4]))) # 
// (\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1] & (\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][4]~q ))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][4]~q ),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [4]),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~4 .lut_mask = 64'h0F330F330F330F33;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y16_N49
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][4] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y16_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~60 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~60_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0] & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0] & 
// (\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [4])) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0] & ((\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][4]~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][4]~q  ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [4]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0]),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][4]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~60_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~60 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~60 .lut_mask = 64'h00FF00FF505F505F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~60 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y26_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout  & ( 
// ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~1_combout  & \u0|mm_interconnect_0|cmd_mux|saved_grant [0])) # (\u0|mm_interconnect_0|cmd_mux|saved_grant [1]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout  & 
// ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~1_combout  & \u0|mm_interconnect_0|cmd_mux|saved_grant [0]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~1_combout ),
        .datac(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
        .datad(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 .lut_mask = 64'h003300330F3F0F3F;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y26_N35
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y26_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~4_combout  & ( 
// (\u0|mm_interconnect_0|cmd_mux|saved_grant [1] & !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~4_combout  & ( ((\u0|mm_interconnect_0|cmd_mux|saved_grant [1] & 
// !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0])) # (\u0|mm_interconnect_0|cmd_mux|saved_grant [0]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),
        .datad(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~4_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 .lut_mask = 64'h30FF30FF30303030;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y26_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout  = ( 
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout  & ( 
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] $ (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])) 
// # (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) # ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout  & ( 
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] $ 
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 .lut_mask = 64'h50A050A05FAF5FAF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y26_N44
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y26_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout  = ( \u0|mm_interconnect_0|cmd_mux|saved_grant [1] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout  
// ) ) # ( !\u0|mm_interconnect_0|cmd_mux|saved_grant [1] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout  & ( (\u0|mm_interconnect_0|cmd_mux|saved_grant [0] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3_combout ) 
// ) ) ) # ( \u0|mm_interconnect_0|cmd_mux|saved_grant [1] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout  & ( (\u0|mm_interconnect_0|cmd_mux|saved_grant [0] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3_combout 
// ) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux|saved_grant [1] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout  & ( (\u0|mm_interconnect_0|cmd_mux|saved_grant [0] & 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3_combout ) ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3_combout ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5 .lut_mask = 64'h030303030303FFFF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y26_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout  = ( 
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( 
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout  & ( 
// ((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])) 
// # (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg 
// [3] & ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout  & ( 
// ((\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])) # 
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) ) # ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] 
// & ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout  & ( 
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # 
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) ) ) # ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout  & ( 
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])) ) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datae(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6 .lut_mask = 64'h0A00A0AA5F55F5FF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y26_N2
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y26_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] & ( 
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3])) ) ) # ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] & ( (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) 
// # ((\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]) # 
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .lut_mask = 64'hAFFFAFFF50005000;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y26_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout  & ( 
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  & ( (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout  & \u0|mm_interconnect_0|cmd_mux|saved_grant [0])) # (\u0|mm_interconnect_0|cmd_mux|saved_grant [1]))) ) ) ) # ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout  & ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  & ( 
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout  & \u0|mm_interconnect_0|cmd_mux|saved_grant [0])) ) ) ) # 
// ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout  & ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  & ( 
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # (((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout  & \u0|mm_interconnect_0|cmd_mux|saved_grant [0])) # 
// (\u0|mm_interconnect_0|cmd_mux|saved_grant [1])) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout  & ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout  & ( 
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout  & \u0|mm_interconnect_0|cmd_mux|saved_grant [0])) ) ) 
// )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout ),
        .datac(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
        .datad(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
        .datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .lut_mask = 64'hABABABFF01010155;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y26_N20
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y26_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  = ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] & ( 
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3])) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .lut_mask = 64'h5000500000000000;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y26_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  
// & ( (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg 
// [5]))) # (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout )) ) ) # ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  & ( (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ((\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) # (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 .lut_mask = 64'h05AF05AFAF05AF05;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y24_N41
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux|src_payload [0]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y19_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  = ( !\u0|mm_interconnect_0|cmd_mux|saved_grant [1] & ( (((!\u0|mm_interconnect_0|cmd_mux|saved_grant [0] & 
// ((\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ))))) ) ) # ( \u0|mm_interconnect_0|cmd_mux|saved_grant [1] & ( 
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ) # (((\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q  & 
// ((\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) # 
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) # (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) 
// ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datae(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datag(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .extended_lut = "on";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .lut_mask = 64'h0000F1F5F0F0FFFF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y17_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~2_combout  = ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & ( 
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~2 .lut_mask = 64'hC000C00000000000;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y17_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~3 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~3_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~2_combout  & ( (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ) 
// # ((\u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~0_combout  & (!\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [0] $ (!\u0|mm_interconnect_0|led_pio_test_s1_agent|local_write~0_combout )))) ) ) # ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~2_combout  & ( (\u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~0_combout  & (!\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [0] $ 
// (!\u0|mm_interconnect_0|led_pio_test_s1_agent|local_write~0_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [0]),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent|local_write~0_combout ),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~3 .lut_mask = 64'h003C003CAABEAABE;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y17_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~3_combout  & ( 
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ((!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & 
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) # (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & 
// ((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ))))) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~3_combout  & ( 
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h5500550051405140;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y19_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  = ( \u0|mm_interconnect_0|cmd_mux|src_valid~0_combout  & ( \u0|mm_interconnect_0|cmd_demux|src0_valid~3_combout  & ( 
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout  & ((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) # 
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ))) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux|src_valid~0_combout  & ( \u0|mm_interconnect_0|cmd_demux|src0_valid~3_combout  & ( 
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout  & ((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) # 
// ((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) # (!\u0|mm_interconnect_0|cmd_mux|saved_grant [0])))) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux|src_valid~0_combout  & ( 
// !\u0|mm_interconnect_0|cmd_demux|src0_valid~3_combout  & ( (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout  & 
// ((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) # (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ))) ) ) ) # 
// ( !\u0|mm_interconnect_0|cmd_mux|src_valid~0_combout  & ( !\u0|mm_interconnect_0|cmd_demux|src0_valid~3_combout  & ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout  ) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datad(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
        .datae(!\u0|mm_interconnect_0|cmd_mux|src_valid~0_combout ),
        .dataf(!\u0|mm_interconnect_0|cmd_demux|src0_valid~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .lut_mask = 64'hCCCCC8C8CCC8C8C8;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y26_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~0_combout  & ( 
// ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout  & \u0|mm_interconnect_0|cmd_mux|saved_grant [1])) # (\u0|mm_interconnect_0|cmd_mux|saved_grant [0]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~0_combout  & 
// ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout  & \u0|mm_interconnect_0|cmd_mux|saved_grant [1]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),
        .datac(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
        .datad(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .lut_mask = 64'h003300330F3F0F3F;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y26_N32
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y26_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  
// & ( (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] $ 
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6])))) # (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout )) ) ) # ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout  & ( (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ((\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]))) # (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 .lut_mask = 64'h11BB11BBB11BB11B;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y26_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  & ( 
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout  ) ) # ( 
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  & ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout  ) ) # ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  & ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout  & ( 
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout  & 
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout  & 
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout  & 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout ),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),
        .datae(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .lut_mask = 64'h2000FFFF0000FFFF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y26_N56
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y24_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|src_data[81] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|src_data [81] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~0_combout  & ( (\u0|mm_interconnect_0|cmd_mux|saved_grant [1] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~0_combout  & ( ((\u0|mm_interconnect_0|cmd_mux|saved_grant [1] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout )) # (\u0|mm_interconnect_0|cmd_mux|saved_grant [0]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux|src_data [81]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|src_data[81] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|src_data[81] .lut_mask = 64'h3F0F3F0F33003300;
defparam \u0|mm_interconnect_0|cmd_mux|src_data[81] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y24_N14
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux|src_data [81]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y24_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2] = ( \u0|mm_interconnect_0|cmd_mux|src_data [81] & ( 
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] & 
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux|src_data [81] & ( 
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout  & ((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]) # 
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux|src_data [81]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .lut_mask = 64'h00F500F500A000A0;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y24_N29
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y24_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout  = ( \u0|mm_interconnect_0|cmd_mux|saved_grant [1] & ( ((\u0|mm_interconnect_0|cmd_mux|saved_grant [0] & 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout )) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [2]) ) ) # ( !\u0|mm_interconnect_0|cmd_mux|saved_grant [1] & ( (\u0|mm_interconnect_0|cmd_mux|saved_grant [0] & 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout ) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [2]),
        .datab(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 .lut_mask = 64'h0033003355775577;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y24_N26
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y24_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|src_data[86] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|src_data [86] = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] & ( ((\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0] & \u0|mm_interconnect_0|cmd_mux|saved_grant [0])) # (\u0|mm_interconnect_0|cmd_mux|saved_grant [1]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] & ( (\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0] & \u0|mm_interconnect_0|cmd_mux|saved_grant [0]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0]),
        .datad(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux|src_data [86]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|src_data[86] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|src_data[86] .lut_mask = 64'h000F000F333F333F;
defparam \u0|mm_interconnect_0|cmd_mux|src_data[86] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y24_N23
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux|src_data [87]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X28_Y24_N53
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux|src_data [88]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y24_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & ( 
// (\u0|mm_interconnect_0|cmd_mux|src_data [87] & (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & !\u0|mm_interconnect_0|cmd_mux|src_data [88])) ) ) # ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & ( (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1])) # (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((\u0|mm_interconnect_0|cmd_mux|src_data [87] & !\u0|mm_interconnect_0|cmd_mux|src_data [88])))) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .datab(!\u0|mm_interconnect_0|cmd_mux|src_data [87]),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(!\u0|mm_interconnect_0|cmd_mux|src_data [88]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .lut_mask = 64'h5350535003000300;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y24_N38
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux|src_data [86]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y24_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  & ( 
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] & ( (!\u0|mm_interconnect_0|cmd_mux|src_data [86] & 
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) ) # ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  & ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] & ( (!\u0|mm_interconnect_0|cmd_mux|src_data [86]) # 
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux|src_data [86]),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .lut_mask = 64'h0000FCFC00000C0C;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y24_N25
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y24_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & ( 
// (!\u0|mm_interconnect_0|cmd_mux|src_data [87] & (!\u0|mm_interconnect_0|cmd_mux|src_data [88] & \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) # ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & ( (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1])) # (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((!\u0|mm_interconnect_0|cmd_mux|src_data [87] & !\u0|mm_interconnect_0|cmd_mux|src_data [88])))) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .datab(!\u0|mm_interconnect_0|cmd_mux|src_data [87]),
        .datac(!\u0|mm_interconnect_0|cmd_mux|src_data [88]),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .lut_mask = 64'hAAC0AAC000C000C0;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y24_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout  = ( \u0|mm_interconnect_0|cmd_mux|src_data [86] & ( 
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  & ((\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]) # 
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) ) # ( !\u0|mm_interconnect_0|cmd_mux|src_data [86] & ( 
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] & 
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux|src_data [86]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .lut_mask = 64'h000A000A005F005F;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y24_N44
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y24_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|src_data[80] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|src_data [80] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~0_combout  & ( (\u0|mm_interconnect_0|cmd_mux|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~1_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~0_combout  & ( ((\u0|mm_interconnect_0|cmd_mux|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~1_combout )) # (\u0|mm_interconnect_0|cmd_mux|saved_grant [0]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~1_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux|src_data [80]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|src_data[80] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|src_data[80] .lut_mask = 64'h03FF03FF03030303;
defparam \u0|mm_interconnect_0|cmd_mux|src_data[80] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y24_N35
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux|src_data [80]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y24_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  = ( \u0|mm_interconnect_0|cmd_mux|src_data [86] & ( 
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  & ( (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] & 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux|src_data [86] & ( 
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  & ( (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]) # 
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux|src_data [86]),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .lut_mask = 64'h00000000AFAFA0A0;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y24_N43
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y24_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|src_data[79] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|src_data [79] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~2_combout  & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout  & \u0|mm_interconnect_0|cmd_mux|saved_grant [0]) ) ) # ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~2_combout  & ( ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout  & \u0|mm_interconnect_0|cmd_mux|saved_grant [0])) # (\u0|mm_interconnect_0|cmd_mux|saved_grant [1]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux|src_data [79]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|src_data[79] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|src_data[79] .lut_mask = 64'h33F333F300F000F0;
defparam \u0|mm_interconnect_0|cmd_mux|src_data[79] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y24_N32
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux|src_data [79]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y24_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout  = SUM(( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) + ( 
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14  = CARRY(( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) + ( 
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
        .cout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y22_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [0] & ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout  & ( (\u0|mm_interconnect_0|cmd_mux|saved_grant [1]) # (\u0|mm_interconnect_0|cmd_mux|saved_grant [0]) ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [0] & ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout  & ( \u0|mm_interconnect_0|cmd_mux|saved_grant [0] ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [0] & ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout  & ( \u0|mm_interconnect_0|cmd_mux|saved_grant [1] ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
        .datac(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
        .datad(gnd),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [0]),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .lut_mask = 64'h00000F0F33333F3F;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y24_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0] = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout  & ( 
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0])) # 
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|cmd_mux|src_data [79]))) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .datad(!\u0|mm_interconnect_0|cmd_mux|src_data [79]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .lut_mask = 64'h00000000F5A0F5A0;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y24_N46
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y24_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0] & 
// ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  & ( 
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ) ) ) 
// ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0] & ( 
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  & ( 
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0] & 
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ))) # (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout )))) ) ) ) # ( 
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0] & ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  & ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0] & ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  & ( 
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0] & 
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
        .datae(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 .lut_mask = 64'h0202AAAA0257AAFF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y24_N49
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y24_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout  = SUM(( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + ( 
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14  ))
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10  = CARRY(( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + ( 
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14  ))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
        .cout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .lut_mask = 64'h0000CCCC00000F0F;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y24_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout  & ( 
// ((\u0|mm_interconnect_0|cmd_mux|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [1])) # (\u0|mm_interconnect_0|cmd_mux|saved_grant [0]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout  & ( 
// (\u0|mm_interconnect_0|cmd_mux|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [1]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y24_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1] = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout  & !\u0|mm_interconnect_0|cmd_mux|src_data [80]) ) ) # ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout  & 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .datad(!\u0|mm_interconnect_0|cmd_mux|src_data [80]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .lut_mask = 64'h5050505055005500;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y24_N37
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y24_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1] & 
// ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  & 
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ) ) ) ) # ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1] & ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  & \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ) ) 
// ) ) # ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1] & ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  ) ) # 
// ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1] & ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1] & \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
        .datae(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .lut_mask = 64'h0505FFFF00330033;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y24_N55
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y24_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout  = SUM(( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + ( 
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10  ))
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6  = CARRY(( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + ( 
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
        .cout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y24_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout  & ( 
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2])) # 
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]))) # (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout )))) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout  & 
// ( (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2])) # 
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 .lut_mask = 64'h0A5F0A5F2A7F2A7F;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y24_N59
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y17_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|src_payload~4 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|src_payload~4_combout  = ( \u0|hps_0|fpga_interfaces|h2f_WDATA [4] & ( \u0|mm_interconnect_0|cmd_mux|saved_grant [0] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_WDATA [4]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux|src_payload~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|src_payload~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|src_payload~4 .lut_mask = 64'h000000000000FFFF;
defparam \u0|mm_interconnect_0|cmd_mux|src_payload~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y17_N8
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux|src_payload~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y24_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|src_data[82] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|src_data [82] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout  & ( ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout  & \u0|mm_interconnect_0|cmd_mux|saved_grant [0])) # 
// (\u0|mm_interconnect_0|cmd_mux|saved_grant [1]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout  & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout  & \u0|mm_interconnect_0|cmd_mux|saved_grant [0]) ) 
// )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout ),
        .datab(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux|src_data [82]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|src_data[82] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|src_data[82] .lut_mask = 64'h00AA00AA33BB33BB;
defparam \u0|mm_interconnect_0|cmd_mux|src_data[82] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y24_N17
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux|src_data [82]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y24_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3] = ( \u0|mm_interconnect_0|cmd_mux|src_data [82] & ( 
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3] & 
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux|src_data [82] & ( 
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout  & ((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]) # 
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux|src_data [82]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .lut_mask = 64'h00F500F500A000A0;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y24_N23
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y24_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [3] & ( ((\u0|mm_interconnect_0|cmd_mux|saved_grant [0] & 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout )) # (\u0|mm_interconnect_0|cmd_mux|saved_grant [1]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [3] & ( (\u0|mm_interconnect_0|cmd_mux|saved_grant [0] & 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout ),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .lut_mask = 64'h005500550F5F0F5F;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y24_N20
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y24_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout  = ( \u0|mm_interconnect_0|cmd_mux|src_data [86] & ( 
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] & ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  ) ) ) # ( 
// !\u0|mm_interconnect_0|cmd_mux|src_data [86] & ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] & ( 
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ) ) ) ) # ( 
// \u0|mm_interconnect_0|cmd_mux|src_data [86] & ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] & ( 
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .datae(!\u0|mm_interconnect_0|cmd_mux|src_data [86]),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .lut_mask = 64'h0000005500AA00FF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y24_N16
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y24_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout  = SUM(( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3] ) + ( 
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3] ) + ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6  ))

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .lut_mask = 64'h0000AAAA000000FF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y24_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout  & ( 
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3])) # 
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]))) # (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout )))) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout  & 
// ( (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3])) # 
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .lut_mask = 64'h0A5F0A5F2A7F2A7F;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y24_N53
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y17_N45
cyclonev_lcell_comb \u0|led_pio_test|always0~0 (
// Equation(s):
// \u0|led_pio_test|always0~0_combout  = ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & ( \u0|mm_interconnect_0|led_pio_test_s1_agent|m0_write~combout  & ( 
// (!\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [1] & (!\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [0] & 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3])) ) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [1]),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [0]),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent|m0_write~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|led_pio_test|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|led_pio_test|always0~0 .extended_lut = "off";
defparam \u0|led_pio_test|always0~0 .lut_mask = 64'h0000000080800000;
defparam \u0|led_pio_test|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y17_N53
dffeas \u0|led_pio_test|data_out[4]~_Duplicate_1 (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [4]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|led_pio_test|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|led_pio_test|data_out[4]~_Duplicate_1_q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|led_pio_test|data_out[4]~_Duplicate_1 .is_wysiwyg = "true";
defparam \u0|led_pio_test|data_out[4]~_Duplicate_1 .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y17_N6
cyclonev_lcell_comb \u0|led_pio_test|readdata[4] (
// Equation(s):
// \u0|led_pio_test|readdata [4] = ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( 
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & \u0|led_pio_test|data_out[4]~_Duplicate_1_q ) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datab(gnd),
        .datac(!\u0|led_pio_test|data_out[4]~_Duplicate_1_q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|led_pio_test|readdata [4]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|led_pio_test|readdata[4] .extended_lut = "off";
defparam \u0|led_pio_test|readdata[4] .lut_mask = 64'h0A0A0A0A00000000;
defparam \u0|led_pio_test|readdata[4] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y17_N8
dffeas \u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|led_pio_test|readdata [4]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre[4] .power_up = "low";
// synopsys translate_on

// Location: FF_X23_Y17_N29
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y17_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~4 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~4_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][4]~q  ) ) # ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre [4] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre [4]),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][4]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~4 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y17_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|always0~0_combout  = ( \u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout  & ( (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [0]) # 
// ((!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|read~0_combout  & \u0|hps_0|fpga_interfaces|h2f_BREADY [0])) ) ) # ( !\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout  & ( (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used 
// [0]) # ((\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & !\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|read~0_combout )) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [0]),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|read~0_combout ),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_BREADY [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|always0~0 .lut_mask = 64'hDCDCDCDCCCFCCCFC;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y17_N53
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~4_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y17_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~59 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~59_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][4]~q  ) ) # ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg [0] & ((\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][4]~q ))) # 
// (\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg [0] & (\u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre [4])) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg [0]),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre [4]),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][4]~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~59_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~59 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~59 .lut_mask = 64'h1B1B1B1B0F0F0F0F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~59 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y2_N18
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|rx_data_flag~4 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|rx_data_flag~4_combout  = ( \A_SPW_TOP|SPW|RX|ready_control_p_r~q  & ( (\A_SPW_TOP|SPW|RX|rx_data_flag~0_combout  & \A_SPW_TOP|SPW|RX|rx_data_flag [4]) ) ) # ( !\A_SPW_TOP|SPW|RX|ready_control_p_r~q  & ( 
// (!\A_SPW_TOP|SPW|RX|data~0_combout  & (((\A_SPW_TOP|SPW|RX|rx_data_flag~0_combout  & \A_SPW_TOP|SPW|RX|rx_data_flag [4])) # (\A_SPW_TOP|SPW|RX|dta_timec_p [4]))) # (\A_SPW_TOP|SPW|RX|data~0_combout  & (((\A_SPW_TOP|SPW|RX|rx_data_flag [4])))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|dta_timec_p [4]),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag~0_combout ),
        .datac(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .datad(!\A_SPW_TOP|SPW|RX|data~0_combout ),
        .datae(!\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|rx_data_flag~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_data_flag~4 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|rx_data_flag~4 .lut_mask = 64'h570F0303570F0303;
defparam \A_SPW_TOP|SPW|RX|rx_data_flag~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y2_N23
dffeas \A_SPW_TOP|SPW|RX|rx_data_flag[4] (
        .clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|RX|rx_data_flag~4_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(!\A_SPW_TOP|SPW|RX|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_data_flag[4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|rx_data_flag[4] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X32_Y6_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector230~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector230~0_combout  = ( \A_SPW_TOP|rx_data|Selector226~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [4])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux4~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector226~0_combout  & ( \A_SPW_TOP|rx_data|mem[23][4]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .datac(!\A_SPW_TOP|rx_data|mem[23][4]~q ),
        .datad(!\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector226~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector230~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector230~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector230~0 .lut_mask = 64'h0F0F0F0F22772277;
defparam \A_SPW_TOP|rx_data|Selector230~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X32_Y6_N20
dffeas \A_SPW_TOP|rx_data|mem[23][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector230~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[23][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[23][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[23][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y6_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector509~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector509~0_combout  = ( \A_SPW_TOP|rx_data|mem[54][4]~q  & ( (!\A_SPW_TOP|rx_data|Selector505~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [4])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux4~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[54][4]~q  & ( (\A_SPW_TOP|rx_data|Selector505~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [4])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux4~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .datab(!\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|Selector505~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[54][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector509~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector509~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector509~0 .lut_mask = 64'h00530053FF53FF53;
defparam \A_SPW_TOP|rx_data|Selector509~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y6_N17
dffeas \A_SPW_TOP|rx_data|mem[54][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector509~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[54][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[54][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[54][4] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X32_Y6_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector221~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector221~0_combout  = ( \A_SPW_TOP|rx_data|Mux4~20_combout  & ( (!\A_SPW_TOP|rx_data|Selector217~0_combout  & (((\A_SPW_TOP|rx_data|mem[22][4]~q )))) # (\A_SPW_TOP|rx_data|Selector217~0_combout  & (((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [4])) # (\A_SPW_TOP|rx_data|state_data_write.00~q ))) ) ) # ( !\A_SPW_TOP|rx_data|Mux4~20_combout  & ( (!\A_SPW_TOP|rx_data|Selector217~0_combout  & (((\A_SPW_TOP|rx_data|mem[22][4]~q )))) # (\A_SPW_TOP|rx_data|Selector217~0_combout  & 
// (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [4]))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .datac(!\A_SPW_TOP|rx_data|mem[22][4]~q ),
        .datad(!\A_SPW_TOP|rx_data|Selector217~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector221~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector221~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector221~0 .lut_mask = 64'h0F220F220F770F77;
defparam \A_SPW_TOP|rx_data|Selector221~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X32_Y6_N23
dffeas \A_SPW_TOP|rx_data|mem[22][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector221~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[22][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[22][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[22][4] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X32_Y6_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector518~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector518~0_combout  = ( \A_SPW_TOP|rx_data|mem[55][4]~q  & ( (!\A_SPW_TOP|rx_data|Selector514~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [4])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux4~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[55][4]~q  & ( (\A_SPW_TOP|rx_data|Selector514~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [4])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux4~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .datac(!\A_SPW_TOP|rx_data|Selector514~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[55][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector518~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector518~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector518~0 .lut_mask = 64'h02070207F2F7F2F7;
defparam \A_SPW_TOP|rx_data|Selector518~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X32_Y6_N8
dffeas \A_SPW_TOP|rx_data|mem[55][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector518~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[55][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[55][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[55][4] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X32_Y6_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux4~17 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux4~17_combout  = ( \A_SPW_TOP|rx_data|mem[55][4]~q  & ( \A_SPW_TOP|rx_data|wr_ptr [0] & ( (\A_SPW_TOP|rx_data|wr_ptr [5]) # (\A_SPW_TOP|rx_data|mem[23][4]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[55][4]~q  & ( \A_SPW_TOP|rx_data|wr_ptr 
// [0] & ( (\A_SPW_TOP|rx_data|mem[23][4]~q  & !\A_SPW_TOP|rx_data|wr_ptr [5]) ) ) ) # ( \A_SPW_TOP|rx_data|mem[55][4]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [0] & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & ((\A_SPW_TOP|rx_data|mem[22][4]~q ))) # 
// (\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|mem[54][4]~q )) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[55][4]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [0] & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & ((\A_SPW_TOP|rx_data|mem[22][4]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr 
// [5] & (\A_SPW_TOP|rx_data|mem[54][4]~q )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[23][4]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[54][4]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[22][4]~q ),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datae(!\A_SPW_TOP|rx_data|mem[55][4]~q ),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux4~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux4~17 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux4~17 .lut_mask = 64'h0F330F33550055FF;
defparam \A_SPW_TOP|rx_data|Mux4~17 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X33_Y6_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector581~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector581~0_combout  = ( \A_SPW_TOP|rx_data|mem[62][4]~q  & ( (!\A_SPW_TOP|rx_data|Selector577~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [4])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux4~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[62][4]~q  & ( (\A_SPW_TOP|rx_data|Selector577~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [4])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux4~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Selector577~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[62][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector581~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector581~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector581~0 .lut_mask = 64'h04070407F4F7F4F7;
defparam \A_SPW_TOP|rx_data|Selector581~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X33_Y6_N17
dffeas \A_SPW_TOP|rx_data|mem[62][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector581~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[62][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[62][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[62][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X33_Y6_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector302~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector302~0_combout  = ( \A_SPW_TOP|rx_data|mem[31][4]~q  & ( (!\A_SPW_TOP|rx_data|Selector298~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [4]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux4~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[31][4]~q  & ( (\A_SPW_TOP|rx_data|Selector298~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [4]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux4~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Selector298~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[31][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector302~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector302~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector302~0 .lut_mask = 64'h010D010DF1FDF1FD;
defparam \A_SPW_TOP|rx_data|Selector302~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X33_Y6_N20
dffeas \A_SPW_TOP|rx_data|mem[31][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector302~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[31][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[31][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[31][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X35_Y6_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector293~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector293~0_combout  = ( \A_SPW_TOP|rx_data|mem[30][4]~q  & ( (!\A_SPW_TOP|rx_data|Selector289~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [4])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux4~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[30][4]~q  & ( (\A_SPW_TOP|rx_data|Selector289~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [4])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux4~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .datab(!\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector289~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[30][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector293~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector293~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector293~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|rx_data|Selector293~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X35_Y6_N20
dffeas \A_SPW_TOP|rx_data|mem[30][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector293~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[30][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[30][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[30][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X33_Y6_N33
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector590~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector590~0_combout  = ( \A_SPW_TOP|rx_data|mem[63][4]~q  & ( (!\A_SPW_TOP|rx_data|Selector586~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [4]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux4~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[63][4]~q  & ( (\A_SPW_TOP|rx_data|Selector586~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [4]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux4~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Selector586~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[63][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector590~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector590~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector590~0 .lut_mask = 64'h010D010DF1FDF1FD;
defparam \A_SPW_TOP|rx_data|Selector590~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X33_Y6_N53
dffeas \A_SPW_TOP|rx_data|mem[63][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector590~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[63][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[63][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[63][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X33_Y6_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux4~18 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux4~18_combout  = ( \A_SPW_TOP|rx_data|mem[30][4]~q  & ( \A_SPW_TOP|rx_data|mem[63][4]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & (((!\A_SPW_TOP|rx_data|wr_ptr [0]) # (\A_SPW_TOP|rx_data|mem[31][4]~q )))) # (\A_SPW_TOP|rx_data|wr_ptr [5] 
// & (((\A_SPW_TOP|rx_data|wr_ptr [0])) # (\A_SPW_TOP|rx_data|mem[62][4]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[30][4]~q  & ( \A_SPW_TOP|rx_data|mem[63][4]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & (((\A_SPW_TOP|rx_data|mem[31][4]~q  & 
// \A_SPW_TOP|rx_data|wr_ptr [0])))) # (\A_SPW_TOP|rx_data|wr_ptr [5] & (((\A_SPW_TOP|rx_data|wr_ptr [0])) # (\A_SPW_TOP|rx_data|mem[62][4]~q ))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[30][4]~q  & ( !\A_SPW_TOP|rx_data|mem[63][4]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr 
// [5] & (((!\A_SPW_TOP|rx_data|wr_ptr [0]) # (\A_SPW_TOP|rx_data|mem[31][4]~q )))) # (\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|mem[62][4]~q  & ((!\A_SPW_TOP|rx_data|wr_ptr [0])))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[30][4]~q  & ( 
// !\A_SPW_TOP|rx_data|mem[63][4]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & (((\A_SPW_TOP|rx_data|mem[31][4]~q  & \A_SPW_TOP|rx_data|wr_ptr [0])))) # (\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|mem[62][4]~q  & ((!\A_SPW_TOP|rx_data|wr_ptr [0])))) ) ) 
// )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datab(!\A_SPW_TOP|rx_data|mem[62][4]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[31][4]~q ),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datae(!\A_SPW_TOP|rx_data|mem[30][4]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[63][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux4~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux4~18 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux4~18 .lut_mask = 64'h110ABB0A115FBB5F;
defparam \A_SPW_TOP|rx_data|Mux4~18 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X32_Y6_N27
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector212~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector212~0_combout  = ( \A_SPW_TOP|rx_data|mem[21][4]~q  & ( (!\A_SPW_TOP|rx_data|Selector208~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [4])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux4~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[21][4]~q  & ( (\A_SPW_TOP|rx_data|Selector208~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [4])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux4~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .datac(!\A_SPW_TOP|rx_data|Selector208~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[21][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector212~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector212~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector212~0 .lut_mask = 64'h02070207F2F7F2F7;
defparam \A_SPW_TOP|rx_data|Selector212~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X32_Y6_N35
dffeas \A_SPW_TOP|rx_data|mem[21][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector212~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[21][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[21][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[21][4] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X32_Y6_N51
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector500~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector500~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector496~0_combout  & ((\A_SPW_TOP|rx_data|mem[53][4]~q ))) # (\A_SPW_TOP|rx_data|Selector496~0_combout  & 
// (\A_SPW_TOP|rx_data|Mux4~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector496~0_combout  & ((\A_SPW_TOP|rx_data|mem[53][4]~q ))) # (\A_SPW_TOP|rx_data|Selector496~0_combout  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [4])) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .datac(!\A_SPW_TOP|rx_data|Selector496~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[53][4]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector500~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector500~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector500~0 .lut_mask = 64'h03F303F305F505F5;
defparam \A_SPW_TOP|rx_data|Selector500~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X32_Y6_N56
dffeas \A_SPW_TOP|rx_data|mem[53][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector500~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[53][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[53][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[53][4] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X32_Y6_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector203~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector203~0_combout  = ( \A_SPW_TOP|rx_data|mem[20][4]~q  & ( (!\A_SPW_TOP|rx_data|Selector199~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [4])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux4~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[20][4]~q  & ( (\A_SPW_TOP|rx_data|Selector199~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [4])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux4~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .datac(!\A_SPW_TOP|rx_data|Selector199~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[20][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector203~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector203~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector203~0 .lut_mask = 64'h02070207F2F7F2F7;
defparam \A_SPW_TOP|rx_data|Selector203~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X32_Y6_N14
dffeas \A_SPW_TOP|rx_data|mem[20][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector203~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[20][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[20][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[20][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y6_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector491~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector491~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( \A_SPW_TOP|SPW|RX|rx_data_flag [4] & ( (!\A_SPW_TOP|rx_data|Selector487~0_combout  & (\A_SPW_TOP|rx_data|mem[52][4]~q )) # 
// (\A_SPW_TOP|rx_data|Selector487~0_combout  & ((\A_SPW_TOP|rx_data|Mux4~20_combout ))) ) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( \A_SPW_TOP|SPW|RX|rx_data_flag [4] & ( (\A_SPW_TOP|rx_data|Selector487~0_combout ) # 
// (\A_SPW_TOP|rx_data|mem[52][4]~q ) ) ) ) # ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( !\A_SPW_TOP|SPW|RX|rx_data_flag [4] & ( (!\A_SPW_TOP|rx_data|Selector487~0_combout  & (\A_SPW_TOP|rx_data|mem[52][4]~q )) # 
// (\A_SPW_TOP|rx_data|Selector487~0_combout  & ((\A_SPW_TOP|rx_data|Mux4~20_combout ))) ) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( !\A_SPW_TOP|SPW|RX|rx_data_flag [4] & ( (\A_SPW_TOP|rx_data|mem[52][4]~q  & 
// !\A_SPW_TOP|rx_data|Selector487~0_combout ) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[52][4]~q ),
        .datab(!\A_SPW_TOP|rx_data|Selector487~0_combout ),
        .datac(!\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .dataf(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector491~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector491~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector491~0 .lut_mask = 64'h4444474777774747;
defparam \A_SPW_TOP|rx_data|Selector491~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y6_N26
dffeas \A_SPW_TOP|rx_data|mem[52][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector491~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[52][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[52][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[52][4] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X32_Y6_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux4~15 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux4~15_combout  = ( \A_SPW_TOP|rx_data|mem[20][4]~q  & ( \A_SPW_TOP|rx_data|mem[52][4]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [0]) # ((!\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|mem[21][4]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [5] & 
// ((\A_SPW_TOP|rx_data|mem[53][4]~q )))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[20][4]~q  & ( \A_SPW_TOP|rx_data|mem[52][4]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & (((\A_SPW_TOP|rx_data|wr_ptr [5])))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & 
// ((!\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|mem[21][4]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [5] & ((\A_SPW_TOP|rx_data|mem[53][4]~q ))))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[20][4]~q  & ( !\A_SPW_TOP|rx_data|mem[52][4]~q  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [0] & (((!\A_SPW_TOP|rx_data|wr_ptr [5])))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & ((!\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|mem[21][4]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [5] & ((\A_SPW_TOP|rx_data|mem[53][4]~q ))))) ) 
// ) ) # ( !\A_SPW_TOP|rx_data|mem[20][4]~q  & ( !\A_SPW_TOP|rx_data|mem[52][4]~q  & ( (\A_SPW_TOP|rx_data|wr_ptr [0] & ((!\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|mem[21][4]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [5] & 
// ((\A_SPW_TOP|rx_data|mem[53][4]~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[21][4]~q ),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datac(!\A_SPW_TOP|rx_data|mem[53][4]~q ),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datae(!\A_SPW_TOP|rx_data|mem[20][4]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[52][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux4~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux4~15 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux4~15 .lut_mask = 64'h1103DD0311CFDDCF;
defparam \A_SPW_TOP|rx_data|Mux4~15 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X32_Y6_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector275~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector275~0_combout  = ( \A_SPW_TOP|rx_data|mem[28][4]~q  & ( (!\A_SPW_TOP|rx_data|Selector271~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [4])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux4~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[28][4]~q  & ( (\A_SPW_TOP|rx_data|Selector271~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [4])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux4~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .datac(!\A_SPW_TOP|rx_data|Selector271~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[28][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector275~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector275~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector275~0 .lut_mask = 64'h02070207F2F7F2F7;
defparam \A_SPW_TOP|rx_data|Selector275~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X32_Y6_N17
dffeas \A_SPW_TOP|rx_data|mem[28][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector275~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[28][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[28][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[28][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X33_Y6_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector563~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector563~0_combout  = ( \A_SPW_TOP|rx_data|mem[60][4]~q  & ( (!\A_SPW_TOP|rx_data|Selector559~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [4]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux4~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[60][4]~q  & ( (\A_SPW_TOP|rx_data|Selector559~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [4]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux4~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Selector559~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[60][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector563~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector563~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector563~0 .lut_mask = 64'h010D010DF1FDF1FD;
defparam \A_SPW_TOP|rx_data|Selector563~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X33_Y6_N26
dffeas \A_SPW_TOP|rx_data|mem[60][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector563~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[60][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[60][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[60][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X35_Y6_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector284~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector284~0_combout  = ( \A_SPW_TOP|rx_data|mem[29][4]~q  & ( (!\A_SPW_TOP|rx_data|Selector280~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [4]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux4~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[29][4]~q  & ( (\A_SPW_TOP|rx_data|Selector280~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [4]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux4~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .datac(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .datad(!\A_SPW_TOP|rx_data|Selector280~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[29][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector284~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector284~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector284~0 .lut_mask = 64'h001B001BFF1BFF1B;
defparam \A_SPW_TOP|rx_data|Selector284~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X35_Y6_N32
dffeas \A_SPW_TOP|rx_data|mem[29][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector284~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[29][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[29][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[29][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X33_Y6_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux4~16 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux4~16_combout  = ( \A_SPW_TOP|rx_data|mem[61][4]~q  & ( \A_SPW_TOP|rx_data|wr_ptr [0] & ( (\A_SPW_TOP|rx_data|mem[29][4]~q ) # (\A_SPW_TOP|rx_data|wr_ptr [5]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[61][4]~q  & ( \A_SPW_TOP|rx_data|wr_ptr 
// [0] & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & \A_SPW_TOP|rx_data|mem[29][4]~q ) ) ) ) # ( \A_SPW_TOP|rx_data|mem[61][4]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [0] & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|mem[28][4]~q )) # 
// (\A_SPW_TOP|rx_data|wr_ptr [5] & ((\A_SPW_TOP|rx_data|mem[60][4]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[61][4]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [0] & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|mem[28][4]~q )) # (\A_SPW_TOP|rx_data|wr_ptr 
// [5] & ((\A_SPW_TOP|rx_data|mem[60][4]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datab(!\A_SPW_TOP|rx_data|mem[28][4]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[60][4]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[29][4]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[61][4]~q ),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux4~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux4~16 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux4~16 .lut_mask = 64'h2727272700AA55FF;
defparam \A_SPW_TOP|rx_data|Mux4~16 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y6_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux4~19 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux4~19_combout  = ( \A_SPW_TOP|rx_data|Mux4~15_combout  & ( \A_SPW_TOP|rx_data|Mux4~16_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [1]) # ((!\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|Mux4~17_combout )) # 
// (\A_SPW_TOP|rx_data|wr_ptr [3] & ((\A_SPW_TOP|rx_data|Mux4~18_combout )))) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux4~15_combout  & ( \A_SPW_TOP|rx_data|Mux4~16_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & (((\A_SPW_TOP|rx_data|wr_ptr [3])))) # 
// (\A_SPW_TOP|rx_data|wr_ptr [1] & ((!\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|Mux4~17_combout )) # (\A_SPW_TOP|rx_data|wr_ptr [3] & ((\A_SPW_TOP|rx_data|Mux4~18_combout ))))) ) ) ) # ( \A_SPW_TOP|rx_data|Mux4~15_combout  & ( 
// !\A_SPW_TOP|rx_data|Mux4~16_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & (((!\A_SPW_TOP|rx_data|wr_ptr [3])))) # (\A_SPW_TOP|rx_data|wr_ptr [1] & ((!\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|Mux4~17_combout )) # (\A_SPW_TOP|rx_data|wr_ptr [3] 
// & ((\A_SPW_TOP|rx_data|Mux4~18_combout ))))) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux4~15_combout  & ( !\A_SPW_TOP|rx_data|Mux4~16_combout  & ( (\A_SPW_TOP|rx_data|wr_ptr [1] & ((!\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|Mux4~17_combout )) # 
// (\A_SPW_TOP|rx_data|wr_ptr [3] & ((\A_SPW_TOP|rx_data|Mux4~18_combout ))))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux4~17_combout ),
        .datab(!\A_SPW_TOP|rx_data|Mux4~18_combout ),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datae(!\A_SPW_TOP|rx_data|Mux4~15_combout ),
        .dataf(!\A_SPW_TOP|rx_data|Mux4~16_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux4~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux4~19 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux4~19 .lut_mask = 64'h0503F50305F3F5F3;
defparam \A_SPW_TOP|rx_data|Mux4~19 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X31_Y6_N21
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector455~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector455~0_combout  = ( \A_SPW_TOP|rx_data|mem[48][4]~q  & ( (!\A_SPW_TOP|rx_data|Selector451~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [4]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux4~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[48][4]~q  & ( (\A_SPW_TOP|rx_data|Selector451~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [4]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux4~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector451~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[48][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector455~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector455~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector455~0 .lut_mask = 64'h010B010BF1FBF1FB;
defparam \A_SPW_TOP|rx_data|Selector455~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y6_N35
dffeas \A_SPW_TOP|rx_data|mem[48][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector455~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[48][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[48][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[48][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y6_N57
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector482~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector482~0_combout  = ( \A_SPW_TOP|rx_data|mem[51][4]~q  & ( (!\A_SPW_TOP|rx_data|Selector478~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [4])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux4~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[51][4]~q  & ( (\A_SPW_TOP|rx_data|Selector478~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [4])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux4~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .datab(!\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector478~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[51][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector482~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector482~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector482~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|rx_data|Selector482~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y6_N8
dffeas \A_SPW_TOP|rx_data|mem[51][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector482~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[51][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[51][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[51][4] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X32_Y4_N21
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector464~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector464~0_combout  = ( \A_SPW_TOP|rx_data|Mux4~20_combout  & ( \A_SPW_TOP|rx_data|mem[49][4]~q  & ( ((!\A_SPW_TOP|rx_data|Selector460~0_combout ) # (\A_SPW_TOP|SPW|RX|rx_data_flag [4])) # (\A_SPW_TOP|rx_data|state_data_write.00~q ) 
// ) ) ) # ( !\A_SPW_TOP|rx_data|Mux4~20_combout  & ( \A_SPW_TOP|rx_data|mem[49][4]~q  & ( (!\A_SPW_TOP|rx_data|Selector460~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & \A_SPW_TOP|SPW|RX|rx_data_flag [4])) ) ) ) # ( 
// \A_SPW_TOP|rx_data|Mux4~20_combout  & ( !\A_SPW_TOP|rx_data|mem[49][4]~q  & ( (\A_SPW_TOP|rx_data|Selector460~0_combout  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [4]) # (\A_SPW_TOP|rx_data|state_data_write.00~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux4~20_combout  
// & ( !\A_SPW_TOP|rx_data|mem[49][4]~q  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Selector460~0_combout  & \A_SPW_TOP|SPW|RX|rx_data_flag [4])) ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Selector460~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .datae(!\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .dataf(!\A_SPW_TOP|rx_data|mem[49][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector464~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector464~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector464~0 .lut_mask = 64'h000C030FF0FCF3FF;
defparam \A_SPW_TOP|rx_data|Selector464~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X32_Y4_N14
dffeas \A_SPW_TOP|rx_data|mem[49][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector464~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[49][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[49][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[49][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y6_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector473~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector473~0_combout  = ( \A_SPW_TOP|rx_data|Selector469~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [4]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux4~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector469~0_combout  & ( \A_SPW_TOP|rx_data|mem[50][4]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|mem[50][4]~q ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector469~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector473~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector473~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector473~0 .lut_mask = 64'h0F0F0F0F11BB11BB;
defparam \A_SPW_TOP|rx_data|Selector473~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y6_N29
dffeas \A_SPW_TOP|rx_data|mem[50][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector473~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[50][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[50][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[50][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y6_N57
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux4~7 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux4~7_combout  = ( \A_SPW_TOP|rx_data|mem[49][4]~q  & ( \A_SPW_TOP|rx_data|mem[50][4]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & (((\A_SPW_TOP|rx_data|wr_ptr [1])) # (\A_SPW_TOP|rx_data|mem[48][4]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & 
// (((!\A_SPW_TOP|rx_data|wr_ptr [1]) # (\A_SPW_TOP|rx_data|mem[51][4]~q )))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[49][4]~q  & ( \A_SPW_TOP|rx_data|mem[50][4]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & (((\A_SPW_TOP|rx_data|wr_ptr [1])) # 
// (\A_SPW_TOP|rx_data|mem[48][4]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & (((\A_SPW_TOP|rx_data|mem[51][4]~q  & \A_SPW_TOP|rx_data|wr_ptr [1])))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[49][4]~q  & ( !\A_SPW_TOP|rx_data|mem[50][4]~q  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|mem[48][4]~q  & ((!\A_SPW_TOP|rx_data|wr_ptr [1])))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & (((!\A_SPW_TOP|rx_data|wr_ptr [1]) # (\A_SPW_TOP|rx_data|mem[51][4]~q )))) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|mem[49][4]~q  & ( !\A_SPW_TOP|rx_data|mem[50][4]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|mem[48][4]~q  & ((!\A_SPW_TOP|rx_data|wr_ptr [1])))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & (((\A_SPW_TOP|rx_data|mem[51][4]~q  & 
// \A_SPW_TOP|rx_data|wr_ptr [1])))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datab(!\A_SPW_TOP|rx_data|mem[48][4]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[51][4]~q ),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datae(!\A_SPW_TOP|rx_data|mem[49][4]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[50][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux4~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux4~7 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux4~7 .lut_mask = 64'h2205770522AF77AF;
defparam \A_SPW_TOP|rx_data|Mux4~7 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X32_Y4_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector545~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector545~0_combout  = ( \A_SPW_TOP|rx_data|Mux4~20_combout  & ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (\A_SPW_TOP|rx_data|mem[58][4]~q ) # (\A_SPW_TOP|rx_data|Selector541~0_combout ) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|Mux4~20_combout  & ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector541~0_combout  & \A_SPW_TOP|rx_data|mem[58][4]~q ) ) ) ) # ( \A_SPW_TOP|rx_data|Mux4~20_combout  & ( 
// !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector541~0_combout  & ((\A_SPW_TOP|rx_data|mem[58][4]~q ))) # (\A_SPW_TOP|rx_data|Selector541~0_combout  & (\A_SPW_TOP|SPW|RX|rx_data_flag [4])) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|Mux4~20_combout  & ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector541~0_combout  & ((\A_SPW_TOP|rx_data|mem[58][4]~q ))) # (\A_SPW_TOP|rx_data|Selector541~0_combout  & (\A_SPW_TOP|SPW|RX|rx_data_flag 
// [4])) ) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .datab(!\A_SPW_TOP|rx_data|Selector541~0_combout ),
        .datac(!\A_SPW_TOP|rx_data|mem[58][4]~q ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector545~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector545~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector545~0 .lut_mask = 64'h1D1D1D1D0C0C3F3F;
defparam \A_SPW_TOP|rx_data|Selector545~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X32_Y4_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|mem[58][4]~feeder (
// Equation(s):
// \A_SPW_TOP|rx_data|mem[58][4]~feeder_combout  = ( \A_SPW_TOP|rx_data|Selector545~0_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector545~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|mem[58][4]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[58][4]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|mem[58][4]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|rx_data|mem[58][4]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X32_Y4_N5
dffeas \A_SPW_TOP|rx_data|mem[58][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|rx_data|mem[58][4]~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[58][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[58][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[58][4] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X32_Y4_N57
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector527~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector527~0_combout  = ( \A_SPW_TOP|SPW|RX|rx_data_flag [4] & ( \A_SPW_TOP|rx_data|mem[56][4]~q  & ( (!\A_SPW_TOP|rx_data|Selector523~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|rx_data|Mux4~20_combout )) 
// ) ) ) # ( !\A_SPW_TOP|SPW|RX|rx_data_flag [4] & ( \A_SPW_TOP|rx_data|mem[56][4]~q  & ( (!\A_SPW_TOP|rx_data|Selector523~0_combout ) # ((\A_SPW_TOP|rx_data|state_data_write.00~q  & \A_SPW_TOP|rx_data|Mux4~20_combout )) ) ) ) # ( 
// \A_SPW_TOP|SPW|RX|rx_data_flag [4] & ( !\A_SPW_TOP|rx_data|mem[56][4]~q  & ( (\A_SPW_TOP|rx_data|Selector523~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|rx_data|Mux4~20_combout ))) ) ) ) # ( !\A_SPW_TOP|SPW|RX|rx_data_flag [4] 
// & ( !\A_SPW_TOP|rx_data|mem[56][4]~q  & ( (\A_SPW_TOP|rx_data|Selector523~0_combout  & (\A_SPW_TOP|rx_data|state_data_write.00~q  & \A_SPW_TOP|rx_data|Mux4~20_combout )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Selector523~0_combout ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .dataf(!\A_SPW_TOP|rx_data|mem[56][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector527~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector527~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector527~0 .lut_mask = 64'h01014545ABABEFEF;
defparam \A_SPW_TOP|rx_data|Selector527~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X32_Y4_N50
dffeas \A_SPW_TOP|rx_data|mem[56][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector527~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[56][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[56][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[56][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y5_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector536~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector536~0_combout  = ( \A_SPW_TOP|SPW|RX|rx_data_flag [4] & ( (!\A_SPW_TOP|rx_data|Selector532~0_combout  & (\A_SPW_TOP|rx_data|mem[57][4]~q )) # (\A_SPW_TOP|rx_data|Selector532~0_combout  & 
// (((!\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|rx_data|Mux4~20_combout )))) ) ) # ( !\A_SPW_TOP|SPW|RX|rx_data_flag [4] & ( (!\A_SPW_TOP|rx_data|Selector532~0_combout  & (\A_SPW_TOP|rx_data|mem[57][4]~q )) # 
// (\A_SPW_TOP|rx_data|Selector532~0_combout  & (((\A_SPW_TOP|rx_data|Mux4~20_combout  & \A_SPW_TOP|rx_data|state_data_write.00~q )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[57][4]~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|Selector532~0_combout ),
        .datae(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector536~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector536~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector536~0 .lut_mask = 64'h550355F3550355F3;
defparam \A_SPW_TOP|rx_data|Selector536~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y5_N53
dffeas \A_SPW_TOP|rx_data|mem[57][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector536~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[57][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[57][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[57][4] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X32_Y4_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector554~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector554~0_combout  = ( \A_SPW_TOP|SPW|RX|rx_data_flag [4] & ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector550~0_combout  & (\A_SPW_TOP|rx_data|mem[59][4]~q )) # 
// (\A_SPW_TOP|rx_data|Selector550~0_combout  & ((\A_SPW_TOP|rx_data|Mux4~20_combout ))) ) ) ) # ( !\A_SPW_TOP|SPW|RX|rx_data_flag [4] & ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector550~0_combout  & 
// (\A_SPW_TOP|rx_data|mem[59][4]~q )) # (\A_SPW_TOP|rx_data|Selector550~0_combout  & ((\A_SPW_TOP|rx_data|Mux4~20_combout ))) ) ) ) # ( \A_SPW_TOP|SPW|RX|rx_data_flag [4] & ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( 
// (\A_SPW_TOP|rx_data|Selector550~0_combout ) # (\A_SPW_TOP|rx_data|mem[59][4]~q ) ) ) ) # ( !\A_SPW_TOP|SPW|RX|rx_data_flag [4] & ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( (\A_SPW_TOP|rx_data|mem[59][4]~q  & !\A_SPW_TOP|rx_data|Selector550~0_combout 
// ) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[59][4]~q ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .datad(!\A_SPW_TOP|rx_data|Selector550~0_combout ),
        .datae(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector554~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector554~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector554~0 .lut_mask = 64'h550055FF550F550F;
defparam \A_SPW_TOP|rx_data|Selector554~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X32_Y4_N56
dffeas \A_SPW_TOP|rx_data|mem[59][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector554~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[59][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[59][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[59][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y5_N51
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux4~8 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux4~8_combout  = ( \A_SPW_TOP|rx_data|mem[57][4]~q  & ( \A_SPW_TOP|rx_data|mem[59][4]~q  & ( ((!\A_SPW_TOP|rx_data|wr_ptr [1] & ((\A_SPW_TOP|rx_data|mem[56][4]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|mem[58][4]~q 
// ))) # (\A_SPW_TOP|rx_data|wr_ptr [0]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[57][4]~q  & ( \A_SPW_TOP|rx_data|mem[59][4]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & (((\A_SPW_TOP|rx_data|mem[56][4]~q  & !\A_SPW_TOP|rx_data|wr_ptr [0])))) # 
// (\A_SPW_TOP|rx_data|wr_ptr [1] & (((\A_SPW_TOP|rx_data|wr_ptr [0])) # (\A_SPW_TOP|rx_data|mem[58][4]~q ))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[57][4]~q  & ( !\A_SPW_TOP|rx_data|mem[59][4]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & (((\A_SPW_TOP|rx_data|wr_ptr 
// [0]) # (\A_SPW_TOP|rx_data|mem[56][4]~q )))) # (\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|mem[58][4]~q  & ((!\A_SPW_TOP|rx_data|wr_ptr [0])))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[57][4]~q  & ( !\A_SPW_TOP|rx_data|mem[59][4]~q  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [0] & ((!\A_SPW_TOP|rx_data|wr_ptr [1] & ((\A_SPW_TOP|rx_data|mem[56][4]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|mem[58][4]~q )))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datab(!\A_SPW_TOP|rx_data|mem[58][4]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[56][4]~q ),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datae(!\A_SPW_TOP|rx_data|mem[57][4]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[59][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux4~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux4~8 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux4~8 .lut_mask = 64'h1B001BAA1B551BFF;
defparam \A_SPW_TOP|rx_data|Mux4~8 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X32_Y6_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector176~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector176~0_combout  = ( \A_SPW_TOP|rx_data|mem[17][4]~q  & ( (!\A_SPW_TOP|rx_data|Selector172~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [4]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux4~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[17][4]~q  & ( (\A_SPW_TOP|rx_data|Selector172~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [4]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux4~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|Selector172~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[17][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector176~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector176~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector176~0 .lut_mask = 64'h00350035FF35FF35;
defparam \A_SPW_TOP|rx_data|Selector176~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X32_Y6_N59
dffeas \A_SPW_TOP|rx_data|mem[17][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector176~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[17][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[17][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[17][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X33_Y6_N57
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector167~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector167~0_combout  = ( \A_SPW_TOP|rx_data|mem[16][4]~q  & ( (!\A_SPW_TOP|rx_data|Selector163~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [4]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux4~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[16][4]~q  & ( (\A_SPW_TOP|rx_data|Selector163~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [4]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux4~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Selector163~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[16][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector167~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector167~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector167~0 .lut_mask = 64'h010D010DF1FDF1FD;
defparam \A_SPW_TOP|rx_data|Selector167~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X33_Y6_N11
dffeas \A_SPW_TOP|rx_data|mem[16][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector167~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[16][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[16][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[16][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X35_Y6_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector185~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector185~0_combout  = ( \A_SPW_TOP|rx_data|Selector181~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [4])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux4~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector181~0_combout  & ( \A_SPW_TOP|rx_data|mem[18][4]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[18][4]~q ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .datad(!\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector181~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector185~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector185~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector185~0 .lut_mask = 64'h555555550C3F0C3F;
defparam \A_SPW_TOP|rx_data|Selector185~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X35_Y6_N2
dffeas \A_SPW_TOP|rx_data|mem[18][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector185~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[18][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[18][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[18][4] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X32_Y6_N39
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector194~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector194~0_combout  = ( \A_SPW_TOP|rx_data|Selector190~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [4])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux4~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector190~0_combout  & ( \A_SPW_TOP|rx_data|mem[19][4]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .datac(!\A_SPW_TOP|rx_data|mem[19][4]~q ),
        .datad(!\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector190~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector194~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector194~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector194~0 .lut_mask = 64'h0F0F0F0F22772277;
defparam \A_SPW_TOP|rx_data|Selector194~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X32_Y6_N32
dffeas \A_SPW_TOP|rx_data|mem[19][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector194~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[19][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[19][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[19][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X33_Y6_N27
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux4~5 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux4~5_combout  = ( \A_SPW_TOP|rx_data|mem[18][4]~q  & ( \A_SPW_TOP|rx_data|mem[19][4]~q  & ( ((!\A_SPW_TOP|rx_data|wr_ptr [0] & ((\A_SPW_TOP|rx_data|mem[16][4]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|mem[17][4]~q 
// ))) # (\A_SPW_TOP|rx_data|wr_ptr [1]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[18][4]~q  & ( \A_SPW_TOP|rx_data|mem[19][4]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & (((\A_SPW_TOP|rx_data|mem[16][4]~q  & !\A_SPW_TOP|rx_data|wr_ptr [1])))) # 
// (\A_SPW_TOP|rx_data|wr_ptr [0] & (((\A_SPW_TOP|rx_data|wr_ptr [1])) # (\A_SPW_TOP|rx_data|mem[17][4]~q ))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[18][4]~q  & ( !\A_SPW_TOP|rx_data|mem[19][4]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & (((\A_SPW_TOP|rx_data|wr_ptr 
// [1]) # (\A_SPW_TOP|rx_data|mem[16][4]~q )))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|mem[17][4]~q  & ((!\A_SPW_TOP|rx_data|wr_ptr [1])))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[18][4]~q  & ( !\A_SPW_TOP|rx_data|mem[19][4]~q  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [1] & ((!\A_SPW_TOP|rx_data|wr_ptr [0] & ((\A_SPW_TOP|rx_data|mem[16][4]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|mem[17][4]~q )))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[17][4]~q ),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datac(!\A_SPW_TOP|rx_data|mem[16][4]~q ),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datae(!\A_SPW_TOP|rx_data|mem[18][4]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[19][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux4~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux4~5 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux4~5 .lut_mask = 64'h1D001DCC1D331DFF;
defparam \A_SPW_TOP|rx_data|Mux4~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X36_Y6_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector248~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector248~0_combout  = ( \A_SPW_TOP|SPW|RX|rx_data_flag [4] & ( \A_SPW_TOP|rx_data|mem[25][4]~q  & ( ((!\A_SPW_TOP|rx_data|Selector244~0_combout ) # (!\A_SPW_TOP|rx_data|state_data_write.00~q )) # (\A_SPW_TOP|rx_data|Mux4~20_combout ) 
// ) ) ) # ( !\A_SPW_TOP|SPW|RX|rx_data_flag [4] & ( \A_SPW_TOP|rx_data|mem[25][4]~q  & ( (!\A_SPW_TOP|rx_data|Selector244~0_combout ) # ((\A_SPW_TOP|rx_data|Mux4~20_combout  & \A_SPW_TOP|rx_data|state_data_write.00~q )) ) ) ) # ( 
// \A_SPW_TOP|SPW|RX|rx_data_flag [4] & ( !\A_SPW_TOP|rx_data|mem[25][4]~q  & ( (\A_SPW_TOP|rx_data|Selector244~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|rx_data|Mux4~20_combout ))) ) ) ) # ( !\A_SPW_TOP|SPW|RX|rx_data_flag [4] 
// & ( !\A_SPW_TOP|rx_data|mem[25][4]~q  & ( (\A_SPW_TOP|rx_data|Mux4~20_combout  & (\A_SPW_TOP|rx_data|Selector244~0_combout  & \A_SPW_TOP|rx_data|state_data_write.00~q )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .datab(!\A_SPW_TOP|rx_data|Selector244~0_combout ),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .dataf(!\A_SPW_TOP|rx_data|mem[25][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector248~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector248~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector248~0 .lut_mask = 64'h01013131CDCDFDFD;
defparam \A_SPW_TOP|rx_data|Selector248~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X33_Y6_N14
dffeas \A_SPW_TOP|rx_data|mem[25][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector248~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[25][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[25][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[25][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X36_Y6_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector239~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector239~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( \A_SPW_TOP|rx_data|mem[24][4]~q  & ( (!\A_SPW_TOP|rx_data|Selector235~0_combout ) # (\A_SPW_TOP|rx_data|Mux4~20_combout ) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( \A_SPW_TOP|rx_data|mem[24][4]~q  & ( (!\A_SPW_TOP|rx_data|Selector235~0_combout ) # (\A_SPW_TOP|SPW|RX|rx_data_flag [4]) ) ) ) # ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( 
// !\A_SPW_TOP|rx_data|mem[24][4]~q  & ( (\A_SPW_TOP|rx_data|Mux4~20_combout  & \A_SPW_TOP|rx_data|Selector235~0_combout ) ) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( !\A_SPW_TOP|rx_data|mem[24][4]~q  & ( (\A_SPW_TOP|SPW|RX|rx_data_flag [4] & 
// \A_SPW_TOP|rx_data|Selector235~0_combout ) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .datad(!\A_SPW_TOP|rx_data|Selector235~0_combout ),
        .datae(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[24][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector239~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector239~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector239~0 .lut_mask = 64'h000F0055FF0FFF55;
defparam \A_SPW_TOP|rx_data|Selector239~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X35_Y6_N5
dffeas \A_SPW_TOP|rx_data|mem[24][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector239~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[24][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[24][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[24][4] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X32_Y6_N45
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector257~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector257~0_combout  = ( \A_SPW_TOP|rx_data|Selector253~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [4])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux4~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector253~0_combout  & ( \A_SPW_TOP|rx_data|mem[26][4]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .datac(!\A_SPW_TOP|rx_data|mem[26][4]~q ),
        .datad(!\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector253~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector257~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector257~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector257~0 .lut_mask = 64'h0F0F0F0F22772277;
defparam \A_SPW_TOP|rx_data|Selector257~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X32_Y6_N11
dffeas \A_SPW_TOP|rx_data|mem[26][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector257~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[26][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[26][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[26][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y6_N39
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector266~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector266~0_combout  = ( \A_SPW_TOP|rx_data|mem[27][4]~q  & ( (!\A_SPW_TOP|rx_data|Selector262~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [4])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux4~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[27][4]~q  & ( (\A_SPW_TOP|rx_data|Selector262~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [4])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux4~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .datab(!\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector262~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[27][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector266~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector266~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector266~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|rx_data|Selector266~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y6_N53
dffeas \A_SPW_TOP|rx_data|mem[27][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector266~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[27][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[27][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[27][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X33_Y6_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux4~6 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux4~6_combout  = ( \A_SPW_TOP|rx_data|mem[27][4]~q  & ( \A_SPW_TOP|rx_data|wr_ptr [1] & ( (\A_SPW_TOP|rx_data|mem[26][4]~q ) # (\A_SPW_TOP|rx_data|wr_ptr [0]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[27][4]~q  & ( \A_SPW_TOP|rx_data|wr_ptr 
// [1] & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & \A_SPW_TOP|rx_data|mem[26][4]~q ) ) ) ) # ( \A_SPW_TOP|rx_data|mem[27][4]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [1] & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & ((\A_SPW_TOP|rx_data|mem[24][4]~q ))) # 
// (\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|mem[25][4]~q )) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[27][4]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [1] & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & ((\A_SPW_TOP|rx_data|mem[24][4]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr 
// [0] & (\A_SPW_TOP|rx_data|mem[25][4]~q )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datab(!\A_SPW_TOP|rx_data|mem[25][4]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[24][4]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[26][4]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[27][4]~q ),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux4~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux4~6 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux4~6 .lut_mask = 64'h1B1B1B1B00AA55FF;
defparam \A_SPW_TOP|rx_data|Mux4~6 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y6_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux4~9 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux4~9_combout  = ( \A_SPW_TOP|rx_data|Mux4~6_combout  & ( \A_SPW_TOP|rx_data|wr_ptr [3] & ( (!\A_SPW_TOP|rx_data|wr_ptr [5]) # (\A_SPW_TOP|rx_data|Mux4~8_combout ) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux4~6_combout  & ( 
// \A_SPW_TOP|rx_data|wr_ptr [3] & ( (\A_SPW_TOP|rx_data|wr_ptr [5] & \A_SPW_TOP|rx_data|Mux4~8_combout ) ) ) ) # ( \A_SPW_TOP|rx_data|Mux4~6_combout  & ( !\A_SPW_TOP|rx_data|wr_ptr [3] & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & 
// ((\A_SPW_TOP|rx_data|Mux4~5_combout ))) # (\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|Mux4~7_combout )) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux4~6_combout  & ( !\A_SPW_TOP|rx_data|wr_ptr [3] & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & 
// ((\A_SPW_TOP|rx_data|Mux4~5_combout ))) # (\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|Mux4~7_combout )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datab(!\A_SPW_TOP|rx_data|Mux4~7_combout ),
        .datac(!\A_SPW_TOP|rx_data|Mux4~8_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux4~5_combout ),
        .datae(!\A_SPW_TOP|rx_data|Mux4~6_combout ),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux4~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux4~9 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux4~9 .lut_mask = 64'h11BB11BB0505AFAF;
defparam \A_SPW_TOP|rx_data|Mux4~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X35_Y6_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector113~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector113~0_combout  = ( \A_SPW_TOP|rx_data|Selector109~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [4])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux4~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector109~0_combout  & ( \A_SPW_TOP|rx_data|mem[10][4]~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .datab(!\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|mem[10][4]~q ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector109~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector113~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector113~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector113~0 .lut_mask = 64'h0F0F0F0F55335533;
defparam \A_SPW_TOP|rx_data|Selector113~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X35_Y6_N23
dffeas \A_SPW_TOP|rx_data|mem[10][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector113~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[10][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[10][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[10][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X35_Y6_N9
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector104~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector104~0_combout  = ( \A_SPW_TOP|rx_data|mem[9][4]~q  & ( (!\A_SPW_TOP|rx_data|Selector100~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [4]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux4~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[9][4]~q  & ( (\A_SPW_TOP|rx_data|Selector100~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [4]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux4~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector100~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[9][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector104~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector104~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector104~0 .lut_mask = 64'h010B010BF1FBF1FB;
defparam \A_SPW_TOP|rx_data|Selector104~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X35_Y6_N14
dffeas \A_SPW_TOP|rx_data|mem[9][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector104~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[9][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[9][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[9][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X35_Y6_N39
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector122~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector122~0_combout  = ( \A_SPW_TOP|rx_data|mem[11][4]~q  & ( (!\A_SPW_TOP|rx_data|Selector118~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [4])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux4~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[11][4]~q  & ( (\A_SPW_TOP|rx_data|Selector118~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [4])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux4~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .datab(!\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|Selector118~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[11][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector122~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector122~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector122~0 .lut_mask = 64'h00530053FF53FF53;
defparam \A_SPW_TOP|rx_data|Selector122~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X35_Y6_N50
dffeas \A_SPW_TOP|rx_data|mem[11][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector122~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[11][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[11][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[11][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X35_Y6_N45
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector95~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector95~0_combout  = ( \A_SPW_TOP|rx_data|mem[8][4]~q  & ( (!\A_SPW_TOP|rx_data|Selector91~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [4])) # (\A_SPW_TOP|rx_data|state_data_write.00~q 
//  & ((\A_SPW_TOP|rx_data|Mux4~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[8][4]~q  & ( (\A_SPW_TOP|rx_data|Selector91~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [4])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux4~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .datab(!\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector91~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[8][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector95~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector95~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector95~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|rx_data|Selector95~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X35_Y6_N35
dffeas \A_SPW_TOP|rx_data|mem[8][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector95~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[8][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[8][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[8][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X35_Y6_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux4~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux4~1_combout  = ( \A_SPW_TOP|rx_data|mem[11][4]~q  & ( \A_SPW_TOP|rx_data|mem[8][4]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & (((!\A_SPW_TOP|rx_data|wr_ptr [1])) # (\A_SPW_TOP|rx_data|mem[10][4]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & 
// (((\A_SPW_TOP|rx_data|wr_ptr [1]) # (\A_SPW_TOP|rx_data|mem[9][4]~q )))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[11][4]~q  & ( \A_SPW_TOP|rx_data|mem[8][4]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & (((!\A_SPW_TOP|rx_data|wr_ptr [1])) # 
// (\A_SPW_TOP|rx_data|mem[10][4]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & (((\A_SPW_TOP|rx_data|mem[9][4]~q  & !\A_SPW_TOP|rx_data|wr_ptr [1])))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[11][4]~q  & ( !\A_SPW_TOP|rx_data|mem[8][4]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr 
// [0] & (\A_SPW_TOP|rx_data|mem[10][4]~q  & ((\A_SPW_TOP|rx_data|wr_ptr [1])))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & (((\A_SPW_TOP|rx_data|wr_ptr [1]) # (\A_SPW_TOP|rx_data|mem[9][4]~q )))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[11][4]~q  & ( 
// !\A_SPW_TOP|rx_data|mem[8][4]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|mem[10][4]~q  & ((\A_SPW_TOP|rx_data|wr_ptr [1])))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & (((\A_SPW_TOP|rx_data|mem[9][4]~q  & !\A_SPW_TOP|rx_data|wr_ptr [1])))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[10][4]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[9][4]~q ),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datae(!\A_SPW_TOP|rx_data|mem[11][4]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[8][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux4~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux4~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux4~1 .lut_mask = 64'h0350035FF350F35F;
defparam \A_SPW_TOP|rx_data|Mux4~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y5_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector338~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector338~0_combout  = ( \A_SPW_TOP|SPW|RX|rx_data_flag [4] & ( (!\A_SPW_TOP|rx_data|Selector334~0_combout  & (((\A_SPW_TOP|rx_data|mem[35][4]~q )))) # (\A_SPW_TOP|rx_data|Selector334~0_combout  & 
// ((!\A_SPW_TOP|rx_data|state_data_write.00~q ) # ((\A_SPW_TOP|rx_data|Mux4~20_combout )))) ) ) # ( !\A_SPW_TOP|SPW|RX|rx_data_flag [4] & ( (!\A_SPW_TOP|rx_data|Selector334~0_combout  & (((\A_SPW_TOP|rx_data|mem[35][4]~q )))) # 
// (\A_SPW_TOP|rx_data|Selector334~0_combout  & (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux4~20_combout ))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|mem[35][4]~q ),
        .datad(!\A_SPW_TOP|rx_data|Selector334~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector338~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector338~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector338~0 .lut_mask = 64'h0F110F110FBB0FBB;
defparam \A_SPW_TOP|rx_data|Selector338~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y5_N5
dffeas \A_SPW_TOP|rx_data|mem[35][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector338~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[35][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[35][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[35][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y5_N27
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector311~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector311~0_combout  = ( \A_SPW_TOP|rx_data|Selector307~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [4]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux4~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector307~0_combout  & ( \A_SPW_TOP|rx_data|mem[32][4]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .datac(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .datad(!\A_SPW_TOP|rx_data|mem[32][4]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector307~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector311~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector311~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector311~0 .lut_mask = 64'h00FF00FF1B1B1B1B;
defparam \A_SPW_TOP|rx_data|Selector311~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y5_N35
dffeas \A_SPW_TOP|rx_data|mem[32][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector311~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[32][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[32][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[32][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y5_N9
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector320~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector320~0_combout  = ( \A_SPW_TOP|rx_data|Selector316~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [4])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux4~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector316~0_combout  & ( \A_SPW_TOP|rx_data|mem[33][4]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .datac(!\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[33][4]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector316~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector320~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector320~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector320~0 .lut_mask = 64'h00FF00FF27272727;
defparam \A_SPW_TOP|rx_data|Selector320~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y5_N23
dffeas \A_SPW_TOP|rx_data|mem[33][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector320~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[33][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[33][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[33][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y6_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector329~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector329~0_combout  = ( \A_SPW_TOP|rx_data|Selector325~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [4])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux4~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector325~0_combout  & ( \A_SPW_TOP|rx_data|mem[34][4]~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .datab(!\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|mem[34][4]~q ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector325~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector329~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector329~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector329~0 .lut_mask = 64'h0F0F0F0F55335533;
defparam \A_SPW_TOP|rx_data|Selector329~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y6_N5
dffeas \A_SPW_TOP|rx_data|mem[34][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector329~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[34][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[34][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[34][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y5_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux4~2 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux4~2_combout  = ( \A_SPW_TOP|rx_data|mem[33][4]~q  & ( \A_SPW_TOP|rx_data|mem[34][4]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & (((\A_SPW_TOP|rx_data|wr_ptr [0]) # (\A_SPW_TOP|rx_data|mem[32][4]~q )))) # (\A_SPW_TOP|rx_data|wr_ptr [1] & 
// (((!\A_SPW_TOP|rx_data|wr_ptr [0])) # (\A_SPW_TOP|rx_data|mem[35][4]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[33][4]~q  & ( \A_SPW_TOP|rx_data|mem[34][4]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & (((\A_SPW_TOP|rx_data|mem[32][4]~q  & 
// !\A_SPW_TOP|rx_data|wr_ptr [0])))) # (\A_SPW_TOP|rx_data|wr_ptr [1] & (((!\A_SPW_TOP|rx_data|wr_ptr [0])) # (\A_SPW_TOP|rx_data|mem[35][4]~q ))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[33][4]~q  & ( !\A_SPW_TOP|rx_data|mem[34][4]~q  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [1] & (((\A_SPW_TOP|rx_data|wr_ptr [0]) # (\A_SPW_TOP|rx_data|mem[32][4]~q )))) # (\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|mem[35][4]~q  & ((\A_SPW_TOP|rx_data|wr_ptr [0])))) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|mem[33][4]~q  & ( !\A_SPW_TOP|rx_data|mem[34][4]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & (((\A_SPW_TOP|rx_data|mem[32][4]~q  & !\A_SPW_TOP|rx_data|wr_ptr [0])))) # (\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|mem[35][4]~q  & 
// ((\A_SPW_TOP|rx_data|wr_ptr [0])))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datab(!\A_SPW_TOP|rx_data|mem[35][4]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[32][4]~q ),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datae(!\A_SPW_TOP|rx_data|mem[33][4]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[34][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux4~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux4~2 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux4~2 .lut_mask = 64'h0A110ABB5F115FBB;
defparam \A_SPW_TOP|rx_data|Mux4~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y6_N21
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector50~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector50~0_combout  = ( \A_SPW_TOP|rx_data|mem[3][4]~q  & ( (!\A_SPW_TOP|rx_data|Selector46~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [4]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux4~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[3][4]~q  & ( (\A_SPW_TOP|rx_data|Selector46~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [4]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux4~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .datac(!\A_SPW_TOP|rx_data|Selector46~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[3][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector50~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector50~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector50~0 .lut_mask = 64'h03050305F3F5F3F5;
defparam \A_SPW_TOP|rx_data|Selector50~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y6_N41
dffeas \A_SPW_TOP|rx_data|mem[3][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector50~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[3][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[3][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[3][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y6_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector23~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector23~0_combout  = ( \A_SPW_TOP|rx_data|mem[0][4]~q  & ( (!\A_SPW_TOP|rx_data|Selector19~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [4]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux4~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[0][4]~q  & ( (\A_SPW_TOP|rx_data|Selector19~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [4]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux4~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|Selector19~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[0][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector23~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector23~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector23~0 .lut_mask = 64'h00350035FF35FF35;
defparam \A_SPW_TOP|rx_data|Selector23~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y6_N53
dffeas \A_SPW_TOP|rx_data|mem[0][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector23~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[0][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[0][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[0][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y5_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector32~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector32~0_combout  = ( \A_SPW_TOP|rx_data|mem[1][4]~q  & ( (!\A_SPW_TOP|rx_data|Selector28~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [4])) # (\A_SPW_TOP|rx_data|state_data_write.00~q 
//  & ((\A_SPW_TOP|rx_data|Mux4~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[1][4]~q  & ( (\A_SPW_TOP|rx_data|Selector28~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [4])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux4~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Selector28~0_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .datae(!\A_SPW_TOP|rx_data|mem[1][4]~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector32~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector32~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector32~0 .lut_mask = 64'h1015BABF1015BABF;
defparam \A_SPW_TOP|rx_data|Selector32~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y5_N47
dffeas \A_SPW_TOP|rx_data|mem[1][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector32~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[1][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[1][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[1][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y6_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector41~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector41~0_combout  = ( \A_SPW_TOP|rx_data|Selector37~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [4]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux4~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector37~0_combout  & ( \A_SPW_TOP|rx_data|mem[2][4]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .datac(!\A_SPW_TOP|rx_data|mem[2][4]~q ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector37~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector41~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector41~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector41~0 .lut_mask = 64'h0F0F0F0F33553355;
defparam \A_SPW_TOP|rx_data|Selector41~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y6_N17
dffeas \A_SPW_TOP|rx_data|mem[2][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector41~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[2][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[2][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[2][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y6_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux4~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux4~0_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [1] & ( \A_SPW_TOP|rx_data|mem[2][4]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [0]) # (\A_SPW_TOP|rx_data|mem[3][4]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [1] & ( \A_SPW_TOP|rx_data|mem[2][4]~q  
// & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|mem[0][4]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [0] & ((\A_SPW_TOP|rx_data|mem[1][4]~q ))) ) ) ) # ( \A_SPW_TOP|rx_data|wr_ptr [1] & ( !\A_SPW_TOP|rx_data|mem[2][4]~q  & ( (\A_SPW_TOP|rx_data|wr_ptr 
// [0] & \A_SPW_TOP|rx_data|mem[3][4]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [1] & ( !\A_SPW_TOP|rx_data|mem[2][4]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|mem[0][4]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [0] & 
// ((\A_SPW_TOP|rx_data|mem[1][4]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datab(!\A_SPW_TOP|rx_data|mem[3][4]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[0][4]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[1][4]~q ),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .dataf(!\A_SPW_TOP|rx_data|mem[2][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux4~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux4~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux4~0 .lut_mask = 64'h0A5F11110A5FBBBB;
defparam \A_SPW_TOP|rx_data|Mux4~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X31_Y5_N57
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector392~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector392~0_combout  = ( \A_SPW_TOP|rx_data|mem[41][4]~q  & ( (!\A_SPW_TOP|rx_data|Selector388~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [4]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux4~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[41][4]~q  & ( (\A_SPW_TOP|rx_data|Selector388~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [4]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux4~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector388~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[41][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector392~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector392~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector392~0 .lut_mask = 64'h010B010BF1FBF1FB;
defparam \A_SPW_TOP|rx_data|Selector392~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y5_N41
dffeas \A_SPW_TOP|rx_data|mem[41][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector392~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[41][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[41][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[41][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X33_Y6_N39
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector401~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector401~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector397~0_combout  & ((\A_SPW_TOP|rx_data|mem[42][4]~q ))) # (\A_SPW_TOP|rx_data|Selector397~0_combout  & 
// (\A_SPW_TOP|rx_data|Mux4~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector397~0_combout  & ((\A_SPW_TOP|rx_data|mem[42][4]~q ))) # (\A_SPW_TOP|rx_data|Selector397~0_combout  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [4])) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .datab(!\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector397~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[42][4]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector401~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector401~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector401~0 .lut_mask = 64'h05F505F503F303F3;
defparam \A_SPW_TOP|rx_data|Selector401~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X33_Y6_N47
dffeas \A_SPW_TOP|rx_data|mem[42][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector401~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[42][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[42][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[42][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y5_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector410~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector410~0_combout  = ( \A_SPW_TOP|SPW|RX|rx_data_flag [4] & ( (!\A_SPW_TOP|rx_data|Selector406~0_combout  & (((\A_SPW_TOP|rx_data|mem[43][4]~q )))) # (\A_SPW_TOP|rx_data|Selector406~0_combout  & 
// ((!\A_SPW_TOP|rx_data|state_data_write.00~q ) # ((\A_SPW_TOP|rx_data|Mux4~20_combout )))) ) ) # ( !\A_SPW_TOP|SPW|RX|rx_data_flag [4] & ( (!\A_SPW_TOP|rx_data|Selector406~0_combout  & (((\A_SPW_TOP|rx_data|mem[43][4]~q )))) # 
// (\A_SPW_TOP|rx_data|Selector406~0_combout  & (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux4~20_combout ))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|mem[43][4]~q ),
        .datad(!\A_SPW_TOP|rx_data|Selector406~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector410~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector410~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector410~0 .lut_mask = 64'h0F110F110FBB0FBB;
defparam \A_SPW_TOP|rx_data|Selector410~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y5_N56
dffeas \A_SPW_TOP|rx_data|mem[43][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector410~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[43][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[43][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[43][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X33_Y6_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector383~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector383~0_combout  = ( \A_SPW_TOP|rx_data|Selector379~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [4])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux4~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector379~0_combout  & ( \A_SPW_TOP|rx_data|mem[40][4]~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .datab(!\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|mem[40][4]~q ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector379~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector383~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector383~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector383~0 .lut_mask = 64'h0F0F0F0F55335533;
defparam \A_SPW_TOP|rx_data|Selector383~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X33_Y6_N23
dffeas \A_SPW_TOP|rx_data|mem[40][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector383~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[40][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[40][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[40][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y5_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux4~3 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux4~3_combout  = ( \A_SPW_TOP|rx_data|mem[43][4]~q  & ( \A_SPW_TOP|rx_data|mem[40][4]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & ((!\A_SPW_TOP|rx_data|wr_ptr [0]) # ((\A_SPW_TOP|rx_data|mem[41][4]~q )))) # (\A_SPW_TOP|rx_data|wr_ptr [1] 
// & (((\A_SPW_TOP|rx_data|mem[42][4]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [0]))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[43][4]~q  & ( \A_SPW_TOP|rx_data|mem[40][4]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & ((!\A_SPW_TOP|rx_data|wr_ptr [0]) # 
// ((\A_SPW_TOP|rx_data|mem[41][4]~q )))) # (\A_SPW_TOP|rx_data|wr_ptr [1] & (!\A_SPW_TOP|rx_data|wr_ptr [0] & ((\A_SPW_TOP|rx_data|mem[42][4]~q )))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[43][4]~q  & ( !\A_SPW_TOP|rx_data|mem[40][4]~q  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|mem[41][4]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [1] & (((\A_SPW_TOP|rx_data|mem[42][4]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [0]))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[43][4]~q 
//  & ( !\A_SPW_TOP|rx_data|mem[40][4]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|mem[41][4]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [1] & (!\A_SPW_TOP|rx_data|wr_ptr [0] & ((\A_SPW_TOP|rx_data|mem[42][4]~q )))) 
// ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datac(!\A_SPW_TOP|rx_data|mem[41][4]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[42][4]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[43][4]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[40][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux4~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux4~3 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux4~3 .lut_mask = 64'h024613578ACE9BDF;
defparam \A_SPW_TOP|rx_data|Mux4~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y6_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux4~4 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux4~4_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [5] & ( \A_SPW_TOP|rx_data|Mux4~3_combout  & ( (\A_SPW_TOP|rx_data|wr_ptr [3]) # (\A_SPW_TOP|rx_data|Mux4~2_combout ) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [5] & ( 
// \A_SPW_TOP|rx_data|Mux4~3_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [3] & ((\A_SPW_TOP|rx_data|Mux4~0_combout ))) # (\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|Mux4~1_combout )) ) ) ) # ( \A_SPW_TOP|rx_data|wr_ptr [5] & ( 
// !\A_SPW_TOP|rx_data|Mux4~3_combout  & ( (\A_SPW_TOP|rx_data|Mux4~2_combout  & !\A_SPW_TOP|rx_data|wr_ptr [3]) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [5] & ( !\A_SPW_TOP|rx_data|Mux4~3_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [3] & 
// ((\A_SPW_TOP|rx_data|Mux4~0_combout ))) # (\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|Mux4~1_combout )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux4~1_combout ),
        .datab(!\A_SPW_TOP|rx_data|Mux4~2_combout ),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datad(!\A_SPW_TOP|rx_data|Mux4~0_combout ),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .dataf(!\A_SPW_TOP|rx_data|Mux4~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux4~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux4~4 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux4~4 .lut_mask = 64'h05F5303005F53F3F;
defparam \A_SPW_TOP|rx_data|Mux4~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y5_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector356~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector356~0_combout  = ( \A_SPW_TOP|rx_data|Selector352~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [4])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux4~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector352~0_combout  & ( \A_SPW_TOP|rx_data|mem[37][4]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .datac(!\A_SPW_TOP|rx_data|mem[37][4]~q ),
        .datad(!\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector352~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector356~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector356~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector356~0 .lut_mask = 64'h0F0F0F0F22772277;
defparam \A_SPW_TOP|rx_data|Selector356~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y5_N38
dffeas \A_SPW_TOP|rx_data|mem[37][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector356~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[37][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[37][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[37][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y5_N57
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector347~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector347~0_combout  = ( \A_SPW_TOP|rx_data|Mux4~20_combout  & ( (!\A_SPW_TOP|rx_data|Selector343~0_combout  & (((\A_SPW_TOP|rx_data|mem[36][4]~q )))) # (\A_SPW_TOP|rx_data|Selector343~0_combout  & (((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [4])) # (\A_SPW_TOP|rx_data|state_data_write.00~q ))) ) ) # ( !\A_SPW_TOP|rx_data|Mux4~20_combout  & ( (!\A_SPW_TOP|rx_data|Selector343~0_combout  & (((\A_SPW_TOP|rx_data|mem[36][4]~q )))) # (\A_SPW_TOP|rx_data|Selector343~0_combout  & 
// (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [4])))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[36][4]~q ),
        .datac(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .datad(!\A_SPW_TOP|rx_data|Selector343~0_combout ),
        .datae(!\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector347~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector347~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector347~0 .lut_mask = 64'h330A335F330A335F;
defparam \A_SPW_TOP|rx_data|Selector347~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y5_N41
dffeas \A_SPW_TOP|rx_data|mem[36][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector347~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[36][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[36][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[36][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y5_N45
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector374~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector374~0_combout  = ( \A_SPW_TOP|rx_data|mem[39][4]~q  & ( (!\A_SPW_TOP|rx_data|Selector370~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [4])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux4~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[39][4]~q  & ( (\A_SPW_TOP|rx_data|Selector370~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [4])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux4~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .datac(!\A_SPW_TOP|rx_data|Selector370~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[39][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector374~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector374~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector374~0 .lut_mask = 64'h02070207F2F7F2F7;
defparam \A_SPW_TOP|rx_data|Selector374~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y5_N50
dffeas \A_SPW_TOP|rx_data|mem[39][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector374~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[39][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[39][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[39][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y5_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector365~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector365~0_combout  = ( \A_SPW_TOP|rx_data|Selector361~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [4])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux4~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector361~0_combout  & ( \A_SPW_TOP|rx_data|mem[38][4]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .datac(!\A_SPW_TOP|rx_data|mem[38][4]~q ),
        .datad(!\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector361~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector365~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector365~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector365~0 .lut_mask = 64'h0F0F0F0F22772277;
defparam \A_SPW_TOP|rx_data|Selector365~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y5_N20
dffeas \A_SPW_TOP|rx_data|mem[38][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector365~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[38][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[38][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[38][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y5_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux4~12 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux4~12_combout  = ( \A_SPW_TOP|rx_data|mem[39][4]~q  & ( \A_SPW_TOP|rx_data|mem[38][4]~q  & ( ((!\A_SPW_TOP|rx_data|wr_ptr [0] & ((\A_SPW_TOP|rx_data|mem[36][4]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|mem[37][4]~q 
// ))) # (\A_SPW_TOP|rx_data|wr_ptr [1]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[39][4]~q  & ( \A_SPW_TOP|rx_data|mem[38][4]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & ((!\A_SPW_TOP|rx_data|wr_ptr [0] & ((\A_SPW_TOP|rx_data|mem[36][4]~q ))) # 
// (\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|mem[37][4]~q )))) # (\A_SPW_TOP|rx_data|wr_ptr [1] & (((!\A_SPW_TOP|rx_data|wr_ptr [0])))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[39][4]~q  & ( !\A_SPW_TOP|rx_data|mem[38][4]~q  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [1] & ((!\A_SPW_TOP|rx_data|wr_ptr [0] & ((\A_SPW_TOP|rx_data|mem[36][4]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|mem[37][4]~q )))) # (\A_SPW_TOP|rx_data|wr_ptr [1] & (((\A_SPW_TOP|rx_data|wr_ptr [0])))) ) ) 
// ) # ( !\A_SPW_TOP|rx_data|mem[39][4]~q  & ( !\A_SPW_TOP|rx_data|mem[38][4]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & ((!\A_SPW_TOP|rx_data|wr_ptr [0] & ((\A_SPW_TOP|rx_data|mem[36][4]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & 
// (\A_SPW_TOP|rx_data|mem[37][4]~q )))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[37][4]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[36][4]~q ),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datae(!\A_SPW_TOP|rx_data|mem[39][4]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[38][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux4~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux4~12 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux4~12 .lut_mask = 64'h3050305F3F503F5F;
defparam \A_SPW_TOP|rx_data|Mux4~12 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y5_N15
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector437~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector437~0_combout  = ( \A_SPW_TOP|rx_data|Selector433~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [4]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux4~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector433~0_combout  & ( \A_SPW_TOP|rx_data|mem[46][4]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .datac(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .datad(!\A_SPW_TOP|rx_data|mem[46][4]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector433~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector437~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector437~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector437~0 .lut_mask = 64'h00FF00FF1B1B1B1B;
defparam \A_SPW_TOP|rx_data|Selector437~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y5_N53
dffeas \A_SPW_TOP|rx_data|mem[46][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector437~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[46][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[46][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[46][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y5_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector419~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector419~0_combout  = ( \A_SPW_TOP|rx_data|mem[44][4]~q  & ( (!\A_SPW_TOP|rx_data|Selector415~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [4]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux4~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[44][4]~q  & ( (\A_SPW_TOP|rx_data|Selector415~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [4]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux4~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector415~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[44][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector419~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector419~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector419~0 .lut_mask = 64'h010B010BF1FBF1FB;
defparam \A_SPW_TOP|rx_data|Selector419~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y5_N17
dffeas \A_SPW_TOP|rx_data|mem[44][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector419~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[44][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[44][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[44][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y5_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector428~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector428~0_combout  = ( \A_SPW_TOP|rx_data|mem[45][4]~q  & ( (!\A_SPW_TOP|rx_data|Selector424~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [4])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux4~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[45][4]~q  & ( (\A_SPW_TOP|rx_data|Selector424~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [4])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux4~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .datac(!\A_SPW_TOP|rx_data|Selector424~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[45][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector428~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector428~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector428~0 .lut_mask = 64'h02070207F2F7F2F7;
defparam \A_SPW_TOP|rx_data|Selector428~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y5_N11
dffeas \A_SPW_TOP|rx_data|mem[45][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector428~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[45][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[45][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[45][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y5_N21
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector446~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector446~0_combout  = ( \A_SPW_TOP|rx_data|mem[47][4]~q  & ( (!\A_SPW_TOP|rx_data|Selector442~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [4])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux4~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[47][4]~q  & ( (\A_SPW_TOP|rx_data|Selector442~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [4])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux4~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .datac(!\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .datad(!\A_SPW_TOP|rx_data|Selector442~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[47][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector446~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector446~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector446~0 .lut_mask = 64'h00270027FF27FF27;
defparam \A_SPW_TOP|rx_data|Selector446~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y5_N32
dffeas \A_SPW_TOP|rx_data|mem[47][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector446~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[47][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[47][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[47][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y5_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux4~13 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux4~13_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [0] & ( \A_SPW_TOP|rx_data|mem[47][4]~q  & ( (\A_SPW_TOP|rx_data|mem[45][4]~q ) # (\A_SPW_TOP|rx_data|wr_ptr [1]) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [0] & ( 
// \A_SPW_TOP|rx_data|mem[47][4]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & ((\A_SPW_TOP|rx_data|mem[44][4]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|mem[46][4]~q )) ) ) ) # ( \A_SPW_TOP|rx_data|wr_ptr [0] & ( 
// !\A_SPW_TOP|rx_data|mem[47][4]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & \A_SPW_TOP|rx_data|mem[45][4]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [0] & ( !\A_SPW_TOP|rx_data|mem[47][4]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & 
// ((\A_SPW_TOP|rx_data|mem[44][4]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|mem[46][4]~q )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[46][4]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[44][4]~q ),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datad(!\A_SPW_TOP|rx_data|mem[45][4]~q ),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .dataf(!\A_SPW_TOP|rx_data|mem[47][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux4~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux4~13 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux4~13 .lut_mask = 64'h353500F035350FFF;
defparam \A_SPW_TOP|rx_data|Mux4~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X36_Y6_N57
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector140~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector140~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( \A_SPW_TOP|rx_data|Mux4~20_combout  & ( (\A_SPW_TOP|rx_data|mem[13][4]~q ) # (\A_SPW_TOP|rx_data|Selector136~0_combout ) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( \A_SPW_TOP|rx_data|Mux4~20_combout  & ( (!\A_SPW_TOP|rx_data|Selector136~0_combout  & (\A_SPW_TOP|rx_data|mem[13][4]~q )) # (\A_SPW_TOP|rx_data|Selector136~0_combout  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [4]))) 
// ) ) ) # ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( !\A_SPW_TOP|rx_data|Mux4~20_combout  & ( (!\A_SPW_TOP|rx_data|Selector136~0_combout  & \A_SPW_TOP|rx_data|mem[13][4]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( 
// !\A_SPW_TOP|rx_data|Mux4~20_combout  & ( (!\A_SPW_TOP|rx_data|Selector136~0_combout  & (\A_SPW_TOP|rx_data|mem[13][4]~q )) # (\A_SPW_TOP|rx_data|Selector136~0_combout  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [4]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Selector136~0_combout ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|rx_data|mem[13][4]~q ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .datae(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .dataf(!\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector140~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector140~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector140~0 .lut_mask = 64'h0A5F0A0A0A5F5F5F;
defparam \A_SPW_TOP|rx_data|Selector140~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X35_Y6_N26
dffeas \A_SPW_TOP|rx_data|mem[13][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector140~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[13][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[13][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[13][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X35_Y6_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector149~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector149~0_combout  = ( \A_SPW_TOP|rx_data|mem[14][4]~q  & ( (!\A_SPW_TOP|rx_data|Selector145~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [4])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux4~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[14][4]~q  & ( (\A_SPW_TOP|rx_data|Selector145~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [4])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux4~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .datab(!\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector145~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[14][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector149~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector149~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector149~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|rx_data|Selector149~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X35_Y6_N53
dffeas \A_SPW_TOP|rx_data|mem[14][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector149~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[14][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[14][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[14][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X35_Y6_N57
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector158~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector158~0_combout  = ( \A_SPW_TOP|rx_data|Selector154~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [4])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux4~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector154~0_combout  & ( \A_SPW_TOP|rx_data|mem[15][4]~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .datab(!\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[15][4]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector154~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector158~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector158~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector158~0 .lut_mask = 64'h00FF00FF53535353;
defparam \A_SPW_TOP|rx_data|Selector158~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X35_Y6_N29
dffeas \A_SPW_TOP|rx_data|mem[15][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector158~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[15][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[15][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[15][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X35_Y6_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector131~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector131~0_combout  = ( \A_SPW_TOP|rx_data|mem[12][4]~q  & ( (!\A_SPW_TOP|rx_data|Selector127~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [4]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux4~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[12][4]~q  & ( (\A_SPW_TOP|rx_data|Selector127~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [4]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux4~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .datac(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .datad(!\A_SPW_TOP|rx_data|Selector127~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[12][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector131~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector131~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector131~0 .lut_mask = 64'h001B001BFF1BFF1B;
defparam \A_SPW_TOP|rx_data|Selector131~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X35_Y6_N17
dffeas \A_SPW_TOP|rx_data|mem[12][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector131~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[12][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[12][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[12][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X35_Y6_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux4~11 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux4~11_combout  = ( \A_SPW_TOP|rx_data|mem[15][4]~q  & ( \A_SPW_TOP|rx_data|mem[12][4]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & (((!\A_SPW_TOP|rx_data|wr_ptr [1]) # (\A_SPW_TOP|rx_data|mem[14][4]~q )))) # (\A_SPW_TOP|rx_data|wr_ptr [0] 
// & (((\A_SPW_TOP|rx_data|wr_ptr [1])) # (\A_SPW_TOP|rx_data|mem[13][4]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[15][4]~q  & ( \A_SPW_TOP|rx_data|mem[12][4]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & (((!\A_SPW_TOP|rx_data|wr_ptr [1]) # 
// (\A_SPW_TOP|rx_data|mem[14][4]~q )))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|mem[13][4]~q  & ((!\A_SPW_TOP|rx_data|wr_ptr [1])))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[15][4]~q  & ( !\A_SPW_TOP|rx_data|mem[12][4]~q  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [0] & (((\A_SPW_TOP|rx_data|mem[14][4]~q  & \A_SPW_TOP|rx_data|wr_ptr [1])))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & (((\A_SPW_TOP|rx_data|wr_ptr [1])) # (\A_SPW_TOP|rx_data|mem[13][4]~q ))) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|mem[15][4]~q  & ( !\A_SPW_TOP|rx_data|mem[12][4]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & (((\A_SPW_TOP|rx_data|mem[14][4]~q  & \A_SPW_TOP|rx_data|wr_ptr [1])))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|mem[13][4]~q  & 
// ((!\A_SPW_TOP|rx_data|wr_ptr [1])))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[13][4]~q ),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datac(!\A_SPW_TOP|rx_data|mem[14][4]~q ),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datae(!\A_SPW_TOP|rx_data|mem[15][4]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[12][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux4~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux4~11 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux4~11 .lut_mask = 64'h110C113FDD0CDD3F;
defparam \A_SPW_TOP|rx_data|Mux4~11 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y6_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector86~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector86~0_combout  = ( \A_SPW_TOP|SPW|RX|rx_data_flag [4] & ( (!\A_SPW_TOP|rx_data|Selector82~0_combout  & (((\A_SPW_TOP|rx_data|mem[7][4]~q )))) # (\A_SPW_TOP|rx_data|Selector82~0_combout  & 
// ((!\A_SPW_TOP|rx_data|state_data_write.00~q ) # ((\A_SPW_TOP|rx_data|Mux4~20_combout )))) ) ) # ( !\A_SPW_TOP|SPW|RX|rx_data_flag [4] & ( (!\A_SPW_TOP|rx_data|Selector82~0_combout  & (((\A_SPW_TOP|rx_data|mem[7][4]~q )))) # 
// (\A_SPW_TOP|rx_data|Selector82~0_combout  & (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux4~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[7][4]~q ),
        .datac(!\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .datad(!\A_SPW_TOP|rx_data|Selector82~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector86~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector86~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector86~0 .lut_mask = 64'h3305330533AF33AF;
defparam \A_SPW_TOP|rx_data|Selector86~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y6_N47
dffeas \A_SPW_TOP|rx_data|mem[7][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector86~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[7][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[7][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[7][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y6_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector77~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector77~0_combout  = ( \A_SPW_TOP|rx_data|mem[6][4]~q  & ( (!\A_SPW_TOP|rx_data|Selector73~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [4]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux4~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[6][4]~q  & ( (\A_SPW_TOP|rx_data|Selector73~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [4]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux4~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|Selector73~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[6][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector77~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector77~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector77~0 .lut_mask = 64'h00350035FF35FF35;
defparam \A_SPW_TOP|rx_data|Selector77~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y6_N11
dffeas \A_SPW_TOP|rx_data|mem[6][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector77~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[6][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[6][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[6][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y6_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector59~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector59~0_combout  = ( \A_SPW_TOP|rx_data|Selector55~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [4]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux4~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector55~0_combout  & ( \A_SPW_TOP|rx_data|mem[4][4]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .datac(!\A_SPW_TOP|rx_data|mem[4][4]~q ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector55~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector59~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector59~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector59~0 .lut_mask = 64'h0F0F0F0F33553355;
defparam \A_SPW_TOP|rx_data|Selector59~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y6_N29
dffeas \A_SPW_TOP|rx_data|mem[4][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector59~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[4][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[4][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[4][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y6_N57
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector68~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector68~0_combout  = ( \A_SPW_TOP|rx_data|mem[5][4]~q  & ( (!\A_SPW_TOP|rx_data|Selector64~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [4]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux4~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[5][4]~q  & ( (\A_SPW_TOP|rx_data|Selector64~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [4]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux4~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .datac(!\A_SPW_TOP|rx_data|Selector64~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[5][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector68~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector68~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector68~0 .lut_mask = 64'h03050305F3F5F3F5;
defparam \A_SPW_TOP|rx_data|Selector68~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y6_N35
dffeas \A_SPW_TOP|rx_data|mem[5][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector68~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[5][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[5][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[5][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y6_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux4~10 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux4~10_combout  = ( \A_SPW_TOP|rx_data|mem[4][4]~q  & ( \A_SPW_TOP|rx_data|mem[5][4]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [1]) # ((!\A_SPW_TOP|rx_data|wr_ptr [0] & ((\A_SPW_TOP|rx_data|mem[6][4]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & 
// (\A_SPW_TOP|rx_data|mem[7][4]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[4][4]~q  & ( \A_SPW_TOP|rx_data|mem[5][4]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & (((\A_SPW_TOP|rx_data|wr_ptr [0])))) # (\A_SPW_TOP|rx_data|wr_ptr [1] & ((!\A_SPW_TOP|rx_data|wr_ptr 
// [0] & ((\A_SPW_TOP|rx_data|mem[6][4]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|mem[7][4]~q )))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[4][4]~q  & ( !\A_SPW_TOP|rx_data|mem[5][4]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & 
// (((!\A_SPW_TOP|rx_data|wr_ptr [0])))) # (\A_SPW_TOP|rx_data|wr_ptr [1] & ((!\A_SPW_TOP|rx_data|wr_ptr [0] & ((\A_SPW_TOP|rx_data|mem[6][4]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|mem[7][4]~q )))) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|mem[4][4]~q  & ( !\A_SPW_TOP|rx_data|mem[5][4]~q  & ( (\A_SPW_TOP|rx_data|wr_ptr [1] & ((!\A_SPW_TOP|rx_data|wr_ptr [0] & ((\A_SPW_TOP|rx_data|mem[6][4]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|mem[7][4]~q )))) ) ) 
// )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datab(!\A_SPW_TOP|rx_data|mem[7][4]~q ),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datad(!\A_SPW_TOP|rx_data|mem[6][4]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[4][4]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[5][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux4~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux4~10 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux4~10 .lut_mask = 64'h0151A1F10B5BABFB;
defparam \A_SPW_TOP|rx_data|Mux4~10 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y6_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux4~14 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux4~14_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [5] & ( \A_SPW_TOP|rx_data|Mux4~10_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|Mux4~12_combout )) # (\A_SPW_TOP|rx_data|wr_ptr [3] & 
// ((\A_SPW_TOP|rx_data|Mux4~13_combout ))) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [5] & ( \A_SPW_TOP|rx_data|Mux4~10_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [3]) # (\A_SPW_TOP|rx_data|Mux4~11_combout ) ) ) ) # ( \A_SPW_TOP|rx_data|wr_ptr [5] & ( 
// !\A_SPW_TOP|rx_data|Mux4~10_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|Mux4~12_combout )) # (\A_SPW_TOP|rx_data|wr_ptr [3] & ((\A_SPW_TOP|rx_data|Mux4~13_combout ))) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [5] & ( 
// !\A_SPW_TOP|rx_data|Mux4~10_combout  & ( (\A_SPW_TOP|rx_data|wr_ptr [3] & \A_SPW_TOP|rx_data|Mux4~11_combout ) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux4~12_combout ),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datac(!\A_SPW_TOP|rx_data|Mux4~13_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux4~11_combout ),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .dataf(!\A_SPW_TOP|rx_data|Mux4~10_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux4~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux4~14 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux4~14 .lut_mask = 64'h00334747CCFF4747;
defparam \A_SPW_TOP|rx_data|Mux4~14 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y6_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux4~20 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux4~20_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [2] & ( \A_SPW_TOP|rx_data|wr_ptr [4] & ( \A_SPW_TOP|rx_data|Mux4~19_combout  ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [2] & ( \A_SPW_TOP|rx_data|wr_ptr [4] & ( 
// \A_SPW_TOP|rx_data|Mux4~9_combout  ) ) ) # ( \A_SPW_TOP|rx_data|wr_ptr [2] & ( !\A_SPW_TOP|rx_data|wr_ptr [4] & ( \A_SPW_TOP|rx_data|Mux4~14_combout  ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [2] & ( !\A_SPW_TOP|rx_data|wr_ptr [4] & ( 
// \A_SPW_TOP|rx_data|Mux4~4_combout  ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux4~19_combout ),
        .datab(!\A_SPW_TOP|rx_data|Mux4~9_combout ),
        .datac(!\A_SPW_TOP|rx_data|Mux4~4_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux4~14_combout ),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux4~20 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux4~20 .lut_mask = 64'h0F0F00FF33335555;
defparam \A_SPW_TOP|rx_data|Mux4~20 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X33_Y6_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector572~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector572~0_combout  = ( \A_SPW_TOP|rx_data|mem[61][4]~q  & ( (!\A_SPW_TOP|rx_data|Selector568~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [4])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux4~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[61][4]~q  & ( (\A_SPW_TOP|rx_data|Selector568~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [4])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux4~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Selector568~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux4~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[61][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector572~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector572~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector572~0 .lut_mask = 64'h04070407F4F7F4F7;
defparam \A_SPW_TOP|rx_data|Selector572~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X33_Y6_N8
dffeas \A_SPW_TOP|rx_data|mem[61][4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector572~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[61][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[61][4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[61][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y6_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux13~17 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux13~17_combout  = ( \A_SPW_TOP|rx_data|rd_ptr [3] & ( \A_SPW_TOP|rx_data|mem[37][4]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & ((\A_SPW_TOP|rx_data|mem[45][4]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [4] & (\A_SPW_TOP|rx_data|mem[61][4]~q )) 
// ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [3] & ( \A_SPW_TOP|rx_data|mem[37][4]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [4]) # (\A_SPW_TOP|rx_data|mem[53][4]~q ) ) ) ) # ( \A_SPW_TOP|rx_data|rd_ptr [3] & ( !\A_SPW_TOP|rx_data|mem[37][4]~q  & ( 
// (!\A_SPW_TOP|rx_data|rd_ptr [4] & ((\A_SPW_TOP|rx_data|mem[45][4]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [4] & (\A_SPW_TOP|rx_data|mem[61][4]~q )) ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [3] & ( !\A_SPW_TOP|rx_data|mem[37][4]~q  & ( 
// (\A_SPW_TOP|rx_data|mem[53][4]~q  & \A_SPW_TOP|rx_data|rd_ptr [4]) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[61][4]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[53][4]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[45][4]~q ),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [4]),
        .datae(!\A_SPW_TOP|rx_data|rd_ptr [3]),
        .dataf(!\A_SPW_TOP|rx_data|mem[37][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux13~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux13~17 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux13~17 .lut_mask = 64'h00330F55FF330F55;
defparam \A_SPW_TOP|rx_data|Mux13~17 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X31_Y5_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux13~15 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux13~15_combout  = ( \A_SPW_TOP|rx_data|rd_ptr [3] & ( \A_SPW_TOP|rx_data|mem[49][4]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & ((\A_SPW_TOP|rx_data|mem[41][4]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [4] & (\A_SPW_TOP|rx_data|mem[57][4]~q )) 
// ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [3] & ( \A_SPW_TOP|rx_data|mem[49][4]~q  & ( (\A_SPW_TOP|rx_data|mem[33][4]~q ) # (\A_SPW_TOP|rx_data|rd_ptr [4]) ) ) ) # ( \A_SPW_TOP|rx_data|rd_ptr [3] & ( !\A_SPW_TOP|rx_data|mem[49][4]~q  & ( 
// (!\A_SPW_TOP|rx_data|rd_ptr [4] & ((\A_SPW_TOP|rx_data|mem[41][4]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [4] & (\A_SPW_TOP|rx_data|mem[57][4]~q )) ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [3] & ( !\A_SPW_TOP|rx_data|mem[49][4]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr 
// [4] & \A_SPW_TOP|rx_data|mem[33][4]~q ) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[57][4]~q ),
        .datab(!\A_SPW_TOP|rx_data|rd_ptr [4]),
        .datac(!\A_SPW_TOP|rx_data|mem[33][4]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[41][4]~q ),
        .datae(!\A_SPW_TOP|rx_data|rd_ptr [3]),
        .dataf(!\A_SPW_TOP|rx_data|mem[49][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux13~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux13~15 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux13~15 .lut_mask = 64'h0C0C11DD3F3F11DD;
defparam \A_SPW_TOP|rx_data|Mux13~15 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X31_Y5_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux13~18 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux13~18_combout  = ( \A_SPW_TOP|rx_data|rd_ptr [4] & ( \A_SPW_TOP|rx_data|mem[47][4]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [3] & ((\A_SPW_TOP|rx_data|mem[55][4]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|mem[63][4]~q )) 
// ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [4] & ( \A_SPW_TOP|rx_data|mem[47][4]~q  & ( (\A_SPW_TOP|rx_data|mem[39][4]~q ) # (\A_SPW_TOP|rx_data|rd_ptr [3]) ) ) ) # ( \A_SPW_TOP|rx_data|rd_ptr [4] & ( !\A_SPW_TOP|rx_data|mem[47][4]~q  & ( 
// (!\A_SPW_TOP|rx_data|rd_ptr [3] & ((\A_SPW_TOP|rx_data|mem[55][4]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|mem[63][4]~q )) ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [4] & ( !\A_SPW_TOP|rx_data|mem[47][4]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr 
// [3] & \A_SPW_TOP|rx_data|mem[39][4]~q ) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [3]),
        .datab(!\A_SPW_TOP|rx_data|mem[63][4]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[55][4]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[39][4]~q ),
        .datae(!\A_SPW_TOP|rx_data|rd_ptr [4]),
        .dataf(!\A_SPW_TOP|rx_data|mem[47][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux13~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux13~18 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux13~18 .lut_mask = 64'h00AA1B1B55FF1B1B;
defparam \A_SPW_TOP|rx_data|Mux13~18 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X31_Y5_N33
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux13~16 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux13~16_combout  = ( \A_SPW_TOP|rx_data|rd_ptr [3] & ( \A_SPW_TOP|rx_data|mem[35][4]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & ((\A_SPW_TOP|rx_data|mem[43][4]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [4] & (\A_SPW_TOP|rx_data|mem[59][4]~q )) 
// ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [3] & ( \A_SPW_TOP|rx_data|mem[35][4]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [4]) # (\A_SPW_TOP|rx_data|mem[51][4]~q ) ) ) ) # ( \A_SPW_TOP|rx_data|rd_ptr [3] & ( !\A_SPW_TOP|rx_data|mem[35][4]~q  & ( 
// (!\A_SPW_TOP|rx_data|rd_ptr [4] & ((\A_SPW_TOP|rx_data|mem[43][4]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [4] & (\A_SPW_TOP|rx_data|mem[59][4]~q )) ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [3] & ( !\A_SPW_TOP|rx_data|mem[35][4]~q  & ( 
// (\A_SPW_TOP|rx_data|mem[51][4]~q  & \A_SPW_TOP|rx_data|rd_ptr [4]) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[51][4]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[59][4]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[43][4]~q ),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [4]),
        .datae(!\A_SPW_TOP|rx_data|rd_ptr [3]),
        .dataf(!\A_SPW_TOP|rx_data|mem[35][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux13~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux13~16 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux13~16 .lut_mask = 64'h00550F33FF550F33;
defparam \A_SPW_TOP|rx_data|Mux13~16 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X31_Y6_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux13~19 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux13~19_combout  = ( \A_SPW_TOP|rx_data|Mux13~18_combout  & ( \A_SPW_TOP|rx_data|Mux13~16_combout  & ( ((!\A_SPW_TOP|rx_data|rd_ptr [2] & ((\A_SPW_TOP|rx_data|Mux13~15_combout ))) # (\A_SPW_TOP|rx_data|rd_ptr [2] & 
// (\A_SPW_TOP|rx_data|Mux13~17_combout ))) # (\A_SPW_TOP|rx_data|rd_ptr [1]) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux13~18_combout  & ( \A_SPW_TOP|rx_data|Mux13~16_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [2] & (((\A_SPW_TOP|rx_data|Mux13~15_combout ) # 
// (\A_SPW_TOP|rx_data|rd_ptr [1])))) # (\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|Mux13~17_combout  & (!\A_SPW_TOP|rx_data|rd_ptr [1]))) ) ) ) # ( \A_SPW_TOP|rx_data|Mux13~18_combout  & ( !\A_SPW_TOP|rx_data|Mux13~16_combout  & ( 
// (!\A_SPW_TOP|rx_data|rd_ptr [2] & (((!\A_SPW_TOP|rx_data|rd_ptr [1] & \A_SPW_TOP|rx_data|Mux13~15_combout )))) # (\A_SPW_TOP|rx_data|rd_ptr [2] & (((\A_SPW_TOP|rx_data|rd_ptr [1])) # (\A_SPW_TOP|rx_data|Mux13~17_combout ))) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|Mux13~18_combout  & ( !\A_SPW_TOP|rx_data|Mux13~16_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & ((!\A_SPW_TOP|rx_data|rd_ptr [2] & ((\A_SPW_TOP|rx_data|Mux13~15_combout ))) # (\A_SPW_TOP|rx_data|rd_ptr [2] & 
// (\A_SPW_TOP|rx_data|Mux13~17_combout )))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datab(!\A_SPW_TOP|rx_data|Mux13~17_combout ),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datad(!\A_SPW_TOP|rx_data|Mux13~15_combout ),
        .datae(!\A_SPW_TOP|rx_data|Mux13~18_combout ),
        .dataf(!\A_SPW_TOP|rx_data|Mux13~16_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux13~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux13~19 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux13~19 .lut_mask = 64'h10B015B51ABA1FBF;
defparam \A_SPW_TOP|rx_data|Mux13~19 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X33_Y6_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux13~13 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux13~13_combout  = ( \A_SPW_TOP|rx_data|mem[27][4]~q  & ( \A_SPW_TOP|rx_data|mem[31][4]~q  & ( ((!\A_SPW_TOP|rx_data|rd_ptr [2] & ((\A_SPW_TOP|rx_data|mem[25][4]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|mem[29][4]~q 
// ))) # (\A_SPW_TOP|rx_data|rd_ptr [1]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[27][4]~q  & ( \A_SPW_TOP|rx_data|mem[31][4]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [2] & (((!\A_SPW_TOP|rx_data|rd_ptr [1] & \A_SPW_TOP|rx_data|mem[25][4]~q )))) # 
// (\A_SPW_TOP|rx_data|rd_ptr [2] & (((\A_SPW_TOP|rx_data|rd_ptr [1])) # (\A_SPW_TOP|rx_data|mem[29][4]~q ))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[27][4]~q  & ( !\A_SPW_TOP|rx_data|mem[31][4]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [2] & 
// (((\A_SPW_TOP|rx_data|mem[25][4]~q ) # (\A_SPW_TOP|rx_data|rd_ptr [1])))) # (\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|mem[29][4]~q  & (!\A_SPW_TOP|rx_data|rd_ptr [1]))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[27][4]~q  & ( 
// !\A_SPW_TOP|rx_data|mem[31][4]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & ((!\A_SPW_TOP|rx_data|rd_ptr [2] & ((\A_SPW_TOP|rx_data|mem[25][4]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|mem[29][4]~q )))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datab(!\A_SPW_TOP|rx_data|mem[29][4]~q ),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datad(!\A_SPW_TOP|rx_data|mem[25][4]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[27][4]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[31][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux13~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux13~13 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux13~13 .lut_mask = 64'h10B01ABA15B51FBF;
defparam \A_SPW_TOP|rx_data|Mux13~13 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X32_Y6_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux13~11 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux13~11_combout  = ( \A_SPW_TOP|rx_data|mem[23][4]~q  & ( \A_SPW_TOP|rx_data|mem[19][4]~q  & ( ((!\A_SPW_TOP|rx_data|rd_ptr [2] & ((\A_SPW_TOP|rx_data|mem[17][4]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|mem[21][4]~q 
// ))) # (\A_SPW_TOP|rx_data|rd_ptr [1]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[23][4]~q  & ( \A_SPW_TOP|rx_data|mem[19][4]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [2] & (((\A_SPW_TOP|rx_data|mem[17][4]~q ) # (\A_SPW_TOP|rx_data|rd_ptr [1])))) # 
// (\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|mem[21][4]~q  & (!\A_SPW_TOP|rx_data|rd_ptr [1]))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[23][4]~q  & ( !\A_SPW_TOP|rx_data|mem[19][4]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [2] & (((!\A_SPW_TOP|rx_data|rd_ptr 
// [1] & \A_SPW_TOP|rx_data|mem[17][4]~q )))) # (\A_SPW_TOP|rx_data|rd_ptr [2] & (((\A_SPW_TOP|rx_data|rd_ptr [1])) # (\A_SPW_TOP|rx_data|mem[21][4]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[23][4]~q  & ( !\A_SPW_TOP|rx_data|mem[19][4]~q  & ( 
// (!\A_SPW_TOP|rx_data|rd_ptr [1] & ((!\A_SPW_TOP|rx_data|rd_ptr [2] & ((\A_SPW_TOP|rx_data|mem[17][4]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|mem[21][4]~q )))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[21][4]~q ),
        .datab(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datad(!\A_SPW_TOP|rx_data|mem[17][4]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[23][4]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[19][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux13~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux13~11 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux13~11 .lut_mask = 64'h10D013D31CDC1FDF;
defparam \A_SPW_TOP|rx_data|Mux13~11 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X35_Y6_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux13~12 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux13~12_combout  = ( \A_SPW_TOP|rx_data|mem[13][4]~q  & ( \A_SPW_TOP|rx_data|rd_ptr [2] & ( (!\A_SPW_TOP|rx_data|rd_ptr [1]) # (\A_SPW_TOP|rx_data|mem[15][4]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[13][4]~q  & ( \A_SPW_TOP|rx_data|rd_ptr 
// [2] & ( (\A_SPW_TOP|rx_data|mem[15][4]~q  & \A_SPW_TOP|rx_data|rd_ptr [1]) ) ) ) # ( \A_SPW_TOP|rx_data|mem[13][4]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [2] & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & ((\A_SPW_TOP|rx_data|mem[9][4]~q ))) # 
// (\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|mem[11][4]~q )) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[13][4]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [2] & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & ((\A_SPW_TOP|rx_data|mem[9][4]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [1] 
// & (\A_SPW_TOP|rx_data|mem[11][4]~q )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[11][4]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[9][4]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[15][4]~q ),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datae(!\A_SPW_TOP|rx_data|mem[13][4]~q ),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux13~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux13~12 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux13~12 .lut_mask = 64'h33553355000FFF0F;
defparam \A_SPW_TOP|rx_data|Mux13~12 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y6_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux13~10 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux13~10_combout  = ( \A_SPW_TOP|rx_data|mem[7][4]~q  & ( \A_SPW_TOP|rx_data|mem[5][4]~q  & ( ((!\A_SPW_TOP|rx_data|rd_ptr [1] & ((\A_SPW_TOP|rx_data|mem[1][4]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|mem[3][4]~q ))) 
// # (\A_SPW_TOP|rx_data|rd_ptr [2]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[7][4]~q  & ( \A_SPW_TOP|rx_data|mem[5][4]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [2] & ((!\A_SPW_TOP|rx_data|rd_ptr [1] & ((\A_SPW_TOP|rx_data|mem[1][4]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [1] 
// & (\A_SPW_TOP|rx_data|mem[3][4]~q )))) # (\A_SPW_TOP|rx_data|rd_ptr [2] & (((!\A_SPW_TOP|rx_data|rd_ptr [1])))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[7][4]~q  & ( !\A_SPW_TOP|rx_data|mem[5][4]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [2] & 
// ((!\A_SPW_TOP|rx_data|rd_ptr [1] & ((\A_SPW_TOP|rx_data|mem[1][4]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|mem[3][4]~q )))) # (\A_SPW_TOP|rx_data|rd_ptr [2] & (((\A_SPW_TOP|rx_data|rd_ptr [1])))) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|mem[7][4]~q  & ( !\A_SPW_TOP|rx_data|mem[5][4]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [2] & ((!\A_SPW_TOP|rx_data|rd_ptr [1] & ((\A_SPW_TOP|rx_data|mem[1][4]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|mem[3][4]~q )))) ) ) 
// )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datab(!\A_SPW_TOP|rx_data|mem[3][4]~q ),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datad(!\A_SPW_TOP|rx_data|mem[1][4]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[7][4]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[5][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux13~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux13~10 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux13~10 .lut_mask = 64'h02A207A752F257F7;
defparam \A_SPW_TOP|rx_data|Mux13~10 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X31_Y6_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux13~14 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux13~14_combout  = ( \A_SPW_TOP|rx_data|rd_ptr [3] & ( \A_SPW_TOP|rx_data|Mux13~10_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & ((\A_SPW_TOP|rx_data|Mux13~12_combout ))) # (\A_SPW_TOP|rx_data|rd_ptr [4] & 
// (\A_SPW_TOP|rx_data|Mux13~13_combout )) ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [3] & ( \A_SPW_TOP|rx_data|Mux13~10_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [4]) # (\A_SPW_TOP|rx_data|Mux13~11_combout ) ) ) ) # ( \A_SPW_TOP|rx_data|rd_ptr [3] & ( 
// !\A_SPW_TOP|rx_data|Mux13~10_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & ((\A_SPW_TOP|rx_data|Mux13~12_combout ))) # (\A_SPW_TOP|rx_data|rd_ptr [4] & (\A_SPW_TOP|rx_data|Mux13~13_combout )) ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [3] & ( 
// !\A_SPW_TOP|rx_data|Mux13~10_combout  & ( (\A_SPW_TOP|rx_data|Mux13~11_combout  & \A_SPW_TOP|rx_data|rd_ptr [4]) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux13~13_combout ),
        .datab(!\A_SPW_TOP|rx_data|Mux13~11_combout ),
        .datac(!\A_SPW_TOP|rx_data|Mux13~12_combout ),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [4]),
        .datae(!\A_SPW_TOP|rx_data|rd_ptr [3]),
        .dataf(!\A_SPW_TOP|rx_data|Mux13~10_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux13~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux13~14 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux13~14 .lut_mask = 64'h00330F55FF330F55;
defparam \A_SPW_TOP|rx_data|Mux13~14 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X33_Y6_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux13~3 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux13~3_combout  = ( \A_SPW_TOP|rx_data|mem[24][4]~q  & ( \A_SPW_TOP|rx_data|mem[28][4]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [1]) # ((!\A_SPW_TOP|rx_data|rd_ptr [2] & ((\A_SPW_TOP|rx_data|mem[26][4]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [2] 
// & (\A_SPW_TOP|rx_data|mem[30][4]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[24][4]~q  & ( \A_SPW_TOP|rx_data|mem[28][4]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & (((\A_SPW_TOP|rx_data|rd_ptr [2])))) # (\A_SPW_TOP|rx_data|rd_ptr [1] & 
// ((!\A_SPW_TOP|rx_data|rd_ptr [2] & ((\A_SPW_TOP|rx_data|mem[26][4]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|mem[30][4]~q )))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[24][4]~q  & ( !\A_SPW_TOP|rx_data|mem[28][4]~q  & ( 
// (!\A_SPW_TOP|rx_data|rd_ptr [1] & (((!\A_SPW_TOP|rx_data|rd_ptr [2])))) # (\A_SPW_TOP|rx_data|rd_ptr [1] & ((!\A_SPW_TOP|rx_data|rd_ptr [2] & ((\A_SPW_TOP|rx_data|mem[26][4]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|mem[30][4]~q )))) ) 
// ) ) # ( !\A_SPW_TOP|rx_data|mem[24][4]~q  & ( !\A_SPW_TOP|rx_data|mem[28][4]~q  & ( (\A_SPW_TOP|rx_data|rd_ptr [1] & ((!\A_SPW_TOP|rx_data|rd_ptr [2] & ((\A_SPW_TOP|rx_data|mem[26][4]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [2] & 
// (\A_SPW_TOP|rx_data|mem[30][4]~q )))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datab(!\A_SPW_TOP|rx_data|mem[30][4]~q ),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datad(!\A_SPW_TOP|rx_data|mem[26][4]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[24][4]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[28][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux13~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux13~3 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux13~3 .lut_mask = 64'h0151A1F10B5BABFB;
defparam \A_SPW_TOP|rx_data|Mux13~3 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X32_Y6_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux13~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux13~1_combout  = ( \A_SPW_TOP|rx_data|mem[16][4]~q  & ( \A_SPW_TOP|rx_data|rd_ptr [1] & ( (!\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|mem[18][4]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [2] & ((\A_SPW_TOP|rx_data|mem[22][4]~q ))) ) 
// ) ) # ( !\A_SPW_TOP|rx_data|mem[16][4]~q  & ( \A_SPW_TOP|rx_data|rd_ptr [1] & ( (!\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|mem[18][4]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [2] & ((\A_SPW_TOP|rx_data|mem[22][4]~q ))) ) ) ) # ( 
// \A_SPW_TOP|rx_data|mem[16][4]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [1] & ( (!\A_SPW_TOP|rx_data|rd_ptr [2]) # (\A_SPW_TOP|rx_data|mem[20][4]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[16][4]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [1] & ( 
// (\A_SPW_TOP|rx_data|mem[20][4]~q  & \A_SPW_TOP|rx_data|rd_ptr [2]) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[18][4]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[20][4]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[22][4]~q ),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datae(!\A_SPW_TOP|rx_data|mem[16][4]~q ),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux13~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux13~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux13~1 .lut_mask = 64'h0033FF33550F550F;
defparam \A_SPW_TOP|rx_data|Mux13~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X35_Y6_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux13~2 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux13~2_combout  = ( \A_SPW_TOP|rx_data|mem[10][4]~q  & ( \A_SPW_TOP|rx_data|mem[14][4]~q  & ( ((!\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|mem[8][4]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [2] & ((\A_SPW_TOP|rx_data|mem[12][4]~q 
// )))) # (\A_SPW_TOP|rx_data|rd_ptr [1]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[10][4]~q  & ( \A_SPW_TOP|rx_data|mem[14][4]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & ((!\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|mem[8][4]~q )) # 
// (\A_SPW_TOP|rx_data|rd_ptr [2] & ((\A_SPW_TOP|rx_data|mem[12][4]~q ))))) # (\A_SPW_TOP|rx_data|rd_ptr [1] & (((\A_SPW_TOP|rx_data|rd_ptr [2])))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[10][4]~q  & ( !\A_SPW_TOP|rx_data|mem[14][4]~q  & ( 
// (!\A_SPW_TOP|rx_data|rd_ptr [1] & ((!\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|mem[8][4]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [2] & ((\A_SPW_TOP|rx_data|mem[12][4]~q ))))) # (\A_SPW_TOP|rx_data|rd_ptr [1] & (((!\A_SPW_TOP|rx_data|rd_ptr [2])))) ) ) 
// ) # ( !\A_SPW_TOP|rx_data|mem[10][4]~q  & ( !\A_SPW_TOP|rx_data|mem[14][4]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & ((!\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|mem[8][4]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [2] & ((\A_SPW_TOP|rx_data|mem[12][4]~q 
// ))))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[8][4]~q ),
        .datab(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datad(!\A_SPW_TOP|rx_data|mem[12][4]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[10][4]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[14][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux13~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux13~2 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux13~2 .lut_mask = 64'h404C707C434F737F;
defparam \A_SPW_TOP|rx_data|Mux13~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y6_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux13~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux13~0_combout  = ( \A_SPW_TOP|rx_data|mem[4][4]~q  & ( \A_SPW_TOP|rx_data|mem[0][4]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [1]) # ((!\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|mem[2][4]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [2] & 
// ((\A_SPW_TOP|rx_data|mem[6][4]~q )))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[4][4]~q  & ( \A_SPW_TOP|rx_data|mem[0][4]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [2] & (((!\A_SPW_TOP|rx_data|rd_ptr [1])) # (\A_SPW_TOP|rx_data|mem[2][4]~q ))) # 
// (\A_SPW_TOP|rx_data|rd_ptr [2] & (((\A_SPW_TOP|rx_data|rd_ptr [1] & \A_SPW_TOP|rx_data|mem[6][4]~q )))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[4][4]~q  & ( !\A_SPW_TOP|rx_data|mem[0][4]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|mem[2][4]~q  & 
// (\A_SPW_TOP|rx_data|rd_ptr [1]))) # (\A_SPW_TOP|rx_data|rd_ptr [2] & (((!\A_SPW_TOP|rx_data|rd_ptr [1]) # (\A_SPW_TOP|rx_data|mem[6][4]~q )))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[4][4]~q  & ( !\A_SPW_TOP|rx_data|mem[0][4]~q  & ( (\A_SPW_TOP|rx_data|rd_ptr 
// [1] & ((!\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|mem[2][4]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [2] & ((\A_SPW_TOP|rx_data|mem[6][4]~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datab(!\A_SPW_TOP|rx_data|mem[2][4]~q ),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datad(!\A_SPW_TOP|rx_data|mem[6][4]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[4][4]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[0][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux13~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux13~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux13~0 .lut_mask = 64'h02075257A2A7F2F7;
defparam \A_SPW_TOP|rx_data|Mux13~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X31_Y6_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux13~4 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux13~4_combout  = ( \A_SPW_TOP|rx_data|Mux13~2_combout  & ( \A_SPW_TOP|rx_data|Mux13~0_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [4]) # ((!\A_SPW_TOP|rx_data|rd_ptr [3] & ((\A_SPW_TOP|rx_data|Mux13~1_combout ))) # 
// (\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|Mux13~3_combout ))) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux13~2_combout  & ( \A_SPW_TOP|rx_data|Mux13~0_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & (((!\A_SPW_TOP|rx_data|rd_ptr [3])))) # 
// (\A_SPW_TOP|rx_data|rd_ptr [4] & ((!\A_SPW_TOP|rx_data|rd_ptr [3] & ((\A_SPW_TOP|rx_data|Mux13~1_combout ))) # (\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|Mux13~3_combout )))) ) ) ) # ( \A_SPW_TOP|rx_data|Mux13~2_combout  & ( 
// !\A_SPW_TOP|rx_data|Mux13~0_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & (((\A_SPW_TOP|rx_data|rd_ptr [3])))) # (\A_SPW_TOP|rx_data|rd_ptr [4] & ((!\A_SPW_TOP|rx_data|rd_ptr [3] & ((\A_SPW_TOP|rx_data|Mux13~1_combout ))) # (\A_SPW_TOP|rx_data|rd_ptr [3] 
// & (\A_SPW_TOP|rx_data|Mux13~3_combout )))) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux13~2_combout  & ( !\A_SPW_TOP|rx_data|Mux13~0_combout  & ( (\A_SPW_TOP|rx_data|rd_ptr [4] & ((!\A_SPW_TOP|rx_data|rd_ptr [3] & ((\A_SPW_TOP|rx_data|Mux13~1_combout ))) # 
// (\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|Mux13~3_combout )))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux13~3_combout ),
        .datab(!\A_SPW_TOP|rx_data|rd_ptr [4]),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [3]),
        .datad(!\A_SPW_TOP|rx_data|Mux13~1_combout ),
        .datae(!\A_SPW_TOP|rx_data|Mux13~2_combout ),
        .dataf(!\A_SPW_TOP|rx_data|Mux13~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux13~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux13~4 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux13~4 .lut_mask = 64'h01310D3DC1F1CDFD;
defparam \A_SPW_TOP|rx_data|Mux13~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X31_Y6_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux13~6 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux13~6_combout  = ( \A_SPW_TOP|rx_data|mem[50][4]~q  & ( \A_SPW_TOP|rx_data|rd_ptr [1] & ( (!\A_SPW_TOP|rx_data|rd_ptr [2]) # (\A_SPW_TOP|rx_data|mem[54][4]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[50][4]~q  & ( \A_SPW_TOP|rx_data|rd_ptr 
// [1] & ( (\A_SPW_TOP|rx_data|rd_ptr [2] & \A_SPW_TOP|rx_data|mem[54][4]~q ) ) ) ) # ( \A_SPW_TOP|rx_data|mem[50][4]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [1] & ( (!\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|mem[48][4]~q )) # (\A_SPW_TOP|rx_data|rd_ptr 
// [2] & ((\A_SPW_TOP|rx_data|mem[52][4]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[50][4]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [1] & ( (!\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|mem[48][4]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [2] & 
// ((\A_SPW_TOP|rx_data|mem[52][4]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[48][4]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[52][4]~q ),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datad(!\A_SPW_TOP|rx_data|mem[54][4]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[50][4]~q ),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux13~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux13~6 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux13~6 .lut_mask = 64'h53535353000FF0FF;
defparam \A_SPW_TOP|rx_data|Mux13~6 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y5_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux13~7 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux13~7_combout  = ( \A_SPW_TOP|rx_data|mem[46][4]~q  & ( \A_SPW_TOP|rx_data|mem[40][4]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [2] & (((!\A_SPW_TOP|rx_data|rd_ptr [1]) # (\A_SPW_TOP|rx_data|mem[42][4]~q )))) # (\A_SPW_TOP|rx_data|rd_ptr [2] 
// & (((\A_SPW_TOP|rx_data|rd_ptr [1])) # (\A_SPW_TOP|rx_data|mem[44][4]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[46][4]~q  & ( \A_SPW_TOP|rx_data|mem[40][4]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [2] & (((!\A_SPW_TOP|rx_data|rd_ptr [1]) # 
// (\A_SPW_TOP|rx_data|mem[42][4]~q )))) # (\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|mem[44][4]~q  & (!\A_SPW_TOP|rx_data|rd_ptr [1]))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[46][4]~q  & ( !\A_SPW_TOP|rx_data|mem[40][4]~q  & ( 
// (!\A_SPW_TOP|rx_data|rd_ptr [2] & (((\A_SPW_TOP|rx_data|rd_ptr [1] & \A_SPW_TOP|rx_data|mem[42][4]~q )))) # (\A_SPW_TOP|rx_data|rd_ptr [2] & (((\A_SPW_TOP|rx_data|rd_ptr [1])) # (\A_SPW_TOP|rx_data|mem[44][4]~q ))) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|mem[46][4]~q  & ( !\A_SPW_TOP|rx_data|mem[40][4]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [2] & (((\A_SPW_TOP|rx_data|rd_ptr [1] & \A_SPW_TOP|rx_data|mem[42][4]~q )))) # (\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|mem[44][4]~q  & 
// (!\A_SPW_TOP|rx_data|rd_ptr [1]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datab(!\A_SPW_TOP|rx_data|mem[44][4]~q ),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datad(!\A_SPW_TOP|rx_data|mem[42][4]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[46][4]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[40][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux13~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux13~7 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux13~7 .lut_mask = 64'h101A151FB0BAB5BF;
defparam \A_SPW_TOP|rx_data|Mux13~7 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X32_Y6_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux13~8 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux13~8_combout  = ( \A_SPW_TOP|rx_data|mem[56][4]~q  & ( \A_SPW_TOP|rx_data|rd_ptr [2] & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & ((\A_SPW_TOP|rx_data|mem[60][4]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|mem[62][4]~q )) ) 
// ) ) # ( !\A_SPW_TOP|rx_data|mem[56][4]~q  & ( \A_SPW_TOP|rx_data|rd_ptr [2] & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & ((\A_SPW_TOP|rx_data|mem[60][4]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|mem[62][4]~q )) ) ) ) # ( 
// \A_SPW_TOP|rx_data|mem[56][4]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [2] & ( (!\A_SPW_TOP|rx_data|rd_ptr [1]) # (\A_SPW_TOP|rx_data|mem[58][4]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[56][4]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [2] & ( (\A_SPW_TOP|rx_data|rd_ptr [1] 
// & \A_SPW_TOP|rx_data|mem[58][4]~q ) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[62][4]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[60][4]~q ),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datad(!\A_SPW_TOP|rx_data|mem[58][4]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[56][4]~q ),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux13~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux13~8 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux13~8 .lut_mask = 64'h000FF0FF35353535;
defparam \A_SPW_TOP|rx_data|Mux13~8 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y5_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux13~5 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux13~5_combout  = ( \A_SPW_TOP|rx_data|mem[38][4]~q  & ( \A_SPW_TOP|rx_data|mem[34][4]~q  & ( ((!\A_SPW_TOP|rx_data|rd_ptr [2] & ((\A_SPW_TOP|rx_data|mem[32][4]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|mem[36][4]~q 
// ))) # (\A_SPW_TOP|rx_data|rd_ptr [1]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[38][4]~q  & ( \A_SPW_TOP|rx_data|mem[34][4]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [2] & (((\A_SPW_TOP|rx_data|mem[32][4]~q ) # (\A_SPW_TOP|rx_data|rd_ptr [1])))) # 
// (\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|mem[36][4]~q  & (!\A_SPW_TOP|rx_data|rd_ptr [1]))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[38][4]~q  & ( !\A_SPW_TOP|rx_data|mem[34][4]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [2] & (((!\A_SPW_TOP|rx_data|rd_ptr 
// [1] & \A_SPW_TOP|rx_data|mem[32][4]~q )))) # (\A_SPW_TOP|rx_data|rd_ptr [2] & (((\A_SPW_TOP|rx_data|rd_ptr [1])) # (\A_SPW_TOP|rx_data|mem[36][4]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[38][4]~q  & ( !\A_SPW_TOP|rx_data|mem[34][4]~q  & ( 
// (!\A_SPW_TOP|rx_data|rd_ptr [1] & ((!\A_SPW_TOP|rx_data|rd_ptr [2] & ((\A_SPW_TOP|rx_data|mem[32][4]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|mem[36][4]~q )))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datab(!\A_SPW_TOP|rx_data|mem[36][4]~q ),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datad(!\A_SPW_TOP|rx_data|mem[32][4]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[38][4]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[34][4]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux13~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux13~5 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux13~5 .lut_mask = 64'h10B015B51ABA1FBF;
defparam \A_SPW_TOP|rx_data|Mux13~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X31_Y6_N9
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux13~9 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux13~9_combout  = ( \A_SPW_TOP|rx_data|rd_ptr [3] & ( \A_SPW_TOP|rx_data|Mux13~5_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & (\A_SPW_TOP|rx_data|Mux13~7_combout )) # (\A_SPW_TOP|rx_data|rd_ptr [4] & 
// ((\A_SPW_TOP|rx_data|Mux13~8_combout ))) ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [3] & ( \A_SPW_TOP|rx_data|Mux13~5_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [4]) # (\A_SPW_TOP|rx_data|Mux13~6_combout ) ) ) ) # ( \A_SPW_TOP|rx_data|rd_ptr [3] & ( 
// !\A_SPW_TOP|rx_data|Mux13~5_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & (\A_SPW_TOP|rx_data|Mux13~7_combout )) # (\A_SPW_TOP|rx_data|rd_ptr [4] & ((\A_SPW_TOP|rx_data|Mux13~8_combout ))) ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [3] & ( 
// !\A_SPW_TOP|rx_data|Mux13~5_combout  & ( (\A_SPW_TOP|rx_data|Mux13~6_combout  & \A_SPW_TOP|rx_data|rd_ptr [4]) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux13~6_combout ),
        .datab(!\A_SPW_TOP|rx_data|Mux13~7_combout ),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [4]),
        .datad(!\A_SPW_TOP|rx_data|Mux13~8_combout ),
        .datae(!\A_SPW_TOP|rx_data|rd_ptr [3]),
        .dataf(!\A_SPW_TOP|rx_data|Mux13~5_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux13~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux13~9 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux13~9 .lut_mask = 64'h0505303FF5F5303F;
defparam \A_SPW_TOP|rx_data|Mux13~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X31_Y6_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux13~20 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux13~20_combout  = ( \A_SPW_TOP|rx_data|rd_ptr [5] & ( \A_SPW_TOP|rx_data|Mux13~9_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [0]) # (\A_SPW_TOP|rx_data|Mux13~19_combout ) ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [5] & ( 
// \A_SPW_TOP|rx_data|Mux13~9_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & ((\A_SPW_TOP|rx_data|Mux13~4_combout ))) # (\A_SPW_TOP|rx_data|rd_ptr [0] & (\A_SPW_TOP|rx_data|Mux13~14_combout )) ) ) ) # ( \A_SPW_TOP|rx_data|rd_ptr [5] & ( 
// !\A_SPW_TOP|rx_data|Mux13~9_combout  & ( (\A_SPW_TOP|rx_data|Mux13~19_combout  & \A_SPW_TOP|rx_data|rd_ptr [0]) ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [5] & ( !\A_SPW_TOP|rx_data|Mux13~9_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & 
// ((\A_SPW_TOP|rx_data|Mux13~4_combout ))) # (\A_SPW_TOP|rx_data|rd_ptr [0] & (\A_SPW_TOP|rx_data|Mux13~14_combout )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux13~19_combout ),
        .datab(!\A_SPW_TOP|rx_data|Mux13~14_combout ),
        .datac(!\A_SPW_TOP|rx_data|Mux13~4_combout ),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .datae(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .dataf(!\A_SPW_TOP|rx_data|Mux13~9_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux13~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux13~20 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux13~20 .lut_mask = 64'h0F3300550F33FF55;
defparam \A_SPW_TOP|rx_data|Mux13~20 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y6_N43
dffeas \A_SPW_TOP|rx_data|data_out[4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|rx_data|Mux13~20_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|data_out [4]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|data_out[4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|data_out[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y16_N57
cyclonev_lcell_comb \u0|data_flag_rx|read_mux_out[4] (
// Equation(s):
// \u0|data_flag_rx|read_mux_out [4] = ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & ( 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & \A_SPW_TOP|rx_data|data_out [4]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datac(!\A_SPW_TOP|rx_data|data_out [4]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|data_flag_rx|read_mux_out [4]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|data_flag_rx|read_mux_out[4] .extended_lut = "off";
defparam \u0|data_flag_rx|read_mux_out[4] .lut_mask = 64'h0C0C00000C0C0000;
defparam \u0|data_flag_rx|read_mux_out[4] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y16_N59
dffeas \u0|data_flag_rx|readdata[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|data_flag_rx|read_mux_out [4]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|data_flag_rx|readdata [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|data_flag_rx|readdata[4] .is_wysiwyg = "true";
defparam \u0|data_flag_rx|readdata[4] .power_up = "low";
// synopsys translate_on

// Location: FF_X23_Y16_N26
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|data_flag_rx|readdata [4]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre[4] .power_up = "low";
// synopsys translate_on

// Location: FF_X27_Y16_N38
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y16_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~4 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~4_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [4] & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1]) # 
// (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][4]~q ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [4] & ( (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][4]~q ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][4]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~4 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y16_N53
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~4_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y16_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~61 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~61_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][4]~q  & ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout  & ( 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout  & \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [4]) ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][4]~q  & ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout  & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout  & \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [4]) ) ) ) # ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][4]~q  & ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout  & ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout  ) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout ),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [4]),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][4]~q ),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~61_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~61 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~61 .lut_mask = 64'h0000AAAA22222222;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~61 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y16_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~62 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~62_combout  = ( \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~61_combout  ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~61_combout  & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout  & 
// (((\u0|mm_interconnect_0|rsp_demux|src1_valid~combout  & \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~59_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~60_combout ))) # (\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout  & 
// (\u0|mm_interconnect_0|rsp_demux|src1_valid~combout  & ((\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~59_combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ),
        .datab(!\u0|mm_interconnect_0|rsp_demux|src1_valid~combout ),
        .datac(!\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~60_combout ),
        .datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~59_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~61_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~62_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~62 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~62 .lut_mask = 64'h0A3B0A3BFFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~62 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y16_N50
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y16_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~4 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~4_combout  = (!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1] & (\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [4])) # 
// (\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1] & ((\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][4]~q )))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [4]),
        .datad(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][4]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~4 .lut_mask = 64'h0C3F0C3F0C3F0C3F;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y16_N41
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~4_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][4]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y16_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~214 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~214_combout  = ( !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout  & ( ((((\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout  & 
// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][4]~q )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~62_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~58_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~218_combout ) 
// ) ) # ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout  & ( ((((\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout  & \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [4])) # 
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~62_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~58_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~218_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ),
        .datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~218_combout ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [4]),
        .datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~58_combout ),
        .datae(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout ),
        .dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~62_combout ),
        .datag(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][4]~q ),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~214_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~214 .extended_lut = "on";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~214 .lut_mask = 64'h37FF37FFFFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~214 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y26_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout  = ( \u0|hps_0|fpga_interfaces|h2f_AWVALID [0] & ( \u0|hps_0|fpga_interfaces|h2f_WVALID [0] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_WVALID [0]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWVALID [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid .lut_mask = 64'h0000000000FF00FF;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y25_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|src14_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|src14_valid~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout  & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q ) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [14]) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [14]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux|src14_valid~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|src14_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|src14_valid~0 .lut_mask = 64'h00000000FF0FFF0F;
defparam \u0|mm_interconnect_0|cmd_demux|src14_valid~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y25_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|src14_valid~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~3_combout  & ( \u0|mm_interconnect_0|cmd_demux|src14_valid~0_combout  & ( 
// (\u0|mm_interconnect_0|router|Equal7~1_combout  & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout  & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout  & 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|router|Equal7~1_combout ),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout ),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout ),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout ),
        .datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~3_combout ),
        .dataf(!\u0|mm_interconnect_0|cmd_demux|src14_valid~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|src14_valid~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|src14_valid~1 .lut_mask = 64'h0000000000000100;
defparam \u0|mm_interconnect_0|cmd_demux|src14_valid~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y22_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|arb|grant[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|arb|grant[0]~1_combout  = ( \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg [1] & ( \u0|mm_interconnect_0|cmd_demux_001|src14_valid~1_combout  & ( (\u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout  & 
// !\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg [0]) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg [1] & ( \u0|mm_interconnect_0|cmd_demux_001|src14_valid~1_combout  & ( (\u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout  & 
// !\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg [0]) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg [1] & ( !\u0|mm_interconnect_0|cmd_demux_001|src14_valid~1_combout  & ( \u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout  ) 
// ) ) # ( !\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg [1] & ( !\u0|mm_interconnect_0|cmd_demux_001|src14_valid~1_combout  & ( (\u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout  & !\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg [0]) 
// ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg [0]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg [1]),
        .dataf(!\u0|mm_interconnect_0|cmd_demux_001|src14_valid~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_014|arb|grant[0]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|arb|grant[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|arb|grant[0]~1 .lut_mask = 64'h3030333330303030;
defparam \u0|mm_interconnect_0|cmd_mux_014|arb|grant[0]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y22_N41
dffeas \u0|mm_interconnect_0|cmd_mux_014|saved_grant[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_014|arb|grant[0]~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|cmd_mux_014|update_grant~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|saved_grant[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_014|saved_grant[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y19_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68]~feeder_combout  = ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y19_N23
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y19_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~0_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~0 .lut_mask = 64'h0000000000FF00FF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y19_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~4 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~4_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [0] & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~0_combout  & 
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~0_combout ) # ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout ) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1])))) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [0] & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~0_combout  & (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout  & \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~0_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~4 .lut_mask = 64'h0040004000BF00BF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~4 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y18_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg~1_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg~0_combout  & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~4_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~4_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg~1 .lut_mask = 64'h0000000000FF00FF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y18_N47
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y18_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[0]~0_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0]) # 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|read~1_combout ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1] & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0] & 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|read~1_combout  & \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0] & 
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|read~1_combout ) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0]))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|read~1_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h30F330F30FFF0FFF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y18_N56
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y18_N33
cyclonev_lcell_comb \u0|timecode_tx_data|readdata[3] (
// Equation(s):
// \u0|timecode_tx_data|readdata [3] = ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & \u0|timecode_tx_data|data_out [3]) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datab(gnd),
        .datac(!\u0|timecode_tx_data|data_out [3]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|timecode_tx_data|readdata [3]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|timecode_tx_data|readdata[3] .extended_lut = "off";
defparam \u0|timecode_tx_data|readdata[3] .lut_mask = 64'h0A0A0A0A00000000;
defparam \u0|timecode_tx_data|readdata[3] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y18_N35
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|timecode_tx_data|readdata [3]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre[3] .power_up = "low";
// synopsys translate_on

// Location: FF_X28_Y16_N47
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y16_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~3_combout  = (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1] & (\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [3])) # 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1] & ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][3]~q )))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [3]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][3]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~3 .lut_mask = 64'h0C3F0C3F0C3F0C3F;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y16_N13
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~3_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y16_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~50 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~50_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [3] & ( \u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout  & ( 
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0] & \u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][3]~q ) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [3] & ( \u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout  & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][3]~q  & 
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0]) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0]))) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][3]~q ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0]),
        .datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [3]),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~50_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~50 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~50 .lut_mask = 64'h000000000F050FAF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~50 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y2_N42
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|rx_data_flag~3 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|rx_data_flag~3_combout  = ( \A_SPW_TOP|SPW|RX|ready_control_p_r~q  & ( (\A_SPW_TOP|SPW|RX|rx_data_flag [3] & \A_SPW_TOP|SPW|RX|rx_data_flag~0_combout ) ) ) # ( !\A_SPW_TOP|SPW|RX|ready_control_p_r~q  & ( 
// (!\A_SPW_TOP|SPW|RX|data~0_combout  & (((\A_SPW_TOP|SPW|RX|rx_data_flag [3] & \A_SPW_TOP|SPW|RX|rx_data_flag~0_combout )) # (\A_SPW_TOP|SPW|RX|dta_timec_p [3]))) # (\A_SPW_TOP|SPW|RX|data~0_combout  & (((\A_SPW_TOP|SPW|RX|rx_data_flag [3])))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|dta_timec_p [3]),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .datac(!\A_SPW_TOP|SPW|RX|data~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag~0_combout ),
        .datae(!\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|rx_data_flag~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_data_flag~3 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|rx_data_flag~3 .lut_mask = 64'h5373003353730033;
defparam \A_SPW_TOP|SPW|RX|rx_data_flag~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y2_N47
dffeas \A_SPW_TOP|SPW|RX|rx_data_flag[3] (
        .clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|RX|rx_data_flag~3_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(!\A_SPW_TOP|SPW|RX|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_data_flag[3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|rx_data_flag[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y6_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector429~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector429~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector424~0_combout  & ((\A_SPW_TOP|rx_data|mem[45][3]~q ))) # (\A_SPW_TOP|rx_data|Selector424~0_combout  & 
// (\A_SPW_TOP|rx_data|Mux5~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector424~0_combout  & ((\A_SPW_TOP|rx_data|mem[45][3]~q ))) # (\A_SPW_TOP|rx_data|Selector424~0_combout  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [3])) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .datac(!\A_SPW_TOP|rx_data|Selector424~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[45][3]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector429~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector429~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector429~0 .lut_mask = 64'h03F303F305F505F5;
defparam \A_SPW_TOP|rx_data|Selector429~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y6_N59
dffeas \A_SPW_TOP|rx_data|mem[45][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector429~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[45][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[45][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[45][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y6_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector591~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector591~0_combout  = ( \A_SPW_TOP|rx_data|Selector586~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [3])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux5~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector586~0_combout  & ( \A_SPW_TOP|rx_data|mem[63][3]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .datac(!\A_SPW_TOP|rx_data|mem[63][3]~q ),
        .datad(!\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector586~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector591~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector591~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector591~0 .lut_mask = 64'h0F0F0F0F22772277;
defparam \A_SPW_TOP|rx_data|Selector591~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y6_N35
dffeas \A_SPW_TOP|rx_data|mem[63][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector591~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[63][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[63][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[63][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y6_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector447~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector447~0_combout  = ( \A_SPW_TOP|rx_data|mem[47][3]~q  & ( (!\A_SPW_TOP|rx_data|Selector442~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [3])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux5~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[47][3]~q  & ( (\A_SPW_TOP|rx_data|Selector442~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [3])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux5~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .datac(!\A_SPW_TOP|rx_data|Selector442~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[47][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector447~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector447~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector447~0 .lut_mask = 64'h02070207F2F7F2F7;
defparam \A_SPW_TOP|rx_data|Selector447~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y6_N38
dffeas \A_SPW_TOP|rx_data|mem[47][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector447~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[47][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[47][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[47][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y6_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector573~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector573~0_combout  = ( \A_SPW_TOP|rx_data|mem[61][3]~q  & ( (!\A_SPW_TOP|rx_data|Selector568~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [3])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux5~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[61][3]~q  & ( (\A_SPW_TOP|rx_data|Selector568~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [3])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux5~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .datad(!\A_SPW_TOP|rx_data|Selector568~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[61][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector573~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector573~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector573~0 .lut_mask = 64'h00470047FF47FF47;
defparam \A_SPW_TOP|rx_data|Selector573~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y6_N11
dffeas \A_SPW_TOP|rx_data|mem[61][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector573~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[61][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[61][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[61][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y6_N15
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux5~18 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux5~18_combout  = ( \A_SPW_TOP|rx_data|mem[47][3]~q  & ( \A_SPW_TOP|rx_data|mem[61][3]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & (((\A_SPW_TOP|rx_data|wr_ptr [4])) # (\A_SPW_TOP|rx_data|mem[45][3]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [1] 
// & (((!\A_SPW_TOP|rx_data|wr_ptr [4]) # (\A_SPW_TOP|rx_data|mem[63][3]~q )))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[47][3]~q  & ( \A_SPW_TOP|rx_data|mem[61][3]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & (((\A_SPW_TOP|rx_data|wr_ptr [4])) # 
// (\A_SPW_TOP|rx_data|mem[45][3]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [1] & (((\A_SPW_TOP|rx_data|wr_ptr [4] & \A_SPW_TOP|rx_data|mem[63][3]~q )))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[47][3]~q  & ( !\A_SPW_TOP|rx_data|mem[61][3]~q  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|mem[45][3]~q  & (!\A_SPW_TOP|rx_data|wr_ptr [4]))) # (\A_SPW_TOP|rx_data|wr_ptr [1] & (((!\A_SPW_TOP|rx_data|wr_ptr [4]) # (\A_SPW_TOP|rx_data|mem[63][3]~q )))) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|mem[47][3]~q  & ( !\A_SPW_TOP|rx_data|mem[61][3]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|mem[45][3]~q  & (!\A_SPW_TOP|rx_data|wr_ptr [4]))) # (\A_SPW_TOP|rx_data|wr_ptr [1] & (((\A_SPW_TOP|rx_data|wr_ptr [4] & 
// \A_SPW_TOP|rx_data|mem[63][3]~q )))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[45][3]~q ),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datad(!\A_SPW_TOP|rx_data|mem[63][3]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[47][3]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[61][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux5~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux5~18 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux5~18 .lut_mask = 64'h404370734C4F7C7F;
defparam \A_SPW_TOP|rx_data|Mux5~18 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y6_N51
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector582~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector582~0_combout  = ( \A_SPW_TOP|rx_data|Selector577~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [3])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux5~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector577~0_combout  & ( \A_SPW_TOP|rx_data|mem[62][3]~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[62][3]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector577~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector582~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector582~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector582~0 .lut_mask = 64'h00FF00FF47474747;
defparam \A_SPW_TOP|rx_data|Selector582~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y6_N23
dffeas \A_SPW_TOP|rx_data|mem[62][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector582~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[62][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[62][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[62][3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y6_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector564~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector564~0_combout  = ( \A_SPW_TOP|rx_data|Selector559~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [3]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux5~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector559~0_combout  & ( \A_SPW_TOP|rx_data|mem[60][3]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .datad(!\A_SPW_TOP|rx_data|mem[60][3]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector559~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector564~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector564~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector564~0 .lut_mask = 64'h00FF00FF1D1D1D1D;
defparam \A_SPW_TOP|rx_data|Selector564~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y6_N59
dffeas \A_SPW_TOP|rx_data|mem[60][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector564~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[60][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[60][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[60][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y6_N9
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector420~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector420~0_combout  = ( \A_SPW_TOP|rx_data|mem[44][3]~q  & ( (!\A_SPW_TOP|rx_data|Selector415~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [3]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux5~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[44][3]~q  & ( (\A_SPW_TOP|rx_data|Selector415~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [3]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux5~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .datac(!\A_SPW_TOP|rx_data|Selector415~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[44][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector420~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector420~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector420~0 .lut_mask = 64'h03050305F3F5F3F5;
defparam \A_SPW_TOP|rx_data|Selector420~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y6_N20
dffeas \A_SPW_TOP|rx_data|mem[44][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector420~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[44][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[44][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[44][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y6_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux5~17 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux5~17_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [1] & ( \A_SPW_TOP|rx_data|mem[46][3]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [4]) # (\A_SPW_TOP|rx_data|mem[62][3]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [1] & ( 
// \A_SPW_TOP|rx_data|mem[46][3]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|mem[44][3]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[60][3]~q )) ) ) ) # ( \A_SPW_TOP|rx_data|wr_ptr [1] & ( 
// !\A_SPW_TOP|rx_data|mem[46][3]~q  & ( (\A_SPW_TOP|rx_data|mem[62][3]~q  & \A_SPW_TOP|rx_data|wr_ptr [4]) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [1] & ( !\A_SPW_TOP|rx_data|mem[46][3]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|mem[44][3]~q 
// ))) # (\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[60][3]~q )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[62][3]~q ),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datac(!\A_SPW_TOP|rx_data|mem[60][3]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[44][3]~q ),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .dataf(!\A_SPW_TOP|rx_data|mem[46][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux5~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux5~17 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux5~17 .lut_mask = 64'h03CF111103CFDDDD;
defparam \A_SPW_TOP|rx_data|Mux5~17 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y6_N9
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector411~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector411~0_combout  = ( \A_SPW_TOP|rx_data|Selector406~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [3]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux5~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector406~0_combout  & ( \A_SPW_TOP|rx_data|mem[43][3]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[43][3]~q ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector406~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector411~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector411~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector411~0 .lut_mask = 64'h0F0F0F0F11DD11DD;
defparam \A_SPW_TOP|rx_data|Selector411~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y6_N20
dffeas \A_SPW_TOP|rx_data|mem[43][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector411~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[43][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[43][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[43][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y6_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector393~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector393~0_combout  = ( \A_SPW_TOP|rx_data|mem[41][3]~q  & ( (!\A_SPW_TOP|rx_data|Selector388~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [3])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux5~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[41][3]~q  & ( (\A_SPW_TOP|rx_data|Selector388~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [3])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux5~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Selector388~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[41][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector393~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector393~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector393~0 .lut_mask = 64'h04070407F4F7F4F7;
defparam \A_SPW_TOP|rx_data|Selector393~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y6_N41
dffeas \A_SPW_TOP|rx_data|mem[41][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector393~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[41][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[41][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[41][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y6_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector555~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector555~0_combout  = ( \A_SPW_TOP|rx_data|Selector550~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [3])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux5~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector550~0_combout  & ( \A_SPW_TOP|rx_data|mem[59][3]~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[59][3]~q ),
        .datad(!\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector550~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector555~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector555~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector555~0 .lut_mask = 64'h0F0F0F0F44774477;
defparam \A_SPW_TOP|rx_data|Selector555~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y6_N35
dffeas \A_SPW_TOP|rx_data|mem[59][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector555~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[59][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[59][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[59][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y6_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector537~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector537~0_combout  = ( \A_SPW_TOP|rx_data|Selector532~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [3])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux5~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector532~0_combout  & ( \A_SPW_TOP|rx_data|mem[57][3]~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[57][3]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector532~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector537~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector537~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector537~0 .lut_mask = 64'h00FF00FF47474747;
defparam \A_SPW_TOP|rx_data|Selector537~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y6_N59
dffeas \A_SPW_TOP|rx_data|mem[57][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector537~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[57][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[57][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[57][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y6_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux5~16 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux5~16_combout  = ( \A_SPW_TOP|rx_data|mem[57][3]~q  & ( \A_SPW_TOP|rx_data|wr_ptr [1] & ( (!\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[43][3]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|mem[59][3]~q ))) ) 
// ) ) # ( !\A_SPW_TOP|rx_data|mem[57][3]~q  & ( \A_SPW_TOP|rx_data|wr_ptr [1] & ( (!\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[43][3]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|mem[59][3]~q ))) ) ) ) # ( 
// \A_SPW_TOP|rx_data|mem[57][3]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [1] & ( (\A_SPW_TOP|rx_data|wr_ptr [4]) # (\A_SPW_TOP|rx_data|mem[41][3]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[57][3]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [1] & ( 
// (\A_SPW_TOP|rx_data|mem[41][3]~q  & !\A_SPW_TOP|rx_data|wr_ptr [4]) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[43][3]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[41][3]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[59][3]~q ),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datae(!\A_SPW_TOP|rx_data|mem[57][3]~q ),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux5~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux5~16 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux5~16 .lut_mask = 64'h330033FF550F550F;
defparam \A_SPW_TOP|rx_data|Mux5~16 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y6_N45
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector384~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector384~0_combout  = ( \A_SPW_TOP|rx_data|mem[40][3]~q  & ( (!\A_SPW_TOP|rx_data|Selector379~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [3])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux5~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[40][3]~q  & ( (\A_SPW_TOP|rx_data|Selector379~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [3])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux5~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Selector379~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[40][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector384~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector384~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector384~0 .lut_mask = 64'h04070407F4F7F4F7;
defparam \A_SPW_TOP|rx_data|Selector384~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y6_N8
dffeas \A_SPW_TOP|rx_data|mem[40][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector384~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[40][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[40][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[40][3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y6_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector546~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector546~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector541~0_combout  & ((\A_SPW_TOP|rx_data|mem[58][3]~q ))) # (\A_SPW_TOP|rx_data|Selector541~0_combout  & 
// (\A_SPW_TOP|rx_data|Mux5~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector541~0_combout  & ((\A_SPW_TOP|rx_data|mem[58][3]~q ))) # (\A_SPW_TOP|rx_data|Selector541~0_combout  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [3])) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .datac(!\A_SPW_TOP|rx_data|Selector541~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[58][3]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector546~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector546~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector546~0 .lut_mask = 64'h03F303F305F505F5;
defparam \A_SPW_TOP|rx_data|Selector546~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y6_N44
dffeas \A_SPW_TOP|rx_data|mem[58][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector546~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[58][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[58][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[58][3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y6_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector528~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector528~0_combout  = ( \A_SPW_TOP|rx_data|mem[56][3]~q  & ( (!\A_SPW_TOP|rx_data|Selector523~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [3]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux5~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[56][3]~q  & ( (\A_SPW_TOP|rx_data|Selector523~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [3]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux5~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Selector523~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[56][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector528~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector528~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector528~0 .lut_mask = 64'h010D010DF1FDF1FD;
defparam \A_SPW_TOP|rx_data|Selector528~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y6_N14
dffeas \A_SPW_TOP|rx_data|mem[56][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector528~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[56][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[56][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[56][3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y6_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector402~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector402~0_combout  = ( \A_SPW_TOP|rx_data|Mux5~20_combout  & ( (!\A_SPW_TOP|rx_data|Selector397~0_combout  & (((\A_SPW_TOP|rx_data|mem[42][3]~q )))) # (\A_SPW_TOP|rx_data|Selector397~0_combout  & 
// (((\A_SPW_TOP|rx_data|state_data_write.00~q )) # (\A_SPW_TOP|SPW|RX|rx_data_flag [3]))) ) ) # ( !\A_SPW_TOP|rx_data|Mux5~20_combout  & ( (!\A_SPW_TOP|rx_data|Selector397~0_combout  & (((\A_SPW_TOP|rx_data|mem[42][3]~q )))) # 
// (\A_SPW_TOP|rx_data|Selector397~0_combout  & (\A_SPW_TOP|SPW|RX|rx_data_flag [3] & ((!\A_SPW_TOP|rx_data|state_data_write.00~q )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Selector397~0_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .datac(!\A_SPW_TOP|rx_data|mem[42][3]~q ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(!\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector402~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector402~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector402~0 .lut_mask = 64'h1B0A1B5F1B0A1B5F;
defparam \A_SPW_TOP|rx_data|Selector402~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y6_N26
dffeas \A_SPW_TOP|rx_data|mem[42][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector402~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[42][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[42][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[42][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y6_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux5~15 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux5~15_combout  = ( \A_SPW_TOP|rx_data|mem[42][3]~q  & ( \A_SPW_TOP|rx_data|wr_ptr [4] & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & ((\A_SPW_TOP|rx_data|mem[56][3]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|mem[58][3]~q )) ) 
// ) ) # ( !\A_SPW_TOP|rx_data|mem[42][3]~q  & ( \A_SPW_TOP|rx_data|wr_ptr [4] & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & ((\A_SPW_TOP|rx_data|mem[56][3]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|mem[58][3]~q )) ) ) ) # ( 
// \A_SPW_TOP|rx_data|mem[42][3]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [4] & ( (\A_SPW_TOP|rx_data|wr_ptr [1]) # (\A_SPW_TOP|rx_data|mem[40][3]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[42][3]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [4] & ( 
// (\A_SPW_TOP|rx_data|mem[40][3]~q  & !\A_SPW_TOP|rx_data|wr_ptr [1]) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[40][3]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[58][3]~q ),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datad(!\A_SPW_TOP|rx_data|mem[56][3]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[42][3]~q ),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux5~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux5~15 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux5~15 .lut_mask = 64'h50505F5F03F303F3;
defparam \A_SPW_TOP|rx_data|Mux5~15 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y6_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux5~19 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux5~19_combout  = ( \A_SPW_TOP|rx_data|Mux5~16_combout  & ( \A_SPW_TOP|rx_data|Mux5~15_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2]) # ((!\A_SPW_TOP|rx_data|wr_ptr [0] & ((\A_SPW_TOP|rx_data|Mux5~17_combout ))) # 
// (\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|Mux5~18_combout ))) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux5~16_combout  & ( \A_SPW_TOP|rx_data|Mux5~15_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & (((!\A_SPW_TOP|rx_data|wr_ptr [0])))) # 
// (\A_SPW_TOP|rx_data|wr_ptr [2] & ((!\A_SPW_TOP|rx_data|wr_ptr [0] & ((\A_SPW_TOP|rx_data|Mux5~17_combout ))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|Mux5~18_combout )))) ) ) ) # ( \A_SPW_TOP|rx_data|Mux5~16_combout  & ( 
// !\A_SPW_TOP|rx_data|Mux5~15_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & (((\A_SPW_TOP|rx_data|wr_ptr [0])))) # (\A_SPW_TOP|rx_data|wr_ptr [2] & ((!\A_SPW_TOP|rx_data|wr_ptr [0] & ((\A_SPW_TOP|rx_data|Mux5~17_combout ))) # (\A_SPW_TOP|rx_data|wr_ptr [0] 
// & (\A_SPW_TOP|rx_data|Mux5~18_combout )))) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux5~16_combout  & ( !\A_SPW_TOP|rx_data|Mux5~15_combout  & ( (\A_SPW_TOP|rx_data|wr_ptr [2] & ((!\A_SPW_TOP|rx_data|wr_ptr [0] & ((\A_SPW_TOP|rx_data|Mux5~17_combout ))) # 
// (\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|Mux5~18_combout )))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datab(!\A_SPW_TOP|rx_data|Mux5~18_combout ),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datad(!\A_SPW_TOP|rx_data|Mux5~17_combout ),
        .datae(!\A_SPW_TOP|rx_data|Mux5~16_combout ),
        .dataf(!\A_SPW_TOP|rx_data|Mux5~15_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux5~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux5~19 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux5~19 .lut_mask = 64'h01510B5BA1F1ABFB;
defparam \A_SPW_TOP|rx_data|Mux5~19 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y6_N21
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector303~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector303~0_combout  = ( \A_SPW_TOP|rx_data|Selector298~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [3]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux5~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector298~0_combout  & ( \A_SPW_TOP|rx_data|mem[31][3]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .datab(!\A_SPW_TOP|rx_data|mem[31][3]~q ),
        .datac(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(!\A_SPW_TOP|rx_data|Selector298~0_combout ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector303~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector303~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector303~0 .lut_mask = 64'h33330F5533330F55;
defparam \A_SPW_TOP|rx_data|Selector303~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y6_N56
dffeas \A_SPW_TOP|rx_data|mem[31][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector303~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[31][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[31][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[31][3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y6_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector123~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector123~0_combout  = ( \A_SPW_TOP|rx_data|Selector118~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [3])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux5~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector118~0_combout  & ( \A_SPW_TOP|rx_data|mem[11][3]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[11][3]~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .datac(!\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector118~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector123~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector123~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector123~0 .lut_mask = 64'h55555555330F330F;
defparam \A_SPW_TOP|rx_data|Selector123~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y6_N56
dffeas \A_SPW_TOP|rx_data|mem[11][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector123~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[11][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[11][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[11][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y6_N45
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector159~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector159~0_combout  = ( \A_SPW_TOP|SPW|RX|rx_data_flag [3] & ( \A_SPW_TOP|rx_data|mem[15][3]~q  & ( ((!\A_SPW_TOP|rx_data|Selector154~0_combout ) # (!\A_SPW_TOP|rx_data|state_data_write.00~q )) # (\A_SPW_TOP|rx_data|Mux5~20_combout ) 
// ) ) ) # ( !\A_SPW_TOP|SPW|RX|rx_data_flag [3] & ( \A_SPW_TOP|rx_data|mem[15][3]~q  & ( (!\A_SPW_TOP|rx_data|Selector154~0_combout ) # ((\A_SPW_TOP|rx_data|Mux5~20_combout  & \A_SPW_TOP|rx_data|state_data_write.00~q )) ) ) ) # ( 
// \A_SPW_TOP|SPW|RX|rx_data_flag [3] & ( !\A_SPW_TOP|rx_data|mem[15][3]~q  & ( (\A_SPW_TOP|rx_data|Selector154~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|rx_data|Mux5~20_combout ))) ) ) ) # ( !\A_SPW_TOP|SPW|RX|rx_data_flag [3] 
// & ( !\A_SPW_TOP|rx_data|mem[15][3]~q  & ( (\A_SPW_TOP|rx_data|Mux5~20_combout  & (\A_SPW_TOP|rx_data|Selector154~0_combout  & \A_SPW_TOP|rx_data|state_data_write.00~q )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|rx_data|Selector154~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .dataf(!\A_SPW_TOP|rx_data|mem[15][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector159~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector159~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector159~0 .lut_mask = 64'h00050F05F0F5FFF5;
defparam \A_SPW_TOP|rx_data|Selector159~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y6_N17
dffeas \A_SPW_TOP|rx_data|mem[15][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector159~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[15][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[15][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[15][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y6_N27
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector267~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector267~0_combout  = ( \A_SPW_TOP|rx_data|mem[27][3]~q  & ( (!\A_SPW_TOP|rx_data|Selector262~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [3])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux5~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[27][3]~q  & ( (\A_SPW_TOP|rx_data|Selector262~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [3])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux5~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Selector262~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[27][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector267~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector267~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector267~0 .lut_mask = 64'h04070407F4F7F4F7;
defparam \A_SPW_TOP|rx_data|Selector267~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y6_N14
dffeas \A_SPW_TOP|rx_data|mem[27][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector267~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[27][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[27][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[27][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y6_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux5~8 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux5~8_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [2] & ( \A_SPW_TOP|rx_data|mem[27][3]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|mem[15][3]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[31][3]~q )) ) 
// ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [2] & ( \A_SPW_TOP|rx_data|mem[27][3]~q  & ( (\A_SPW_TOP|rx_data|mem[11][3]~q ) # (\A_SPW_TOP|rx_data|wr_ptr [4]) ) ) ) # ( \A_SPW_TOP|rx_data|wr_ptr [2] & ( !\A_SPW_TOP|rx_data|mem[27][3]~q  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|mem[15][3]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[31][3]~q )) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [2] & ( !\A_SPW_TOP|rx_data|mem[27][3]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr 
// [4] & \A_SPW_TOP|rx_data|mem[11][3]~q ) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[31][3]~q ),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datac(!\A_SPW_TOP|rx_data|mem[11][3]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[15][3]~q ),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .dataf(!\A_SPW_TOP|rx_data|mem[27][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux5~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux5~8 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux5~8 .lut_mask = 64'h0C0C11DD3F3F11DD;
defparam \A_SPW_TOP|rx_data|Mux5~8 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y6_N27
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector141~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector141~0_combout  = ( \A_SPW_TOP|rx_data|mem[13][3]~q  & ( (!\A_SPW_TOP|rx_data|Selector136~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [3])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux5~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[13][3]~q  & ( (\A_SPW_TOP|rx_data|Selector136~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [3])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux5~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .datac(!\A_SPW_TOP|rx_data|Selector136~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[13][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector141~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector141~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector141~0 .lut_mask = 64'h02070207F2F7F2F7;
defparam \A_SPW_TOP|rx_data|Selector141~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y6_N53
dffeas \A_SPW_TOP|rx_data|mem[13][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector141~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[13][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[13][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[13][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y5_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector105~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector105~0_combout  = ( \A_SPW_TOP|rx_data|mem[9][3]~q  & ( (!\A_SPW_TOP|rx_data|Selector100~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [3]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux5~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[9][3]~q  & ( (\A_SPW_TOP|rx_data|Selector100~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [3]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux5~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .datac(!\A_SPW_TOP|rx_data|Selector100~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[9][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector105~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector105~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector105~0 .lut_mask = 64'h03050305F3F5F3F5;
defparam \A_SPW_TOP|rx_data|Selector105~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y5_N50
dffeas \A_SPW_TOP|rx_data|mem[9][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector105~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[9][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[9][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[9][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y6_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector285~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector285~0_combout  = ( \A_SPW_TOP|rx_data|mem[29][3]~q  & ( (!\A_SPW_TOP|rx_data|Selector280~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [3])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux5~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[29][3]~q  & ( (\A_SPW_TOP|rx_data|Selector280~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [3])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux5~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Selector280~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[29][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector285~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector285~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector285~0 .lut_mask = 64'h04070407F4F7F4F7;
defparam \A_SPW_TOP|rx_data|Selector285~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y6_N50
dffeas \A_SPW_TOP|rx_data|mem[29][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector285~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[29][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[29][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[29][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y6_N21
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector249~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector249~0_combout  = ( \A_SPW_TOP|rx_data|mem[25][3]~q  & ( (!\A_SPW_TOP|rx_data|Selector244~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [3])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux5~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[25][3]~q  & ( (\A_SPW_TOP|rx_data|Selector244~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [3])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux5~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Selector244~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[25][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector249~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector249~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector249~0 .lut_mask = 64'h04070407F4F7F4F7;
defparam \A_SPW_TOP|rx_data|Selector249~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y6_N53
dffeas \A_SPW_TOP|rx_data|mem[25][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector249~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[25][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[25][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[25][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y6_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux5~6 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux5~6_combout  = ( \A_SPW_TOP|rx_data|mem[29][3]~q  & ( \A_SPW_TOP|rx_data|mem[25][3]~q  & ( ((!\A_SPW_TOP|rx_data|wr_ptr [2] & ((\A_SPW_TOP|rx_data|mem[9][3]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|mem[13][3]~q 
// ))) # (\A_SPW_TOP|rx_data|wr_ptr [4]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[29][3]~q  & ( \A_SPW_TOP|rx_data|mem[25][3]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & (((\A_SPW_TOP|rx_data|wr_ptr [4]) # (\A_SPW_TOP|rx_data|mem[9][3]~q )))) # 
// (\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|mem[13][3]~q  & ((!\A_SPW_TOP|rx_data|wr_ptr [4])))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[29][3]~q  & ( !\A_SPW_TOP|rx_data|mem[25][3]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & 
// (((\A_SPW_TOP|rx_data|mem[9][3]~q  & !\A_SPW_TOP|rx_data|wr_ptr [4])))) # (\A_SPW_TOP|rx_data|wr_ptr [2] & (((\A_SPW_TOP|rx_data|wr_ptr [4])) # (\A_SPW_TOP|rx_data|mem[13][3]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[29][3]~q  & ( 
// !\A_SPW_TOP|rx_data|mem[25][3]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [4] & ((!\A_SPW_TOP|rx_data|wr_ptr [2] & ((\A_SPW_TOP|rx_data|mem[9][3]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|mem[13][3]~q )))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datab(!\A_SPW_TOP|rx_data|mem[13][3]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[9][3]~q ),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datae(!\A_SPW_TOP|rx_data|mem[29][3]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[25][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux5~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux5~6 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux5~6 .lut_mask = 64'h1B001B551BAA1BFF;
defparam \A_SPW_TOP|rx_data|Mux5~6 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y6_N45
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector258~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector258~0_combout  = ( \A_SPW_TOP|rx_data|Mux5~20_combout  & ( \A_SPW_TOP|rx_data|mem[26][3]~q  & ( ((!\A_SPW_TOP|rx_data|Selector253~0_combout ) # (\A_SPW_TOP|rx_data|state_data_write.00~q )) # (\A_SPW_TOP|SPW|RX|rx_data_flag [3]) 
// ) ) ) # ( !\A_SPW_TOP|rx_data|Mux5~20_combout  & ( \A_SPW_TOP|rx_data|mem[26][3]~q  & ( (!\A_SPW_TOP|rx_data|Selector253~0_combout ) # ((\A_SPW_TOP|SPW|RX|rx_data_flag [3] & !\A_SPW_TOP|rx_data|state_data_write.00~q )) ) ) ) # ( 
// \A_SPW_TOP|rx_data|Mux5~20_combout  & ( !\A_SPW_TOP|rx_data|mem[26][3]~q  & ( (\A_SPW_TOP|rx_data|Selector253~0_combout  & ((\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|SPW|RX|rx_data_flag [3]))) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux5~20_combout  
// & ( !\A_SPW_TOP|rx_data|mem[26][3]~q  & ( (\A_SPW_TOP|SPW|RX|rx_data_flag [3] & (!\A_SPW_TOP|rx_data|state_data_write.00~q  & \A_SPW_TOP|rx_data|Selector253~0_combout )) ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|Selector253~0_combout ),
        .datae(!\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .dataf(!\A_SPW_TOP|rx_data|mem[26][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector258~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector258~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector258~0 .lut_mask = 64'h0030003FFF30FF3F;
defparam \A_SPW_TOP|rx_data|Selector258~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y6_N17
dffeas \A_SPW_TOP|rx_data|mem[26][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector258~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[26][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[26][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[26][3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y6_N51
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector114~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector114~0_combout  = ( \A_SPW_TOP|rx_data|Selector109~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [3])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux5~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector109~0_combout  & ( \A_SPW_TOP|rx_data|mem[10][3]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .datac(!\A_SPW_TOP|rx_data|mem[10][3]~q ),
        .datad(!\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector109~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector114~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector114~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector114~0 .lut_mask = 64'h0F0F0F0F22772277;
defparam \A_SPW_TOP|rx_data|Selector114~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y6_N32
dffeas \A_SPW_TOP|rx_data|mem[10][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector114~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[10][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[10][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[10][3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y6_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector294~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector294~0_combout  = ( \A_SPW_TOP|rx_data|mem[30][3]~q  & ( (!\A_SPW_TOP|rx_data|Selector289~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [3]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux5~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[30][3]~q  & ( (\A_SPW_TOP|rx_data|Selector289~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [3]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux5~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Selector289~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[30][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector294~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector294~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector294~0 .lut_mask = 64'h010D010DF1FDF1FD;
defparam \A_SPW_TOP|rx_data|Selector294~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y6_N38
dffeas \A_SPW_TOP|rx_data|mem[30][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector294~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[30][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[30][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[30][3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y6_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector150~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector150~0_combout  = ( \A_SPW_TOP|rx_data|Selector145~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [3])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux5~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector145~0_combout  & ( \A_SPW_TOP|rx_data|mem[14][3]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .datac(!\A_SPW_TOP|rx_data|mem[14][3]~q ),
        .datad(!\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector145~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector150~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector150~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector150~0 .lut_mask = 64'h0F0F0F0F22772277;
defparam \A_SPW_TOP|rx_data|Selector150~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y6_N47
dffeas \A_SPW_TOP|rx_data|mem[14][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector150~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[14][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[14][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[14][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y6_N57
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux5~7 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux5~7_combout  = ( \A_SPW_TOP|rx_data|mem[30][3]~q  & ( \A_SPW_TOP|rx_data|mem[14][3]~q  & ( ((!\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|mem[10][3]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[26][3]~q 
// ))) # (\A_SPW_TOP|rx_data|wr_ptr [2]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[30][3]~q  & ( \A_SPW_TOP|rx_data|mem[14][3]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [4] & (((\A_SPW_TOP|rx_data|mem[10][3]~q ) # (\A_SPW_TOP|rx_data|wr_ptr [2])))) # 
// (\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[26][3]~q  & (!\A_SPW_TOP|rx_data|wr_ptr [2]))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[30][3]~q  & ( !\A_SPW_TOP|rx_data|mem[14][3]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [4] & (((!\A_SPW_TOP|rx_data|wr_ptr 
// [2] & \A_SPW_TOP|rx_data|mem[10][3]~q )))) # (\A_SPW_TOP|rx_data|wr_ptr [4] & (((\A_SPW_TOP|rx_data|wr_ptr [2])) # (\A_SPW_TOP|rx_data|mem[26][3]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[30][3]~q  & ( !\A_SPW_TOP|rx_data|mem[14][3]~q  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [2] & ((!\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|mem[10][3]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[26][3]~q )))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[26][3]~q ),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datad(!\A_SPW_TOP|rx_data|mem[10][3]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[30][3]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[14][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux5~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux5~7 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux5~7 .lut_mask = 64'h10D013D31CDC1FDF;
defparam \A_SPW_TOP|rx_data|Mux5~7 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y6_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector276~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector276~0_combout  = ( \A_SPW_TOP|SPW|RX|rx_data_flag [3] & ( (!\A_SPW_TOP|rx_data|Selector271~0_combout  & (((\A_SPW_TOP|rx_data|mem[28][3]~q )))) # (\A_SPW_TOP|rx_data|Selector271~0_combout  & 
// (((!\A_SPW_TOP|rx_data|state_data_write.00~q )) # (\A_SPW_TOP|rx_data|Mux5~20_combout ))) ) ) # ( !\A_SPW_TOP|SPW|RX|rx_data_flag [3] & ( (!\A_SPW_TOP|rx_data|Selector271~0_combout  & (((\A_SPW_TOP|rx_data|mem[28][3]~q )))) # 
// (\A_SPW_TOP|rx_data|Selector271~0_combout  & (\A_SPW_TOP|rx_data|Mux5~20_combout  & ((\A_SPW_TOP|rx_data|state_data_write.00~q )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Selector271~0_combout ),
        .datab(!\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|mem[28][3]~q ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector276~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector276~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector276~0 .lut_mask = 64'h0A1B5F1B0A1B5F1B;
defparam \A_SPW_TOP|rx_data|Selector276~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y6_N35
dffeas \A_SPW_TOP|rx_data|mem[28][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector276~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[28][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[28][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[28][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y6_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector240~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector240~0_combout  = ( \A_SPW_TOP|rx_data|Selector235~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [3])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux5~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector235~0_combout  & ( \A_SPW_TOP|rx_data|mem[24][3]~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[24][3]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector235~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector240~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector240~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector240~0 .lut_mask = 64'h00FF00FF47474747;
defparam \A_SPW_TOP|rx_data|Selector240~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y6_N29
dffeas \A_SPW_TOP|rx_data|mem[24][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector240~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[24][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[24][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[24][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y6_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector96~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector96~0_combout  = ( \A_SPW_TOP|rx_data|Selector91~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [3])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux5~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector91~0_combout  & ( \A_SPW_TOP|rx_data|mem[8][3]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .datac(!\A_SPW_TOP|rx_data|mem[8][3]~q ),
        .datad(!\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector91~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector96~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector96~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector96~0 .lut_mask = 64'h0F0F0F0F22772277;
defparam \A_SPW_TOP|rx_data|Selector96~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y6_N23
dffeas \A_SPW_TOP|rx_data|mem[8][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector96~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[8][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[8][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[8][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y6_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector132~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector132~0_combout  = ( \A_SPW_TOP|rx_data|mem[12][3]~q  & ( (!\A_SPW_TOP|rx_data|Selector127~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [3])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux5~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[12][3]~q  & ( (\A_SPW_TOP|rx_data|Selector127~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [3])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux5~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Selector127~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[12][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector132~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector132~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector132~0 .lut_mask = 64'h04070407F4F7F4F7;
defparam \A_SPW_TOP|rx_data|Selector132~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y6_N44
dffeas \A_SPW_TOP|rx_data|mem[12][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector132~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[12][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[12][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[12][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y6_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux5~5 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux5~5_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [2] & ( \A_SPW_TOP|rx_data|mem[12][3]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [4]) # (\A_SPW_TOP|rx_data|mem[28][3]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [2] & ( 
// \A_SPW_TOP|rx_data|mem[12][3]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|mem[8][3]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[24][3]~q )) ) ) ) # ( \A_SPW_TOP|rx_data|wr_ptr [2] & ( !\A_SPW_TOP|rx_data|mem[12][3]~q 
//  & ( (\A_SPW_TOP|rx_data|mem[28][3]~q  & \A_SPW_TOP|rx_data|wr_ptr [4]) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [2] & ( !\A_SPW_TOP|rx_data|mem[12][3]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|mem[8][3]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr 
// [4] & (\A_SPW_TOP|rx_data|mem[24][3]~q )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[28][3]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[24][3]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[8][3]~q ),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .dataf(!\A_SPW_TOP|rx_data|mem[12][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux5~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux5~5 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux5~5 .lut_mask = 64'h0F3300550F33FF55;
defparam \A_SPW_TOP|rx_data|Mux5~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y6_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux5~9 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux5~9_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [1] & ( \A_SPW_TOP|rx_data|Mux5~5_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & ((\A_SPW_TOP|rx_data|Mux5~7_combout ))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|Mux5~8_combout 
// )) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [1] & ( \A_SPW_TOP|rx_data|Mux5~5_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [0]) # (\A_SPW_TOP|rx_data|Mux5~6_combout ) ) ) ) # ( \A_SPW_TOP|rx_data|wr_ptr [1] & ( !\A_SPW_TOP|rx_data|Mux5~5_combout  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [0] & ((\A_SPW_TOP|rx_data|Mux5~7_combout ))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|Mux5~8_combout )) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [1] & ( !\A_SPW_TOP|rx_data|Mux5~5_combout  & ( 
// (\A_SPW_TOP|rx_data|Mux5~6_combout  & \A_SPW_TOP|rx_data|wr_ptr [0]) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux5~8_combout ),
        .datab(!\A_SPW_TOP|rx_data|Mux5~6_combout ),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datad(!\A_SPW_TOP|rx_data|Mux5~7_combout ),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .dataf(!\A_SPW_TOP|rx_data|Mux5~5_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux5~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux5~9 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux5~9 .lut_mask = 64'h030305F5F3F305F5;
defparam \A_SPW_TOP|rx_data|Mux5~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y5_N21
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector69~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector69~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector64~0_combout  & ((\A_SPW_TOP|rx_data|mem[5][3]~q ))) # (\A_SPW_TOP|rx_data|Selector64~0_combout  & (\A_SPW_TOP|rx_data|Mux5~20_combout 
// )) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector64~0_combout  & ((\A_SPW_TOP|rx_data|mem[5][3]~q ))) # (\A_SPW_TOP|rx_data|Selector64~0_combout  & (\A_SPW_TOP|SPW|RX|rx_data_flag [3])) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .datac(!\A_SPW_TOP|rx_data|Selector64~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[5][3]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector69~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector69~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector69~0 .lut_mask = 64'h03F303F305F505F5;
defparam \A_SPW_TOP|rx_data|Selector69~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y5_N5
dffeas \A_SPW_TOP|rx_data|mem[5][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector69~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[5][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[5][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[5][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y5_N21
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector177~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector177~0_combout  = ( \A_SPW_TOP|rx_data|mem[17][3]~q  & ( (!\A_SPW_TOP|rx_data|Selector172~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [3]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux5~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[17][3]~q  & ( (\A_SPW_TOP|rx_data|Selector172~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [3]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux5~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|Selector172~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[17][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector177~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector177~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector177~0 .lut_mask = 64'h00350035FF35FF35;
defparam \A_SPW_TOP|rx_data|Selector177~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y5_N17
dffeas \A_SPW_TOP|rx_data|mem[17][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector177~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[17][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[17][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[17][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y5_N57
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector213~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector213~0_combout  = ( \A_SPW_TOP|rx_data|mem[21][3]~q  & ( (!\A_SPW_TOP|rx_data|Selector208~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [3])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux5~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[21][3]~q  & ( (\A_SPW_TOP|rx_data|Selector208~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [3])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux5~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .datac(!\A_SPW_TOP|rx_data|Selector208~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[21][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector213~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector213~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector213~0 .lut_mask = 64'h02070207F2F7F2F7;
defparam \A_SPW_TOP|rx_data|Selector213~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y5_N26
dffeas \A_SPW_TOP|rx_data|mem[21][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector213~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[21][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[21][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[21][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y7_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector33~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector33~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( \A_SPW_TOP|rx_data|Selector28~0_combout  & ( \A_SPW_TOP|rx_data|Mux5~20_combout  ) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( 
// \A_SPW_TOP|rx_data|Selector28~0_combout  & ( \A_SPW_TOP|SPW|RX|rx_data_flag [3] ) ) ) # ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( !\A_SPW_TOP|rx_data|Selector28~0_combout  & ( \A_SPW_TOP|rx_data|mem[1][3]~q  ) ) ) # ( 
// !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( !\A_SPW_TOP|rx_data|Selector28~0_combout  & ( \A_SPW_TOP|rx_data|mem[1][3]~q  ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .datac(!\A_SPW_TOP|rx_data|mem[1][3]~q ),
        .datad(!\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .datae(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .dataf(!\A_SPW_TOP|rx_data|Selector28~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector33~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector33~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector33~0 .lut_mask = 64'h0F0F0F0F333300FF;
defparam \A_SPW_TOP|rx_data|Selector33~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y7_N15
cyclonev_lcell_comb \A_SPW_TOP|rx_data|mem[1][3]~feeder (
// Equation(s):
// \A_SPW_TOP|rx_data|mem[1][3]~feeder_combout  = ( \A_SPW_TOP|rx_data|Selector33~0_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector33~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|mem[1][3]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[1][3]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|mem[1][3]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|rx_data|mem[1][3]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y7_N17
dffeas \A_SPW_TOP|rx_data|mem[1][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|rx_data|mem[1][3]~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[1][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[1][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[1][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y5_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux5~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux5~1_combout  = ( \A_SPW_TOP|rx_data|mem[21][3]~q  & ( \A_SPW_TOP|rx_data|mem[1][3]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & (((!\A_SPW_TOP|rx_data|wr_ptr [4]) # (\A_SPW_TOP|rx_data|mem[17][3]~q )))) # (\A_SPW_TOP|rx_data|wr_ptr [2] & 
// (((\A_SPW_TOP|rx_data|wr_ptr [4])) # (\A_SPW_TOP|rx_data|mem[5][3]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[21][3]~q  & ( \A_SPW_TOP|rx_data|mem[1][3]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & (((!\A_SPW_TOP|rx_data|wr_ptr [4]) # 
// (\A_SPW_TOP|rx_data|mem[17][3]~q )))) # (\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|mem[5][3]~q  & (!\A_SPW_TOP|rx_data|wr_ptr [4]))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[21][3]~q  & ( !\A_SPW_TOP|rx_data|mem[1][3]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr 
// [2] & (((\A_SPW_TOP|rx_data|wr_ptr [4] & \A_SPW_TOP|rx_data|mem[17][3]~q )))) # (\A_SPW_TOP|rx_data|wr_ptr [2] & (((\A_SPW_TOP|rx_data|wr_ptr [4])) # (\A_SPW_TOP|rx_data|mem[5][3]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[21][3]~q  & ( 
// !\A_SPW_TOP|rx_data|mem[1][3]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & (((\A_SPW_TOP|rx_data|wr_ptr [4] & \A_SPW_TOP|rx_data|mem[17][3]~q )))) # (\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|mem[5][3]~q  & (!\A_SPW_TOP|rx_data|wr_ptr [4]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[5][3]~q ),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datad(!\A_SPW_TOP|rx_data|mem[17][3]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[21][3]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[1][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux5~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux5~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux5~1 .lut_mask = 64'h101C131FD0DCD3DF;
defparam \A_SPW_TOP|rx_data|Mux5~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y7_N33
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector78~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector78~0_combout  = ( \A_SPW_TOP|rx_data|Selector73~0_combout  & ( \A_SPW_TOP|rx_data|mem[6][3]~q  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [3]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q 
//  & (\A_SPW_TOP|rx_data|Mux5~20_combout )) ) ) ) # ( !\A_SPW_TOP|rx_data|Selector73~0_combout  & ( \A_SPW_TOP|rx_data|mem[6][3]~q  ) ) # ( \A_SPW_TOP|rx_data|Selector73~0_combout  & ( !\A_SPW_TOP|rx_data|mem[6][3]~q  & ( 
// (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [3]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux5~20_combout )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .datac(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .datad(gnd),
        .datae(!\A_SPW_TOP|rx_data|Selector73~0_combout ),
        .dataf(!\A_SPW_TOP|rx_data|mem[6][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector78~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector78~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector78~0 .lut_mask = 64'h00001B1BFFFF1B1B;
defparam \A_SPW_TOP|rx_data|Selector78~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y7_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|mem[6][3]~feeder (
// Equation(s):
// \A_SPW_TOP|rx_data|mem[6][3]~feeder_combout  = ( \A_SPW_TOP|rx_data|Selector78~0_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector78~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|mem[6][3]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[6][3]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|mem[6][3]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|rx_data|mem[6][3]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y7_N44
dffeas \A_SPW_TOP|rx_data|mem[6][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|rx_data|mem[6][3]~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[6][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[6][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[6][3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y5_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector186~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector186~0_combout  = ( \A_SPW_TOP|rx_data|Mux5~20_combout  & ( (!\A_SPW_TOP|rx_data|Selector181~0_combout  & (((\A_SPW_TOP|rx_data|mem[18][3]~q )))) # (\A_SPW_TOP|rx_data|Selector181~0_combout  & 
// (((\A_SPW_TOP|rx_data|state_data_write.00~q )) # (\A_SPW_TOP|SPW|RX|rx_data_flag [3]))) ) ) # ( !\A_SPW_TOP|rx_data|Mux5~20_combout  & ( (!\A_SPW_TOP|rx_data|Selector181~0_combout  & (((\A_SPW_TOP|rx_data|mem[18][3]~q )))) # 
// (\A_SPW_TOP|rx_data|Selector181~0_combout  & (\A_SPW_TOP|SPW|RX|rx_data_flag [3] & (!\A_SPW_TOP|rx_data|state_data_write.00~q ))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Selector181~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[18][3]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector186~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector186~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector186~0 .lut_mask = 64'h04F404F407F707F7;
defparam \A_SPW_TOP|rx_data|Selector186~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y5_N47
dffeas \A_SPW_TOP|rx_data|mem[18][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector186~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[18][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[18][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[18][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y5_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector222~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector222~0_combout  = ( \A_SPW_TOP|rx_data|mem[22][3]~q  & ( \A_SPW_TOP|SPW|RX|rx_data_flag [3] & ( (!\A_SPW_TOP|rx_data|Selector217~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|rx_data|Mux5~20_combout )) 
// ) ) ) # ( !\A_SPW_TOP|rx_data|mem[22][3]~q  & ( \A_SPW_TOP|SPW|RX|rx_data_flag [3] & ( (\A_SPW_TOP|rx_data|Selector217~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|rx_data|Mux5~20_combout ))) ) ) ) # ( 
// \A_SPW_TOP|rx_data|mem[22][3]~q  & ( !\A_SPW_TOP|SPW|RX|rx_data_flag [3] & ( (!\A_SPW_TOP|rx_data|Selector217~0_combout ) # ((\A_SPW_TOP|rx_data|state_data_write.00~q  & \A_SPW_TOP|rx_data|Mux5~20_combout )) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[22][3]~q  & ( 
// !\A_SPW_TOP|SPW|RX|rx_data_flag [3] & ( (\A_SPW_TOP|rx_data|Selector217~0_combout  & (\A_SPW_TOP|rx_data|state_data_write.00~q  & \A_SPW_TOP|rx_data|Mux5~20_combout )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Selector217~0_combout ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|rx_data|mem[22][3]~q ),
        .dataf(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector222~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector222~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector222~0 .lut_mask = 64'h0101ABAB4545EFEF;
defparam \A_SPW_TOP|rx_data|Selector222~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y5_N59
dffeas \A_SPW_TOP|rx_data|mem[22][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector222~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[22][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[22][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[22][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X36_Y5_N9
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector42~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector42~0_combout  = ( \A_SPW_TOP|rx_data|mem[2][3]~q  & ( (!\A_SPW_TOP|rx_data|Selector37~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [3])) # (\A_SPW_TOP|rx_data|state_data_write.00~q 
//  & ((\A_SPW_TOP|rx_data|Mux5~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[2][3]~q  & ( (\A_SPW_TOP|rx_data|Selector37~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [3])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux5~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .datab(!\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector37~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[2][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector42~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector42~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector42~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|rx_data|Selector42~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X36_Y5_N53
dffeas \A_SPW_TOP|rx_data|mem[2][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector42~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[2][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[2][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[2][3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y5_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux5~2 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux5~2_combout  = ( \A_SPW_TOP|rx_data|mem[22][3]~q  & ( \A_SPW_TOP|rx_data|mem[2][3]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [4] & (((!\A_SPW_TOP|rx_data|wr_ptr [2])) # (\A_SPW_TOP|rx_data|mem[6][3]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [4] & 
// (((\A_SPW_TOP|rx_data|wr_ptr [2]) # (\A_SPW_TOP|rx_data|mem[18][3]~q )))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[22][3]~q  & ( \A_SPW_TOP|rx_data|mem[2][3]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [4] & (((!\A_SPW_TOP|rx_data|wr_ptr [2])) # 
// (\A_SPW_TOP|rx_data|mem[6][3]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [4] & (((\A_SPW_TOP|rx_data|mem[18][3]~q  & !\A_SPW_TOP|rx_data|wr_ptr [2])))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[22][3]~q  & ( !\A_SPW_TOP|rx_data|mem[2][3]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr 
// [4] & (\A_SPW_TOP|rx_data|mem[6][3]~q  & ((\A_SPW_TOP|rx_data|wr_ptr [2])))) # (\A_SPW_TOP|rx_data|wr_ptr [4] & (((\A_SPW_TOP|rx_data|wr_ptr [2]) # (\A_SPW_TOP|rx_data|mem[18][3]~q )))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[22][3]~q  & ( 
// !\A_SPW_TOP|rx_data|mem[2][3]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[6][3]~q  & ((\A_SPW_TOP|rx_data|wr_ptr [2])))) # (\A_SPW_TOP|rx_data|wr_ptr [4] & (((\A_SPW_TOP|rx_data|mem[18][3]~q  & !\A_SPW_TOP|rx_data|wr_ptr [2])))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[6][3]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[18][3]~q ),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datae(!\A_SPW_TOP|rx_data|mem[22][3]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[2][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux5~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux5~2 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux5~2 .lut_mask = 64'h0350035FF350F35F;
defparam \A_SPW_TOP|rx_data|Mux5~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y5_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector204~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector204~0_combout  = ( \A_SPW_TOP|rx_data|mem[20][3]~q  & ( (!\A_SPW_TOP|rx_data|Selector199~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [3])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux5~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[20][3]~q  & ( (\A_SPW_TOP|rx_data|Selector199~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [3])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux5~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .datac(!\A_SPW_TOP|rx_data|Selector199~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[20][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector204~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector204~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector204~0 .lut_mask = 64'h02070207F2F7F2F7;
defparam \A_SPW_TOP|rx_data|Selector204~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y5_N35
dffeas \A_SPW_TOP|rx_data|mem[20][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector204~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[20][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[20][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[20][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X36_Y5_N57
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector60~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector60~0_combout  = ( \A_SPW_TOP|rx_data|mem[4][3]~q  & ( (!\A_SPW_TOP|rx_data|Selector55~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [3]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux5~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[4][3]~q  & ( (\A_SPW_TOP|rx_data|Selector55~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [3]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux5~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector55~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[4][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector60~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector60~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector60~0 .lut_mask = 64'h010B010BF1FBF1FB;
defparam \A_SPW_TOP|rx_data|Selector60~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X36_Y5_N2
dffeas \A_SPW_TOP|rx_data|mem[4][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector60~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[4][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[4][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[4][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y7_N39
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector168~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector168~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( \A_SPW_TOP|rx_data|mem[16][3]~q  & ( (!\A_SPW_TOP|rx_data|Selector163~0_combout ) # (\A_SPW_TOP|rx_data|Mux5~20_combout ) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( \A_SPW_TOP|rx_data|mem[16][3]~q  & ( (!\A_SPW_TOP|rx_data|Selector163~0_combout ) # (\A_SPW_TOP|SPW|RX|rx_data_flag [3]) ) ) ) # ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( 
// !\A_SPW_TOP|rx_data|mem[16][3]~q  & ( (\A_SPW_TOP|rx_data|Mux5~20_combout  & \A_SPW_TOP|rx_data|Selector163~0_combout ) ) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( !\A_SPW_TOP|rx_data|mem[16][3]~q  & ( (\A_SPW_TOP|SPW|RX|rx_data_flag [3] & 
// \A_SPW_TOP|rx_data|Selector163~0_combout ) ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .datac(!\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .datad(!\A_SPW_TOP|rx_data|Selector163~0_combout ),
        .datae(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[16][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector168~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector168~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector168~0 .lut_mask = 64'h0033000FFF33FF0F;
defparam \A_SPW_TOP|rx_data|Selector168~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y7_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|mem[16][3]~feeder (
// Equation(s):
// \A_SPW_TOP|rx_data|mem[16][3]~feeder_combout  = ( \A_SPW_TOP|rx_data|Selector168~0_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector168~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|mem[16][3]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[16][3]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|mem[16][3]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|rx_data|mem[16][3]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y7_N20
dffeas \A_SPW_TOP|rx_data|mem[16][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|rx_data|mem[16][3]~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[16][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[16][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[16][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y5_N45
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector24~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector24~0_combout  = ( \A_SPW_TOP|rx_data|mem[0][3]~q  & ( (!\A_SPW_TOP|rx_data|Selector19~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [3])) # (\A_SPW_TOP|rx_data|state_data_write.00~q 
//  & ((\A_SPW_TOP|rx_data|Mux5~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[0][3]~q  & ( (\A_SPW_TOP|rx_data|Selector19~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [3])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux5~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .datac(!\A_SPW_TOP|rx_data|Selector19~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[0][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector24~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector24~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector24~0 .lut_mask = 64'h02070207F2F7F2F7;
defparam \A_SPW_TOP|rx_data|Selector24~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y5_N11
dffeas \A_SPW_TOP|rx_data|mem[0][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector24~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[0][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[0][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[0][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y5_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux5~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux5~0_combout  = ( \A_SPW_TOP|rx_data|mem[16][3]~q  & ( \A_SPW_TOP|rx_data|mem[0][3]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2]) # ((!\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|mem[4][3]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [4] & 
// (\A_SPW_TOP|rx_data|mem[20][3]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[16][3]~q  & ( \A_SPW_TOP|rx_data|mem[0][3]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & (((!\A_SPW_TOP|rx_data|wr_ptr [4])))) # (\A_SPW_TOP|rx_data|wr_ptr [2] & 
// ((!\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|mem[4][3]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[20][3]~q )))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[16][3]~q  & ( !\A_SPW_TOP|rx_data|mem[0][3]~q  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [2] & (((\A_SPW_TOP|rx_data|wr_ptr [4])))) # (\A_SPW_TOP|rx_data|wr_ptr [2] & ((!\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|mem[4][3]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[20][3]~q )))) ) ) 
// ) # ( !\A_SPW_TOP|rx_data|mem[16][3]~q  & ( !\A_SPW_TOP|rx_data|mem[0][3]~q  & ( (\A_SPW_TOP|rx_data|wr_ptr [2] & ((!\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|mem[4][3]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[20][3]~q 
// )))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[20][3]~q ),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datad(!\A_SPW_TOP|rx_data|mem[4][3]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[16][3]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[0][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux5~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux5~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux5~0 .lut_mask = 64'h01310D3DC1F1CDFD;
defparam \A_SPW_TOP|rx_data|Mux5~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y5_N27
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector87~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector87~0_combout  = ( \A_SPW_TOP|SPW|RX|rx_data_flag [3] & ( (!\A_SPW_TOP|rx_data|Selector82~0_combout  & (((\A_SPW_TOP|rx_data|mem[7][3]~q )))) # (\A_SPW_TOP|rx_data|Selector82~0_combout  & 
// ((!\A_SPW_TOP|rx_data|state_data_write.00~q ) # ((\A_SPW_TOP|rx_data|Mux5~20_combout )))) ) ) # ( !\A_SPW_TOP|SPW|RX|rx_data_flag [3] & ( (!\A_SPW_TOP|rx_data|Selector82~0_combout  & (((\A_SPW_TOP|rx_data|mem[7][3]~q )))) # 
// (\A_SPW_TOP|rx_data|Selector82~0_combout  & (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux5~20_combout ))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector82~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[7][3]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector87~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector87~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector87~0 .lut_mask = 64'h01F101F10BFB0BFB;
defparam \A_SPW_TOP|rx_data|Selector87~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y5_N35
dffeas \A_SPW_TOP|rx_data|mem[7][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector87~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[7][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[7][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[7][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y5_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector195~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector195~0_combout  = ( \A_SPW_TOP|rx_data|Selector190~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [3])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux5~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector190~0_combout  & ( \A_SPW_TOP|rx_data|mem[19][3]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .datac(!\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[19][3]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector190~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector195~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector195~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector195~0 .lut_mask = 64'h00FF00FF27272727;
defparam \A_SPW_TOP|rx_data|Selector195~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y5_N29
dffeas \A_SPW_TOP|rx_data|mem[19][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector195~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[19][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[19][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[19][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y5_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector231~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector231~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( \A_SPW_TOP|rx_data|mem[23][3]~q  & ( (!\A_SPW_TOP|rx_data|Selector226~0_combout ) # (\A_SPW_TOP|rx_data|Mux5~20_combout ) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( \A_SPW_TOP|rx_data|mem[23][3]~q  & ( (!\A_SPW_TOP|rx_data|Selector226~0_combout ) # (\A_SPW_TOP|SPW|RX|rx_data_flag [3]) ) ) ) # ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( 
// !\A_SPW_TOP|rx_data|mem[23][3]~q  & ( (\A_SPW_TOP|rx_data|Mux5~20_combout  & \A_SPW_TOP|rx_data|Selector226~0_combout ) ) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( !\A_SPW_TOP|rx_data|mem[23][3]~q  & ( (\A_SPW_TOP|SPW|RX|rx_data_flag [3] & 
// \A_SPW_TOP|rx_data|Selector226~0_combout ) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .datac(!\A_SPW_TOP|rx_data|Selector226~0_combout ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[23][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector231~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector231~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector231~0 .lut_mask = 64'h03030505F3F3F5F5;
defparam \A_SPW_TOP|rx_data|Selector231~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y5_N17
dffeas \A_SPW_TOP|rx_data|mem[23][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector231~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[23][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[23][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[23][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X36_Y5_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector51~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector51~0_combout  = ( \A_SPW_TOP|rx_data|mem[3][3]~q  & ( (!\A_SPW_TOP|rx_data|Selector46~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [3])) # (\A_SPW_TOP|rx_data|state_data_write.00~q 
//  & ((\A_SPW_TOP|rx_data|Mux5~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[3][3]~q  & ( (\A_SPW_TOP|rx_data|Selector46~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [3])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux5~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .datab(!\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector46~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[3][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector51~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector51~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector51~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|rx_data|Selector51~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X36_Y5_N5
dffeas \A_SPW_TOP|rx_data|mem[3][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector51~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[3][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[3][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[3][3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y5_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux5~3 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux5~3_combout  = ( \A_SPW_TOP|rx_data|mem[23][3]~q  & ( \A_SPW_TOP|rx_data|mem[3][3]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & (((!\A_SPW_TOP|rx_data|wr_ptr [4]) # (\A_SPW_TOP|rx_data|mem[19][3]~q )))) # (\A_SPW_TOP|rx_data|wr_ptr [2] & 
// (((\A_SPW_TOP|rx_data|wr_ptr [4])) # (\A_SPW_TOP|rx_data|mem[7][3]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[23][3]~q  & ( \A_SPW_TOP|rx_data|mem[3][3]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & (((!\A_SPW_TOP|rx_data|wr_ptr [4]) # 
// (\A_SPW_TOP|rx_data|mem[19][3]~q )))) # (\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|mem[7][3]~q  & (!\A_SPW_TOP|rx_data|wr_ptr [4]))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[23][3]~q  & ( !\A_SPW_TOP|rx_data|mem[3][3]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr 
// [2] & (((\A_SPW_TOP|rx_data|wr_ptr [4] & \A_SPW_TOP|rx_data|mem[19][3]~q )))) # (\A_SPW_TOP|rx_data|wr_ptr [2] & (((\A_SPW_TOP|rx_data|wr_ptr [4])) # (\A_SPW_TOP|rx_data|mem[7][3]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[23][3]~q  & ( 
// !\A_SPW_TOP|rx_data|mem[3][3]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & (((\A_SPW_TOP|rx_data|wr_ptr [4] & \A_SPW_TOP|rx_data|mem[19][3]~q )))) # (\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|mem[7][3]~q  & (!\A_SPW_TOP|rx_data|wr_ptr [4]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[7][3]~q ),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datad(!\A_SPW_TOP|rx_data|mem[19][3]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[23][3]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[3][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux5~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux5~3 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux5~3 .lut_mask = 64'h101C131FD0DCD3DF;
defparam \A_SPW_TOP|rx_data|Mux5~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y5_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux5~4 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux5~4_combout  = ( \A_SPW_TOP|rx_data|Mux5~3_combout  & ( \A_SPW_TOP|rx_data|wr_ptr [1] & ( (\A_SPW_TOP|rx_data|wr_ptr [0]) # (\A_SPW_TOP|rx_data|Mux5~2_combout ) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux5~3_combout  & ( 
// \A_SPW_TOP|rx_data|wr_ptr [1] & ( (\A_SPW_TOP|rx_data|Mux5~2_combout  & !\A_SPW_TOP|rx_data|wr_ptr [0]) ) ) ) # ( \A_SPW_TOP|rx_data|Mux5~3_combout  & ( !\A_SPW_TOP|rx_data|wr_ptr [1] & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & 
// ((\A_SPW_TOP|rx_data|Mux5~0_combout ))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|Mux5~1_combout )) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux5~3_combout  & ( !\A_SPW_TOP|rx_data|wr_ptr [1] & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & 
// ((\A_SPW_TOP|rx_data|Mux5~0_combout ))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|Mux5~1_combout )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux5~1_combout ),
        .datab(!\A_SPW_TOP|rx_data|Mux5~2_combout ),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datad(!\A_SPW_TOP|rx_data|Mux5~0_combout ),
        .datae(!\A_SPW_TOP|rx_data|Mux5~3_combout ),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux5~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux5~4 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux5~4 .lut_mask = 64'h05F505F530303F3F;
defparam \A_SPW_TOP|rx_data|Mux5~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y5_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector321~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector321~0_combout  = ( \A_SPW_TOP|rx_data|Selector316~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [3]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux5~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector316~0_combout  & ( \A_SPW_TOP|rx_data|mem[33][3]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .datac(!\A_SPW_TOP|rx_data|mem[33][3]~q ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector316~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector321~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector321~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector321~0 .lut_mask = 64'h0F0F0F0F33553355;
defparam \A_SPW_TOP|rx_data|Selector321~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y5_N53
dffeas \A_SPW_TOP|rx_data|mem[33][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector321~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[33][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[33][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[33][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X36_Y5_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector357~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector357~0_combout  = ( \A_SPW_TOP|rx_data|mem[37][3]~q  & ( (!\A_SPW_TOP|rx_data|Selector352~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [3]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux5~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[37][3]~q  & ( (\A_SPW_TOP|rx_data|Selector352~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [3]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux5~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .datac(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .datad(!\A_SPW_TOP|rx_data|Selector352~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[37][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector357~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector357~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector357~0 .lut_mask = 64'h001B001BFF1BFF1B;
defparam \A_SPW_TOP|rx_data|Selector357~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X36_Y5_N14
dffeas \A_SPW_TOP|rx_data|mem[37][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector357~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[37][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[37][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[37][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y5_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector501~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector501~0_combout  = ( \A_SPW_TOP|rx_data|Selector496~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [3])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux5~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector496~0_combout  & ( \A_SPW_TOP|rx_data|mem[53][3]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .datac(!\A_SPW_TOP|rx_data|mem[53][3]~q ),
        .datad(!\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector496~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector501~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector501~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector501~0 .lut_mask = 64'h0F0F0F0F22772277;
defparam \A_SPW_TOP|rx_data|Selector501~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y5_N38
dffeas \A_SPW_TOP|rx_data|mem[53][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector501~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[53][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[53][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[53][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y5_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector465~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector465~0_combout  = ( \A_SPW_TOP|rx_data|mem[49][3]~q  & ( (!\A_SPW_TOP|rx_data|Selector460~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [3])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux5~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[49][3]~q  & ( (\A_SPW_TOP|rx_data|Selector460~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [3])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux5~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .datac(!\A_SPW_TOP|rx_data|Selector460~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[49][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector465~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector465~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector465~0 .lut_mask = 64'h02070207F2F7F2F7;
defparam \A_SPW_TOP|rx_data|Selector465~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y5_N41
dffeas \A_SPW_TOP|rx_data|mem[49][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector465~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[49][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[49][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[49][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y5_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux5~11 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux5~11_combout  = ( \A_SPW_TOP|rx_data|mem[53][3]~q  & ( \A_SPW_TOP|rx_data|mem[49][3]~q  & ( ((!\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|mem[33][3]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [2] & ((\A_SPW_TOP|rx_data|mem[37][3]~q 
// )))) # (\A_SPW_TOP|rx_data|wr_ptr [4]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[53][3]~q  & ( \A_SPW_TOP|rx_data|mem[49][3]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & (((\A_SPW_TOP|rx_data|wr_ptr [4])) # (\A_SPW_TOP|rx_data|mem[33][3]~q ))) # 
// (\A_SPW_TOP|rx_data|wr_ptr [2] & (((!\A_SPW_TOP|rx_data|wr_ptr [4] & \A_SPW_TOP|rx_data|mem[37][3]~q )))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[53][3]~q  & ( !\A_SPW_TOP|rx_data|mem[49][3]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & 
// (\A_SPW_TOP|rx_data|mem[33][3]~q  & (!\A_SPW_TOP|rx_data|wr_ptr [4]))) # (\A_SPW_TOP|rx_data|wr_ptr [2] & (((\A_SPW_TOP|rx_data|mem[37][3]~q ) # (\A_SPW_TOP|rx_data|wr_ptr [4])))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[53][3]~q  & ( 
// !\A_SPW_TOP|rx_data|mem[49][3]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [4] & ((!\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|mem[33][3]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [2] & ((\A_SPW_TOP|rx_data|mem[37][3]~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[33][3]~q ),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datad(!\A_SPW_TOP|rx_data|mem[37][3]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[53][3]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[49][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux5~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux5~11 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux5~11 .lut_mask = 64'h407043734C7C4F7F;
defparam \A_SPW_TOP|rx_data|Mux5~11 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y5_N15
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector474~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector474~0_combout  = ( \A_SPW_TOP|rx_data|Selector469~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [3])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux5~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector469~0_combout  & ( \A_SPW_TOP|rx_data|mem[50][3]~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .datab(!\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[50][3]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector469~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector474~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector474~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector474~0 .lut_mask = 64'h00FF00FF53535353;
defparam \A_SPW_TOP|rx_data|Selector474~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y5_N23
dffeas \A_SPW_TOP|rx_data|mem[50][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector474~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[50][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[50][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[50][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y7_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector366~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector366~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( \A_SPW_TOP|rx_data|mem[38][3]~q  & ( (!\A_SPW_TOP|rx_data|Selector361~0_combout ) # (\A_SPW_TOP|rx_data|Mux5~20_combout ) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( \A_SPW_TOP|rx_data|mem[38][3]~q  & ( (!\A_SPW_TOP|rx_data|Selector361~0_combout ) # (\A_SPW_TOP|SPW|RX|rx_data_flag [3]) ) ) ) # ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( 
// !\A_SPW_TOP|rx_data|mem[38][3]~q  & ( (\A_SPW_TOP|rx_data|Mux5~20_combout  & \A_SPW_TOP|rx_data|Selector361~0_combout ) ) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( !\A_SPW_TOP|rx_data|mem[38][3]~q  & ( 
// (\A_SPW_TOP|rx_data|Selector361~0_combout  & \A_SPW_TOP|SPW|RX|rx_data_flag [3]) ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector361~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .datae(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[38][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector366~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector366~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector366~0 .lut_mask = 64'h000F0303F0FFF3F3;
defparam \A_SPW_TOP|rx_data|Selector366~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y7_N8
dffeas \A_SPW_TOP|rx_data|mem[38][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector366~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[38][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[38][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[38][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X36_Y5_N27
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector330~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector330~0_combout  = ( \A_SPW_TOP|rx_data|Selector325~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [3])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux5~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector325~0_combout  & ( \A_SPW_TOP|rx_data|mem[34][3]~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .datab(!\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[34][3]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector325~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector330~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector330~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector330~0 .lut_mask = 64'h00FF00FF53535353;
defparam \A_SPW_TOP|rx_data|Selector330~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X36_Y5_N23
dffeas \A_SPW_TOP|rx_data|mem[34][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector330~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[34][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[34][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[34][3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y5_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector510~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector510~0_combout  = ( \A_SPW_TOP|rx_data|Selector505~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [3])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux5~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector505~0_combout  & ( \A_SPW_TOP|rx_data|mem[54][3]~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .datab(!\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|mem[54][3]~q ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector505~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector510~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector510~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector510~0 .lut_mask = 64'h0F0F0F0F55335533;
defparam \A_SPW_TOP|rx_data|Selector510~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y5_N35
dffeas \A_SPW_TOP|rx_data|mem[54][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector510~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[54][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[54][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[54][3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y5_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux5~12 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux5~12_combout  = ( \A_SPW_TOP|rx_data|mem[34][3]~q  & ( \A_SPW_TOP|rx_data|mem[54][3]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & (((!\A_SPW_TOP|rx_data|wr_ptr [4])) # (\A_SPW_TOP|rx_data|mem[50][3]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [2] 
// & (((\A_SPW_TOP|rx_data|wr_ptr [4]) # (\A_SPW_TOP|rx_data|mem[38][3]~q )))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[34][3]~q  & ( \A_SPW_TOP|rx_data|mem[54][3]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|mem[50][3]~q  & 
// ((\A_SPW_TOP|rx_data|wr_ptr [4])))) # (\A_SPW_TOP|rx_data|wr_ptr [2] & (((\A_SPW_TOP|rx_data|wr_ptr [4]) # (\A_SPW_TOP|rx_data|mem[38][3]~q )))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[34][3]~q  & ( !\A_SPW_TOP|rx_data|mem[54][3]~q  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [2] & (((!\A_SPW_TOP|rx_data|wr_ptr [4])) # (\A_SPW_TOP|rx_data|mem[50][3]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [2] & (((\A_SPW_TOP|rx_data|mem[38][3]~q  & !\A_SPW_TOP|rx_data|wr_ptr [4])))) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|mem[34][3]~q  & ( !\A_SPW_TOP|rx_data|mem[54][3]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|mem[50][3]~q  & ((\A_SPW_TOP|rx_data|wr_ptr [4])))) # (\A_SPW_TOP|rx_data|wr_ptr [2] & (((\A_SPW_TOP|rx_data|mem[38][3]~q  & 
// !\A_SPW_TOP|rx_data|wr_ptr [4])))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[50][3]~q ),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datac(!\A_SPW_TOP|rx_data|mem[38][3]~q ),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datae(!\A_SPW_TOP|rx_data|mem[34][3]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[54][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux5~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux5~12 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux5~12 .lut_mask = 64'h0344CF440377CF77;
defparam \A_SPW_TOP|rx_data|Mux5~12 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y5_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector492~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector492~0_combout  = ( \A_SPW_TOP|rx_data|Mux5~20_combout  & ( (!\A_SPW_TOP|rx_data|Selector487~0_combout  & (((\A_SPW_TOP|rx_data|mem[52][3]~q )))) # (\A_SPW_TOP|rx_data|Selector487~0_combout  & (((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [3])) # (\A_SPW_TOP|rx_data|state_data_write.00~q ))) ) ) # ( !\A_SPW_TOP|rx_data|Mux5~20_combout  & ( (!\A_SPW_TOP|rx_data|Selector487~0_combout  & (((\A_SPW_TOP|rx_data|mem[52][3]~q )))) # (\A_SPW_TOP|rx_data|Selector487~0_combout  & 
// (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [3]))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .datac(!\A_SPW_TOP|rx_data|mem[52][3]~q ),
        .datad(!\A_SPW_TOP|rx_data|Selector487~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector492~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector492~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector492~0 .lut_mask = 64'h0F220F220F770F77;
defparam \A_SPW_TOP|rx_data|Selector492~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y5_N44
dffeas \A_SPW_TOP|rx_data|mem[52][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector492~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[52][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[52][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[52][3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y6_N39
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector312~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector312~0_combout  = ( \A_SPW_TOP|SPW|RX|rx_data_flag [3] & ( (!\A_SPW_TOP|rx_data|Selector307~0_combout  & (((\A_SPW_TOP|rx_data|mem[32][3]~q )))) # (\A_SPW_TOP|rx_data|Selector307~0_combout  & 
// ((!\A_SPW_TOP|rx_data|state_data_write.00~q ) # ((\A_SPW_TOP|rx_data|Mux5~20_combout )))) ) ) # ( !\A_SPW_TOP|SPW|RX|rx_data_flag [3] & ( (!\A_SPW_TOP|rx_data|Selector307~0_combout  & (((\A_SPW_TOP|rx_data|mem[32][3]~q )))) # 
// (\A_SPW_TOP|rx_data|Selector307~0_combout  & (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux5~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Selector307~0_combout ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[32][3]~q ),
        .datad(!\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector312~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector312~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector312~0 .lut_mask = 64'h0A1B0A1B4E5F4E5F;
defparam \A_SPW_TOP|rx_data|Selector312~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y6_N53
dffeas \A_SPW_TOP|rx_data|mem[32][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector312~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[32][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[32][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[32][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y5_N39
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector456~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector456~0_combout  = ( \A_SPW_TOP|rx_data|Selector451~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [3])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux5~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector451~0_combout  & ( \A_SPW_TOP|rx_data|mem[48][3]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .datac(!\A_SPW_TOP|rx_data|mem[48][3]~q ),
        .datad(!\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector451~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector456~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector456~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector456~0 .lut_mask = 64'h0F0F0F0F22772277;
defparam \A_SPW_TOP|rx_data|Selector456~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y5_N45
cyclonev_lcell_comb \A_SPW_TOP|rx_data|mem[48][3]~feeder (
// Equation(s):
// \A_SPW_TOP|rx_data|mem[48][3]~feeder_combout  = ( \A_SPW_TOP|rx_data|Selector456~0_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector456~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|mem[48][3]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[48][3]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|mem[48][3]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|rx_data|mem[48][3]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y5_N47
dffeas \A_SPW_TOP|rx_data|mem[48][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|rx_data|mem[48][3]~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[48][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[48][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[48][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X36_Y5_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector348~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector348~0_combout  = ( \A_SPW_TOP|SPW|RX|rx_data_flag [3] & ( \A_SPW_TOP|rx_data|Mux5~20_combout  & ( (\A_SPW_TOP|rx_data|mem[36][3]~q ) # (\A_SPW_TOP|rx_data|Selector343~0_combout ) ) ) ) # ( !\A_SPW_TOP|SPW|RX|rx_data_flag [3] & ( 
// \A_SPW_TOP|rx_data|Mux5~20_combout  & ( (!\A_SPW_TOP|rx_data|Selector343~0_combout  & ((\A_SPW_TOP|rx_data|mem[36][3]~q ))) # (\A_SPW_TOP|rx_data|Selector343~0_combout  & (\A_SPW_TOP|rx_data|state_data_write.00~q )) ) ) ) # ( 
// \A_SPW_TOP|SPW|RX|rx_data_flag [3] & ( !\A_SPW_TOP|rx_data|Mux5~20_combout  & ( (!\A_SPW_TOP|rx_data|Selector343~0_combout  & ((\A_SPW_TOP|rx_data|mem[36][3]~q ))) # (\A_SPW_TOP|rx_data|Selector343~0_combout  & (!\A_SPW_TOP|rx_data|state_data_write.00~q 
// )) ) ) ) # ( !\A_SPW_TOP|SPW|RX|rx_data_flag [3] & ( !\A_SPW_TOP|rx_data|Mux5~20_combout  & ( (!\A_SPW_TOP|rx_data|Selector343~0_combout  & \A_SPW_TOP|rx_data|mem[36][3]~q ) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Selector343~0_combout ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[36][3]~q ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .dataf(!\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector348~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector348~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector348~0 .lut_mask = 64'h0A0A4E4E1B1B5F5F;
defparam \A_SPW_TOP|rx_data|Selector348~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X36_Y5_N47
dffeas \A_SPW_TOP|rx_data|mem[36][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector348~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[36][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[36][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[36][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y5_N51
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux5~10 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux5~10_combout  = ( \A_SPW_TOP|rx_data|mem[48][3]~q  & ( \A_SPW_TOP|rx_data|mem[36][3]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [4] & (((\A_SPW_TOP|rx_data|mem[32][3]~q ) # (\A_SPW_TOP|rx_data|wr_ptr [2])))) # (\A_SPW_TOP|rx_data|wr_ptr [4] 
// & (((!\A_SPW_TOP|rx_data|wr_ptr [2])) # (\A_SPW_TOP|rx_data|mem[52][3]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[48][3]~q  & ( \A_SPW_TOP|rx_data|mem[36][3]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [4] & (((\A_SPW_TOP|rx_data|mem[32][3]~q ) # 
// (\A_SPW_TOP|rx_data|wr_ptr [2])))) # (\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[52][3]~q  & (\A_SPW_TOP|rx_data|wr_ptr [2]))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[48][3]~q  & ( !\A_SPW_TOP|rx_data|mem[36][3]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr 
// [4] & (((!\A_SPW_TOP|rx_data|wr_ptr [2] & \A_SPW_TOP|rx_data|mem[32][3]~q )))) # (\A_SPW_TOP|rx_data|wr_ptr [4] & (((!\A_SPW_TOP|rx_data|wr_ptr [2])) # (\A_SPW_TOP|rx_data|mem[52][3]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[48][3]~q  & ( 
// !\A_SPW_TOP|rx_data|mem[36][3]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [4] & (((!\A_SPW_TOP|rx_data|wr_ptr [2] & \A_SPW_TOP|rx_data|mem[32][3]~q )))) # (\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[52][3]~q  & (\A_SPW_TOP|rx_data|wr_ptr [2]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[52][3]~q ),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datad(!\A_SPW_TOP|rx_data|mem[32][3]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[48][3]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[36][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux5~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux5~10 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux5~10 .lut_mask = 64'h01C131F10DCD3DFD;
defparam \A_SPW_TOP|rx_data|Mux5~10 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y5_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector519~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector519~0_combout  = ( \A_SPW_TOP|rx_data|Selector514~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [3])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux5~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector514~0_combout  & ( \A_SPW_TOP|rx_data|mem[55][3]~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .datab(!\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|mem[55][3]~q ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector514~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector519~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector519~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector519~0 .lut_mask = 64'h0F0F0F0F55335533;
defparam \A_SPW_TOP|rx_data|Selector519~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y5_N53
dffeas \A_SPW_TOP|rx_data|mem[55][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector519~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[55][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[55][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[55][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X36_Y5_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector339~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector339~0_combout  = ( \A_SPW_TOP|rx_data|mem[35][3]~q  & ( (!\A_SPW_TOP|rx_data|Selector334~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [3])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux5~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[35][3]~q  & ( (\A_SPW_TOP|rx_data|Selector334~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [3])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux5~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .datab(!\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector334~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[35][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector339~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector339~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector339~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|rx_data|Selector339~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X36_Y5_N41
dffeas \A_SPW_TOP|rx_data|mem[35][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector339~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[35][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[35][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[35][3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y5_N57
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector483~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector483~0_combout  = ( \A_SPW_TOP|rx_data|mem[51][3]~q  & ( (!\A_SPW_TOP|rx_data|Selector478~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [3])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux5~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[51][3]~q  & ( (\A_SPW_TOP|rx_data|Selector478~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [3])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux5~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .datad(!\A_SPW_TOP|rx_data|Selector478~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[51][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector483~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector483~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector483~0 .lut_mask = 64'h00470047FF47FF47;
defparam \A_SPW_TOP|rx_data|Selector483~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y5_N41
dffeas \A_SPW_TOP|rx_data|mem[51][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector483~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[51][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[51][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[51][3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y5_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector375~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector375~0_combout  = ( \A_SPW_TOP|rx_data|mem[39][3]~q  & ( (!\A_SPW_TOP|rx_data|Selector370~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [3])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux5~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[39][3]~q  & ( (\A_SPW_TOP|rx_data|Selector370~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [3])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux5~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .datab(!\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector370~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[39][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector375~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector375~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector375~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|rx_data|Selector375~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y5_N26
dffeas \A_SPW_TOP|rx_data|mem[39][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector375~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[39][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[39][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[39][3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y5_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux5~13 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux5~13_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [4] & ( \A_SPW_TOP|rx_data|mem[39][3]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & ((\A_SPW_TOP|rx_data|mem[51][3]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|mem[55][3]~q )) ) 
// ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [4] & ( \A_SPW_TOP|rx_data|mem[39][3]~q  & ( (\A_SPW_TOP|rx_data|mem[35][3]~q ) # (\A_SPW_TOP|rx_data|wr_ptr [2]) ) ) ) # ( \A_SPW_TOP|rx_data|wr_ptr [4] & ( !\A_SPW_TOP|rx_data|mem[39][3]~q  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [2] & ((\A_SPW_TOP|rx_data|mem[51][3]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|mem[55][3]~q )) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [4] & ( !\A_SPW_TOP|rx_data|mem[39][3]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr 
// [2] & \A_SPW_TOP|rx_data|mem[35][3]~q ) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[55][3]~q ),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datac(!\A_SPW_TOP|rx_data|mem[35][3]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[51][3]~q ),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .dataf(!\A_SPW_TOP|rx_data|mem[39][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux5~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux5~13 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux5~13 .lut_mask = 64'h0C0C11DD3F3F11DD;
defparam \A_SPW_TOP|rx_data|Mux5~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y5_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux5~14 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux5~14_combout  = ( \A_SPW_TOP|rx_data|Mux5~13_combout  & ( \A_SPW_TOP|rx_data|wr_ptr [1] & ( (\A_SPW_TOP|rx_data|wr_ptr [0]) # (\A_SPW_TOP|rx_data|Mux5~12_combout ) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux5~13_combout  & ( 
// \A_SPW_TOP|rx_data|wr_ptr [1] & ( (\A_SPW_TOP|rx_data|Mux5~12_combout  & !\A_SPW_TOP|rx_data|wr_ptr [0]) ) ) ) # ( \A_SPW_TOP|rx_data|Mux5~13_combout  & ( !\A_SPW_TOP|rx_data|wr_ptr [1] & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & 
// ((\A_SPW_TOP|rx_data|Mux5~10_combout ))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|Mux5~11_combout )) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux5~13_combout  & ( !\A_SPW_TOP|rx_data|wr_ptr [1] & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & 
// ((\A_SPW_TOP|rx_data|Mux5~10_combout ))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|Mux5~11_combout )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux5~11_combout ),
        .datab(!\A_SPW_TOP|rx_data|Mux5~12_combout ),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datad(!\A_SPW_TOP|rx_data|Mux5~10_combout ),
        .datae(!\A_SPW_TOP|rx_data|Mux5~13_combout ),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux5~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux5~14 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux5~14 .lut_mask = 64'h05F505F530303F3F;
defparam \A_SPW_TOP|rx_data|Mux5~14 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y5_N9
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux5~20 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux5~20_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [5] & ( \A_SPW_TOP|rx_data|wr_ptr [3] & ( \A_SPW_TOP|rx_data|Mux5~19_combout  ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [5] & ( \A_SPW_TOP|rx_data|wr_ptr [3] & ( 
// \A_SPW_TOP|rx_data|Mux5~9_combout  ) ) ) # ( \A_SPW_TOP|rx_data|wr_ptr [5] & ( !\A_SPW_TOP|rx_data|wr_ptr [3] & ( \A_SPW_TOP|rx_data|Mux5~14_combout  ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [5] & ( !\A_SPW_TOP|rx_data|wr_ptr [3] & ( 
// \A_SPW_TOP|rx_data|Mux5~4_combout  ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux5~19_combout ),
        .datab(!\A_SPW_TOP|rx_data|Mux5~9_combout ),
        .datac(!\A_SPW_TOP|rx_data|Mux5~4_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux5~14_combout ),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux5~20 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux5~20 .lut_mask = 64'h0F0F00FF33335555;
defparam \A_SPW_TOP|rx_data|Mux5~20 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y6_N9
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector438~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector438~0_combout  = ( \A_SPW_TOP|rx_data|mem[46][3]~q  & ( (!\A_SPW_TOP|rx_data|Selector433~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [3])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux5~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[46][3]~q  & ( (\A_SPW_TOP|rx_data|Selector433~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [3])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux5~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Mux5~20_combout ),
        .datad(!\A_SPW_TOP|rx_data|Selector433~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[46][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector438~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector438~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector438~0 .lut_mask = 64'h00470047FF47FF47;
defparam \A_SPW_TOP|rx_data|Selector438~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y6_N41
dffeas \A_SPW_TOP|rx_data|mem[46][3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector438~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[46][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[46][3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[46][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y6_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux14~13 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux14~13_combout  = ( \A_SPW_TOP|rx_data|mem[15][3]~q  & ( \A_SPW_TOP|rx_data|mem[14][3]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [5]) # ((!\A_SPW_TOP|rx_data|rd_ptr [0] & (\A_SPW_TOP|rx_data|mem[46][3]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [0] & 
// ((\A_SPW_TOP|rx_data|mem[47][3]~q )))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[15][3]~q  & ( \A_SPW_TOP|rx_data|mem[14][3]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & (((!\A_SPW_TOP|rx_data|rd_ptr [5])) # (\A_SPW_TOP|rx_data|mem[46][3]~q ))) # 
// (\A_SPW_TOP|rx_data|rd_ptr [0] & (((\A_SPW_TOP|rx_data|mem[47][3]~q  & \A_SPW_TOP|rx_data|rd_ptr [5])))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[15][3]~q  & ( !\A_SPW_TOP|rx_data|mem[14][3]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & 
// (\A_SPW_TOP|rx_data|mem[46][3]~q  & ((\A_SPW_TOP|rx_data|rd_ptr [5])))) # (\A_SPW_TOP|rx_data|rd_ptr [0] & (((!\A_SPW_TOP|rx_data|rd_ptr [5]) # (\A_SPW_TOP|rx_data|mem[47][3]~q )))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[15][3]~q  & ( 
// !\A_SPW_TOP|rx_data|mem[14][3]~q  & ( (\A_SPW_TOP|rx_data|rd_ptr [5] & ((!\A_SPW_TOP|rx_data|rd_ptr [0] & (\A_SPW_TOP|rx_data|mem[46][3]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [0] & ((\A_SPW_TOP|rx_data|mem[47][3]~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[46][3]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[47][3]~q ),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .datae(!\A_SPW_TOP|rx_data|mem[15][3]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[14][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux14~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux14~13 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux14~13 .lut_mask = 64'h00530F53F053FF53;
defparam \A_SPW_TOP|rx_data|Mux14~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y6_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux14~12 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux14~12_combout  = ( \A_SPW_TOP|rx_data|mem[11][3]~q  & ( \A_SPW_TOP|rx_data|mem[43][3]~q  & ( ((!\A_SPW_TOP|rx_data|rd_ptr [5] & (\A_SPW_TOP|rx_data|mem[10][3]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [5] & ((\A_SPW_TOP|rx_data|mem[42][3]~q 
// )))) # (\A_SPW_TOP|rx_data|rd_ptr [0]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[11][3]~q  & ( \A_SPW_TOP|rx_data|mem[43][3]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [5] & (\A_SPW_TOP|rx_data|mem[10][3]~q  & (!\A_SPW_TOP|rx_data|rd_ptr [0]))) # 
// (\A_SPW_TOP|rx_data|rd_ptr [5] & (((\A_SPW_TOP|rx_data|mem[42][3]~q ) # (\A_SPW_TOP|rx_data|rd_ptr [0])))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[11][3]~q  & ( !\A_SPW_TOP|rx_data|mem[43][3]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [5] & (((\A_SPW_TOP|rx_data|rd_ptr 
// [0])) # (\A_SPW_TOP|rx_data|mem[10][3]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [5] & (((!\A_SPW_TOP|rx_data|rd_ptr [0] & \A_SPW_TOP|rx_data|mem[42][3]~q )))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[11][3]~q  & ( !\A_SPW_TOP|rx_data|mem[43][3]~q  & ( 
// (!\A_SPW_TOP|rx_data|rd_ptr [0] & ((!\A_SPW_TOP|rx_data|rd_ptr [5] & (\A_SPW_TOP|rx_data|mem[10][3]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [5] & ((\A_SPW_TOP|rx_data|mem[42][3]~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[10][3]~q ),
        .datab(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .datad(!\A_SPW_TOP|rx_data|mem[42][3]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[11][3]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[43][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux14~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux14~12 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux14~12 .lut_mask = 64'h40704C7C43734F7F;
defparam \A_SPW_TOP|rx_data|Mux14~12 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y6_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux14~11 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux14~11_combout  = ( \A_SPW_TOP|rx_data|rd_ptr [0] & ( \A_SPW_TOP|rx_data|mem[12][3]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [5] & (\A_SPW_TOP|rx_data|mem[13][3]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [5] & ((\A_SPW_TOP|rx_data|mem[45][3]~q ))) 
// ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [0] & ( \A_SPW_TOP|rx_data|mem[12][3]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [5]) # (\A_SPW_TOP|rx_data|mem[44][3]~q ) ) ) ) # ( \A_SPW_TOP|rx_data|rd_ptr [0] & ( !\A_SPW_TOP|rx_data|mem[12][3]~q  & ( 
// (!\A_SPW_TOP|rx_data|rd_ptr [5] & (\A_SPW_TOP|rx_data|mem[13][3]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [5] & ((\A_SPW_TOP|rx_data|mem[45][3]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [0] & ( !\A_SPW_TOP|rx_data|mem[12][3]~q  & ( 
// (\A_SPW_TOP|rx_data|mem[44][3]~q  & \A_SPW_TOP|rx_data|rd_ptr [5]) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[13][3]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[45][3]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[44][3]~q ),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .datae(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .dataf(!\A_SPW_TOP|rx_data|mem[12][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux14~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux14~11 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux14~11 .lut_mask = 64'h000F5533FF0F5533;
defparam \A_SPW_TOP|rx_data|Mux14~11 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y6_N9
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux14~10 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux14~10_combout  = ( \A_SPW_TOP|rx_data|rd_ptr [0] & ( \A_SPW_TOP|rx_data|mem[41][3]~q  & ( (\A_SPW_TOP|rx_data|rd_ptr [5]) # (\A_SPW_TOP|rx_data|mem[9][3]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [0] & ( 
// \A_SPW_TOP|rx_data|mem[41][3]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [5] & ((\A_SPW_TOP|rx_data|mem[8][3]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [5] & (\A_SPW_TOP|rx_data|mem[40][3]~q )) ) ) ) # ( \A_SPW_TOP|rx_data|rd_ptr [0] & ( !\A_SPW_TOP|rx_data|mem[41][3]~q 
//  & ( (\A_SPW_TOP|rx_data|mem[9][3]~q  & !\A_SPW_TOP|rx_data|rd_ptr [5]) ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [0] & ( !\A_SPW_TOP|rx_data|mem[41][3]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [5] & ((\A_SPW_TOP|rx_data|mem[8][3]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr 
// [5] & (\A_SPW_TOP|rx_data|mem[40][3]~q )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[9][3]~q ),
        .datab(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .datac(!\A_SPW_TOP|rx_data|mem[40][3]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[8][3]~q ),
        .datae(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .dataf(!\A_SPW_TOP|rx_data|mem[41][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux14~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux14~10 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux14~10 .lut_mask = 64'h03CF444403CF7777;
defparam \A_SPW_TOP|rx_data|Mux14~10 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y6_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux14~14 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux14~14_combout  = ( \A_SPW_TOP|rx_data|Mux14~10_combout  & ( \A_SPW_TOP|rx_data|rd_ptr [2] & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & ((\A_SPW_TOP|rx_data|Mux14~11_combout ))) # (\A_SPW_TOP|rx_data|rd_ptr [1] & 
// (\A_SPW_TOP|rx_data|Mux14~13_combout )) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux14~10_combout  & ( \A_SPW_TOP|rx_data|rd_ptr [2] & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & ((\A_SPW_TOP|rx_data|Mux14~11_combout ))) # (\A_SPW_TOP|rx_data|rd_ptr [1] & 
// (\A_SPW_TOP|rx_data|Mux14~13_combout )) ) ) ) # ( \A_SPW_TOP|rx_data|Mux14~10_combout  & ( !\A_SPW_TOP|rx_data|rd_ptr [2] & ( (!\A_SPW_TOP|rx_data|rd_ptr [1]) # (\A_SPW_TOP|rx_data|Mux14~12_combout ) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux14~10_combout  & ( 
// !\A_SPW_TOP|rx_data|rd_ptr [2] & ( (\A_SPW_TOP|rx_data|Mux14~12_combout  & \A_SPW_TOP|rx_data|rd_ptr [1]) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux14~13_combout ),
        .datab(!\A_SPW_TOP|rx_data|Mux14~12_combout ),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datad(!\A_SPW_TOP|rx_data|Mux14~11_combout ),
        .datae(!\A_SPW_TOP|rx_data|Mux14~10_combout ),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux14~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux14~14 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux14~14 .lut_mask = 64'h0303F3F305F505F5;
defparam \A_SPW_TOP|rx_data|Mux14~14 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X36_Y5_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux14~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux14~1_combout  = ( \A_SPW_TOP|rx_data|rd_ptr [0] & ( \A_SPW_TOP|rx_data|rd_ptr [5] & ( \A_SPW_TOP|rx_data|mem[37][3]~q  ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [0] & ( \A_SPW_TOP|rx_data|rd_ptr [5] & ( \A_SPW_TOP|rx_data|mem[36][3]~q  ) 
// ) ) # ( \A_SPW_TOP|rx_data|rd_ptr [0] & ( !\A_SPW_TOP|rx_data|rd_ptr [5] & ( \A_SPW_TOP|rx_data|mem[5][3]~q  ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [0] & ( !\A_SPW_TOP|rx_data|rd_ptr [5] & ( \A_SPW_TOP|rx_data|mem[4][3]~q  ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[5][3]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[37][3]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[4][3]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[36][3]~q ),
        .datae(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux14~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux14~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux14~1 .lut_mask = 64'h0F0F555500FF3333;
defparam \A_SPW_TOP|rx_data|Mux14~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y5_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux14~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux14~0_combout  = ( \A_SPW_TOP|rx_data|rd_ptr [0] & ( \A_SPW_TOP|rx_data|mem[1][3]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [5]) # (\A_SPW_TOP|rx_data|mem[33][3]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [0] & ( \A_SPW_TOP|rx_data|mem[1][3]~q 
//  & ( (!\A_SPW_TOP|rx_data|rd_ptr [5] & ((\A_SPW_TOP|rx_data|mem[0][3]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [5] & (\A_SPW_TOP|rx_data|mem[32][3]~q )) ) ) ) # ( \A_SPW_TOP|rx_data|rd_ptr [0] & ( !\A_SPW_TOP|rx_data|mem[1][3]~q  & ( 
// (\A_SPW_TOP|rx_data|mem[33][3]~q  & \A_SPW_TOP|rx_data|rd_ptr [5]) ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [0] & ( !\A_SPW_TOP|rx_data|mem[1][3]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [5] & ((\A_SPW_TOP|rx_data|mem[0][3]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [5] & 
// (\A_SPW_TOP|rx_data|mem[32][3]~q )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[32][3]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[0][3]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[33][3]~q ),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .datae(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .dataf(!\A_SPW_TOP|rx_data|mem[1][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux14~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux14~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux14~0 .lut_mask = 64'h3355000F3355FF0F;
defparam \A_SPW_TOP|rx_data|Mux14~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X36_Y5_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux14~2 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux14~2_combout  = ( \A_SPW_TOP|rx_data|mem[34][3]~q  & ( \A_SPW_TOP|rx_data|rd_ptr [5] & ( (!\A_SPW_TOP|rx_data|rd_ptr [0]) # (\A_SPW_TOP|rx_data|mem[35][3]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[34][3]~q  & ( \A_SPW_TOP|rx_data|rd_ptr 
// [5] & ( (\A_SPW_TOP|rx_data|rd_ptr [0] & \A_SPW_TOP|rx_data|mem[35][3]~q ) ) ) ) # ( \A_SPW_TOP|rx_data|mem[34][3]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [5] & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & (\A_SPW_TOP|rx_data|mem[2][3]~q )) # (\A_SPW_TOP|rx_data|rd_ptr 
// [0] & ((\A_SPW_TOP|rx_data|mem[3][3]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[34][3]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [5] & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & (\A_SPW_TOP|rx_data|mem[2][3]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [0] & 
// ((\A_SPW_TOP|rx_data|mem[3][3]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .datab(!\A_SPW_TOP|rx_data|mem[35][3]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[2][3]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[3][3]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[34][3]~q ),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux14~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux14~2 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux14~2 .lut_mask = 64'h0A5F0A5F1111BBBB;
defparam \A_SPW_TOP|rx_data|Mux14~2 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y5_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux14~3 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux14~3_combout  = ( \A_SPW_TOP|rx_data|mem[38][3]~q  & ( \A_SPW_TOP|rx_data|mem[39][3]~q  & ( ((!\A_SPW_TOP|rx_data|rd_ptr [0] & ((\A_SPW_TOP|rx_data|mem[6][3]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [0] & (\A_SPW_TOP|rx_data|mem[7][3]~q 
// ))) # (\A_SPW_TOP|rx_data|rd_ptr [5]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[38][3]~q  & ( \A_SPW_TOP|rx_data|mem[39][3]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & (((\A_SPW_TOP|rx_data|mem[6][3]~q  & !\A_SPW_TOP|rx_data|rd_ptr [5])))) # 
// (\A_SPW_TOP|rx_data|rd_ptr [0] & (((\A_SPW_TOP|rx_data|rd_ptr [5])) # (\A_SPW_TOP|rx_data|mem[7][3]~q ))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[38][3]~q  & ( !\A_SPW_TOP|rx_data|mem[39][3]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & (((\A_SPW_TOP|rx_data|rd_ptr 
// [5]) # (\A_SPW_TOP|rx_data|mem[6][3]~q )))) # (\A_SPW_TOP|rx_data|rd_ptr [0] & (\A_SPW_TOP|rx_data|mem[7][3]~q  & ((!\A_SPW_TOP|rx_data|rd_ptr [5])))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[38][3]~q  & ( !\A_SPW_TOP|rx_data|mem[39][3]~q  & ( 
// (!\A_SPW_TOP|rx_data|rd_ptr [5] & ((!\A_SPW_TOP|rx_data|rd_ptr [0] & ((\A_SPW_TOP|rx_data|mem[6][3]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [0] & (\A_SPW_TOP|rx_data|mem[7][3]~q )))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[7][3]~q ),
        .datab(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .datac(!\A_SPW_TOP|rx_data|mem[6][3]~q ),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .datae(!\A_SPW_TOP|rx_data|mem[38][3]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[39][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux14~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux14~3 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux14~3 .lut_mask = 64'h1D001DCC1D331DFF;
defparam \A_SPW_TOP|rx_data|Mux14~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X36_Y5_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux14~4 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux14~4_combout  = ( \A_SPW_TOP|rx_data|rd_ptr [1] & ( \A_SPW_TOP|rx_data|rd_ptr [2] & ( \A_SPW_TOP|rx_data|Mux14~3_combout  ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [1] & ( \A_SPW_TOP|rx_data|rd_ptr [2] & ( 
// \A_SPW_TOP|rx_data|Mux14~1_combout  ) ) ) # ( \A_SPW_TOP|rx_data|rd_ptr [1] & ( !\A_SPW_TOP|rx_data|rd_ptr [2] & ( \A_SPW_TOP|rx_data|Mux14~2_combout  ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [1] & ( !\A_SPW_TOP|rx_data|rd_ptr [2] & ( 
// \A_SPW_TOP|rx_data|Mux14~0_combout  ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux14~1_combout ),
        .datab(!\A_SPW_TOP|rx_data|Mux14~0_combout ),
        .datac(!\A_SPW_TOP|rx_data|Mux14~2_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux14~3_combout ),
        .datae(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux14~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux14~4 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux14~4 .lut_mask = 64'h33330F0F555500FF;
defparam \A_SPW_TOP|rx_data|Mux14~4 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y6_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux14~17 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux14~17_combout  = ( \A_SPW_TOP|rx_data|mem[62][3]~q  & ( \A_SPW_TOP|rx_data|mem[30][3]~q  & ( ((!\A_SPW_TOP|rx_data|rd_ptr [5] & (\A_SPW_TOP|rx_data|mem[28][3]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [5] & ((\A_SPW_TOP|rx_data|mem[60][3]~q 
// )))) # (\A_SPW_TOP|rx_data|rd_ptr [1]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[62][3]~q  & ( \A_SPW_TOP|rx_data|mem[30][3]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & ((!\A_SPW_TOP|rx_data|rd_ptr [5] & (\A_SPW_TOP|rx_data|mem[28][3]~q )) # 
// (\A_SPW_TOP|rx_data|rd_ptr [5] & ((\A_SPW_TOP|rx_data|mem[60][3]~q ))))) # (\A_SPW_TOP|rx_data|rd_ptr [1] & (((!\A_SPW_TOP|rx_data|rd_ptr [5])))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[62][3]~q  & ( !\A_SPW_TOP|rx_data|mem[30][3]~q  & ( 
// (!\A_SPW_TOP|rx_data|rd_ptr [1] & ((!\A_SPW_TOP|rx_data|rd_ptr [5] & (\A_SPW_TOP|rx_data|mem[28][3]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [5] & ((\A_SPW_TOP|rx_data|mem[60][3]~q ))))) # (\A_SPW_TOP|rx_data|rd_ptr [1] & (((\A_SPW_TOP|rx_data|rd_ptr [5])))) ) ) 
// ) # ( !\A_SPW_TOP|rx_data|mem[62][3]~q  & ( !\A_SPW_TOP|rx_data|mem[30][3]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & ((!\A_SPW_TOP|rx_data|rd_ptr [5] & (\A_SPW_TOP|rx_data|mem[28][3]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [5] & ((\A_SPW_TOP|rx_data|mem[60][3]~q 
// ))))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[28][3]~q ),
        .datab(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .datad(!\A_SPW_TOP|rx_data|mem[60][3]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[62][3]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[30][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux14~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux14~17 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux14~17 .lut_mask = 64'h404C434F707C737F;
defparam \A_SPW_TOP|rx_data|Mux14~17 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y6_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux14~16 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux14~16_combout  = ( \A_SPW_TOP|rx_data|mem[57][3]~q  & ( \A_SPW_TOP|rx_data|rd_ptr [1] & ( (!\A_SPW_TOP|rx_data|rd_ptr [5] & ((\A_SPW_TOP|rx_data|mem[27][3]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [5] & (\A_SPW_TOP|rx_data|mem[59][3]~q )) 
// ) ) ) # ( !\A_SPW_TOP|rx_data|mem[57][3]~q  & ( \A_SPW_TOP|rx_data|rd_ptr [1] & ( (!\A_SPW_TOP|rx_data|rd_ptr [5] & ((\A_SPW_TOP|rx_data|mem[27][3]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [5] & (\A_SPW_TOP|rx_data|mem[59][3]~q )) ) ) ) # ( 
// \A_SPW_TOP|rx_data|mem[57][3]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [1] & ( (\A_SPW_TOP|rx_data|mem[25][3]~q ) # (\A_SPW_TOP|rx_data|rd_ptr [5]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[57][3]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [1] & ( (!\A_SPW_TOP|rx_data|rd_ptr [5] 
// & \A_SPW_TOP|rx_data|mem[25][3]~q ) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[59][3]~q ),
        .datab(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .datac(!\A_SPW_TOP|rx_data|mem[25][3]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[27][3]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[57][3]~q ),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux14~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux14~16 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux14~16 .lut_mask = 64'h0C0C3F3F11DD11DD;
defparam \A_SPW_TOP|rx_data|Mux14~16 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y6_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux14~15 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux14~15_combout  = ( \A_SPW_TOP|rx_data|rd_ptr [1] & ( \A_SPW_TOP|rx_data|mem[26][3]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [5]) # (\A_SPW_TOP|rx_data|mem[58][3]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [1] & ( 
// \A_SPW_TOP|rx_data|mem[26][3]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [5] & ((\A_SPW_TOP|rx_data|mem[24][3]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [5] & (\A_SPW_TOP|rx_data|mem[56][3]~q )) ) ) ) # ( \A_SPW_TOP|rx_data|rd_ptr [1] & ( 
// !\A_SPW_TOP|rx_data|mem[26][3]~q  & ( (\A_SPW_TOP|rx_data|rd_ptr [5] & \A_SPW_TOP|rx_data|mem[58][3]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [1] & ( !\A_SPW_TOP|rx_data|mem[26][3]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [5] & ((\A_SPW_TOP|rx_data|mem[24][3]~q 
// ))) # (\A_SPW_TOP|rx_data|rd_ptr [5] & (\A_SPW_TOP|rx_data|mem[56][3]~q )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .datab(!\A_SPW_TOP|rx_data|mem[56][3]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[24][3]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[58][3]~q ),
        .datae(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .dataf(!\A_SPW_TOP|rx_data|mem[26][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux14~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux14~15 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux14~15 .lut_mask = 64'h1B1B00551B1BAAFF;
defparam \A_SPW_TOP|rx_data|Mux14~15 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y6_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux14~18 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux14~18_combout  = ( \A_SPW_TOP|rx_data|rd_ptr [5] & ( \A_SPW_TOP|rx_data|mem[61][3]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [1]) # (\A_SPW_TOP|rx_data|mem[63][3]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [5] & ( 
// \A_SPW_TOP|rx_data|mem[61][3]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & ((\A_SPW_TOP|rx_data|mem[29][3]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|mem[31][3]~q )) ) ) ) # ( \A_SPW_TOP|rx_data|rd_ptr [5] & ( 
// !\A_SPW_TOP|rx_data|mem[61][3]~q  & ( (\A_SPW_TOP|rx_data|mem[63][3]~q  & \A_SPW_TOP|rx_data|rd_ptr [1]) ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [5] & ( !\A_SPW_TOP|rx_data|mem[61][3]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & ((\A_SPW_TOP|rx_data|mem[29][3]~q 
// ))) # (\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|mem[31][3]~q )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[63][3]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[31][3]~q ),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datad(!\A_SPW_TOP|rx_data|mem[29][3]~q ),
        .datae(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .dataf(!\A_SPW_TOP|rx_data|mem[61][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux14~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux14~18 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux14~18 .lut_mask = 64'h03F3050503F3F5F5;
defparam \A_SPW_TOP|rx_data|Mux14~18 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y6_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux14~19 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux14~19_combout  = ( \A_SPW_TOP|rx_data|rd_ptr [0] & ( \A_SPW_TOP|rx_data|Mux14~18_combout  & ( (\A_SPW_TOP|rx_data|Mux14~16_combout ) # (\A_SPW_TOP|rx_data|rd_ptr [2]) ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [0] & ( 
// \A_SPW_TOP|rx_data|Mux14~18_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [2] & ((\A_SPW_TOP|rx_data|Mux14~15_combout ))) # (\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|Mux14~17_combout )) ) ) ) # ( \A_SPW_TOP|rx_data|rd_ptr [0] & ( 
// !\A_SPW_TOP|rx_data|Mux14~18_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [2] & \A_SPW_TOP|rx_data|Mux14~16_combout ) ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [0] & ( !\A_SPW_TOP|rx_data|Mux14~18_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [2] & 
// ((\A_SPW_TOP|rx_data|Mux14~15_combout ))) # (\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|Mux14~17_combout )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datab(!\A_SPW_TOP|rx_data|Mux14~17_combout ),
        .datac(!\A_SPW_TOP|rx_data|Mux14~16_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux14~15_combout ),
        .datae(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .dataf(!\A_SPW_TOP|rx_data|Mux14~18_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux14~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux14~19 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux14~19 .lut_mask = 64'h11BB0A0A11BB5F5F;
defparam \A_SPW_TOP|rx_data|Mux14~19 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y5_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux14~8 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux14~8_combout  = ( \A_SPW_TOP|rx_data|mem[23][3]~q  & ( \A_SPW_TOP|rx_data|mem[54][3]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [5] & (((\A_SPW_TOP|rx_data|rd_ptr [0])) # (\A_SPW_TOP|rx_data|mem[22][3]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [5] 
// & (((!\A_SPW_TOP|rx_data|rd_ptr [0]) # (\A_SPW_TOP|rx_data|mem[55][3]~q )))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[23][3]~q  & ( \A_SPW_TOP|rx_data|mem[54][3]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [5] & (\A_SPW_TOP|rx_data|mem[22][3]~q  & 
// ((!\A_SPW_TOP|rx_data|rd_ptr [0])))) # (\A_SPW_TOP|rx_data|rd_ptr [5] & (((!\A_SPW_TOP|rx_data|rd_ptr [0]) # (\A_SPW_TOP|rx_data|mem[55][3]~q )))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[23][3]~q  & ( !\A_SPW_TOP|rx_data|mem[54][3]~q  & ( 
// (!\A_SPW_TOP|rx_data|rd_ptr [5] & (((\A_SPW_TOP|rx_data|rd_ptr [0])) # (\A_SPW_TOP|rx_data|mem[22][3]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [5] & (((\A_SPW_TOP|rx_data|mem[55][3]~q  & \A_SPW_TOP|rx_data|rd_ptr [0])))) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|mem[23][3]~q  & ( !\A_SPW_TOP|rx_data|mem[54][3]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [5] & (\A_SPW_TOP|rx_data|mem[22][3]~q  & ((!\A_SPW_TOP|rx_data|rd_ptr [0])))) # (\A_SPW_TOP|rx_data|rd_ptr [5] & (((\A_SPW_TOP|rx_data|mem[55][3]~q  & 
// \A_SPW_TOP|rx_data|rd_ptr [0])))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .datab(!\A_SPW_TOP|rx_data|mem[22][3]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[55][3]~q ),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .datae(!\A_SPW_TOP|rx_data|mem[23][3]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[54][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux14~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux14~8 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux14~8 .lut_mask = 64'h220522AF770577AF;
defparam \A_SPW_TOP|rx_data|Mux14~8 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y5_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux14~5 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux14~5_combout  = ( \A_SPW_TOP|rx_data|rd_ptr [0] & ( \A_SPW_TOP|rx_data|mem[17][3]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [5]) # (\A_SPW_TOP|rx_data|mem[49][3]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [0] & ( 
// \A_SPW_TOP|rx_data|mem[17][3]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [5] & (\A_SPW_TOP|rx_data|mem[16][3]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [5] & ((\A_SPW_TOP|rx_data|mem[48][3]~q ))) ) ) ) # ( \A_SPW_TOP|rx_data|rd_ptr [0] & ( 
// !\A_SPW_TOP|rx_data|mem[17][3]~q  & ( (\A_SPW_TOP|rx_data|rd_ptr [5] & \A_SPW_TOP|rx_data|mem[49][3]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [0] & ( !\A_SPW_TOP|rx_data|mem[17][3]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [5] & (\A_SPW_TOP|rx_data|mem[16][3]~q 
// )) # (\A_SPW_TOP|rx_data|rd_ptr [5] & ((\A_SPW_TOP|rx_data|mem[48][3]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[16][3]~q ),
        .datab(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .datac(!\A_SPW_TOP|rx_data|mem[48][3]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[49][3]~q ),
        .datae(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .dataf(!\A_SPW_TOP|rx_data|mem[17][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux14~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux14~5 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux14~5 .lut_mask = 64'h474700334747CCFF;
defparam \A_SPW_TOP|rx_data|Mux14~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y5_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux14~6 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux14~6_combout  = ( \A_SPW_TOP|rx_data|mem[53][3]~q  & ( \A_SPW_TOP|rx_data|mem[21][3]~q  & ( ((!\A_SPW_TOP|rx_data|rd_ptr [5] & ((\A_SPW_TOP|rx_data|mem[20][3]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [5] & (\A_SPW_TOP|rx_data|mem[52][3]~q 
// ))) # (\A_SPW_TOP|rx_data|rd_ptr [0]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[53][3]~q  & ( \A_SPW_TOP|rx_data|mem[21][3]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & ((!\A_SPW_TOP|rx_data|rd_ptr [5] & ((\A_SPW_TOP|rx_data|mem[20][3]~q ))) # 
// (\A_SPW_TOP|rx_data|rd_ptr [5] & (\A_SPW_TOP|rx_data|mem[52][3]~q )))) # (\A_SPW_TOP|rx_data|rd_ptr [0] & (((!\A_SPW_TOP|rx_data|rd_ptr [5])))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[53][3]~q  & ( !\A_SPW_TOP|rx_data|mem[21][3]~q  & ( 
// (!\A_SPW_TOP|rx_data|rd_ptr [0] & ((!\A_SPW_TOP|rx_data|rd_ptr [5] & ((\A_SPW_TOP|rx_data|mem[20][3]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [5] & (\A_SPW_TOP|rx_data|mem[52][3]~q )))) # (\A_SPW_TOP|rx_data|rd_ptr [0] & (((\A_SPW_TOP|rx_data|rd_ptr [5])))) ) ) 
// ) # ( !\A_SPW_TOP|rx_data|mem[53][3]~q  & ( !\A_SPW_TOP|rx_data|mem[21][3]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & ((!\A_SPW_TOP|rx_data|rd_ptr [5] & ((\A_SPW_TOP|rx_data|mem[20][3]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [5] & 
// (\A_SPW_TOP|rx_data|mem[52][3]~q )))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .datab(!\A_SPW_TOP|rx_data|mem[52][3]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[20][3]~q ),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .datae(!\A_SPW_TOP|rx_data|mem[53][3]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[21][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux14~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux14~6 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux14~6 .lut_mask = 64'h0A220A775F225F77;
defparam \A_SPW_TOP|rx_data|Mux14~6 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y5_N27
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux14~7 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux14~7_combout  = ( \A_SPW_TOP|rx_data|mem[18][3]~q  & ( \A_SPW_TOP|rx_data|mem[19][3]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [5]) # ((!\A_SPW_TOP|rx_data|rd_ptr [0] & (\A_SPW_TOP|rx_data|mem[50][3]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [0] & 
// ((\A_SPW_TOP|rx_data|mem[51][3]~q )))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[18][3]~q  & ( \A_SPW_TOP|rx_data|mem[19][3]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & (\A_SPW_TOP|rx_data|mem[50][3]~q  & ((\A_SPW_TOP|rx_data|rd_ptr [5])))) # 
// (\A_SPW_TOP|rx_data|rd_ptr [0] & (((!\A_SPW_TOP|rx_data|rd_ptr [5]) # (\A_SPW_TOP|rx_data|mem[51][3]~q )))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[18][3]~q  & ( !\A_SPW_TOP|rx_data|mem[19][3]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & 
// (((!\A_SPW_TOP|rx_data|rd_ptr [5])) # (\A_SPW_TOP|rx_data|mem[50][3]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [0] & (((\A_SPW_TOP|rx_data|mem[51][3]~q  & \A_SPW_TOP|rx_data|rd_ptr [5])))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[18][3]~q  & ( 
// !\A_SPW_TOP|rx_data|mem[19][3]~q  & ( (\A_SPW_TOP|rx_data|rd_ptr [5] & ((!\A_SPW_TOP|rx_data|rd_ptr [0] & (\A_SPW_TOP|rx_data|mem[50][3]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [0] & ((\A_SPW_TOP|rx_data|mem[51][3]~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[50][3]~q ),
        .datab(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .datac(!\A_SPW_TOP|rx_data|mem[51][3]~q ),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .datae(!\A_SPW_TOP|rx_data|mem[18][3]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[19][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux14~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux14~7 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux14~7 .lut_mask = 64'h0047CC473347FF47;
defparam \A_SPW_TOP|rx_data|Mux14~7 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y5_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux14~9 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux14~9_combout  = ( \A_SPW_TOP|rx_data|rd_ptr [2] & ( \A_SPW_TOP|rx_data|rd_ptr [1] & ( \A_SPW_TOP|rx_data|Mux14~8_combout  ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [2] & ( \A_SPW_TOP|rx_data|rd_ptr [1] & ( 
// \A_SPW_TOP|rx_data|Mux14~7_combout  ) ) ) # ( \A_SPW_TOP|rx_data|rd_ptr [2] & ( !\A_SPW_TOP|rx_data|rd_ptr [1] & ( \A_SPW_TOP|rx_data|Mux14~6_combout  ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [2] & ( !\A_SPW_TOP|rx_data|rd_ptr [1] & ( 
// \A_SPW_TOP|rx_data|Mux14~5_combout  ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux14~8_combout ),
        .datab(!\A_SPW_TOP|rx_data|Mux14~5_combout ),
        .datac(!\A_SPW_TOP|rx_data|Mux14~6_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux14~7_combout ),
        .datae(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux14~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux14~9 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux14~9 .lut_mask = 64'h33330F0F00FF5555;
defparam \A_SPW_TOP|rx_data|Mux14~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y6_N39
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux14~20 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux14~20_combout  = ( \A_SPW_TOP|rx_data|Mux14~19_combout  & ( \A_SPW_TOP|rx_data|Mux14~9_combout  & ( ((!\A_SPW_TOP|rx_data|rd_ptr [3] & ((\A_SPW_TOP|rx_data|Mux14~4_combout ))) # (\A_SPW_TOP|rx_data|rd_ptr [3] & 
// (\A_SPW_TOP|rx_data|Mux14~14_combout ))) # (\A_SPW_TOP|rx_data|rd_ptr [4]) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux14~19_combout  & ( \A_SPW_TOP|rx_data|Mux14~9_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & ((!\A_SPW_TOP|rx_data|rd_ptr [3] & 
// ((\A_SPW_TOP|rx_data|Mux14~4_combout ))) # (\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|Mux14~14_combout )))) # (\A_SPW_TOP|rx_data|rd_ptr [4] & (!\A_SPW_TOP|rx_data|rd_ptr [3])) ) ) ) # ( \A_SPW_TOP|rx_data|Mux14~19_combout  & ( 
// !\A_SPW_TOP|rx_data|Mux14~9_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & ((!\A_SPW_TOP|rx_data|rd_ptr [3] & ((\A_SPW_TOP|rx_data|Mux14~4_combout ))) # (\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|Mux14~14_combout )))) # 
// (\A_SPW_TOP|rx_data|rd_ptr [4] & (\A_SPW_TOP|rx_data|rd_ptr [3])) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux14~19_combout  & ( !\A_SPW_TOP|rx_data|Mux14~9_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & ((!\A_SPW_TOP|rx_data|rd_ptr [3] & 
// ((\A_SPW_TOP|rx_data|Mux14~4_combout ))) # (\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|Mux14~14_combout )))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [4]),
        .datab(!\A_SPW_TOP|rx_data|rd_ptr [3]),
        .datac(!\A_SPW_TOP|rx_data|Mux14~14_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux14~4_combout ),
        .datae(!\A_SPW_TOP|rx_data|Mux14~19_combout ),
        .dataf(!\A_SPW_TOP|rx_data|Mux14~9_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux14~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux14~20 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux14~20 .lut_mask = 64'h028A139B46CE57DF;
defparam \A_SPW_TOP|rx_data|Mux14~20 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y6_N41
dffeas \A_SPW_TOP|rx_data|data_out[3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|rx_data|Mux14~20_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|data_out [3]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|data_out[3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|data_out[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y16_N21
cyclonev_lcell_comb \u0|data_flag_rx|read_mux_out[3] (
// Equation(s):
// \u0|data_flag_rx|read_mux_out [3] = ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( \A_SPW_TOP|rx_data|data_out [3] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|rx_data|data_out [3]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|data_flag_rx|read_mux_out [3]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|data_flag_rx|read_mux_out[3] .extended_lut = "off";
defparam \u0|data_flag_rx|read_mux_out[3] .lut_mask = 64'h0F0F000000000000;
defparam \u0|data_flag_rx|read_mux_out[3] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y16_N23
dffeas \u0|data_flag_rx|readdata[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|data_flag_rx|read_mux_out [3]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|data_flag_rx|readdata [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|data_flag_rx|readdata[3] .is_wysiwyg = "true";
defparam \u0|data_flag_rx|readdata[3] .power_up = "low";
// synopsys translate_on

// Location: FF_X23_Y16_N20
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|data_flag_rx|readdata [3]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre[3] .power_up = "low";
// synopsys translate_on

// Location: FF_X23_Y17_N23
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y17_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~3 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~3_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][3]~q  ) ) # ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [3] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [3]),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][3]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~3 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y17_N13
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~3_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y17_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~53 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~53_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][3]~q  & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout  & 
// ((!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout ) # (\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [3]))) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][3]~q  & ( 
// (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout  & (\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [3] & !\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout )) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout ),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [3]),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][3]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~53_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~53 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~53 .lut_mask = 64'h10101010B0B0B0B0;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~53 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y17_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|src_payload~3 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|src_payload~3_combout  = ( \u0|hps_0|fpga_interfaces|h2f_WDATA [3] & ( \u0|mm_interconnect_0|cmd_mux|saved_grant [0] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_WDATA [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux|src_payload~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|src_payload~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|src_payload~3 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux|src_payload~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y17_N32
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux|src_payload~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[3] .power_up = "low";
// synopsys translate_on

// Location: FF_X25_Y17_N44
dffeas \u0|led_pio_test|data_out[3]~_Duplicate_1 (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [3]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|led_pio_test|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|led_pio_test|data_out[3]~_Duplicate_1_q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|led_pio_test|data_out[3]~_Duplicate_1 .is_wysiwyg = "true";
defparam \u0|led_pio_test|data_out[3]~_Duplicate_1 .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y17_N21
cyclonev_lcell_comb \u0|led_pio_test|readdata[3] (
// Equation(s):
// \u0|led_pio_test|readdata [3] = ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( (\u0|led_pio_test|data_out[3]~_Duplicate_1_q  & 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|led_pio_test|data_out[3]~_Duplicate_1_q ),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|led_pio_test|readdata [3]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|led_pio_test|readdata[3] .extended_lut = "off";
defparam \u0|led_pio_test|readdata[3] .lut_mask = 64'h0F000F0000000000;
defparam \u0|led_pio_test|readdata[3] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y17_N23
dffeas \u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|led_pio_test|readdata [3]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre[3] .power_up = "low";
// synopsys translate_on

// Location: FF_X23_Y17_N25
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~3_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y17_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~3 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~3_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][3]~q  ) ) # ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre [3] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][3]~q ),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre [3]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~3 .lut_mask = 64'h0F0F0F0F33333333;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y17_N49
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~3_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y17_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~51 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~51_combout  = (!\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg [0] & (((\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][3]~q )))) # 
// (\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg [0] & ((!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [0] & (\u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre [3])) # 
// (\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [0] & ((\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][3]~q )))))

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg [0]),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [0]),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre [3]),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][3]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~51_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~51 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~51 .lut_mask = 64'h04BF04BF04BF04BF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~51 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y2_N18
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|timecode~4 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|timecode~4_combout  = ( \A_SPW_TOP|SPW|RX|timecode [3] & ( (!\A_SPW_TOP|SPW|RX|timecode~0_combout ) # (\A_SPW_TOP|SPW|RX|dta_timec_p [3]) ) ) # ( !\A_SPW_TOP|SPW|RX|timecode [3] & ( (\A_SPW_TOP|SPW|RX|timecode~0_combout  & 
// \A_SPW_TOP|SPW|RX|dta_timec_p [3]) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|timecode~0_combout ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|RX|dta_timec_p [3]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|timecode [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|timecode~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|timecode~4 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|timecode~4 .lut_mask = 64'h05050505AFAFAFAF;
defparam \A_SPW_TOP|SPW|RX|timecode~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y2_N9
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|timecode[3]~feeder (
// Equation(s):
// \A_SPW_TOP|SPW|RX|timecode[3]~feeder_combout  = ( \A_SPW_TOP|SPW|RX|timecode~4_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|timecode~4_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|timecode[3]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|timecode[3]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|timecode[3]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|SPW|RX|timecode[3]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y2_N11
dffeas \A_SPW_TOP|SPW|RX|timecode[3] (
        .clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(\A_SPW_TOP|SPW|RX|timecode[3]~feeder_combout ),
        .asdata(vcc),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(!\A_SPW_TOP|SPW|RX|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|timecode [3]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|timecode[3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|timecode[3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y14_N30
cyclonev_lcell_comb \u0|timecode_rx|read_mux_out[3] (
// Equation(s):
// \u0|timecode_rx|read_mux_out [3] = ( \A_SPW_TOP|SPW|RX|timecode [3] & ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datad(gnd),
        .datae(!\A_SPW_TOP|SPW|RX|timecode [3]),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|timecode_rx|read_mux_out [3]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|timecode_rx|read_mux_out[3] .extended_lut = "off";
defparam \u0|timecode_rx|read_mux_out[3] .lut_mask = 64'h0000F0F000000000;
defparam \u0|timecode_rx|read_mux_out[3] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y14_N31
dffeas \u0|timecode_rx|readdata[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|timecode_rx|read_mux_out [3]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|timecode_rx|readdata [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|timecode_rx|readdata[3] .is_wysiwyg = "true";
defparam \u0|timecode_rx|readdata[3] .power_up = "low";
// synopsys translate_on

// Location: FF_X25_Y16_N32
dffeas \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|timecode_rx|readdata [3]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[3] .power_up = "low";
// synopsys translate_on

// Location: FF_X25_Y16_N35
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y16_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~3_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][3]~q  & ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1] ) ) # ( 
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][3]~q  & ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [3] ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][3]~q  & ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [3] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [3]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][3]~q ),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~3 .lut_mask = 64'h0F0F0F0F0000FFFF;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y16_N41
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~3_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y16_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~52 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~52_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][3]~q  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0] & ((\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][3]~q ))) # 
// (\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0] & (\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [3])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [3]),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0]),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][3]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~52_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~52 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~52 .lut_mask = 64'h03F303F300FF00FF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~52 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y17_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~54 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~54_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout  & ( ((\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~51_combout  & \u0|mm_interconnect_0|rsp_demux|src1_valid~combout )) # 
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~53_combout ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout  & ( (((\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~51_combout  & \u0|mm_interconnect_0|rsp_demux|src1_valid~combout )) # 
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~52_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~53_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~53_combout ),
        .datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~51_combout ),
        .datac(!\u0|mm_interconnect_0|rsp_demux|src1_valid~combout ),
        .datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~52_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~54_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~54 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~54 .lut_mask = 64'h57FF57FF57575757;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~54 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X54_Y9_N18
cyclonev_lcell_comb \m_x|always10~0 (
// Equation(s):
// \m_x|always10~0_combout  = ( !\m_x|control [1] & ( (!\m_x|control [0] & (\m_x|control [2] & \m_x|last_is_control~q )) ) )

        .dataa(!\m_x|control [0]),
        .datab(!\m_x|control [2]),
        .datac(gnd),
        .datad(!\m_x|last_is_control~q ),
        .datae(gnd),
        .dataf(!\m_x|control [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|always10~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|always10~0 .extended_lut = "off";
defparam \m_x|always10~0 .lut_mask = 64'h0022002200000000;
defparam \m_x|always10~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X53_Y9_N24
cyclonev_lcell_comb \m_x|always10~1 (
// Equation(s):
// \m_x|always10~1_combout  = (\m_x|control_l_r [1] & (\m_x|control_l_r [0] & \m_x|control_l_r [2]))

        .dataa(!\m_x|control_l_r [1]),
        .datab(gnd),
        .datac(!\m_x|control_l_r [0]),
        .datad(!\m_x|control_l_r [2]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|always10~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|always10~1 .extended_lut = "off";
defparam \m_x|always10~1 .lut_mask = 64'h0005000500050005;
defparam \m_x|always10~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X54_Y9_N15
cyclonev_lcell_comb \m_x|rx_got_null~0 (
// Equation(s):
// \m_x|rx_got_null~0_combout  = ( \m_x|rx_got_null~q  & ( (!\m_x|last_is_data~q  & ((!\m_x|always10~0_combout ) # (\m_x|always10~1_combout ))) ) ) # ( !\m_x|rx_got_null~q  & ( (\m_x|always10~0_combout  & (\m_x|always10~1_combout  & !\m_x|last_is_data~q )) ) 
// )

        .dataa(!\m_x|always10~0_combout ),
        .datab(!\m_x|always10~1_combout ),
        .datac(!\m_x|last_is_data~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\m_x|rx_got_null~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|rx_got_null~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|rx_got_null~0 .extended_lut = "off";
defparam \m_x|rx_got_null~0 .lut_mask = 64'h10101010B0B0B0B0;
defparam \m_x|rx_got_null~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X54_Y9_N8
dffeas \m_x|rx_got_null (
        .clk(!\m_x|always3~0_combout ),
        .d(gnd),
        .asdata(\m_x|rx_got_null~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|rx_got_null~q ),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|rx_got_null .is_wysiwyg = "true";
defparam \m_x|rx_got_null .power_up = "low";
// synopsys translate_on

// Location: FF_X53_Y9_N7
dffeas \m_x|info[3] (
        .clk(!\m_x|always3~0_combout ),
        .d(gnd),
        .asdata(\m_x|rx_got_null~q ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\m_x|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|info [3]),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|info[3] .is_wysiwyg = "true";
defparam \m_x|info[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y13_N42
cyclonev_lcell_comb \u0|data_info|read_mux_out[3] (
// Equation(s):
// \u0|data_info|read_mux_out [3] = ( \m_x|info [3] & ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( 
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datac(gnd),
        .datad(gnd),
        .datae(!\m_x|info [3]),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|data_info|read_mux_out [3]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|data_info|read_mux_out[3] .extended_lut = "off";
defparam \u0|data_info|read_mux_out[3] .lut_mask = 64'h0000CCCC00000000;
defparam \u0|data_info|read_mux_out[3] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y13_N43
dffeas \u0|data_info|readdata[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|data_info|read_mux_out [3]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|data_info|readdata [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|data_info|readdata[3] .is_wysiwyg = "true";
defparam \u0|data_info|readdata[3] .power_up = "low";
// synopsys translate_on

// Location: FF_X31_Y16_N53
dffeas \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|data_info|readdata [3]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y15_N3
cyclonev_lcell_comb \u0|fsm_info|read_mux_out[3]~3 (
// Equation(s):
// \u0|fsm_info|read_mux_out[3]~3_combout  = ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & ( (\A_SPW_TOP|SPW|FSM|state_fsm.connecting~q  & 
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|state_fsm.connecting~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|fsm_info|read_mux_out[3]~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|fsm_info|read_mux_out[3]~3 .extended_lut = "off";
defparam \u0|fsm_info|read_mux_out[3]~3 .lut_mask = 64'h5050505000000000;
defparam \u0|fsm_info|read_mux_out[3]~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y15_N5
dffeas \u0|fsm_info|readdata[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|fsm_info|read_mux_out[3]~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|fsm_info|readdata [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|fsm_info|readdata[3] .is_wysiwyg = "true";
defparam \u0|fsm_info|readdata[3] .power_up = "low";
// synopsys translate_on

// Location: FF_X25_Y15_N53
dffeas \u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|fsm_info|readdata [3]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre[3] .power_up = "low";
// synopsys translate_on

// Location: FF_X25_Y15_N59
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~3_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y15_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~3 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~3_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][3]~q  ) ) # ( 
// !\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre [3] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre [3]),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][3]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~3 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y15_N7
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y15_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~55 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~55_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][3]~q  & ( \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0] & ( 
// (!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout  & ((\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0]) # (\u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre [3]))) ) ) ) # ( 
// !\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][3]~q  & ( \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0] & ( (\u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre [3] & 
// (!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout  & !\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0])) ) ) ) # ( \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][3]~q  & ( 
// !\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0] & ( !\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout  ) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre [3]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout ),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0]),
        .datae(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][3]~q ),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~55_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~55 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~55 .lut_mask = 64'h0000F0F0500050F0;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~55 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X31_Y14_N54
cyclonev_lcell_comb \u0|write_data_fifo_tx|readdata[3] (
// Equation(s):
// \u0|write_data_fifo_tx|readdata [3] = (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & \u0|write_data_fifo_tx|data_out [3]))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datad(!\u0|write_data_fifo_tx|data_out [3]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|write_data_fifo_tx|readdata [3]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|write_data_fifo_tx|readdata[3] .extended_lut = "off";
defparam \u0|write_data_fifo_tx|readdata[3] .lut_mask = 64'h00C000C000C000C0;
defparam \u0|write_data_fifo_tx|readdata[3] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y14_N56
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|write_data_fifo_tx|readdata [3]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y14_N48
cyclonev_lcell_comb \u0|counter_tx_fifo|read_mux_out[3]~3 (
// Equation(s):
// \u0|counter_tx_fifo|read_mux_out[3]~3_combout  = ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( \A_SPW_TOP|tx_data|counter [3] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|tx_data|counter [3]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|counter_tx_fifo|read_mux_out[3]~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|counter_tx_fifo|read_mux_out[3]~3 .extended_lut = "off";
defparam \u0|counter_tx_fifo|read_mux_out[3]~3 .lut_mask = 64'h0F0F000000000000;
defparam \u0|counter_tx_fifo|read_mux_out[3]~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y14_N50
dffeas \u0|counter_tx_fifo|readdata[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|counter_tx_fifo|read_mux_out[3]~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|counter_tx_fifo|readdata [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|counter_tx_fifo|readdata[3] .is_wysiwyg = "true";
defparam \u0|counter_tx_fifo|readdata[3] .power_up = "low";
// synopsys translate_on

// Location: FF_X27_Y14_N49
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|counter_tx_fifo|readdata [3]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre[3] .power_up = "low";
// synopsys translate_on

// Location: FF_X27_Y15_N56
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~3_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y15_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~3 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~3_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [3] & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [1]) # 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][3]~q ) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [3] & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][3]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][3]~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~3 .lut_mask = 64'h03030303CFCFCFCF;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y15_N53
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~3_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y15_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~56 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~56_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0] & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout  & 
// ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0] & (\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [3])) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0] & 
// ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][3]~q ))))) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0] & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout  & 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][3]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0]),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [3]),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][3]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~56_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~56 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~56 .lut_mask = 64'h00CC00CC084C084C;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~56 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X31_Y14_N39
cyclonev_lcell_comb \u0|counter_rx_fifo|read_mux_out[3]~3 (
// Equation(s):
// \u0|counter_rx_fifo|read_mux_out[3]~3_combout  = ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & ( 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & \A_SPW_TOP|rx_data|counter [3]) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datad(!\A_SPW_TOP|rx_data|counter [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|counter_rx_fifo|read_mux_out[3]~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|counter_rx_fifo|read_mux_out[3]~3 .extended_lut = "off";
defparam \u0|counter_rx_fifo|read_mux_out[3]~3 .lut_mask = 64'h00F000F000000000;
defparam \u0|counter_rx_fifo|read_mux_out[3]~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y14_N40
dffeas \u0|counter_rx_fifo|readdata[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|counter_rx_fifo|read_mux_out[3]~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|counter_rx_fifo|readdata [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|counter_rx_fifo|readdata[3] .is_wysiwyg = "true";
defparam \u0|counter_rx_fifo|readdata[3] .power_up = "low";
// synopsys translate_on

// Location: FF_X31_Y15_N5
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|counter_rx_fifo|readdata [3]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre[3] .power_up = "low";
// synopsys translate_on

// Location: FF_X31_Y15_N2
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~3_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y15_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~3 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~3_combout  = (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [1] & (\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [3])) # 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [1] & ((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][3]~q )))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [3]),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][3]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~3 .lut_mask = 64'h0C3F0C3F0C3F0C3F;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y15_N17
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~3_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y15_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~57 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~57_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0] & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout  & 
// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0] & (\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [3])) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0] & 
// ((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][3]~q ))))) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0] & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout  & 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][3]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [3]),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0]),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][3]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~57_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~57 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~57 .lut_mask = 64'h00F000F040704070;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~57 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y15_N50
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y15_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~3 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~3_combout  = (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1] & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [3])) # 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1] & ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][3]~q )))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [3]),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][3]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~3 .lut_mask = 64'h0C3F0C3F0C3F0C3F;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y15_N2
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~3_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y15_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~226 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~226_combout  = ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout  & ( ((((\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout  & 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][3]~q )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~57_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~56_combout )) # 
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~55_combout ) ) ) # ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout  & ( ((((\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout  & 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [3])) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~57_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~56_combout )) # 
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~55_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ),
        .datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~55_combout ),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [3]),
        .datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~56_combout ),
        .datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout ),
        .dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~57_combout ),
        .datag(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][3]~q ),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~226_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~226 .extended_lut = "on";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~226 .lut_mask = 64'h37FF37FFFFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~226 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y16_N59
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y16_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~3 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~3_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][3]~q  ) ) # ( 
// !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [3] ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [3]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][3]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~3 .lut_mask = 64'h5555555500FF00FF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y16_N11
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~3_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][3]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y16_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~222 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~222_combout  = ( !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout  & ( ((((\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][3]~q  & 
// \u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~226_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~54_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~50_combout ) ) ) # 
// ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout  & ( ((((\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [3] & \u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout )) # 
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~226_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~54_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~50_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~50_combout ),
        .datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~54_combout ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [3]),
        .datad(!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ),
        .datae(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout ),
        .dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~226_combout ),
        .datag(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][3]~q ),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~222_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~222 .extended_lut = "on";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~222 .lut_mask = 64'h777F777FFFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~222 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y31_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal1~1 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal1~1_combout  = ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [14] & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [12] & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [10] & !\u0|hps_0|fpga_interfaces|h2f_ARADDR [11])) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [12]),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [10]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [11]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [14]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router_001|Equal1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal1~1 .lut_mask = 64'hA000A00000000000;
defparam \u0|mm_interconnect_0|router_001|Equal1~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y31_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal4~0 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal4~0_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & ( \u0|mm_interconnect_0|router_001|Equal2~0_combout  & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & 
// (\u0|mm_interconnect_0|router_001|Equal1~1_combout  & \u0|mm_interconnect_0|router_001|Equal1~0_combout ))) ) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),
        .datac(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),
        .datad(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),
        .dataf(!\u0|mm_interconnect_0|router_001|Equal2~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router_001|Equal4~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal4~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal4~0 .lut_mask = 64'h0000000000000008;
defparam \u0|mm_interconnect_0|router_001|Equal4~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y31_N58
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[17] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|router_001|Equal4~0_combout ),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [17]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[17] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[17] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y33_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_017|last_cycle~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_017|last_cycle~0_combout  = ( \u0|mm_interconnect_0|router_001|Equal4~0_combout  & ( (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [17]))) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [17]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|router_001|Equal4~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_017|last_cycle~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_017|last_cycle~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_017|last_cycle~0 .lut_mask = 64'h0000000050555055;
defparam \u0|mm_interconnect_0|cmd_mux_017|last_cycle~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y33_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_017|packet_in_progress~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_017|packet_in_progress~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_017|last_cycle~0_combout  & ( (!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] & ((\u0|mm_interconnect_0|cmd_mux_017|packet_in_progress~q ))) # 
// (\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] & (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_017|last_cycle~0_combout  & ( 
// \u0|mm_interconnect_0|cmd_mux_017|packet_in_progress~q  ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|cmd_mux_017|packet_in_progress~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_017|last_cycle~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_017|packet_in_progress~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_017|packet_in_progress~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_017|packet_in_progress~0 .lut_mask = 64'h00FF00FF11DD11DD;
defparam \u0|mm_interconnect_0|cmd_mux_017|packet_in_progress~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y33_N38
dffeas \u0|mm_interconnect_0|cmd_mux_017|packet_in_progress (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_017|packet_in_progress~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_017|packet_in_progress~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_017|packet_in_progress .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_017|packet_in_progress .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y33_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_017|update_grant~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_017|update_grant~0_combout  = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout  & ( (!\u0|mm_interconnect_0|cmd_mux_017|packet_in_progress~q  & 
// ((!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]) # (!\u0|mm_interconnect_0|cmd_mux_017|last_cycle~0_combout ))) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout  & ( 
// (!\u0|mm_interconnect_0|cmd_mux_017|packet_in_progress~q ) # ((\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] & \u0|mm_interconnect_0|cmd_mux_017|last_cycle~0_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_017|packet_in_progress~q ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_017|last_cycle~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_017|update_grant~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_017|update_grant~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_017|update_grant~0 .lut_mask = 64'hABABABABA8A8A8A8;
defparam \u0|mm_interconnect_0|cmd_mux_017|update_grant~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y33_N11
dffeas \u0|mm_interconnect_0|cmd_mux_017|saved_grant[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_017|last_cycle~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|cmd_mux_017|update_grant~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_017|saved_grant[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_017|saved_grant[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X23_Y33_N53
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y33_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0_combout  = ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & ( 
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q  & ( (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & 
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & 
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]))) ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & ( 
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q  & ( (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & 
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2])) ) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .datae(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0 .lut_mask = 64'hA000000080000000;
defparam \u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y33_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg~0_combout  = ( \u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override~q  & ( (!\u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0_combout  & 
// (\u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter [0] & \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~0_combout )) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0_combout ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter [0]),
        .datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg~0 .lut_mask = 64'h00000000000C000C;
defparam \u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y33_N44
dffeas \u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y33_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[0]~0_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|read~0_combout  & ( ((\u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg [0] & 
// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|read~0_combout  & ( 
// ((\u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1])) # (\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [0]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg [0]),
        .datac(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|read~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h30FF30FF0F3F0F3F;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y33_N26
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y33_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|rp_valid (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout  = ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [0] & ( ((\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][129]~q ) # 
// (\u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [0]) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [0] & ( 
// (\u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg [0]) # (\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [0]) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg [0]),
        .datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent|rp_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent|rp_valid .lut_mask = 64'h5F5F5F5F5FFF5FFF;
defparam \u0|mm_interconnect_0|data_info_s1_agent|rp_valid .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y18_N30
cyclonev_lcell_comb \u0|timecode_tx_data|readdata[2] (
// Equation(s):
// \u0|timecode_tx_data|readdata [2] = ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & \u0|timecode_tx_data|data_out [2]) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datab(gnd),
        .datac(!\u0|timecode_tx_data|data_out [2]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|timecode_tx_data|readdata [2]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|timecode_tx_data|readdata[2] .extended_lut = "off";
defparam \u0|timecode_tx_data|readdata[2] .lut_mask = 64'h0A0A0A0A00000000;
defparam \u0|timecode_tx_data|readdata[2] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y18_N32
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|timecode_tx_data|readdata [2]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre[2] .power_up = "low";
// synopsys translate_on

// Location: FF_X28_Y16_N29
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y16_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~2_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][2]~q  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [2] ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [2]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][2]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~2 .lut_mask = 64'h5555555500FF00FF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y16_N50
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~2_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y16_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~47 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~47_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][2]~q  & ( ((!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0]) # 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [2]) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][2]~q  & ( 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [2] & (\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0])) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [2]),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~47_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~47 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~47 .lut_mask = 64'h10101010DFDFDFDF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~47 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y22_N8
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][69] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][69]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][69] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y22_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~1 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~1_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & ( (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]) # 
// (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][69]~q ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & ( (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] 
// & \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][69]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][69]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y22_N23
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][69] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][69]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][69] .power_up = "low";
// synopsys translate_on

// Location: FF_X28_Y20_N2
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][68] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~2_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][68]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][68] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][68] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y20_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~2 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~2_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][68]~q  ) ) # ( 
// !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][68]~q ),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~2 .lut_mask = 64'h00FF00FF0F0F0F0F;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y22_N35
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][68] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~2_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][68]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][68] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][68] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y22_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_018|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_018|WideOr0~0_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][68]~q  & ( (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][66]~q  & 
// ((!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][69]~q  & ((\u0|hps_0|fpga_interfaces|h2f_BREADY [0]))) # (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][69]~q  & (\u0|hps_0|fpga_interfaces|h2f_RREADY [0])))) # 
// (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][66]~q  & (\u0|hps_0|fpga_interfaces|h2f_RREADY [0])) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][68]~q  & ( \u0|hps_0|fpga_interfaces|h2f_RREADY [0] ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][66]~q ),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_BREADY [0]),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][69]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][68]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_demux_018|WideOr0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_018|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_018|WideOr0~0 .lut_mask = 64'h333333331B331B33;
defparam \u0|mm_interconnect_0|rsp_demux_018|WideOr0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y22_N50
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][129] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][129]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y22_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~0_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][129]~q  & ( \u0|mm_interconnect_0|clock_sel_s1_agent|WideOr0~0_combout  & ( 
// (((\u0|mm_interconnect_0|clock_sel_s1_agent|local_write~0_combout  & \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout )) # (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used 
// [1])) # (\u0|mm_interconnect_0|clock_sel_s1_agent|m0_read~0_combout ) ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][129]~q  & ( \u0|mm_interconnect_0|clock_sel_s1_agent|WideOr0~0_combout  & ( 
// (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & (((\u0|mm_interconnect_0|clock_sel_s1_agent|local_write~0_combout  & \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout 
// )) # (\u0|mm_interconnect_0|clock_sel_s1_agent|m0_read~0_combout ))) ) ) ) # ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][129]~q  & ( !\u0|mm_interconnect_0|clock_sel_s1_agent|WideOr0~0_combout  & ( 
// ((\u0|mm_interconnect_0|clock_sel_s1_agent|local_write~0_combout  & \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout )) # (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]) 
// ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][129]~q  & ( !\u0|mm_interconnect_0|clock_sel_s1_agent|WideOr0~0_combout  & ( (\u0|mm_interconnect_0|clock_sel_s1_agent|local_write~0_combout  & 
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1])) ) ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent|local_write~0_combout ),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_agent|m0_read~0_combout ),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),
        .datae(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][129]~q ),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent|WideOr0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~0 .lut_mask = 64'h050005FF370037FF;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y22_N41
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][129] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][129]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y22_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|read~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|read~0_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg [0] & ( (\u0|mm_interconnect_0|rsp_demux_018|WideOr0~0_combout  & 
// ((!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [0]) # (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][129]~q ))) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg [0] & ( 
// (\u0|mm_interconnect_0|rsp_demux_018|WideOr0~0_combout  & (\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [0] & ((!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [0]) # 
// (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][129]~q )))) ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [0]),
        .datab(!\u0|mm_interconnect_0|rsp_demux_018|WideOr0~0_combout ),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [0]),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|read~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|read~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|read~0 .lut_mask = 64'h0302030233223322;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|read~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y22_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used[1]~1_combout  = ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|read~0_combout  & ( ((\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [0] & 
// \u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [1]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [0]),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|read~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used[1]~1 .lut_mask = 64'h0F3F0F3F00000000;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used[1]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y22_N47
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y22_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used[0]~0_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|read~0_combout  & ( ((\u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg [0] & 
// \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|read~0_combout  & ( 
// ((\u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [1])) # (\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [0]) ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|read~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h50FF50FF0F5F0F5F;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y22_N44
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y17_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_payload~2 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|src_payload~2_combout  = ( \u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_WDATA [2] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_WDATA [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_018|src_payload~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|src_payload~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|src_payload~2 .lut_mask = 64'h000000000000FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_018|src_payload~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y17_N22
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_018|src_payload~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X59_Y13_N15
cyclonev_lcell_comb \u0|clock_sel|data_out[2]~feeder (
// Equation(s):
// \u0|clock_sel|data_out[2]~feeder_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [2] )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|clock_sel|data_out[2]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|clock_sel|data_out[2]~feeder .extended_lut = "off";
defparam \u0|clock_sel|data_out[2]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|clock_sel|data_out[2]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y20_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|m0_write (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent|m0_write~combout  = ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ( (!\u0|mm_interconnect_0|clock_sel_s1_agent|WideOr0~0_combout  & 
// \u0|mm_interconnect_0|clock_sel_s1_agent|local_write~0_combout ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_agent|WideOr0~0_combout ),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_agent|local_write~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_agent|m0_write~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|m0_write .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|m0_write .lut_mask = 64'h00F000F000000000;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|m0_write .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y20_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_data[81] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|src_data [81] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~0_combout  & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout  & \u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]) ) ) 
// # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~0_combout  & ( ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout  & \u0|mm_interconnect_0|cmd_mux_018|saved_grant [1])) # (\u0|mm_interconnect_0|cmd_mux_018|saved_grant 
// [0]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_018|src_data [81]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[81] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[81] .lut_mask = 64'h55F555F500F000F0;
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[81] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y20_N14
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_018|src_data [81]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .power_up = "low";
// synopsys translate_on

// Location: FF_X28_Y20_N58
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y20_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_data[86] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|src_data [86] = ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [0] & ( ((\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [0])) # (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0] & ( (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_018|src_data [86]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[86] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[86] .lut_mask = 64'h0303030357575757;
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[86] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y20_N8
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_018|src_data [86]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X27_Y20_N29
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_018|src_data [87]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X27_Y20_N59
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_018|src_data [88]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y20_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// (\u0|mm_interconnect_0|cmd_mux_018|src_data [87] & !\u0|mm_interconnect_0|cmd_mux_018|src_data [88]) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]) ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_018|src_data [87]),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_018|src_data [88]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .lut_mask = 64'h5050505033003300;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y20_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  & ( 
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]))) # 
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|cmd_mux_018|src_data [86])) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_018|src_data [86]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .lut_mask = 64'h00000000F0AAF0AA;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y20_N5
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y20_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// (!\u0|mm_interconnect_0|cmd_mux_018|src_data [88] & !\u0|mm_interconnect_0|cmd_mux_018|src_data [87]) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_018|src_data [88]),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_018|src_data [87]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .lut_mask = 64'hC0C0C0C0AA00AA00;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y20_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  & ( 
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]))) # 
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|cmd_mux_018|src_data [86])) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_018|src_data [86]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .lut_mask = 64'h000000000F550F55;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y20_N23
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y20_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_data[79] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|src_data [79] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout  & ( (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~2_combout ) ) ) 
// # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout  & ( ((\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~2_combout )) # (\u0|mm_interconnect_0|cmd_mux_018|saved_grant 
// [0]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~2_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_018|src_data [79]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[79] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[79] .lut_mask = 64'h7575757530303030;
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[79] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y20_N29
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_018|src_data [79]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y20_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  = ( 
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  & ( (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) # (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ((!\u0|mm_interconnect_0|cmd_mux_018|src_data [86]))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_018|src_data [86]),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .lut_mask = 64'h00000000CCF0CCF0;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y20_N19
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y20_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout  = SUM(( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) + ( 
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14  = CARRY(( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) + ( 
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
        .cout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .lut_mask = 64'h0000FF00000000FF;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y20_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0] = ( \u0|mm_interconnect_0|cmd_mux_018|src_data [79] & ( 
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0] & 
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_018|src_data [79] & ( 
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout  & ((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]) # 
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_018|src_data [79]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .lut_mask = 64'h00F300F300C000C0;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y20_N49
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y22_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [0] & ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout  & ( (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]) # (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]) ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [0] 
// & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout  & ( \u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [0] & ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout  & ( \u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
        .datad(gnd),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [0]),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .lut_mask = 64'h000033330F0F3F3F;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y20_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0] & ( 
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  & ( (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # 
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ) ) ) ) # ( 
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0] & ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  & ( 
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0] & 
// ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout )))) # (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout )))) ) ) ) # ( 
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0] & ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  & ( 
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0] & ( 
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  & ( (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0] & 
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
        .datae(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 .lut_mask = 64'h0044CCCC0347CFCF;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y20_N55
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y20_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout  = SUM(( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + ( 
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14  ))
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10  = CARRY(( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + ( 
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14  ))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
        .cout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .lut_mask = 64'h0000CCCC000000FF;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y20_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_data[80] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|src_data [80] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~1_combout  & ( ((\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~0_combout )) # 
// (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~1_combout  & ( (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~0_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_018|src_data [80]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[80] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[80] .lut_mask = 64'h5500550077337733;
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[80] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y20_N11
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_018|src_data [80]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y20_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1] = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout  & ( 
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1])) # 
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|cmd_mux_018|src_data [80]))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_018|src_data [80]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .lut_mask = 64'h00000000F3C0F3C0;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y20_N53
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y20_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout  & ( 
// ((\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [1])) # (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout  & 
// ( (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [1]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .lut_mask = 64'h0303030357575757;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y20_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  & ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout  ) ) ) # 
// ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  & ( 
// ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout  & \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1])) # 
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]) ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  & ( ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout  & 
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1])) # (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]) ) ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
        .datae(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .lut_mask = 64'h1F1F00001F1F00FF;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y20_N13
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y20_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout  = SUM(( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + ( 
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10  ))
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6  = CARRY(( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + ( 
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
        .cout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y20_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout  & ( 
// ((\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [2])) # (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout  & 
// ( (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [2]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y20_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2] = ( \u0|mm_interconnect_0|cmd_mux_018|src_data [81] & ( 
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] & 
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_018|src_data [81] & ( 
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout  & ((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]) # 
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_018|src_data [81]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .lut_mask = 64'h00F500F500A000A0;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y20_N22
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y20_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( 
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] & (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ))) # 
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 .lut_mask = 64'h02570257AAFFAAFF;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y20_N47
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y20_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_data[82] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|src_data [82] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout  & ( ((\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout )) # 
// (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout  & ( (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_018|src_data [82]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[82] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[82] .lut_mask = 64'h5050505073737373;
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[82] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y20_N26
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_018|src_data [82]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y20_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3] = ( \u0|mm_interconnect_0|cmd_mux_018|src_data [82] & ( 
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3] & 
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_018|src_data [82] & ( 
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout  & ((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]) # 
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_018|src_data [82]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .lut_mask = 64'h00F300F300C000C0;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y20_N44
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y20_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [3] & ( ((\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout )) # (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [3] & ( (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] 
// & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .lut_mask = 64'h0505050505FF05FF;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y20_N46
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y20_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  & ( 
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) # 
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((\u0|mm_interconnect_0|cmd_mux_018|src_data [86]))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_018|src_data [86]),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .lut_mask = 64'h00000000330F330F;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y20_N2
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y20_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout  = SUM(( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3] ) + ( 
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3] ) + ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y20_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout  & ( 
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3])) # 
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]))) # (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout )))) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout  & ( 
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3])) # 
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .lut_mask = 64'h0C3F0C3F4C7F4C7F;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y20_N53
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y20_N27
cyclonev_lcell_comb \u0|clock_sel|always0~0 (
// Equation(s):
// \u0|clock_sel|always0~0_combout  = ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( (\u0|mm_interconnect_0|clock_sel_s1_agent|m0_write~combout  & 
// (!\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [0] & (!\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [1] & 
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]))) ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent|m0_write~combout ),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [0]),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [1]),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|clock_sel|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|clock_sel|always0~0 .extended_lut = "off";
defparam \u0|clock_sel|always0~0 .lut_mask = 64'h4000400000000000;
defparam \u0|clock_sel|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X59_Y13_N17
dffeas \u0|clock_sel|data_out[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|clock_sel|data_out[2]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|clock_sel|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|clock_sel|data_out [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|clock_sel|data_out[2] .is_wysiwyg = "true";
defparam \u0|clock_sel|data_out[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X59_Y10_N24
cyclonev_lcell_comb \u0|clock_sel|readdata[2]~2 (
// Equation(s):
// \u0|clock_sel|readdata[2]~2_combout  = ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & ( 
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( \u0|clock_sel|data_out [2] ) ) )

        .dataa(gnd),
        .datab(!\u0|clock_sel|data_out [2]),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|clock_sel|readdata[2]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|clock_sel|readdata[2]~2 .extended_lut = "off";
defparam \u0|clock_sel|readdata[2]~2 .lut_mask = 64'h3333000000000000;
defparam \u0|clock_sel|readdata[2]~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X59_Y10_N26
dffeas \u0|mm_interconnect_0|clock_sel_s1_translator|av_readdata_pre[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|clock_sel|readdata[2]~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_translator|av_readdata_pre [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_translator|av_readdata_pre[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_translator|av_readdata_pre[2] .power_up = "low";
// synopsys translate_on

// Location: FF_X30_Y22_N50
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[1][2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[1][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[1][2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[1][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y22_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem~2 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem~2_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[1][2]~q  ) ) # ( 
// !\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|clock_sel_s1_translator|av_readdata_pre [2] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_translator|av_readdata_pre [2]),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[1][2]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem~2 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y22_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|always0~0_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|rsp_demux_018|WideOr0~0_combout  & 
// ((!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [0]) # (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][129]~q ))) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [0] )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [0]),
        .datab(!\u0|mm_interconnect_0|rsp_demux_018|WideOr0~0_combout ),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|always0~0 .lut_mask = 64'hFFFFFFFF33223322;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y22_N17
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[0][2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem~2_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[0][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[0][2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[0][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y22_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~48 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~48_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_translator|av_readdata_pre [2] & ( ((\u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg [0] & 
// !\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[0][2]~q ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_translator|av_readdata_pre [2] & ( 
// (\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[0][2]~q  & ((!\u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg [0]) # (\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [0]))) ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [0]),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[0][2]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_translator|av_readdata_pre [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~48_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~48 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~48 .lut_mask = 64'h00AF00AF50FF50FF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~48 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X31_Y16_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~49 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~49_combout  = ( \u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout  & ( ((\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout  & \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~47_combout )) # 
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~48_combout ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout  & ( (\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout  & \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~47_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout ),
        .datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~47_combout ),
        .datac(!\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~48_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~49_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~49 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~49 .lut_mask = 64'h111111111F1F1F1F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~49 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X54_Y9_N36
cyclonev_lcell_comb \m_x|rx_got_nchar~0 (
// Equation(s):
// \m_x|rx_got_nchar~0_combout  = ( \m_x|always10~1_combout  & ( (!\m_x|last_is_data~q  & (((!\m_x|always10~0_combout  & \m_x|rx_got_nchar~q )))) # (\m_x|last_is_data~q  & (!\m_x|rx_got_time_code~0_combout )) ) ) # ( !\m_x|always10~1_combout  & ( 
// (!\m_x|always10~0_combout  & ((!\m_x|last_is_data~q  & ((\m_x|rx_got_nchar~q ))) # (\m_x|last_is_data~q  & (!\m_x|rx_got_time_code~0_combout )))) ) )

        .dataa(!\m_x|rx_got_time_code~0_combout ),
        .datab(!\m_x|last_is_data~q ),
        .datac(!\m_x|always10~0_combout ),
        .datad(!\m_x|rx_got_nchar~q ),
        .datae(gnd),
        .dataf(!\m_x|always10~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|rx_got_nchar~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|rx_got_nchar~0 .extended_lut = "off";
defparam \m_x|rx_got_nchar~0 .lut_mask = 64'h20E020E022E222E2;
defparam \m_x|rx_got_nchar~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X54_Y9_N2
dffeas \m_x|rx_got_nchar (
        .clk(!\m_x|always3~0_combout ),
        .d(gnd),
        .asdata(\m_x|rx_got_nchar~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|rx_got_nchar~q ),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|rx_got_nchar .is_wysiwyg = "true";
defparam \m_x|rx_got_nchar .power_up = "low";
// synopsys translate_on

// Location: FF_X54_Y9_N13
dffeas \m_x|info[2] (
        .clk(!\m_x|always3~0_combout ),
        .d(gnd),
        .asdata(\m_x|rx_got_nchar~q ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\m_x|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|info [2]),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|info[2] .is_wysiwyg = "true";
defparam \m_x|info[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y13_N6
cyclonev_lcell_comb \u0|data_info|read_mux_out[2] (
// Equation(s):
// \u0|data_info|read_mux_out [2] = ( \m_x|info [2] & ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( 
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datac(gnd),
        .datad(gnd),
        .datae(!\m_x|info [2]),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|data_info|read_mux_out [2]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|data_info|read_mux_out[2] .extended_lut = "off";
defparam \u0|data_info|read_mux_out[2] .lut_mask = 64'h0000CCCC00000000;
defparam \u0|data_info|read_mux_out[2] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y13_N7
dffeas \u0|data_info|readdata[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|data_info|read_mux_out [2]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|data_info|readdata [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|data_info|readdata[2] .is_wysiwyg = "true";
defparam \u0|data_info|readdata[2] .power_up = "low";
// synopsys translate_on

// Location: FF_X31_Y13_N11
dffeas \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|data_info|readdata [2]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y14_N51
cyclonev_lcell_comb \u0|counter_rx_fifo|read_mux_out[2]~2 (
// Equation(s):
// \u0|counter_rx_fifo|read_mux_out[2]~2_combout  = ( \A_SPW_TOP|rx_data|counter [2] & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|counter [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|counter_rx_fifo|read_mux_out[2]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|counter_rx_fifo|read_mux_out[2]~2 .extended_lut = "off";
defparam \u0|counter_rx_fifo|read_mux_out[2]~2 .lut_mask = 64'h00000000C0C0C0C0;
defparam \u0|counter_rx_fifo|read_mux_out[2]~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y14_N52
dffeas \u0|counter_rx_fifo|readdata[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|counter_rx_fifo|read_mux_out[2]~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|counter_rx_fifo|readdata [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|counter_rx_fifo|readdata[2] .is_wysiwyg = "true";
defparam \u0|counter_rx_fifo|readdata[2] .power_up = "low";
// synopsys translate_on

// Location: FF_X31_Y15_N8
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|counter_rx_fifo|readdata [2]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre[2] .power_up = "low";
// synopsys translate_on

// Location: FF_X31_Y15_N11
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y15_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~2 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~2_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][2]~q  & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [1] ) ) # ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][2]~q  & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [2] ) ) ) # ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][2]~q  & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [2] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [2]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][2]~q ),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~2 .lut_mask = 64'h0F0F0F0F0000FFFF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y15_N31
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~2_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y15_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~46 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~46_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0] & ( 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][2]~q  & !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ) ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0] & ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][2]~q  & !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ) ) ) ) # ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0] & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [2] & 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ) ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0] & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0] & ( 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][2]~q  & !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ) ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [2]),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][2]~q ),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ),
        .datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0]),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~46_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~46 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~46 .lut_mask = 64'h0F0033000F000F00;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~46 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y14_N21
cyclonev_lcell_comb \u0|counter_tx_fifo|read_mux_out[2]~2 (
// Equation(s):
// \u0|counter_tx_fifo|read_mux_out[2]~2_combout  = ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( \A_SPW_TOP|tx_data|counter [2] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|tx_data|counter [2]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|counter_tx_fifo|read_mux_out[2]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|counter_tx_fifo|read_mux_out[2]~2 .extended_lut = "off";
defparam \u0|counter_tx_fifo|read_mux_out[2]~2 .lut_mask = 64'h0F0F000000000000;
defparam \u0|counter_tx_fifo|read_mux_out[2]~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y14_N22
dffeas \u0|counter_tx_fifo|readdata[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|counter_tx_fifo|read_mux_out[2]~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|counter_tx_fifo|readdata [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|counter_tx_fifo|readdata[2] .is_wysiwyg = "true";
defparam \u0|counter_tx_fifo|readdata[2] .power_up = "low";
// synopsys translate_on

// Location: FF_X27_Y15_N59
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|counter_tx_fifo|readdata [2]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre[2] .power_up = "low";
// synopsys translate_on

// Location: FF_X27_Y15_N35
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y15_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~2 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~2_combout  = (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [1] & (\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [2])) # 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [1] & ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][2]~q )))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [2]),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][2]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~2 .lut_mask = 64'h303F303F303F303F;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y15_N43
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~2_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y15_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~45 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~45_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [2] & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0] & ( 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout  & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0]) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][2]~q ))) ) ) ) # ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [2] & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0] & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0] & 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][2]~q  & !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout )) ) ) ) # ( \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [2] & ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0] & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][2]~q  & !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ) ) ) ) # ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [2] & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0] & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][2]~q  & 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][2]~q ),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ),
        .datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [2]),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~45_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~45 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~45 .lut_mask = 64'h0F000F000500AF00;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~45 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X31_Y14_N6
cyclonev_lcell_comb \u0|write_data_fifo_tx|readdata[2] (
// Equation(s):
// \u0|write_data_fifo_tx|readdata [2] = ( \u0|write_data_fifo_tx|data_out [2] & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]) ) )

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|write_data_fifo_tx|data_out [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|write_data_fifo_tx|readdata [2]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|write_data_fifo_tx|readdata[2] .extended_lut = "off";
defparam \u0|write_data_fifo_tx|readdata[2] .lut_mask = 64'h0000000088888888;
defparam \u0|write_data_fifo_tx|readdata[2] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y14_N8
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|write_data_fifo_tx|readdata [2]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre[2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y15_N39
cyclonev_lcell_comb \u0|fsm_info|read_mux_out[2]~2 (
// Equation(s):
// \u0|fsm_info|read_mux_out[2]~2_combout  = ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & ( (\A_SPW_TOP|SPW|FSM|state_fsm.started~q  & 
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|state_fsm.started~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|fsm_info|read_mux_out[2]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|fsm_info|read_mux_out[2]~2 .extended_lut = "off";
defparam \u0|fsm_info|read_mux_out[2]~2 .lut_mask = 64'h5050505000000000;
defparam \u0|fsm_info|read_mux_out[2]~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y15_N35
dffeas \u0|fsm_info|readdata[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|fsm_info|read_mux_out[2]~2_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|fsm_info|readdata [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|fsm_info|readdata[2] .is_wysiwyg = "true";
defparam \u0|fsm_info|readdata[2] .power_up = "low";
// synopsys translate_on

// Location: FF_X25_Y15_N17
dffeas \u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|fsm_info|readdata [2]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre[2] .power_up = "low";
// synopsys translate_on

// Location: FF_X25_Y15_N50
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~2_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y15_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~2 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~2_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][2]~q  ) ) # ( 
// !\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre [2] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre [2]),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][2]~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~2 .lut_mask = 64'h333333330F0F0F0F;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y15_N40
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~2_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y15_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~44 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~44_combout  = ( !\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout  & ( \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0] & ( 
// (!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0] & (\u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre [2])) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0] & 
// ((\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][2]~q ))) ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout  & ( !\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0] & ( 
// \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][2]~q  ) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0]),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre [2]),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][2]~q ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout ),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~44_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~44 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~44 .lut_mask = 64'h0F0F000027270000;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~44 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y15_N53
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y15_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~2 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~2_combout  = (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1] & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [2])) # 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1] & ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][2]~q )))

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [2]),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][2]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~2 .lut_mask = 64'h4477447744774477;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y15_N7
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~2_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y15_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~234 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~234_combout  = ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout  & ( ((((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][2]~q  & 
// \u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~44_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~45_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~46_combout ) ) ) # ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout  & ( ((((\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [2] & \u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout )) # 
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~44_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~45_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~46_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~46_combout ),
        .datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~45_combout ),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [2]),
        .datad(!\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ),
        .datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout ),
        .dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~44_combout ),
        .datag(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][2]~q ),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~234_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~234 .extended_lut = "on";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~234 .lut_mask = 64'h777F777FFFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~234 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y2_N51
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|timecode~3 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|timecode~3_combout  = ( \A_SPW_TOP|SPW|RX|dta_timec_p [2] & ( (\A_SPW_TOP|SPW|RX|timecode [2]) # (\A_SPW_TOP|SPW|RX|timecode~0_combout ) ) ) # ( !\A_SPW_TOP|SPW|RX|dta_timec_p [2] & ( (!\A_SPW_TOP|SPW|RX|timecode~0_combout  & 
// \A_SPW_TOP|SPW|RX|timecode [2]) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|timecode~0_combout ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|RX|timecode [2]),
        .datad(gnd),
        .datae(!\A_SPW_TOP|SPW|RX|dta_timec_p [2]),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|timecode~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|timecode~3 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|timecode~3 .lut_mask = 64'h0A0A5F5F0A0A5F5F;
defparam \A_SPW_TOP|SPW|RX|timecode~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y2_N10
dffeas \A_SPW_TOP|SPW|RX|timecode[2] (
        .clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|RX|timecode~3_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(!\A_SPW_TOP|SPW|RX|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|timecode [2]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|timecode[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|timecode[2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y14_N57
cyclonev_lcell_comb \u0|timecode_rx|read_mux_out[2] (
// Equation(s):
// \u0|timecode_rx|read_mux_out [2] = ( \A_SPW_TOP|SPW|RX|timecode [2] & ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\A_SPW_TOP|SPW|RX|timecode [2]),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|timecode_rx|read_mux_out [2]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|timecode_rx|read_mux_out[2] .extended_lut = "off";
defparam \u0|timecode_rx|read_mux_out[2] .lut_mask = 64'h0000AAAA00000000;
defparam \u0|timecode_rx|read_mux_out[2] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y14_N59
dffeas \u0|timecode_rx|readdata[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|timecode_rx|read_mux_out [2]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|timecode_rx|readdata [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|timecode_rx|readdata[2] .is_wysiwyg = "true";
defparam \u0|timecode_rx|readdata[2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y16_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[2]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[2]~feeder_combout  = ( \u0|timecode_rx|readdata [2] )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|timecode_rx|readdata [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[2]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[2]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[2]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[2]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y16_N23
dffeas \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[2]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[2] .power_up = "low";
// synopsys translate_on

// Location: FF_X25_Y16_N44
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~2_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y16_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~2_combout  = (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1] & ((\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [2]))) # 
// (\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1] & (\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][2]~q ))

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1]),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][2]~q ),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [2]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~2 .lut_mask = 64'h1B1B1B1B1B1B1B1B;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y16_N37
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y16_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~41 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~41_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][2]~q  & ( \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0] & ( 
// (\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0]) # (\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [2]) ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][2]~q  & ( 
// \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0] & ( (\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [2] & !\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0]) ) ) ) # ( 
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][2]~q  & ( !\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0] ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [2]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][2]~q ),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~41_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~41 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~41 .lut_mask = 64'h0000FFFF50505F5F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~41 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y2_N0
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|rx_data_flag~2 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|rx_data_flag~2_combout  = ( \A_SPW_TOP|SPW|RX|ready_control_p_r~q  & ( (\A_SPW_TOP|SPW|RX|rx_data_flag~0_combout  & \A_SPW_TOP|SPW|RX|rx_data_flag [2]) ) ) # ( !\A_SPW_TOP|SPW|RX|ready_control_p_r~q  & ( 
// (!\A_SPW_TOP|SPW|RX|data~0_combout  & (((\A_SPW_TOP|SPW|RX|rx_data_flag~0_combout  & \A_SPW_TOP|SPW|RX|rx_data_flag [2])) # (\A_SPW_TOP|SPW|RX|dta_timec_p [2]))) # (\A_SPW_TOP|SPW|RX|data~0_combout  & (((\A_SPW_TOP|SPW|RX|rx_data_flag [2])))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag~0_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|dta_timec_p [2]),
        .datac(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .datad(!\A_SPW_TOP|SPW|RX|data~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|rx_data_flag~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_data_flag~2 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|rx_data_flag~2 .lut_mask = 64'h370F370F05050505;
defparam \A_SPW_TOP|SPW|RX|rx_data_flag~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y2_N53
dffeas \A_SPW_TOP|SPW|RX|rx_data_flag[2] (
        .clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|RX|rx_data_flag~2_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(!\A_SPW_TOP|SPW|RX|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_data_flag[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|rx_data_flag[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y8_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector250~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector250~0_combout  = ( \A_SPW_TOP|rx_data|Selector244~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [2])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux6~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector244~0_combout  & ( \A_SPW_TOP|rx_data|mem[25][2]~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .datab(!\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|mem[25][2]~q ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector244~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector250~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector250~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector250~0 .lut_mask = 64'h0F0F0F0F55335533;
defparam \A_SPW_TOP|rx_data|Selector250~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y8_N35
dffeas \A_SPW_TOP|rx_data|mem[25][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector250~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[25][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[25][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[25][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y8_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector178~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector178~0_combout  = ( \A_SPW_TOP|SPW|RX|rx_data_flag [2] & ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector172~0_combout  & ((\A_SPW_TOP|rx_data|mem[17][2]~q ))) # 
// (\A_SPW_TOP|rx_data|Selector172~0_combout  & (\A_SPW_TOP|rx_data|Mux6~20_combout )) ) ) ) # ( !\A_SPW_TOP|SPW|RX|rx_data_flag [2] & ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector172~0_combout  & 
// ((\A_SPW_TOP|rx_data|mem[17][2]~q ))) # (\A_SPW_TOP|rx_data|Selector172~0_combout  & (\A_SPW_TOP|rx_data|Mux6~20_combout )) ) ) ) # ( \A_SPW_TOP|SPW|RX|rx_data_flag [2] & ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( (\A_SPW_TOP|rx_data|mem[17][2]~q ) 
// # (\A_SPW_TOP|rx_data|Selector172~0_combout ) ) ) ) # ( !\A_SPW_TOP|SPW|RX|rx_data_flag [2] & ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector172~0_combout  & \A_SPW_TOP|rx_data|mem[17][2]~q ) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Selector172~0_combout ),
        .datab(!\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|mem[17][2]~q ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector178~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector178~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector178~0 .lut_mask = 64'h0A0A5F5F1B1B1B1B;
defparam \A_SPW_TOP|rx_data|Selector178~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y8_N2
dffeas \A_SPW_TOP|rx_data|mem[17][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector178~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[17][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[17][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[17][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y8_N45
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector538~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector538~0_combout  = ( \A_SPW_TOP|rx_data|mem[57][2]~q  & ( (!\A_SPW_TOP|rx_data|Selector532~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [2])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux6~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[57][2]~q  & ( (\A_SPW_TOP|rx_data|Selector532~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [2])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux6~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .datab(!\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector532~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[57][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector538~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector538~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector538~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|rx_data|Selector538~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y8_N11
dffeas \A_SPW_TOP|rx_data|mem[57][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector538~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[57][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[57][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[57][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y8_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector466~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector466~0_combout  = ( \A_SPW_TOP|rx_data|Selector460~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [2])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux6~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector460~0_combout  & ( \A_SPW_TOP|rx_data|mem[49][2]~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .datab(!\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|mem[49][2]~q ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector460~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector466~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector466~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector466~0 .lut_mask = 64'h0F0F0F0F55335533;
defparam \A_SPW_TOP|rx_data|Selector466~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y8_N5
dffeas \A_SPW_TOP|rx_data|mem[49][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector466~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[49][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[49][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[49][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y8_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux6~7 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux6~7_combout  = ( \A_SPW_TOP|rx_data|mem[49][2]~q  & ( \A_SPW_TOP|rx_data|wr_ptr [5] & ( (!\A_SPW_TOP|rx_data|wr_ptr [3]) # (\A_SPW_TOP|rx_data|mem[57][2]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[49][2]~q  & ( \A_SPW_TOP|rx_data|wr_ptr 
// [5] & ( (\A_SPW_TOP|rx_data|wr_ptr [3] & \A_SPW_TOP|rx_data|mem[57][2]~q ) ) ) ) # ( \A_SPW_TOP|rx_data|mem[49][2]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [5] & ( (!\A_SPW_TOP|rx_data|wr_ptr [3] & ((\A_SPW_TOP|rx_data|mem[17][2]~q ))) # 
// (\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|mem[25][2]~q )) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[49][2]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [5] & ( (!\A_SPW_TOP|rx_data|wr_ptr [3] & ((\A_SPW_TOP|rx_data|mem[17][2]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr 
// [3] & (\A_SPW_TOP|rx_data|mem[25][2]~q )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[25][2]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[17][2]~q ),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datad(!\A_SPW_TOP|rx_data|mem[57][2]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[49][2]~q ),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux6~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux6~7 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux6~7 .lut_mask = 64'h35353535000FF0FF;
defparam \A_SPW_TOP|rx_data|Mux6~7 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y8_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector574~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector574~0_combout  = ( \A_SPW_TOP|rx_data|Selector568~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [2])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux6~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector568~0_combout  & ( \A_SPW_TOP|rx_data|mem[61][2]~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .datab(!\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|mem[61][2]~q ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector568~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector574~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector574~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector574~0 .lut_mask = 64'h0F0F0F0F55335533;
defparam \A_SPW_TOP|rx_data|Selector574~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y8_N53
dffeas \A_SPW_TOP|rx_data|mem[61][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector574~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[61][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[61][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[61][2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y8_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector502~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector502~0_combout  = ( \A_SPW_TOP|rx_data|Selector496~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [2]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux6~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector496~0_combout  & ( \A_SPW_TOP|rx_data|mem[53][2]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|mem[53][2]~q ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector496~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector502~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector502~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector502~0 .lut_mask = 64'h0F0F0F0F11BB11BB;
defparam \A_SPW_TOP|rx_data|Selector502~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y8_N14
dffeas \A_SPW_TOP|rx_data|mem[53][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector502~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[53][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[53][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[53][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y8_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector286~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector286~0_combout  = ( \A_SPW_TOP|rx_data|Selector280~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [2])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux6~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector280~0_combout  & ( \A_SPW_TOP|rx_data|mem[29][2]~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .datab(!\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|mem[29][2]~q ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector280~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector286~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector286~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector286~0 .lut_mask = 64'h0F0F0F0F55335533;
defparam \A_SPW_TOP|rx_data|Selector286~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y8_N35
dffeas \A_SPW_TOP|rx_data|mem[29][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector286~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[29][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[29][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[29][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y8_N39
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector214~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector214~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector208~0_combout  & ((\A_SPW_TOP|rx_data|mem[21][2]~q ))) # (\A_SPW_TOP|rx_data|Selector208~0_combout  & 
// (\A_SPW_TOP|rx_data|Mux6~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector208~0_combout  & ((\A_SPW_TOP|rx_data|mem[21][2]~q ))) # (\A_SPW_TOP|rx_data|Selector208~0_combout  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [2])) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .datab(!\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector208~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[21][2]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector214~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector214~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector214~0 .lut_mask = 64'h05F505F503F303F3;
defparam \A_SPW_TOP|rx_data|Selector214~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y8_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|mem[21][2]~feeder (
// Equation(s):
// \A_SPW_TOP|rx_data|mem[21][2]~feeder_combout  = ( \A_SPW_TOP|rx_data|Selector214~0_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector214~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|mem[21][2]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[21][2]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|mem[21][2]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|rx_data|mem[21][2]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y8_N56
dffeas \A_SPW_TOP|rx_data|mem[21][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|rx_data|mem[21][2]~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[21][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[21][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[21][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y8_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux6~8 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux6~8_combout  = ( \A_SPW_TOP|rx_data|mem[21][2]~q  & ( \A_SPW_TOP|rx_data|wr_ptr [5] & ( (!\A_SPW_TOP|rx_data|wr_ptr [3] & ((\A_SPW_TOP|rx_data|mem[53][2]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|mem[61][2]~q )) ) 
// ) ) # ( !\A_SPW_TOP|rx_data|mem[21][2]~q  & ( \A_SPW_TOP|rx_data|wr_ptr [5] & ( (!\A_SPW_TOP|rx_data|wr_ptr [3] & ((\A_SPW_TOP|rx_data|mem[53][2]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|mem[61][2]~q )) ) ) ) # ( 
// \A_SPW_TOP|rx_data|mem[21][2]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [5] & ( (!\A_SPW_TOP|rx_data|wr_ptr [3]) # (\A_SPW_TOP|rx_data|mem[29][2]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[21][2]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [5] & ( 
// (\A_SPW_TOP|rx_data|mem[29][2]~q  & \A_SPW_TOP|rx_data|wr_ptr [3]) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[61][2]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[53][2]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[29][2]~q ),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datae(!\A_SPW_TOP|rx_data|mem[21][2]~q ),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux6~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux6~8 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux6~8 .lut_mask = 64'h000FFF0F33553355;
defparam \A_SPW_TOP|rx_data|Mux6~8 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y8_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector358~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector358~0_combout  = ( \A_SPW_TOP|rx_data|Selector352~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [2]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux6~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector352~0_combout  & ( \A_SPW_TOP|rx_data|mem[37][2]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|mem[37][2]~q ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector352~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector358~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector358~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector358~0 .lut_mask = 64'h0F0F0F0F11BB11BB;
defparam \A_SPW_TOP|rx_data|Selector358~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y8_N47
dffeas \A_SPW_TOP|rx_data|mem[37][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector358~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[37][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[37][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[37][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y8_N21
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector70~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector70~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector64~0_combout  & ((\A_SPW_TOP|rx_data|mem[5][2]~q ))) # (\A_SPW_TOP|rx_data|Selector64~0_combout  & (\A_SPW_TOP|rx_data|Mux6~20_combout 
// )) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector64~0_combout  & ((\A_SPW_TOP|rx_data|mem[5][2]~q ))) # (\A_SPW_TOP|rx_data|Selector64~0_combout  & (\A_SPW_TOP|SPW|RX|rx_data_flag [2])) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .datab(!\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector64~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[5][2]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector70~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector70~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector70~0 .lut_mask = 64'h05F505F503F303F3;
defparam \A_SPW_TOP|rx_data|Selector70~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y8_N5
dffeas \A_SPW_TOP|rx_data|mem[5][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector70~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[5][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[5][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[5][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y8_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector142~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector142~0_combout  = ( \A_SPW_TOP|rx_data|mem[13][2]~q  & ( (!\A_SPW_TOP|rx_data|Selector136~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [2])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux6~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[13][2]~q  & ( (\A_SPW_TOP|rx_data|Selector136~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [2])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux6~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .datab(!\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector136~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[13][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector142~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector142~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector142~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|rx_data|Selector142~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y8_N11
dffeas \A_SPW_TOP|rx_data|mem[13][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector142~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[13][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[13][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[13][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y8_N45
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector430~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector430~0_combout  = ( \A_SPW_TOP|rx_data|Selector424~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [2])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux6~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector424~0_combout  & ( \A_SPW_TOP|rx_data|mem[45][2]~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .datab(!\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|mem[45][2]~q ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector424~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector430~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector430~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector430~0 .lut_mask = 64'h0F0F0F0F55335533;
defparam \A_SPW_TOP|rx_data|Selector430~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y8_N59
dffeas \A_SPW_TOP|rx_data|mem[45][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector430~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[45][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[45][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[45][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y8_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux6~6 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux6~6_combout  = ( \A_SPW_TOP|rx_data|mem[45][2]~q  & ( \A_SPW_TOP|rx_data|wr_ptr [5] & ( (\A_SPW_TOP|rx_data|wr_ptr [3]) # (\A_SPW_TOP|rx_data|mem[37][2]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[45][2]~q  & ( \A_SPW_TOP|rx_data|wr_ptr 
// [5] & ( (\A_SPW_TOP|rx_data|mem[37][2]~q  & !\A_SPW_TOP|rx_data|wr_ptr [3]) ) ) ) # ( \A_SPW_TOP|rx_data|mem[45][2]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [5] & ( (!\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|mem[5][2]~q )) # (\A_SPW_TOP|rx_data|wr_ptr 
// [3] & ((\A_SPW_TOP|rx_data|mem[13][2]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[45][2]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [5] & ( (!\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|mem[5][2]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [3] & 
// ((\A_SPW_TOP|rx_data|mem[13][2]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[37][2]~q ),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datac(!\A_SPW_TOP|rx_data|mem[5][2]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[13][2]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[45][2]~q ),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux6~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux6~6 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux6~6 .lut_mask = 64'h0C3F0C3F44447777;
defparam \A_SPW_TOP|rx_data|Mux6~6 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y8_N39
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector34~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector34~0_combout  = ( \A_SPW_TOP|rx_data|mem[1][2]~q  & ( (!\A_SPW_TOP|rx_data|Selector28~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [2])) # (\A_SPW_TOP|rx_data|state_data_write.00~q 
//  & ((\A_SPW_TOP|rx_data|Mux6~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[1][2]~q  & ( (\A_SPW_TOP|rx_data|Selector28~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [2])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux6~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .datab(!\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector28~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[1][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector34~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector34~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector34~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|rx_data|Selector34~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y8_N53
dffeas \A_SPW_TOP|rx_data|mem[1][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector34~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[1][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[1][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[1][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y8_N27
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector394~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector394~0_combout  = ( \A_SPW_TOP|rx_data|mem[41][2]~q  & ( (!\A_SPW_TOP|rx_data|Selector388~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [2])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux6~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[41][2]~q  & ( (\A_SPW_TOP|rx_data|Selector388~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [2])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux6~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .datab(!\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector388~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[41][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector394~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector394~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector394~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|rx_data|Selector394~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y8_N41
dffeas \A_SPW_TOP|rx_data|mem[41][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector394~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[41][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[41][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[41][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y8_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector106~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector106~0_combout  = ( \A_SPW_TOP|rx_data|Selector100~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [2]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux6~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector100~0_combout  & ( \A_SPW_TOP|rx_data|mem[9][2]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|mem[9][2]~q ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector100~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector106~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector106~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector106~0 .lut_mask = 64'h0F0F0F0F11BB11BB;
defparam \A_SPW_TOP|rx_data|Selector106~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y8_N23
dffeas \A_SPW_TOP|rx_data|mem[9][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector106~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[9][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[9][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[9][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y8_N57
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector322~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector322~0_combout  = ( \A_SPW_TOP|rx_data|mem[33][2]~q  & ( (!\A_SPW_TOP|rx_data|Selector316~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [2]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux6~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[33][2]~q  & ( (\A_SPW_TOP|rx_data|Selector316~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [2]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux6~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector316~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[33][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector322~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector322~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector322~0 .lut_mask = 64'h010B010BF1FBF1FB;
defparam \A_SPW_TOP|rx_data|Selector322~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y8_N53
dffeas \A_SPW_TOP|rx_data|mem[33][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector322~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[33][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[33][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[33][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y8_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux6~5 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux6~5_combout  = ( \A_SPW_TOP|rx_data|mem[9][2]~q  & ( \A_SPW_TOP|rx_data|mem[33][2]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [3] & (((\A_SPW_TOP|rx_data|wr_ptr [5])) # (\A_SPW_TOP|rx_data|mem[1][2]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [3] & 
// (((!\A_SPW_TOP|rx_data|wr_ptr [5]) # (\A_SPW_TOP|rx_data|mem[41][2]~q )))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[9][2]~q  & ( \A_SPW_TOP|rx_data|mem[33][2]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [3] & (((\A_SPW_TOP|rx_data|wr_ptr [5])) # 
// (\A_SPW_TOP|rx_data|mem[1][2]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [3] & (((\A_SPW_TOP|rx_data|mem[41][2]~q  & \A_SPW_TOP|rx_data|wr_ptr [5])))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[9][2]~q  & ( !\A_SPW_TOP|rx_data|mem[33][2]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr 
// [3] & (\A_SPW_TOP|rx_data|mem[1][2]~q  & ((!\A_SPW_TOP|rx_data|wr_ptr [5])))) # (\A_SPW_TOP|rx_data|wr_ptr [3] & (((!\A_SPW_TOP|rx_data|wr_ptr [5]) # (\A_SPW_TOP|rx_data|mem[41][2]~q )))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[9][2]~q  & ( 
// !\A_SPW_TOP|rx_data|mem[33][2]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|mem[1][2]~q  & ((!\A_SPW_TOP|rx_data|wr_ptr [5])))) # (\A_SPW_TOP|rx_data|wr_ptr [3] & (((\A_SPW_TOP|rx_data|mem[41][2]~q  & \A_SPW_TOP|rx_data|wr_ptr [5])))) ) ) 
// )

        .dataa(!\A_SPW_TOP|rx_data|mem[1][2]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[41][2]~q ),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datae(!\A_SPW_TOP|rx_data|mem[9][2]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[33][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux6~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux6~5 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux6~5 .lut_mask = 64'h50035F0350F35FF3;
defparam \A_SPW_TOP|rx_data|Mux6~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y8_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux6~9 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux6~9_combout  = ( \A_SPW_TOP|rx_data|Mux6~6_combout  & ( \A_SPW_TOP|rx_data|Mux6~5_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [4]) # ((!\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|Mux6~7_combout )) # (\A_SPW_TOP|rx_data|wr_ptr 
// [2] & ((\A_SPW_TOP|rx_data|Mux6~8_combout )))) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux6~6_combout  & ( \A_SPW_TOP|rx_data|Mux6~5_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [4] & (((!\A_SPW_TOP|rx_data|wr_ptr [2])))) # (\A_SPW_TOP|rx_data|wr_ptr [4] & 
// ((!\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|Mux6~7_combout )) # (\A_SPW_TOP|rx_data|wr_ptr [2] & ((\A_SPW_TOP|rx_data|Mux6~8_combout ))))) ) ) ) # ( \A_SPW_TOP|rx_data|Mux6~6_combout  & ( !\A_SPW_TOP|rx_data|Mux6~5_combout  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [4] & (((\A_SPW_TOP|rx_data|wr_ptr [2])))) # (\A_SPW_TOP|rx_data|wr_ptr [4] & ((!\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|Mux6~7_combout )) # (\A_SPW_TOP|rx_data|wr_ptr [2] & ((\A_SPW_TOP|rx_data|Mux6~8_combout ))))) 
// ) ) ) # ( !\A_SPW_TOP|rx_data|Mux6~6_combout  & ( !\A_SPW_TOP|rx_data|Mux6~5_combout  & ( (\A_SPW_TOP|rx_data|wr_ptr [4] & ((!\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|Mux6~7_combout )) # (\A_SPW_TOP|rx_data|wr_ptr [2] & 
// ((\A_SPW_TOP|rx_data|Mux6~8_combout ))))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux6~7_combout ),
        .datab(!\A_SPW_TOP|rx_data|Mux6~8_combout ),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datae(!\A_SPW_TOP|rx_data|Mux6~6_combout ),
        .dataf(!\A_SPW_TOP|rx_data|Mux6~5_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux6~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux6~9 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux6~9 .lut_mask = 64'h050305F3F503F5F3;
defparam \A_SPW_TOP|rx_data|Mux6~9 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y8_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector493~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector493~0_combout  = ( \A_SPW_TOP|rx_data|mem[52][2]~q  & ( (!\A_SPW_TOP|rx_data|Selector487~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [2]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux6~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[52][2]~q  & ( (\A_SPW_TOP|rx_data|Selector487~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [2]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux6~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector487~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[52][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector493~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector493~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector493~0 .lut_mask = 64'h010B010BF1FBF1FB;
defparam \A_SPW_TOP|rx_data|Selector493~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y8_N50
dffeas \A_SPW_TOP|rx_data|mem[52][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector493~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[52][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[52][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[52][2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y8_N21
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector277~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector277~0_combout  = ( \A_SPW_TOP|rx_data|mem[28][2]~q  & ( (!\A_SPW_TOP|rx_data|Selector271~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [2]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux6~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[28][2]~q  & ( (\A_SPW_TOP|rx_data|Selector271~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [2]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux6~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector271~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[28][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector277~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector277~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector277~0 .lut_mask = 64'h010B010BF1FBF1FB;
defparam \A_SPW_TOP|rx_data|Selector277~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y8_N41
dffeas \A_SPW_TOP|rx_data|mem[28][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector277~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[28][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[28][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[28][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y8_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector205~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector205~0_combout  = ( \A_SPW_TOP|rx_data|mem[20][2]~q  & ( (!\A_SPW_TOP|rx_data|Selector199~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [2])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux6~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[20][2]~q  & ( (\A_SPW_TOP|rx_data|Selector199~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [2])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux6~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .datab(!\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector199~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[20][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector205~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector205~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector205~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|rx_data|Selector205~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y8_N8
dffeas \A_SPW_TOP|rx_data|mem[20][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector205~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[20][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[20][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[20][2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y8_N57
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector565~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector565~0_combout  = ( \A_SPW_TOP|rx_data|Selector559~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [2]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux6~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector559~0_combout  & ( \A_SPW_TOP|rx_data|mem[60][2]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|mem[60][2]~q ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector559~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector565~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector565~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector565~0 .lut_mask = 64'h0F0F0F0F11BB11BB;
defparam \A_SPW_TOP|rx_data|Selector565~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y8_N17
dffeas \A_SPW_TOP|rx_data|mem[60][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector565~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[60][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[60][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[60][2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y8_N9
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux6~3 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux6~3_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [3] & ( \A_SPW_TOP|rx_data|mem[60][2]~q  & ( (\A_SPW_TOP|rx_data|mem[28][2]~q ) # (\A_SPW_TOP|rx_data|wr_ptr [5]) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [3] & ( \A_SPW_TOP|rx_data|mem[60][2]~q 
//  & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & ((\A_SPW_TOP|rx_data|mem[20][2]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|mem[52][2]~q )) ) ) ) # ( \A_SPW_TOP|rx_data|wr_ptr [3] & ( !\A_SPW_TOP|rx_data|mem[60][2]~q  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [5] & \A_SPW_TOP|rx_data|mem[28][2]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [3] & ( !\A_SPW_TOP|rx_data|mem[60][2]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & ((\A_SPW_TOP|rx_data|mem[20][2]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [5] 
// & (\A_SPW_TOP|rx_data|mem[52][2]~q )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[52][2]~q ),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datac(!\A_SPW_TOP|rx_data|mem[28][2]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[20][2]~q ),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .dataf(!\A_SPW_TOP|rx_data|mem[60][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux6~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux6~3 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux6~3 .lut_mask = 64'h11DD0C0C11DD3F3F;
defparam \A_SPW_TOP|rx_data|Mux6~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y8_N15
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector61~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector61~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector55~0_combout  & ((\A_SPW_TOP|rx_data|mem[4][2]~q ))) # (\A_SPW_TOP|rx_data|Selector55~0_combout  & (\A_SPW_TOP|rx_data|Mux6~20_combout 
// )) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector55~0_combout  & ((\A_SPW_TOP|rx_data|mem[4][2]~q ))) # (\A_SPW_TOP|rx_data|Selector55~0_combout  & (\A_SPW_TOP|SPW|RX|rx_data_flag [2])) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .datab(!\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector55~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[4][2]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector61~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector61~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector61~0 .lut_mask = 64'h05F505F503F303F3;
defparam \A_SPW_TOP|rx_data|Selector61~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y8_N29
dffeas \A_SPW_TOP|rx_data|mem[4][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector61~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[4][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[4][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[4][2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y8_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector421~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector421~0_combout  = ( \A_SPW_TOP|rx_data|mem[44][2]~q  & ( (!\A_SPW_TOP|rx_data|Selector415~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [2]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux6~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[44][2]~q  & ( (\A_SPW_TOP|rx_data|Selector415~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [2]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux6~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector415~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[44][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector421~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector421~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector421~0 .lut_mask = 64'h010B010BF1FBF1FB;
defparam \A_SPW_TOP|rx_data|Selector421~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y8_N8
dffeas \A_SPW_TOP|rx_data|mem[44][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector421~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[44][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[44][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[44][2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y8_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector133~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector133~0_combout  = ( \A_SPW_TOP|rx_data|Selector127~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [2]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux6~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector127~0_combout  & ( \A_SPW_TOP|rx_data|mem[12][2]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|mem[12][2]~q ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector127~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector133~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector133~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector133~0 .lut_mask = 64'h0F0F0F0F11BB11BB;
defparam \A_SPW_TOP|rx_data|Selector133~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y8_N38
dffeas \A_SPW_TOP|rx_data|mem[12][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector133~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[12][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[12][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[12][2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y8_N27
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector349~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector349~0_combout  = ( \A_SPW_TOP|rx_data|mem[36][2]~q  & ( (!\A_SPW_TOP|rx_data|Selector343~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [2]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux6~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[36][2]~q  & ( (\A_SPW_TOP|rx_data|Selector343~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [2]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux6~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector343~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[36][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector349~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector349~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector349~0 .lut_mask = 64'h010B010BF1FBF1FB;
defparam \A_SPW_TOP|rx_data|Selector349~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y8_N35
dffeas \A_SPW_TOP|rx_data|mem[36][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector349~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[36][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[36][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[36][2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y8_N51
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux6~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux6~1_combout  = ( \A_SPW_TOP|rx_data|mem[12][2]~q  & ( \A_SPW_TOP|rx_data|mem[36][2]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [3] & (((\A_SPW_TOP|rx_data|wr_ptr [5])) # (\A_SPW_TOP|rx_data|mem[4][2]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [3] & 
// (((!\A_SPW_TOP|rx_data|wr_ptr [5]) # (\A_SPW_TOP|rx_data|mem[44][2]~q )))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[12][2]~q  & ( \A_SPW_TOP|rx_data|mem[36][2]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [3] & (((\A_SPW_TOP|rx_data|wr_ptr [5])) # 
// (\A_SPW_TOP|rx_data|mem[4][2]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [3] & (((\A_SPW_TOP|rx_data|mem[44][2]~q  & \A_SPW_TOP|rx_data|wr_ptr [5])))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[12][2]~q  & ( !\A_SPW_TOP|rx_data|mem[36][2]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr 
// [3] & (\A_SPW_TOP|rx_data|mem[4][2]~q  & ((!\A_SPW_TOP|rx_data|wr_ptr [5])))) # (\A_SPW_TOP|rx_data|wr_ptr [3] & (((!\A_SPW_TOP|rx_data|wr_ptr [5]) # (\A_SPW_TOP|rx_data|mem[44][2]~q )))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[12][2]~q  & ( 
// !\A_SPW_TOP|rx_data|mem[36][2]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|mem[4][2]~q  & ((!\A_SPW_TOP|rx_data|wr_ptr [5])))) # (\A_SPW_TOP|rx_data|wr_ptr [3] & (((\A_SPW_TOP|rx_data|mem[44][2]~q  & \A_SPW_TOP|rx_data|wr_ptr [5])))) ) ) 
// )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datab(!\A_SPW_TOP|rx_data|mem[4][2]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[44][2]~q ),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datae(!\A_SPW_TOP|rx_data|mem[12][2]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[36][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux6~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux6~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux6~1 .lut_mask = 64'h2205770522AF77AF;
defparam \A_SPW_TOP|rx_data|Mux6~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y8_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector97~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector97~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector91~0_combout  & ((\A_SPW_TOP|rx_data|mem[8][2]~q ))) # (\A_SPW_TOP|rx_data|Selector91~0_combout  & (\A_SPW_TOP|rx_data|Mux6~20_combout 
// )) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector91~0_combout  & ((\A_SPW_TOP|rx_data|mem[8][2]~q ))) # (\A_SPW_TOP|rx_data|Selector91~0_combout  & (\A_SPW_TOP|SPW|RX|rx_data_flag [2])) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .datab(!\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector91~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[8][2]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector97~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector97~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector97~0 .lut_mask = 64'h05F505F503F303F3;
defparam \A_SPW_TOP|rx_data|Selector97~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y8_N23
dffeas \A_SPW_TOP|rx_data|mem[8][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector97~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[8][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[8][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[8][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y8_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector313~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector313~0_combout  = ( \A_SPW_TOP|rx_data|Selector307~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [2])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux6~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector307~0_combout  & ( \A_SPW_TOP|rx_data|mem[32][2]~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .datab(!\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[32][2]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector307~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector313~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector313~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector313~0 .lut_mask = 64'h00FF00FF53535353;
defparam \A_SPW_TOP|rx_data|Selector313~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y8_N59
dffeas \A_SPW_TOP|rx_data|mem[32][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector313~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[32][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[32][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[32][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y8_N9
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector385~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector385~0_combout  = ( \A_SPW_TOP|rx_data|mem[40][2]~q  & ( (!\A_SPW_TOP|rx_data|Selector379~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [2])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux6~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[40][2]~q  & ( (\A_SPW_TOP|rx_data|Selector379~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [2])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux6~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .datab(!\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector379~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[40][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector385~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector385~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector385~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|rx_data|Selector385~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y8_N20
dffeas \A_SPW_TOP|rx_data|mem[40][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector385~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[40][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[40][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[40][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y8_N27
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector25~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector25~0_combout  = ( \A_SPW_TOP|rx_data|mem[0][2]~q  & ( (!\A_SPW_TOP|rx_data|Selector19~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [2]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux6~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[0][2]~q  & ( (\A_SPW_TOP|rx_data|Selector19~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [2]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux6~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector19~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[0][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector25~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector25~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector25~0 .lut_mask = 64'h010B010BF1FBF1FB;
defparam \A_SPW_TOP|rx_data|Selector25~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y8_N26
dffeas \A_SPW_TOP|rx_data|mem[0][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector25~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[0][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[0][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[0][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y8_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux6~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux6~0_combout  = ( \A_SPW_TOP|rx_data|mem[40][2]~q  & ( \A_SPW_TOP|rx_data|mem[0][2]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & (((!\A_SPW_TOP|rx_data|wr_ptr [3])) # (\A_SPW_TOP|rx_data|mem[8][2]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [5] & 
// (((\A_SPW_TOP|rx_data|wr_ptr [3]) # (\A_SPW_TOP|rx_data|mem[32][2]~q )))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[40][2]~q  & ( \A_SPW_TOP|rx_data|mem[0][2]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & (((!\A_SPW_TOP|rx_data|wr_ptr [3])) # 
// (\A_SPW_TOP|rx_data|mem[8][2]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [5] & (((\A_SPW_TOP|rx_data|mem[32][2]~q  & !\A_SPW_TOP|rx_data|wr_ptr [3])))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[40][2]~q  & ( !\A_SPW_TOP|rx_data|mem[0][2]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr 
// [5] & (\A_SPW_TOP|rx_data|mem[8][2]~q  & ((\A_SPW_TOP|rx_data|wr_ptr [3])))) # (\A_SPW_TOP|rx_data|wr_ptr [5] & (((\A_SPW_TOP|rx_data|wr_ptr [3]) # (\A_SPW_TOP|rx_data|mem[32][2]~q )))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[40][2]~q  & ( 
// !\A_SPW_TOP|rx_data|mem[0][2]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|mem[8][2]~q  & ((\A_SPW_TOP|rx_data|wr_ptr [3])))) # (\A_SPW_TOP|rx_data|wr_ptr [5] & (((\A_SPW_TOP|rx_data|mem[32][2]~q  & !\A_SPW_TOP|rx_data|wr_ptr [3])))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[8][2]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[32][2]~q ),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datae(!\A_SPW_TOP|rx_data|mem[40][2]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[0][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux6~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux6~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux6~0 .lut_mask = 64'h0350035FF350F35F;
defparam \A_SPW_TOP|rx_data|Mux6~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y8_N45
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector457~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector457~0_combout  = ( \A_SPW_TOP|rx_data|Selector451~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [2])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux6~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector451~0_combout  & ( \A_SPW_TOP|rx_data|mem[48][2]~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .datab(!\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[48][2]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector451~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector457~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector457~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector457~0 .lut_mask = 64'h00FF00FF53535353;
defparam \A_SPW_TOP|rx_data|Selector457~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y8_N56
dffeas \A_SPW_TOP|rx_data|mem[48][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector457~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[48][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[48][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[48][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y8_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector241~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector241~0_combout  = ( \A_SPW_TOP|rx_data|mem[24][2]~q  & ( (!\A_SPW_TOP|rx_data|Selector235~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [2])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux6~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[24][2]~q  & ( (\A_SPW_TOP|rx_data|Selector235~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [2])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux6~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .datab(!\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|Selector235~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[24][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector241~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector241~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector241~0 .lut_mask = 64'h00530053FF53FF53;
defparam \A_SPW_TOP|rx_data|Selector241~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y8_N14
dffeas \A_SPW_TOP|rx_data|mem[24][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector241~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[24][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[24][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[24][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y8_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector529~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector529~0_combout  = ( \A_SPW_TOP|rx_data|mem[56][2]~q  & ( (!\A_SPW_TOP|rx_data|Selector523~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [2])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux6~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[56][2]~q  & ( (\A_SPW_TOP|rx_data|Selector523~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [2])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux6~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .datab(!\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector523~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[56][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector529~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector529~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector529~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|rx_data|Selector529~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y8_N50
dffeas \A_SPW_TOP|rx_data|mem[56][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector529~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[56][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[56][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[56][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y8_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector169~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector169~0_combout  = ( \A_SPW_TOP|rx_data|Selector163~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [2])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux6~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector163~0_combout  & ( \A_SPW_TOP|rx_data|mem[16][2]~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .datab(!\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|mem[16][2]~q ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector163~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector169~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector169~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector169~0 .lut_mask = 64'h0F0F0F0F55335533;
defparam \A_SPW_TOP|rx_data|Selector169~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y8_N35
dffeas \A_SPW_TOP|rx_data|mem[16][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector169~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[16][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[16][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[16][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y8_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux6~2 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux6~2_combout  = ( \A_SPW_TOP|rx_data|mem[56][2]~q  & ( \A_SPW_TOP|rx_data|mem[16][2]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & ((!\A_SPW_TOP|rx_data|wr_ptr [3]) # ((\A_SPW_TOP|rx_data|mem[24][2]~q )))) # (\A_SPW_TOP|rx_data|wr_ptr [5] 
// & (((\A_SPW_TOP|rx_data|mem[48][2]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [3]))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[56][2]~q  & ( \A_SPW_TOP|rx_data|mem[16][2]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & ((!\A_SPW_TOP|rx_data|wr_ptr [3]) # 
// ((\A_SPW_TOP|rx_data|mem[24][2]~q )))) # (\A_SPW_TOP|rx_data|wr_ptr [5] & (!\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|mem[48][2]~q ))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[56][2]~q  & ( !\A_SPW_TOP|rx_data|mem[16][2]~q  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|wr_ptr [3] & ((\A_SPW_TOP|rx_data|mem[24][2]~q )))) # (\A_SPW_TOP|rx_data|wr_ptr [5] & (((\A_SPW_TOP|rx_data|mem[48][2]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [3]))) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|mem[56][2]~q  & ( !\A_SPW_TOP|rx_data|mem[16][2]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|wr_ptr [3] & ((\A_SPW_TOP|rx_data|mem[24][2]~q )))) # (\A_SPW_TOP|rx_data|wr_ptr [5] & (!\A_SPW_TOP|rx_data|wr_ptr [3] & 
// (\A_SPW_TOP|rx_data|mem[48][2]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datac(!\A_SPW_TOP|rx_data|mem[48][2]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[24][2]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[56][2]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[16][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux6~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux6~2 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux6~2 .lut_mask = 64'h042615378CAE9DBF;
defparam \A_SPW_TOP|rx_data|Mux6~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y8_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux6~4 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux6~4_combout  = ( \A_SPW_TOP|rx_data|Mux6~2_combout  & ( \A_SPW_TOP|rx_data|wr_ptr [4] & ( (!\A_SPW_TOP|rx_data|wr_ptr [2]) # (\A_SPW_TOP|rx_data|Mux6~3_combout ) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux6~2_combout  & ( 
// \A_SPW_TOP|rx_data|wr_ptr [4] & ( (\A_SPW_TOP|rx_data|Mux6~3_combout  & \A_SPW_TOP|rx_data|wr_ptr [2]) ) ) ) # ( \A_SPW_TOP|rx_data|Mux6~2_combout  & ( !\A_SPW_TOP|rx_data|wr_ptr [4] & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & 
// ((\A_SPW_TOP|rx_data|Mux6~0_combout ))) # (\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|Mux6~1_combout )) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux6~2_combout  & ( !\A_SPW_TOP|rx_data|wr_ptr [4] & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & 
// ((\A_SPW_TOP|rx_data|Mux6~0_combout ))) # (\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|Mux6~1_combout )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux6~3_combout ),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datac(!\A_SPW_TOP|rx_data|Mux6~1_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux6~0_combout ),
        .datae(!\A_SPW_TOP|rx_data|Mux6~2_combout ),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux6~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux6~4 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux6~4 .lut_mask = 64'h03CF03CF1111DDDD;
defparam \A_SPW_TOP|rx_data|Mux6~4 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y8_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector187~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector187~0_combout  = ( \A_SPW_TOP|rx_data|mem[18][2]~q  & ( (!\A_SPW_TOP|rx_data|Selector181~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [2]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux6~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[18][2]~q  & ( (\A_SPW_TOP|rx_data|Selector181~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [2]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux6~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector181~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .datae(!\A_SPW_TOP|rx_data|mem[18][2]~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector187~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector187~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector187~0 .lut_mask = 64'h010BF1FB010BF1FB;
defparam \A_SPW_TOP|rx_data|Selector187~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y8_N29
dffeas \A_SPW_TOP|rx_data|mem[18][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector187~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[18][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[18][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[18][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y8_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector475~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector475~0_combout  = ( \A_SPW_TOP|rx_data|mem[50][2]~q  & ( (!\A_SPW_TOP|rx_data|Selector469~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [2]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux6~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[50][2]~q  & ( (\A_SPW_TOP|rx_data|Selector469~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [2]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux6~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Selector469~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[50][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector475~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector475~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector475~0 .lut_mask = 64'h010D010DF1FDF1FD;
defparam \A_SPW_TOP|rx_data|Selector475~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y8_N14
dffeas \A_SPW_TOP|rx_data|mem[50][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector475~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[50][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[50][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[50][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y8_N33
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector547~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector547~0_combout  = ( \A_SPW_TOP|rx_data|mem[58][2]~q  & ( (!\A_SPW_TOP|rx_data|Selector541~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [2]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux6~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[58][2]~q  & ( (\A_SPW_TOP|rx_data|Selector541~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [2]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux6~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Selector541~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[58][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector547~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector547~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector547~0 .lut_mask = 64'h010D010DF1FDF1FD;
defparam \A_SPW_TOP|rx_data|Selector547~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y8_N8
dffeas \A_SPW_TOP|rx_data|mem[58][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector547~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[58][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[58][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[58][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y8_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector259~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector259~0_combout  = ( \A_SPW_TOP|rx_data|Selector253~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [2]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux6~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector253~0_combout  & ( \A_SPW_TOP|rx_data|mem[26][2]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[26][2]~q ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector253~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector259~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector259~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector259~0 .lut_mask = 64'h0F0F0F0F11DD11DD;
defparam \A_SPW_TOP|rx_data|Selector259~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y8_N20
dffeas \A_SPW_TOP|rx_data|mem[26][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector259~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[26][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[26][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[26][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y8_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux6~12 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux6~12_combout  = ( \A_SPW_TOP|rx_data|mem[58][2]~q  & ( \A_SPW_TOP|rx_data|mem[26][2]~q  & ( ((!\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|mem[18][2]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [5] & ((\A_SPW_TOP|rx_data|mem[50][2]~q 
// )))) # (\A_SPW_TOP|rx_data|wr_ptr [3]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[58][2]~q  & ( \A_SPW_TOP|rx_data|mem[26][2]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & (((\A_SPW_TOP|rx_data|wr_ptr [3])) # (\A_SPW_TOP|rx_data|mem[18][2]~q ))) # 
// (\A_SPW_TOP|rx_data|wr_ptr [5] & (((!\A_SPW_TOP|rx_data|wr_ptr [3] & \A_SPW_TOP|rx_data|mem[50][2]~q )))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[58][2]~q  & ( !\A_SPW_TOP|rx_data|mem[26][2]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & 
// (\A_SPW_TOP|rx_data|mem[18][2]~q  & (!\A_SPW_TOP|rx_data|wr_ptr [3]))) # (\A_SPW_TOP|rx_data|wr_ptr [5] & (((\A_SPW_TOP|rx_data|mem[50][2]~q ) # (\A_SPW_TOP|rx_data|wr_ptr [3])))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[58][2]~q  & ( 
// !\A_SPW_TOP|rx_data|mem[26][2]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [3] & ((!\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|mem[18][2]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [5] & ((\A_SPW_TOP|rx_data|mem[50][2]~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datab(!\A_SPW_TOP|rx_data|mem[18][2]~q ),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datad(!\A_SPW_TOP|rx_data|mem[50][2]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[58][2]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[26][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux6~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux6~12 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux6~12 .lut_mask = 64'h207025752A7A2F7F;
defparam \A_SPW_TOP|rx_data|Mux6~12 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y8_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector511~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector511~0_combout  = ( \A_SPW_TOP|rx_data|Selector505~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [2]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux6~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector505~0_combout  & ( \A_SPW_TOP|rx_data|mem[54][2]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .datac(!\A_SPW_TOP|rx_data|mem[54][2]~q ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector505~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector511~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector511~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector511~0 .lut_mask = 64'h0F0F0F0F33553355;
defparam \A_SPW_TOP|rx_data|Selector511~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y8_N35
dffeas \A_SPW_TOP|rx_data|mem[54][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector511~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[54][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[54][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[54][2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y8_N45
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector223~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector223~0_combout  = ( \A_SPW_TOP|rx_data|mem[22][2]~q  & ( (!\A_SPW_TOP|rx_data|Selector217~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [2]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux6~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[22][2]~q  & ( (\A_SPW_TOP|rx_data|Selector217~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [2]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux6~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .datac(!\A_SPW_TOP|rx_data|Selector217~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[22][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector223~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector223~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector223~0 .lut_mask = 64'h03050305F3F5F3F5;
defparam \A_SPW_TOP|rx_data|Selector223~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y8_N14
dffeas \A_SPW_TOP|rx_data|mem[22][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector223~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[22][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[22][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[22][2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y7_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector295~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector295~0_combout  = ( \A_SPW_TOP|rx_data|Mux6~20_combout  & ( \A_SPW_TOP|SPW|RX|rx_data_flag [2] & ( (\A_SPW_TOP|rx_data|Selector289~0_combout ) # (\A_SPW_TOP|rx_data|mem[30][2]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux6~20_combout  & 
// ( \A_SPW_TOP|SPW|RX|rx_data_flag [2] & ( (!\A_SPW_TOP|rx_data|Selector289~0_combout  & (\A_SPW_TOP|rx_data|mem[30][2]~q )) # (\A_SPW_TOP|rx_data|Selector289~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q ))) ) ) ) # ( 
// \A_SPW_TOP|rx_data|Mux6~20_combout  & ( !\A_SPW_TOP|SPW|RX|rx_data_flag [2] & ( (!\A_SPW_TOP|rx_data|Selector289~0_combout  & (\A_SPW_TOP|rx_data|mem[30][2]~q )) # (\A_SPW_TOP|rx_data|Selector289~0_combout  & ((\A_SPW_TOP|rx_data|state_data_write.00~q ))) 
// ) ) ) # ( !\A_SPW_TOP|rx_data|Mux6~20_combout  & ( !\A_SPW_TOP|SPW|RX|rx_data_flag [2] & ( (\A_SPW_TOP|rx_data|mem[30][2]~q  & !\A_SPW_TOP|rx_data|Selector289~0_combout ) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[30][2]~q ),
        .datab(!\A_SPW_TOP|rx_data|Selector289~0_combout ),
        .datac(gnd),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(!\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .dataf(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector295~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector295~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector295~0 .lut_mask = 64'h4444447777447777;
defparam \A_SPW_TOP|rx_data|Selector295~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y7_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|mem[30][2]~feeder (
// Equation(s):
// \A_SPW_TOP|rx_data|mem[30][2]~feeder_combout  = ( \A_SPW_TOP|rx_data|Selector295~0_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector295~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|mem[30][2]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[30][2]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|mem[30][2]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|rx_data|mem[30][2]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y7_N26
dffeas \A_SPW_TOP|rx_data|mem[30][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|rx_data|mem[30][2]~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[30][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[30][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[30][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y8_N57
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector583~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector583~0_combout  = ( \A_SPW_TOP|rx_data|mem[62][2]~q  & ( (!\A_SPW_TOP|rx_data|Selector577~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [2]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux6~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[62][2]~q  & ( (\A_SPW_TOP|rx_data|Selector577~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [2]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux6~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Selector577~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[62][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector583~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector583~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector583~0 .lut_mask = 64'h010D010DF1FDF1FD;
defparam \A_SPW_TOP|rx_data|Selector583~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y8_N53
dffeas \A_SPW_TOP|rx_data|mem[62][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector583~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[62][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[62][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[62][2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y8_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux6~13 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux6~13_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [5] & ( \A_SPW_TOP|rx_data|mem[62][2]~q  & ( (\A_SPW_TOP|rx_data|wr_ptr [3]) # (\A_SPW_TOP|rx_data|mem[54][2]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [5] & ( 
// \A_SPW_TOP|rx_data|mem[62][2]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|mem[22][2]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [3] & ((\A_SPW_TOP|rx_data|mem[30][2]~q ))) ) ) ) # ( \A_SPW_TOP|rx_data|wr_ptr [5] & ( 
// !\A_SPW_TOP|rx_data|mem[62][2]~q  & ( (\A_SPW_TOP|rx_data|mem[54][2]~q  & !\A_SPW_TOP|rx_data|wr_ptr [3]) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [5] & ( !\A_SPW_TOP|rx_data|mem[62][2]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|mem[22][2]~q 
// )) # (\A_SPW_TOP|rx_data|wr_ptr [3] & ((\A_SPW_TOP|rx_data|mem[30][2]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[54][2]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[22][2]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[30][2]~q ),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .dataf(!\A_SPW_TOP|rx_data|mem[62][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux6~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux6~13 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux6~13 .lut_mask = 64'h330F5500330F55FF;
defparam \A_SPW_TOP|rx_data|Mux6~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X35_Y8_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector79~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector79~0_combout  = ( \A_SPW_TOP|rx_data|mem[6][2]~q  & ( (!\A_SPW_TOP|rx_data|Selector73~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [2])) # (\A_SPW_TOP|rx_data|state_data_write.00~q 
//  & ((\A_SPW_TOP|rx_data|Mux6~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[6][2]~q  & ( (\A_SPW_TOP|rx_data|Selector73~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [2])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux6~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Selector73~0_combout ),
        .datac(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .datad(!\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .datae(!\A_SPW_TOP|rx_data|mem[6][2]~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector79~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector79~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector79~0 .lut_mask = 64'h0213CEDF0213CEDF;
defparam \A_SPW_TOP|rx_data|Selector79~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X35_Y8_N29
dffeas \A_SPW_TOP|rx_data|mem[6][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector79~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[6][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[6][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[6][2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y8_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector439~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector439~0_combout  = ( \A_SPW_TOP|rx_data|mem[46][2]~q  & ( (!\A_SPW_TOP|rx_data|Selector433~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [2]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux6~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[46][2]~q  & ( (\A_SPW_TOP|rx_data|Selector433~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [2]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux6~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .datac(!\A_SPW_TOP|rx_data|Selector433~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[46][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector439~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector439~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector439~0 .lut_mask = 64'h03050305F3F5F3F5;
defparam \A_SPW_TOP|rx_data|Selector439~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y8_N11
dffeas \A_SPW_TOP|rx_data|mem[46][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector439~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[46][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[46][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[46][2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y8_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector367~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector367~0_combout  = ( \A_SPW_TOP|rx_data|mem[38][2]~q  & ( (!\A_SPW_TOP|rx_data|Selector361~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [2]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux6~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[38][2]~q  & ( (\A_SPW_TOP|rx_data|Selector361~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [2]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux6~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .datac(!\A_SPW_TOP|rx_data|Selector361~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[38][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector367~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector367~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector367~0 .lut_mask = 64'h03050305F3F5F3F5;
defparam \A_SPW_TOP|rx_data|Selector367~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y8_N53
dffeas \A_SPW_TOP|rx_data|mem[38][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector367~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[38][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[38][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[38][2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y8_N57
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector151~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector151~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector145~0_combout  & ((\A_SPW_TOP|rx_data|mem[14][2]~q ))) # (\A_SPW_TOP|rx_data|Selector145~0_combout  & 
// (\A_SPW_TOP|rx_data|Mux6~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector145~0_combout  & ((\A_SPW_TOP|rx_data|mem[14][2]~q ))) # (\A_SPW_TOP|rx_data|Selector145~0_combout  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [2])) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .datac(!\A_SPW_TOP|rx_data|mem[14][2]~q ),
        .datad(!\A_SPW_TOP|rx_data|Selector145~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector151~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector151~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector151~0 .lut_mask = 64'h0F330F330F550F55;
defparam \A_SPW_TOP|rx_data|Selector151~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y8_N41
dffeas \A_SPW_TOP|rx_data|mem[14][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector151~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[14][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[14][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[14][2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y8_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux6~11 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux6~11_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [5] & ( \A_SPW_TOP|rx_data|wr_ptr [3] & ( \A_SPW_TOP|rx_data|mem[46][2]~q  ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [5] & ( \A_SPW_TOP|rx_data|wr_ptr [3] & ( \A_SPW_TOP|rx_data|mem[14][2]~q  ) 
// ) ) # ( \A_SPW_TOP|rx_data|wr_ptr [5] & ( !\A_SPW_TOP|rx_data|wr_ptr [3] & ( \A_SPW_TOP|rx_data|mem[38][2]~q  ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [5] & ( !\A_SPW_TOP|rx_data|wr_ptr [3] & ( \A_SPW_TOP|rx_data|mem[6][2]~q  ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[6][2]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[46][2]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[38][2]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[14][2]~q ),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux6~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux6~11 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux6~11 .lut_mask = 64'h55550F0F00FF3333;
defparam \A_SPW_TOP|rx_data|Mux6~11 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y8_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector115~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector115~0_combout  = ( \A_SPW_TOP|rx_data|mem[10][2]~q  & ( (!\A_SPW_TOP|rx_data|Selector109~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [2]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux6~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[10][2]~q  & ( (\A_SPW_TOP|rx_data|Selector109~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [2]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux6~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Selector109~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[10][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector115~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector115~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector115~0 .lut_mask = 64'h010D010DF1FDF1FD;
defparam \A_SPW_TOP|rx_data|Selector115~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y8_N11
dffeas \A_SPW_TOP|rx_data|mem[10][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector115~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[10][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[10][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[10][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y8_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector331~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector331~0_combout  = ( \A_SPW_TOP|rx_data|Selector325~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [2]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux6~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector325~0_combout  & ( \A_SPW_TOP|rx_data|mem[34][2]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[34][2]~q ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector325~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector331~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector331~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector331~0 .lut_mask = 64'h0F0F0F0F11DD11DD;
defparam \A_SPW_TOP|rx_data|Selector331~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y8_N23
dffeas \A_SPW_TOP|rx_data|mem[34][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector331~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[34][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[34][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[34][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y8_N27
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector403~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector403~0_combout  = ( \A_SPW_TOP|rx_data|Selector397~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [2]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux6~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector397~0_combout  & ( \A_SPW_TOP|rx_data|mem[42][2]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[42][2]~q ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector397~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector403~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector403~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector403~0 .lut_mask = 64'h0F0F0F0F11DD11DD;
defparam \A_SPW_TOP|rx_data|Selector403~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y8_N44
dffeas \A_SPW_TOP|rx_data|mem[42][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector403~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[42][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[42][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[42][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y8_N39
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector43~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector43~0_combout  = ( \A_SPW_TOP|rx_data|mem[2][2]~q  & ( (!\A_SPW_TOP|rx_data|Selector37~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [2]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux6~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[2][2]~q  & ( (\A_SPW_TOP|rx_data|Selector37~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [2]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux6~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Selector37~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[2][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector43~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector43~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector43~0 .lut_mask = 64'h010D010DF1FDF1FD;
defparam \A_SPW_TOP|rx_data|Selector43~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y8_N50
dffeas \A_SPW_TOP|rx_data|mem[2][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector43~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[2][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[2][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[2][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y8_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux6~10 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux6~10_combout  = ( \A_SPW_TOP|rx_data|mem[42][2]~q  & ( \A_SPW_TOP|rx_data|mem[2][2]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & (((!\A_SPW_TOP|rx_data|wr_ptr [3])) # (\A_SPW_TOP|rx_data|mem[10][2]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [5] 
// & (((\A_SPW_TOP|rx_data|wr_ptr [3]) # (\A_SPW_TOP|rx_data|mem[34][2]~q )))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[42][2]~q  & ( \A_SPW_TOP|rx_data|mem[2][2]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & (((!\A_SPW_TOP|rx_data|wr_ptr [3])) # 
// (\A_SPW_TOP|rx_data|mem[10][2]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [5] & (((\A_SPW_TOP|rx_data|mem[34][2]~q  & !\A_SPW_TOP|rx_data|wr_ptr [3])))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[42][2]~q  & ( !\A_SPW_TOP|rx_data|mem[2][2]~q  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|mem[10][2]~q  & ((\A_SPW_TOP|rx_data|wr_ptr [3])))) # (\A_SPW_TOP|rx_data|wr_ptr [5] & (((\A_SPW_TOP|rx_data|wr_ptr [3]) # (\A_SPW_TOP|rx_data|mem[34][2]~q )))) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|mem[42][2]~q  & ( !\A_SPW_TOP|rx_data|mem[2][2]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|mem[10][2]~q  & ((\A_SPW_TOP|rx_data|wr_ptr [3])))) # (\A_SPW_TOP|rx_data|wr_ptr [5] & (((\A_SPW_TOP|rx_data|mem[34][2]~q  & 
// !\A_SPW_TOP|rx_data|wr_ptr [3])))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datab(!\A_SPW_TOP|rx_data|mem[10][2]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[34][2]~q ),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datae(!\A_SPW_TOP|rx_data|mem[42][2]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[2][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux6~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux6~10 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux6~10 .lut_mask = 64'h05220577AF22AF77;
defparam \A_SPW_TOP|rx_data|Mux6~10 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y8_N51
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux6~14 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux6~14_combout  = ( \A_SPW_TOP|rx_data|Mux6~10_combout  & ( \A_SPW_TOP|rx_data|wr_ptr [4] & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|Mux6~12_combout )) # (\A_SPW_TOP|rx_data|wr_ptr [2] & 
// ((\A_SPW_TOP|rx_data|Mux6~13_combout ))) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux6~10_combout  & ( \A_SPW_TOP|rx_data|wr_ptr [4] & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|Mux6~12_combout )) # (\A_SPW_TOP|rx_data|wr_ptr [2] & 
// ((\A_SPW_TOP|rx_data|Mux6~13_combout ))) ) ) ) # ( \A_SPW_TOP|rx_data|Mux6~10_combout  & ( !\A_SPW_TOP|rx_data|wr_ptr [4] & ( (!\A_SPW_TOP|rx_data|wr_ptr [2]) # (\A_SPW_TOP|rx_data|Mux6~11_combout ) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux6~10_combout  & ( 
// !\A_SPW_TOP|rx_data|wr_ptr [4] & ( (\A_SPW_TOP|rx_data|wr_ptr [2] & \A_SPW_TOP|rx_data|Mux6~11_combout ) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux6~12_combout ),
        .datab(!\A_SPW_TOP|rx_data|Mux6~13_combout ),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datad(!\A_SPW_TOP|rx_data|Mux6~11_combout ),
        .datae(!\A_SPW_TOP|rx_data|Mux6~10_combout ),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux6~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux6~14 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux6~14 .lut_mask = 64'h000FF0FF53535353;
defparam \A_SPW_TOP|rx_data|Mux6~14 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y8_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector52~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector52~0_combout  = ( \A_SPW_TOP|rx_data|Selector46~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [2]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux6~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector46~0_combout  & ( \A_SPW_TOP|rx_data|mem[3][2]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .datac(!\A_SPW_TOP|rx_data|mem[3][2]~q ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector46~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector52~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector52~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector52~0 .lut_mask = 64'h0F0F0F0F33553355;
defparam \A_SPW_TOP|rx_data|Selector52~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y8_N23
dffeas \A_SPW_TOP|rx_data|mem[3][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector52~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[3][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[3][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[3][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X36_Y8_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector160~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector160~0_combout  = ( \A_SPW_TOP|rx_data|mem[15][2]~q  & ( (!\A_SPW_TOP|rx_data|Selector154~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [2]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux6~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[15][2]~q  & ( (\A_SPW_TOP|rx_data|Selector154~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [2]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux6~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .datac(!\A_SPW_TOP|rx_data|Selector154~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[15][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector160~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector160~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector160~0 .lut_mask = 64'h03050305F3F5F3F5;
defparam \A_SPW_TOP|rx_data|Selector160~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X36_Y8_N17
dffeas \A_SPW_TOP|rx_data|mem[15][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector160~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[15][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[15][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[15][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y8_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector124~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector124~0_combout  = ( \A_SPW_TOP|rx_data|mem[11][2]~q  & ( (!\A_SPW_TOP|rx_data|Selector118~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [2]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux6~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[11][2]~q  & ( (\A_SPW_TOP|rx_data|Selector118~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [2]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux6~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Selector118~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[11][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector124~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector124~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector124~0 .lut_mask = 64'h010D010DF1FDF1FD;
defparam \A_SPW_TOP|rx_data|Selector124~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y8_N17
dffeas \A_SPW_TOP|rx_data|mem[11][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector124~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[11][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[11][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[11][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y8_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector88~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector88~0_combout  = ( \A_SPW_TOP|rx_data|Selector82~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [2]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux6~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector82~0_combout  & ( \A_SPW_TOP|rx_data|mem[7][2]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[7][2]~q ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector82~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector88~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector88~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector88~0 .lut_mask = 64'h0F0F0F0F11DD11DD;
defparam \A_SPW_TOP|rx_data|Selector88~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y8_N47
dffeas \A_SPW_TOP|rx_data|mem[7][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector88~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[7][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[7][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[7][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X36_Y8_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux6~15 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux6~15_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [2] & ( \A_SPW_TOP|rx_data|mem[7][2]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [3]) # (\A_SPW_TOP|rx_data|mem[15][2]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [2] & ( \A_SPW_TOP|rx_data|mem[7][2]~q 
//  & ( (!\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|mem[3][2]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [3] & ((\A_SPW_TOP|rx_data|mem[11][2]~q ))) ) ) ) # ( \A_SPW_TOP|rx_data|wr_ptr [2] & ( !\A_SPW_TOP|rx_data|mem[7][2]~q  & ( 
// (\A_SPW_TOP|rx_data|mem[15][2]~q  & \A_SPW_TOP|rx_data|wr_ptr [3]) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [2] & ( !\A_SPW_TOP|rx_data|mem[7][2]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|mem[3][2]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [3] & 
// ((\A_SPW_TOP|rx_data|mem[11][2]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[3][2]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[15][2]~q ),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datad(!\A_SPW_TOP|rx_data|mem[11][2]~q ),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .dataf(!\A_SPW_TOP|rx_data|mem[7][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux6~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux6~15 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux6~15 .lut_mask = 64'h505F0303505FF3F3;
defparam \A_SPW_TOP|rx_data|Mux6~15 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X36_Y8_N57
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector304~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector304~0_combout  = ( \A_SPW_TOP|rx_data|Mux6~20_combout  & ( (!\A_SPW_TOP|rx_data|Selector298~0_combout  & (((\A_SPW_TOP|rx_data|mem[31][2]~q )))) # (\A_SPW_TOP|rx_data|Selector298~0_combout  & (((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [2])) # (\A_SPW_TOP|rx_data|state_data_write.00~q ))) ) ) # ( !\A_SPW_TOP|rx_data|Mux6~20_combout  & ( (!\A_SPW_TOP|rx_data|Selector298~0_combout  & (((\A_SPW_TOP|rx_data|mem[31][2]~q )))) # (\A_SPW_TOP|rx_data|Selector298~0_combout  & 
// (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [2]))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .datac(!\A_SPW_TOP|rx_data|Selector298~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[31][2]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector304~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector304~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector304~0 .lut_mask = 64'h02F202F207F707F7;
defparam \A_SPW_TOP|rx_data|Selector304~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X36_Y8_N29
dffeas \A_SPW_TOP|rx_data|mem[31][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector304~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[31][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[31][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[31][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X36_Y8_N45
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector232~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector232~0_combout  = ( \A_SPW_TOP|rx_data|Mux6~20_combout  & ( (!\A_SPW_TOP|rx_data|Selector226~0_combout  & (((\A_SPW_TOP|rx_data|mem[23][2]~q )))) # (\A_SPW_TOP|rx_data|Selector226~0_combout  & (((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [2])) # (\A_SPW_TOP|rx_data|state_data_write.00~q ))) ) ) # ( !\A_SPW_TOP|rx_data|Mux6~20_combout  & ( (!\A_SPW_TOP|rx_data|Selector226~0_combout  & (((\A_SPW_TOP|rx_data|mem[23][2]~q )))) # (\A_SPW_TOP|rx_data|Selector226~0_combout  & 
// (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [2]))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .datac(!\A_SPW_TOP|rx_data|Selector226~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[23][2]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector232~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector232~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector232~0 .lut_mask = 64'h02F202F207F707F7;
defparam \A_SPW_TOP|rx_data|Selector232~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X36_Y8_N5
dffeas \A_SPW_TOP|rx_data|mem[23][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector232~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[23][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[23][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[23][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X36_Y8_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector268~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector268~0_combout  = ( \A_SPW_TOP|rx_data|mem[27][2]~q  & ( (!\A_SPW_TOP|rx_data|Selector262~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [2])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux6~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[27][2]~q  & ( (\A_SPW_TOP|rx_data|Selector262~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [2])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux6~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .datac(!\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .datad(!\A_SPW_TOP|rx_data|Selector262~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[27][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector268~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector268~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector268~0 .lut_mask = 64'h00270027FF27FF27;
defparam \A_SPW_TOP|rx_data|Selector268~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X36_Y8_N32
dffeas \A_SPW_TOP|rx_data|mem[27][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector268~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[27][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[27][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[27][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X36_Y8_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux6~17 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux6~17_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [3] & ( \A_SPW_TOP|rx_data|mem[27][2]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2]) # (\A_SPW_TOP|rx_data|mem[31][2]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [3] & ( 
// \A_SPW_TOP|rx_data|mem[27][2]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|mem[19][2]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [2] & ((\A_SPW_TOP|rx_data|mem[23][2]~q ))) ) ) ) # ( \A_SPW_TOP|rx_data|wr_ptr [3] & ( 
// !\A_SPW_TOP|rx_data|mem[27][2]~q  & ( (\A_SPW_TOP|rx_data|mem[31][2]~q  & \A_SPW_TOP|rx_data|wr_ptr [2]) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [3] & ( !\A_SPW_TOP|rx_data|mem[27][2]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|mem[19][2]~q 
// )) # (\A_SPW_TOP|rx_data|wr_ptr [2] & ((\A_SPW_TOP|rx_data|mem[23][2]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[31][2]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[19][2]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[23][2]~q ),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .dataf(!\A_SPW_TOP|rx_data|mem[27][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux6~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux6~17 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux6~17 .lut_mask = 64'h330F0055330FFF55;
defparam \A_SPW_TOP|rx_data|Mux6~17 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X36_Y8_N39
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector520~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector520~0_combout  = ( \A_SPW_TOP|rx_data|mem[55][2]~q  & ( (!\A_SPW_TOP|rx_data|Selector514~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [2]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux6~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[55][2]~q  & ( (\A_SPW_TOP|rx_data|Selector514~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [2]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux6~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|Selector514~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[55][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector520~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector520~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector520~0 .lut_mask = 64'h00350035FF35FF35;
defparam \A_SPW_TOP|rx_data|Selector520~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X36_Y8_N11
dffeas \A_SPW_TOP|rx_data|mem[55][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector520~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[55][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[55][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[55][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X35_Y8_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector484~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector484~0_combout  = ( \A_SPW_TOP|rx_data|Selector478~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [2])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux6~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector478~0_combout  & ( \A_SPW_TOP|rx_data|mem[51][2]~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .datab(!\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|mem[51][2]~q ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector478~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector484~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector484~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector484~0 .lut_mask = 64'h0F0F0F0F55335533;
defparam \A_SPW_TOP|rx_data|Selector484~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X35_Y8_N5
dffeas \A_SPW_TOP|rx_data|mem[51][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector484~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[51][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[51][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[51][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X35_Y8_N51
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector592~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector592~0_combout  = ( \A_SPW_TOP|rx_data|mem[63][2]~q  & ( (!\A_SPW_TOP|rx_data|Selector586~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [2])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux6~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[63][2]~q  & ( (\A_SPW_TOP|rx_data|Selector586~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [2])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux6~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .datab(!\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|Selector586~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[63][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector592~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector592~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector592~0 .lut_mask = 64'h00530053FF53FF53;
defparam \A_SPW_TOP|rx_data|Selector592~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X35_Y8_N2
dffeas \A_SPW_TOP|rx_data|mem[63][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector592~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[63][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[63][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[63][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X36_Y8_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector556~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector556~0_combout  = ( \A_SPW_TOP|rx_data|Mux6~20_combout  & ( (!\A_SPW_TOP|rx_data|Selector550~0_combout  & (((\A_SPW_TOP|rx_data|mem[59][2]~q )))) # (\A_SPW_TOP|rx_data|Selector550~0_combout  & (((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [2])) # (\A_SPW_TOP|rx_data|state_data_write.00~q ))) ) ) # ( !\A_SPW_TOP|rx_data|Mux6~20_combout  & ( (!\A_SPW_TOP|rx_data|Selector550~0_combout  & (((\A_SPW_TOP|rx_data|mem[59][2]~q )))) # (\A_SPW_TOP|rx_data|Selector550~0_combout  & 
// (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [2]))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .datac(!\A_SPW_TOP|rx_data|Selector550~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[59][2]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector556~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector556~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector556~0 .lut_mask = 64'h02F202F207F707F7;
defparam \A_SPW_TOP|rx_data|Selector556~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X35_Y8_N44
dffeas \A_SPW_TOP|rx_data|mem[59][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector556~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[59][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[59][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[59][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X35_Y8_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux6~18 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux6~18_combout  = ( \A_SPW_TOP|rx_data|mem[59][2]~q  & ( \A_SPW_TOP|rx_data|wr_ptr [2] & ( (!\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|mem[55][2]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [3] & ((\A_SPW_TOP|rx_data|mem[63][2]~q ))) ) 
// ) ) # ( !\A_SPW_TOP|rx_data|mem[59][2]~q  & ( \A_SPW_TOP|rx_data|wr_ptr [2] & ( (!\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|mem[55][2]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [3] & ((\A_SPW_TOP|rx_data|mem[63][2]~q ))) ) ) ) # ( 
// \A_SPW_TOP|rx_data|mem[59][2]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [2] & ( (\A_SPW_TOP|rx_data|mem[51][2]~q ) # (\A_SPW_TOP|rx_data|wr_ptr [3]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[59][2]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [2] & ( (!\A_SPW_TOP|rx_data|wr_ptr [3] 
// & \A_SPW_TOP|rx_data|mem[51][2]~q ) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[55][2]~q ),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datac(!\A_SPW_TOP|rx_data|mem[51][2]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[63][2]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[59][2]~q ),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux6~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux6~18 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux6~18 .lut_mask = 64'h0C0C3F3F44774477;
defparam \A_SPW_TOP|rx_data|Mux6~18 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X36_Y8_N51
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector340~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector340~0_combout  = ( \A_SPW_TOP|rx_data|mem[35][2]~q  & ( (!\A_SPW_TOP|rx_data|Selector334~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [2]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux6~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[35][2]~q  & ( (\A_SPW_TOP|rx_data|Selector334~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [2]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux6~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .datac(!\A_SPW_TOP|rx_data|Selector334~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[35][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector340~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector340~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector340~0 .lut_mask = 64'h03050305F3F5F3F5;
defparam \A_SPW_TOP|rx_data|Selector340~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X35_Y8_N20
dffeas \A_SPW_TOP|rx_data|mem[35][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector340~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[35][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[35][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[35][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X35_Y8_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector412~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector412~0_combout  = ( \A_SPW_TOP|rx_data|mem[43][2]~q  & ( (!\A_SPW_TOP|rx_data|Selector406~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [2])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux6~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[43][2]~q  & ( (\A_SPW_TOP|rx_data|Selector406~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [2])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux6~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .datab(!\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|Selector406~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[43][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector412~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector412~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector412~0 .lut_mask = 64'h00530053FF53FF53;
defparam \A_SPW_TOP|rx_data|Selector412~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X35_Y8_N56
dffeas \A_SPW_TOP|rx_data|mem[43][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector412~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[43][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[43][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[43][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X35_Y8_N39
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector448~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector448~0_combout  = ( \A_SPW_TOP|rx_data|mem[47][2]~q  & ( (!\A_SPW_TOP|rx_data|Selector442~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [2])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux6~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[47][2]~q  & ( (\A_SPW_TOP|rx_data|Selector442~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [2])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux6~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .datab(!\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|Selector442~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[47][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector448~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector448~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector448~0 .lut_mask = 64'h00530053FF53FF53;
defparam \A_SPW_TOP|rx_data|Selector448~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X35_Y8_N8
dffeas \A_SPW_TOP|rx_data|mem[47][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector448~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[47][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[47][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[47][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X36_Y8_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector376~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector376~0_combout  = ( \A_SPW_TOP|rx_data|Selector370~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [2]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux6~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector370~0_combout  & ( \A_SPW_TOP|rx_data|mem[39][2]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .datac(!\A_SPW_TOP|rx_data|mem[39][2]~q ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector370~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector376~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector376~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector376~0 .lut_mask = 64'h0F0F0F0F33553355;
defparam \A_SPW_TOP|rx_data|Selector376~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X35_Y8_N11
dffeas \A_SPW_TOP|rx_data|mem[39][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector376~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[39][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[39][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[39][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X35_Y8_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux6~16 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux6~16_combout  = ( \A_SPW_TOP|rx_data|mem[47][2]~q  & ( \A_SPW_TOP|rx_data|mem[39][2]~q  & ( ((!\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|mem[35][2]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [3] & ((\A_SPW_TOP|rx_data|mem[43][2]~q 
// )))) # (\A_SPW_TOP|rx_data|wr_ptr [2]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[47][2]~q  & ( \A_SPW_TOP|rx_data|mem[39][2]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & ((!\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|mem[35][2]~q )) # 
// (\A_SPW_TOP|rx_data|wr_ptr [3] & ((\A_SPW_TOP|rx_data|mem[43][2]~q ))))) # (\A_SPW_TOP|rx_data|wr_ptr [2] & (((!\A_SPW_TOP|rx_data|wr_ptr [3])))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[47][2]~q  & ( !\A_SPW_TOP|rx_data|mem[39][2]~q  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [2] & ((!\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|mem[35][2]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [3] & ((\A_SPW_TOP|rx_data|mem[43][2]~q ))))) # (\A_SPW_TOP|rx_data|wr_ptr [2] & (((\A_SPW_TOP|rx_data|wr_ptr [3])))) ) ) 
// ) # ( !\A_SPW_TOP|rx_data|mem[47][2]~q  & ( !\A_SPW_TOP|rx_data|mem[39][2]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & ((!\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|mem[35][2]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [3] & ((\A_SPW_TOP|rx_data|mem[43][2]~q 
// ))))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[35][2]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[43][2]~q ),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datae(!\A_SPW_TOP|rx_data|mem[47][2]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[39][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux6~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux6~16 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux6~16 .lut_mask = 64'h5030503F5F305F3F;
defparam \A_SPW_TOP|rx_data|Mux6~16 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X35_Y8_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux6~19 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux6~19_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [5] & ( \A_SPW_TOP|rx_data|Mux6~16_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [4]) # (\A_SPW_TOP|rx_data|Mux6~18_combout ) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [5] & ( 
// \A_SPW_TOP|rx_data|Mux6~16_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|Mux6~15_combout )) # (\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|Mux6~17_combout ))) ) ) ) # ( \A_SPW_TOP|rx_data|wr_ptr [5] & ( 
// !\A_SPW_TOP|rx_data|Mux6~16_combout  & ( (\A_SPW_TOP|rx_data|wr_ptr [4] & \A_SPW_TOP|rx_data|Mux6~18_combout ) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [5] & ( !\A_SPW_TOP|rx_data|Mux6~16_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [4] & 
// (\A_SPW_TOP|rx_data|Mux6~15_combout )) # (\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|Mux6~17_combout ))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux6~15_combout ),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datac(!\A_SPW_TOP|rx_data|Mux6~17_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux6~18_combout ),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .dataf(!\A_SPW_TOP|rx_data|Mux6~16_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux6~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux6~19 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux6~19 .lut_mask = 64'h474700334747CCFF;
defparam \A_SPW_TOP|rx_data|Mux6~19 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y8_N15
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux6~20 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux6~20_combout  = ( \A_SPW_TOP|rx_data|Mux6~14_combout  & ( \A_SPW_TOP|rx_data|Mux6~19_combout  & ( ((!\A_SPW_TOP|rx_data|wr_ptr [0] & ((\A_SPW_TOP|rx_data|Mux6~4_combout ))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & 
// (\A_SPW_TOP|rx_data|Mux6~9_combout ))) # (\A_SPW_TOP|rx_data|wr_ptr [1]) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux6~14_combout  & ( \A_SPW_TOP|rx_data|Mux6~19_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & (((\A_SPW_TOP|rx_data|Mux6~4_combout  & 
// !\A_SPW_TOP|rx_data|wr_ptr [1])))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & (((\A_SPW_TOP|rx_data|wr_ptr [1])) # (\A_SPW_TOP|rx_data|Mux6~9_combout ))) ) ) ) # ( \A_SPW_TOP|rx_data|Mux6~14_combout  & ( !\A_SPW_TOP|rx_data|Mux6~19_combout  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [0] & (((\A_SPW_TOP|rx_data|wr_ptr [1]) # (\A_SPW_TOP|rx_data|Mux6~4_combout )))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|Mux6~9_combout  & ((!\A_SPW_TOP|rx_data|wr_ptr [1])))) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|Mux6~14_combout  & ( !\A_SPW_TOP|rx_data|Mux6~19_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & ((!\A_SPW_TOP|rx_data|wr_ptr [0] & ((\A_SPW_TOP|rx_data|Mux6~4_combout ))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & 
// (\A_SPW_TOP|rx_data|Mux6~9_combout )))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux6~9_combout ),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datac(!\A_SPW_TOP|rx_data|Mux6~4_combout ),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datae(!\A_SPW_TOP|rx_data|Mux6~14_combout ),
        .dataf(!\A_SPW_TOP|rx_data|Mux6~19_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux6~20 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux6~20 .lut_mask = 64'h1D001DCC1D331DFF;
defparam \A_SPW_TOP|rx_data|Mux6~20 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y7_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector196~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector196~0_combout  = ( \A_SPW_TOP|rx_data|mem[19][2]~q  & ( (!\A_SPW_TOP|rx_data|Selector190~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [2]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux6~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[19][2]~q  & ( (\A_SPW_TOP|rx_data|Selector190~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [2]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux6~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Selector190~0_combout ),
        .datab(!\A_SPW_TOP|rx_data|Mux6~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[19][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector196~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector196~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector196~0 .lut_mask = 64'h01510151ABFBABFB;
defparam \A_SPW_TOP|rx_data|Selector196~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y7_N35
dffeas \A_SPW_TOP|rx_data|mem[19][2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector196~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[19][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[19][2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[19][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X36_Y8_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux15~11 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux15~11_combout  = ( \A_SPW_TOP|rx_data|mem[3][2]~q  & ( \A_SPW_TOP|rx_data|mem[11][2]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [4]) # ((!\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|mem[19][2]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [3] & 
// ((\A_SPW_TOP|rx_data|mem[27][2]~q )))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[3][2]~q  & ( \A_SPW_TOP|rx_data|mem[11][2]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|mem[19][2]~q  & ((\A_SPW_TOP|rx_data|rd_ptr [4])))) # 
// (\A_SPW_TOP|rx_data|rd_ptr [3] & (((!\A_SPW_TOP|rx_data|rd_ptr [4]) # (\A_SPW_TOP|rx_data|mem[27][2]~q )))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[3][2]~q  & ( !\A_SPW_TOP|rx_data|mem[11][2]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [3] & (((!\A_SPW_TOP|rx_data|rd_ptr 
// [4])) # (\A_SPW_TOP|rx_data|mem[19][2]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [3] & (((\A_SPW_TOP|rx_data|mem[27][2]~q  & \A_SPW_TOP|rx_data|rd_ptr [4])))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[3][2]~q  & ( !\A_SPW_TOP|rx_data|mem[11][2]~q  & ( 
// (\A_SPW_TOP|rx_data|rd_ptr [4] & ((!\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|mem[19][2]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [3] & ((\A_SPW_TOP|rx_data|mem[27][2]~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[19][2]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[27][2]~q ),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [3]),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [4]),
        .datae(!\A_SPW_TOP|rx_data|mem[3][2]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[11][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux15~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux15~11 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux15~11 .lut_mask = 64'h0053F0530F53FF53;
defparam \A_SPW_TOP|rx_data|Mux15~11 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y8_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux15~10 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux15~10_combout  = ( \A_SPW_TOP|rx_data|mem[26][2]~q  & ( \A_SPW_TOP|rx_data|mem[2][2]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & (((!\A_SPW_TOP|rx_data|rd_ptr [3])) # (\A_SPW_TOP|rx_data|mem[10][2]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [4] 
// & (((\A_SPW_TOP|rx_data|mem[18][2]~q ) # (\A_SPW_TOP|rx_data|rd_ptr [3])))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[26][2]~q  & ( \A_SPW_TOP|rx_data|mem[2][2]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & (((!\A_SPW_TOP|rx_data|rd_ptr [3])) # 
// (\A_SPW_TOP|rx_data|mem[10][2]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [4] & (((!\A_SPW_TOP|rx_data|rd_ptr [3] & \A_SPW_TOP|rx_data|mem[18][2]~q )))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[26][2]~q  & ( !\A_SPW_TOP|rx_data|mem[2][2]~q  & ( 
// (!\A_SPW_TOP|rx_data|rd_ptr [4] & (\A_SPW_TOP|rx_data|mem[10][2]~q  & (\A_SPW_TOP|rx_data|rd_ptr [3]))) # (\A_SPW_TOP|rx_data|rd_ptr [4] & (((\A_SPW_TOP|rx_data|mem[18][2]~q ) # (\A_SPW_TOP|rx_data|rd_ptr [3])))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[26][2]~q 
//  & ( !\A_SPW_TOP|rx_data|mem[2][2]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & (\A_SPW_TOP|rx_data|mem[10][2]~q  & (\A_SPW_TOP|rx_data|rd_ptr [3]))) # (\A_SPW_TOP|rx_data|rd_ptr [4] & (((!\A_SPW_TOP|rx_data|rd_ptr [3] & \A_SPW_TOP|rx_data|mem[18][2]~q )))) ) 
// ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [4]),
        .datab(!\A_SPW_TOP|rx_data|mem[10][2]~q ),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [3]),
        .datad(!\A_SPW_TOP|rx_data|mem[18][2]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[26][2]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[2][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux15~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux15~10 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux15~10 .lut_mask = 64'h02520757A2F2A7F7;
defparam \A_SPW_TOP|rx_data|Mux15~10 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X36_Y8_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux15~13 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux15~13_combout  = ( \A_SPW_TOP|rx_data|mem[59][2]~q  & ( \A_SPW_TOP|rx_data|mem[51][2]~q  & ( ((!\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|mem[35][2]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [3] & ((\A_SPW_TOP|rx_data|mem[43][2]~q 
// )))) # (\A_SPW_TOP|rx_data|rd_ptr [4]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[59][2]~q  & ( \A_SPW_TOP|rx_data|mem[51][2]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [3] & (((\A_SPW_TOP|rx_data|rd_ptr [4])) # (\A_SPW_TOP|rx_data|mem[35][2]~q ))) # 
// (\A_SPW_TOP|rx_data|rd_ptr [3] & (((\A_SPW_TOP|rx_data|mem[43][2]~q  & !\A_SPW_TOP|rx_data|rd_ptr [4])))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[59][2]~q  & ( !\A_SPW_TOP|rx_data|mem[51][2]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [3] & 
// (\A_SPW_TOP|rx_data|mem[35][2]~q  & ((!\A_SPW_TOP|rx_data|rd_ptr [4])))) # (\A_SPW_TOP|rx_data|rd_ptr [3] & (((\A_SPW_TOP|rx_data|rd_ptr [4]) # (\A_SPW_TOP|rx_data|mem[43][2]~q )))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[59][2]~q  & ( 
// !\A_SPW_TOP|rx_data|mem[51][2]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & ((!\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|mem[35][2]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [3] & ((\A_SPW_TOP|rx_data|mem[43][2]~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[35][2]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[43][2]~q ),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [3]),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [4]),
        .datae(!\A_SPW_TOP|rx_data|mem[59][2]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[51][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux15~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux15~13 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux15~13 .lut_mask = 64'h5300530F53F053FF;
defparam \A_SPW_TOP|rx_data|Mux15~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y8_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux15~12 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux15~12_combout  = ( \A_SPW_TOP|rx_data|mem[50][2]~q  & ( \A_SPW_TOP|rx_data|mem[42][2]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & (((\A_SPW_TOP|rx_data|rd_ptr [3])) # (\A_SPW_TOP|rx_data|mem[34][2]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [4] 
// & (((!\A_SPW_TOP|rx_data|rd_ptr [3]) # (\A_SPW_TOP|rx_data|mem[58][2]~q )))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[50][2]~q  & ( \A_SPW_TOP|rx_data|mem[42][2]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & (((\A_SPW_TOP|rx_data|rd_ptr [3])) # 
// (\A_SPW_TOP|rx_data|mem[34][2]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [4] & (((\A_SPW_TOP|rx_data|rd_ptr [3] & \A_SPW_TOP|rx_data|mem[58][2]~q )))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[50][2]~q  & ( !\A_SPW_TOP|rx_data|mem[42][2]~q  & ( 
// (!\A_SPW_TOP|rx_data|rd_ptr [4] & (\A_SPW_TOP|rx_data|mem[34][2]~q  & (!\A_SPW_TOP|rx_data|rd_ptr [3]))) # (\A_SPW_TOP|rx_data|rd_ptr [4] & (((!\A_SPW_TOP|rx_data|rd_ptr [3]) # (\A_SPW_TOP|rx_data|mem[58][2]~q )))) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|mem[50][2]~q  & ( !\A_SPW_TOP|rx_data|mem[42][2]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & (\A_SPW_TOP|rx_data|mem[34][2]~q  & (!\A_SPW_TOP|rx_data|rd_ptr [3]))) # (\A_SPW_TOP|rx_data|rd_ptr [4] & (((\A_SPW_TOP|rx_data|rd_ptr [3] & 
// \A_SPW_TOP|rx_data|mem[58][2]~q )))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[34][2]~q ),
        .datab(!\A_SPW_TOP|rx_data|rd_ptr [4]),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [3]),
        .datad(!\A_SPW_TOP|rx_data|mem[58][2]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[50][2]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[42][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux15~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux15~12 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux15~12 .lut_mask = 64'h404370734C4F7C7F;
defparam \A_SPW_TOP|rx_data|Mux15~12 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y8_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux15~14 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux15~14_combout  = ( \A_SPW_TOP|rx_data|rd_ptr [5] & ( \A_SPW_TOP|rx_data|rd_ptr [0] & ( \A_SPW_TOP|rx_data|Mux15~13_combout  ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [5] & ( \A_SPW_TOP|rx_data|rd_ptr [0] & ( 
// \A_SPW_TOP|rx_data|Mux15~11_combout  ) ) ) # ( \A_SPW_TOP|rx_data|rd_ptr [5] & ( !\A_SPW_TOP|rx_data|rd_ptr [0] & ( \A_SPW_TOP|rx_data|Mux15~12_combout  ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [5] & ( !\A_SPW_TOP|rx_data|rd_ptr [0] & ( 
// \A_SPW_TOP|rx_data|Mux15~10_combout  ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux15~11_combout ),
        .datab(!\A_SPW_TOP|rx_data|Mux15~10_combout ),
        .datac(!\A_SPW_TOP|rx_data|Mux15~13_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux15~12_combout ),
        .datae(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux15~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux15~14 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux15~14 .lut_mask = 64'h333300FF55550F0F;
defparam \A_SPW_TOP|rx_data|Mux15~14 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y8_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux15~6 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux15~6_combout  = ( \A_SPW_TOP|rx_data|rd_ptr [4] & ( \A_SPW_TOP|rx_data|mem[29][2]~q  & ( (\A_SPW_TOP|rx_data|mem[28][2]~q ) # (\A_SPW_TOP|rx_data|rd_ptr [0]) ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [4] & ( 
// \A_SPW_TOP|rx_data|mem[29][2]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & (\A_SPW_TOP|rx_data|mem[12][2]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [0] & ((\A_SPW_TOP|rx_data|mem[13][2]~q ))) ) ) ) # ( \A_SPW_TOP|rx_data|rd_ptr [4] & ( 
// !\A_SPW_TOP|rx_data|mem[29][2]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & \A_SPW_TOP|rx_data|mem[28][2]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [4] & ( !\A_SPW_TOP|rx_data|mem[29][2]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & (\A_SPW_TOP|rx_data|mem[12][2]~q 
// )) # (\A_SPW_TOP|rx_data|rd_ptr [0] & ((\A_SPW_TOP|rx_data|mem[13][2]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .datab(!\A_SPW_TOP|rx_data|mem[28][2]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[12][2]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[13][2]~q ),
        .datae(!\A_SPW_TOP|rx_data|rd_ptr [4]),
        .dataf(!\A_SPW_TOP|rx_data|mem[29][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux15~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux15~6 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux15~6 .lut_mask = 64'h0A5F22220A5F7777;
defparam \A_SPW_TOP|rx_data|Mux15~6 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y8_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux15~5 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux15~5_combout  = ( \A_SPW_TOP|rx_data|mem[5][2]~q  & ( \A_SPW_TOP|rx_data|rd_ptr [0] & ( (!\A_SPW_TOP|rx_data|rd_ptr [4]) # (\A_SPW_TOP|rx_data|mem[21][2]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[5][2]~q  & ( \A_SPW_TOP|rx_data|rd_ptr 
// [0] & ( (\A_SPW_TOP|rx_data|rd_ptr [4] & \A_SPW_TOP|rx_data|mem[21][2]~q ) ) ) ) # ( \A_SPW_TOP|rx_data|mem[5][2]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [0] & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & (\A_SPW_TOP|rx_data|mem[4][2]~q )) # (\A_SPW_TOP|rx_data|rd_ptr 
// [4] & ((\A_SPW_TOP|rx_data|mem[20][2]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[5][2]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [0] & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & (\A_SPW_TOP|rx_data|mem[4][2]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [4] & 
// ((\A_SPW_TOP|rx_data|mem[20][2]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[4][2]~q ),
        .datab(!\A_SPW_TOP|rx_data|rd_ptr [4]),
        .datac(!\A_SPW_TOP|rx_data|mem[21][2]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[20][2]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[5][2]~q ),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux15~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux15~5 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux15~5 .lut_mask = 64'h447744770303CFCF;
defparam \A_SPW_TOP|rx_data|Mux15~5 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y8_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux15~7 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux15~7_combout  = ( \A_SPW_TOP|rx_data|mem[53][2]~q  & ( \A_SPW_TOP|rx_data|mem[36][2]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & (((!\A_SPW_TOP|rx_data|rd_ptr [4]) # (\A_SPW_TOP|rx_data|mem[52][2]~q )))) # (\A_SPW_TOP|rx_data|rd_ptr [0] 
// & (((\A_SPW_TOP|rx_data|rd_ptr [4])) # (\A_SPW_TOP|rx_data|mem[37][2]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[53][2]~q  & ( \A_SPW_TOP|rx_data|mem[36][2]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & (((!\A_SPW_TOP|rx_data|rd_ptr [4]) # 
// (\A_SPW_TOP|rx_data|mem[52][2]~q )))) # (\A_SPW_TOP|rx_data|rd_ptr [0] & (\A_SPW_TOP|rx_data|mem[37][2]~q  & ((!\A_SPW_TOP|rx_data|rd_ptr [4])))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[53][2]~q  & ( !\A_SPW_TOP|rx_data|mem[36][2]~q  & ( 
// (!\A_SPW_TOP|rx_data|rd_ptr [0] & (((\A_SPW_TOP|rx_data|mem[52][2]~q  & \A_SPW_TOP|rx_data|rd_ptr [4])))) # (\A_SPW_TOP|rx_data|rd_ptr [0] & (((\A_SPW_TOP|rx_data|rd_ptr [4])) # (\A_SPW_TOP|rx_data|mem[37][2]~q ))) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|mem[53][2]~q  & ( !\A_SPW_TOP|rx_data|mem[36][2]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & (((\A_SPW_TOP|rx_data|mem[52][2]~q  & \A_SPW_TOP|rx_data|rd_ptr [4])))) # (\A_SPW_TOP|rx_data|rd_ptr [0] & (\A_SPW_TOP|rx_data|mem[37][2]~q  & 
// ((!\A_SPW_TOP|rx_data|rd_ptr [4])))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .datab(!\A_SPW_TOP|rx_data|mem[37][2]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[52][2]~q ),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [4]),
        .datae(!\A_SPW_TOP|rx_data|mem[53][2]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[36][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux15~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux15~7 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux15~7 .lut_mask = 64'h110A115FBB0ABB5F;
defparam \A_SPW_TOP|rx_data|Mux15~7 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y8_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux15~8 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux15~8_combout  = ( \A_SPW_TOP|rx_data|mem[45][2]~q  & ( \A_SPW_TOP|rx_data|rd_ptr [0] & ( (!\A_SPW_TOP|rx_data|rd_ptr [4]) # (\A_SPW_TOP|rx_data|mem[61][2]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[45][2]~q  & ( \A_SPW_TOP|rx_data|rd_ptr 
// [0] & ( (\A_SPW_TOP|rx_data|rd_ptr [4] & \A_SPW_TOP|rx_data|mem[61][2]~q ) ) ) ) # ( \A_SPW_TOP|rx_data|mem[45][2]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [0] & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & ((\A_SPW_TOP|rx_data|mem[44][2]~q ))) # 
// (\A_SPW_TOP|rx_data|rd_ptr [4] & (\A_SPW_TOP|rx_data|mem[60][2]~q )) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[45][2]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [0] & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & ((\A_SPW_TOP|rx_data|mem[44][2]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr 
// [4] & (\A_SPW_TOP|rx_data|mem[60][2]~q )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[60][2]~q ),
        .datab(!\A_SPW_TOP|rx_data|rd_ptr [4]),
        .datac(!\A_SPW_TOP|rx_data|mem[61][2]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[44][2]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[45][2]~q ),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux15~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux15~8 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux15~8 .lut_mask = 64'h11DD11DD0303CFCF;
defparam \A_SPW_TOP|rx_data|Mux15~8 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y8_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux15~9 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux15~9_combout  = ( \A_SPW_TOP|rx_data|Mux15~7_combout  & ( \A_SPW_TOP|rx_data|Mux15~8_combout  & ( ((!\A_SPW_TOP|rx_data|rd_ptr [3] & ((\A_SPW_TOP|rx_data|Mux15~5_combout ))) # (\A_SPW_TOP|rx_data|rd_ptr [3] & 
// (\A_SPW_TOP|rx_data|Mux15~6_combout ))) # (\A_SPW_TOP|rx_data|rd_ptr [5]) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux15~7_combout  & ( \A_SPW_TOP|rx_data|Mux15~8_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [5] & ((!\A_SPW_TOP|rx_data|rd_ptr [3] & 
// ((\A_SPW_TOP|rx_data|Mux15~5_combout ))) # (\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|Mux15~6_combout )))) # (\A_SPW_TOP|rx_data|rd_ptr [5] & (((\A_SPW_TOP|rx_data|rd_ptr [3])))) ) ) ) # ( \A_SPW_TOP|rx_data|Mux15~7_combout  & ( 
// !\A_SPW_TOP|rx_data|Mux15~8_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [5] & ((!\A_SPW_TOP|rx_data|rd_ptr [3] & ((\A_SPW_TOP|rx_data|Mux15~5_combout ))) # (\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|Mux15~6_combout )))) # (\A_SPW_TOP|rx_data|rd_ptr 
// [5] & (((!\A_SPW_TOP|rx_data|rd_ptr [3])))) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux15~7_combout  & ( !\A_SPW_TOP|rx_data|Mux15~8_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [5] & ((!\A_SPW_TOP|rx_data|rd_ptr [3] & ((\A_SPW_TOP|rx_data|Mux15~5_combout ))) # 
// (\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|Mux15~6_combout )))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .datab(!\A_SPW_TOP|rx_data|Mux15~6_combout ),
        .datac(!\A_SPW_TOP|rx_data|Mux15~5_combout ),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [3]),
        .datae(!\A_SPW_TOP|rx_data|Mux15~7_combout ),
        .dataf(!\A_SPW_TOP|rx_data|Mux15~8_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux15~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux15~9 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux15~9 .lut_mask = 64'h0A225F220A775F77;
defparam \A_SPW_TOP|rx_data|Mux15~9 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y8_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux15~16 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux15~16_combout  = ( \A_SPW_TOP|rx_data|rd_ptr [5] & ( \A_SPW_TOP|rx_data|mem[62][2]~q  & ( (\A_SPW_TOP|rx_data|mem[54][2]~q ) # (\A_SPW_TOP|rx_data|rd_ptr [3]) ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [5] & ( 
// \A_SPW_TOP|rx_data|mem[62][2]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|mem[22][2]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [3] & ((\A_SPW_TOP|rx_data|mem[30][2]~q ))) ) ) ) # ( \A_SPW_TOP|rx_data|rd_ptr [5] & ( 
// !\A_SPW_TOP|rx_data|mem[62][2]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [3] & \A_SPW_TOP|rx_data|mem[54][2]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [5] & ( !\A_SPW_TOP|rx_data|mem[62][2]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|mem[22][2]~q 
// )) # (\A_SPW_TOP|rx_data|rd_ptr [3] & ((\A_SPW_TOP|rx_data|mem[30][2]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [3]),
        .datab(!\A_SPW_TOP|rx_data|mem[22][2]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[54][2]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[30][2]~q ),
        .datae(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .dataf(!\A_SPW_TOP|rx_data|mem[62][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux15~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux15~16 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux15~16 .lut_mask = 64'h22770A0A22775F5F;
defparam \A_SPW_TOP|rx_data|Mux15~16 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X36_Y8_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux15~18 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux15~18_combout  = ( \A_SPW_TOP|rx_data|mem[23][2]~q  & ( \A_SPW_TOP|rx_data|rd_ptr [3] & ( (!\A_SPW_TOP|rx_data|rd_ptr [5] & (\A_SPW_TOP|rx_data|mem[31][2]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [5] & ((\A_SPW_TOP|rx_data|mem[63][2]~q ))) 
// ) ) ) # ( !\A_SPW_TOP|rx_data|mem[23][2]~q  & ( \A_SPW_TOP|rx_data|rd_ptr [3] & ( (!\A_SPW_TOP|rx_data|rd_ptr [5] & (\A_SPW_TOP|rx_data|mem[31][2]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [5] & ((\A_SPW_TOP|rx_data|mem[63][2]~q ))) ) ) ) # ( 
// \A_SPW_TOP|rx_data|mem[23][2]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [3] & ( (!\A_SPW_TOP|rx_data|rd_ptr [5]) # (\A_SPW_TOP|rx_data|mem[55][2]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[23][2]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [3] & ( (\A_SPW_TOP|rx_data|rd_ptr [5] 
// & \A_SPW_TOP|rx_data|mem[55][2]~q ) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[31][2]~q ),
        .datab(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .datac(!\A_SPW_TOP|rx_data|mem[63][2]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[55][2]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[23][2]~q ),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux15~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux15~18 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux15~18 .lut_mask = 64'h0033CCFF47474747;
defparam \A_SPW_TOP|rx_data|Mux15~18 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y8_N15
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux15~15 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux15~15_combout  = ( \A_SPW_TOP|rx_data|rd_ptr [5] & ( \A_SPW_TOP|rx_data|mem[6][2]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|mem[38][2]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [3] & ((\A_SPW_TOP|rx_data|mem[46][2]~q ))) ) 
// ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [5] & ( \A_SPW_TOP|rx_data|mem[6][2]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [3]) # (\A_SPW_TOP|rx_data|mem[14][2]~q ) ) ) ) # ( \A_SPW_TOP|rx_data|rd_ptr [5] & ( !\A_SPW_TOP|rx_data|mem[6][2]~q  & ( 
// (!\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|mem[38][2]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [3] & ((\A_SPW_TOP|rx_data|mem[46][2]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [5] & ( !\A_SPW_TOP|rx_data|mem[6][2]~q  & ( 
// (\A_SPW_TOP|rx_data|mem[14][2]~q  & \A_SPW_TOP|rx_data|rd_ptr [3]) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[38][2]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[46][2]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[14][2]~q ),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [3]),
        .datae(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .dataf(!\A_SPW_TOP|rx_data|mem[6][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux15~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux15~15 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux15~15 .lut_mask = 64'h000F5533FF0F5533;
defparam \A_SPW_TOP|rx_data|Mux15~15 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X36_Y8_N33
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux15~17 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux15~17_combout  = ( \A_SPW_TOP|rx_data|rd_ptr [5] & ( \A_SPW_TOP|rx_data|mem[47][2]~q  & ( (\A_SPW_TOP|rx_data|rd_ptr [3]) # (\A_SPW_TOP|rx_data|mem[39][2]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [5] & ( 
// \A_SPW_TOP|rx_data|mem[47][2]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [3] & ((\A_SPW_TOP|rx_data|mem[7][2]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|mem[15][2]~q )) ) ) ) # ( \A_SPW_TOP|rx_data|rd_ptr [5] & ( !\A_SPW_TOP|rx_data|mem[47][2]~q 
//  & ( (\A_SPW_TOP|rx_data|mem[39][2]~q  & !\A_SPW_TOP|rx_data|rd_ptr [3]) ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [5] & ( !\A_SPW_TOP|rx_data|mem[47][2]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [3] & ((\A_SPW_TOP|rx_data|mem[7][2]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr 
// [3] & (\A_SPW_TOP|rx_data|mem[15][2]~q )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[39][2]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[15][2]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[7][2]~q ),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [3]),
        .datae(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .dataf(!\A_SPW_TOP|rx_data|mem[47][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux15~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux15~17 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux15~17 .lut_mask = 64'h0F3355000F3355FF;
defparam \A_SPW_TOP|rx_data|Mux15~17 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y8_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux15~19 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux15~19_combout  = ( \A_SPW_TOP|rx_data|Mux15~17_combout  & ( \A_SPW_TOP|rx_data|rd_ptr [0] & ( (!\A_SPW_TOP|rx_data|rd_ptr [4]) # (\A_SPW_TOP|rx_data|Mux15~18_combout ) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux15~17_combout  & ( 
// \A_SPW_TOP|rx_data|rd_ptr [0] & ( (\A_SPW_TOP|rx_data|Mux15~18_combout  & \A_SPW_TOP|rx_data|rd_ptr [4]) ) ) ) # ( \A_SPW_TOP|rx_data|Mux15~17_combout  & ( !\A_SPW_TOP|rx_data|rd_ptr [0] & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & 
// ((\A_SPW_TOP|rx_data|Mux15~15_combout ))) # (\A_SPW_TOP|rx_data|rd_ptr [4] & (\A_SPW_TOP|rx_data|Mux15~16_combout )) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux15~17_combout  & ( !\A_SPW_TOP|rx_data|rd_ptr [0] & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & 
// ((\A_SPW_TOP|rx_data|Mux15~15_combout ))) # (\A_SPW_TOP|rx_data|rd_ptr [4] & (\A_SPW_TOP|rx_data|Mux15~16_combout )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux15~16_combout ),
        .datab(!\A_SPW_TOP|rx_data|Mux15~18_combout ),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [4]),
        .datad(!\A_SPW_TOP|rx_data|Mux15~15_combout ),
        .datae(!\A_SPW_TOP|rx_data|Mux15~17_combout ),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux15~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux15~19 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux15~19 .lut_mask = 64'h05F505F50303F3F3;
defparam \A_SPW_TOP|rx_data|Mux15~19 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y8_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux15~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux15~1_combout  = ( \A_SPW_TOP|rx_data|mem[9][2]~q  & ( \A_SPW_TOP|rx_data|mem[1][2]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [4]) # ((!\A_SPW_TOP|rx_data|rd_ptr [3] & ((\A_SPW_TOP|rx_data|mem[17][2]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [3] & 
// (\A_SPW_TOP|rx_data|mem[25][2]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[9][2]~q  & ( \A_SPW_TOP|rx_data|mem[1][2]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & (((!\A_SPW_TOP|rx_data|rd_ptr [3])))) # (\A_SPW_TOP|rx_data|rd_ptr [4] & ((!\A_SPW_TOP|rx_data|rd_ptr 
// [3] & ((\A_SPW_TOP|rx_data|mem[17][2]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|mem[25][2]~q )))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[9][2]~q  & ( !\A_SPW_TOP|rx_data|mem[1][2]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & 
// (((\A_SPW_TOP|rx_data|rd_ptr [3])))) # (\A_SPW_TOP|rx_data|rd_ptr [4] & ((!\A_SPW_TOP|rx_data|rd_ptr [3] & ((\A_SPW_TOP|rx_data|mem[17][2]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|mem[25][2]~q )))) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|mem[9][2]~q  & ( !\A_SPW_TOP|rx_data|mem[1][2]~q  & ( (\A_SPW_TOP|rx_data|rd_ptr [4] & ((!\A_SPW_TOP|rx_data|rd_ptr [3] & ((\A_SPW_TOP|rx_data|mem[17][2]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|mem[25][2]~q )))) ) 
// ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[25][2]~q ),
        .datab(!\A_SPW_TOP|rx_data|rd_ptr [4]),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [3]),
        .datad(!\A_SPW_TOP|rx_data|mem[17][2]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[9][2]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[1][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux15~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux15~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux15~1 .lut_mask = 64'h01310D3DC1F1CDFD;
defparam \A_SPW_TOP|rx_data|Mux15~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y8_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux15~3 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux15~3_combout  = ( \A_SPW_TOP|rx_data|rd_ptr [3] & ( \A_SPW_TOP|rx_data|rd_ptr [4] & ( \A_SPW_TOP|rx_data|mem[57][2]~q  ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [3] & ( \A_SPW_TOP|rx_data|rd_ptr [4] & ( \A_SPW_TOP|rx_data|mem[49][2]~q  ) 
// ) ) # ( \A_SPW_TOP|rx_data|rd_ptr [3] & ( !\A_SPW_TOP|rx_data|rd_ptr [4] & ( \A_SPW_TOP|rx_data|mem[41][2]~q  ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [3] & ( !\A_SPW_TOP|rx_data|rd_ptr [4] & ( \A_SPW_TOP|rx_data|mem[33][2]~q  ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[49][2]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[41][2]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[33][2]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[57][2]~q ),
        .datae(!\A_SPW_TOP|rx_data|rd_ptr [3]),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux15~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux15~3 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux15~3 .lut_mask = 64'h0F0F3333555500FF;
defparam \A_SPW_TOP|rx_data|Mux15~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y8_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux15~2 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux15~2_combout  = ( \A_SPW_TOP|rx_data|mem[48][2]~q  & ( \A_SPW_TOP|rx_data|mem[56][2]~q  & ( ((!\A_SPW_TOP|rx_data|rd_ptr [3] & ((\A_SPW_TOP|rx_data|mem[32][2]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|mem[40][2]~q 
// ))) # (\A_SPW_TOP|rx_data|rd_ptr [4]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[48][2]~q  & ( \A_SPW_TOP|rx_data|mem[56][2]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [3] & (((\A_SPW_TOP|rx_data|mem[32][2]~q  & !\A_SPW_TOP|rx_data|rd_ptr [4])))) # 
// (\A_SPW_TOP|rx_data|rd_ptr [3] & (((\A_SPW_TOP|rx_data|rd_ptr [4])) # (\A_SPW_TOP|rx_data|mem[40][2]~q ))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[48][2]~q  & ( !\A_SPW_TOP|rx_data|mem[56][2]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [3] & (((\A_SPW_TOP|rx_data|rd_ptr 
// [4]) # (\A_SPW_TOP|rx_data|mem[32][2]~q )))) # (\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|mem[40][2]~q  & ((!\A_SPW_TOP|rx_data|rd_ptr [4])))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[48][2]~q  & ( !\A_SPW_TOP|rx_data|mem[56][2]~q  & ( 
// (!\A_SPW_TOP|rx_data|rd_ptr [4] & ((!\A_SPW_TOP|rx_data|rd_ptr [3] & ((\A_SPW_TOP|rx_data|mem[32][2]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|mem[40][2]~q )))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[40][2]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[32][2]~q ),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [3]),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [4]),
        .datae(!\A_SPW_TOP|rx_data|mem[48][2]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[56][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux15~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux15~2 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux15~2 .lut_mask = 64'h350035F0350F35FF;
defparam \A_SPW_TOP|rx_data|Mux15~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y8_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux15~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux15~0_combout  = ( \A_SPW_TOP|rx_data|mem[8][2]~q  & ( \A_SPW_TOP|rx_data|mem[0][2]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [4]) # ((!\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|mem[16][2]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [3] & 
// ((\A_SPW_TOP|rx_data|mem[24][2]~q )))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[8][2]~q  & ( \A_SPW_TOP|rx_data|mem[0][2]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [3] & ((!\A_SPW_TOP|rx_data|rd_ptr [4]) # ((\A_SPW_TOP|rx_data|mem[16][2]~q )))) # 
// (\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|rd_ptr [4] & ((\A_SPW_TOP|rx_data|mem[24][2]~q )))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[8][2]~q  & ( !\A_SPW_TOP|rx_data|mem[0][2]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|rd_ptr [4] & 
// (\A_SPW_TOP|rx_data|mem[16][2]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [3] & ((!\A_SPW_TOP|rx_data|rd_ptr [4]) # ((\A_SPW_TOP|rx_data|mem[24][2]~q )))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[8][2]~q  & ( !\A_SPW_TOP|rx_data|mem[0][2]~q  & ( 
// (\A_SPW_TOP|rx_data|rd_ptr [4] & ((!\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|mem[16][2]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [3] & ((\A_SPW_TOP|rx_data|mem[24][2]~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [3]),
        .datab(!\A_SPW_TOP|rx_data|rd_ptr [4]),
        .datac(!\A_SPW_TOP|rx_data|mem[16][2]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[24][2]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[8][2]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[0][2]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux15~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux15~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux15~0 .lut_mask = 64'h021346578A9BCEDF;
defparam \A_SPW_TOP|rx_data|Mux15~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y8_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux15~4 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux15~4_combout  = ( \A_SPW_TOP|rx_data|rd_ptr [5] & ( \A_SPW_TOP|rx_data|Mux15~0_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & ((\A_SPW_TOP|rx_data|Mux15~2_combout ))) # (\A_SPW_TOP|rx_data|rd_ptr [0] & 
// (\A_SPW_TOP|rx_data|Mux15~3_combout )) ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [5] & ( \A_SPW_TOP|rx_data|Mux15~0_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [0]) # (\A_SPW_TOP|rx_data|Mux15~1_combout ) ) ) ) # ( \A_SPW_TOP|rx_data|rd_ptr [5] & ( 
// !\A_SPW_TOP|rx_data|Mux15~0_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & ((\A_SPW_TOP|rx_data|Mux15~2_combout ))) # (\A_SPW_TOP|rx_data|rd_ptr [0] & (\A_SPW_TOP|rx_data|Mux15~3_combout )) ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [5] & ( 
// !\A_SPW_TOP|rx_data|Mux15~0_combout  & ( (\A_SPW_TOP|rx_data|Mux15~1_combout  & \A_SPW_TOP|rx_data|rd_ptr [0]) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux15~1_combout ),
        .datab(!\A_SPW_TOP|rx_data|Mux15~3_combout ),
        .datac(!\A_SPW_TOP|rx_data|Mux15~2_combout ),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .datae(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .dataf(!\A_SPW_TOP|rx_data|Mux15~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux15~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux15~4 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux15~4 .lut_mask = 64'h00550F33FF550F33;
defparam \A_SPW_TOP|rx_data|Mux15~4 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y8_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux15~20 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux15~20_combout  = ( \A_SPW_TOP|rx_data|Mux15~4_combout  & ( \A_SPW_TOP|rx_data|rd_ptr [2] & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|Mux15~9_combout )) # (\A_SPW_TOP|rx_data|rd_ptr [1] & 
// ((\A_SPW_TOP|rx_data|Mux15~19_combout ))) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux15~4_combout  & ( \A_SPW_TOP|rx_data|rd_ptr [2] & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|Mux15~9_combout )) # (\A_SPW_TOP|rx_data|rd_ptr [1] & 
// ((\A_SPW_TOP|rx_data|Mux15~19_combout ))) ) ) ) # ( \A_SPW_TOP|rx_data|Mux15~4_combout  & ( !\A_SPW_TOP|rx_data|rd_ptr [2] & ( (!\A_SPW_TOP|rx_data|rd_ptr [1]) # (\A_SPW_TOP|rx_data|Mux15~14_combout ) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux15~4_combout  & ( 
// !\A_SPW_TOP|rx_data|rd_ptr [2] & ( (\A_SPW_TOP|rx_data|Mux15~14_combout  & \A_SPW_TOP|rx_data|rd_ptr [1]) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux15~14_combout ),
        .datab(!\A_SPW_TOP|rx_data|Mux15~9_combout ),
        .datac(!\A_SPW_TOP|rx_data|Mux15~19_combout ),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datae(!\A_SPW_TOP|rx_data|Mux15~4_combout ),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux15~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux15~20 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux15~20 .lut_mask = 64'h0055FF55330F330F;
defparam \A_SPW_TOP|rx_data|Mux15~20 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y8_N43
dffeas \A_SPW_TOP|rx_data|data_out[2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|rx_data|Mux15~20_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|data_out [2]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|data_out[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|data_out[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y16_N39
cyclonev_lcell_comb \u0|data_flag_rx|read_mux_out[2] (
// Equation(s):
// \u0|data_flag_rx|read_mux_out [2] = ( \A_SPW_TOP|rx_data|data_out [2] & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datad(gnd),
        .datae(!\A_SPW_TOP|rx_data|data_out [2]),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|data_flag_rx|read_mux_out [2]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|data_flag_rx|read_mux_out[2] .extended_lut = "off";
defparam \u0|data_flag_rx|read_mux_out[2] .lut_mask = 64'h0000A0A00000A0A0;
defparam \u0|data_flag_rx|read_mux_out[2] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y16_N41
dffeas \u0|data_flag_rx|readdata[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|data_flag_rx|read_mux_out [2]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|data_flag_rx|readdata [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|data_flag_rx|readdata[2] .is_wysiwyg = "true";
defparam \u0|data_flag_rx|readdata[2] .power_up = "low";
// synopsys translate_on

// Location: FF_X23_Y16_N38
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|data_flag_rx|readdata [2]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre[2] .power_up = "low";
// synopsys translate_on

// Location: FF_X23_Y17_N2
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y17_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~2_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][2]~q  ) ) # ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [2] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [2]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][2]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~2 .lut_mask = 64'h3333333300FF00FF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y17_N17
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~2_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y17_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~42 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~42_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout  & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout  & 
// \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [2]) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout  & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout  & 
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][2]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [2]),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][2]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~42_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~42 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~42 .lut_mask = 64'h00AA00AA0A0A0A0A;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~42 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y17_N59
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~2_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y17_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|src_payload~2 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|src_payload~2_combout  = ( \u0|hps_0|fpga_interfaces|h2f_WDATA [2] & ( \u0|mm_interconnect_0|cmd_mux|saved_grant [0] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_WDATA [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux|src_payload~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|src_payload~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|src_payload~2 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux|src_payload~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y17_N14
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux|src_payload~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y17_N48
cyclonev_lcell_comb \u0|led_pio_test|data_out[2]~_Duplicate_1feeder (
// Equation(s):
// \u0|led_pio_test|data_out[2]~_Duplicate_1feeder_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [2] )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|led_pio_test|data_out[2]~_Duplicate_1feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|led_pio_test|data_out[2]~_Duplicate_1feeder .extended_lut = "off";
defparam \u0|led_pio_test|data_out[2]~_Duplicate_1feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|led_pio_test|data_out[2]~_Duplicate_1feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y17_N50
dffeas \u0|led_pio_test|data_out[2]~_Duplicate_1 (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|led_pio_test|data_out[2]~_Duplicate_1feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|led_pio_test|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|led_pio_test|data_out[2]~_Duplicate_1_q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|led_pio_test|data_out[2]~_Duplicate_1 .is_wysiwyg = "true";
defparam \u0|led_pio_test|data_out[2]~_Duplicate_1 .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y17_N18
cyclonev_lcell_comb \u0|led_pio_test|readdata[2] (
// Equation(s):
// \u0|led_pio_test|readdata [2] = ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( (\u0|led_pio_test|data_out[2]~_Duplicate_1_q  & 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|led_pio_test|data_out[2]~_Duplicate_1_q ),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|led_pio_test|readdata [2]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|led_pio_test|readdata[2] .extended_lut = "off";
defparam \u0|led_pio_test|readdata[2] .lut_mask = 64'h0F000F0000000000;
defparam \u0|led_pio_test|readdata[2] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y17_N20
dffeas \u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|led_pio_test|readdata [2]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y17_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~2 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~2_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][2]~q  ) ) # ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre [2] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][2]~q ),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~2 .lut_mask = 64'h00FF00FF0F0F0F0F;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y17_N34
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y17_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~40 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~40_combout  = (!\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg [0] & (((\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][2]~q )))) # 
// (\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg [0] & ((!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [0] & ((\u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre [2]))) # 
// (\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [0] & (\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][2]~q ))))

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg [0]),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [0]),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][2]~q ),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre [2]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~40_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~40 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~40 .lut_mask = 64'h0B4F0B4F0B4F0B4F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~40 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y17_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~43 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~43_combout  = ( \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~40_combout  & ( (((\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~41_combout  & !\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout )) # 
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~42_combout )) # (\u0|mm_interconnect_0|rsp_demux|src1_valid~combout ) ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~40_combout  & ( ((\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~41_combout  & 
// !\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~42_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux|src1_valid~combout ),
        .datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~41_combout ),
        .datac(!\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~42_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~40_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~43_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~43 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~43 .lut_mask = 64'h3F0F3F0F7F5F7F5F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~43 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y16_N17
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y16_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~2_combout  = (!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1] & (\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [2])) # 
// (\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1] & ((\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][2]~q )))

        .dataa(!\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [2]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][2]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~2 .lut_mask = 64'h505F505F505F505F;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y16_N25
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~2_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][2]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y16_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~230 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~230_combout  = ( !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout  & ( ((((\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout  & 
// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][2]~q )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~43_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~234_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~49_combout ) 
// ) ) # ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout  & ( ((((\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout  & \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [2])) # 
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~43_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~234_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~49_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ),
        .datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~49_combout ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [2]),
        .datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~234_combout ),
        .datae(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout ),
        .dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~43_combout ),
        .datag(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][2]~q ),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~230_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~230 .extended_lut = "on";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~230 .lut_mask = 64'h37FF37FFFFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~230 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y28_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [16] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  
// ) ) # ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [16] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ( \u0|hps_0|fpga_interfaces|h2f_AWADDR [16] ) ) ) # ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [16] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ( \u0|hps_0|fpga_interfaces|h2f_AWADDR [16] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [16]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [16]),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1 .lut_mask = 64'h0F0F0F0F0000FFFF;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y25_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|router|Equal15~0 (
// Equation(s):
// \u0|mm_interconnect_0|router|Equal15~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout  & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout  & 
// (\u0|mm_interconnect_0|router|Equal14~0_combout  & \u0|mm_interconnect_0|router|Equal7~1_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|router|Equal14~0_combout ),
        .datad(!\u0|mm_interconnect_0|router|Equal7~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router|Equal15~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router|Equal15~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router|Equal15~0 .lut_mask = 64'h00000000000A000A;
defparam \u0|mm_interconnect_0|router|Equal15~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y25_N59
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[9] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|router|Equal15~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [9]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[9] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[9] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y25_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|src9_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|src9_valid~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout  & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q ) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [9]) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [9]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux|src9_valid~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|src9_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|src9_valid~0 .lut_mask = 64'h00000000FF0FFF0F;
defparam \u0|mm_interconnect_0|cmd_demux|src9_valid~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y25_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|arb|grant[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|arb|grant[0]~1_combout  = ( \u0|mm_interconnect_0|router|Equal15~0_combout  & ( \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg [1] & ( (\u0|mm_interconnect_0|cmd_demux|src9_valid~0_combout  & 
// ((!\u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg [0]) # (!\u0|mm_interconnect_0|cmd_demux_001|src9_valid~1_combout ))) ) ) ) # ( \u0|mm_interconnect_0|router|Equal15~0_combout  & ( !\u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg [1] & ( 
// (\u0|mm_interconnect_0|cmd_demux|src9_valid~0_combout  & !\u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg [0]) ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_demux|src9_valid~0_combout ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg [0]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|cmd_demux_001|src9_valid~1_combout ),
        .datae(!\u0|mm_interconnect_0|router|Equal15~0_combout ),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_009|arb|grant[0]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|arb|grant[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|arb|grant[0]~1 .lut_mask = 64'h0000444400005544;
defparam \u0|mm_interconnect_0|cmd_mux_009|arb|grant[0]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y25_N23
dffeas \u0|mm_interconnect_0|cmd_mux_009|saved_grant[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_009|arb|grant[0]~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|cmd_mux_009|update_grant~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|saved_grant[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_009|saved_grant[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y24_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|src_payload~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|src_payload~0_combout  = ( \u0|hps_0|fpga_interfaces|h2f_WDATA [0] & ( \u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_WDATA [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_009|src_payload~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|src_payload~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|src_payload~0 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_009|src_payload~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y24_N14
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_009|src_payload~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y21_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|src_data[81] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|src_data [81] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout  & ( (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~0_combout ) ) ) 
// # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout  & ( ((\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~0_combout )) # (\u0|mm_interconnect_0|cmd_mux_009|saved_grant 
// [1]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_009|src_data [81]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[81] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[81] .lut_mask = 64'h7373737350505050;
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[81] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y21_N2
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_009|src_data [81]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y21_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|src_data[86] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|src_data [86] = ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [0] & ( ((\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [0])) # (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0] & ( (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_009|src_data [86]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[86] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[86] .lut_mask = 64'h0303030303FF03FF;
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[86] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y21_N29
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_009|src_data [86]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X15_Y22_N2
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_009|src_data [88]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .power_up = "low";
// synopsys translate_on

// Location: FF_X15_Y22_N47
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_009|src_data [87]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y22_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_009|src_data [88] & ( 
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1])) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_009|src_data [88] & ( 
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & 
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]))) # (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((\u0|mm_interconnect_0|cmd_mux_009|src_data [87])))) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_009|src_data [87]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_009|src_data [88]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .lut_mask = 64'h083B083B08080808;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y21_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout  = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  & ( 
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( !\u0|mm_interconnect_0|cmd_mux_009|src_data [86] ) ) ) # ( 
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  & ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] ) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|cmd_mux_009|src_data [86]),
        .datae(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .lut_mask = 64'h0000AAAA0000FF00;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y21_N4
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .power_up = "low";
// synopsys translate_on

// Location: FF_X14_Y21_N19
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y22_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  = ( \u0|mm_interconnect_0|cmd_mux_009|src_data [87] & ( 
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2])) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_009|src_data [87] & ( 
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2])))) # (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (!\u0|mm_interconnect_0|cmd_mux_009|src_data [88])) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_009|src_data [88]),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_009|src_data [87]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .lut_mask = 64'hCA0ACA0AC000C000;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y21_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout  = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  & ( 
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) # 
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((\u0|mm_interconnect_0|cmd_mux_009|src_data [86]))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_009|src_data [86]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .lut_mask = 64'h000000000C3F0C3F;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y21_N37
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y21_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|src_data[79] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|src_data [79] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout  & ( (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~2_combout ) ) ) 
// # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout  & ( ((\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~2_combout )) # (\u0|mm_interconnect_0|cmd_mux_009|saved_grant 
// [0]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~2_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_009|src_data [79]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[79] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[79] .lut_mask = 64'h7575757530303030;
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[79] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y21_N26
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_009|src_data [79]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y21_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  = ( 
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  & ( (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) # (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ((!\u0|mm_interconnect_0|cmd_mux_009|src_data [86]))) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|cmd_mux_009|src_data [86]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .lut_mask = 64'h00000000BB88BB88;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y21_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0] = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout  & ( 
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0])) # 
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|cmd_mux_009|src_data [79]))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_009|src_data [79]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .lut_mask = 64'h00000000F3C0F3C0;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y21_N56
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X14_Y21_N58
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y21_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout  = SUM(( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) + ( 
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14  = CARRY(( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) + ( 
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
        .cout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .lut_mask = 64'h0000F0F000003333;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y21_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [0] & ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout  & ( (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]) # (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]) ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [0] 
// & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout  & ( \u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [0] & ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout  & ( \u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [0]),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .lut_mask = 64'h0000333300FF33FF;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y21_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout  = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout  & ( 
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  & ( (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0])) # (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]))) # 
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout )))) ) ) ) # ( 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout  & ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  & ( 
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]))) # 
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout )) ) ) ) # ( 
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout  & ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  & ( 
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]) # 
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]))) ) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout  & ( 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  & ( (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0] 
// & !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 .lut_mask = 64'h0F005F000F335F33;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y21_N43
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y21_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout  = SUM(( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + ( 
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14  ))
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10  = CARRY(( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + ( 
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
        .cout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y21_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|src_data[80] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|src_data [80] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~1_combout  & ( ((\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~0_combout )) # 
// (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~1_combout  & ( (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~0_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_009|src_data [80]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[80] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[80] .lut_mask = 64'h5050505073737373;
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[80] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y21_N5
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_009|src_data [80]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y21_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1] = ( \u0|mm_interconnect_0|cmd_mux_009|src_data [80] & ( 
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout  & 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1])) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_009|src_data [80] & ( 
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout  & ((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]) 
// # (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_009|src_data [80]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .lut_mask = 64'h0F030F030C000C00;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y21_N41
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y21_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout  & ( 
// ((\u0|hps_0|fpga_interfaces|h2f_ARADDR [1] & \u0|mm_interconnect_0|cmd_mux_009|saved_grant [1])) # (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout  & 
// ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [1] & \u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]) ) )

        .dataa(gnd),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [1]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .lut_mask = 64'h0303030303FF03FF;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y21_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout  = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1] & 
// ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout  & ( (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]) # (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout )))) # 
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout )) ) ) ) # ( 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1] & ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout  & 
// ( (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]))) # 
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout )) ) ) ) # ( 
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1] & ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout  & 
// ( (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]) # 
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ))) ) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1] & ( 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout  & ( (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]) ) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
        .datae(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .lut_mask = 64'h00AA0AAA11BB1BBB;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y21_N13
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y21_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout  = SUM(( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + ( 
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10  ))
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6  = CARRY(( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + ( 
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10  ))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
        .cout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .lut_mask = 64'h0000CCCC000000FF;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y21_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2] = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout  & ( 
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2])) # 
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|cmd_mux_009|src_data [81]))) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_009|src_data [81]),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .lut_mask = 64'h00000000AAF0AAF0;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y21_N23
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y21_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout  = ( \u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout  & ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [2]) # (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] 
// & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout  & ( \u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout  & ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [2] ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [2]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 .lut_mask = 64'h00000F0F55555F5F;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y21_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout  = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout  & ( 
// (((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] & \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout )) # 
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) # (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]) ) ) # ( 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout  & ( (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] & \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout )) # 
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]))) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 .lut_mask = 64'h1F001F001FFF1FFF;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y21_N47
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y21_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|src_data[82] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|src_data [82] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout  & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout  & ( \u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] ) ) 
// ) # ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout  & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout  & ( (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]) # 
// (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout  & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout  & ( 
// \u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
        .datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_009|src_data [82]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[82] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[82] .lut_mask = 64'h00FF33FF00003333;
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[82] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y21_N32
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_009|src_data [82]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y21_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3] = ( \u0|mm_interconnect_0|cmd_mux_009|src_data [82] & ( 
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3] & 
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_009|src_data [82] & ( 
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout  & ((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]) # 
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_009|src_data [82]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .lut_mask = 64'h00F500F500A000A0;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y21_N53
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .power_up = "low";
// synopsys translate_on

// Location: FF_X14_Y21_N50
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y21_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout  = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// (\u0|mm_interconnect_0|cmd_mux_009|src_data [86] & \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] & 
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_009|src_data [86]),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .lut_mask = 64'h00550055000F000F;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y21_N55
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y21_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout  = SUM(( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3] ) + ( 
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3] ) + ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6  ))

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .lut_mask = 64'h0000FF0000005555;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y21_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout  & ( (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [3]) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] 
// & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout  & ( \u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout  & ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [3] ) ) )

        .dataa(gnd),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [3]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .lut_mask = 64'h000033330F0F3F3F;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y21_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout  = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout  & ( 
// (((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3] & \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout )) # 
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3])) # (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) # ( 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout  & ( (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3] & \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout )) # 
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]))) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .lut_mask = 64'h0A2A0A2A5F7F5F7F;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y21_N35
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y22_N0
cyclonev_lcell_comb \u0|link_disable|always0~0 (
// Equation(s):
// \u0|link_disable|always0~0_combout  = ( \u0|mm_interconnect_0|link_disable_s1_agent|m0_write~combout  & ( (!\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [0] & 
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & (!\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [1] & 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]))) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [0]),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [1]),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_agent|m0_write~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|link_disable|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|link_disable|always0~0 .extended_lut = "off";
defparam \u0|link_disable|always0~0 .lut_mask = 64'h0000000080008000;
defparam \u0|link_disable|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y22_N47
dffeas \u0|link_disable|data_out (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [0]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|link_disable|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|link_disable|data_out~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|link_disable|data_out .is_wysiwyg = "true";
defparam \u0|link_disable|data_out .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y27_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|src_payload~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|src_payload~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_WDATA [0] ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_WDATA [0]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_007|src_payload~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|src_payload~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|src_payload~0 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_007|src_payload~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y27_N23
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_007|src_payload~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y28_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|src_data[82] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|src_data [82] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout  & ( (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ) ) ) 
// # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout  & ( ((\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout )) # (\u0|mm_interconnect_0|cmd_mux_007|saved_grant 
// [0]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_007|src_data [82]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[82] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[82] .lut_mask = 64'h5577557700330033;
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[82] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y28_N59
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_007|src_data [82]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y28_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3] = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout  & ( 
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3])) # 
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|cmd_mux_007|src_data [82]))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_007|src_data [82]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .lut_mask = 64'h00000000CFC0CFC0;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y28_N29
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .power_up = "low";
// synopsys translate_on

// Location: FF_X23_Y28_N28
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y28_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|src_data[86] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|src_data [86] = ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [0] & ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] & ( (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]) # (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]) ) ) ) # 
// ( !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0] & ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] & ( \u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [0] & ( !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] & ( 
// \u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
        .datad(gnd),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0]),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_007|src_data [86]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[86] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[86] .lut_mask = 64'h000033330F0F3F3F;
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[86] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y28_N20
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_007|src_data [86]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X23_Y27_N2
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_007|src_data [88]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .power_up = "low";
// synopsys translate_on

// Location: FF_X23_Y27_N11
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_007|src_data [87]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y27_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & ( 
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2])) # 
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((!\u0|mm_interconnect_0|cmd_mux_007|src_data [88] & \u0|mm_interconnect_0|cmd_mux_007|src_data [87])))) ) ) # ( 
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & ( (!\u0|mm_interconnect_0|cmd_mux_007|src_data [88] & 
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & \u0|mm_interconnect_0|cmd_mux_007|src_data [87])) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_007|src_data [88]),
        .datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_007|src_data [87]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .lut_mask = 64'h000C000CA0ACA0AC;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y28_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout  = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  & ( 
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) # 
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((\u0|mm_interconnect_0|cmd_mux_007|src_data [86]))) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_007|src_data [86]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .lut_mask = 64'h0000000055335533;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y28_N5
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y28_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout  = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  & ( 
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) # 
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|cmd_mux_007|src_data [86]))) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_007|src_data [86]),
        .datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .lut_mask = 64'h00000000ACACACAC;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y28_N2
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y28_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|src_data[81] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|src_data [81] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout  & ( (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~0_combout ) ) ) 
// # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout  & ( ((\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~0_combout )) # (\u0|mm_interconnect_0|cmd_mux_007|saved_grant 
// [1]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_007|src_data [81]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[81] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[81] .lut_mask = 64'h7373737350505050;
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[81] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y28_N14
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_007|src_data [81]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y28_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2] = ( \u0|mm_interconnect_0|cmd_mux_007|src_data [81] & ( 
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] & 
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_007|src_data [81] & ( 
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout  & ((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]) # 
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_007|src_data [81]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .lut_mask = 64'h00F500F500A000A0;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y28_N58
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y27_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  = ( \u0|mm_interconnect_0|cmd_mux_007|src_data [87] & ( 
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & 
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_007|src_data [87] & ( 
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & 
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]))) # (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((!\u0|mm_interconnect_0|cmd_mux_007|src_data [88])))) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_007|src_data [88]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_007|src_data [87]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .lut_mask = 64'h8F808F8080808080;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y28_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout  = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  & ( 
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) # 
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((\u0|mm_interconnect_0|cmd_mux_007|src_data [86]))) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_007|src_data [86]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .lut_mask = 64'h0000000055335533;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y28_N11
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y28_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|src_data[79] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|src_data [79] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~2_combout  & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout  & \u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]) ) ) 
// # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~2_combout  & ( ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout  & \u0|mm_interconnect_0|cmd_mux_007|saved_grant [0])) # (\u0|mm_interconnect_0|cmd_mux_007|saved_grant 
// [1]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_007|src_data [79]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[79] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[79] .lut_mask = 64'h33F333F300F000F0;
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[79] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y28_N23
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_007|src_data [79]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y28_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  = ( 
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  & ( (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) # (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ((!\u0|mm_interconnect_0|cmd_mux_007|src_data [86]))) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_007|src_data [86]),
        .datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .lut_mask = 64'h00000000ACACACAC;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y28_N7
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y28_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout  = SUM(( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) + ( 
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14  = CARRY(( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) + ( 
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
        .datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
        .cout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .lut_mask = 64'h0000F0F000003333;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y28_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0] = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout  & ( 
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0])) # 
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|cmd_mux_007|src_data [79]))) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_007|src_data [79]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .lut_mask = 64'h00000000F5A0F5A0;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y28_N49
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y28_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout  & ( 
// \u0|hps_0|fpga_interfaces|h2f_ARADDR [0] & ( (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]) # (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout  
// & ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [0] & ( \u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] ) ) ) # ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout  & ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [0] & ( 
// \u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout ),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .lut_mask = 64'h00000F0F55555F5F;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y28_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout  = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0] & ( 
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  & ( (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # 
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ) ) ) ) # ( 
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0] & ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  & ( 
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0] & 
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ))) # (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout )))) ) ) ) # ( 
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0] & ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  & ( 
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0] & ( 
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  & ( (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0] & 
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout  & !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
        .datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .datae(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 .lut_mask = 64'h1010F0F0101FF0FF;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y28_N25
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y28_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout  = SUM(( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + ( 
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14  ))
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10  = CARRY(( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + ( 
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
        .datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
        .cout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y28_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|src_data[80] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|src_data [80] = ( \u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & ( ((\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~0_combout )) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~1_combout ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & ( (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~0_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~1_combout ),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_007|src_data [80]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[80] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[80] .lut_mask = 64'h550055005F0F5F0F;
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[80] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y28_N17
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_007|src_data [80]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y28_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1] = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout  & ( 
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1])) # 
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|cmd_mux_007|src_data [80]))) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_007|src_data [80]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .lut_mask = 64'h00000000F5A0F5A0;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y28_N53
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y28_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout  & ( 
// ((\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [1])) # (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout  & 
// ( (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [1]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .lut_mask = 64'h0303030357575757;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y28_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout  = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  & ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout  ) ) ) 
// # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  & ( 
// ((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout  & \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1])) # 
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]) ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  & ( ((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout  & 
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1])) # (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]) ) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
        .datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
        .datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
        .datae(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .lut_mask = 64'h1F1F00001F1F00FF;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y28_N43
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y28_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout  = SUM(( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + ( 
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10  ))
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6  = CARRY(( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + ( 
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
        .datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
        .cout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y28_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [2] & ( \u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & ( 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout ) # (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]) ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [2] & ( \u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] 
// & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout  ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [2] & ( !\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & ( \u0|mm_interconnect_0|cmd_mux_007|saved_grant 
// [1] ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout ),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [2]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 .lut_mask = 64'h0000555500FF55FF;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y28_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout  = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout  & ( 
// (((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] & \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout )) # 
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2])) # (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) # ( 
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout  & ( (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] & \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout )) # 
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]))) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
        .datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 .lut_mask = 64'h0A2A0A2A5F7F5F7F;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y28_N55
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y28_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout  = SUM(( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3] ) + ( 
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3] ) + ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
        .datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y28_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout  = (!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & 
// ((\u0|hps_0|fpga_interfaces|h2f_ARADDR [3])))) # (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & (((\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [3])) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout )))

        .dataa(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout ),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [3]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .lut_mask = 64'h0537053705370537;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y28_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout  = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout  ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// ((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3] & \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout )) # 
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
        .datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
        .datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .lut_mask = 64'h5757575700FF00FF;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y29_N28
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .power_up = "low";
// synopsys translate_on

// Location: FF_X23_Y29_N53
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y29_N27
cyclonev_lcell_comb \u0|link_start|always0~0 (
// Equation(s):
// \u0|link_start|always0~0_combout  = ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & ( (!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [1] & 
// (!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0] & (\u0|mm_interconnect_0|link_start_s1_agent|m0_write~combout  & !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg 
// [3]))) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [1]),
        .datab(!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0]),
        .datac(!\u0|mm_interconnect_0|link_start_s1_agent|m0_write~combout ),
        .datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|link_start|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|link_start|always0~0 .extended_lut = "off";
defparam \u0|link_start|always0~0 .lut_mask = 64'h0800080000000000;
defparam \u0|link_start|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y27_N38
dffeas \u0|link_start|data_out (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [0]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|link_start|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|link_start|data_out~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|link_start|data_out .is_wysiwyg = "true";
defparam \u0|link_start|data_out .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y25_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_payload~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|src_payload~0_combout  = (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_WDATA [0])

        .dataa(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_WDATA [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_008|src_payload~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|src_payload~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|src_payload~0 .lut_mask = 64'h0505050505050505;
defparam \u0|mm_interconnect_0|cmd_mux_008|src_payload~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y25_N52
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_008|src_payload~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y25_N54
cyclonev_lcell_comb \u0|auto_start|data_out~feeder (
// Equation(s):
// \u0|auto_start|data_out~feeder_combout  = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [0] )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|auto_start|data_out~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|auto_start|data_out~feeder .extended_lut = "off";
defparam \u0|auto_start|data_out~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|auto_start|data_out~feeder .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y24_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout  & ( 
// ((\u0|hps_0|fpga_interfaces|h2f_ARADDR [2] & \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1])) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout  & 
// ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [2] & \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [2]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 .lut_mask = 64'h0505050505FF05FF;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y24_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_data[81] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|src_data [81] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout  & ( (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~0_combout ) ) ) 
// # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout  & ( ((\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~0_combout )) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant 
// [1]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_008|src_data [81]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[81] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[81] .lut_mask = 64'h3F333F330F000F00;
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[81] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y24_N32
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_008|src_data [81]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .power_up = "low";
// synopsys translate_on

// Location: FF_X13_Y24_N10
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y24_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_data[86] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|src_data [86] = ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [0] & ( ((\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [0])) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0] & ( (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
        .datac(gnd),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_008|src_data [86]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[86] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[86] .lut_mask = 64'h0055005533773377;
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[86] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y24_N14
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_008|src_data [86]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X14_Y24_N50
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_008|src_data [88]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .power_up = "low";
// synopsys translate_on

// Location: FF_X14_Y24_N38
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_008|src_data [87]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y24_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_008|src_data [88] & ( 
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & 
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1])) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_008|src_data [88] & ( 
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & 
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1])))) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|cmd_mux_008|src_data [87])) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_008|src_data [87]),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_008|src_data [88]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .lut_mask = 64'h11B111B100A000A0;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y24_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout  = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  & ( 
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) # 
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|cmd_mux_008|src_data [86]))) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_008|src_data [86]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .lut_mask = 64'h00000000F5A0F5A0;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y24_N5
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y24_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & ( 
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|cmd_mux_008|src_data [87] & !\u0|mm_interconnect_0|cmd_mux_008|src_data [88])) ) ) # ( 
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1])))) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (!\u0|mm_interconnect_0|cmd_mux_008|src_data [87] & ((!\u0|mm_interconnect_0|cmd_mux_008|src_data [88])))) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_008|src_data [87]),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_008|src_data [88]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .lut_mask = 64'hE4A0E4A044004400;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y24_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout  = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  & ( 
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) # 
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((\u0|mm_interconnect_0|cmd_mux_008|src_data [86]))) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_008|src_data [86]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .lut_mask = 64'h0000000027272727;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y24_N26
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y24_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_data[80] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|src_data [80] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~0_combout  & ( (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~1_combout ) ) ) 
// # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~0_combout  & ( ((\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~1_combout )) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant 
// [0]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_008|src_data [80]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[80] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[80] .lut_mask = 64'h3377337700550055;
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[80] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y24_N17
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_008|src_data [80]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y24_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  = ( 
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ((!\u0|mm_interconnect_0|cmd_mux_008|src_data [86]))) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|cmd_mux_008|src_data [86]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .lut_mask = 64'h00000000DD88DD88;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y24_N29
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y24_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout  = SUM(( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( 
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) + ( !VCC ))
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14  = CARRY(( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( 
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) + ( !VCC ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
        .cout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y24_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_data[79] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|src_data [79] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout  & ( (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~2_combout ) ) ) 
// # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout  & ( ((\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~2_combout )) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant 
// [0]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~2_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_008|src_data [79]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[79] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[79] .lut_mask = 64'h7373737350505050;
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[79] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y24_N44
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_008|src_data [79]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y24_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0] = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout  & ( 
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0])) # 
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|cmd_mux_008|src_data [79]))) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|cmd_mux_008|src_data [79]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .lut_mask = 64'h00000000DD88DD88;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y24_N56
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y24_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout  & ( 
// ((\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [0])) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout  & 
// ( (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [0]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .lut_mask = 64'h0505050537373737;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y24_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout  = ( 
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  ) ) ) # ( 
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  & ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout  & \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0])) # 
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]) ) ) ) # ( 
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  & ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout  & \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0])) # 
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]) ) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .datae(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 .lut_mask = 64'h0F3F0F3F00005555;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y24_N7
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y24_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout  = SUM(( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + ( 
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14  ))
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10  = CARRY(( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + ( 
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14  ))

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
        .cout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .lut_mask = 64'h0000AAAA00000F0F;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y24_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1] = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout  & ( 
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1])) # 
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|cmd_mux_008|src_data [80]))) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_008|src_data [80]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .lut_mask = 64'h00000000F5A0F5A0;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y24_N59
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y24_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout  & ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [1]) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] 
// & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout  & ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout  & ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [1] ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [1]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .lut_mask = 64'h00000F0F33333F3F;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y24_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout  = ( 
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout  & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  & ( 
// (((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1] & \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout )) # 
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1])) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) ) # ( 
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout  & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  & ( 
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1] & 
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout )) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]))) ) ) ) # ( 
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout  & ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  & ( 
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1] & 
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout )) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]))) ) ) ) # ( 
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout  & ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  & ( 
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1] & 
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout )) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]))) ) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
        .datae(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .lut_mask = 64'h02AA02AA02AA57FF;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y24_N19
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y24_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout  = SUM(( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + ( 
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10  ))
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6  = CARRY(( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + ( 
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10  ))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
        .cout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .lut_mask = 64'h0000F0F000003333;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y24_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2] = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// (!\u0|mm_interconnect_0|cmd_mux_008|src_data [81] & \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] & 
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_008|src_data [81]),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .lut_mask = 64'h00CC00CC00F000F0;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y24_N25
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y24_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout  = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( 
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] & \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout )))) # 
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 .lut_mask = 64'h05350535F5F5F5F5;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y24_N59
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y25_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_data[82] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|src_data [82] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout  & ( (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ) ) ) 
// # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout  & ( ((\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout )) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant 
// [0]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_008|src_data [82]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[82] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[82] .lut_mask = 64'h5577557700330033;
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[82] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y25_N20
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_008|src_data [82]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y25_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout  & ( 
// ((\u0|hps_0|fpga_interfaces|h2f_ARADDR [3] & \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1])) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout  & 
// ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [3] & \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [3]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y24_N16
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y24_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout  = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  & ( 
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) # 
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((\u0|mm_interconnect_0|cmd_mux_008|src_data [86]))) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_008|src_data [86]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .lut_mask = 64'h0000000027272727;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y24_N2
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y24_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout  = SUM(( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3] ) + ( 
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3] ) + ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X10_Y25_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3] = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout  & ( 
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3])) # 
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|cmd_mux_008|src_data [82]))) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|cmd_mux_008|src_data [82]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .lut_mask = 64'h00000000BB88BB88;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y25_N31
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y25_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout  = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3] & ( 
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3] & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3] & ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout )))) # 
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .lut_mask = 64'h03470347CFCFCFCF;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y25_N44
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y25_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|m0_write (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent|m0_write~combout  = ( !\u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout  & ( (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|auto_start_s1_agent|local_write~0_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_agent|local_write~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_agent|m0_write~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|m0_write .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|m0_write .lut_mask = 64'h0A0A0A0A00000000;
defparam \u0|mm_interconnect_0|auto_start_s1_agent|m0_write .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X10_Y25_N42
cyclonev_lcell_comb \u0|auto_start|always0~0 (
// Equation(s):
// \u0|auto_start|always0~0_combout  = ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( \u0|mm_interconnect_0|auto_start_s1_agent|m0_write~combout  & ( 
// (!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [1] & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & 
// !\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0])) ) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0]),
        .datae(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|m0_write~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|auto_start|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|auto_start|always0~0 .extended_lut = "off";
defparam \u0|auto_start|always0~0 .lut_mask = 64'h00000000A0000000;
defparam \u0|auto_start|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y25_N56
dffeas \u0|auto_start|data_out (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|auto_start|data_out~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|auto_start|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|auto_start|data_out~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|auto_start|data_out .is_wysiwyg = "true";
defparam \u0|auto_start|data_out .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y4_N45
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|state_fsm~26 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|state_fsm~26_combout  = ( \A_SPW_TOP|SPW|FSM|Selector4~0_combout  & ( \din_a~input_o  & ( (!\u0|link_disable|data_out~q  & ((\u0|auto_start|data_out~q ) # (\u0|link_start|data_out~q ))) ) ) ) # ( !\A_SPW_TOP|SPW|FSM|Selector4~0_combout  
// & ( \din_a~input_o  & ( (!\u0|link_disable|data_out~q  & ((\u0|auto_start|data_out~q ) # (\u0|link_start|data_out~q ))) ) ) ) # ( \A_SPW_TOP|SPW|FSM|Selector4~0_combout  & ( !\din_a~input_o  & ( (!\sin_a~input_o ) # ((!\u0|link_disable|data_out~q  & 
// ((\u0|auto_start|data_out~q ) # (\u0|link_start|data_out~q )))) ) ) ) # ( !\A_SPW_TOP|SPW|FSM|Selector4~0_combout  & ( !\din_a~input_o  & ( (!\u0|link_disable|data_out~q  & ((\u0|auto_start|data_out~q ) # (\u0|link_start|data_out~q ))) ) ) )

        .dataa(!\u0|link_disable|data_out~q ),
        .datab(!\sin_a~input_o ),
        .datac(!\u0|link_start|data_out~q ),
        .datad(!\u0|auto_start|data_out~q ),
        .datae(!\A_SPW_TOP|SPW|FSM|Selector4~0_combout ),
        .dataf(!\din_a~input_o ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|state_fsm~26_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|state_fsm~26 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|state_fsm~26 .lut_mask = 64'h0AAACEEE0AAA0AAA;
defparam \A_SPW_TOP|SPW|FSM|state_fsm~26 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y4_N6
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|state_fsm~20 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|state_fsm~20_combout  = ( !\u0|link_disable|data_out~q  & ( ((\u0|auto_start|data_out~q  & \A_SPW_TOP|SPW|RX|rx_got_null~q )) # (\u0|link_start|data_out~q ) ) )

        .dataa(!\u0|auto_start|data_out~q ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|RX|rx_got_null~q ),
        .datad(!\u0|link_start|data_out~q ),
        .datae(gnd),
        .dataf(!\u0|link_disable|data_out~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|state_fsm~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|state_fsm~20 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|state_fsm~20 .lut_mask = 64'h05FF05FF00000000;
defparam \A_SPW_TOP|SPW|FSM|state_fsm~20 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y4_N36
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|state_fsm~16 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|state_fsm~16_combout  = ( \A_SPW_TOP|SPW|FSM|Equal0~3_combout  & ( \A_SPW_TOP|SPW|FSM|state_fsm.error_wait~q  & ( \A_SPW_TOP|SPW|FSM|state_fsm.error_reset~0_combout  ) ) ) # ( !\A_SPW_TOP|SPW|FSM|Equal0~3_combout  & ( 
// \A_SPW_TOP|SPW|FSM|state_fsm.error_wait~q  & ( (\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~0_combout  & (\A_SPW_TOP|SPW|FSM|state_fsm.ready~q  & (!\A_SPW_TOP|SPW|FSM|state_fsm~20_combout  & \A_SPW_TOP|SPW|FSM|always0~0_combout ))) ) ) ) # ( 
// \A_SPW_TOP|SPW|FSM|Equal0~3_combout  & ( !\A_SPW_TOP|SPW|FSM|state_fsm.error_wait~q  & ( (\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~0_combout  & (\A_SPW_TOP|SPW|FSM|state_fsm.ready~q  & (!\A_SPW_TOP|SPW|FSM|state_fsm~20_combout  & 
// \A_SPW_TOP|SPW|FSM|always0~0_combout ))) ) ) ) # ( !\A_SPW_TOP|SPW|FSM|Equal0~3_combout  & ( !\A_SPW_TOP|SPW|FSM|state_fsm.error_wait~q  & ( (\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~0_combout  & (\A_SPW_TOP|SPW|FSM|state_fsm.ready~q  & 
// (!\A_SPW_TOP|SPW|FSM|state_fsm~20_combout  & \A_SPW_TOP|SPW|FSM|always0~0_combout ))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~0_combout ),
        .datab(!\A_SPW_TOP|SPW|FSM|state_fsm.ready~q ),
        .datac(!\A_SPW_TOP|SPW|FSM|state_fsm~20_combout ),
        .datad(!\A_SPW_TOP|SPW|FSM|always0~0_combout ),
        .datae(!\A_SPW_TOP|SPW|FSM|Equal0~3_combout ),
        .dataf(!\A_SPW_TOP|SPW|FSM|state_fsm.error_wait~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|state_fsm~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|state_fsm~16 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|state_fsm~16 .lut_mask = 64'h0010001000105555;
defparam \A_SPW_TOP|SPW|FSM|state_fsm~16 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y4_N47
dffeas \A_SPW_TOP|SPW|FSM|state_fsm.ready (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|FSM|state_fsm~16_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|FSM|state_fsm.ready~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|state_fsm.ready .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|state_fsm.ready .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y4_N6
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|state_fsm~27 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|state_fsm~27_combout  = ( \A_SPW_TOP|SPW|FSM|state_fsm.ready~q  & ( \din_a~input_o  & ( ((\A_SPW_TOP|SPW|FSM|Selector4~0_combout  & !\A_SPW_TOP|SPW|RX|rx_got_null~q )) # (\A_SPW_TOP|SPW|FSM|state_fsm~26_combout ) ) ) ) # ( 
// !\A_SPW_TOP|SPW|FSM|state_fsm.ready~q  & ( \din_a~input_o  & ( (\A_SPW_TOP|SPW|FSM|Selector4~0_combout  & !\A_SPW_TOP|SPW|RX|rx_got_null~q ) ) ) ) # ( \A_SPW_TOP|SPW|FSM|state_fsm.ready~q  & ( !\din_a~input_o  & ( ((\A_SPW_TOP|SPW|FSM|Selector4~0_combout  
// & !\A_SPW_TOP|SPW|RX|rx_got_null~q )) # (\A_SPW_TOP|SPW|FSM|state_fsm~26_combout ) ) ) ) # ( !\A_SPW_TOP|SPW|FSM|state_fsm.ready~q  & ( !\din_a~input_o  & ( (\A_SPW_TOP|SPW|FSM|Selector4~0_combout  & ((!\A_SPW_TOP|SPW|RX|rx_got_null~q ) # (!\sin_a~input_o 
// ))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|Selector4~0_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_got_null~q ),
        .datac(!\A_SPW_TOP|SPW|FSM|state_fsm~26_combout ),
        .datad(!\sin_a~input_o ),
        .datae(!\A_SPW_TOP|SPW|FSM|state_fsm.ready~q ),
        .dataf(!\din_a~input_o ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|state_fsm~27_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|state_fsm~27 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|state_fsm~27 .lut_mask = 64'h55444F4F44444F4F;
defparam \A_SPW_TOP|SPW|FSM|state_fsm~27 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y4_N33
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|state_fsm~28 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|state_fsm~28_combout  = ( !\A_SPW_TOP|SPW|RX|rx_error_c~q  & ( (!\A_SPW_TOP|SPW|RX|rx_error_d~q  & (((\A_SPW_TOP|SPW|FSM|Selector4~0_combout ) # (\u0|link_start|data_out~q )) # (\A_SPW_TOP|SPW|RX|rx_got_null~q ))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_got_null~q ),
        .datab(!\u0|link_start|data_out~q ),
        .datac(!\A_SPW_TOP|SPW|FSM|Selector4~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_error_d~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|rx_error_c~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|state_fsm~28_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|state_fsm~28 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|state_fsm~28 .lut_mask = 64'h7F007F0000000000;
defparam \A_SPW_TOP|SPW|FSM|state_fsm~28 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y4_N36
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|state_fsm~17 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|state_fsm~17_combout  = ( !\A_SPW_TOP|SPW|RX|rx_got_nchar~q  & ( !\A_SPW_TOP|SPW|RX|rx_got_fct_fsm~q  & ( (\A_SPW_TOP|SPW|FSM|state_fsm~27_combout  & (\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~0_combout  & 
// (\A_SPW_TOP|SPW|FSM|state_fsm~28_combout  & !\A_SPW_TOP|SPW|RX|rx_got_time_code~q ))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|state_fsm~27_combout ),
        .datab(!\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~0_combout ),
        .datac(!\A_SPW_TOP|SPW|FSM|state_fsm~28_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_got_time_code~q ),
        .datae(!\A_SPW_TOP|SPW|RX|rx_got_nchar~q ),
        .dataf(!\A_SPW_TOP|SPW|RX|rx_got_fct_fsm~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|state_fsm~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|state_fsm~17 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|state_fsm~17 .lut_mask = 64'h0100000000000000;
defparam \A_SPW_TOP|SPW|FSM|state_fsm~17 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y4_N41
dffeas \A_SPW_TOP|SPW|FSM|state_fsm.started (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|FSM|state_fsm~17_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|FSM|state_fsm.started~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|state_fsm.started .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|state_fsm.started .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y4_N18
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after128us~0 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after128us~0_combout  = ( \A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q  & ( (!\db_system_spwulight_b|aux_pb~q  & (((\A_SPW_TOP|SPW|FSM|state_fsm.started~q ) # (\A_SPW_TOP|SPW|FSM|state_fsm.connecting~q )) # 
// (\A_SPW_TOP|SPW|FSM|state_fsm.error_wait~q ))) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|state_fsm.error_wait~q ),
        .datab(!\A_SPW_TOP|SPW|FSM|state_fsm.connecting~q ),
        .datac(!\A_SPW_TOP|SPW|FSM|state_fsm.started~q ),
        .datad(!\db_system_spwulight_b|aux_pb~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|after128us~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after128us~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after128us~0 .lut_mask = 64'h000000007F007F00;
defparam \A_SPW_TOP|SPW|FSM|after128us~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y4_N0
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add0~1 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add0~1_sumout  = SUM(( \A_SPW_TOP|SPW|FSM|after128us [0] ) + ( VCC ) + ( !VCC ))
// \A_SPW_TOP|SPW|FSM|Add0~2  = CARRY(( \A_SPW_TOP|SPW|FSM|after128us [0] ) + ( VCC ) + ( !VCC ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|FSM|after128us [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(),
        .sumout(\A_SPW_TOP|SPW|FSM|Add0~1_sumout ),
        .cout(\A_SPW_TOP|SPW|FSM|Add0~2 ),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add0~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add0~1 .lut_mask = 64'h0000000000000F0F;
defparam \A_SPW_TOP|SPW|FSM|Add0~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y4_N24
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after128us~1 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after128us~1_combout  = ( \A_SPW_TOP|SPW|FSM|Add0~1_sumout  & ( \A_SPW_TOP|SPW|FSM|always0~1_combout  & ( (\A_SPW_TOP|SPW|FSM|LessThan0~0_combout  & (\A_SPW_TOP|SPW|FSM|after128us~0_combout  & ((!\A_SPW_TOP|SPW|FSM|Selector4~0_combout ) 
// # (!\A_SPW_TOP|SPW|FSM|always0~0_combout )))) ) ) ) # ( \A_SPW_TOP|SPW|FSM|Add0~1_sumout  & ( !\A_SPW_TOP|SPW|FSM|always0~1_combout  & ( (\A_SPW_TOP|SPW|FSM|LessThan0~0_combout  & \A_SPW_TOP|SPW|FSM|after128us~0_combout ) ) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|Selector4~0_combout ),
        .datab(!\A_SPW_TOP|SPW|FSM|LessThan0~0_combout ),
        .datac(!\A_SPW_TOP|SPW|FSM|after128us~0_combout ),
        .datad(!\A_SPW_TOP|SPW|FSM|always0~0_combout ),
        .datae(!\A_SPW_TOP|SPW|FSM|Add0~1_sumout ),
        .dataf(!\A_SPW_TOP|SPW|FSM|always0~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|after128us~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after128us~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after128us~1 .lut_mask = 64'h0000030300000302;
defparam \A_SPW_TOP|SPW|FSM|after128us~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y4_N26
dffeas \A_SPW_TOP|SPW|FSM|after128us[0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|SPW|FSM|after128us~1_combout ),
        .asdata(vcc),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|FSM|after128us [0]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after128us[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after128us[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y4_N3
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add0~5 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add0~5_sumout  = SUM(( \A_SPW_TOP|SPW|FSM|after128us [1] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add0~2  ))
// \A_SPW_TOP|SPW|FSM|Add0~6  = CARRY(( \A_SPW_TOP|SPW|FSM|after128us [1] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add0~2  ))

        .dataa(!\A_SPW_TOP|SPW|FSM|after128us [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\A_SPW_TOP|SPW|FSM|Add0~2 ),
        .sharein(gnd),
        .combout(),
        .sumout(\A_SPW_TOP|SPW|FSM|Add0~5_sumout ),
        .cout(\A_SPW_TOP|SPW|FSM|Add0~6 ),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add0~5 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add0~5 .lut_mask = 64'h0000FFFF00005555;
defparam \A_SPW_TOP|SPW|FSM|Add0~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y4_N0
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after128us~2 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after128us~2_combout  = ( \A_SPW_TOP|SPW|FSM|after128us~0_combout  & ( \A_SPW_TOP|SPW|FSM|Add0~5_sumout  & ( (\A_SPW_TOP|SPW|FSM|LessThan0~0_combout  & ((!\A_SPW_TOP|SPW|FSM|Selector4~0_combout ) # 
// ((!\A_SPW_TOP|SPW|FSM|always0~1_combout ) # (!\A_SPW_TOP|SPW|FSM|always0~0_combout )))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|Selector4~0_combout ),
        .datab(!\A_SPW_TOP|SPW|FSM|LessThan0~0_combout ),
        .datac(!\A_SPW_TOP|SPW|FSM|always0~1_combout ),
        .datad(!\A_SPW_TOP|SPW|FSM|always0~0_combout ),
        .datae(!\A_SPW_TOP|SPW|FSM|after128us~0_combout ),
        .dataf(!\A_SPW_TOP|SPW|FSM|Add0~5_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|after128us~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after128us~2 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after128us~2 .lut_mask = 64'h0000000000003332;
defparam \A_SPW_TOP|SPW|FSM|after128us~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y4_N2
dffeas \A_SPW_TOP|SPW|FSM|after128us[1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|SPW|FSM|after128us~2_combout ),
        .asdata(vcc),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|FSM|after128us [1]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after128us[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after128us[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y4_N6
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add0~9 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add0~9_sumout  = SUM(( \A_SPW_TOP|SPW|FSM|after128us [2] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add0~6  ))
// \A_SPW_TOP|SPW|FSM|Add0~10  = CARRY(( \A_SPW_TOP|SPW|FSM|after128us [2] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add0~6  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|FSM|after128us [2]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\A_SPW_TOP|SPW|FSM|Add0~6 ),
        .sharein(gnd),
        .combout(),
        .sumout(\A_SPW_TOP|SPW|FSM|Add0~9_sumout ),
        .cout(\A_SPW_TOP|SPW|FSM|Add0~10 ),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add0~9 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add0~9 .lut_mask = 64'h0000FFFF00000F0F;
defparam \A_SPW_TOP|SPW|FSM|Add0~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y4_N9
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after128us~3 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after128us~3_combout  = ( \A_SPW_TOP|SPW|FSM|Add0~9_sumout  & ( \A_SPW_TOP|SPW|FSM|always0~1_combout  & ( (\A_SPW_TOP|SPW|FSM|after128us~0_combout  & (\A_SPW_TOP|SPW|FSM|LessThan0~0_combout  & ((!\A_SPW_TOP|SPW|FSM|always0~0_combout ) # 
// (!\A_SPW_TOP|SPW|FSM|Selector4~0_combout )))) ) ) ) # ( \A_SPW_TOP|SPW|FSM|Add0~9_sumout  & ( !\A_SPW_TOP|SPW|FSM|always0~1_combout  & ( (\A_SPW_TOP|SPW|FSM|after128us~0_combout  & \A_SPW_TOP|SPW|FSM|LessThan0~0_combout ) ) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|after128us~0_combout ),
        .datab(!\A_SPW_TOP|SPW|FSM|always0~0_combout ),
        .datac(!\A_SPW_TOP|SPW|FSM|LessThan0~0_combout ),
        .datad(!\A_SPW_TOP|SPW|FSM|Selector4~0_combout ),
        .datae(!\A_SPW_TOP|SPW|FSM|Add0~9_sumout ),
        .dataf(!\A_SPW_TOP|SPW|FSM|always0~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|after128us~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after128us~3 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after128us~3 .lut_mask = 64'h0000050500000504;
defparam \A_SPW_TOP|SPW|FSM|after128us~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y4_N11
dffeas \A_SPW_TOP|SPW|FSM|after128us[2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|SPW|FSM|after128us~3_combout ),
        .asdata(vcc),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|FSM|after128us [2]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after128us[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after128us[2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y4_N9
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add0~13 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add0~13_sumout  = SUM(( \A_SPW_TOP|SPW|FSM|after128us [3] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add0~10  ))
// \A_SPW_TOP|SPW|FSM|Add0~14  = CARRY(( \A_SPW_TOP|SPW|FSM|after128us [3] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add0~10  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|FSM|after128us [3]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\A_SPW_TOP|SPW|FSM|Add0~10 ),
        .sharein(gnd),
        .combout(),
        .sumout(\A_SPW_TOP|SPW|FSM|Add0~13_sumout ),
        .cout(\A_SPW_TOP|SPW|FSM|Add0~14 ),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add0~13 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add0~13 .lut_mask = 64'h0000FFFF00000F0F;
defparam \A_SPW_TOP|SPW|FSM|Add0~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y4_N36
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after128us~4 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after128us~4_combout  = ( \A_SPW_TOP|SPW|FSM|after128us~0_combout  & ( \A_SPW_TOP|SPW|FSM|Add0~13_sumout  & ( (\A_SPW_TOP|SPW|FSM|LessThan0~0_combout  & ((!\A_SPW_TOP|SPW|FSM|always0~1_combout ) # 
// ((!\A_SPW_TOP|SPW|FSM|Selector4~0_combout ) # (!\A_SPW_TOP|SPW|FSM|always0~0_combout )))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|always0~1_combout ),
        .datab(!\A_SPW_TOP|SPW|FSM|LessThan0~0_combout ),
        .datac(!\A_SPW_TOP|SPW|FSM|Selector4~0_combout ),
        .datad(!\A_SPW_TOP|SPW|FSM|always0~0_combout ),
        .datae(!\A_SPW_TOP|SPW|FSM|after128us~0_combout ),
        .dataf(!\A_SPW_TOP|SPW|FSM|Add0~13_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|after128us~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after128us~4 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after128us~4 .lut_mask = 64'h0000000000003332;
defparam \A_SPW_TOP|SPW|FSM|after128us~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y4_N38
dffeas \A_SPW_TOP|SPW|FSM|after128us[3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|SPW|FSM|after128us~4_combout ),
        .asdata(vcc),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|FSM|after128us [3]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after128us[3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after128us[3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y4_N12
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add0~17 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add0~17_sumout  = SUM(( \A_SPW_TOP|SPW|FSM|after128us [4] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add0~14  ))
// \A_SPW_TOP|SPW|FSM|Add0~18  = CARRY(( \A_SPW_TOP|SPW|FSM|after128us [4] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add0~14  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|FSM|after128us [4]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\A_SPW_TOP|SPW|FSM|Add0~14 ),
        .sharein(gnd),
        .combout(),
        .sumout(\A_SPW_TOP|SPW|FSM|Add0~17_sumout ),
        .cout(\A_SPW_TOP|SPW|FSM|Add0~18 ),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add0~17 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add0~17 .lut_mask = 64'h0000FFFF00000F0F;
defparam \A_SPW_TOP|SPW|FSM|Add0~17 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y4_N39
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after128us~5 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after128us~5_combout  = ( \A_SPW_TOP|SPW|FSM|after128us~0_combout  & ( \A_SPW_TOP|SPW|FSM|Add0~17_sumout  & ( (\A_SPW_TOP|SPW|FSM|LessThan0~0_combout  & ((!\A_SPW_TOP|SPW|FSM|always0~1_combout ) # ((!\A_SPW_TOP|SPW|FSM|always0~0_combout 
// ) # (!\A_SPW_TOP|SPW|FSM|Selector4~0_combout )))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|always0~1_combout ),
        .datab(!\A_SPW_TOP|SPW|FSM|LessThan0~0_combout ),
        .datac(!\A_SPW_TOP|SPW|FSM|always0~0_combout ),
        .datad(!\A_SPW_TOP|SPW|FSM|Selector4~0_combout ),
        .datae(!\A_SPW_TOP|SPW|FSM|after128us~0_combout ),
        .dataf(!\A_SPW_TOP|SPW|FSM|Add0~17_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|after128us~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after128us~5 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after128us~5 .lut_mask = 64'h0000000000003332;
defparam \A_SPW_TOP|SPW|FSM|after128us~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y4_N41
dffeas \A_SPW_TOP|SPW|FSM|after128us[4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|SPW|FSM|after128us~5_combout ),
        .asdata(vcc),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|FSM|after128us [4]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after128us[4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after128us[4] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y4_N15
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add0~21 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add0~21_sumout  = SUM(( \A_SPW_TOP|SPW|FSM|after128us [5] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add0~18  ))
// \A_SPW_TOP|SPW|FSM|Add0~22  = CARRY(( \A_SPW_TOP|SPW|FSM|after128us [5] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add0~18  ))

        .dataa(!\A_SPW_TOP|SPW|FSM|after128us [5]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\A_SPW_TOP|SPW|FSM|Add0~18 ),
        .sharein(gnd),
        .combout(),
        .sumout(\A_SPW_TOP|SPW|FSM|Add0~21_sumout ),
        .cout(\A_SPW_TOP|SPW|FSM|Add0~22 ),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add0~21 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add0~21 .lut_mask = 64'h0000FFFF00005555;
defparam \A_SPW_TOP|SPW|FSM|Add0~21 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y4_N42
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after128us~6 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after128us~6_combout  = ( \A_SPW_TOP|SPW|FSM|after128us~0_combout  & ( \A_SPW_TOP|SPW|FSM|Add0~21_sumout  & ( (\A_SPW_TOP|SPW|FSM|LessThan0~0_combout  & ((!\A_SPW_TOP|SPW|FSM|always0~1_combout ) # 
// ((!\A_SPW_TOP|SPW|FSM|Selector4~0_combout ) # (!\A_SPW_TOP|SPW|FSM|always0~0_combout )))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|always0~1_combout ),
        .datab(!\A_SPW_TOP|SPW|FSM|LessThan0~0_combout ),
        .datac(!\A_SPW_TOP|SPW|FSM|Selector4~0_combout ),
        .datad(!\A_SPW_TOP|SPW|FSM|always0~0_combout ),
        .datae(!\A_SPW_TOP|SPW|FSM|after128us~0_combout ),
        .dataf(!\A_SPW_TOP|SPW|FSM|Add0~21_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|after128us~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after128us~6 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after128us~6 .lut_mask = 64'h0000000000003332;
defparam \A_SPW_TOP|SPW|FSM|after128us~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y4_N44
dffeas \A_SPW_TOP|SPW|FSM|after128us[5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|SPW|FSM|after128us~6_combout ),
        .asdata(vcc),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|FSM|after128us [5]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after128us[5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after128us[5] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y4_N18
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add0~25 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add0~25_sumout  = SUM(( \A_SPW_TOP|SPW|FSM|after128us [6] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add0~22  ))
// \A_SPW_TOP|SPW|FSM|Add0~26  = CARRY(( \A_SPW_TOP|SPW|FSM|after128us [6] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add0~22  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|FSM|after128us [6]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\A_SPW_TOP|SPW|FSM|Add0~22 ),
        .sharein(gnd),
        .combout(),
        .sumout(\A_SPW_TOP|SPW|FSM|Add0~25_sumout ),
        .cout(\A_SPW_TOP|SPW|FSM|Add0~26 ),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add0~25 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add0~25 .lut_mask = 64'h0000FFFF00000F0F;
defparam \A_SPW_TOP|SPW|FSM|Add0~25 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y4_N21
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add0~29 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add0~29_sumout  = SUM(( \A_SPW_TOP|SPW|FSM|after128us [7] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add0~26  ))
// \A_SPW_TOP|SPW|FSM|Add0~30  = CARRY(( \A_SPW_TOP|SPW|FSM|after128us [7] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add0~26  ))

        .dataa(!\A_SPW_TOP|SPW|FSM|after128us [7]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\A_SPW_TOP|SPW|FSM|Add0~26 ),
        .sharein(gnd),
        .combout(),
        .sumout(\A_SPW_TOP|SPW|FSM|Add0~29_sumout ),
        .cout(\A_SPW_TOP|SPW|FSM|Add0~30 ),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add0~29 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add0~29 .lut_mask = 64'h0000FFFF00005555;
defparam \A_SPW_TOP|SPW|FSM|Add0~29 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y4_N48
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after128us~8 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after128us~8_combout  = ( \A_SPW_TOP|SPW|FSM|after128us~0_combout  & ( \A_SPW_TOP|SPW|FSM|Add0~29_sumout  & ( (\A_SPW_TOP|SPW|FSM|LessThan0~0_combout  & ((!\A_SPW_TOP|SPW|FSM|Selector4~0_combout ) # 
// ((!\A_SPW_TOP|SPW|FSM|always0~1_combout ) # (!\A_SPW_TOP|SPW|FSM|always0~0_combout )))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|Selector4~0_combout ),
        .datab(!\A_SPW_TOP|SPW|FSM|LessThan0~0_combout ),
        .datac(!\A_SPW_TOP|SPW|FSM|always0~1_combout ),
        .datad(!\A_SPW_TOP|SPW|FSM|always0~0_combout ),
        .datae(!\A_SPW_TOP|SPW|FSM|after128us~0_combout ),
        .dataf(!\A_SPW_TOP|SPW|FSM|Add0~29_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|after128us~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after128us~8 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after128us~8 .lut_mask = 64'h0000000000003332;
defparam \A_SPW_TOP|SPW|FSM|after128us~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y4_N50
dffeas \A_SPW_TOP|SPW|FSM|after128us[7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|SPW|FSM|after128us~8_combout ),
        .asdata(vcc),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|FSM|after128us [7]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after128us[7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after128us[7] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y4_N24
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add0~37 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add0~37_sumout  = SUM(( \A_SPW_TOP|SPW|FSM|after128us [8] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add0~30  ))
// \A_SPW_TOP|SPW|FSM|Add0~38  = CARRY(( \A_SPW_TOP|SPW|FSM|after128us [8] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add0~30  ))

        .dataa(gnd),
        .datab(!\A_SPW_TOP|SPW|FSM|after128us [8]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\A_SPW_TOP|SPW|FSM|Add0~30 ),
        .sharein(gnd),
        .combout(),
        .sumout(\A_SPW_TOP|SPW|FSM|Add0~37_sumout ),
        .cout(\A_SPW_TOP|SPW|FSM|Add0~38 ),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add0~37 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add0~37 .lut_mask = 64'h0000FFFF00003333;
defparam \A_SPW_TOP|SPW|FSM|Add0~37 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y4_N18
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after128us~10 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after128us~10_combout  = ( \A_SPW_TOP|SPW|FSM|after128us~0_combout  & ( \A_SPW_TOP|SPW|FSM|Add0~37_sumout  & ( (\A_SPW_TOP|SPW|FSM|LessThan0~0_combout  & ((!\A_SPW_TOP|SPW|FSM|always0~1_combout ) # 
// ((!\A_SPW_TOP|SPW|FSM|Selector4~0_combout ) # (!\A_SPW_TOP|SPW|FSM|always0~0_combout )))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|always0~1_combout ),
        .datab(!\A_SPW_TOP|SPW|FSM|LessThan0~0_combout ),
        .datac(!\A_SPW_TOP|SPW|FSM|Selector4~0_combout ),
        .datad(!\A_SPW_TOP|SPW|FSM|always0~0_combout ),
        .datae(!\A_SPW_TOP|SPW|FSM|after128us~0_combout ),
        .dataf(!\A_SPW_TOP|SPW|FSM|Add0~37_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|after128us~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after128us~10 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after128us~10 .lut_mask = 64'h0000000000003332;
defparam \A_SPW_TOP|SPW|FSM|after128us~10 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y4_N20
dffeas \A_SPW_TOP|SPW|FSM|after128us[8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|SPW|FSM|after128us~10_combout ),
        .asdata(vcc),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|FSM|after128us [8]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after128us[8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after128us[8] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y4_N27
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add0~41 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add0~41_sumout  = SUM(( \A_SPW_TOP|SPW|FSM|after128us [9] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add0~38  ))
// \A_SPW_TOP|SPW|FSM|Add0~42  = CARRY(( \A_SPW_TOP|SPW|FSM|after128us [9] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add0~38  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|FSM|after128us [9]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\A_SPW_TOP|SPW|FSM|Add0~38 ),
        .sharein(gnd),
        .combout(),
        .sumout(\A_SPW_TOP|SPW|FSM|Add0~41_sumout ),
        .cout(\A_SPW_TOP|SPW|FSM|Add0~42 ),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add0~41 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add0~41 .lut_mask = 64'h0000FFFF00000F0F;
defparam \A_SPW_TOP|SPW|FSM|Add0~41 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y4_N21
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after128us~11 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after128us~11_combout  = ( \A_SPW_TOP|SPW|FSM|after128us~0_combout  & ( \A_SPW_TOP|SPW|FSM|Add0~41_sumout  & ( (\A_SPW_TOP|SPW|FSM|LessThan0~0_combout  & ((!\A_SPW_TOP|SPW|FSM|always0~1_combout ) # 
// ((!\A_SPW_TOP|SPW|FSM|always0~0_combout ) # (!\A_SPW_TOP|SPW|FSM|Selector4~0_combout )))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|always0~1_combout ),
        .datab(!\A_SPW_TOP|SPW|FSM|LessThan0~0_combout ),
        .datac(!\A_SPW_TOP|SPW|FSM|always0~0_combout ),
        .datad(!\A_SPW_TOP|SPW|FSM|Selector4~0_combout ),
        .datae(!\A_SPW_TOP|SPW|FSM|after128us~0_combout ),
        .dataf(!\A_SPW_TOP|SPW|FSM|Add0~41_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|after128us~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after128us~11 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after128us~11 .lut_mask = 64'h0000000000003332;
defparam \A_SPW_TOP|SPW|FSM|after128us~11 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y4_N23
dffeas \A_SPW_TOP|SPW|FSM|after128us[9] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|SPW|FSM|after128us~11_combout ),
        .asdata(vcc),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|FSM|after128us [9]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after128us[9] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after128us[9] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y4_N30
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add0~33 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add0~33_sumout  = SUM(( \A_SPW_TOP|SPW|FSM|after128us [10] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add0~42  ))
// \A_SPW_TOP|SPW|FSM|Add0~34  = CARRY(( \A_SPW_TOP|SPW|FSM|after128us [10] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add0~42  ))

        .dataa(gnd),
        .datab(!\A_SPW_TOP|SPW|FSM|after128us [10]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\A_SPW_TOP|SPW|FSM|Add0~42 ),
        .sharein(gnd),
        .combout(),
        .sumout(\A_SPW_TOP|SPW|FSM|Add0~33_sumout ),
        .cout(\A_SPW_TOP|SPW|FSM|Add0~34 ),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add0~33 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add0~33 .lut_mask = 64'h0000FFFF00003333;
defparam \A_SPW_TOP|SPW|FSM|Add0~33 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y4_N51
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after128us~9 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after128us~9_combout  = ( \A_SPW_TOP|SPW|FSM|after128us~0_combout  & ( \A_SPW_TOP|SPW|FSM|Add0~33_sumout  & ( (\A_SPW_TOP|SPW|FSM|LessThan0~0_combout  & ((!\A_SPW_TOP|SPW|FSM|Selector4~0_combout ) # 
// ((!\A_SPW_TOP|SPW|FSM|always0~0_combout ) # (!\A_SPW_TOP|SPW|FSM|always0~1_combout )))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|Selector4~0_combout ),
        .datab(!\A_SPW_TOP|SPW|FSM|LessThan0~0_combout ),
        .datac(!\A_SPW_TOP|SPW|FSM|always0~0_combout ),
        .datad(!\A_SPW_TOP|SPW|FSM|always0~1_combout ),
        .datae(!\A_SPW_TOP|SPW|FSM|after128us~0_combout ),
        .dataf(!\A_SPW_TOP|SPW|FSM|Add0~33_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|after128us~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after128us~9 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after128us~9 .lut_mask = 64'h0000000000003332;
defparam \A_SPW_TOP|SPW|FSM|after128us~9 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y4_N53
dffeas \A_SPW_TOP|SPW|FSM|after128us[10] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|SPW|FSM|after128us~9_combout ),
        .asdata(vcc),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|FSM|after128us [10]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after128us[10] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after128us[10] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y4_N45
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Equal0~0 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Equal0~0_combout  = ( \A_SPW_TOP|SPW|FSM|after128us [1] & ( \A_SPW_TOP|SPW|FSM|after128us [4] & ( (\A_SPW_TOP|SPW|FSM|after128us [5] & (\A_SPW_TOP|SPW|FSM|after128us [3] & (\A_SPW_TOP|SPW|FSM|after128us [0] & 
// \A_SPW_TOP|SPW|FSM|after128us [2]))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|after128us [5]),
        .datab(!\A_SPW_TOP|SPW|FSM|after128us [3]),
        .datac(!\A_SPW_TOP|SPW|FSM|after128us [0]),
        .datad(!\A_SPW_TOP|SPW|FSM|after128us [2]),
        .datae(!\A_SPW_TOP|SPW|FSM|after128us [1]),
        .dataf(!\A_SPW_TOP|SPW|FSM|after128us [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|Equal0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Equal0~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Equal0~0 .lut_mask = 64'h0000000000000001;
defparam \A_SPW_TOP|SPW|FSM|Equal0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y4_N30
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|LessThan0~0 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|LessThan0~0_combout  = ( \A_SPW_TOP|SPW|FSM|after128us [9] & ( \A_SPW_TOP|SPW|FSM|after128us [8] & ( (!\A_SPW_TOP|SPW|FSM|after128us [10] & !\A_SPW_TOP|SPW|FSM|after128us [11]) ) ) ) # ( !\A_SPW_TOP|SPW|FSM|after128us [9] & ( 
// \A_SPW_TOP|SPW|FSM|after128us [8] & ( (!\A_SPW_TOP|SPW|FSM|after128us [10] & !\A_SPW_TOP|SPW|FSM|after128us [11]) ) ) ) # ( \A_SPW_TOP|SPW|FSM|after128us [9] & ( !\A_SPW_TOP|SPW|FSM|after128us [8] & ( (!\A_SPW_TOP|SPW|FSM|after128us [10] & 
// !\A_SPW_TOP|SPW|FSM|after128us [11]) ) ) ) # ( !\A_SPW_TOP|SPW|FSM|after128us [9] & ( !\A_SPW_TOP|SPW|FSM|after128us [8] & ( (!\A_SPW_TOP|SPW|FSM|after128us [11] & ((!\A_SPW_TOP|SPW|FSM|after128us [10]) # ((!\A_SPW_TOP|SPW|FSM|Equal0~0_combout ) # 
// (!\A_SPW_TOP|SPW|FSM|Equal0~1_combout )))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|after128us [10]),
        .datab(!\A_SPW_TOP|SPW|FSM|Equal0~0_combout ),
        .datac(!\A_SPW_TOP|SPW|FSM|after128us [11]),
        .datad(!\A_SPW_TOP|SPW|FSM|Equal0~1_combout ),
        .datae(!\A_SPW_TOP|SPW|FSM|after128us [9]),
        .dataf(!\A_SPW_TOP|SPW|FSM|after128us [8]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|LessThan0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|LessThan0~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|LessThan0~0 .lut_mask = 64'hF0E0A0A0A0A0A0A0;
defparam \A_SPW_TOP|SPW|FSM|LessThan0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y4_N45
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after128us~7 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after128us~7_combout  = ( \A_SPW_TOP|SPW|FSM|after128us~0_combout  & ( \A_SPW_TOP|SPW|FSM|Add0~25_sumout  & ( (\A_SPW_TOP|SPW|FSM|LessThan0~0_combout  & ((!\A_SPW_TOP|SPW|FSM|always0~1_combout ) # ((!\A_SPW_TOP|SPW|FSM|always0~0_combout 
// ) # (!\A_SPW_TOP|SPW|FSM|Selector4~0_combout )))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|always0~1_combout ),
        .datab(!\A_SPW_TOP|SPW|FSM|LessThan0~0_combout ),
        .datac(!\A_SPW_TOP|SPW|FSM|always0~0_combout ),
        .datad(!\A_SPW_TOP|SPW|FSM|Selector4~0_combout ),
        .datae(!\A_SPW_TOP|SPW|FSM|after128us~0_combout ),
        .dataf(!\A_SPW_TOP|SPW|FSM|Add0~25_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|after128us~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after128us~7 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after128us~7 .lut_mask = 64'h0000000000003332;
defparam \A_SPW_TOP|SPW|FSM|after128us~7 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y4_N47
dffeas \A_SPW_TOP|SPW|FSM|after128us[6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|SPW|FSM|after128us~7_combout ),
        .asdata(vcc),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|FSM|after128us [6]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after128us[6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after128us[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y4_N15
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Equal0~1 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Equal0~1_combout  = ( \A_SPW_TOP|SPW|FSM|after128us [7] & ( \A_SPW_TOP|SPW|FSM|after128us [6] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|FSM|after128us [6]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|FSM|after128us [7]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|Equal0~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Equal0~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Equal0~1 .lut_mask = 64'h000000000F0F0F0F;
defparam \A_SPW_TOP|SPW|FSM|Equal0~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y4_N48
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Selector4~0 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Selector4~0_combout  = ( \A_SPW_TOP|SPW|FSM|Equal0~0_combout  & ( (\A_SPW_TOP|SPW|FSM|state_fsm.started~q  & ((!\A_SPW_TOP|SPW|FSM|Equal0~2_combout ) # (!\A_SPW_TOP|SPW|FSM|Equal0~1_combout ))) ) ) # ( 
// !\A_SPW_TOP|SPW|FSM|Equal0~0_combout  & ( \A_SPW_TOP|SPW|FSM|state_fsm.started~q  ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|SPW|FSM|Equal0~2_combout ),
        .datac(!\A_SPW_TOP|SPW|FSM|state_fsm.started~q ),
        .datad(!\A_SPW_TOP|SPW|FSM|Equal0~1_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|FSM|Equal0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|Selector4~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Selector4~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Selector4~0 .lut_mask = 64'h0F0F0F0F0F0C0F0C;
defparam \A_SPW_TOP|SPW|FSM|Selector4~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y4_N33
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add0~45 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add0~45_sumout  = SUM(( \A_SPW_TOP|SPW|FSM|after128us [11] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add0~34  ))

        .dataa(!\A_SPW_TOP|SPW|FSM|after128us [11]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\A_SPW_TOP|SPW|FSM|Add0~34 ),
        .sharein(gnd),
        .combout(),
        .sumout(\A_SPW_TOP|SPW|FSM|Add0~45_sumout ),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add0~45 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add0~45 .lut_mask = 64'h0000FFFF00005555;
defparam \A_SPW_TOP|SPW|FSM|Add0~45 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y4_N3
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after128us~12 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after128us~12_combout  = ( \A_SPW_TOP|SPW|FSM|after128us~0_combout  & ( \A_SPW_TOP|SPW|FSM|Add0~45_sumout  & ( (\A_SPW_TOP|SPW|FSM|LessThan0~0_combout  & ((!\A_SPW_TOP|SPW|FSM|Selector4~0_combout ) # 
// ((!\A_SPW_TOP|SPW|FSM|always0~0_combout ) # (!\A_SPW_TOP|SPW|FSM|always0~1_combout )))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|Selector4~0_combout ),
        .datab(!\A_SPW_TOP|SPW|FSM|LessThan0~0_combout ),
        .datac(!\A_SPW_TOP|SPW|FSM|always0~0_combout ),
        .datad(!\A_SPW_TOP|SPW|FSM|always0~1_combout ),
        .datae(!\A_SPW_TOP|SPW|FSM|after128us~0_combout ),
        .dataf(!\A_SPW_TOP|SPW|FSM|Add0~45_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|after128us~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after128us~12 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after128us~12 .lut_mask = 64'h0000000000003332;
defparam \A_SPW_TOP|SPW|FSM|after128us~12 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y4_N5
dffeas \A_SPW_TOP|SPW|FSM|after128us[11] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|SPW|FSM|after128us~12_combout ),
        .asdata(vcc),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|FSM|after128us [11]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after128us[11] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after128us[11] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y4_N12
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Equal0~2 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Equal0~2_combout  = ( !\A_SPW_TOP|SPW|FSM|after128us [8] & ( (!\A_SPW_TOP|SPW|FSM|after128us [11] & (\A_SPW_TOP|SPW|FSM|after128us [10] & !\A_SPW_TOP|SPW|FSM|after128us [9])) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|after128us [11]),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|FSM|after128us [10]),
        .datad(!\A_SPW_TOP|SPW|FSM|after128us [9]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|FSM|after128us [8]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|Equal0~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Equal0~2 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Equal0~2 .lut_mask = 64'h0A000A0000000000;
defparam \A_SPW_TOP|SPW|FSM|Equal0~2 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y4_N57
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Equal0~3 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Equal0~3_combout  = ( \A_SPW_TOP|SPW|FSM|Equal0~0_combout  & ( (\A_SPW_TOP|SPW|FSM|Equal0~2_combout  & \A_SPW_TOP|SPW|FSM|Equal0~1_combout ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|FSM|Equal0~2_combout ),
        .datad(!\A_SPW_TOP|SPW|FSM|Equal0~1_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|FSM|Equal0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|Equal0~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Equal0~3 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Equal0~3 .lut_mask = 64'h00000000000F000F;
defparam \A_SPW_TOP|SPW|FSM|Equal0~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X51_Y4_N33
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Selector0~1 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Selector0~1_combout  = ( \A_SPW_TOP|SPW|RX|rx_got_time_code~q  & ( \A_SPW_TOP|SPW|FSM|state_fsm.connecting~q  ) ) # ( !\A_SPW_TOP|SPW|RX|rx_got_time_code~q  & ( \A_SPW_TOP|SPW|FSM|state_fsm.connecting~q  & ( 
// (((\A_SPW_TOP|SPW|FSM|Equal0~3_combout ) # (\A_SPW_TOP|SPW|RX|rx_error_c~q )) # (\A_SPW_TOP|SPW|RX|rx_error_d~q )) # (\A_SPW_TOP|SPW|RX|rx_got_nchar~q ) ) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_got_nchar~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_error_d~q ),
        .datac(!\A_SPW_TOP|SPW|RX|rx_error_c~q ),
        .datad(!\A_SPW_TOP|SPW|FSM|Equal0~3_combout ),
        .datae(!\A_SPW_TOP|SPW|RX|rx_got_time_code~q ),
        .dataf(!\A_SPW_TOP|SPW|FSM|state_fsm.connecting~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|Selector0~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Selector0~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Selector0~1 .lut_mask = 64'h000000007FFFFFFF;
defparam \A_SPW_TOP|SPW|FSM|Selector0~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y4_N3
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Selector0~2 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Selector0~2_combout  = ( \A_SPW_TOP|SPW|FSM|state_fsm.started~q  & ( (\A_SPW_TOP|SPW|FSM|Equal0~0_combout  & (\A_SPW_TOP|SPW|FSM|Equal0~2_combout  & \A_SPW_TOP|SPW|FSM|Equal0~1_combout )) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|Equal0~0_combout ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|FSM|Equal0~2_combout ),
        .datad(!\A_SPW_TOP|SPW|FSM|Equal0~1_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|FSM|state_fsm.started~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|Selector0~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Selector0~2 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Selector0~2 .lut_mask = 64'h0000000000050005;
defparam \A_SPW_TOP|SPW|FSM|Selector0~2 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y4_N27
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|got_bit_internal~0 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|got_bit_internal~0_combout  = ( \din_a~input_o  & ( !\db_system_spwulight_b|aux_pb~q  ) ) # ( !\din_a~input_o  & ( (!\db_system_spwulight_b|aux_pb~q  & \sin_a~input_o ) ) )

        .dataa(!\db_system_spwulight_b|aux_pb~q ),
        .datab(gnd),
        .datac(!\sin_a~input_o ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\din_a~input_o ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|got_bit_internal~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|got_bit_internal~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|got_bit_internal~0 .lut_mask = 64'h0A0A0A0AAAAAAAAA;
defparam \A_SPW_TOP|SPW|FSM|got_bit_internal~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y4_N35
dffeas \A_SPW_TOP|SPW|FSM|got_bit_internal (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|FSM|got_bit_internal~0_combout ),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|FSM|got_bit_internal~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|got_bit_internal .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|got_bit_internal .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y6_N0
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add2~29 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add2~29_sumout  = SUM(( \A_SPW_TOP|SPW|FSM|after850ns [0] ) + ( VCC ) + ( !VCC ))
// \A_SPW_TOP|SPW|FSM|Add2~30  = CARRY(( \A_SPW_TOP|SPW|FSM|after850ns [0] ) + ( VCC ) + ( !VCC ))

        .dataa(gnd),
        .datab(!\A_SPW_TOP|SPW|FSM|after850ns [0]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(),
        .sumout(\A_SPW_TOP|SPW|FSM|Add2~29_sumout ),
        .cout(\A_SPW_TOP|SPW|FSM|Add2~30 ),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add2~29 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add2~29 .lut_mask = 64'h0000000000003333;
defparam \A_SPW_TOP|SPW|FSM|Add2~29 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y6_N6
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after850ns~7 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after850ns~7_combout  = ( \A_SPW_TOP|SPW|FSM|after850ns [0] & ( \A_SPW_TOP|SPW|FSM|Add2~29_sumout  & ( (\A_SPW_TOP|SPW|FSM|state_fsm.run~q  & (!\A_SPW_TOP|SPW|FSM|got_bit_internal~q  & !\db_system_spwulight_b|aux_pb~q )) ) ) ) # ( 
// !\A_SPW_TOP|SPW|FSM|after850ns [0] & ( \A_SPW_TOP|SPW|FSM|Add2~29_sumout  & ( (\A_SPW_TOP|SPW|FSM|state_fsm.run~q  & (!\A_SPW_TOP|SPW|FSM|got_bit_internal~q  & (\A_SPW_TOP|SPW|FSM|always5~1_combout  & !\db_system_spwulight_b|aux_pb~q ))) ) ) ) # ( 
// \A_SPW_TOP|SPW|FSM|after850ns [0] & ( !\A_SPW_TOP|SPW|FSM|Add2~29_sumout  & ( (\A_SPW_TOP|SPW|FSM|state_fsm.run~q  & (!\A_SPW_TOP|SPW|FSM|got_bit_internal~q  & (!\A_SPW_TOP|SPW|FSM|always5~1_combout  & !\db_system_spwulight_b|aux_pb~q ))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|state_fsm.run~q ),
        .datab(!\A_SPW_TOP|SPW|FSM|got_bit_internal~q ),
        .datac(!\A_SPW_TOP|SPW|FSM|always5~1_combout ),
        .datad(!\db_system_spwulight_b|aux_pb~q ),
        .datae(!\A_SPW_TOP|SPW|FSM|after850ns [0]),
        .dataf(!\A_SPW_TOP|SPW|FSM|Add2~29_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|after850ns~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after850ns~7 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after850ns~7 .lut_mask = 64'h0000400004004400;
defparam \A_SPW_TOP|SPW|FSM|after850ns~7 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X51_Y6_N56
dffeas \A_SPW_TOP|SPW|FSM|after850ns[0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|FSM|after850ns~7_combout ),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|FSM|after850ns [0]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after850ns[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after850ns[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y6_N3
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add2~25 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add2~25_sumout  = SUM(( \A_SPW_TOP|SPW|FSM|after850ns [1] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add2~30  ))
// \A_SPW_TOP|SPW|FSM|Add2~26  = CARRY(( \A_SPW_TOP|SPW|FSM|after850ns [1] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add2~30  ))

        .dataa(!\A_SPW_TOP|SPW|FSM|after850ns [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\A_SPW_TOP|SPW|FSM|Add2~30 ),
        .sharein(gnd),
        .combout(),
        .sumout(\A_SPW_TOP|SPW|FSM|Add2~25_sumout ),
        .cout(\A_SPW_TOP|SPW|FSM|Add2~26 ),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add2~25 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add2~25 .lut_mask = 64'h0000FFFF00005555;
defparam \A_SPW_TOP|SPW|FSM|Add2~25 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y6_N36
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after850ns~6 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after850ns~6_combout  = ( \A_SPW_TOP|SPW|FSM|after850ns [1] & ( \A_SPW_TOP|SPW|FSM|Add2~25_sumout  & ( (!\A_SPW_TOP|SPW|FSM|got_bit_internal~q  & (!\db_system_spwulight_b|aux_pb~q  & \A_SPW_TOP|SPW|FSM|state_fsm.run~q )) ) ) ) # ( 
// !\A_SPW_TOP|SPW|FSM|after850ns [1] & ( \A_SPW_TOP|SPW|FSM|Add2~25_sumout  & ( (!\A_SPW_TOP|SPW|FSM|got_bit_internal~q  & (\A_SPW_TOP|SPW|FSM|always5~1_combout  & (!\db_system_spwulight_b|aux_pb~q  & \A_SPW_TOP|SPW|FSM|state_fsm.run~q ))) ) ) ) # ( 
// \A_SPW_TOP|SPW|FSM|after850ns [1] & ( !\A_SPW_TOP|SPW|FSM|Add2~25_sumout  & ( (!\A_SPW_TOP|SPW|FSM|got_bit_internal~q  & (!\A_SPW_TOP|SPW|FSM|always5~1_combout  & (!\db_system_spwulight_b|aux_pb~q  & \A_SPW_TOP|SPW|FSM|state_fsm.run~q ))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|got_bit_internal~q ),
        .datab(!\A_SPW_TOP|SPW|FSM|always5~1_combout ),
        .datac(!\db_system_spwulight_b|aux_pb~q ),
        .datad(!\A_SPW_TOP|SPW|FSM|state_fsm.run~q ),
        .datae(!\A_SPW_TOP|SPW|FSM|after850ns [1]),
        .dataf(!\A_SPW_TOP|SPW|FSM|Add2~25_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|after850ns~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after850ns~6 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after850ns~6 .lut_mask = 64'h00000080002000A0;
defparam \A_SPW_TOP|SPW|FSM|after850ns~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y6_N56
dffeas \A_SPW_TOP|SPW|FSM|after850ns[1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|FSM|after850ns~6_combout ),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|FSM|after850ns [1]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after850ns[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after850ns[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y6_N6
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add2~21 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add2~21_sumout  = SUM(( \A_SPW_TOP|SPW|FSM|after850ns [2] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add2~26  ))
// \A_SPW_TOP|SPW|FSM|Add2~22  = CARRY(( \A_SPW_TOP|SPW|FSM|after850ns [2] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add2~26  ))

        .dataa(gnd),
        .datab(!\A_SPW_TOP|SPW|FSM|after850ns [2]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\A_SPW_TOP|SPW|FSM|Add2~26 ),
        .sharein(gnd),
        .combout(),
        .sumout(\A_SPW_TOP|SPW|FSM|Add2~21_sumout ),
        .cout(\A_SPW_TOP|SPW|FSM|Add2~22 ),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add2~21 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add2~21 .lut_mask = 64'h0000FFFF00003333;
defparam \A_SPW_TOP|SPW|FSM|Add2~21 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y6_N9
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add2~9 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add2~9_sumout  = SUM(( \A_SPW_TOP|SPW|FSM|after850ns [3] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add2~22  ))
// \A_SPW_TOP|SPW|FSM|Add2~10  = CARRY(( \A_SPW_TOP|SPW|FSM|after850ns [3] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add2~22  ))

        .dataa(!\A_SPW_TOP|SPW|FSM|after850ns [3]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\A_SPW_TOP|SPW|FSM|Add2~22 ),
        .sharein(gnd),
        .combout(),
        .sumout(\A_SPW_TOP|SPW|FSM|Add2~9_sumout ),
        .cout(\A_SPW_TOP|SPW|FSM|Add2~10 ),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add2~9 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add2~9 .lut_mask = 64'h0000FFFF00005555;
defparam \A_SPW_TOP|SPW|FSM|Add2~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y6_N39
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after850ns~2 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after850ns~2_combout  = ( \A_SPW_TOP|SPW|FSM|after850ns [3] & ( \A_SPW_TOP|SPW|FSM|Add2~9_sumout  & ( (!\A_SPW_TOP|SPW|FSM|got_bit_internal~q  & (\A_SPW_TOP|SPW|FSM|state_fsm.run~q  & !\db_system_spwulight_b|aux_pb~q )) ) ) ) # ( 
// !\A_SPW_TOP|SPW|FSM|after850ns [3] & ( \A_SPW_TOP|SPW|FSM|Add2~9_sumout  & ( (!\A_SPW_TOP|SPW|FSM|got_bit_internal~q  & (\A_SPW_TOP|SPW|FSM|always5~1_combout  & (\A_SPW_TOP|SPW|FSM|state_fsm.run~q  & !\db_system_spwulight_b|aux_pb~q ))) ) ) ) # ( 
// \A_SPW_TOP|SPW|FSM|after850ns [3] & ( !\A_SPW_TOP|SPW|FSM|Add2~9_sumout  & ( (!\A_SPW_TOP|SPW|FSM|got_bit_internal~q  & (!\A_SPW_TOP|SPW|FSM|always5~1_combout  & (\A_SPW_TOP|SPW|FSM|state_fsm.run~q  & !\db_system_spwulight_b|aux_pb~q ))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|got_bit_internal~q ),
        .datab(!\A_SPW_TOP|SPW|FSM|always5~1_combout ),
        .datac(!\A_SPW_TOP|SPW|FSM|state_fsm.run~q ),
        .datad(!\db_system_spwulight_b|aux_pb~q ),
        .datae(!\A_SPW_TOP|SPW|FSM|after850ns [3]),
        .dataf(!\A_SPW_TOP|SPW|FSM|Add2~9_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|after850ns~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after850ns~2 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after850ns~2 .lut_mask = 64'h0000080002000A00;
defparam \A_SPW_TOP|SPW|FSM|after850ns~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y6_N35
dffeas \A_SPW_TOP|SPW|FSM|after850ns[3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|FSM|after850ns~2_combout ),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|FSM|after850ns [3]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after850ns[3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after850ns[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y6_N12
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add2~17 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add2~17_sumout  = SUM(( \A_SPW_TOP|SPW|FSM|after850ns [4] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add2~10  ))
// \A_SPW_TOP|SPW|FSM|Add2~18  = CARRY(( \A_SPW_TOP|SPW|FSM|after850ns [4] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add2~10  ))

        .dataa(gnd),
        .datab(!\A_SPW_TOP|SPW|FSM|after850ns [4]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\A_SPW_TOP|SPW|FSM|Add2~10 ),
        .sharein(gnd),
        .combout(),
        .sumout(\A_SPW_TOP|SPW|FSM|Add2~17_sumout ),
        .cout(\A_SPW_TOP|SPW|FSM|Add2~18 ),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add2~17 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add2~17 .lut_mask = 64'h0000FFFF00003333;
defparam \A_SPW_TOP|SPW|FSM|Add2~17 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y6_N45
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after850ns~4 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after850ns~4_combout  = ( \A_SPW_TOP|SPW|FSM|after850ns [4] & ( \A_SPW_TOP|SPW|FSM|Add2~17_sumout  & ( (!\A_SPW_TOP|SPW|FSM|got_bit_internal~q  & (\A_SPW_TOP|SPW|FSM|state_fsm.run~q  & !\db_system_spwulight_b|aux_pb~q )) ) ) ) # ( 
// !\A_SPW_TOP|SPW|FSM|after850ns [4] & ( \A_SPW_TOP|SPW|FSM|Add2~17_sumout  & ( (!\A_SPW_TOP|SPW|FSM|got_bit_internal~q  & (\A_SPW_TOP|SPW|FSM|state_fsm.run~q  & (\A_SPW_TOP|SPW|FSM|always5~1_combout  & !\db_system_spwulight_b|aux_pb~q ))) ) ) ) # ( 
// \A_SPW_TOP|SPW|FSM|after850ns [4] & ( !\A_SPW_TOP|SPW|FSM|Add2~17_sumout  & ( (!\A_SPW_TOP|SPW|FSM|got_bit_internal~q  & (\A_SPW_TOP|SPW|FSM|state_fsm.run~q  & (!\A_SPW_TOP|SPW|FSM|always5~1_combout  & !\db_system_spwulight_b|aux_pb~q ))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|got_bit_internal~q ),
        .datab(!\A_SPW_TOP|SPW|FSM|state_fsm.run~q ),
        .datac(!\A_SPW_TOP|SPW|FSM|always5~1_combout ),
        .datad(!\db_system_spwulight_b|aux_pb~q ),
        .datae(!\A_SPW_TOP|SPW|FSM|after850ns [4]),
        .dataf(!\A_SPW_TOP|SPW|FSM|Add2~17_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|after850ns~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after850ns~4 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after850ns~4 .lut_mask = 64'h0000200002002200;
defparam \A_SPW_TOP|SPW|FSM|after850ns~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y6_N59
dffeas \A_SPW_TOP|SPW|FSM|after850ns[4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|FSM|after850ns~4_combout ),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|FSM|after850ns [4]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after850ns[4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after850ns[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y6_N15
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add2~5 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add2~5_sumout  = SUM(( \A_SPW_TOP|SPW|FSM|after850ns [5] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add2~18  ))
// \A_SPW_TOP|SPW|FSM|Add2~6  = CARRY(( \A_SPW_TOP|SPW|FSM|after850ns [5] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add2~18  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|FSM|after850ns [5]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\A_SPW_TOP|SPW|FSM|Add2~18 ),
        .sharein(gnd),
        .combout(),
        .sumout(\A_SPW_TOP|SPW|FSM|Add2~5_sumout ),
        .cout(\A_SPW_TOP|SPW|FSM|Add2~6 ),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add2~5 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add2~5 .lut_mask = 64'h0000FFFF00000F0F;
defparam \A_SPW_TOP|SPW|FSM|Add2~5 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y6_N42
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after850ns~1 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after850ns~1_combout  = ( \A_SPW_TOP|SPW|FSM|after850ns [5] & ( \A_SPW_TOP|SPW|FSM|Add2~5_sumout  & ( (\A_SPW_TOP|SPW|FSM|state_fsm.run~q  & (!\A_SPW_TOP|SPW|FSM|got_bit_internal~q  & !\db_system_spwulight_b|aux_pb~q )) ) ) ) # ( 
// !\A_SPW_TOP|SPW|FSM|after850ns [5] & ( \A_SPW_TOP|SPW|FSM|Add2~5_sumout  & ( (\A_SPW_TOP|SPW|FSM|state_fsm.run~q  & (!\A_SPW_TOP|SPW|FSM|got_bit_internal~q  & (\A_SPW_TOP|SPW|FSM|always5~1_combout  & !\db_system_spwulight_b|aux_pb~q ))) ) ) ) # ( 
// \A_SPW_TOP|SPW|FSM|after850ns [5] & ( !\A_SPW_TOP|SPW|FSM|Add2~5_sumout  & ( (\A_SPW_TOP|SPW|FSM|state_fsm.run~q  & (!\A_SPW_TOP|SPW|FSM|got_bit_internal~q  & (!\A_SPW_TOP|SPW|FSM|always5~1_combout  & !\db_system_spwulight_b|aux_pb~q ))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|state_fsm.run~q ),
        .datab(!\A_SPW_TOP|SPW|FSM|got_bit_internal~q ),
        .datac(!\A_SPW_TOP|SPW|FSM|always5~1_combout ),
        .datad(!\db_system_spwulight_b|aux_pb~q ),
        .datae(!\A_SPW_TOP|SPW|FSM|after850ns [5]),
        .dataf(!\A_SPW_TOP|SPW|FSM|Add2~5_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|after850ns~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after850ns~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after850ns~1 .lut_mask = 64'h0000400004004400;
defparam \A_SPW_TOP|SPW|FSM|after850ns~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y6_N17
dffeas \A_SPW_TOP|SPW|FSM|after850ns[5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|FSM|after850ns~1_combout ),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|FSM|after850ns [5]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after850ns[5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after850ns[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y6_N18
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add2~13 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add2~13_sumout  = SUM(( \A_SPW_TOP|SPW|FSM|after850ns [6] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add2~6  ))
// \A_SPW_TOP|SPW|FSM|Add2~14  = CARRY(( \A_SPW_TOP|SPW|FSM|after850ns [6] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add2~6  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|FSM|after850ns [6]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\A_SPW_TOP|SPW|FSM|Add2~6 ),
        .sharein(gnd),
        .combout(),
        .sumout(\A_SPW_TOP|SPW|FSM|Add2~13_sumout ),
        .cout(\A_SPW_TOP|SPW|FSM|Add2~14 ),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add2~13 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add2~13 .lut_mask = 64'h0000FFFF00000F0F;
defparam \A_SPW_TOP|SPW|FSM|Add2~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y6_N42
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after850ns~3 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after850ns~3_combout  = ( \A_SPW_TOP|SPW|FSM|after850ns [6] & ( \A_SPW_TOP|SPW|FSM|Add2~13_sumout  & ( (!\A_SPW_TOP|SPW|FSM|got_bit_internal~q  & (\A_SPW_TOP|SPW|FSM|state_fsm.run~q  & !\db_system_spwulight_b|aux_pb~q )) ) ) ) # ( 
// !\A_SPW_TOP|SPW|FSM|after850ns [6] & ( \A_SPW_TOP|SPW|FSM|Add2~13_sumout  & ( (!\A_SPW_TOP|SPW|FSM|got_bit_internal~q  & (\A_SPW_TOP|SPW|FSM|state_fsm.run~q  & (!\db_system_spwulight_b|aux_pb~q  & \A_SPW_TOP|SPW|FSM|always5~1_combout ))) ) ) ) # ( 
// \A_SPW_TOP|SPW|FSM|after850ns [6] & ( !\A_SPW_TOP|SPW|FSM|Add2~13_sumout  & ( (!\A_SPW_TOP|SPW|FSM|got_bit_internal~q  & (\A_SPW_TOP|SPW|FSM|state_fsm.run~q  & (!\db_system_spwulight_b|aux_pb~q  & !\A_SPW_TOP|SPW|FSM|always5~1_combout ))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|got_bit_internal~q ),
        .datab(!\A_SPW_TOP|SPW|FSM|state_fsm.run~q ),
        .datac(!\db_system_spwulight_b|aux_pb~q ),
        .datad(!\A_SPW_TOP|SPW|FSM|always5~1_combout ),
        .datae(!\A_SPW_TOP|SPW|FSM|after850ns [6]),
        .dataf(!\A_SPW_TOP|SPW|FSM|Add2~13_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|after850ns~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after850ns~3 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after850ns~3 .lut_mask = 64'h0000200000202020;
defparam \A_SPW_TOP|SPW|FSM|after850ns~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y6_N20
dffeas \A_SPW_TOP|SPW|FSM|after850ns[6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|FSM|after850ns~3_combout ),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|FSM|after850ns [6]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after850ns[6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after850ns[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y6_N57
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|LessThan2~1 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|LessThan2~1_combout  = ( \A_SPW_TOP|SPW|FSM|after850ns [5] & ( \A_SPW_TOP|SPW|FSM|after850ns [6] ) ) # ( !\A_SPW_TOP|SPW|FSM|after850ns [5] & ( (\A_SPW_TOP|SPW|FSM|after850ns [6] & \A_SPW_TOP|SPW|FSM|after850ns [4]) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|after850ns [6]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\A_SPW_TOP|SPW|FSM|after850ns [4]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|FSM|after850ns [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|LessThan2~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|LessThan2~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|LessThan2~1 .lut_mask = 64'h0055005555555555;
defparam \A_SPW_TOP|SPW|FSM|LessThan2~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y6_N21
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add2~33 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add2~33_sumout  = SUM(( \A_SPW_TOP|SPW|FSM|after850ns [7] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add2~14  ))
// \A_SPW_TOP|SPW|FSM|Add2~34  = CARRY(( \A_SPW_TOP|SPW|FSM|after850ns [7] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add2~14  ))

        .dataa(!\A_SPW_TOP|SPW|FSM|after850ns [7]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\A_SPW_TOP|SPW|FSM|Add2~14 ),
        .sharein(gnd),
        .combout(),
        .sumout(\A_SPW_TOP|SPW|FSM|Add2~33_sumout ),
        .cout(\A_SPW_TOP|SPW|FSM|Add2~34 ),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add2~33 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add2~33 .lut_mask = 64'h0000FFFF00005555;
defparam \A_SPW_TOP|SPW|FSM|Add2~33 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y6_N48
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after850ns~8 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after850ns~8_combout  = ( \A_SPW_TOP|SPW|FSM|after850ns [7] & ( \A_SPW_TOP|SPW|FSM|Add2~33_sumout  & ( (!\A_SPW_TOP|SPW|FSM|got_bit_internal~q  & (\A_SPW_TOP|SPW|FSM|state_fsm.run~q  & !\db_system_spwulight_b|aux_pb~q )) ) ) ) # ( 
// !\A_SPW_TOP|SPW|FSM|after850ns [7] & ( \A_SPW_TOP|SPW|FSM|Add2~33_sumout  & ( (!\A_SPW_TOP|SPW|FSM|got_bit_internal~q  & (\A_SPW_TOP|SPW|FSM|state_fsm.run~q  & (!\db_system_spwulight_b|aux_pb~q  & \A_SPW_TOP|SPW|FSM|always5~1_combout ))) ) ) ) # ( 
// \A_SPW_TOP|SPW|FSM|after850ns [7] & ( !\A_SPW_TOP|SPW|FSM|Add2~33_sumout  & ( (!\A_SPW_TOP|SPW|FSM|got_bit_internal~q  & (\A_SPW_TOP|SPW|FSM|state_fsm.run~q  & !\db_system_spwulight_b|aux_pb~q )) ) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|got_bit_internal~q ),
        .datab(!\A_SPW_TOP|SPW|FSM|state_fsm.run~q ),
        .datac(!\db_system_spwulight_b|aux_pb~q ),
        .datad(!\A_SPW_TOP|SPW|FSM|always5~1_combout ),
        .datae(!\A_SPW_TOP|SPW|FSM|after850ns [7]),
        .dataf(!\A_SPW_TOP|SPW|FSM|Add2~33_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|after850ns~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after850ns~8 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after850ns~8 .lut_mask = 64'h0000202000202020;
defparam \A_SPW_TOP|SPW|FSM|after850ns~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y6_N23
dffeas \A_SPW_TOP|SPW|FSM|after850ns[7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|FSM|after850ns~8_combout ),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|FSM|after850ns [7]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after850ns[7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after850ns[7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y6_N24
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add2~37 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add2~37_sumout  = SUM(( \A_SPW_TOP|SPW|FSM|after850ns [8] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add2~34  ))
// \A_SPW_TOP|SPW|FSM|Add2~38  = CARRY(( \A_SPW_TOP|SPW|FSM|after850ns [8] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add2~34  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|FSM|after850ns [8]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\A_SPW_TOP|SPW|FSM|Add2~34 ),
        .sharein(gnd),
        .combout(),
        .sumout(\A_SPW_TOP|SPW|FSM|Add2~37_sumout ),
        .cout(\A_SPW_TOP|SPW|FSM|Add2~38 ),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add2~37 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add2~37 .lut_mask = 64'h0000FFFF00000F0F;
defparam \A_SPW_TOP|SPW|FSM|Add2~37 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y6_N51
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after850ns~9 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after850ns~9_combout  = ( \A_SPW_TOP|SPW|FSM|after850ns [8] & ( \A_SPW_TOP|SPW|FSM|Add2~37_sumout  & ( (!\A_SPW_TOP|SPW|FSM|got_bit_internal~q  & (\A_SPW_TOP|SPW|FSM|state_fsm.run~q  & !\db_system_spwulight_b|aux_pb~q )) ) ) ) # ( 
// !\A_SPW_TOP|SPW|FSM|after850ns [8] & ( \A_SPW_TOP|SPW|FSM|Add2~37_sumout  & ( (!\A_SPW_TOP|SPW|FSM|got_bit_internal~q  & (\A_SPW_TOP|SPW|FSM|state_fsm.run~q  & (\A_SPW_TOP|SPW|FSM|always5~1_combout  & !\db_system_spwulight_b|aux_pb~q ))) ) ) ) # ( 
// \A_SPW_TOP|SPW|FSM|after850ns [8] & ( !\A_SPW_TOP|SPW|FSM|Add2~37_sumout  & ( (!\A_SPW_TOP|SPW|FSM|got_bit_internal~q  & (\A_SPW_TOP|SPW|FSM|state_fsm.run~q  & !\db_system_spwulight_b|aux_pb~q )) ) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|got_bit_internal~q ),
        .datab(!\A_SPW_TOP|SPW|FSM|state_fsm.run~q ),
        .datac(!\A_SPW_TOP|SPW|FSM|always5~1_combout ),
        .datad(!\db_system_spwulight_b|aux_pb~q ),
        .datae(!\A_SPW_TOP|SPW|FSM|after850ns [8]),
        .dataf(!\A_SPW_TOP|SPW|FSM|Add2~37_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|after850ns~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after850ns~9 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after850ns~9 .lut_mask = 64'h0000220002002200;
defparam \A_SPW_TOP|SPW|FSM|after850ns~9 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y6_N26
dffeas \A_SPW_TOP|SPW|FSM|after850ns[8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|FSM|after850ns~9_combout ),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|FSM|after850ns [8]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after850ns[8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after850ns[8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y6_N27
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add2~41 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add2~41_sumout  = SUM(( \A_SPW_TOP|SPW|FSM|after850ns [9] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add2~38  ))
// \A_SPW_TOP|SPW|FSM|Add2~42  = CARRY(( \A_SPW_TOP|SPW|FSM|after850ns [9] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add2~38  ))

        .dataa(!\A_SPW_TOP|SPW|FSM|after850ns [9]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\A_SPW_TOP|SPW|FSM|Add2~38 ),
        .sharein(gnd),
        .combout(),
        .sumout(\A_SPW_TOP|SPW|FSM|Add2~41_sumout ),
        .cout(\A_SPW_TOP|SPW|FSM|Add2~42 ),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add2~41 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add2~41 .lut_mask = 64'h0000FFFF00005555;
defparam \A_SPW_TOP|SPW|FSM|Add2~41 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y6_N24
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after850ns~10 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after850ns~10_combout  = ( \A_SPW_TOP|SPW|FSM|after850ns [9] & ( \A_SPW_TOP|SPW|FSM|Add2~41_sumout  & ( (\A_SPW_TOP|SPW|FSM|state_fsm.run~q  & (!\A_SPW_TOP|SPW|FSM|got_bit_internal~q  & !\db_system_spwulight_b|aux_pb~q )) ) ) ) # ( 
// !\A_SPW_TOP|SPW|FSM|after850ns [9] & ( \A_SPW_TOP|SPW|FSM|Add2~41_sumout  & ( (\A_SPW_TOP|SPW|FSM|state_fsm.run~q  & (!\A_SPW_TOP|SPW|FSM|got_bit_internal~q  & (\A_SPW_TOP|SPW|FSM|always5~1_combout  & !\db_system_spwulight_b|aux_pb~q ))) ) ) ) # ( 
// \A_SPW_TOP|SPW|FSM|after850ns [9] & ( !\A_SPW_TOP|SPW|FSM|Add2~41_sumout  & ( (\A_SPW_TOP|SPW|FSM|state_fsm.run~q  & (!\A_SPW_TOP|SPW|FSM|got_bit_internal~q  & !\db_system_spwulight_b|aux_pb~q )) ) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|state_fsm.run~q ),
        .datab(!\A_SPW_TOP|SPW|FSM|got_bit_internal~q ),
        .datac(!\A_SPW_TOP|SPW|FSM|always5~1_combout ),
        .datad(!\db_system_spwulight_b|aux_pb~q ),
        .datae(!\A_SPW_TOP|SPW|FSM|after850ns [9]),
        .dataf(!\A_SPW_TOP|SPW|FSM|Add2~41_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|after850ns~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after850ns~10 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after850ns~10 .lut_mask = 64'h0000440004004400;
defparam \A_SPW_TOP|SPW|FSM|after850ns~10 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y6_N29
dffeas \A_SPW_TOP|SPW|FSM|after850ns[9] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|FSM|after850ns~10_combout ),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|FSM|after850ns [9]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after850ns[9] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after850ns[9] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y6_N30
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add2~45 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add2~45_sumout  = SUM(( \A_SPW_TOP|SPW|FSM|after850ns [10] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add2~42  ))
// \A_SPW_TOP|SPW|FSM|Add2~46  = CARRY(( \A_SPW_TOP|SPW|FSM|after850ns [10] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add2~42  ))

        .dataa(gnd),
        .datab(!\A_SPW_TOP|SPW|FSM|after850ns [10]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\A_SPW_TOP|SPW|FSM|Add2~42 ),
        .sharein(gnd),
        .combout(),
        .sumout(\A_SPW_TOP|SPW|FSM|Add2~45_sumout ),
        .cout(\A_SPW_TOP|SPW|FSM|Add2~46 ),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add2~45 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add2~45 .lut_mask = 64'h0000FFFF00003333;
defparam \A_SPW_TOP|SPW|FSM|Add2~45 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y6_N27
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after850ns~11 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after850ns~11_combout  = ( \A_SPW_TOP|SPW|FSM|after850ns [10] & ( \A_SPW_TOP|SPW|FSM|Add2~45_sumout  & ( (\A_SPW_TOP|SPW|FSM|state_fsm.run~q  & (!\A_SPW_TOP|SPW|FSM|got_bit_internal~q  & !\db_system_spwulight_b|aux_pb~q )) ) ) ) # ( 
// !\A_SPW_TOP|SPW|FSM|after850ns [10] & ( \A_SPW_TOP|SPW|FSM|Add2~45_sumout  & ( (\A_SPW_TOP|SPW|FSM|state_fsm.run~q  & (!\A_SPW_TOP|SPW|FSM|got_bit_internal~q  & (!\db_system_spwulight_b|aux_pb~q  & \A_SPW_TOP|SPW|FSM|always5~1_combout ))) ) ) ) # ( 
// \A_SPW_TOP|SPW|FSM|after850ns [10] & ( !\A_SPW_TOP|SPW|FSM|Add2~45_sumout  & ( (\A_SPW_TOP|SPW|FSM|state_fsm.run~q  & (!\A_SPW_TOP|SPW|FSM|got_bit_internal~q  & !\db_system_spwulight_b|aux_pb~q )) ) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|state_fsm.run~q ),
        .datab(!\A_SPW_TOP|SPW|FSM|got_bit_internal~q ),
        .datac(!\db_system_spwulight_b|aux_pb~q ),
        .datad(!\A_SPW_TOP|SPW|FSM|always5~1_combout ),
        .datae(!\A_SPW_TOP|SPW|FSM|after850ns [10]),
        .dataf(!\A_SPW_TOP|SPW|FSM|Add2~45_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|after850ns~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after850ns~11 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after850ns~11 .lut_mask = 64'h0000404000404040;
defparam \A_SPW_TOP|SPW|FSM|after850ns~11 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y6_N32
dffeas \A_SPW_TOP|SPW|FSM|after850ns[10] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|FSM|after850ns~11_combout ),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|FSM|after850ns [10]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after850ns[10] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after850ns[10] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y6_N39
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Equal1~1 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Equal1~1_combout  = ( !\A_SPW_TOP|SPW|FSM|after850ns [7] & ( (!\A_SPW_TOP|SPW|FSM|after850ns [8] & (!\A_SPW_TOP|SPW|FSM|after850ns [10] & !\A_SPW_TOP|SPW|FSM|after850ns [9])) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|after850ns [8]),
        .datab(!\A_SPW_TOP|SPW|FSM|after850ns [10]),
        .datac(!\A_SPW_TOP|SPW|FSM|after850ns [9]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|FSM|after850ns [7]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|Equal1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Equal1~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Equal1~1 .lut_mask = 64'h8080808000000000;
defparam \A_SPW_TOP|SPW|FSM|Equal1~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y6_N54
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|always5~1 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|always5~1_combout  = ( \A_SPW_TOP|SPW|FSM|Equal1~1_combout  & ( (\A_SPW_TOP|SPW|FSM|state_fsm.run~q  & (!\A_SPW_TOP|SPW|FSM|after850ns [11] & ((!\A_SPW_TOP|SPW|FSM|LessThan2~1_combout ) # (\A_SPW_TOP|SPW|FSM|LessThan2~0_combout )))) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|LessThan2~0_combout ),
        .datab(!\A_SPW_TOP|SPW|FSM|LessThan2~1_combout ),
        .datac(!\A_SPW_TOP|SPW|FSM|state_fsm.run~q ),
        .datad(!\A_SPW_TOP|SPW|FSM|after850ns [11]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|FSM|Equal1~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|always5~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|always5~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|always5~1 .lut_mask = 64'h000000000D000D00;
defparam \A_SPW_TOP|SPW|FSM|always5~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y6_N45
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after850ns~5 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after850ns~5_combout  = ( \A_SPW_TOP|SPW|FSM|after850ns [2] & ( \A_SPW_TOP|SPW|FSM|Add2~21_sumout  & ( (\A_SPW_TOP|SPW|FSM|state_fsm.run~q  & (!\A_SPW_TOP|SPW|FSM|got_bit_internal~q  & !\db_system_spwulight_b|aux_pb~q )) ) ) ) # ( 
// !\A_SPW_TOP|SPW|FSM|after850ns [2] & ( \A_SPW_TOP|SPW|FSM|Add2~21_sumout  & ( (\A_SPW_TOP|SPW|FSM|state_fsm.run~q  & (!\A_SPW_TOP|SPW|FSM|got_bit_internal~q  & (!\db_system_spwulight_b|aux_pb~q  & \A_SPW_TOP|SPW|FSM|always5~1_combout ))) ) ) ) # ( 
// \A_SPW_TOP|SPW|FSM|after850ns [2] & ( !\A_SPW_TOP|SPW|FSM|Add2~21_sumout  & ( (\A_SPW_TOP|SPW|FSM|state_fsm.run~q  & (!\A_SPW_TOP|SPW|FSM|got_bit_internal~q  & (!\db_system_spwulight_b|aux_pb~q  & !\A_SPW_TOP|SPW|FSM|always5~1_combout ))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|state_fsm.run~q ),
        .datab(!\A_SPW_TOP|SPW|FSM|got_bit_internal~q ),
        .datac(!\db_system_spwulight_b|aux_pb~q ),
        .datad(!\A_SPW_TOP|SPW|FSM|always5~1_combout ),
        .datae(!\A_SPW_TOP|SPW|FSM|after850ns [2]),
        .dataf(!\A_SPW_TOP|SPW|FSM|Add2~21_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|after850ns~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after850ns~5 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after850ns~5 .lut_mask = 64'h0000400000404040;
defparam \A_SPW_TOP|SPW|FSM|after850ns~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y6_N8
dffeas \A_SPW_TOP|SPW|FSM|after850ns[2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|FSM|after850ns~5_combout ),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|FSM|after850ns [2]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after850ns[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after850ns[2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y6_N18
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|LessThan2~0 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|LessThan2~0_combout  = ( \A_SPW_TOP|SPW|FSM|after850ns [1] & ( (!\A_SPW_TOP|SPW|FSM|after850ns [2] & (!\A_SPW_TOP|SPW|FSM|after850ns [3] & !\A_SPW_TOP|SPW|FSM|after850ns [5])) ) ) # ( !\A_SPW_TOP|SPW|FSM|after850ns [1] & ( 
// (!\A_SPW_TOP|SPW|FSM|after850ns [3] & (!\A_SPW_TOP|SPW|FSM|after850ns [5] & ((!\A_SPW_TOP|SPW|FSM|after850ns [2]) # (!\A_SPW_TOP|SPW|FSM|after850ns [0])))) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|after850ns [2]),
        .datab(!\A_SPW_TOP|SPW|FSM|after850ns [0]),
        .datac(!\A_SPW_TOP|SPW|FSM|after850ns [3]),
        .datad(!\A_SPW_TOP|SPW|FSM|after850ns [5]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|FSM|after850ns [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|LessThan2~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|LessThan2~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|LessThan2~0 .lut_mask = 64'hE000E000A000A000;
defparam \A_SPW_TOP|SPW|FSM|LessThan2~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y6_N57
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|always5~0 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|always5~0_combout  = ( \A_SPW_TOP|SPW|FSM|Equal1~1_combout  & ( (!\A_SPW_TOP|SPW|FSM|LessThan2~1_combout ) # (\A_SPW_TOP|SPW|FSM|LessThan2~0_combout ) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|LessThan2~0_combout ),
        .datab(!\A_SPW_TOP|SPW|FSM|LessThan2~1_combout ),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|FSM|Equal1~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|always5~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|always5~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|always5~0 .lut_mask = 64'h00000000DDDDDDDD;
defparam \A_SPW_TOP|SPW|FSM|always5~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y6_N33
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add2~1 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add2~1_sumout  = SUM(( \A_SPW_TOP|SPW|FSM|after850ns [11] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add2~46  ))

        .dataa(!\A_SPW_TOP|SPW|FSM|after850ns [11]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\A_SPW_TOP|SPW|FSM|Add2~46 ),
        .sharein(gnd),
        .combout(),
        .sumout(\A_SPW_TOP|SPW|FSM|Add2~1_sumout ),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add2~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add2~1 .lut_mask = 64'h0000FFFF00005555;
defparam \A_SPW_TOP|SPW|FSM|Add2~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y6_N0
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after850ns~0 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after850ns~0_combout  = ( \A_SPW_TOP|SPW|FSM|Add2~1_sumout  & ( !\A_SPW_TOP|SPW|FSM|got_bit_internal~q  & ( (\A_SPW_TOP|SPW|FSM|state_fsm.run~q  & (!\db_system_spwulight_b|aux_pb~q  & ((\A_SPW_TOP|SPW|FSM|after850ns [11]) # 
// (\A_SPW_TOP|SPW|FSM|always5~0_combout )))) ) ) ) # ( !\A_SPW_TOP|SPW|FSM|Add2~1_sumout  & ( !\A_SPW_TOP|SPW|FSM|got_bit_internal~q  & ( (\A_SPW_TOP|SPW|FSM|state_fsm.run~q  & (\A_SPW_TOP|SPW|FSM|after850ns [11] & !\db_system_spwulight_b|aux_pb~q )) ) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|state_fsm.run~q ),
        .datab(!\A_SPW_TOP|SPW|FSM|always5~0_combout ),
        .datac(!\A_SPW_TOP|SPW|FSM|after850ns [11]),
        .datad(!\db_system_spwulight_b|aux_pb~q ),
        .datae(!\A_SPW_TOP|SPW|FSM|Add2~1_sumout ),
        .dataf(!\A_SPW_TOP|SPW|FSM|got_bit_internal~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|after850ns~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after850ns~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after850ns~0 .lut_mask = 64'h0500150000000000;
defparam \A_SPW_TOP|SPW|FSM|after850ns~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y6_N2
dffeas \A_SPW_TOP|SPW|FSM|after850ns[11] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|FSM|after850ns~0_combout ),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|FSM|after850ns [11]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after850ns[11] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after850ns[11] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y6_N54
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Equal1~0 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Equal1~0_combout  = ( \A_SPW_TOP|SPW|FSM|after850ns [2] & ( (\A_SPW_TOP|SPW|FSM|after850ns [6] & (\A_SPW_TOP|SPW|FSM|after850ns [4] & (\A_SPW_TOP|SPW|FSM|after850ns [0] & !\A_SPW_TOP|SPW|FSM|after850ns [1]))) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|after850ns [6]),
        .datab(!\A_SPW_TOP|SPW|FSM|after850ns [4]),
        .datac(!\A_SPW_TOP|SPW|FSM|after850ns [0]),
        .datad(!\A_SPW_TOP|SPW|FSM|after850ns [1]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|FSM|after850ns [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|Equal1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Equal1~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Equal1~0 .lut_mask = 64'h0000000001000100;
defparam \A_SPW_TOP|SPW|FSM|Equal1~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y6_N51
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Equal1~2 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Equal1~2_combout  = ( !\A_SPW_TOP|SPW|FSM|after850ns [5] & ( \A_SPW_TOP|SPW|FSM|Equal1~0_combout  & ( (!\A_SPW_TOP|SPW|FSM|after850ns [11] & (\A_SPW_TOP|SPW|FSM|Equal1~1_combout  & !\A_SPW_TOP|SPW|FSM|after850ns [3])) ) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|after850ns [11]),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|FSM|Equal1~1_combout ),
        .datad(!\A_SPW_TOP|SPW|FSM|after850ns [3]),
        .datae(!\A_SPW_TOP|SPW|FSM|after850ns [5]),
        .dataf(!\A_SPW_TOP|SPW|FSM|Equal1~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|Equal1~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Equal1~2 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Equal1~2 .lut_mask = 64'h000000000A000000;
defparam \A_SPW_TOP|SPW|FSM|Equal1~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y4_N57
cyclonev_lcell_comb \A_SPW_TOP|rx_data|credit_counter_write[0]~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|credit_counter_write[0]~0_combout  = ( !\A_SPW_TOP|rx_data|credit_counter_write [0] )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|credit_counter_write [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|credit_counter_write[0]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|credit_counter_write[0]~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|credit_counter_write[0]~0 .lut_mask = 64'hFFFFFFFF00000000;
defparam \A_SPW_TOP|rx_data|credit_counter_write[0]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y4_N14
dffeas \A_SPW_TOP|rx_data|credit_counter_write[0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|credit_counter_write[0]~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|rx_data|state_data_write.10~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|credit_counter_write [0]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|credit_counter_write[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|credit_counter_write[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y4_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Add2~2 (
// Equation(s):
// \A_SPW_TOP|rx_data|Add2~2_combout  = !\A_SPW_TOP|rx_data|credit_counter_write [0] $ (!\A_SPW_TOP|rx_data|credit_counter_write [1])

        .dataa(!\A_SPW_TOP|rx_data|credit_counter_write [0]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\A_SPW_TOP|rx_data|credit_counter_write [1]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Add2~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Add2~2 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Add2~2 .lut_mask = 64'h55AA55AA55AA55AA;
defparam \A_SPW_TOP|rx_data|Add2~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y4_N2
dffeas \A_SPW_TOP|rx_data|credit_counter_write[1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Add2~2_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|rx_data|state_data_write.10~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|credit_counter_write [1]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|credit_counter_write[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|credit_counter_write[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y4_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Add2~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Add2~1_combout  = ( \A_SPW_TOP|rx_data|credit_counter_write [2] & ( (!\A_SPW_TOP|rx_data|credit_counter_write [0]) # (!\A_SPW_TOP|rx_data|credit_counter_write [1]) ) ) # ( !\A_SPW_TOP|rx_data|credit_counter_write [2] & ( 
// (\A_SPW_TOP|rx_data|credit_counter_write [0] & \A_SPW_TOP|rx_data|credit_counter_write [1]) ) )

        .dataa(!\A_SPW_TOP|rx_data|credit_counter_write [0]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\A_SPW_TOP|rx_data|credit_counter_write [1]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|credit_counter_write [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Add2~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Add2~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Add2~1 .lut_mask = 64'h00550055FFAAFFAA;
defparam \A_SPW_TOP|rx_data|Add2~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y4_N17
dffeas \A_SPW_TOP|rx_data|credit_counter_write[2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Add2~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|rx_data|state_data_write.10~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|credit_counter_write [2]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|credit_counter_write[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|credit_counter_write[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y5_N9
cyclonev_lcell_comb \A_SPW_TOP|rx_data|credit_counter_reader~4 (
// Equation(s):
// \A_SPW_TOP|rx_data|credit_counter_reader~4_combout  = ( \A_SPW_TOP|rx_data|always3~0_combout  & ( !\A_SPW_TOP|rx_data|credit_counter_reader [0] $ (!\A_SPW_TOP|rx_data|LessThan0~0_combout ) ) ) # ( !\A_SPW_TOP|rx_data|always3~0_combout  & ( 
// \A_SPW_TOP|rx_data|credit_counter_reader [0] ) )

        .dataa(!\A_SPW_TOP|rx_data|credit_counter_reader [0]),
        .datab(gnd),
        .datac(!\A_SPW_TOP|rx_data|LessThan0~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|always3~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|credit_counter_reader~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|credit_counter_reader~4 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|credit_counter_reader~4 .lut_mask = 64'h555555555A5A5A5A;
defparam \A_SPW_TOP|rx_data|credit_counter_reader~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y5_N56
dffeas \A_SPW_TOP|rx_data|credit_counter_reader[0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|credit_counter_reader~4_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|rx_data|always5~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|credit_counter_reader [0]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|credit_counter_reader[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|credit_counter_reader[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y5_N27
cyclonev_lcell_comb \A_SPW_TOP|rx_data|credit_counter_reader~3 (
// Equation(s):
// \A_SPW_TOP|rx_data|credit_counter_reader~3_combout  = ( \A_SPW_TOP|rx_data|credit_counter_reader [0] & ( \A_SPW_TOP|rx_data|always3~0_combout  & ( \A_SPW_TOP|rx_data|credit_counter_reader [1] ) ) ) # ( !\A_SPW_TOP|rx_data|credit_counter_reader [0] & ( 
// \A_SPW_TOP|rx_data|always3~0_combout  & ( !\A_SPW_TOP|rx_data|LessThan0~0_combout  $ (!\A_SPW_TOP|rx_data|credit_counter_reader [1]) ) ) ) # ( \A_SPW_TOP|rx_data|credit_counter_reader [0] & ( !\A_SPW_TOP|rx_data|always3~0_combout  & ( 
// \A_SPW_TOP|rx_data|credit_counter_reader [1] ) ) ) # ( !\A_SPW_TOP|rx_data|credit_counter_reader [0] & ( !\A_SPW_TOP|rx_data|always3~0_combout  & ( \A_SPW_TOP|rx_data|credit_counter_reader [1] ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|rx_data|LessThan0~0_combout ),
        .datac(!\A_SPW_TOP|rx_data|credit_counter_reader [1]),
        .datad(gnd),
        .datae(!\A_SPW_TOP|rx_data|credit_counter_reader [0]),
        .dataf(!\A_SPW_TOP|rx_data|always3~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|credit_counter_reader~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|credit_counter_reader~3 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|credit_counter_reader~3 .lut_mask = 64'h0F0F0F0F3C3C0F0F;
defparam \A_SPW_TOP|rx_data|credit_counter_reader~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y5_N47
dffeas \A_SPW_TOP|rx_data|credit_counter_reader[1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|credit_counter_reader~3_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|rx_data|always5~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|credit_counter_reader [1]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|credit_counter_reader[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|credit_counter_reader[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y5_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|credit_counter_reader~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|credit_counter_reader~0_combout  = (!\A_SPW_TOP|rx_data|credit_counter_reader [0] & (!\A_SPW_TOP|rx_data|credit_counter_reader [2] & !\A_SPW_TOP|rx_data|credit_counter_reader [1]))

        .dataa(!\A_SPW_TOP|rx_data|credit_counter_reader [0]),
        .datab(gnd),
        .datac(!\A_SPW_TOP|rx_data|credit_counter_reader [2]),
        .datad(!\A_SPW_TOP|rx_data|credit_counter_reader [1]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|credit_counter_reader~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|credit_counter_reader~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|credit_counter_reader~0 .lut_mask = 64'hA000A000A000A000;
defparam \A_SPW_TOP|rx_data|credit_counter_reader~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y4_N51
cyclonev_lcell_comb \A_SPW_TOP|rx_data|credit_counter_reader~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|credit_counter_reader~1_combout  = ( \A_SPW_TOP|rx_data|credit_counter_reader [3] & ( (!\A_SPW_TOP|rx_data|always3~0_combout ) # ((\A_SPW_TOP|rx_data|credit_counter_reader~0_combout  & \A_SPW_TOP|rx_data|LessThan0~0_combout )) ) ) # ( 
// !\A_SPW_TOP|rx_data|credit_counter_reader [3] & ( (\A_SPW_TOP|rx_data|always3~0_combout  & ((!\A_SPW_TOP|rx_data|credit_counter_reader~0_combout ) # (!\A_SPW_TOP|rx_data|LessThan0~0_combout ))) ) )

        .dataa(!\A_SPW_TOP|rx_data|always3~0_combout ),
        .datab(!\A_SPW_TOP|rx_data|credit_counter_reader~0_combout ),
        .datac(gnd),
        .datad(!\A_SPW_TOP|rx_data|LessThan0~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|credit_counter_reader [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|credit_counter_reader~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|credit_counter_reader~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|credit_counter_reader~1 .lut_mask = 64'h55445544AABBAABB;
defparam \A_SPW_TOP|rx_data|credit_counter_reader~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y4_N50
dffeas \A_SPW_TOP|rx_data|credit_counter_reader[3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|credit_counter_reader~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|rx_data|always5~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|credit_counter_reader [3]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|credit_counter_reader[3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|credit_counter_reader[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y4_N15
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Add2~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Add2~0_combout  = !\A_SPW_TOP|rx_data|credit_counter_write [3] $ (((!\A_SPW_TOP|rx_data|credit_counter_write [1]) # ((!\A_SPW_TOP|rx_data|credit_counter_write [0]) # (!\A_SPW_TOP|rx_data|credit_counter_write [2]))))

        .dataa(!\A_SPW_TOP|rx_data|credit_counter_write [1]),
        .datab(!\A_SPW_TOP|rx_data|credit_counter_write [3]),
        .datac(!\A_SPW_TOP|rx_data|credit_counter_write [0]),
        .datad(!\A_SPW_TOP|rx_data|credit_counter_write [2]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Add2~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Add2~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Add2~0 .lut_mask = 64'h3336333633363336;
defparam \A_SPW_TOP|rx_data|Add2~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y4_N59
dffeas \A_SPW_TOP|rx_data|credit_counter_write[3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Add2~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|rx_data|state_data_write.10~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|credit_counter_write [3]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|credit_counter_write[3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|credit_counter_write[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y4_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Add5~13 (
// Equation(s):
// \A_SPW_TOP|rx_data|Add5~13_sumout  = SUM(( !\A_SPW_TOP|rx_data|credit_counter_reader [0] $ (!\A_SPW_TOP|rx_data|credit_counter_write [0]) ) + ( !VCC ) + ( !VCC ))
// \A_SPW_TOP|rx_data|Add5~14  = CARRY(( !\A_SPW_TOP|rx_data|credit_counter_reader [0] $ (!\A_SPW_TOP|rx_data|credit_counter_write [0]) ) + ( !VCC ) + ( !VCC ))
// \A_SPW_TOP|rx_data|Add5~15  = SHARE((!\A_SPW_TOP|rx_data|credit_counter_write [0]) # (\A_SPW_TOP|rx_data|credit_counter_reader [0]))

        .dataa(gnd),
        .datab(!\A_SPW_TOP|rx_data|credit_counter_reader [0]),
        .datac(gnd),
        .datad(!\A_SPW_TOP|rx_data|credit_counter_write [0]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(),
        .sumout(\A_SPW_TOP|rx_data|Add5~13_sumout ),
        .cout(\A_SPW_TOP|rx_data|Add5~14 ),
        .shareout(\A_SPW_TOP|rx_data|Add5~15 ));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Add5~13 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Add5~13 .lut_mask = 64'h0000FF33000033CC;
defparam \A_SPW_TOP|rx_data|Add5~13 .shared_arith = "on";
// synopsys translate_on

// Location: LABCELL_X46_Y4_N33
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Add5~9 (
// Equation(s):
// \A_SPW_TOP|rx_data|Add5~9_sumout  = SUM(( !\A_SPW_TOP|rx_data|credit_counter_reader [1] $ (\A_SPW_TOP|rx_data|credit_counter_write [1]) ) + ( \A_SPW_TOP|rx_data|Add5~15  ) + ( \A_SPW_TOP|rx_data|Add5~14  ))
// \A_SPW_TOP|rx_data|Add5~10  = CARRY(( !\A_SPW_TOP|rx_data|credit_counter_reader [1] $ (\A_SPW_TOP|rx_data|credit_counter_write [1]) ) + ( \A_SPW_TOP|rx_data|Add5~15  ) + ( \A_SPW_TOP|rx_data|Add5~14  ))
// \A_SPW_TOP|rx_data|Add5~11  = SHARE((\A_SPW_TOP|rx_data|credit_counter_reader [1] & !\A_SPW_TOP|rx_data|credit_counter_write [1]))

        .dataa(!\A_SPW_TOP|rx_data|credit_counter_reader [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\A_SPW_TOP|rx_data|credit_counter_write [1]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\A_SPW_TOP|rx_data|Add5~14 ),
        .sharein(\A_SPW_TOP|rx_data|Add5~15 ),
        .combout(),
        .sumout(\A_SPW_TOP|rx_data|Add5~9_sumout ),
        .cout(\A_SPW_TOP|rx_data|Add5~10 ),
        .shareout(\A_SPW_TOP|rx_data|Add5~11 ));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Add5~9 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Add5~9 .lut_mask = 64'h000055000000AA55;
defparam \A_SPW_TOP|rx_data|Add5~9 .shared_arith = "on";
// synopsys translate_on

// Location: LABCELL_X46_Y4_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Add5~5 (
// Equation(s):
// \A_SPW_TOP|rx_data|Add5~5_sumout  = SUM(( !\A_SPW_TOP|rx_data|credit_counter_write [2] $ (\A_SPW_TOP|rx_data|credit_counter_reader [2]) ) + ( \A_SPW_TOP|rx_data|Add5~11  ) + ( \A_SPW_TOP|rx_data|Add5~10  ))
// \A_SPW_TOP|rx_data|Add5~6  = CARRY(( !\A_SPW_TOP|rx_data|credit_counter_write [2] $ (\A_SPW_TOP|rx_data|credit_counter_reader [2]) ) + ( \A_SPW_TOP|rx_data|Add5~11  ) + ( \A_SPW_TOP|rx_data|Add5~10  ))
// \A_SPW_TOP|rx_data|Add5~7  = SHARE((!\A_SPW_TOP|rx_data|credit_counter_write [2] & \A_SPW_TOP|rx_data|credit_counter_reader [2]))

        .dataa(gnd),
        .datab(!\A_SPW_TOP|rx_data|credit_counter_write [2]),
        .datac(!\A_SPW_TOP|rx_data|credit_counter_reader [2]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\A_SPW_TOP|rx_data|Add5~10 ),
        .sharein(\A_SPW_TOP|rx_data|Add5~11 ),
        .combout(),
        .sumout(\A_SPW_TOP|rx_data|Add5~5_sumout ),
        .cout(\A_SPW_TOP|rx_data|Add5~6 ),
        .shareout(\A_SPW_TOP|rx_data|Add5~7 ));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Add5~5 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Add5~5 .lut_mask = 64'h00000C0C0000C3C3;
defparam \A_SPW_TOP|rx_data|Add5~5 .shared_arith = "on";
// synopsys translate_on

// Location: LABCELL_X46_Y4_N39
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Add5~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Add5~1_sumout  = SUM(( !\A_SPW_TOP|rx_data|credit_counter_reader [3] $ (!\A_SPW_TOP|rx_data|credit_counter_write [3]) ) + ( \A_SPW_TOP|rx_data|Add5~7  ) + ( \A_SPW_TOP|rx_data|Add5~6  ))
// \A_SPW_TOP|rx_data|Add5~2  = CARRY(( !\A_SPW_TOP|rx_data|credit_counter_reader [3] $ (!\A_SPW_TOP|rx_data|credit_counter_write [3]) ) + ( \A_SPW_TOP|rx_data|Add5~7  ) + ( \A_SPW_TOP|rx_data|Add5~6  ))
// \A_SPW_TOP|rx_data|Add5~3  = SHARE((!\A_SPW_TOP|rx_data|credit_counter_reader [3] & !\A_SPW_TOP|rx_data|credit_counter_write [3]))

        .dataa(!\A_SPW_TOP|rx_data|credit_counter_reader [3]),
        .datab(gnd),
        .datac(!\A_SPW_TOP|rx_data|credit_counter_write [3]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\A_SPW_TOP|rx_data|Add5~6 ),
        .sharein(\A_SPW_TOP|rx_data|Add5~7 ),
        .combout(),
        .sumout(\A_SPW_TOP|rx_data|Add5~1_sumout ),
        .cout(\A_SPW_TOP|rx_data|Add5~2 ),
        .shareout(\A_SPW_TOP|rx_data|Add5~3 ));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Add5~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Add5~1 .lut_mask = 64'h0000A0A000005A5A;
defparam \A_SPW_TOP|rx_data|Add5~1 .shared_arith = "on";
// synopsys translate_on

// Location: FF_X46_Y4_N41
dffeas \A_SPW_TOP|rx_data|credit_counter[3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|rx_data|Add5~1_sumout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|credit_counter [3]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|credit_counter[3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|credit_counter[3] .power_up = "low";
// synopsys translate_on

// Location: FF_X46_Y4_N35
dffeas \A_SPW_TOP|rx_data|credit_counter[1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|rx_data|Add5~9_sumout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|credit_counter [1]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|credit_counter[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|credit_counter[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X46_Y4_N32
dffeas \A_SPW_TOP|rx_data|credit_counter[0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|rx_data|Add5~13_sumout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|credit_counter [0]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|credit_counter[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|credit_counter[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y4_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|credit_counter_reader~6 (
// Equation(s):
// \A_SPW_TOP|rx_data|credit_counter_reader~6_combout  = ( \A_SPW_TOP|rx_data|credit_counter_reader [4] & ( (!\A_SPW_TOP|rx_data|always3~0_combout ) # (((\A_SPW_TOP|rx_data|credit_counter_reader~0_combout  & \A_SPW_TOP|rx_data|LessThan0~0_combout )) # 
// (\A_SPW_TOP|rx_data|credit_counter_reader [3])) ) ) # ( !\A_SPW_TOP|rx_data|credit_counter_reader [4] & ( (\A_SPW_TOP|rx_data|always3~0_combout  & (!\A_SPW_TOP|rx_data|credit_counter_reader [3] & ((!\A_SPW_TOP|rx_data|credit_counter_reader~0_combout ) # 
// (!\A_SPW_TOP|rx_data|LessThan0~0_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|always3~0_combout ),
        .datab(!\A_SPW_TOP|rx_data|credit_counter_reader~0_combout ),
        .datac(!\A_SPW_TOP|rx_data|LessThan0~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|credit_counter_reader [3]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|credit_counter_reader [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|credit_counter_reader~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|credit_counter_reader~6 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|credit_counter_reader~6 .lut_mask = 64'h54005400ABFFABFF;
defparam \A_SPW_TOP|rx_data|credit_counter_reader~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y4_N8
dffeas \A_SPW_TOP|rx_data|credit_counter_reader[4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|credit_counter_reader~6_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|rx_data|always5~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|credit_counter_reader [4]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|credit_counter_reader[4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|credit_counter_reader[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y4_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|credit_counter_reader~5 (
// Equation(s):
// \A_SPW_TOP|rx_data|credit_counter_reader~5_combout  = ( \A_SPW_TOP|rx_data|credit_counter_reader [4] & ( \A_SPW_TOP|rx_data|credit_counter_reader [3] & ( \A_SPW_TOP|rx_data|credit_counter_reader [5] ) ) ) # ( !\A_SPW_TOP|rx_data|credit_counter_reader [4] 
// & ( \A_SPW_TOP|rx_data|credit_counter_reader [3] & ( \A_SPW_TOP|rx_data|credit_counter_reader [5] ) ) ) # ( \A_SPW_TOP|rx_data|credit_counter_reader [4] & ( !\A_SPW_TOP|rx_data|credit_counter_reader [3] & ( \A_SPW_TOP|rx_data|credit_counter_reader [5] ) ) 
// ) # ( !\A_SPW_TOP|rx_data|credit_counter_reader [4] & ( !\A_SPW_TOP|rx_data|credit_counter_reader [3] & ( !\A_SPW_TOP|rx_data|credit_counter_reader [5] $ (((!\A_SPW_TOP|rx_data|always3~0_combout ) # ((\A_SPW_TOP|rx_data|credit_counter_reader~0_combout  & 
// \A_SPW_TOP|rx_data|LessThan0~0_combout )))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|always3~0_combout ),
        .datab(!\A_SPW_TOP|rx_data|credit_counter_reader~0_combout ),
        .datac(!\A_SPW_TOP|rx_data|LessThan0~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|credit_counter_reader [5]),
        .datae(!\A_SPW_TOP|rx_data|credit_counter_reader [4]),
        .dataf(!\A_SPW_TOP|rx_data|credit_counter_reader [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|credit_counter_reader~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|credit_counter_reader~5 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|credit_counter_reader~5 .lut_mask = 64'h54AB00FF00FF00FF;
defparam \A_SPW_TOP|rx_data|credit_counter_reader~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y4_N11
dffeas \A_SPW_TOP|rx_data|credit_counter_reader[5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|credit_counter_reader~5_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|rx_data|always5~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|credit_counter_reader [5]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|credit_counter_reader[5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|credit_counter_reader[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y4_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Add2~4 (
// Equation(s):
// \A_SPW_TOP|rx_data|Add2~4_combout  = ( \A_SPW_TOP|rx_data|credit_counter_write [2] & ( !\A_SPW_TOP|rx_data|credit_counter_write [4] $ (((!\A_SPW_TOP|rx_data|credit_counter_write [1]) # ((!\A_SPW_TOP|rx_data|credit_counter_write [3]) # 
// (!\A_SPW_TOP|rx_data|credit_counter_write [0])))) ) ) # ( !\A_SPW_TOP|rx_data|credit_counter_write [2] & ( \A_SPW_TOP|rx_data|credit_counter_write [4] ) )

        .dataa(!\A_SPW_TOP|rx_data|credit_counter_write [1]),
        .datab(!\A_SPW_TOP|rx_data|credit_counter_write [3]),
        .datac(!\A_SPW_TOP|rx_data|credit_counter_write [4]),
        .datad(!\A_SPW_TOP|rx_data|credit_counter_write [0]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|credit_counter_write [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Add2~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Add2~4 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Add2~4 .lut_mask = 64'h0F0F0F0F0F1E0F1E;
defparam \A_SPW_TOP|rx_data|Add2~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y4_N20
dffeas \A_SPW_TOP|rx_data|credit_counter_write[4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Add2~4_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|rx_data|state_data_write.10~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|credit_counter_write [4]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|credit_counter_write[4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|credit_counter_write[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y4_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Add2~3 (
// Equation(s):
// \A_SPW_TOP|rx_data|Add2~3_combout  = ( \A_SPW_TOP|rx_data|credit_counter_write [4] & ( \A_SPW_TOP|rx_data|credit_counter_write [0] & ( !\A_SPW_TOP|rx_data|credit_counter_write [5] $ (((!\A_SPW_TOP|rx_data|credit_counter_write [3]) # 
// ((!\A_SPW_TOP|rx_data|credit_counter_write [1]) # (!\A_SPW_TOP|rx_data|credit_counter_write [2])))) ) ) ) # ( !\A_SPW_TOP|rx_data|credit_counter_write [4] & ( \A_SPW_TOP|rx_data|credit_counter_write [0] & ( \A_SPW_TOP|rx_data|credit_counter_write [5] ) ) 
// ) # ( \A_SPW_TOP|rx_data|credit_counter_write [4] & ( !\A_SPW_TOP|rx_data|credit_counter_write [0] & ( \A_SPW_TOP|rx_data|credit_counter_write [5] ) ) ) # ( !\A_SPW_TOP|rx_data|credit_counter_write [4] & ( !\A_SPW_TOP|rx_data|credit_counter_write [0] & ( 
// \A_SPW_TOP|rx_data|credit_counter_write [5] ) ) )

        .dataa(!\A_SPW_TOP|rx_data|credit_counter_write [5]),
        .datab(!\A_SPW_TOP|rx_data|credit_counter_write [3]),
        .datac(!\A_SPW_TOP|rx_data|credit_counter_write [1]),
        .datad(!\A_SPW_TOP|rx_data|credit_counter_write [2]),
        .datae(!\A_SPW_TOP|rx_data|credit_counter_write [4]),
        .dataf(!\A_SPW_TOP|rx_data|credit_counter_write [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Add2~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Add2~3 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Add2~3 .lut_mask = 64'h5555555555555556;
defparam \A_SPW_TOP|rx_data|Add2~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y4_N23
dffeas \A_SPW_TOP|rx_data|credit_counter_write[5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Add2~3_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|rx_data|state_data_write.10~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|credit_counter_write [5]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|credit_counter_write[5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|credit_counter_write[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y4_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Add5~21 (
// Equation(s):
// \A_SPW_TOP|rx_data|Add5~21_sumout  = SUM(( !\A_SPW_TOP|rx_data|credit_counter_write [4] $ (!\A_SPW_TOP|rx_data|credit_counter_reader [4]) ) + ( \A_SPW_TOP|rx_data|Add5~3  ) + ( \A_SPW_TOP|rx_data|Add5~2  ))
// \A_SPW_TOP|rx_data|Add5~22  = CARRY(( !\A_SPW_TOP|rx_data|credit_counter_write [4] $ (!\A_SPW_TOP|rx_data|credit_counter_reader [4]) ) + ( \A_SPW_TOP|rx_data|Add5~3  ) + ( \A_SPW_TOP|rx_data|Add5~2  ))
// \A_SPW_TOP|rx_data|Add5~23  = SHARE((!\A_SPW_TOP|rx_data|credit_counter_write [4] & !\A_SPW_TOP|rx_data|credit_counter_reader [4]))

        .dataa(!\A_SPW_TOP|rx_data|credit_counter_write [4]),
        .datab(!\A_SPW_TOP|rx_data|credit_counter_reader [4]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\A_SPW_TOP|rx_data|Add5~2 ),
        .sharein(\A_SPW_TOP|rx_data|Add5~3 ),
        .combout(),
        .sumout(\A_SPW_TOP|rx_data|Add5~21_sumout ),
        .cout(\A_SPW_TOP|rx_data|Add5~22 ),
        .shareout(\A_SPW_TOP|rx_data|Add5~23 ));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Add5~21 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Add5~21 .lut_mask = 64'h0000888800006666;
defparam \A_SPW_TOP|rx_data|Add5~21 .shared_arith = "on";
// synopsys translate_on

// Location: LABCELL_X46_Y4_N45
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Add5~17 (
// Equation(s):
// \A_SPW_TOP|rx_data|Add5~17_sumout  = SUM(( !\A_SPW_TOP|rx_data|credit_counter_reader [5] $ (!\A_SPW_TOP|rx_data|credit_counter_write [5]) ) + ( \A_SPW_TOP|rx_data|Add5~23  ) + ( \A_SPW_TOP|rx_data|Add5~22  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|rx_data|credit_counter_reader [5]),
        .datad(!\A_SPW_TOP|rx_data|credit_counter_write [5]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\A_SPW_TOP|rx_data|Add5~22 ),
        .sharein(\A_SPW_TOP|rx_data|Add5~23 ),
        .combout(),
        .sumout(\A_SPW_TOP|rx_data|Add5~17_sumout ),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Add5~17 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Add5~17 .lut_mask = 64'h0000000000000FF0;
defparam \A_SPW_TOP|rx_data|Add5~17 .shared_arith = "on";
// synopsys translate_on

// Location: FF_X46_Y4_N47
dffeas \A_SPW_TOP|rx_data|credit_counter[5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|rx_data|Add5~17_sumout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|credit_counter [5]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|credit_counter[5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|credit_counter[5] .power_up = "low";
// synopsys translate_on

// Location: FF_X46_Y4_N44
dffeas \A_SPW_TOP|rx_data|credit_counter[4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|rx_data|Add5~21_sumout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|credit_counter [4]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|credit_counter[4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|credit_counter[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y4_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|LessThan0~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|LessThan0~0_combout  = ( \A_SPW_TOP|rx_data|credit_counter [5] & ( \A_SPW_TOP|rx_data|credit_counter [4] & ( (((\A_SPW_TOP|rx_data|credit_counter [0]) # (\A_SPW_TOP|rx_data|credit_counter [1])) # (\A_SPW_TOP|rx_data|credit_counter [3])) 
// # (\A_SPW_TOP|rx_data|credit_counter [2]) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|credit_counter [2]),
        .datab(!\A_SPW_TOP|rx_data|credit_counter [3]),
        .datac(!\A_SPW_TOP|rx_data|credit_counter [1]),
        .datad(!\A_SPW_TOP|rx_data|credit_counter [0]),
        .datae(!\A_SPW_TOP|rx_data|credit_counter [5]),
        .dataf(!\A_SPW_TOP|rx_data|credit_counter [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|LessThan0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|LessThan0~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|LessThan0~0 .lut_mask = 64'h0000000000007FFF;
defparam \A_SPW_TOP|rx_data|LessThan0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y5_N57
cyclonev_lcell_comb \A_SPW_TOP|rx_data|credit_counter_reader~2 (
// Equation(s):
// \A_SPW_TOP|rx_data|credit_counter_reader~2_combout  = ( \A_SPW_TOP|rx_data|credit_counter_reader [0] & ( \A_SPW_TOP|rx_data|credit_counter_reader [2] ) ) # ( !\A_SPW_TOP|rx_data|credit_counter_reader [0] & ( !\A_SPW_TOP|rx_data|credit_counter_reader [2] $ 
// (((!\A_SPW_TOP|rx_data|always3~0_combout ) # ((!\A_SPW_TOP|rx_data|LessThan0~0_combout ) # (\A_SPW_TOP|rx_data|credit_counter_reader [1])))) ) )

        .dataa(!\A_SPW_TOP|rx_data|always3~0_combout ),
        .datab(!\A_SPW_TOP|rx_data|LessThan0~0_combout ),
        .datac(!\A_SPW_TOP|rx_data|credit_counter_reader [1]),
        .datad(!\A_SPW_TOP|rx_data|credit_counter_reader [2]),
        .datae(!\A_SPW_TOP|rx_data|credit_counter_reader [0]),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|credit_counter_reader~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|credit_counter_reader~2 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|credit_counter_reader~2 .lut_mask = 64'h10EF00FF10EF00FF;
defparam \A_SPW_TOP|rx_data|credit_counter_reader~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y5_N5
dffeas \A_SPW_TOP|rx_data|credit_counter_reader[2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|credit_counter_reader~2_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|rx_data|always5~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|credit_counter_reader [2]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|credit_counter_reader[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|credit_counter_reader[2] .power_up = "low";
// synopsys translate_on

// Location: FF_X46_Y4_N38
dffeas \A_SPW_TOP|rx_data|credit_counter[2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|rx_data|Add5~5_sumout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|credit_counter [2]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|credit_counter[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|credit_counter[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y4_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|LessThan1~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|LessThan1~0_combout  = ( \A_SPW_TOP|rx_data|credit_counter [5] & ( \A_SPW_TOP|rx_data|credit_counter [3] & ( (\A_SPW_TOP|rx_data|credit_counter [4] & (((\A_SPW_TOP|rx_data|credit_counter [0]) # (\A_SPW_TOP|rx_data|credit_counter [1])) # 
// (\A_SPW_TOP|rx_data|credit_counter [2]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|credit_counter [2]),
        .datab(!\A_SPW_TOP|rx_data|credit_counter [4]),
        .datac(!\A_SPW_TOP|rx_data|credit_counter [1]),
        .datad(!\A_SPW_TOP|rx_data|credit_counter [0]),
        .datae(!\A_SPW_TOP|rx_data|credit_counter [5]),
        .dataf(!\A_SPW_TOP|rx_data|credit_counter [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|LessThan1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|LessThan1~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|LessThan1~0 .lut_mask = 64'h0000000000001333;
defparam \A_SPW_TOP|rx_data|LessThan1~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y4_N26
dffeas \A_SPW_TOP|rx_data|overflow_credit_error (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|rx_data|LessThan1~0_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|overflow_credit_error~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|overflow_credit_error .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|overflow_credit_error .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y4_N12
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Selector0~0 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Selector0~0_combout  = ( \A_SPW_TOP|rx_data|overflow_credit_error~q  & ( \A_SPW_TOP|SPW|RX|rx_error_d~q  & ( \A_SPW_TOP|SPW|FSM|state_fsm.run~q  ) ) ) # ( !\A_SPW_TOP|rx_data|overflow_credit_error~q  & ( \A_SPW_TOP|SPW|RX|rx_error_d~q  
// & ( \A_SPW_TOP|SPW|FSM|state_fsm.run~q  ) ) ) # ( \A_SPW_TOP|rx_data|overflow_credit_error~q  & ( !\A_SPW_TOP|SPW|RX|rx_error_d~q  & ( \A_SPW_TOP|SPW|FSM|state_fsm.run~q  ) ) ) # ( !\A_SPW_TOP|rx_data|overflow_credit_error~q  & ( 
// !\A_SPW_TOP|SPW|RX|rx_error_d~q  & ( (\A_SPW_TOP|SPW|FSM|state_fsm.run~q  & (((\A_SPW_TOP|SPW|FSM|Equal1~2_combout ) # (\u0|link_disable|data_out~q )) # (\A_SPW_TOP|SPW|RX|rx_error_c~q ))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_error_c~q ),
        .datab(!\A_SPW_TOP|SPW|FSM|state_fsm.run~q ),
        .datac(!\u0|link_disable|data_out~q ),
        .datad(!\A_SPW_TOP|SPW|FSM|Equal1~2_combout ),
        .datae(!\A_SPW_TOP|rx_data|overflow_credit_error~q ),
        .dataf(!\A_SPW_TOP|SPW|RX|rx_error_d~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|Selector0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Selector0~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Selector0~0 .lut_mask = 64'h1333333333333333;
defparam \A_SPW_TOP|SPW|FSM|Selector0~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y4_N30
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|state_fsm~13 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|state_fsm~13_combout  = ( !\A_SPW_TOP|SPW|FSM|state_fsm.ready~q  & ( \A_SPW_TOP|SPW|FSM|Equal0~2_combout  & ( (!\A_SPW_TOP|SPW|FSM|state_fsm.started~q  & ((!\A_SPW_TOP|SPW|FSM|state_fsm.error_wait~q ) # 
// ((\A_SPW_TOP|SPW|FSM|Equal0~1_combout  & \A_SPW_TOP|SPW|FSM|Equal0~0_combout )))) ) ) ) # ( !\A_SPW_TOP|SPW|FSM|state_fsm.ready~q  & ( !\A_SPW_TOP|SPW|FSM|Equal0~2_combout  & ( (!\A_SPW_TOP|SPW|FSM|state_fsm.started~q  & 
// !\A_SPW_TOP|SPW|FSM|state_fsm.error_wait~q ) ) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|Equal0~1_combout ),
        .datab(!\A_SPW_TOP|SPW|FSM|state_fsm.started~q ),
        .datac(!\A_SPW_TOP|SPW|FSM|Equal0~0_combout ),
        .datad(!\A_SPW_TOP|SPW|FSM|state_fsm.error_wait~q ),
        .datae(!\A_SPW_TOP|SPW|FSM|state_fsm.ready~q ),
        .dataf(!\A_SPW_TOP|SPW|FSM|Equal0~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|state_fsm~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|state_fsm~13 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|state_fsm~13 .lut_mask = 64'hCC000000CC040000;
defparam \A_SPW_TOP|SPW|FSM|state_fsm~13 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y4_N57
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|state_fsm~14 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|state_fsm~14_combout  = ( \A_SPW_TOP|SPW|RX|rx_got_fct_fsm~q  & ( \A_SPW_TOP|SPW|RX|rx_error_d~q  & ( !\A_SPW_TOP|SPW|FSM|state_fsm~13_combout  ) ) ) # ( !\A_SPW_TOP|SPW|RX|rx_got_fct_fsm~q  & ( \A_SPW_TOP|SPW|RX|rx_error_d~q  & ( 
// !\A_SPW_TOP|SPW|FSM|state_fsm~13_combout  ) ) ) # ( \A_SPW_TOP|SPW|RX|rx_got_fct_fsm~q  & ( !\A_SPW_TOP|SPW|RX|rx_error_d~q  & ( !\A_SPW_TOP|SPW|FSM|state_fsm~13_combout  ) ) ) # ( !\A_SPW_TOP|SPW|RX|rx_got_fct_fsm~q  & ( !\A_SPW_TOP|SPW|RX|rx_error_d~q  
// & ( (!\A_SPW_TOP|SPW|FSM|state_fsm~13_combout  & (((\A_SPW_TOP|SPW|RX|rx_got_nchar~q ) # (\A_SPW_TOP|SPW|RX|rx_error_c~q )) # (\A_SPW_TOP|SPW|RX|rx_got_time_code~q ))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_got_time_code~q ),
        .datab(!\A_SPW_TOP|SPW|FSM|state_fsm~13_combout ),
        .datac(!\A_SPW_TOP|SPW|RX|rx_error_c~q ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_got_nchar~q ),
        .datae(!\A_SPW_TOP|SPW|RX|rx_got_fct_fsm~q ),
        .dataf(!\A_SPW_TOP|SPW|RX|rx_error_d~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|state_fsm~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|state_fsm~14 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|state_fsm~14 .lut_mask = 64'h4CCCCCCCCCCCCCCC;
defparam \A_SPW_TOP|SPW|FSM|state_fsm~14 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y4_N42
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|state_fsm~15 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|state_fsm~15_combout  = ( \A_SPW_TOP|SPW|FSM|rx_resetn~0_combout  & ( !\A_SPW_TOP|SPW|FSM|state_fsm~14_combout  & ( (!\A_SPW_TOP|SPW|FSM|Selector0~1_combout  & (\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~0_combout  & 
// (!\A_SPW_TOP|SPW|FSM|Selector0~2_combout  & !\A_SPW_TOP|SPW|FSM|Selector0~0_combout ))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|Selector0~1_combout ),
        .datab(!\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~0_combout ),
        .datac(!\A_SPW_TOP|SPW|FSM|Selector0~2_combout ),
        .datad(!\A_SPW_TOP|SPW|FSM|Selector0~0_combout ),
        .datae(!\A_SPW_TOP|SPW|FSM|rx_resetn~0_combout ),
        .dataf(!\A_SPW_TOP|SPW|FSM|state_fsm~14_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|state_fsm~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|state_fsm~15 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|state_fsm~15 .lut_mask = 64'h0000200000000000;
defparam \A_SPW_TOP|SPW|FSM|state_fsm~15 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y4_N44
dffeas \A_SPW_TOP|SPW|FSM|state_fsm.error_reset (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|SPW|FSM|state_fsm~15_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|state_fsm.error_reset .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|state_fsm.error_reset .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y9_N36
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Equal2~3 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Equal2~3_combout  = ( \A_SPW_TOP|SPW|FSM|after64us [6] & ( \A_SPW_TOP|SPW|FSM|Equal2~0_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|FSM|Equal2~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|FSM|after64us [6]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|Equal2~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Equal2~3 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Equal2~3 .lut_mask = 64'h000000000F0F0F0F;
defparam \A_SPW_TOP|SPW|FSM|Equal2~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y9_N0
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add1~5 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add1~5_sumout  = SUM(( \A_SPW_TOP|SPW|FSM|after64us [0] ) + ( VCC ) + ( !VCC ))
// \A_SPW_TOP|SPW|FSM|Add1~6  = CARRY(( \A_SPW_TOP|SPW|FSM|after64us [0] ) + ( VCC ) + ( !VCC ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|FSM|after64us [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(),
        .sumout(\A_SPW_TOP|SPW|FSM|Add1~5_sumout ),
        .cout(\A_SPW_TOP|SPW|FSM|Add1~6 ),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add1~5 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add1~5 .lut_mask = 64'h0000000000000F0F;
defparam \A_SPW_TOP|SPW|FSM|Add1~5 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y9_N15
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after64us~2 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after64us~2_combout  = ( \A_SPW_TOP|SPW|FSM|after64us~0_combout  & ( \A_SPW_TOP|SPW|FSM|Add1~5_sumout  & ( (!\A_SPW_TOP|SPW|FSM|after64us [9]) # ((\A_SPW_TOP|SPW|FSM|Equal2~2_combout  & ((!\A_SPW_TOP|SPW|FSM|after64us [6]) # 
// (!\A_SPW_TOP|SPW|FSM|Equal2~0_combout )))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|after64us [6]),
        .datab(!\A_SPW_TOP|SPW|FSM|Equal2~2_combout ),
        .datac(!\A_SPW_TOP|SPW|FSM|after64us [9]),
        .datad(!\A_SPW_TOP|SPW|FSM|Equal2~0_combout ),
        .datae(!\A_SPW_TOP|SPW|FSM|after64us~0_combout ),
        .dataf(!\A_SPW_TOP|SPW|FSM|Add1~5_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|after64us~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after64us~2 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after64us~2 .lut_mask = 64'h000000000000F3F2;
defparam \A_SPW_TOP|SPW|FSM|after64us~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y9_N17
dffeas \A_SPW_TOP|SPW|FSM|after64us[0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|SPW|FSM|after64us~2_combout ),
        .asdata(vcc),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|FSM|after64us [0]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after64us[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after64us[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y9_N3
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add1~9 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add1~9_sumout  = SUM(( \A_SPW_TOP|SPW|FSM|after64us [1] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add1~6  ))
// \A_SPW_TOP|SPW|FSM|Add1~10  = CARRY(( \A_SPW_TOP|SPW|FSM|after64us [1] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add1~6  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|FSM|after64us [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\A_SPW_TOP|SPW|FSM|Add1~6 ),
        .sharein(gnd),
        .combout(),
        .sumout(\A_SPW_TOP|SPW|FSM|Add1~9_sumout ),
        .cout(\A_SPW_TOP|SPW|FSM|Add1~10 ),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add1~9 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add1~9 .lut_mask = 64'h0000FFFF00000F0F;
defparam \A_SPW_TOP|SPW|FSM|Add1~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y9_N6
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add1~13 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add1~13_sumout  = SUM(( \A_SPW_TOP|SPW|FSM|after64us [2] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add1~10  ))
// \A_SPW_TOP|SPW|FSM|Add1~14  = CARRY(( \A_SPW_TOP|SPW|FSM|after64us [2] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add1~10  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|FSM|after64us [2]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\A_SPW_TOP|SPW|FSM|Add1~10 ),
        .sharein(gnd),
        .combout(),
        .sumout(\A_SPW_TOP|SPW|FSM|Add1~13_sumout ),
        .cout(\A_SPW_TOP|SPW|FSM|Add1~14 ),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add1~13 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add1~13 .lut_mask = 64'h0000FFFF00000F0F;
defparam \A_SPW_TOP|SPW|FSM|Add1~13 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y9_N21
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after64us~4 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after64us~4_combout  = ( \A_SPW_TOP|SPW|FSM|after64us~0_combout  & ( \A_SPW_TOP|SPW|FSM|Add1~13_sumout  & ( (!\A_SPW_TOP|SPW|FSM|after64us [9]) # ((\A_SPW_TOP|SPW|FSM|Equal2~2_combout  & ((!\A_SPW_TOP|SPW|FSM|Equal2~0_combout ) # 
// (!\A_SPW_TOP|SPW|FSM|after64us [6])))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|Equal2~0_combout ),
        .datab(!\A_SPW_TOP|SPW|FSM|Equal2~2_combout ),
        .datac(!\A_SPW_TOP|SPW|FSM|after64us [9]),
        .datad(!\A_SPW_TOP|SPW|FSM|after64us [6]),
        .datae(!\A_SPW_TOP|SPW|FSM|after64us~0_combout ),
        .dataf(!\A_SPW_TOP|SPW|FSM|Add1~13_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|after64us~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after64us~4 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after64us~4 .lut_mask = 64'h000000000000F3F2;
defparam \A_SPW_TOP|SPW|FSM|after64us~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y9_N23
dffeas \A_SPW_TOP|SPW|FSM|after64us[2] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|SPW|FSM|after64us~4_combout ),
        .asdata(vcc),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|FSM|after64us [2]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after64us[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after64us[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y9_N9
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add1~17 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add1~17_sumout  = SUM(( \A_SPW_TOP|SPW|FSM|after64us [3] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add1~14  ))
// \A_SPW_TOP|SPW|FSM|Add1~18  = CARRY(( \A_SPW_TOP|SPW|FSM|after64us [3] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add1~14  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|FSM|after64us [3]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\A_SPW_TOP|SPW|FSM|Add1~14 ),
        .sharein(gnd),
        .combout(),
        .sumout(\A_SPW_TOP|SPW|FSM|Add1~17_sumout ),
        .cout(\A_SPW_TOP|SPW|FSM|Add1~18 ),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add1~17 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add1~17 .lut_mask = 64'h0000FFFF00000F0F;
defparam \A_SPW_TOP|SPW|FSM|Add1~17 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y9_N42
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after64us~5 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after64us~5_combout  = ( \A_SPW_TOP|SPW|FSM|Add1~17_sumout  & ( \A_SPW_TOP|SPW|FSM|after64us~0_combout  & ( (!\A_SPW_TOP|SPW|FSM|after64us [9]) # ((\A_SPW_TOP|SPW|FSM|Equal2~2_combout  & ((!\A_SPW_TOP|SPW|FSM|Equal2~0_combout ) # 
// (!\A_SPW_TOP|SPW|FSM|after64us [6])))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|Equal2~0_combout ),
        .datab(!\A_SPW_TOP|SPW|FSM|after64us [9]),
        .datac(!\A_SPW_TOP|SPW|FSM|after64us [6]),
        .datad(!\A_SPW_TOP|SPW|FSM|Equal2~2_combout ),
        .datae(!\A_SPW_TOP|SPW|FSM|Add1~17_sumout ),
        .dataf(!\A_SPW_TOP|SPW|FSM|after64us~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|after64us~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after64us~5 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after64us~5 .lut_mask = 64'h000000000000CCFE;
defparam \A_SPW_TOP|SPW|FSM|after64us~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y9_N44
dffeas \A_SPW_TOP|SPW|FSM|after64us[3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|SPW|FSM|after64us~5_combout ),
        .asdata(vcc),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|FSM|after64us [3]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after64us[3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after64us[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y9_N12
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add1~21 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add1~21_sumout  = SUM(( \A_SPW_TOP|SPW|FSM|after64us [4] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add1~18  ))
// \A_SPW_TOP|SPW|FSM|Add1~22  = CARRY(( \A_SPW_TOP|SPW|FSM|after64us [4] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add1~18  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|FSM|after64us [4]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\A_SPW_TOP|SPW|FSM|Add1~18 ),
        .sharein(gnd),
        .combout(),
        .sumout(\A_SPW_TOP|SPW|FSM|Add1~21_sumout ),
        .cout(\A_SPW_TOP|SPW|FSM|Add1~22 ),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add1~21 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add1~21 .lut_mask = 64'h0000FFFF00000F0F;
defparam \A_SPW_TOP|SPW|FSM|Add1~21 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y9_N45
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after64us~6 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after64us~6_combout  = ( \A_SPW_TOP|SPW|FSM|after64us~0_combout  & ( \A_SPW_TOP|SPW|FSM|Add1~21_sumout  & ( (!\A_SPW_TOP|SPW|FSM|after64us [9]) # ((\A_SPW_TOP|SPW|FSM|Equal2~2_combout  & ((!\A_SPW_TOP|SPW|FSM|Equal2~0_combout ) # 
// (!\A_SPW_TOP|SPW|FSM|after64us [6])))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|Equal2~0_combout ),
        .datab(!\A_SPW_TOP|SPW|FSM|after64us [9]),
        .datac(!\A_SPW_TOP|SPW|FSM|Equal2~2_combout ),
        .datad(!\A_SPW_TOP|SPW|FSM|after64us [6]),
        .datae(!\A_SPW_TOP|SPW|FSM|after64us~0_combout ),
        .dataf(!\A_SPW_TOP|SPW|FSM|Add1~21_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|after64us~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after64us~6 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after64us~6 .lut_mask = 64'h000000000000CFCE;
defparam \A_SPW_TOP|SPW|FSM|after64us~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y9_N47
dffeas \A_SPW_TOP|SPW|FSM|after64us[4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|SPW|FSM|after64us~6_combout ),
        .asdata(vcc),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|FSM|after64us [4]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after64us[4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after64us[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y9_N15
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add1~25 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add1~25_sumout  = SUM(( \A_SPW_TOP|SPW|FSM|after64us [5] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add1~22  ))
// \A_SPW_TOP|SPW|FSM|Add1~26  = CARRY(( \A_SPW_TOP|SPW|FSM|after64us [5] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add1~22  ))

        .dataa(!\A_SPW_TOP|SPW|FSM|after64us [5]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\A_SPW_TOP|SPW|FSM|Add1~22 ),
        .sharein(gnd),
        .combout(),
        .sumout(\A_SPW_TOP|SPW|FSM|Add1~25_sumout ),
        .cout(\A_SPW_TOP|SPW|FSM|Add1~26 ),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add1~25 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add1~25 .lut_mask = 64'h0000FFFF00005555;
defparam \A_SPW_TOP|SPW|FSM|Add1~25 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y9_N0
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after64us~7 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after64us~7_combout  = ( \A_SPW_TOP|SPW|FSM|after64us~0_combout  & ( \A_SPW_TOP|SPW|FSM|Add1~25_sumout  & ( (!\A_SPW_TOP|SPW|FSM|after64us [9]) # ((\A_SPW_TOP|SPW|FSM|Equal2~2_combout  & ((!\A_SPW_TOP|SPW|FSM|after64us [6]) # 
// (!\A_SPW_TOP|SPW|FSM|Equal2~0_combout )))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|after64us [6]),
        .datab(!\A_SPW_TOP|SPW|FSM|Equal2~2_combout ),
        .datac(!\A_SPW_TOP|SPW|FSM|Equal2~0_combout ),
        .datad(!\A_SPW_TOP|SPW|FSM|after64us [9]),
        .datae(!\A_SPW_TOP|SPW|FSM|after64us~0_combout ),
        .dataf(!\A_SPW_TOP|SPW|FSM|Add1~25_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|after64us~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after64us~7 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after64us~7 .lut_mask = 64'h000000000000FF32;
defparam \A_SPW_TOP|SPW|FSM|after64us~7 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y9_N2
dffeas \A_SPW_TOP|SPW|FSM|after64us[5] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|SPW|FSM|after64us~7_combout ),
        .asdata(vcc),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|FSM|after64us [5]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after64us[5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after64us[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y9_N18
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add1~1 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add1~1_sumout  = SUM(( \A_SPW_TOP|SPW|FSM|after64us [6] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add1~26  ))
// \A_SPW_TOP|SPW|FSM|Add1~2  = CARRY(( \A_SPW_TOP|SPW|FSM|after64us [6] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add1~26  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|FSM|after64us [6]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\A_SPW_TOP|SPW|FSM|Add1~26 ),
        .sharein(gnd),
        .combout(),
        .sumout(\A_SPW_TOP|SPW|FSM|Add1~1_sumout ),
        .cout(\A_SPW_TOP|SPW|FSM|Add1~2 ),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add1~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add1~1 .lut_mask = 64'h0000FFFF00000F0F;
defparam \A_SPW_TOP|SPW|FSM|Add1~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y9_N21
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add1~33 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add1~33_sumout  = SUM(( \A_SPW_TOP|SPW|FSM|after64us [7] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add1~2  ))
// \A_SPW_TOP|SPW|FSM|Add1~34  = CARRY(( \A_SPW_TOP|SPW|FSM|after64us [7] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add1~2  ))

        .dataa(!\A_SPW_TOP|SPW|FSM|after64us [7]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\A_SPW_TOP|SPW|FSM|Add1~2 ),
        .sharein(gnd),
        .combout(),
        .sumout(\A_SPW_TOP|SPW|FSM|Add1~33_sumout ),
        .cout(\A_SPW_TOP|SPW|FSM|Add1~34 ),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add1~33 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add1~33 .lut_mask = 64'h0000FFFF00005555;
defparam \A_SPW_TOP|SPW|FSM|Add1~33 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y9_N24
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add1~37 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add1~37_sumout  = SUM(( \A_SPW_TOP|SPW|FSM|after64us [8] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add1~34  ))
// \A_SPW_TOP|SPW|FSM|Add1~38  = CARRY(( \A_SPW_TOP|SPW|FSM|after64us [8] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add1~34  ))

        .dataa(gnd),
        .datab(!\A_SPW_TOP|SPW|FSM|after64us [8]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\A_SPW_TOP|SPW|FSM|Add1~34 ),
        .sharein(gnd),
        .combout(),
        .sumout(\A_SPW_TOP|SPW|FSM|Add1~37_sumout ),
        .cout(\A_SPW_TOP|SPW|FSM|Add1~38 ),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add1~37 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add1~37 .lut_mask = 64'h0000FFFF00003333;
defparam \A_SPW_TOP|SPW|FSM|Add1~37 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y9_N27
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add1~29 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add1~29_sumout  = SUM(( \A_SPW_TOP|SPW|FSM|after64us [9] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add1~38  ))
// \A_SPW_TOP|SPW|FSM|Add1~30  = CARRY(( \A_SPW_TOP|SPW|FSM|after64us [9] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add1~38  ))

        .dataa(!\A_SPW_TOP|SPW|FSM|after64us [9]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\A_SPW_TOP|SPW|FSM|Add1~38 ),
        .sharein(gnd),
        .combout(),
        .sumout(\A_SPW_TOP|SPW|FSM|Add1~29_sumout ),
        .cout(\A_SPW_TOP|SPW|FSM|Add1~30 ),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add1~29 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add1~29 .lut_mask = 64'h0000FFFF00005555;
defparam \A_SPW_TOP|SPW|FSM|Add1~29 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y9_N30
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add1~41 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add1~41_sumout  = SUM(( \A_SPW_TOP|SPW|FSM|after64us [10] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add1~30  ))
// \A_SPW_TOP|SPW|FSM|Add1~42  = CARRY(( \A_SPW_TOP|SPW|FSM|after64us [10] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add1~30  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|FSM|after64us [10]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\A_SPW_TOP|SPW|FSM|Add1~30 ),
        .sharein(gnd),
        .combout(),
        .sumout(\A_SPW_TOP|SPW|FSM|Add1~41_sumout ),
        .cout(\A_SPW_TOP|SPW|FSM|Add1~42 ),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add1~41 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add1~41 .lut_mask = 64'h0000FFFF00000F0F;
defparam \A_SPW_TOP|SPW|FSM|Add1~41 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y9_N39
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after64us~11 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after64us~11_combout  = ( \A_SPW_TOP|SPW|FSM|Add1~41_sumout  & ( (\A_SPW_TOP|SPW|FSM|after64us~0_combout  & ((!\A_SPW_TOP|SPW|FSM|after64us [9]) # ((!\A_SPW_TOP|SPW|FSM|Equal2~3_combout  & \A_SPW_TOP|SPW|FSM|Equal2~2_combout )))) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|Equal2~3_combout ),
        .datab(!\A_SPW_TOP|SPW|FSM|after64us [9]),
        .datac(!\A_SPW_TOP|SPW|FSM|Equal2~2_combout ),
        .datad(!\A_SPW_TOP|SPW|FSM|after64us~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|FSM|Add1~41_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|after64us~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after64us~11 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after64us~11 .lut_mask = 64'h0000000000CE00CE;
defparam \A_SPW_TOP|SPW|FSM|after64us~11 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y9_N41
dffeas \A_SPW_TOP|SPW|FSM|after64us[10] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|SPW|FSM|after64us~11_combout ),
        .asdata(vcc),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|FSM|after64us [10]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after64us[10] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after64us[10] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y9_N33
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add1~45 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add1~45_sumout  = SUM(( \A_SPW_TOP|SPW|FSM|after64us [11] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add1~42  ))

        .dataa(!\A_SPW_TOP|SPW|FSM|after64us [11]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\A_SPW_TOP|SPW|FSM|Add1~42 ),
        .sharein(gnd),
        .combout(),
        .sumout(\A_SPW_TOP|SPW|FSM|Add1~45_sumout ),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add1~45 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add1~45 .lut_mask = 64'h0000FFFF00005555;
defparam \A_SPW_TOP|SPW|FSM|Add1~45 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y9_N30
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after64us~12 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after64us~12_combout  = ( \A_SPW_TOP|SPW|FSM|after64us [9] & ( (\A_SPW_TOP|SPW|FSM|Add1~45_sumout  & (\A_SPW_TOP|SPW|FSM|Equal2~2_combout  & (!\A_SPW_TOP|SPW|FSM|Equal2~3_combout  & \A_SPW_TOP|SPW|FSM|after64us~0_combout ))) ) ) # ( 
// !\A_SPW_TOP|SPW|FSM|after64us [9] & ( (\A_SPW_TOP|SPW|FSM|Add1~45_sumout  & \A_SPW_TOP|SPW|FSM|after64us~0_combout ) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|Add1~45_sumout ),
        .datab(!\A_SPW_TOP|SPW|FSM|Equal2~2_combout ),
        .datac(!\A_SPW_TOP|SPW|FSM|Equal2~3_combout ),
        .datad(!\A_SPW_TOP|SPW|FSM|after64us~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|FSM|after64us [9]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|after64us~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after64us~12 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after64us~12 .lut_mask = 64'h0055005500100010;
defparam \A_SPW_TOP|SPW|FSM|after64us~12 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y9_N32
dffeas \A_SPW_TOP|SPW|FSM|after64us[11] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|SPW|FSM|after64us~12_combout ),
        .asdata(vcc),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|FSM|after64us [11]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after64us[11] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after64us[11] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y9_N48
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after64us~0 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after64us~0_combout  = ( \u0|auto_start|data_out~q  & ( !\A_SPW_TOP|SPW|FSM|after64us [11] & ( (!\A_SPW_TOP|SPW|FSM|after64us [10] & (!\db_system_spwulight_b|aux_pb~q  & !\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q )) ) ) ) # ( 
// !\u0|auto_start|data_out~q  & ( !\A_SPW_TOP|SPW|FSM|after64us [11] & ( (!\A_SPW_TOP|SPW|FSM|after64us [10] & (!\db_system_spwulight_b|aux_pb~q  & (\u0|link_start|data_out~q  & !\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q ))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|after64us [10]),
        .datab(!\db_system_spwulight_b|aux_pb~q ),
        .datac(!\u0|link_start|data_out~q ),
        .datad(!\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q ),
        .datae(!\u0|auto_start|data_out~q ),
        .dataf(!\A_SPW_TOP|SPW|FSM|after64us [11]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|after64us~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after64us~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after64us~0 .lut_mask = 64'h0800880000000000;
defparam \A_SPW_TOP|SPW|FSM|after64us~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y9_N18
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after64us~3 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after64us~3_combout  = ( \A_SPW_TOP|SPW|FSM|after64us~0_combout  & ( \A_SPW_TOP|SPW|FSM|Add1~9_sumout  & ( (!\A_SPW_TOP|SPW|FSM|after64us [9]) # ((\A_SPW_TOP|SPW|FSM|Equal2~2_combout  & ((!\A_SPW_TOP|SPW|FSM|Equal2~0_combout ) # 
// (!\A_SPW_TOP|SPW|FSM|after64us [6])))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|Equal2~0_combout ),
        .datab(!\A_SPW_TOP|SPW|FSM|Equal2~2_combout ),
        .datac(!\A_SPW_TOP|SPW|FSM|after64us [6]),
        .datad(!\A_SPW_TOP|SPW|FSM|after64us [9]),
        .datae(!\A_SPW_TOP|SPW|FSM|after64us~0_combout ),
        .dataf(!\A_SPW_TOP|SPW|FSM|Add1~9_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|after64us~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after64us~3 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after64us~3 .lut_mask = 64'h000000000000FF32;
defparam \A_SPW_TOP|SPW|FSM|after64us~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y9_N20
dffeas \A_SPW_TOP|SPW|FSM|after64us[1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|SPW|FSM|after64us~3_combout ),
        .asdata(vcc),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|FSM|after64us [1]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after64us[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after64us[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y9_N48
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Equal2~0 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Equal2~0_combout  = ( \A_SPW_TOP|SPW|FSM|after64us [5] & ( \A_SPW_TOP|SPW|FSM|after64us [0] & ( (\A_SPW_TOP|SPW|FSM|after64us [1] & (\A_SPW_TOP|SPW|FSM|after64us [4] & (\A_SPW_TOP|SPW|FSM|after64us [2] & \A_SPW_TOP|SPW|FSM|after64us 
// [3]))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|after64us [1]),
        .datab(!\A_SPW_TOP|SPW|FSM|after64us [4]),
        .datac(!\A_SPW_TOP|SPW|FSM|after64us [2]),
        .datad(!\A_SPW_TOP|SPW|FSM|after64us [3]),
        .datae(!\A_SPW_TOP|SPW|FSM|after64us [5]),
        .dataf(!\A_SPW_TOP|SPW|FSM|after64us [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|Equal2~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Equal2~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Equal2~0 .lut_mask = 64'h0000000000000001;
defparam \A_SPW_TOP|SPW|FSM|Equal2~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y9_N27
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after64us~8 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after64us~8_combout  = ( \A_SPW_TOP|SPW|FSM|after64us~0_combout  & ( \A_SPW_TOP|SPW|FSM|Add1~29_sumout  & ( (!\A_SPW_TOP|SPW|FSM|after64us [9]) # ((\A_SPW_TOP|SPW|FSM|Equal2~2_combout  & ((!\A_SPW_TOP|SPW|FSM|after64us [6]) # 
// (!\A_SPW_TOP|SPW|FSM|Equal2~0_combout )))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|after64us [6]),
        .datab(!\A_SPW_TOP|SPW|FSM|after64us [9]),
        .datac(!\A_SPW_TOP|SPW|FSM|Equal2~2_combout ),
        .datad(!\A_SPW_TOP|SPW|FSM|Equal2~0_combout ),
        .datae(!\A_SPW_TOP|SPW|FSM|after64us~0_combout ),
        .dataf(!\A_SPW_TOP|SPW|FSM|Add1~29_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|after64us~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after64us~8 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after64us~8 .lut_mask = 64'h000000000000CFCE;
defparam \A_SPW_TOP|SPW|FSM|after64us~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y9_N11
dffeas \A_SPW_TOP|SPW|FSM|after64us[9] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|FSM|after64us~8_combout ),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|FSM|after64us [9]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after64us[9] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after64us[9] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y9_N24
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after64us~10 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after64us~10_combout  = ( \A_SPW_TOP|SPW|FSM|after64us~0_combout  & ( \A_SPW_TOP|SPW|FSM|Add1~37_sumout  & ( (!\A_SPW_TOP|SPW|FSM|after64us [9]) # ((\A_SPW_TOP|SPW|FSM|Equal2~2_combout  & ((!\A_SPW_TOP|SPW|FSM|after64us [6]) # 
// (!\A_SPW_TOP|SPW|FSM|Equal2~0_combout )))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|after64us [6]),
        .datab(!\A_SPW_TOP|SPW|FSM|after64us [9]),
        .datac(!\A_SPW_TOP|SPW|FSM|Equal2~0_combout ),
        .datad(!\A_SPW_TOP|SPW|FSM|Equal2~2_combout ),
        .datae(!\A_SPW_TOP|SPW|FSM|after64us~0_combout ),
        .dataf(!\A_SPW_TOP|SPW|FSM|Add1~37_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|after64us~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after64us~10 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after64us~10 .lut_mask = 64'h000000000000CCFE;
defparam \A_SPW_TOP|SPW|FSM|after64us~10 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y9_N26
dffeas \A_SPW_TOP|SPW|FSM|after64us[8] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|SPW|FSM|after64us~10_combout ),
        .asdata(vcc),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|FSM|after64us [8]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after64us[8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after64us[8] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y9_N57
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Equal2~2 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Equal2~2_combout  = (!\A_SPW_TOP|SPW|FSM|after64us [7] & !\A_SPW_TOP|SPW|FSM|after64us [8])

        .dataa(!\A_SPW_TOP|SPW|FSM|after64us [7]),
        .datab(!\A_SPW_TOP|SPW|FSM|after64us [8]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|Equal2~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Equal2~2 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Equal2~2 .lut_mask = 64'h8888888888888888;
defparam \A_SPW_TOP|SPW|FSM|Equal2~2 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y9_N12
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after64us~1 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after64us~1_combout  = ( \A_SPW_TOP|SPW|FSM|after64us~0_combout  & ( \A_SPW_TOP|SPW|FSM|Add1~1_sumout  & ( (!\A_SPW_TOP|SPW|FSM|after64us [9]) # ((\A_SPW_TOP|SPW|FSM|Equal2~2_combout  & ((!\A_SPW_TOP|SPW|FSM|after64us [6]) # 
// (!\A_SPW_TOP|SPW|FSM|Equal2~0_combout )))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|after64us [6]),
        .datab(!\A_SPW_TOP|SPW|FSM|Equal2~2_combout ),
        .datac(!\A_SPW_TOP|SPW|FSM|Equal2~0_combout ),
        .datad(!\A_SPW_TOP|SPW|FSM|after64us [9]),
        .datae(!\A_SPW_TOP|SPW|FSM|after64us~0_combout ),
        .dataf(!\A_SPW_TOP|SPW|FSM|Add1~1_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|after64us~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after64us~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after64us~1 .lut_mask = 64'h000000000000FF32;
defparam \A_SPW_TOP|SPW|FSM|after64us~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y9_N53
dffeas \A_SPW_TOP|SPW|FSM|after64us[6] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|FSM|after64us~1_combout ),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|FSM|after64us [6]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after64us[6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after64us[6] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y9_N3
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after64us~9 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after64us~9_combout  = ( \A_SPW_TOP|SPW|FSM|after64us~0_combout  & ( \A_SPW_TOP|SPW|FSM|Add1~33_sumout  & ( (!\A_SPW_TOP|SPW|FSM|after64us [9]) # ((\A_SPW_TOP|SPW|FSM|Equal2~2_combout  & ((!\A_SPW_TOP|SPW|FSM|after64us [6]) # 
// (!\A_SPW_TOP|SPW|FSM|Equal2~0_combout )))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|after64us [6]),
        .datab(!\A_SPW_TOP|SPW|FSM|Equal2~2_combout ),
        .datac(!\A_SPW_TOP|SPW|FSM|after64us [9]),
        .datad(!\A_SPW_TOP|SPW|FSM|Equal2~0_combout ),
        .datae(!\A_SPW_TOP|SPW|FSM|after64us~0_combout ),
        .dataf(!\A_SPW_TOP|SPW|FSM|Add1~33_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|after64us~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after64us~9 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after64us~9 .lut_mask = 64'h000000000000F3F2;
defparam \A_SPW_TOP|SPW|FSM|after64us~9 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X50_Y9_N5
dffeas \A_SPW_TOP|SPW|FSM|after64us[7] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|SPW|FSM|after64us~9_combout ),
        .asdata(vcc),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|FSM|after64us [7]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after64us[7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after64us[7] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y9_N54
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Equal2~1 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Equal2~1_combout  = ( \A_SPW_TOP|SPW|FSM|after64us [9] & ( (!\A_SPW_TOP|SPW|FSM|after64us [7] & (!\A_SPW_TOP|SPW|FSM|after64us [8] & (!\A_SPW_TOP|SPW|FSM|after64us [10] & !\A_SPW_TOP|SPW|FSM|after64us [11]))) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|after64us [7]),
        .datab(!\A_SPW_TOP|SPW|FSM|after64us [8]),
        .datac(!\A_SPW_TOP|SPW|FSM|after64us [10]),
        .datad(!\A_SPW_TOP|SPW|FSM|after64us [11]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|FSM|after64us [9]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|Equal2~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Equal2~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Equal2~1 .lut_mask = 64'h0000000080008000;
defparam \A_SPW_TOP|SPW|FSM|Equal2~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y4_N0
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|rx_resetn~0 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|rx_resetn~0_combout  = ( \A_SPW_TOP|SPW|FSM|Equal2~0_combout  & ( ((\A_SPW_TOP|SPW|FSM|Equal2~1_combout  & \A_SPW_TOP|SPW|FSM|after64us [6])) # (\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q ) ) ) # ( !\A_SPW_TOP|SPW|FSM|Equal2~0_combout  
// & ( \A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q  ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q ),
        .datac(!\A_SPW_TOP|SPW|FSM|Equal2~1_combout ),
        .datad(!\A_SPW_TOP|SPW|FSM|after64us [6]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|FSM|Equal2~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|rx_resetn~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|rx_resetn~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|rx_resetn~0 .lut_mask = 64'h33333333333F333F;
defparam \A_SPW_TOP|SPW|FSM|rx_resetn~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y4_N2
dffeas \A_SPW_TOP|SPW|FSM|rx_resetn (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|SPW|FSM|rx_resetn~0_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|rx_resetn .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|rx_resetn .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y3_N36
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|WideOr7~0 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|WideOr7~0_combout  = ( !\A_SPW_TOP|SPW|RX|counter_neg [3] & ( \A_SPW_TOP|SPW|RX|counter_neg [4] & ( (!\A_SPW_TOP|SPW|RX|counter_neg [5] & (\A_SPW_TOP|SPW|RX|counter_neg [0] & (!\A_SPW_TOP|SPW|RX|counter_neg [2] & 
// !\A_SPW_TOP|SPW|RX|counter_neg [1]))) ) ) ) # ( \A_SPW_TOP|SPW|RX|counter_neg [3] & ( !\A_SPW_TOP|SPW|RX|counter_neg [4] & ( (!\A_SPW_TOP|SPW|RX|counter_neg [5] & (\A_SPW_TOP|SPW|RX|counter_neg [0] & (!\A_SPW_TOP|SPW|RX|counter_neg [2] & 
// !\A_SPW_TOP|SPW|RX|counter_neg [1]))) ) ) ) # ( !\A_SPW_TOP|SPW|RX|counter_neg [3] & ( !\A_SPW_TOP|SPW|RX|counter_neg [4] & ( (!\A_SPW_TOP|SPW|RX|counter_neg [5] & ((!\A_SPW_TOP|SPW|RX|counter_neg [0] & (!\A_SPW_TOP|SPW|RX|counter_neg [2] & 
// !\A_SPW_TOP|SPW|RX|counter_neg [1])) # (\A_SPW_TOP|SPW|RX|counter_neg [0] & (!\A_SPW_TOP|SPW|RX|counter_neg [2] $ (!\A_SPW_TOP|SPW|RX|counter_neg [1]))))) # (\A_SPW_TOP|SPW|RX|counter_neg [5] & (\A_SPW_TOP|SPW|RX|counter_neg [0] & 
// (!\A_SPW_TOP|SPW|RX|counter_neg [2] & !\A_SPW_TOP|SPW|RX|counter_neg [1]))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|counter_neg [5]),
        .datab(!\A_SPW_TOP|SPW|RX|counter_neg [0]),
        .datac(!\A_SPW_TOP|SPW|RX|counter_neg [2]),
        .datad(!\A_SPW_TOP|SPW|RX|counter_neg [1]),
        .datae(!\A_SPW_TOP|SPW|RX|counter_neg [3]),
        .dataf(!\A_SPW_TOP|SPW|RX|counter_neg [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|WideOr7~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|WideOr7~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|WideOr7~0 .lut_mask = 64'h9220200020000000;
defparam \A_SPW_TOP|SPW|RX|WideOr7~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y3_N44
dffeas \A_SPW_TOP|SPW|RX|counter_neg[0] (
        .clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(\A_SPW_TOP|SPW|RX|counter_neg[0]~feeder_combout ),
        .asdata(vcc),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\A_SPW_TOP|SPW|RX|WideOr7~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|counter_neg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|counter_neg[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|counter_neg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y3_N3
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|Selector2~0 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|Selector2~0_combout  = ( !\A_SPW_TOP|SPW|RX|counter_neg [2] & ( (!\A_SPW_TOP|SPW|RX|counter_neg [5] & (!\A_SPW_TOP|SPW|RX|counter_neg [1] & \A_SPW_TOP|SPW|RX|counter_neg [0])) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|counter_neg [5]),
        .datab(!\A_SPW_TOP|SPW|RX|counter_neg [1]),
        .datac(!\A_SPW_TOP|SPW|RX|counter_neg [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|counter_neg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|Selector2~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|Selector2~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|Selector2~0 .lut_mask = 64'h0808080800000000;
defparam \A_SPW_TOP|SPW|RX|Selector2~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y3_N33
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|Selector3~0 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|Selector3~0_combout  = ( !\A_SPW_TOP|SPW|RX|counter_neg [1] & ( (\A_SPW_TOP|SPW|RX|counter_neg [2] & !\A_SPW_TOP|SPW|RX|is_control~q ) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|counter_neg [2]),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|RX|is_control~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|counter_neg [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|Selector3~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|Selector3~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|Selector3~0 .lut_mask = 64'h5050505000000000;
defparam \A_SPW_TOP|SPW|RX|Selector3~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y3_N54
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|Selector3~1 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|Selector3~1_combout  = ( \A_SPW_TOP|SPW|RX|counter_neg [5] & ( \A_SPW_TOP|SPW|RX|Selector3~0_combout  & ( (\A_SPW_TOP|SPW|RX|counter_neg [3] & ((!\A_SPW_TOP|SPW|RX|Selector2~0_combout ) # (\A_SPW_TOP|SPW|RX|counter_neg [4]))) ) ) ) # ( 
// !\A_SPW_TOP|SPW|RX|counter_neg [5] & ( \A_SPW_TOP|SPW|RX|Selector3~0_combout  & ( (!\A_SPW_TOP|SPW|RX|counter_neg [4] & (((!\A_SPW_TOP|SPW|RX|Selector2~0_combout  & \A_SPW_TOP|SPW|RX|counter_neg [3])) # (\A_SPW_TOP|SPW|RX|counter_neg [0]))) # 
// (\A_SPW_TOP|SPW|RX|counter_neg [4] & (((\A_SPW_TOP|SPW|RX|counter_neg [3])))) ) ) ) # ( \A_SPW_TOP|SPW|RX|counter_neg [5] & ( !\A_SPW_TOP|SPW|RX|Selector3~0_combout  & ( (\A_SPW_TOP|SPW|RX|counter_neg [3] & ((!\A_SPW_TOP|SPW|RX|Selector2~0_combout ) # 
// (\A_SPW_TOP|SPW|RX|counter_neg [4]))) ) ) ) # ( !\A_SPW_TOP|SPW|RX|counter_neg [5] & ( !\A_SPW_TOP|SPW|RX|Selector3~0_combout  & ( (\A_SPW_TOP|SPW|RX|counter_neg [3] & ((!\A_SPW_TOP|SPW|RX|Selector2~0_combout ) # (\A_SPW_TOP|SPW|RX|counter_neg [4]))) ) ) 
// )

        .dataa(!\A_SPW_TOP|SPW|RX|Selector2~0_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|counter_neg [0]),
        .datac(!\A_SPW_TOP|SPW|RX|counter_neg [3]),
        .datad(!\A_SPW_TOP|SPW|RX|counter_neg [4]),
        .datae(!\A_SPW_TOP|SPW|RX|counter_neg [5]),
        .dataf(!\A_SPW_TOP|SPW|RX|Selector3~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|Selector3~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|Selector3~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|Selector3~1 .lut_mask = 64'h0A0F0A0F3B0F0A0F;
defparam \A_SPW_TOP|SPW|RX|Selector3~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y3_N5
dffeas \A_SPW_TOP|SPW|RX|counter_neg[3] (
        .clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|RX|Selector3~1_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|counter_neg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|counter_neg[3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|counter_neg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y3_N27
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|Selector2~1 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|Selector2~1_combout  = ( \A_SPW_TOP|SPW|RX|counter_neg [4] & ( (!\A_SPW_TOP|SPW|RX|Selector2~0_combout ) # (\A_SPW_TOP|SPW|RX|counter_neg [3]) ) ) # ( !\A_SPW_TOP|SPW|RX|counter_neg [4] & ( (\A_SPW_TOP|SPW|RX|counter_neg [3] & 
// \A_SPW_TOP|SPW|RX|Selector2~0_combout ) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|counter_neg [3]),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|RX|Selector2~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|counter_neg [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|Selector2~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|Selector2~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|Selector2~1 .lut_mask = 64'h05050505F5F5F5F5;
defparam \A_SPW_TOP|SPW|RX|Selector2~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y3_N11
dffeas \A_SPW_TOP|SPW|RX|counter_neg[4] (
        .clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|RX|Selector2~1_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|counter_neg [4]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|counter_neg[4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|counter_neg[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y3_N30
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|Selector0~0 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|Selector0~0_combout  = ( \A_SPW_TOP|SPW|RX|counter_neg [0] & ( (!\A_SPW_TOP|SPW|RX|counter_neg [4] & (!\A_SPW_TOP|SPW|RX|counter_neg [3] & !\A_SPW_TOP|SPW|RX|counter_neg [5])) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|SPW|RX|counter_neg [4]),
        .datac(!\A_SPW_TOP|SPW|RX|counter_neg [3]),
        .datad(!\A_SPW_TOP|SPW|RX|counter_neg [5]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|counter_neg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|Selector0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|Selector0~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|Selector0~0 .lut_mask = 64'h00000000C000C000;
defparam \A_SPW_TOP|SPW|RX|Selector0~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X50_Y3_N57
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|Selector4~0 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|Selector4~0_combout  = ( \A_SPW_TOP|SPW|RX|counter_neg [2] & ( \A_SPW_TOP|SPW|RX|Selector0~0_combout  & ( \A_SPW_TOP|SPW|RX|counter_neg [1] ) ) ) # ( !\A_SPW_TOP|SPW|RX|counter_neg [2] & ( \A_SPW_TOP|SPW|RX|Selector0~0_combout  & ( 
// \A_SPW_TOP|SPW|RX|counter_neg [1] ) ) ) # ( \A_SPW_TOP|SPW|RX|counter_neg [2] & ( !\A_SPW_TOP|SPW|RX|Selector0~0_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|RX|counter_neg [1]),
        .datad(gnd),
        .datae(!\A_SPW_TOP|SPW|RX|counter_neg [2]),
        .dataf(!\A_SPW_TOP|SPW|RX|Selector0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|Selector4~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|Selector4~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|Selector4~0 .lut_mask = 64'h0000FFFF0F0F0F0F;
defparam \A_SPW_TOP|SPW|RX|Selector4~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y3_N50
dffeas \A_SPW_TOP|SPW|RX|counter_neg[2] (
        .clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|RX|Selector4~0_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|counter_neg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|counter_neg[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|counter_neg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y3_N24
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|Selector1~0 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|Selector1~0_combout  = ( \A_SPW_TOP|SPW|RX|counter_neg [0] & ( (!\A_SPW_TOP|SPW|RX|counter_neg [1] & (!\A_SPW_TOP|SPW|RX|counter_neg [2] & !\A_SPW_TOP|SPW|RX|counter_neg [3])) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|SPW|RX|counter_neg [1]),
        .datac(!\A_SPW_TOP|SPW|RX|counter_neg [2]),
        .datad(!\A_SPW_TOP|SPW|RX|counter_neg [3]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|counter_neg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|Selector1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|Selector1~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|Selector1~0 .lut_mask = 64'h00000000C000C000;
defparam \A_SPW_TOP|SPW|RX|Selector1~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y3_N0
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|Selector1~1 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|Selector1~1_combout  = ( \A_SPW_TOP|SPW|RX|counter_neg [4] & ( (\A_SPW_TOP|SPW|RX|Selector1~0_combout ) # (\A_SPW_TOP|SPW|RX|counter_neg [5]) ) ) # ( !\A_SPW_TOP|SPW|RX|counter_neg [4] & ( (\A_SPW_TOP|SPW|RX|counter_neg [5] & 
// !\A_SPW_TOP|SPW|RX|Selector1~0_combout ) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|counter_neg [5]),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|RX|Selector1~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|counter_neg [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|Selector1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|Selector1~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|Selector1~1 .lut_mask = 64'h505050505F5F5F5F;
defparam \A_SPW_TOP|SPW|RX|Selector1~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y3_N56
dffeas \A_SPW_TOP|SPW|RX|counter_neg[5] (
        .clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|RX|Selector1~1_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|counter_neg [5]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|counter_neg[5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|counter_neg[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y3_N51
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|Selector0~2 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|Selector0~2_combout  = ( !\A_SPW_TOP|SPW|RX|counter_neg [2] & ( (!\A_SPW_TOP|SPW|RX|counter_neg [5] & (\A_SPW_TOP|SPW|RX|counter_neg [0] & (!\A_SPW_TOP|SPW|RX|counter_neg [4] & !\A_SPW_TOP|SPW|RX|counter_neg [3]))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|counter_neg [5]),
        .datab(!\A_SPW_TOP|SPW|RX|counter_neg [0]),
        .datac(!\A_SPW_TOP|SPW|RX|counter_neg [4]),
        .datad(!\A_SPW_TOP|SPW|RX|counter_neg [3]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|counter_neg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|Selector0~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|Selector0~2 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|Selector0~2 .lut_mask = 64'h2000200000000000;
defparam \A_SPW_TOP|SPW|RX|Selector0~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y3_N48
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|Selector5~0 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|Selector5~0_combout  = ( \A_SPW_TOP|SPW|RX|counter_neg [1] & ( (!\A_SPW_TOP|SPW|RX|counter_neg [5] & (\A_SPW_TOP|SPW|RX|counter_neg [0] & (\A_SPW_TOP|SPW|RX|is_control~q  & \A_SPW_TOP|SPW|RX|counter_neg [2]))) ) ) # ( 
// !\A_SPW_TOP|SPW|RX|counter_neg [1] & ( (!\A_SPW_TOP|SPW|RX|counter_neg [2] & (!\A_SPW_TOP|SPW|RX|counter_neg [5] $ ((\A_SPW_TOP|SPW|RX|counter_neg [0])))) # (\A_SPW_TOP|SPW|RX|counter_neg [2] & (!\A_SPW_TOP|SPW|RX|counter_neg [5] & 
// (\A_SPW_TOP|SPW|RX|counter_neg [0] & \A_SPW_TOP|SPW|RX|is_control~q ))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|counter_neg [5]),
        .datab(!\A_SPW_TOP|SPW|RX|counter_neg [0]),
        .datac(!\A_SPW_TOP|SPW|RX|is_control~q ),
        .datad(!\A_SPW_TOP|SPW|RX|counter_neg [2]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|counter_neg [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|Selector5~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|Selector5~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|Selector5~0 .lut_mask = 64'h9902990200020002;
defparam \A_SPW_TOP|SPW|RX|Selector5~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y3_N15
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|Selector5~1 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|Selector5~1_combout  = ( \A_SPW_TOP|SPW|RX|counter_neg [4] & ( (!\A_SPW_TOP|SPW|RX|Selector0~2_combout  & \A_SPW_TOP|SPW|RX|counter_neg [1]) ) ) # ( !\A_SPW_TOP|SPW|RX|counter_neg [4] & ( (!\A_SPW_TOP|SPW|RX|Selector0~2_combout  & 
// (((\A_SPW_TOP|SPW|RX|Selector5~0_combout  & !\A_SPW_TOP|SPW|RX|counter_neg [3])) # (\A_SPW_TOP|SPW|RX|counter_neg [1]))) # (\A_SPW_TOP|SPW|RX|Selector0~2_combout  & (((\A_SPW_TOP|SPW|RX|Selector5~0_combout  & !\A_SPW_TOP|SPW|RX|counter_neg [3])))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|Selector0~2_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|counter_neg [1]),
        .datac(!\A_SPW_TOP|SPW|RX|Selector5~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|counter_neg [3]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|counter_neg [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|Selector5~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|Selector5~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|Selector5~1 .lut_mask = 64'h2F222F2222222222;
defparam \A_SPW_TOP|SPW|RX|Selector5~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y3_N17
dffeas \A_SPW_TOP|SPW|RX|counter_neg[1] (
        .clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(\A_SPW_TOP|SPW|RX|Selector5~1_combout ),
        .asdata(vcc),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|counter_neg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|counter_neg[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|counter_neg[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X50_Y3_N51
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|always1~0 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|always1~0_combout  = LCELL(( \A_SPW_TOP|SPW|RX|counter_neg [2] & ( !\A_SPW_TOP|SPW|RX|always3~0_combout  & ( (!\A_SPW_TOP|SPW|RX|counter_neg [1] & \A_SPW_TOP|SPW|RX|Selector0~0_combout ) ) ) ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|RX|counter_neg [1]),
        .datad(!\A_SPW_TOP|SPW|RX|Selector0~0_combout ),
        .datae(!\A_SPW_TOP|SPW|RX|counter_neg [2]),
        .dataf(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|always1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|always1~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|always1~0 .lut_mask = 64'h000000F000000000;
defparam \A_SPW_TOP|SPW|RX|always1~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X49_Y3_N21
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|ready_control_p_r~0 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|ready_control_p_r~0_combout  = ( \A_SPW_TOP|SPW|RX|always2~0_combout  & ( \A_SPW_TOP|SPW|RX|is_control~q  ) ) # ( !\A_SPW_TOP|SPW|RX|always2~0_combout  & ( (\A_SPW_TOP|SPW|RX|always1~0_combout  & \A_SPW_TOP|SPW|RX|is_control~q ) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|always1~0_combout ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|RX|is_control~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|always2~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|ready_control_p_r~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|ready_control_p_r~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|ready_control_p_r~0 .lut_mask = 64'h050505050F0F0F0F;
defparam \A_SPW_TOP|SPW|RX|ready_control_p_r~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X49_Y3_N23
dffeas \A_SPW_TOP|SPW|RX|ready_control_p_r (
        .clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(\A_SPW_TOP|SPW|RX|ready_control_p_r~0_combout ),
        .asdata(vcc),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|ready_control_p_r .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|ready_control_p_r .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y3_N54
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|last_is_data~0 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|last_is_data~0_combout  = ( \A_SPW_TOP|SPW|RX|last_is_data~q  & ( (!\A_SPW_TOP|SPW|RX|ready_control_p_r~q  & ((!\A_SPW_TOP|SPW|RX|ready_data_p_r~q ) # (!\A_SPW_TOP|SPW|RX|data~0_combout ))) ) ) # ( !\A_SPW_TOP|SPW|RX|last_is_data~q  & ( 
// (!\A_SPW_TOP|SPW|RX|ready_control_p_r~q  & !\A_SPW_TOP|SPW|RX|data~0_combout ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),
        .datac(!\A_SPW_TOP|SPW|RX|ready_data_p_r~q ),
        .datad(!\A_SPW_TOP|SPW|RX|data~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|last_is_data~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|last_is_data~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|last_is_data~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|last_is_data~0 .lut_mask = 64'hCC00CC00CCC0CCC0;
defparam \A_SPW_TOP|SPW|RX|last_is_data~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y3_N53
dffeas \A_SPW_TOP|SPW|RX|last_is_data (
        .clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|RX|last_is_data~0_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(!\A_SPW_TOP|SPW|RX|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|last_is_data~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|last_is_data .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|last_is_data .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y3_N6
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|rx_got_nchar~0 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|rx_got_nchar~0_combout  = ( \A_SPW_TOP|SPW|RX|rx_got_nchar~q  & ( \A_SPW_TOP|SPW|RX|last_is_timec~q  ) ) # ( !\A_SPW_TOP|SPW|RX|rx_got_nchar~q  & ( \A_SPW_TOP|SPW|RX|last_is_timec~q  & ( \A_SPW_TOP|SPW|RX|last_is_data~q  ) ) ) # ( 
// \A_SPW_TOP|SPW|RX|rx_got_nchar~q  & ( !\A_SPW_TOP|SPW|RX|last_is_timec~q  & ( (\A_SPW_TOP|SPW|RX|last_is_control~q ) # (\A_SPW_TOP|SPW|RX|last_is_data~q ) ) ) ) # ( !\A_SPW_TOP|SPW|RX|rx_got_nchar~q  & ( !\A_SPW_TOP|SPW|RX|last_is_timec~q  & ( 
// \A_SPW_TOP|SPW|RX|last_is_data~q  ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|SPW|RX|last_is_data~q ),
        .datac(!\A_SPW_TOP|SPW|RX|last_is_control~q ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|SPW|RX|rx_got_nchar~q ),
        .dataf(!\A_SPW_TOP|SPW|RX|last_is_timec~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|rx_got_nchar~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_got_nchar~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|rx_got_nchar~0 .lut_mask = 64'h33333F3F3333FFFF;
defparam \A_SPW_TOP|SPW|RX|rx_got_nchar~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y3_N21
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|rx_got_nchar~feeder (
// Equation(s):
// \A_SPW_TOP|SPW|RX|rx_got_nchar~feeder_combout  = ( \A_SPW_TOP|SPW|RX|rx_got_nchar~0_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|rx_got_nchar~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|rx_got_nchar~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_got_nchar~feeder .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|rx_got_nchar~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|SPW|RX|rx_got_nchar~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y3_N23
dffeas \A_SPW_TOP|SPW|RX|rx_got_nchar (
        .clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(\A_SPW_TOP|SPW|RX|rx_got_nchar~feeder_combout ),
        .asdata(vcc),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|rx_got_nchar~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_got_nchar .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|rx_got_nchar .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y4_N24
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|state_fsm~24 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|state_fsm~24_combout  = ( \A_SPW_TOP|rx_data|overflow_credit_error~q  & ( \u0|link_disable|data_out~q  & ( (!\A_SPW_TOP|SPW|RX|rx_got_nchar~q  & (!\A_SPW_TOP|SPW|FSM|Equal0~3_combout  & \A_SPW_TOP|SPW|FSM|state_fsm.connecting~q )) ) ) ) 
// # ( !\A_SPW_TOP|rx_data|overflow_credit_error~q  & ( \u0|link_disable|data_out~q  & ( !\A_SPW_TOP|SPW|FSM|Equal0~3_combout  ) ) ) # ( \A_SPW_TOP|rx_data|overflow_credit_error~q  & ( !\u0|link_disable|data_out~q  & ( (!\A_SPW_TOP|SPW|RX|rx_got_nchar~q  & 
// (!\A_SPW_TOP|SPW|FSM|Equal0~3_combout  & \A_SPW_TOP|SPW|FSM|state_fsm.connecting~q )) ) ) ) # ( !\A_SPW_TOP|rx_data|overflow_credit_error~q  & ( !\u0|link_disable|data_out~q  & ( (!\A_SPW_TOP|SPW|FSM|Equal0~3_combout ) # 
// (\A_SPW_TOP|SPW|FSM|state_fsm.run~q ) ) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_got_nchar~q ),
        .datab(!\A_SPW_TOP|SPW|FSM|Equal0~3_combout ),
        .datac(!\A_SPW_TOP|SPW|FSM|state_fsm.connecting~q ),
        .datad(!\A_SPW_TOP|SPW|FSM|state_fsm.run~q ),
        .datae(!\A_SPW_TOP|rx_data|overflow_credit_error~q ),
        .dataf(!\u0|link_disable|data_out~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|state_fsm~24_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|state_fsm~24 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|state_fsm~24 .lut_mask = 64'hCCFF0808CCCC0808;
defparam \A_SPW_TOP|SPW|FSM|state_fsm~24 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y4_N21
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|state_fsm~22 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|state_fsm~22_combout  = ( \A_SPW_TOP|SPW|FSM|state_fsm.run~q  & ( \u0|link_disable|data_out~q  & ( (!\A_SPW_TOP|SPW|RX|rx_got_nchar~q  & (!\A_SPW_TOP|SPW|RX|rx_got_time_code~q  & (\A_SPW_TOP|SPW|RX|rx_got_fct_fsm~q  & 
// \A_SPW_TOP|SPW|FSM|state_fsm.connecting~q ))) ) ) ) # ( !\A_SPW_TOP|SPW|FSM|state_fsm.run~q  & ( \u0|link_disable|data_out~q  & ( (!\A_SPW_TOP|SPW|RX|rx_got_nchar~q  & (!\A_SPW_TOP|SPW|RX|rx_got_time_code~q  & (\A_SPW_TOP|SPW|RX|rx_got_fct_fsm~q  & 
// \A_SPW_TOP|SPW|FSM|state_fsm.connecting~q ))) ) ) ) # ( \A_SPW_TOP|SPW|FSM|state_fsm.run~q  & ( !\u0|link_disable|data_out~q  ) ) # ( !\A_SPW_TOP|SPW|FSM|state_fsm.run~q  & ( !\u0|link_disable|data_out~q  & ( (!\A_SPW_TOP|SPW|RX|rx_got_nchar~q  & 
// (!\A_SPW_TOP|SPW|RX|rx_got_time_code~q  & (\A_SPW_TOP|SPW|RX|rx_got_fct_fsm~q  & \A_SPW_TOP|SPW|FSM|state_fsm.connecting~q ))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_got_nchar~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_got_time_code~q ),
        .datac(!\A_SPW_TOP|SPW|RX|rx_got_fct_fsm~q ),
        .datad(!\A_SPW_TOP|SPW|FSM|state_fsm.connecting~q ),
        .datae(!\A_SPW_TOP|SPW|FSM|state_fsm.run~q ),
        .dataf(!\u0|link_disable|data_out~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|state_fsm~22_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|state_fsm~22 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|state_fsm~22 .lut_mask = 64'h0008FFFF00080008;
defparam \A_SPW_TOP|SPW|FSM|state_fsm~22 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y4_N48
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|state_fsm~23 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|state_fsm~23_combout  = ( \A_SPW_TOP|rx_data|overflow_credit_error~q  & ( !\A_SPW_TOP|SPW|RX|rx_error_d~q  & ( (!\A_SPW_TOP|SPW|RX|rx_error_c~q  & (\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~0_combout  & 
// !\A_SPW_TOP|SPW|RX|rx_got_time_code~q )) ) ) ) # ( !\A_SPW_TOP|rx_data|overflow_credit_error~q  & ( !\A_SPW_TOP|SPW|RX|rx_error_d~q  & ( (!\A_SPW_TOP|SPW|RX|rx_error_c~q  & (\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~0_combout  & 
// \A_SPW_TOP|SPW|FSM|state_fsm~22_combout )) ) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_error_c~q ),
        .datab(!\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~0_combout ),
        .datac(!\A_SPW_TOP|SPW|FSM|state_fsm~22_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_got_time_code~q ),
        .datae(!\A_SPW_TOP|rx_data|overflow_credit_error~q ),
        .dataf(!\A_SPW_TOP|SPW|RX|rx_error_d~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|state_fsm~23_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|state_fsm~23 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|state_fsm~23 .lut_mask = 64'h0202220000000000;
defparam \A_SPW_TOP|SPW|FSM|state_fsm~23 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y4_N9
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|state_fsm~25 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|state_fsm~25_combout  = ( \A_SPW_TOP|SPW|RX|rx_got_fct_fsm~q  & ( (\A_SPW_TOP|SPW|FSM|state_fsm.connecting~q  & (!\A_SPW_TOP|SPW|RX|rx_got_time_code~q  & !\A_SPW_TOP|SPW|RX|rx_got_nchar~q )) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|SPW|FSM|state_fsm.connecting~q ),
        .datac(!\A_SPW_TOP|SPW|RX|rx_got_time_code~q ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_got_nchar~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|rx_got_fct_fsm~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|state_fsm~25_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|state_fsm~25 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|state_fsm~25 .lut_mask = 64'h0000000030003000;
defparam \A_SPW_TOP|SPW|FSM|state_fsm~25 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y4_N0
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|state_fsm~19 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|state_fsm~19_combout  = ( \A_SPW_TOP|rx_data|overflow_credit_error~q  & ( \A_SPW_TOP|SPW|FSM|Equal1~2_combout  & ( (!\A_SPW_TOP|SPW|FSM|Equal0~3_combout  & (\A_SPW_TOP|SPW|FSM|state_fsm~23_combout  & 
// \A_SPW_TOP|SPW|FSM|state_fsm~25_combout )) ) ) ) # ( !\A_SPW_TOP|rx_data|overflow_credit_error~q  & ( \A_SPW_TOP|SPW|FSM|Equal1~2_combout  & ( (!\A_SPW_TOP|SPW|FSM|Equal0~3_combout  & (\A_SPW_TOP|SPW|FSM|state_fsm~23_combout  & 
// \A_SPW_TOP|SPW|FSM|state_fsm~25_combout )) ) ) ) # ( \A_SPW_TOP|rx_data|overflow_credit_error~q  & ( !\A_SPW_TOP|SPW|FSM|Equal1~2_combout  & ( (\A_SPW_TOP|SPW|FSM|state_fsm~24_combout  & (\A_SPW_TOP|SPW|FSM|state_fsm~23_combout  & 
// \A_SPW_TOP|SPW|FSM|state_fsm~25_combout )) ) ) ) # ( !\A_SPW_TOP|rx_data|overflow_credit_error~q  & ( !\A_SPW_TOP|SPW|FSM|Equal1~2_combout  & ( (\A_SPW_TOP|SPW|FSM|state_fsm~24_combout  & \A_SPW_TOP|SPW|FSM|state_fsm~23_combout ) ) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|state_fsm~24_combout ),
        .datab(!\A_SPW_TOP|SPW|FSM|Equal0~3_combout ),
        .datac(!\A_SPW_TOP|SPW|FSM|state_fsm~23_combout ),
        .datad(!\A_SPW_TOP|SPW|FSM|state_fsm~25_combout ),
        .datae(!\A_SPW_TOP|rx_data|overflow_credit_error~q ),
        .dataf(!\A_SPW_TOP|SPW|FSM|Equal1~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|state_fsm~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|state_fsm~19 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|state_fsm~19 .lut_mask = 64'h05050005000C000C;
defparam \A_SPW_TOP|SPW|FSM|state_fsm~19 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y4_N35
dffeas \A_SPW_TOP|SPW|FSM|state_fsm.run (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|FSM|state_fsm~19_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|FSM|state_fsm.run~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|state_fsm.run .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|state_fsm.run .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y4_N15
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|state_fsm.error_reset~0 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|state_fsm.error_reset~0_combout  = ( !\A_SPW_TOP|SPW|FSM|state_fsm.ready~q  & ( \A_SPW_TOP|SPW|FSM|state_fsm.started~q  & ( (!\A_SPW_TOP|SPW|FSM|state_fsm.run~q  & (\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q  & 
// (!\A_SPW_TOP|SPW|FSM|state_fsm.connecting~q  & !\A_SPW_TOP|SPW|FSM|state_fsm.error_wait~q ))) ) ) ) # ( \A_SPW_TOP|SPW|FSM|state_fsm.ready~q  & ( !\A_SPW_TOP|SPW|FSM|state_fsm.started~q  & ( (!\A_SPW_TOP|SPW|FSM|state_fsm.run~q  & 
// (\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q  & (!\A_SPW_TOP|SPW|FSM|state_fsm.connecting~q  & !\A_SPW_TOP|SPW|FSM|state_fsm.error_wait~q ))) ) ) ) # ( !\A_SPW_TOP|SPW|FSM|state_fsm.ready~q  & ( !\A_SPW_TOP|SPW|FSM|state_fsm.started~q  & ( 
// (!\A_SPW_TOP|SPW|FSM|state_fsm.run~q  & ((!\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q  & (!\A_SPW_TOP|SPW|FSM|state_fsm.connecting~q  & !\A_SPW_TOP|SPW|FSM|state_fsm.error_wait~q )) # (\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q  & 
// (!\A_SPW_TOP|SPW|FSM|state_fsm.connecting~q  $ (!\A_SPW_TOP|SPW|FSM|state_fsm.error_wait~q ))))) # (\A_SPW_TOP|SPW|FSM|state_fsm.run~q  & (\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q  & (!\A_SPW_TOP|SPW|FSM|state_fsm.connecting~q  & 
// !\A_SPW_TOP|SPW|FSM|state_fsm.error_wait~q ))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|state_fsm.run~q ),
        .datab(!\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q ),
        .datac(!\A_SPW_TOP|SPW|FSM|state_fsm.connecting~q ),
        .datad(!\A_SPW_TOP|SPW|FSM|state_fsm.error_wait~q ),
        .datae(!\A_SPW_TOP|SPW|FSM|state_fsm.ready~q ),
        .dataf(!\A_SPW_TOP|SPW|FSM|state_fsm.started~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|state_fsm.error_reset~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|state_fsm.error_reset~0 .lut_mask = 64'h9220200020000000;
defparam \A_SPW_TOP|SPW|FSM|state_fsm.error_reset~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y4_N51
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|state_fsm~11 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|state_fsm~11_combout  = ( !\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q  & ( (\A_SPW_TOP|SPW|FSM|Equal2~0_combout  & (\A_SPW_TOP|SPW|FSM|Equal2~1_combout  & \A_SPW_TOP|SPW|FSM|after64us [6])) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|Equal2~0_combout ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|FSM|Equal2~1_combout ),
        .datad(!\A_SPW_TOP|SPW|FSM|after64us [6]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|state_fsm~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|state_fsm~11 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|state_fsm~11 .lut_mask = 64'h0005000500000000;
defparam \A_SPW_TOP|SPW|FSM|state_fsm~11 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y4_N54
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|state_fsm~12 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|state_fsm~12_combout  = ( \A_SPW_TOP|SPW|FSM|state_fsm.error_wait~q  & ( (\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~0_combout  & (((\A_SPW_TOP|SPW|FSM|always0~0_combout  & !\A_SPW_TOP|SPW|FSM|Equal0~3_combout )) # 
// (\A_SPW_TOP|SPW|FSM|state_fsm~11_combout ))) ) ) # ( !\A_SPW_TOP|SPW|FSM|state_fsm.error_wait~q  & ( (\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~0_combout  & \A_SPW_TOP|SPW|FSM|state_fsm~11_combout ) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~0_combout ),
        .datab(!\A_SPW_TOP|SPW|FSM|always0~0_combout ),
        .datac(!\A_SPW_TOP|SPW|FSM|state_fsm~11_combout ),
        .datad(!\A_SPW_TOP|SPW|FSM|Equal0~3_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|FSM|state_fsm.error_wait~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|state_fsm~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|state_fsm~12 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|state_fsm~12 .lut_mask = 64'h0505050515051505;
defparam \A_SPW_TOP|SPW|FSM|state_fsm~12 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y4_N14
dffeas \A_SPW_TOP|SPW|FSM|state_fsm.error_wait (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|FSM|state_fsm~12_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|FSM|state_fsm.error_wait~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|state_fsm.error_wait .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|state_fsm.error_wait .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y4_N24
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|WideOr0 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|WideOr0~combout  = ( \A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q  & ( (!\A_SPW_TOP|SPW|FSM|state_fsm.error_wait~q  & !\A_SPW_TOP|SPW|FSM|state_fsm.ready~q ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|SPW|FSM|state_fsm.error_wait~q ),
        .datac(gnd),
        .datad(!\A_SPW_TOP|SPW|FSM|state_fsm.ready~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|FSM|WideOr0~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|WideOr0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|WideOr0 .lut_mask = 64'h00000000CC00CC00;
defparam \A_SPW_TOP|SPW|FSM|WideOr0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y4_N26
dffeas \A_SPW_TOP|SPW|FSM|send_null_tx (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|SPW|FSM|WideOr0~combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|FSM|send_null_tx~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|send_null_tx .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|send_null_tx .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X53_Y6_N27
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector63~3 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector63~3_combout  = ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c~q  & ( (!\A_SPW_TOP|SPW|TX|Equal0~3_combout ) # ((\A_SPW_TOP|SPW|FSM|send_null_tx~q  & (\A_SPW_TOP|SPW|FSM|enable_tx~q  & !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~q 
// ))) ) ) # ( !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c~q  & ( (\A_SPW_TOP|SPW|FSM|send_null_tx~q  & (\A_SPW_TOP|SPW|FSM|enable_tx~q  & !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~q )) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|send_null_tx~q ),
        .datab(!\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .datac(!\A_SPW_TOP|SPW|TX|Equal0~3_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector63~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector63~3 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector63~3 .lut_mask = 64'h11001100F1F0F1F0;
defparam \A_SPW_TOP|SPW|TX|Selector63~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X54_Y6_N3
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector64~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector64~0_combout  = ( \A_SPW_TOP|SPW|TX|global_counter_transfer [0] & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & (((!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~0_combout ) # (!\A_SPW_TOP|SPW|TX|Selector62~1_combout )) # 
// (\A_SPW_TOP|SPW|TX|Selector63~3_combout ))) ) ) # ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & ( (\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & (((!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~0_combout ) # (!\A_SPW_TOP|SPW|TX|Selector62~1_combout )) # 
// (\A_SPW_TOP|SPW|TX|Selector63~3_combout ))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|Selector63~3_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~0_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|Selector62~1_combout ),
        .datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector64~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector64~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector64~0 .lut_mask = 64'h00FD00FDFD00FD00;
defparam \A_SPW_TOP|SPW|TX|Selector64~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X54_Y6_N23
dffeas \A_SPW_TOP|SPW|TX|global_counter_transfer[1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|Selector64~0_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|global_counter_transfer[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|global_counter_transfer[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X54_Y6_N33
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Equal0~4 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Equal0~4_combout  = ( \A_SPW_TOP|SPW|TX|global_counter_transfer [0] & ( (\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & (!\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & !\A_SPW_TOP|SPW|TX|global_counter_transfer [3])) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
        .datab(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
        .datac(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Equal0~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Equal0~4 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Equal0~4 .lut_mask = 64'h0000000040404040;
defparam \A_SPW_TOP|SPW|TX|Equal0~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X51_Y6_N33
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector73~1 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector73~1_combout  = ( \A_SPW_TOP|SPW|TX|state_tx~19_combout  & ( !\A_SPW_TOP|SPW|TX|Equal0~4_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|TX|Equal0~4_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|state_tx~19_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector73~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector73~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector73~1 .lut_mask = 64'h00000000F0F0F0F0;
defparam \A_SPW_TOP|SPW|TX|Selector73~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X51_Y6_N24
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector60~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector60~0_combout  = ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct_c~q  & ( \A_SPW_TOP|SPW|TX|LessThan6~1_combout  & ( (((!\A_SPW_TOP|SPW|TX|Equal0~5_combout  & \A_SPW_TOP|SPW|TX|Selector63~0_combout )) # (\A_SPW_TOP|SPW|TX|ready_tx_data~q 
// )) # (\A_SPW_TOP|SPW|TX|Selector73~1_combout ) ) ) ) # ( !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct_c~q  & ( \A_SPW_TOP|SPW|TX|LessThan6~1_combout  & ( ((\A_SPW_TOP|SPW|TX|Selector63~0_combout  & ((!\A_SPW_TOP|SPW|TX|Equal0~5_combout ) # 
// (\A_SPW_TOP|SPW|TX|ready_tx_data~q )))) # (\A_SPW_TOP|SPW|TX|Selector73~1_combout ) ) ) ) # ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct_c~q  & ( !\A_SPW_TOP|SPW|TX|LessThan6~1_combout  & ( (\A_SPW_TOP|SPW|TX|ready_tx_data~q ) # 
// (\A_SPW_TOP|SPW|TX|Selector73~1_combout ) ) ) ) # ( !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct_c~q  & ( !\A_SPW_TOP|SPW|TX|LessThan6~1_combout  & ( ((\A_SPW_TOP|SPW|TX|Equal0~5_combout  & (\A_SPW_TOP|SPW|TX|ready_tx_data~q  & 
// \A_SPW_TOP|SPW|TX|Selector63~0_combout ))) # (\A_SPW_TOP|SPW|TX|Selector73~1_combout ) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|Selector73~1_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|Equal0~5_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|ready_tx_data~q ),
        .datad(!\A_SPW_TOP|SPW|TX|Selector63~0_combout ),
        .datae(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct_c~q ),
        .dataf(!\A_SPW_TOP|SPW|TX|LessThan6~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector60~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector60~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector60~0 .lut_mask = 64'h55575F5F55DF5FDF;
defparam \A_SPW_TOP|SPW|TX|Selector60~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X54_Y6_N17
dffeas \A_SPW_TOP|SPW|TX|ready_tx_data (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|Selector60~0_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|ready_tx_data~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|ready_tx_data .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|ready_tx_data .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X51_Y6_N21
cyclonev_lcell_comb \A_SPW_TOP|tx_data|state_data_read~13 (
// Equation(s):
// \A_SPW_TOP|tx_data|state_data_read~13_combout  = ( \A_SPW_TOP|tx_data|state_data_read.00~q  & ( (!\A_SPW_TOP|SPW|TX|ready_tx_data~q  & (!\A_SPW_TOP|tx_data|state_data_read.01~q  & (\A_SPW_TOP|tx_data|state_data_read.10~q  & 
// !\A_SPW_TOP|tx_data|state_data_read.11~q ))) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|ready_tx_data~q ),
        .datab(!\A_SPW_TOP|tx_data|state_data_read.01~q ),
        .datac(!\A_SPW_TOP|tx_data|state_data_read.10~q ),
        .datad(!\A_SPW_TOP|tx_data|state_data_read.11~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|state_data_read.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|state_data_read~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|state_data_read~13 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|state_data_read~13 .lut_mask = 64'h0000000008000800;
defparam \A_SPW_TOP|tx_data|state_data_read~13 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X51_Y6_N29
dffeas \A_SPW_TOP|tx_data|state_data_read.11 (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|state_data_read~13_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|state_data_read.11~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|state_data_read.11 .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|state_data_read.11 .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X51_Y6_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|state_data_read~12 (
// Equation(s):
// \A_SPW_TOP|tx_data|state_data_read~12_combout  = ( \A_SPW_TOP|tx_data|f_empty~q  & ( \A_SPW_TOP|tx_data|state_data_read.00~q  & ( (!\A_SPW_TOP|tx_data|state_data_read.11~q  & (\A_SPW_TOP|tx_data|state_data_read.10~q  & (\A_SPW_TOP|SPW|TX|ready_tx_data~q  
// & !\A_SPW_TOP|tx_data|state_data_read.01~q ))) ) ) ) # ( !\A_SPW_TOP|tx_data|f_empty~q  & ( \A_SPW_TOP|tx_data|state_data_read.00~q  & ( (!\A_SPW_TOP|tx_data|state_data_read.11~q  & (\A_SPW_TOP|SPW|TX|ready_tx_data~q  & 
// (!\A_SPW_TOP|tx_data|state_data_read.10~q  $ (!\A_SPW_TOP|tx_data|state_data_read.01~q )))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_read.11~q ),
        .datab(!\A_SPW_TOP|tx_data|state_data_read.10~q ),
        .datac(!\A_SPW_TOP|SPW|TX|ready_tx_data~q ),
        .datad(!\A_SPW_TOP|tx_data|state_data_read.01~q ),
        .datae(!\A_SPW_TOP|tx_data|f_empty~q ),
        .dataf(!\A_SPW_TOP|tx_data|state_data_read.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|state_data_read~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|state_data_read~12 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|state_data_read~12 .lut_mask = 64'h0000000002080200;
defparam \A_SPW_TOP|tx_data|state_data_read~12 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X51_Y6_N41
dffeas \A_SPW_TOP|tx_data|state_data_read.10 (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|state_data_read~12_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|state_data_read.10~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|state_data_read.10 .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|state_data_read.10 .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y10_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|always3~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|always3~0_combout  = ( !\A_SPW_TOP|SPW|TX|ready_tx_data~q  & ( \A_SPW_TOP|tx_data|state_data_read.10~q  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|tx_data|state_data_read.10~q ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|SPW|TX|ready_tx_data~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|always3~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|always3~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|always3~0 .lut_mask = 64'h0F0F00000F0F0000;
defparam \A_SPW_TOP|tx_data|always3~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X36_Y10_N47
dffeas \A_SPW_TOP|tx_data|counter_reader[0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|counter_reader[0]~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|tx_data|always3~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|counter_reader [0]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|counter_reader[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|counter_reader[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X36_Y10_N51
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Add2~2 (
// Equation(s):
// \A_SPW_TOP|tx_data|Add2~2_combout  = ( \A_SPW_TOP|tx_data|counter_reader [1] & ( !\A_SPW_TOP|tx_data|counter_reader [3] $ (((!\A_SPW_TOP|tx_data|counter_reader [0]) # (!\A_SPW_TOP|tx_data|counter_reader [2]))) ) ) # ( !\A_SPW_TOP|tx_data|counter_reader 
// [1] & ( \A_SPW_TOP|tx_data|counter_reader [3] ) )

        .dataa(!\A_SPW_TOP|tx_data|counter_reader [3]),
        .datab(gnd),
        .datac(!\A_SPW_TOP|tx_data|counter_reader [0]),
        .datad(!\A_SPW_TOP|tx_data|counter_reader [2]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|counter_reader [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Add2~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Add2~2 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Add2~2 .lut_mask = 64'h55555555555A555A;
defparam \A_SPW_TOP|tx_data|Add2~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X36_Y10_N35
dffeas \A_SPW_TOP|tx_data|counter_reader[3] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Add2~2_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|tx_data|always3~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|counter_reader [3]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|counter_reader[3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|counter_reader[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X36_Y10_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Add2~3 (
// Equation(s):
// \A_SPW_TOP|tx_data|Add2~3_combout  = ( \A_SPW_TOP|tx_data|counter_reader [2] & ( !\A_SPW_TOP|tx_data|counter_reader [4] $ (((!\A_SPW_TOP|tx_data|counter_reader [3]) # ((!\A_SPW_TOP|tx_data|counter_reader [1]) # (!\A_SPW_TOP|tx_data|counter_reader [0])))) 
// ) ) # ( !\A_SPW_TOP|tx_data|counter_reader [2] & ( \A_SPW_TOP|tx_data|counter_reader [4] ) )

        .dataa(!\A_SPW_TOP|tx_data|counter_reader [3]),
        .datab(!\A_SPW_TOP|tx_data|counter_reader [1]),
        .datac(!\A_SPW_TOP|tx_data|counter_reader [4]),
        .datad(!\A_SPW_TOP|tx_data|counter_reader [0]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|tx_data|counter_reader [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Add2~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Add2~3 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Add2~3 .lut_mask = 64'h0F0F0F0F0F1E0F1E;
defparam \A_SPW_TOP|tx_data|Add2~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X36_Y10_N56
dffeas \A_SPW_TOP|tx_data|counter_reader[4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Add2~3_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|tx_data|always3~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|counter_reader [4]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|counter_reader[4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|counter_reader[4] .power_up = "low";
// synopsys translate_on

// Location: FF_X36_Y10_N14
dffeas \A_SPW_TOP|tx_data|counter[4] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|tx_data|Add3~17_sumout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|counter [4]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|counter[4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|counter[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X36_Y10_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Equal0~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Equal0~0_combout  = ( \A_SPW_TOP|tx_data|counter [1] & ( \A_SPW_TOP|tx_data|counter [2] & ( (\A_SPW_TOP|tx_data|counter [4] & (\A_SPW_TOP|tx_data|counter [5] & (\A_SPW_TOP|tx_data|counter [0] & \A_SPW_TOP|tx_data|counter [3]))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|counter [4]),
        .datab(!\A_SPW_TOP|tx_data|counter [5]),
        .datac(!\A_SPW_TOP|tx_data|counter [0]),
        .datad(!\A_SPW_TOP|tx_data|counter [3]),
        .datae(!\A_SPW_TOP|tx_data|counter [1]),
        .dataf(!\A_SPW_TOP|tx_data|counter [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Equal0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Equal0~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Equal0~0 .lut_mask = 64'h0000000000000001;
defparam \A_SPW_TOP|tx_data|Equal0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X36_Y10_N20
dffeas \A_SPW_TOP|tx_data|f_full (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|tx_data|Equal0~0_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|f_full~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|f_full .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|f_full .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y20_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|src_payload~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|src_payload~0_combout  = (\u0|hps_0|fpga_interfaces|h2f_WDATA [0] & \u0|mm_interconnect_0|cmd_mux_011|saved_grant [0])

        .dataa(gnd),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_WDATA [0]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_011|src_payload~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|src_payload~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|src_payload~0 .lut_mask = 64'h0303030303030303;
defparam \u0|mm_interconnect_0|cmd_mux_011|src_payload~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y20_N23
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_011|src_payload~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y20_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|src_data[81] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|src_data [81] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout  & ( (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~0_combout ) ) ) 
// # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout  & ( ((\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~0_combout )) # (\u0|mm_interconnect_0|cmd_mux_011|saved_grant 
// [1]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_011|src_data [81]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[81] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[81] .lut_mask = 64'h7755775533003300;
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[81] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y20_N53
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_011|src_data [81]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y20_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2] = ( \u0|mm_interconnect_0|cmd_mux_011|src_data [81] & ( 
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] & 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_011|src_data [81] & ( 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout  & ((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]) # 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_011|src_data [81]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .lut_mask = 64'h00F500F500A000A0;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y20_N44
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y20_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|src_data[86] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|src_data [86] = ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [0] & ( ((\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [0])) # (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0] & ( (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
        .datac(gnd),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_011|src_data [86]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[86] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[86] .lut_mask = 64'h0055005533773377;
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[86] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y20_N29
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_011|src_data [86]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X18_Y20_N32
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_011|src_data [87]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X18_Y20_N2
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_011|src_data [88]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y20_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  = ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & ( 
// \u0|mm_interconnect_0|cmd_mux_011|src_data [88] & ( (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]) ) ) ) # ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & ( 
// !\u0|mm_interconnect_0|cmd_mux_011|src_data [88] & ( (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & \u0|mm_interconnect_0|cmd_mux_011|src_data [87]) ) ) ) # ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & ( !\u0|mm_interconnect_0|cmd_mux_011|src_data [88] & ( 
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]))) # 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|cmd_mux_011|src_data [87])) ) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_011|src_data [87]),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_011|src_data [88]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .lut_mask = 64'h1B1B11110A0A0000;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y20_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  & ( 
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) # 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|cmd_mux_011|src_data [86]))) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_011|src_data [86]),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .lut_mask = 64'h00000000ACACACAC;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y20_N38
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .power_up = "low";
// synopsys translate_on

// Location: FF_X17_Y20_N22
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y20_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|src_data[80] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|src_data [80] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~0_combout  & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~1_combout  & \u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]) ) ) 
// # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~0_combout  & ( ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~1_combout  & \u0|mm_interconnect_0|cmd_mux_011|saved_grant [1])) # (\u0|mm_interconnect_0|cmd_mux_011|saved_grant 
// [0]) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~1_combout ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~0_combout ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_011|src_data [80]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[80] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[80] .lut_mask = 64'h3737050537370505;
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[80] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y20_N26
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_011|src_data [80]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y20_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1] = ( \u0|mm_interconnect_0|cmd_mux_011|src_data [80] & ( 
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1] & 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_011|src_data [80] & ( 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout  & ((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]) # 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_011|src_data [80]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .lut_mask = 64'h00F300F300C000C0;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y20_N20
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y21_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout  & ( 
// ((\u0|hps_0|fpga_interfaces|h2f_ARADDR [1] & \u0|mm_interconnect_0|cmd_mux_011|saved_grant [1])) # (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout  & 
// ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [1] & \u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [1]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y20_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & ( 
// (!\u0|mm_interconnect_0|cmd_mux_011|src_data [88] & (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & !\u0|mm_interconnect_0|cmd_mux_011|src_data [87])) ) ) # ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & ( (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2])))) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (!\u0|mm_interconnect_0|cmd_mux_011|src_data [88] & ((!\u0|mm_interconnect_0|cmd_mux_011|src_data [87])))) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_011|src_data [88]),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_011|src_data [87]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .lut_mask = 64'hE2C0E2C022002200;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y20_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  & ( 
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) # 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((\u0|mm_interconnect_0|cmd_mux_011|src_data [86]))) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_011|src_data [86]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .lut_mask = 64'h0000000047474747;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y20_N17
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y20_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  = ( 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  & ( (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ((!\u0|mm_interconnect_0|cmd_mux_011|src_data [86]))) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_011|src_data [86]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .lut_mask = 64'h00000000B8B8B8B8;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y20_N13
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y20_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|src_data[79] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|src_data [79] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout  & ( (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~2_combout ) ) ) 
// # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout  & ( ((\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~2_combout )) # (\u0|mm_interconnect_0|cmd_mux_011|saved_grant 
// [0]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~2_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_011|src_data [79]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[79] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[79] .lut_mask = 64'h7373737350505050;
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[79] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y20_N32
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_011|src_data [79]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y20_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout  = SUM(( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) + ( 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14  = CARRY(( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) + ( 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
        .cout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .lut_mask = 64'h0000CCCC000000FF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y20_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0] = ( \u0|mm_interconnect_0|cmd_mux_011|src_data [79] & ( 
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0] & 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_011|src_data [79] & ( 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout  & ((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]) # 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_011|src_data [79]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .lut_mask = 64'h00F500F500A000A0;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y20_N47
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y20_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout  & ( 
// ((\u0|hps_0|fpga_interfaces|h2f_ARADDR [0] & \u0|mm_interconnect_0|cmd_mux_011|saved_grant [1])) # (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout  & 
// ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [0] & \u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [0]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .lut_mask = 64'h000F000F333F333F;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y20_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout  = ( 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  & ( 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  & ( 
// (((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0] & \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout )) # 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0])) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) ) # ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  & ( 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  & ( 
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0] & 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout )) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]))) ) ) ) # ( 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  & ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  & ( 
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0] & 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout )) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]))) ) ) ) # ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  & ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  & ( 
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0] & 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout )) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]))) ) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
        .datae(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 .lut_mask = 64'h02AA02AA02AA57FF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y20_N55
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y20_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout  = SUM(( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + ( 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14  ))
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10  = CARRY(( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + ( 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14  ))

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
        .cout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .lut_mask = 64'h0000F0F000005555;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y20_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout  & ( 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  & ( (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1])) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]))) # 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout )))) ) 
// ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout  & ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  & ( 
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1])) # 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ))) ) ) 
// ) # ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout  & ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  & ( 
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]) # 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]))) ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout  & ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  & ( (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]) ) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
        .datae(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .lut_mask = 64'h0C0C4C4C0C3F4C7F;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y20_N37
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y20_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout  = SUM(( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + ( 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10  ))
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6  = CARRY(( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + ( 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10  ))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
        .cout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .lut_mask = 64'h0000FF0000003333;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y20_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout  & ( 
// ((\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [2])) # (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout  & 
// ( (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [2]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [2]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 .lut_mask = 64'h0505050537373737;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y20_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout  & ( 
// (((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] & \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout )) # 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2])) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) # ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout  & ( (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] & \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout )) # 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]))) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 .lut_mask = 64'h0C4C0C4C3F7F3F7F;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y20_N41
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y20_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|src_data[82] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|src_data [82] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout  & ( ((\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout )) # 
// (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout  & ( (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] & 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_011|src_data [82]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[82] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[82] .lut_mask = 64'h0F000F005F555F55;
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[82] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y20_N35
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_011|src_data [82]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y20_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout  & ( 
// ((\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [3])) # (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout  & 
// ( (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [3]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [3]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .lut_mask = 64'h0303030357575757;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y20_N8
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y20_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  & ( 
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) # 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((\u0|mm_interconnect_0|cmd_mux_011|src_data [86]))) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_011|src_data [86]),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .lut_mask = 64'h00000000550F550F;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y20_N40
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y20_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout  = SUM(( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3] ) + ( 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3] ) + ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y20_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3] = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout  & ( 
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3])) # 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|cmd_mux_011|src_data [82]))) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_011|src_data [82]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .lut_mask = 64'h00000000D8D8D8D8;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y20_N31
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y20_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3] & ( 
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3] & ( (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3] & ((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout )))) # 
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .lut_mask = 64'h05270527AFAFAFAF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y20_N1
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y20_N0
cyclonev_lcell_comb \u0|write_en_tx|always0~0 (
// Equation(s):
// \u0|write_en_tx|always0~0_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_agent|m0_write~combout  & ( (!\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [1] & 
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & (!\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [0] & 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]))) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [1]),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [0]),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent|m0_write~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|write_en_tx|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|write_en_tx|always0~0 .extended_lut = "off";
defparam \u0|write_en_tx|always0~0 .lut_mask = 64'h0000000080008000;
defparam \u0|write_en_tx|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y20_N56
dffeas \u0|write_en_tx|data_out (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [0]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|write_en_tx|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|write_en_tx|data_out~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|write_en_tx|data_out .is_wysiwyg = "true";
defparam \u0|write_en_tx|data_out .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y9_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|state_data_write~7 (
// Equation(s):
// \A_SPW_TOP|tx_data|state_data_write~7_combout  = ( \u0|write_en_tx|data_out~q  & ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|state_data_write.10~q  & \A_SPW_TOP|tx_data|state_data_write.01~q ) ) ) ) # ( !\u0|write_en_tx|data_out~q 
//  & ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|state_data_write.10~q  & \A_SPW_TOP|tx_data|state_data_write.01~q ) ) ) ) # ( \u0|write_en_tx|data_out~q  & ( !\A_SPW_TOP|tx_data|state_data_write.00~q  & ( 
// (!\A_SPW_TOP|tx_data|f_full~q  & (!\A_SPW_TOP|tx_data|state_data_write.10~q  & !\A_SPW_TOP|tx_data|state_data_write.01~q )) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|f_full~q ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.10~q ),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .datad(gnd),
        .datae(!\u0|write_en_tx|data_out~q ),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|state_data_write~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|state_data_write~7 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|state_data_write~7 .lut_mask = 64'h000080800C0C0C0C;
defparam \A_SPW_TOP|tx_data|state_data_write~7 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y9_N11
dffeas \A_SPW_TOP|tx_data|state_data_write.00 (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|state_data_write~7_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|state_data_write.00 .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|state_data_write.00 .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y9_N45
cyclonev_lcell_comb \A_SPW_TOP|tx_data|state_data_write~8 (
// Equation(s):
// \A_SPW_TOP|tx_data|state_data_write~8_combout  = ( !\A_SPW_TOP|tx_data|state_data_write.10~q  & ( \A_SPW_TOP|tx_data|f_full~q  & ( (\A_SPW_TOP|tx_data|state_data_write.01~q  & (\A_SPW_TOP|tx_data|state_data_write.00~q  & \u0|write_en_tx|data_out~q )) ) ) 
// ) # ( !\A_SPW_TOP|tx_data|state_data_write.10~q  & ( !\A_SPW_TOP|tx_data|f_full~q  & ( (\u0|write_en_tx|data_out~q  & (!\A_SPW_TOP|tx_data|state_data_write.01~q  $ (\A_SPW_TOP|tx_data|state_data_write.00~q ))) ) ) )

        .dataa(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datac(gnd),
        .datad(!\u0|write_en_tx|data_out~q ),
        .datae(!\A_SPW_TOP|tx_data|state_data_write.10~q ),
        .dataf(!\A_SPW_TOP|tx_data|f_full~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|state_data_write~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|state_data_write~8 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|state_data_write~8 .lut_mask = 64'h0099000000110000;
defparam \A_SPW_TOP|tx_data|state_data_write~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y9_N44
dffeas \A_SPW_TOP|tx_data|state_data_write.01 (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|state_data_write~8_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|state_data_write.01 .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|state_data_write.01 .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X49_Y9_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|state_data_write~9 (
// Equation(s):
// \A_SPW_TOP|tx_data|state_data_write~9_combout  = ( !\u0|write_en_tx|data_out~q  & ( \A_SPW_TOP|tx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|tx_data|state_data_write.10~q  & \A_SPW_TOP|tx_data|state_data_write.01~q ) ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|tx_data|state_data_write.10~q ),
        .datac(!\A_SPW_TOP|tx_data|state_data_write.01~q ),
        .datad(gnd),
        .datae(!\u0|write_en_tx|data_out~q ),
        .dataf(!\A_SPW_TOP|tx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|state_data_write~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|state_data_write~9 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|state_data_write~9 .lut_mask = 64'h000000000C0C0000;
defparam \A_SPW_TOP|tx_data|state_data_write~9 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y9_N35
dffeas \A_SPW_TOP|tx_data|state_data_write.10 (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|state_data_write~9_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|state_data_write.10~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|state_data_write.10 .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|state_data_write.10 .power_up = "low";
// synopsys translate_on

// Location: FF_X37_Y10_N44
dffeas \A_SPW_TOP|tx_data|counter_writer[0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|counter_writer[0]~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|tx_data|state_data_write.10~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|counter_writer [0]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|counter_writer[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|counter_writer[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y10_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Add1~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Add1~0_combout  = !\A_SPW_TOP|tx_data|counter_writer [1] $ (!\A_SPW_TOP|tx_data|counter_writer [0])

        .dataa(!\A_SPW_TOP|tx_data|counter_writer [1]),
        .datab(gnd),
        .datac(!\A_SPW_TOP|tx_data|counter_writer [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|tx_data|Add1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Add1~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Add1~0 .lut_mask = 64'h5A5A5A5A5A5A5A5A;
defparam \A_SPW_TOP|tx_data|Add1~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y10_N35
dffeas \A_SPW_TOP|tx_data|counter_writer[1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|tx_data|Add1~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|tx_data|state_data_write.10~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|counter_writer [1]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|counter_writer[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|counter_writer[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X36_Y10_N5
dffeas \A_SPW_TOP|tx_data|counter[1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|tx_data|Add3~5_sumout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|tx_data|counter [1]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|counter[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|counter[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y14_N42
cyclonev_lcell_comb \u0|counter_tx_fifo|read_mux_out[1]~1 (
// Equation(s):
// \u0|counter_tx_fifo|read_mux_out[1]~1_combout  = ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( \A_SPW_TOP|tx_data|counter [1] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|tx_data|counter [1]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|counter_tx_fifo|read_mux_out[1]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|counter_tx_fifo|read_mux_out[1]~1 .extended_lut = "off";
defparam \u0|counter_tx_fifo|read_mux_out[1]~1 .lut_mask = 64'h0F0F000000000000;
defparam \u0|counter_tx_fifo|read_mux_out[1]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y14_N43
dffeas \u0|counter_tx_fifo|readdata[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|counter_tx_fifo|read_mux_out[1]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|counter_tx_fifo|readdata [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|counter_tx_fifo|readdata[1] .is_wysiwyg = "true";
defparam \u0|counter_tx_fifo|readdata[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X27_Y15_N38
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|counter_tx_fifo|readdata [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X27_Y15_N26
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y15_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~1_combout  = (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [1] & ((\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [1]))) # 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [1] & (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][1]~q ))

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][1]~q ),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~1 .lut_mask = 64'h1D1D1D1D1D1D1D1D;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y15_N13
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y15_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~35 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~35_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0] & ( 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][1]~q  & !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ) ) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0] & ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0] & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [1] & !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ) ) ) ) # ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0] & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0] & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][1]~q  & 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ) ) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0] & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0] & ( 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][1]~q  & !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [1]),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][1]~q ),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0]),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~35_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~35 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~35 .lut_mask = 64'h3030303050503030;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~35 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y15_N0
cyclonev_lcell_comb \u0|write_data_fifo_tx|readdata[1] (
// Equation(s):
// \u0|write_data_fifo_tx|readdata [1] = ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & \u0|write_data_fifo_tx|data_out [1]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datac(gnd),
        .datad(!\u0|write_data_fifo_tx|data_out [1]),
        .datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|write_data_fifo_tx|readdata [1]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|write_data_fifo_tx|readdata[1] .extended_lut = "off";
defparam \u0|write_data_fifo_tx|readdata[1] .lut_mask = 64'h00CC000000CC0000;
defparam \u0|write_data_fifo_tx|readdata[1] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y15_N2
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|write_data_fifo_tx|readdata [1]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X25_Y15_N29
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y14_N57
cyclonev_lcell_comb \u0|fsm_info|read_mux_out[1]~1 (
// Equation(s):
// \u0|fsm_info|read_mux_out[1]~1_combout  = ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & ( (\A_SPW_TOP|SPW|FSM|state_fsm.ready~q  & 
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]) ) )

        .dataa(!\A_SPW_TOP|SPW|FSM|state_fsm.ready~q ),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|fsm_info|read_mux_out[1]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|fsm_info|read_mux_out[1]~1 .extended_lut = "off";
defparam \u0|fsm_info|read_mux_out[1]~1 .lut_mask = 64'h5500550000000000;
defparam \u0|fsm_info|read_mux_out[1]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y14_N59
dffeas \u0|fsm_info|readdata[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|fsm_info|read_mux_out[1]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|fsm_info|readdata [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|fsm_info|readdata[1] .is_wysiwyg = "true";
defparam \u0|fsm_info|readdata[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X31_Y14_N20
dffeas \u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|fsm_info|readdata [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y15_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~1 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~1_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre [1] & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [1]) # 
// (\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][1]~q ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre [1] & ( (\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][1]~q ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][1]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~1 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y15_N19
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y15_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~34 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~34_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0] & ( 
// (\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][1]~q  & !\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout ) ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0] & ( 
// \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0] & ( (\u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre [1] & !\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout ) ) ) ) # ( 
// \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0] & ( !\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0] & ( (\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][1]~q  & 
// !\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout ) ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0] & ( !\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0] & ( 
// (\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][1]~q  & !\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout ) ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][1]~q ),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre [1]),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout ),
        .datae(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0]),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~34_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~34 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~34 .lut_mask = 64'h330033000F003300;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~34 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X31_Y14_N0
cyclonev_lcell_comb \u0|counter_rx_fifo|read_mux_out[1]~1 (
// Equation(s):
// \u0|counter_rx_fifo|read_mux_out[1]~1_combout  = ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & ( 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & \A_SPW_TOP|rx_data|counter [1]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datac(!\A_SPW_TOP|rx_data|counter [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|counter_rx_fifo|read_mux_out[1]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|counter_rx_fifo|read_mux_out[1]~1 .extended_lut = "off";
defparam \u0|counter_rx_fifo|read_mux_out[1]~1 .lut_mask = 64'h0C0C0C0C00000000;
defparam \u0|counter_rx_fifo|read_mux_out[1]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y14_N1
dffeas \u0|counter_rx_fifo|readdata[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|counter_rx_fifo|read_mux_out[1]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|counter_rx_fifo|readdata [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|counter_rx_fifo|readdata[1] .is_wysiwyg = "true";
defparam \u0|counter_rx_fifo|readdata[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X31_Y15_N58
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|counter_rx_fifo|readdata [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X31_Y15_N29
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y15_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~1_combout  = (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [1] & ((\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [1]))) # 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [1] & (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][1]~q ))

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][1]~q ),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [1]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [1]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~1 .lut_mask = 64'h11DD11DD11DD11DD;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y15_N38
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y15_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~36 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~36_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0] & ( 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout  & \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][1]~q ) ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0] & ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout  & \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][1]~q ) ) ) ) # ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0] & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [1] & 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ) ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0] & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0] & ( 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout  & \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][1]~q ) ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [1]),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][1]~q ),
        .datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0]),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~36_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~36 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~36 .lut_mask = 64'h00CC444400CC00CC;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~36 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y15_N44
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y15_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~1_combout  = (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1] & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [1])) # 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1] & ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][1]~q )))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [1]),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][1]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~1 .lut_mask = 64'h0C3F0C3F0C3F0C3F;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y15_N25
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y15_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~242 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~242_combout  = ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout  & ( ((((\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout  & 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][1]~q )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~36_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~34_combout )) # 
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~35_combout ) ) ) # ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout  & ( ((((\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout  & 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [1])) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~36_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~34_combout )) # 
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~35_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ),
        .datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~35_combout ),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [1]),
        .datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~34_combout ),
        .datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout ),
        .dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~36_combout ),
        .datag(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][1]~q ),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~242_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~242 .extended_lut = "on";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~242 .lut_mask = 64'h37FF37FFFFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~242 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X54_Y9_N9
cyclonev_lcell_comb \m_x|rx_got_time_code~1 (
// Equation(s):
// \m_x|rx_got_time_code~1_combout  = ( \m_x|rx_got_time_code~0_combout  & ( (!\m_x|always10~0_combout  & (((\m_x|rx_got_time_code~q ) # (\m_x|last_is_data~q )))) # (\m_x|always10~0_combout  & (\m_x|always10~1_combout  & (\m_x|last_is_data~q ))) ) ) # ( 
// !\m_x|rx_got_time_code~0_combout  & ( (!\m_x|always10~0_combout  & (!\m_x|last_is_data~q  & \m_x|rx_got_time_code~q )) ) )

        .dataa(!\m_x|always10~0_combout ),
        .datab(!\m_x|always10~1_combout ),
        .datac(!\m_x|last_is_data~q ),
        .datad(!\m_x|rx_got_time_code~q ),
        .datae(!\m_x|rx_got_time_code~0_combout ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|rx_got_time_code~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|rx_got_time_code~1 .extended_lut = "off";
defparam \m_x|rx_got_time_code~1 .lut_mask = 64'h00A00BAB00A00BAB;
defparam \m_x|rx_got_time_code~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X54_Y9_N44
dffeas \m_x|rx_got_time_code (
        .clk(!\m_x|always3~0_combout ),
        .d(gnd),
        .asdata(\m_x|rx_got_time_code~1_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|rx_got_time_code~q ),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|rx_got_time_code .is_wysiwyg = "true";
defparam \m_x|rx_got_time_code .power_up = "low";
// synopsys translate_on

// Location: FF_X51_Y9_N34
dffeas \m_x|info[1] (
        .clk(!\m_x|always3~0_combout ),
        .d(gnd),
        .asdata(\m_x|rx_got_time_code~q ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\m_x|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|info [1]),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|info[1] .is_wysiwyg = "true";
defparam \m_x|info[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y13_N39
cyclonev_lcell_comb \u0|data_info|read_mux_out[1] (
// Equation(s):
// \u0|data_info|read_mux_out [1] = ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( (\m_x|info [1] & 
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]) ) )

        .dataa(!\m_x|info [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|data_info|read_mux_out [1]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|data_info|read_mux_out[1] .extended_lut = "off";
defparam \u0|data_info|read_mux_out[1] .lut_mask = 64'h5050505000000000;
defparam \u0|data_info|read_mux_out[1] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y13_N41
dffeas \u0|data_info|readdata[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|data_info|read_mux_out [1]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|data_info|readdata [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|data_info|readdata[1] .is_wysiwyg = "true";
defparam \u0|data_info|readdata[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X31_Y16_N11
dffeas \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|data_info|readdata [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y17_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|src_payload~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|src_payload~1_combout  = ( \u0|hps_0|fpga_interfaces|h2f_WDATA [1] & ( \u0|mm_interconnect_0|cmd_mux|saved_grant [0] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_WDATA [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux|src_payload~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|src_payload~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|src_payload~1 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux|src_payload~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y17_N17
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux|src_payload~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y17_N33
cyclonev_lcell_comb \u0|led_pio_test|data_out[1]~_Duplicate_1feeder (
// Equation(s):
// \u0|led_pio_test|data_out[1]~_Duplicate_1feeder_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [1] )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|led_pio_test|data_out[1]~_Duplicate_1feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|led_pio_test|data_out[1]~_Duplicate_1feeder .extended_lut = "off";
defparam \u0|led_pio_test|data_out[1]~_Duplicate_1feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|led_pio_test|data_out[1]~_Duplicate_1feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y17_N35
dffeas \u0|led_pio_test|data_out[1]~_Duplicate_1 (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|led_pio_test|data_out[1]~_Duplicate_1feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|led_pio_test|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|led_pio_test|data_out[1]~_Duplicate_1_q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|led_pio_test|data_out[1]~_Duplicate_1 .is_wysiwyg = "true";
defparam \u0|led_pio_test|data_out[1]~_Duplicate_1 .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y17_N54
cyclonev_lcell_comb \u0|led_pio_test|readdata[1] (
// Equation(s):
// \u0|led_pio_test|readdata [1] = ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( \u0|led_pio_test|data_out[1]~_Duplicate_1_q  ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|led_pio_test|data_out[1]~_Duplicate_1_q ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|led_pio_test|readdata [1]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|led_pio_test|readdata[1] .extended_lut = "off";
defparam \u0|led_pio_test|readdata[1] .lut_mask = 64'h0F0F000000000000;
defparam \u0|led_pio_test|readdata[1] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y17_N56
dffeas \u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|led_pio_test|readdata [1]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X23_Y17_N38
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y17_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~1 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~1_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][1]~q  ) ) # ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre [1] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre [1]),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][1]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~1 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y17_N32
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y17_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~30 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~30_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre [1] & ( ((\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg [0] & 
// !\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][1]~q ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre [1] & ( 
// (\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][1]~q  & ((!\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg [0]) # (\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [0]))) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg [0]),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [0]),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][1]~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~30_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~30 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~30 .lut_mask = 64'h0B0B0B0B4F4F4F4F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~30 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y2_N57
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|timecode~2 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|timecode~2_combout  = ( \A_SPW_TOP|SPW|RX|timecode~0_combout  & ( \A_SPW_TOP|SPW|RX|dta_timec_p [1] ) ) # ( !\A_SPW_TOP|SPW|RX|timecode~0_combout  & ( \A_SPW_TOP|SPW|RX|dta_timec_p [1] & ( \A_SPW_TOP|SPW|RX|timecode [1] ) ) ) # ( 
// !\A_SPW_TOP|SPW|RX|timecode~0_combout  & ( !\A_SPW_TOP|SPW|RX|dta_timec_p [1] & ( \A_SPW_TOP|SPW|RX|timecode [1] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|RX|timecode [1]),
        .datad(gnd),
        .datae(!\A_SPW_TOP|SPW|RX|timecode~0_combout ),
        .dataf(!\A_SPW_TOP|SPW|RX|dta_timec_p [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|timecode~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|timecode~2 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|timecode~2 .lut_mask = 64'h0F0F00000F0FFFFF;
defparam \A_SPW_TOP|SPW|RX|timecode~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y2_N11
dffeas \A_SPW_TOP|SPW|RX|timecode[1] (
        .clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|RX|timecode~2_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(!\A_SPW_TOP|SPW|RX|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|timecode [1]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|timecode[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|timecode[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y14_N51
cyclonev_lcell_comb \u0|timecode_rx|read_mux_out[1] (
// Equation(s):
// \u0|timecode_rx|read_mux_out [1] = ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( \A_SPW_TOP|SPW|RX|timecode [1] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|RX|timecode [1]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|timecode_rx|read_mux_out [1]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|timecode_rx|read_mux_out[1] .extended_lut = "off";
defparam \u0|timecode_rx|read_mux_out[1] .lut_mask = 64'h0F0F000000000000;
defparam \u0|timecode_rx|read_mux_out[1] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y14_N52
dffeas \u0|timecode_rx|readdata[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|timecode_rx|read_mux_out [1]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|timecode_rx|readdata [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|timecode_rx|readdata[1] .is_wysiwyg = "true";
defparam \u0|timecode_rx|readdata[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X25_Y16_N29
dffeas \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|timecode_rx|readdata [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X25_Y16_N26
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y16_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~1_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][1]~q  & ( (\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [1]) # 
// (\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][1]~q  & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [1]) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~1 .lut_mask = 64'h00AA00AA55FF55FF;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y16_N2
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y16_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~31 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~31_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0] & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0] & 
// (\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [1])) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0] & ((\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][1]~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][1]~q  ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0]),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][1]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~31_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~31 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~31 .lut_mask = 64'h00FF00FF505F505F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~31 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X47_Y2_N6
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|rx_data_flag~1 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|rx_data_flag~1_combout  = ( \A_SPW_TOP|SPW|RX|dta_timec_p [1] & ( (!\A_SPW_TOP|SPW|RX|ready_control_p_r~q  & ((!\A_SPW_TOP|SPW|RX|data~0_combout ) # ((\A_SPW_TOP|SPW|RX|rx_data_flag [1])))) # (\A_SPW_TOP|SPW|RX|ready_control_p_r~q  & 
// (((\A_SPW_TOP|SPW|RX|rx_data_flag~0_combout  & \A_SPW_TOP|SPW|RX|rx_data_flag [1])))) ) ) # ( !\A_SPW_TOP|SPW|RX|dta_timec_p [1] & ( (\A_SPW_TOP|SPW|RX|rx_data_flag [1] & (((\A_SPW_TOP|SPW|RX|data~0_combout  & !\A_SPW_TOP|SPW|RX|ready_control_p_r~q )) # 
// (\A_SPW_TOP|SPW|RX|rx_data_flag~0_combout ))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|data~0_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),
        .datac(!\A_SPW_TOP|SPW|RX|rx_data_flag~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|dta_timec_p [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|rx_data_flag~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_data_flag~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|rx_data_flag~1 .lut_mask = 64'h004F004F88CF88CF;
defparam \A_SPW_TOP|SPW|RX|rx_data_flag~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y2_N38
dffeas \A_SPW_TOP|SPW|RX|rx_data_flag[1] (
        .clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|RX|rx_data_flag~1_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(!\A_SPW_TOP|SPW|RX|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_data_flag[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|rx_data_flag[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y4_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector494~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector494~0_combout  = ( \A_SPW_TOP|rx_data|Mux7~20_combout  & ( (!\A_SPW_TOP|rx_data|Selector487~0_combout  & (((\A_SPW_TOP|rx_data|mem[52][1]~q )))) # (\A_SPW_TOP|rx_data|Selector487~0_combout  & 
// (((\A_SPW_TOP|rx_data|state_data_write.00~q )) # (\A_SPW_TOP|SPW|RX|rx_data_flag [1]))) ) ) # ( !\A_SPW_TOP|rx_data|Mux7~20_combout  & ( (!\A_SPW_TOP|rx_data|Selector487~0_combout  & (((\A_SPW_TOP|rx_data|mem[52][1]~q )))) # 
// (\A_SPW_TOP|rx_data|Selector487~0_combout  & (\A_SPW_TOP|SPW|RX|rx_data_flag [1] & (!\A_SPW_TOP|rx_data|state_data_write.00~q ))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[52][1]~q ),
        .datad(!\A_SPW_TOP|rx_data|Selector487~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector494~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector494~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector494~0 .lut_mask = 64'h0F440F440F770F77;
defparam \A_SPW_TOP|rx_data|Selector494~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y4_N5
dffeas \A_SPW_TOP|rx_data|mem[52][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector494~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[52][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[52][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[52][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y4_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector215~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector215~0_combout  = ( \A_SPW_TOP|rx_data|mem[21][1]~q  & ( (!\A_SPW_TOP|rx_data|Selector208~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [1])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux7~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[21][1]~q  & ( (\A_SPW_TOP|rx_data|Selector208~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [1])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux7~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datab(!\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector208~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[21][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector215~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector215~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector215~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|rx_data|Selector215~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X45_Y4_N17
dffeas \A_SPW_TOP|rx_data|mem[21][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector215~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[21][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[21][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[21][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y4_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector503~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector503~0_combout  = ( \A_SPW_TOP|rx_data|mem[53][1]~q  & ( (!\A_SPW_TOP|rx_data|Selector496~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [1]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux7~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[53][1]~q  & ( (\A_SPW_TOP|rx_data|Selector496~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [1]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux7~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datad(!\A_SPW_TOP|rx_data|Selector496~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[53][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector503~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector503~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector503~0 .lut_mask = 64'h001D001DFF1DFF1D;
defparam \A_SPW_TOP|rx_data|Selector503~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y4_N32
dffeas \A_SPW_TOP|rx_data|mem[53][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector503~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[53][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[53][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[53][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y4_N51
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector206~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector206~0_combout  = ( \A_SPW_TOP|SPW|RX|rx_data_flag [1] & ( (!\A_SPW_TOP|rx_data|Selector199~0_combout  & (((\A_SPW_TOP|rx_data|mem[20][1]~q )))) # (\A_SPW_TOP|rx_data|Selector199~0_combout  & 
// (((!\A_SPW_TOP|rx_data|state_data_write.00~q )) # (\A_SPW_TOP|rx_data|Mux7~20_combout ))) ) ) # ( !\A_SPW_TOP|SPW|RX|rx_data_flag [1] & ( (!\A_SPW_TOP|rx_data|Selector199~0_combout  & (((\A_SPW_TOP|rx_data|mem[20][1]~q )))) # 
// (\A_SPW_TOP|rx_data|Selector199~0_combout  & (\A_SPW_TOP|rx_data|Mux7~20_combout  & (\A_SPW_TOP|rx_data|state_data_write.00~q ))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[20][1]~q ),
        .datad(!\A_SPW_TOP|rx_data|Selector199~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector206~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector206~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector206~0 .lut_mask = 64'h0F110F110FDD0FDD;
defparam \A_SPW_TOP|rx_data|Selector206~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y4_N11
dffeas \A_SPW_TOP|rx_data|mem[20][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector206~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[20][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[20][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[20][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y4_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux7~15 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux7~15_combout  = ( \A_SPW_TOP|rx_data|mem[53][1]~q  & ( \A_SPW_TOP|rx_data|mem[20][1]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & (((!\A_SPW_TOP|rx_data|wr_ptr [5])) # (\A_SPW_TOP|rx_data|mem[52][1]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [0] 
// & (((\A_SPW_TOP|rx_data|mem[21][1]~q ) # (\A_SPW_TOP|rx_data|wr_ptr [5])))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[53][1]~q  & ( \A_SPW_TOP|rx_data|mem[20][1]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & (((!\A_SPW_TOP|rx_data|wr_ptr [5])) # 
// (\A_SPW_TOP|rx_data|mem[52][1]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & (((!\A_SPW_TOP|rx_data|wr_ptr [5] & \A_SPW_TOP|rx_data|mem[21][1]~q )))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[53][1]~q  & ( !\A_SPW_TOP|rx_data|mem[20][1]~q  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|mem[52][1]~q  & (\A_SPW_TOP|rx_data|wr_ptr [5]))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & (((\A_SPW_TOP|rx_data|mem[21][1]~q ) # (\A_SPW_TOP|rx_data|wr_ptr [5])))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[53][1]~q 
//  & ( !\A_SPW_TOP|rx_data|mem[20][1]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|mem[52][1]~q  & (\A_SPW_TOP|rx_data|wr_ptr [5]))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & (((!\A_SPW_TOP|rx_data|wr_ptr [5] & \A_SPW_TOP|rx_data|mem[21][1]~q )))) 
// ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datab(!\A_SPW_TOP|rx_data|mem[52][1]~q ),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datad(!\A_SPW_TOP|rx_data|mem[21][1]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[53][1]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[20][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux7~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux7~15 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux7~15 .lut_mask = 64'h02520757A2F2A7F7;
defparam \A_SPW_TOP|rx_data|Mux7~15 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y4_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector566~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector566~0_combout  = ( \A_SPW_TOP|rx_data|Selector559~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [1]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux7~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector559~0_combout  & ( \A_SPW_TOP|rx_data|mem[60][1]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[60][1]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector559~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector566~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector566~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector566~0 .lut_mask = 64'h00FF00FF35353535;
defparam \A_SPW_TOP|rx_data|Selector566~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y4_N59
dffeas \A_SPW_TOP|rx_data|mem[60][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector566~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[60][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[60][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[60][1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y4_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector278~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector278~0_combout  = ( \A_SPW_TOP|rx_data|Mux7~20_combout  & ( \A_SPW_TOP|rx_data|mem[28][1]~q  & ( ((!\A_SPW_TOP|rx_data|Selector271~0_combout ) # (\A_SPW_TOP|SPW|RX|rx_data_flag [1])) # (\A_SPW_TOP|rx_data|state_data_write.00~q ) 
// ) ) ) # ( !\A_SPW_TOP|rx_data|Mux7~20_combout  & ( \A_SPW_TOP|rx_data|mem[28][1]~q  & ( (!\A_SPW_TOP|rx_data|Selector271~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & \A_SPW_TOP|SPW|RX|rx_data_flag [1])) ) ) ) # ( 
// \A_SPW_TOP|rx_data|Mux7~20_combout  & ( !\A_SPW_TOP|rx_data|mem[28][1]~q  & ( (\A_SPW_TOP|rx_data|Selector271~0_combout  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [1]) # (\A_SPW_TOP|rx_data|state_data_write.00~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux7~20_combout  
// & ( !\A_SPW_TOP|rx_data|mem[28][1]~q  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Selector271~0_combout  & \A_SPW_TOP|SPW|RX|rx_data_flag [1])) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Selector271~0_combout ),
        .datac(gnd),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datae(!\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .dataf(!\A_SPW_TOP|rx_data|mem[28][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector278~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector278~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector278~0 .lut_mask = 64'h00221133CCEEDDFF;
defparam \A_SPW_TOP|rx_data|Selector278~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y4_N41
dffeas \A_SPW_TOP|rx_data|mem[28][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector278~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[28][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[28][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[28][1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y4_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector287~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector287~0_combout  = ( \A_SPW_TOP|rx_data|Mux7~20_combout  & ( \A_SPW_TOP|rx_data|mem[29][1]~q  & ( ((!\A_SPW_TOP|rx_data|Selector280~0_combout ) # (\A_SPW_TOP|rx_data|state_data_write.00~q )) # (\A_SPW_TOP|SPW|RX|rx_data_flag [1]) 
// ) ) ) # ( !\A_SPW_TOP|rx_data|Mux7~20_combout  & ( \A_SPW_TOP|rx_data|mem[29][1]~q  & ( (!\A_SPW_TOP|rx_data|Selector280~0_combout ) # ((\A_SPW_TOP|SPW|RX|rx_data_flag [1] & !\A_SPW_TOP|rx_data|state_data_write.00~q )) ) ) ) # ( 
// \A_SPW_TOP|rx_data|Mux7~20_combout  & ( !\A_SPW_TOP|rx_data|mem[29][1]~q  & ( (\A_SPW_TOP|rx_data|Selector280~0_combout  & ((\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|SPW|RX|rx_data_flag [1]))) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux7~20_combout  
// & ( !\A_SPW_TOP|rx_data|mem[29][1]~q  & ( (\A_SPW_TOP|SPW|RX|rx_data_flag [1] & (!\A_SPW_TOP|rx_data|state_data_write.00~q  & \A_SPW_TOP|rx_data|Selector280~0_combout )) ) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Selector280~0_combout ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .dataf(!\A_SPW_TOP|rx_data|mem[29][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector287~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector287~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector287~0 .lut_mask = 64'h04040707F4F4F7F7;
defparam \A_SPW_TOP|rx_data|Selector287~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y4_N8
dffeas \A_SPW_TOP|rx_data|mem[29][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector287~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[29][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[29][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[29][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y4_N15
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector575~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector575~0_combout  = ( \A_SPW_TOP|rx_data|Mux7~20_combout  & ( (!\A_SPW_TOP|rx_data|Selector568~0_combout  & (((\A_SPW_TOP|rx_data|mem[61][1]~q )))) # (\A_SPW_TOP|rx_data|Selector568~0_combout  & 
// (((\A_SPW_TOP|rx_data|state_data_write.00~q )) # (\A_SPW_TOP|SPW|RX|rx_data_flag [1]))) ) ) # ( !\A_SPW_TOP|rx_data|Mux7~20_combout  & ( (!\A_SPW_TOP|rx_data|Selector568~0_combout  & (((\A_SPW_TOP|rx_data|mem[61][1]~q )))) # 
// (\A_SPW_TOP|rx_data|Selector568~0_combout  & (\A_SPW_TOP|SPW|RX|rx_data_flag [1] & (!\A_SPW_TOP|rx_data|state_data_write.00~q ))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[61][1]~q ),
        .datad(!\A_SPW_TOP|rx_data|Selector568~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector575~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector575~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector575~0 .lut_mask = 64'h0F440F440F770F77;
defparam \A_SPW_TOP|rx_data|Selector575~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y4_N41
dffeas \A_SPW_TOP|rx_data|mem[61][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector575~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[61][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[61][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[61][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y4_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux7~16 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux7~16_combout  = ( \A_SPW_TOP|rx_data|mem[29][1]~q  & ( \A_SPW_TOP|rx_data|mem[61][1]~q  & ( ((!\A_SPW_TOP|rx_data|wr_ptr [5] & ((\A_SPW_TOP|rx_data|mem[28][1]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|mem[60][1]~q 
// ))) # (\A_SPW_TOP|rx_data|wr_ptr [0]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[29][1]~q  & ( \A_SPW_TOP|rx_data|mem[61][1]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & ((!\A_SPW_TOP|rx_data|wr_ptr [5] & ((\A_SPW_TOP|rx_data|mem[28][1]~q ))) # 
// (\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|mem[60][1]~q )))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & (((\A_SPW_TOP|rx_data|wr_ptr [5])))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[29][1]~q  & ( !\A_SPW_TOP|rx_data|mem[61][1]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr 
// [0] & ((!\A_SPW_TOP|rx_data|wr_ptr [5] & ((\A_SPW_TOP|rx_data|mem[28][1]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|mem[60][1]~q )))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & (((!\A_SPW_TOP|rx_data|wr_ptr [5])))) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|mem[29][1]~q  & ( !\A_SPW_TOP|rx_data|mem[61][1]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & ((!\A_SPW_TOP|rx_data|wr_ptr [5] & ((\A_SPW_TOP|rx_data|mem[28][1]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|mem[60][1]~q )))) 
// ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datab(!\A_SPW_TOP|rx_data|mem[60][1]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[28][1]~q ),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datae(!\A_SPW_TOP|rx_data|mem[29][1]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[61][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux7~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux7~16 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux7~16 .lut_mask = 64'h0A225F220A775F77;
defparam \A_SPW_TOP|rx_data|Mux7~16 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y4_N51
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector512~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector512~0_combout  = ( \A_SPW_TOP|rx_data|mem[54][1]~q  & ( (!\A_SPW_TOP|rx_data|Selector505~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [1])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux7~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[54][1]~q  & ( (\A_SPW_TOP|rx_data|Selector505~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [1])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux7~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Selector505~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[54][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector512~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector512~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector512~0 .lut_mask = 64'h04070407F4F7F4F7;
defparam \A_SPW_TOP|rx_data|Selector512~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y4_N11
dffeas \A_SPW_TOP|rx_data|mem[54][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector512~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[54][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[54][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[54][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y4_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector224~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector224~0_combout  = ( \A_SPW_TOP|rx_data|mem[22][1]~q  & ( (!\A_SPW_TOP|rx_data|Selector217~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [1]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux7~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[22][1]~q  & ( (\A_SPW_TOP|rx_data|Selector217~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [1]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux7~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .datac(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datad(!\A_SPW_TOP|rx_data|Selector217~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[22][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector224~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector224~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector224~0 .lut_mask = 64'h001B001BFF1BFF1B;
defparam \A_SPW_TOP|rx_data|Selector224~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X45_Y4_N14
dffeas \A_SPW_TOP|rx_data|mem[22][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector224~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[22][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[22][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[22][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y4_N33
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector521~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector521~0_combout  = ( \A_SPW_TOP|rx_data|mem[55][1]~q  & ( (!\A_SPW_TOP|rx_data|Selector514~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [1])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux7~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[55][1]~q  & ( (\A_SPW_TOP|rx_data|Selector514~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [1])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux7~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datab(!\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector514~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[55][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector521~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector521~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector521~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|rx_data|Selector521~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X45_Y4_N44
dffeas \A_SPW_TOP|rx_data|mem[55][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector521~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[55][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[55][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[55][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y4_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector233~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector233~0_combout  = ( \A_SPW_TOP|rx_data|mem[23][1]~q  & ( (!\A_SPW_TOP|rx_data|Selector226~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [1])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux7~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[23][1]~q  & ( (\A_SPW_TOP|rx_data|Selector226~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [1])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux7~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datab(!\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|Selector226~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[23][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector233~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector233~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector233~0 .lut_mask = 64'h00530053FF53FF53;
defparam \A_SPW_TOP|rx_data|Selector233~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X45_Y4_N26
dffeas \A_SPW_TOP|rx_data|mem[23][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector233~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[23][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[23][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[23][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y4_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux7~17 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux7~17_combout  = ( \A_SPW_TOP|rx_data|mem[55][1]~q  & ( \A_SPW_TOP|rx_data|mem[23][1]~q  & ( ((!\A_SPW_TOP|rx_data|wr_ptr [5] & ((\A_SPW_TOP|rx_data|mem[22][1]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|mem[54][1]~q 
// ))) # (\A_SPW_TOP|rx_data|wr_ptr [0]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[55][1]~q  & ( \A_SPW_TOP|rx_data|mem[23][1]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & ((!\A_SPW_TOP|rx_data|wr_ptr [5] & ((\A_SPW_TOP|rx_data|mem[22][1]~q ))) # 
// (\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|mem[54][1]~q )))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & (((!\A_SPW_TOP|rx_data|wr_ptr [5])))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[55][1]~q  & ( !\A_SPW_TOP|rx_data|mem[23][1]~q  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [0] & ((!\A_SPW_TOP|rx_data|wr_ptr [5] & ((\A_SPW_TOP|rx_data|mem[22][1]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|mem[54][1]~q )))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & (((\A_SPW_TOP|rx_data|wr_ptr [5])))) ) ) 
// ) # ( !\A_SPW_TOP|rx_data|mem[55][1]~q  & ( !\A_SPW_TOP|rx_data|mem[23][1]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & ((!\A_SPW_TOP|rx_data|wr_ptr [5] & ((\A_SPW_TOP|rx_data|mem[22][1]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [5] & 
// (\A_SPW_TOP|rx_data|mem[54][1]~q )))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[54][1]~q ),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datad(!\A_SPW_TOP|rx_data|mem[22][1]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[55][1]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[23][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux7~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux7~17 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux7~17 .lut_mask = 64'h04C407C734F437F7;
defparam \A_SPW_TOP|rx_data|Mux7~17 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y4_N45
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector584~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector584~0_combout  = ( \A_SPW_TOP|rx_data|Selector577~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [1]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux7~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector577~0_combout  & ( \A_SPW_TOP|rx_data|mem[62][1]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[62][1]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector577~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector584~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector584~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector584~0 .lut_mask = 64'h00FF00FF35353535;
defparam \A_SPW_TOP|rx_data|Selector584~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y4_N23
dffeas \A_SPW_TOP|rx_data|mem[62][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector584~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[62][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[62][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[62][1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y4_N57
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector593~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector593~0_combout  = ( \A_SPW_TOP|SPW|RX|rx_data_flag [1] & ( (!\A_SPW_TOP|rx_data|Selector586~0_combout  & (((\A_SPW_TOP|rx_data|mem[63][1]~q )))) # (\A_SPW_TOP|rx_data|Selector586~0_combout  & 
// ((!\A_SPW_TOP|rx_data|state_data_write.00~q ) # ((\A_SPW_TOP|rx_data|Mux7~20_combout )))) ) ) # ( !\A_SPW_TOP|SPW|RX|rx_data_flag [1] & ( (!\A_SPW_TOP|rx_data|Selector586~0_combout  & (((\A_SPW_TOP|rx_data|mem[63][1]~q )))) # 
// (\A_SPW_TOP|rx_data|Selector586~0_combout  & (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux7~20_combout ))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector586~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[63][1]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector593~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector593~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector593~0 .lut_mask = 64'h01F101F10BFB0BFB;
defparam \A_SPW_TOP|rx_data|Selector593~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y4_N38
dffeas \A_SPW_TOP|rx_data|mem[63][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector593~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[63][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[63][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[63][1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y4_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector305~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector305~0_combout  = ( \A_SPW_TOP|rx_data|Selector298~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [1]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux7~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector298~0_combout  & ( \A_SPW_TOP|rx_data|mem[31][1]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|mem[31][1]~q ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector298~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector305~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector305~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector305~0 .lut_mask = 64'h0F0F0F0F11BB11BB;
defparam \A_SPW_TOP|rx_data|Selector305~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y4_N29
dffeas \A_SPW_TOP|rx_data|mem[31][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector305~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[31][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[31][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[31][1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y4_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector296~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector296~0_combout  = ( \A_SPW_TOP|rx_data|mem[30][1]~q  & ( (!\A_SPW_TOP|rx_data|Selector289~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [1]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux7~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[30][1]~q  & ( (\A_SPW_TOP|rx_data|Selector289~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [1]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux7~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .datac(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datad(!\A_SPW_TOP|rx_data|Selector289~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[30][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector296~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector296~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector296~0 .lut_mask = 64'h001B001BFF1BFF1B;
defparam \A_SPW_TOP|rx_data|Selector296~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y4_N17
dffeas \A_SPW_TOP|rx_data|mem[30][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector296~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[30][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[30][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[30][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y4_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux7~18 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux7~18_combout  = ( \A_SPW_TOP|rx_data|mem[30][1]~q  & ( \A_SPW_TOP|rx_data|wr_ptr [0] & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & ((\A_SPW_TOP|rx_data|mem[31][1]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|mem[63][1]~q )) ) 
// ) ) # ( !\A_SPW_TOP|rx_data|mem[30][1]~q  & ( \A_SPW_TOP|rx_data|wr_ptr [0] & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & ((\A_SPW_TOP|rx_data|mem[31][1]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|mem[63][1]~q )) ) ) ) # ( 
// \A_SPW_TOP|rx_data|mem[30][1]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [0] & ( (!\A_SPW_TOP|rx_data|wr_ptr [5]) # (\A_SPW_TOP|rx_data|mem[62][1]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[30][1]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [0] & ( 
// (\A_SPW_TOP|rx_data|mem[62][1]~q  & \A_SPW_TOP|rx_data|wr_ptr [5]) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[62][1]~q ),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datac(!\A_SPW_TOP|rx_data|mem[63][1]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[31][1]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[30][1]~q ),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux7~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux7~18 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux7~18 .lut_mask = 64'h1111DDDD03CF03CF;
defparam \A_SPW_TOP|rx_data|Mux7~18 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y4_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux7~19 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux7~19_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [3] & ( \A_SPW_TOP|rx_data|Mux7~18_combout  & ( (\A_SPW_TOP|rx_data|Mux7~16_combout ) # (\A_SPW_TOP|rx_data|wr_ptr [1]) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [3] & ( 
// \A_SPW_TOP|rx_data|Mux7~18_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|Mux7~15_combout )) # (\A_SPW_TOP|rx_data|wr_ptr [1] & ((\A_SPW_TOP|rx_data|Mux7~17_combout ))) ) ) ) # ( \A_SPW_TOP|rx_data|wr_ptr [3] & ( 
// !\A_SPW_TOP|rx_data|Mux7~18_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & \A_SPW_TOP|rx_data|Mux7~16_combout ) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [3] & ( !\A_SPW_TOP|rx_data|Mux7~18_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & 
// (\A_SPW_TOP|rx_data|Mux7~15_combout )) # (\A_SPW_TOP|rx_data|wr_ptr [1] & ((\A_SPW_TOP|rx_data|Mux7~17_combout ))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datab(!\A_SPW_TOP|rx_data|Mux7~15_combout ),
        .datac(!\A_SPW_TOP|rx_data|Mux7~16_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux7~17_combout ),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .dataf(!\A_SPW_TOP|rx_data|Mux7~18_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux7~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux7~19 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux7~19 .lut_mask = 64'h22770A0A22775F5F;
defparam \A_SPW_TOP|rx_data|Mux7~19 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y4_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector152~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector152~0_combout  = ( \A_SPW_TOP|rx_data|Selector145~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [1]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux7~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector145~0_combout  & ( \A_SPW_TOP|rx_data|mem[14][1]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datac(!\A_SPW_TOP|rx_data|mem[14][1]~q ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector145~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector152~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector152~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector152~0 .lut_mask = 64'h0F0F0F0F33553355;
defparam \A_SPW_TOP|rx_data|Selector152~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y4_N20
dffeas \A_SPW_TOP|rx_data|mem[14][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector152~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[14][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[14][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[14][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y4_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector134~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector134~0_combout  = ( \A_SPW_TOP|rx_data|mem[12][1]~q  & ( (!\A_SPW_TOP|rx_data|Selector127~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [1])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux7~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[12][1]~q  & ( (\A_SPW_TOP|rx_data|Selector127~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [1])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux7~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datac(!\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .datad(!\A_SPW_TOP|rx_data|Selector127~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[12][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector134~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector134~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector134~0 .lut_mask = 64'h00270027FF27FF27;
defparam \A_SPW_TOP|rx_data|Selector134~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y4_N17
dffeas \A_SPW_TOP|rx_data|mem[12][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector134~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[12][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[12][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[12][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y4_N33
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector161~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector161~0_combout  = ( \A_SPW_TOP|rx_data|mem[15][1]~q  & ( (!\A_SPW_TOP|rx_data|Selector154~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [1]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux7~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[15][1]~q  & ( (\A_SPW_TOP|rx_data|Selector154~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [1]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux7~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datac(!\A_SPW_TOP|rx_data|Selector154~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[15][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector161~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector161~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector161~0 .lut_mask = 64'h03050305F3F5F3F5;
defparam \A_SPW_TOP|rx_data|Selector161~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y4_N50
dffeas \A_SPW_TOP|rx_data|mem[15][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector161~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[15][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[15][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[15][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y4_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector143~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector143~0_combout  = ( \A_SPW_TOP|rx_data|mem[13][1]~q  & ( (!\A_SPW_TOP|rx_data|Selector136~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [1]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux7~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[13][1]~q  & ( (\A_SPW_TOP|rx_data|Selector136~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [1]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux7~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|Selector136~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[13][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector143~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector143~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector143~0 .lut_mask = 64'h00350035FF35FF35;
defparam \A_SPW_TOP|rx_data|Selector143~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y4_N14
dffeas \A_SPW_TOP|rx_data|mem[13][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector143~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[13][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[13][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[13][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y4_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux7~11 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux7~11_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [0] & ( \A_SPW_TOP|rx_data|mem[13][1]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [1]) # (\A_SPW_TOP|rx_data|mem[15][1]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [0] & ( 
// \A_SPW_TOP|rx_data|mem[13][1]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & ((\A_SPW_TOP|rx_data|mem[12][1]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|mem[14][1]~q )) ) ) ) # ( \A_SPW_TOP|rx_data|wr_ptr [0] & ( 
// !\A_SPW_TOP|rx_data|mem[13][1]~q  & ( (\A_SPW_TOP|rx_data|mem[15][1]~q  & \A_SPW_TOP|rx_data|wr_ptr [1]) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [0] & ( !\A_SPW_TOP|rx_data|mem[13][1]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & ((\A_SPW_TOP|rx_data|mem[12][1]~q 
// ))) # (\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|mem[14][1]~q )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[14][1]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[12][1]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[15][1]~q ),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .dataf(!\A_SPW_TOP|rx_data|mem[13][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux7~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux7~11 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux7~11 .lut_mask = 64'h3355000F3355FF0F;
defparam \A_SPW_TOP|rx_data|Mux7~11 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y4_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector431~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector431~0_combout  = ( \A_SPW_TOP|rx_data|Selector424~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [1])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux7~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector424~0_combout  & ( \A_SPW_TOP|rx_data|mem[45][1]~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[45][1]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector424~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector431~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector431~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector431~0 .lut_mask = 64'h00FF00FF47474747;
defparam \A_SPW_TOP|rx_data|Selector431~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y4_N47
dffeas \A_SPW_TOP|rx_data|mem[45][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector431~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[45][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[45][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[45][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y4_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector422~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector422~0_combout  = ( \A_SPW_TOP|rx_data|Selector415~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [1]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux7~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector415~0_combout  & ( \A_SPW_TOP|rx_data|mem[44][1]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[44][1]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector415~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector422~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector422~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector422~0 .lut_mask = 64'h00FF00FF35353535;
defparam \A_SPW_TOP|rx_data|Selector422~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y4_N38
dffeas \A_SPW_TOP|rx_data|mem[44][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector422~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[44][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[44][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[44][1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y4_N9
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector449~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector449~0_combout  = ( \A_SPW_TOP|rx_data|Selector442~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [1])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux7~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector442~0_combout  & ( \A_SPW_TOP|rx_data|mem[47][1]~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[47][1]~q ),
        .datad(!\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector442~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector449~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector449~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector449~0 .lut_mask = 64'h0F0F0F0F44774477;
defparam \A_SPW_TOP|rx_data|Selector449~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y4_N44
dffeas \A_SPW_TOP|rx_data|mem[47][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector449~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[47][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[47][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[47][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y4_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector440~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector440~0_combout  = ( \A_SPW_TOP|rx_data|mem[46][1]~q  & ( (!\A_SPW_TOP|rx_data|Selector433~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [1])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux7~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[46][1]~q  & ( (\A_SPW_TOP|rx_data|Selector433~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [1])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux7~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .datad(!\A_SPW_TOP|rx_data|Selector433~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[46][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector440~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector440~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector440~0 .lut_mask = 64'h00470047FF47FF47;
defparam \A_SPW_TOP|rx_data|Selector440~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y4_N20
dffeas \A_SPW_TOP|rx_data|mem[46][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector440~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[46][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[46][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[46][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y4_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux7~13 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux7~13_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [1] & ( \A_SPW_TOP|rx_data|wr_ptr [0] & ( \A_SPW_TOP|rx_data|mem[47][1]~q  ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [1] & ( \A_SPW_TOP|rx_data|wr_ptr [0] & ( \A_SPW_TOP|rx_data|mem[45][1]~q  ) 
// ) ) # ( \A_SPW_TOP|rx_data|wr_ptr [1] & ( !\A_SPW_TOP|rx_data|wr_ptr [0] & ( \A_SPW_TOP|rx_data|mem[46][1]~q  ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [1] & ( !\A_SPW_TOP|rx_data|wr_ptr [0] & ( \A_SPW_TOP|rx_data|mem[44][1]~q  ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[45][1]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[44][1]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[47][1]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[46][1]~q ),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux7~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux7~13 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux7~13 .lut_mask = 64'h333300FF55550F0F;
defparam \A_SPW_TOP|rx_data|Mux7~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X36_Y4_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector359~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector359~0_combout  = ( \A_SPW_TOP|rx_data|mem[37][1]~q  & ( (!\A_SPW_TOP|rx_data|Selector352~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [1]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux7~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[37][1]~q  & ( (\A_SPW_TOP|rx_data|Selector352~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [1]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux7~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Selector352~0_combout ),
        .datab(!\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .datac(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[37][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector359~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector359~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector359~0 .lut_mask = 64'h05110511AFBBAFBB;
defparam \A_SPW_TOP|rx_data|Selector359~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X36_Y4_N53
dffeas \A_SPW_TOP|rx_data|mem[37][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector359~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[37][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[37][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[37][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X36_Y4_N33
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector368~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector368~0_combout  = ( \A_SPW_TOP|rx_data|Selector361~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [1]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux7~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector361~0_combout  & ( \A_SPW_TOP|rx_data|mem[38][1]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|mem[38][1]~q ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector361~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector368~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector368~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector368~0 .lut_mask = 64'h0F0F0F0F11BB11BB;
defparam \A_SPW_TOP|rx_data|Selector368~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y4_N59
dffeas \A_SPW_TOP|rx_data|mem[38][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector368~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[38][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[38][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[38][1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y4_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector350~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector350~0_combout  = ( \A_SPW_TOP|rx_data|Selector343~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [1]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux7~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector343~0_combout  & ( \A_SPW_TOP|rx_data|mem[36][1]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datad(!\A_SPW_TOP|rx_data|mem[36][1]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector343~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector350~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector350~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector350~0 .lut_mask = 64'h00FF00FF1D1D1D1D;
defparam \A_SPW_TOP|rx_data|Selector350~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y4_N29
dffeas \A_SPW_TOP|rx_data|mem[36][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector350~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[36][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[36][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[36][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X36_Y4_N27
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector377~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector377~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector370~0_combout  & ((\A_SPW_TOP|rx_data|mem[39][1]~q ))) # (\A_SPW_TOP|rx_data|Selector370~0_combout  & 
// (\A_SPW_TOP|rx_data|Mux7~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector370~0_combout  & ((\A_SPW_TOP|rx_data|mem[39][1]~q ))) # (\A_SPW_TOP|rx_data|Selector370~0_combout  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [1])) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datab(!\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|mem[39][1]~q ),
        .datad(!\A_SPW_TOP|rx_data|Selector370~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector377~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector377~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector377~0 .lut_mask = 64'h0F550F550F330F33;
defparam \A_SPW_TOP|rx_data|Selector377~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X36_Y4_N5
dffeas \A_SPW_TOP|rx_data|mem[39][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector377~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[39][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[39][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[39][1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y4_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux7~12 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux7~12_combout  = ( \A_SPW_TOP|rx_data|mem[36][1]~q  & ( \A_SPW_TOP|rx_data|mem[39][1]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & (((!\A_SPW_TOP|rx_data|wr_ptr [1]) # (\A_SPW_TOP|rx_data|mem[38][1]~q )))) # (\A_SPW_TOP|rx_data|wr_ptr [0] 
// & (((\A_SPW_TOP|rx_data|wr_ptr [1])) # (\A_SPW_TOP|rx_data|mem[37][1]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[36][1]~q  & ( \A_SPW_TOP|rx_data|mem[39][1]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & (((\A_SPW_TOP|rx_data|mem[38][1]~q  & 
// \A_SPW_TOP|rx_data|wr_ptr [1])))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & (((\A_SPW_TOP|rx_data|wr_ptr [1])) # (\A_SPW_TOP|rx_data|mem[37][1]~q ))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[36][1]~q  & ( !\A_SPW_TOP|rx_data|mem[39][1]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr 
// [0] & (((!\A_SPW_TOP|rx_data|wr_ptr [1]) # (\A_SPW_TOP|rx_data|mem[38][1]~q )))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|mem[37][1]~q  & ((!\A_SPW_TOP|rx_data|wr_ptr [1])))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[36][1]~q  & ( 
// !\A_SPW_TOP|rx_data|mem[39][1]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & (((\A_SPW_TOP|rx_data|mem[38][1]~q  & \A_SPW_TOP|rx_data|wr_ptr [1])))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|mem[37][1]~q  & ((!\A_SPW_TOP|rx_data|wr_ptr [1])))) ) ) 
// )

        .dataa(!\A_SPW_TOP|rx_data|mem[37][1]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[38][1]~q ),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datae(!\A_SPW_TOP|rx_data|mem[36][1]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[39][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux7~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux7~12 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux7~12 .lut_mask = 64'h0530F530053FF53F;
defparam \A_SPW_TOP|rx_data|Mux7~12 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X36_Y4_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector80~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector80~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector73~0_combout  & ((\A_SPW_TOP|rx_data|mem[6][1]~q ))) # (\A_SPW_TOP|rx_data|Selector73~0_combout  & (\A_SPW_TOP|rx_data|Mux7~20_combout 
// )) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector73~0_combout  & ((\A_SPW_TOP|rx_data|mem[6][1]~q ))) # (\A_SPW_TOP|rx_data|Selector73~0_combout  & (\A_SPW_TOP|SPW|RX|rx_data_flag [1])) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datab(!\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector73~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[6][1]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector80~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector80~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector80~0 .lut_mask = 64'h05F505F503F303F3;
defparam \A_SPW_TOP|rx_data|Selector80~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X36_Y4_N2
dffeas \A_SPW_TOP|rx_data|mem[6][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector80~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[6][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[6][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[6][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X36_Y4_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector62~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector62~0_combout  = ( \A_SPW_TOP|rx_data|mem[4][1]~q  & ( (!\A_SPW_TOP|rx_data|Selector55~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [1])) # (\A_SPW_TOP|rx_data|state_data_write.00~q 
//  & ((\A_SPW_TOP|rx_data|Mux7~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[4][1]~q  & ( (\A_SPW_TOP|rx_data|Selector55~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [1])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux7~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datab(!\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector55~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[4][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector62~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector62~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector62~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|rx_data|Selector62~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X36_Y4_N17
dffeas \A_SPW_TOP|rx_data|mem[4][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector62~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[4][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[4][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[4][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X36_Y4_N21
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector89~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector89~0_combout  = ( \A_SPW_TOP|rx_data|mem[7][1]~q  & ( (!\A_SPW_TOP|rx_data|Selector82~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [1])) # (\A_SPW_TOP|rx_data|state_data_write.00~q 
//  & ((\A_SPW_TOP|rx_data|Mux7~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[7][1]~q  & ( (\A_SPW_TOP|rx_data|Selector82~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [1])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux7~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datab(!\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|Selector82~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[7][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector89~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector89~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector89~0 .lut_mask = 64'h00530053FF53FF53;
defparam \A_SPW_TOP|rx_data|Selector89~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X36_Y4_N14
dffeas \A_SPW_TOP|rx_data|mem[7][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector89~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[7][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[7][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[7][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X36_Y4_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector71~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector71~0_combout  = ( \A_SPW_TOP|rx_data|mem[5][1]~q  & ( (!\A_SPW_TOP|rx_data|Selector64~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [1]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux7~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[5][1]~q  & ( (\A_SPW_TOP|rx_data|Selector64~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [1]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux7~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .datac(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datad(!\A_SPW_TOP|rx_data|Selector64~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[5][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector71~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector71~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector71~0 .lut_mask = 64'h001B001BFF1BFF1B;
defparam \A_SPW_TOP|rx_data|Selector71~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X36_Y4_N8
dffeas \A_SPW_TOP|rx_data|mem[5][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector71~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[5][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[5][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[5][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X36_Y4_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux7~10 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux7~10_combout  = ( \A_SPW_TOP|rx_data|mem[7][1]~q  & ( \A_SPW_TOP|rx_data|mem[5][1]~q  & ( ((!\A_SPW_TOP|rx_data|wr_ptr [1] & ((\A_SPW_TOP|rx_data|mem[4][1]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|mem[6][1]~q ))) 
// # (\A_SPW_TOP|rx_data|wr_ptr [0]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[7][1]~q  & ( \A_SPW_TOP|rx_data|mem[5][1]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & ((!\A_SPW_TOP|rx_data|wr_ptr [1] & ((\A_SPW_TOP|rx_data|mem[4][1]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [1] 
// & (\A_SPW_TOP|rx_data|mem[6][1]~q )))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & (!\A_SPW_TOP|rx_data|wr_ptr [1])) ) ) ) # ( \A_SPW_TOP|rx_data|mem[7][1]~q  & ( !\A_SPW_TOP|rx_data|mem[5][1]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & ((!\A_SPW_TOP|rx_data|wr_ptr 
// [1] & ((\A_SPW_TOP|rx_data|mem[4][1]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|mem[6][1]~q )))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|wr_ptr [1])) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[7][1]~q  & ( 
// !\A_SPW_TOP|rx_data|mem[5][1]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & ((!\A_SPW_TOP|rx_data|wr_ptr [1] & ((\A_SPW_TOP|rx_data|mem[4][1]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|mem[6][1]~q )))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datac(!\A_SPW_TOP|rx_data|mem[6][1]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[4][1]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[7][1]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[5][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux7~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux7~10 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux7~10 .lut_mask = 64'h028A139B46CE57DF;
defparam \A_SPW_TOP|rx_data|Mux7~10 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y4_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux7~14 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux7~14_combout  = ( \A_SPW_TOP|rx_data|Mux7~12_combout  & ( \A_SPW_TOP|rx_data|Mux7~10_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [3]) # ((!\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|Mux7~11_combout )) # 
// (\A_SPW_TOP|rx_data|wr_ptr [5] & ((\A_SPW_TOP|rx_data|Mux7~13_combout )))) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux7~12_combout  & ( \A_SPW_TOP|rx_data|Mux7~10_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & (((!\A_SPW_TOP|rx_data|wr_ptr [3])) # 
// (\A_SPW_TOP|rx_data|Mux7~11_combout ))) # (\A_SPW_TOP|rx_data|wr_ptr [5] & (((\A_SPW_TOP|rx_data|Mux7~13_combout  & \A_SPW_TOP|rx_data|wr_ptr [3])))) ) ) ) # ( \A_SPW_TOP|rx_data|Mux7~12_combout  & ( !\A_SPW_TOP|rx_data|Mux7~10_combout  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|Mux7~11_combout  & ((\A_SPW_TOP|rx_data|wr_ptr [3])))) # (\A_SPW_TOP|rx_data|wr_ptr [5] & (((!\A_SPW_TOP|rx_data|wr_ptr [3]) # (\A_SPW_TOP|rx_data|Mux7~13_combout )))) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|Mux7~12_combout  & ( !\A_SPW_TOP|rx_data|Mux7~10_combout  & ( (\A_SPW_TOP|rx_data|wr_ptr [3] & ((!\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|Mux7~11_combout )) # (\A_SPW_TOP|rx_data|wr_ptr [5] & 
// ((\A_SPW_TOP|rx_data|Mux7~13_combout ))))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datab(!\A_SPW_TOP|rx_data|Mux7~11_combout ),
        .datac(!\A_SPW_TOP|rx_data|Mux7~13_combout ),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datae(!\A_SPW_TOP|rx_data|Mux7~12_combout ),
        .dataf(!\A_SPW_TOP|rx_data|Mux7~10_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux7~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux7~14 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux7~14 .lut_mask = 64'h00275527AA27FF27;
defparam \A_SPW_TOP|rx_data|Mux7~14 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y4_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector539~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector539~0_combout  = ( \A_SPW_TOP|rx_data|Selector532~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [1])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux7~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector532~0_combout  & ( \A_SPW_TOP|rx_data|mem[57][1]~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[57][1]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector532~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector539~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector539~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector539~0 .lut_mask = 64'h00FF00FF47474747;
defparam \A_SPW_TOP|rx_data|Selector539~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y4_N56
dffeas \A_SPW_TOP|rx_data|mem[57][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector539~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[57][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[57][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[57][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y4_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector530~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector530~0_combout  = ( \A_SPW_TOP|rx_data|Mux7~20_combout  & ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (\A_SPW_TOP|rx_data|Selector523~0_combout ) # (\A_SPW_TOP|rx_data|mem[56][1]~q ) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|Mux7~20_combout  & ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (\A_SPW_TOP|rx_data|mem[56][1]~q  & !\A_SPW_TOP|rx_data|Selector523~0_combout ) ) ) ) # ( \A_SPW_TOP|rx_data|Mux7~20_combout  & ( 
// !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector523~0_combout  & (\A_SPW_TOP|rx_data|mem[56][1]~q )) # (\A_SPW_TOP|rx_data|Selector523~0_combout  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [1]))) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|Mux7~20_combout  & ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector523~0_combout  & (\A_SPW_TOP|rx_data|mem[56][1]~q )) # (\A_SPW_TOP|rx_data|Selector523~0_combout  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [1]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[56][1]~q ),
        .datab(!\A_SPW_TOP|rx_data|Selector523~0_combout ),
        .datac(gnd),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datae(!\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector530~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector530~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector530~0 .lut_mask = 64'h4477447744447777;
defparam \A_SPW_TOP|rx_data|Selector530~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y4_N35
dffeas \A_SPW_TOP|rx_data|mem[56][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector530~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[56][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[56][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[56][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X40_Y4_N51
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector548~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector548~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector541~0_combout  & ((\A_SPW_TOP|rx_data|mem[58][1]~q ))) # (\A_SPW_TOP|rx_data|Selector541~0_combout  & 
// (\A_SPW_TOP|rx_data|Mux7~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector541~0_combout  & ((\A_SPW_TOP|rx_data|mem[58][1]~q ))) # (\A_SPW_TOP|rx_data|Selector541~0_combout  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [1])) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datac(!\A_SPW_TOP|rx_data|mem[58][1]~q ),
        .datad(!\A_SPW_TOP|rx_data|Selector541~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector548~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector548~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector548~0 .lut_mask = 64'h0F330F330F550F55;
defparam \A_SPW_TOP|rx_data|Selector548~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y4_N2
dffeas \A_SPW_TOP|rx_data|mem[58][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector548~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[58][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[58][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[58][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y4_N45
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector557~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector557~0_combout  = ( \A_SPW_TOP|rx_data|Mux7~20_combout  & ( (!\A_SPW_TOP|rx_data|Selector550~0_combout  & (((\A_SPW_TOP|rx_data|mem[59][1]~q )))) # (\A_SPW_TOP|rx_data|Selector550~0_combout  & 
// (((\A_SPW_TOP|rx_data|state_data_write.00~q )) # (\A_SPW_TOP|SPW|RX|rx_data_flag [1]))) ) ) # ( !\A_SPW_TOP|rx_data|Mux7~20_combout  & ( (!\A_SPW_TOP|rx_data|Selector550~0_combout  & (((\A_SPW_TOP|rx_data|mem[59][1]~q )))) # 
// (\A_SPW_TOP|rx_data|Selector550~0_combout  & (\A_SPW_TOP|SPW|RX|rx_data_flag [1] & (!\A_SPW_TOP|rx_data|state_data_write.00~q ))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Selector550~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[59][1]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector557~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector557~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector557~0 .lut_mask = 64'h04F404F407F707F7;
defparam \A_SPW_TOP|rx_data|Selector557~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y4_N23
dffeas \A_SPW_TOP|rx_data|mem[59][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector557~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[59][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[59][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[59][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y4_N39
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux7~8 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux7~8_combout  = ( \A_SPW_TOP|rx_data|mem[59][1]~q  & ( \A_SPW_TOP|rx_data|wr_ptr [0] & ( (\A_SPW_TOP|rx_data|wr_ptr [1]) # (\A_SPW_TOP|rx_data|mem[57][1]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[59][1]~q  & ( \A_SPW_TOP|rx_data|wr_ptr 
// [0] & ( (\A_SPW_TOP|rx_data|mem[57][1]~q  & !\A_SPW_TOP|rx_data|wr_ptr [1]) ) ) ) # ( \A_SPW_TOP|rx_data|mem[59][1]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [0] & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|mem[56][1]~q )) # 
// (\A_SPW_TOP|rx_data|wr_ptr [1] & ((\A_SPW_TOP|rx_data|mem[58][1]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[59][1]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [0] & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|mem[56][1]~q )) # (\A_SPW_TOP|rx_data|wr_ptr 
// [1] & ((\A_SPW_TOP|rx_data|mem[58][1]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[57][1]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[56][1]~q ),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datad(!\A_SPW_TOP|rx_data|mem[58][1]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[59][1]~q ),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux7~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux7~8 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux7~8 .lut_mask = 64'h303F303F50505F5F;
defparam \A_SPW_TOP|rx_data|Mux7~8 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y4_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector269~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector269~0_combout  = ( \A_SPW_TOP|rx_data|mem[27][1]~q  & ( (!\A_SPW_TOP|rx_data|Selector262~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [1])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux7~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[27][1]~q  & ( (\A_SPW_TOP|rx_data|Selector262~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [1])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux7~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .datad(!\A_SPW_TOP|rx_data|Selector262~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[27][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector269~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector269~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector269~0 .lut_mask = 64'h00470047FF47FF47;
defparam \A_SPW_TOP|rx_data|Selector269~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y4_N17
dffeas \A_SPW_TOP|rx_data|mem[27][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector269~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[27][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[27][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[27][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y4_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector242~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector242~0_combout  = ( \A_SPW_TOP|rx_data|mem[24][1]~q  & ( (!\A_SPW_TOP|rx_data|Selector235~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [1])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux7~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[24][1]~q  & ( (\A_SPW_TOP|rx_data|Selector235~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [1])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux7~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .datad(!\A_SPW_TOP|rx_data|Selector235~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[24][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector242~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector242~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector242~0 .lut_mask = 64'h00470047FF47FF47;
defparam \A_SPW_TOP|rx_data|Selector242~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y4_N35
dffeas \A_SPW_TOP|rx_data|mem[24][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector242~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[24][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[24][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[24][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y4_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector251~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector251~0_combout  = ( \A_SPW_TOP|rx_data|Selector244~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [1])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux7~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector244~0_combout  & ( \A_SPW_TOP|rx_data|mem[25][1]~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[25][1]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector244~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector251~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector251~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector251~0 .lut_mask = 64'h00FF00FF47474747;
defparam \A_SPW_TOP|rx_data|Selector251~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y4_N47
dffeas \A_SPW_TOP|rx_data|mem[25][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector251~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[25][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[25][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[25][1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y4_N45
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector260~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector260~0_combout  = ( \A_SPW_TOP|SPW|RX|rx_data_flag [1] & ( (!\A_SPW_TOP|rx_data|Selector253~0_combout  & (((\A_SPW_TOP|rx_data|mem[26][1]~q )))) # (\A_SPW_TOP|rx_data|Selector253~0_combout  & 
// ((!\A_SPW_TOP|rx_data|state_data_write.00~q ) # ((\A_SPW_TOP|rx_data|Mux7~20_combout )))) ) ) # ( !\A_SPW_TOP|SPW|RX|rx_data_flag [1] & ( (!\A_SPW_TOP|rx_data|Selector253~0_combout  & (((\A_SPW_TOP|rx_data|mem[26][1]~q )))) # 
// (\A_SPW_TOP|rx_data|Selector253~0_combout  & (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux7~20_combout ))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|mem[26][1]~q ),
        .datad(!\A_SPW_TOP|rx_data|Selector253~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector260~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector260~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector260~0 .lut_mask = 64'h0F110F110FBB0FBB;
defparam \A_SPW_TOP|rx_data|Selector260~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y4_N35
dffeas \A_SPW_TOP|rx_data|mem[26][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector260~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[26][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[26][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[26][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y4_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux7~6 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux7~6_combout  = ( \A_SPW_TOP|rx_data|mem[25][1]~q  & ( \A_SPW_TOP|rx_data|mem[26][1]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & (((\A_SPW_TOP|rx_data|wr_ptr [0]) # (\A_SPW_TOP|rx_data|mem[24][1]~q )))) # (\A_SPW_TOP|rx_data|wr_ptr [1] & 
// (((!\A_SPW_TOP|rx_data|wr_ptr [0])) # (\A_SPW_TOP|rx_data|mem[27][1]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[25][1]~q  & ( \A_SPW_TOP|rx_data|mem[26][1]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & (((\A_SPW_TOP|rx_data|mem[24][1]~q  & 
// !\A_SPW_TOP|rx_data|wr_ptr [0])))) # (\A_SPW_TOP|rx_data|wr_ptr [1] & (((!\A_SPW_TOP|rx_data|wr_ptr [0])) # (\A_SPW_TOP|rx_data|mem[27][1]~q ))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[25][1]~q  & ( !\A_SPW_TOP|rx_data|mem[26][1]~q  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [1] & (((\A_SPW_TOP|rx_data|wr_ptr [0]) # (\A_SPW_TOP|rx_data|mem[24][1]~q )))) # (\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|mem[27][1]~q  & ((\A_SPW_TOP|rx_data|wr_ptr [0])))) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|mem[25][1]~q  & ( !\A_SPW_TOP|rx_data|mem[26][1]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & (((\A_SPW_TOP|rx_data|mem[24][1]~q  & !\A_SPW_TOP|rx_data|wr_ptr [0])))) # (\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|mem[27][1]~q  & 
// ((\A_SPW_TOP|rx_data|wr_ptr [0])))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datab(!\A_SPW_TOP|rx_data|mem[27][1]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[24][1]~q ),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datae(!\A_SPW_TOP|rx_data|mem[25][1]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[26][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux7~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux7~6 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux7~6 .lut_mask = 64'h0A110ABB5F115FBB;
defparam \A_SPW_TOP|rx_data|Mux7~6 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y4_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector170~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector170~0_combout  = ( \A_SPW_TOP|rx_data|mem[16][1]~q  & ( (!\A_SPW_TOP|rx_data|Selector163~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [1])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux7~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[16][1]~q  & ( (\A_SPW_TOP|rx_data|Selector163~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [1])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux7~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datab(!\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector163~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[16][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector170~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector170~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector170~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|rx_data|Selector170~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X45_Y4_N53
dffeas \A_SPW_TOP|rx_data|mem[16][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector170~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[16][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[16][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[16][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y4_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector188~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector188~0_combout  = ( \A_SPW_TOP|rx_data|mem[18][1]~q  & ( (!\A_SPW_TOP|rx_data|Selector181~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [1]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux7~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[18][1]~q  & ( (\A_SPW_TOP|rx_data|Selector181~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [1]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux7~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Selector181~0_combout ),
        .datab(!\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .datac(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[18][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector188~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector188~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector188~0 .lut_mask = 64'h05110511AFBBAFBB;
defparam \A_SPW_TOP|rx_data|Selector188~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X45_Y4_N11
dffeas \A_SPW_TOP|rx_data|mem[18][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector188~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[18][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[18][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[18][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y4_N21
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector197~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector197~0_combout  = ( \A_SPW_TOP|SPW|RX|rx_data_flag [1] & ( (!\A_SPW_TOP|rx_data|Selector190~0_combout  & (((\A_SPW_TOP|rx_data|mem[19][1]~q )))) # (\A_SPW_TOP|rx_data|Selector190~0_combout  & 
// ((!\A_SPW_TOP|rx_data|state_data_write.00~q ) # ((\A_SPW_TOP|rx_data|Mux7~20_combout )))) ) ) # ( !\A_SPW_TOP|SPW|RX|rx_data_flag [1] & ( (!\A_SPW_TOP|rx_data|Selector190~0_combout  & (((\A_SPW_TOP|rx_data|mem[19][1]~q )))) # 
// (\A_SPW_TOP|rx_data|Selector190~0_combout  & (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux7~20_combout ))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector190~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[19][1]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector197~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector197~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector197~0 .lut_mask = 64'h01F101F10BFB0BFB;
defparam \A_SPW_TOP|rx_data|Selector197~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X45_Y4_N29
dffeas \A_SPW_TOP|rx_data|mem[19][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector197~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[19][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[19][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[19][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y4_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector179~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector179~0_combout  = ( \A_SPW_TOP|rx_data|Selector172~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [1])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux7~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector172~0_combout  & ( \A_SPW_TOP|rx_data|mem[17][1]~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[17][1]~q ),
        .datad(!\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector172~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector179~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector179~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector179~0 .lut_mask = 64'h0F0F0F0F44774477;
defparam \A_SPW_TOP|rx_data|Selector179~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y4_N44
dffeas \A_SPW_TOP|rx_data|mem[17][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector179~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[17][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[17][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[17][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y4_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux7~5 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux7~5_combout  = ( \A_SPW_TOP|rx_data|mem[19][1]~q  & ( \A_SPW_TOP|rx_data|mem[17][1]~q  & ( ((!\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|mem[16][1]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [1] & ((\A_SPW_TOP|rx_data|mem[18][1]~q 
// )))) # (\A_SPW_TOP|rx_data|wr_ptr [0]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[19][1]~q  & ( \A_SPW_TOP|rx_data|mem[17][1]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & ((!\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|mem[16][1]~q )) # 
// (\A_SPW_TOP|rx_data|wr_ptr [1] & ((\A_SPW_TOP|rx_data|mem[18][1]~q ))))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & (((!\A_SPW_TOP|rx_data|wr_ptr [1])))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[19][1]~q  & ( !\A_SPW_TOP|rx_data|mem[17][1]~q  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [0] & ((!\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|mem[16][1]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [1] & ((\A_SPW_TOP|rx_data|mem[18][1]~q ))))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & (((\A_SPW_TOP|rx_data|wr_ptr [1])))) ) ) 
// ) # ( !\A_SPW_TOP|rx_data|mem[19][1]~q  & ( !\A_SPW_TOP|rx_data|mem[17][1]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & ((!\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|mem[16][1]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [1] & ((\A_SPW_TOP|rx_data|mem[18][1]~q 
// ))))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[16][1]~q ),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datad(!\A_SPW_TOP|rx_data|mem[18][1]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[19][1]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[17][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux7~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux7~5 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux7~5 .lut_mask = 64'h404C434F707C737F;
defparam \A_SPW_TOP|rx_data|Mux7~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y4_N27
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector467~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector467~0_combout  = ( \A_SPW_TOP|rx_data|mem[49][1]~q  & ( (!\A_SPW_TOP|rx_data|Selector460~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [1])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux7~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[49][1]~q  & ( (\A_SPW_TOP|rx_data|Selector460~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [1])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux7~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Selector460~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[49][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector467~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector467~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector467~0 .lut_mask = 64'h04070407F4F7F4F7;
defparam \A_SPW_TOP|rx_data|Selector467~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y4_N20
dffeas \A_SPW_TOP|rx_data|mem[49][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector467~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[49][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[49][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[49][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y4_N57
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector485~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector485~0_combout  = ( \A_SPW_TOP|rx_data|Selector478~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [1])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux7~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector478~0_combout  & ( \A_SPW_TOP|rx_data|mem[51][1]~q  ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[51][1]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector478~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector485~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector485~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector485~0 .lut_mask = 64'h00FF00FF47474747;
defparam \A_SPW_TOP|rx_data|Selector485~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y4_N23
dffeas \A_SPW_TOP|rx_data|mem[51][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector485~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[51][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[51][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[51][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y4_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector458~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector458~0_combout  = ( \A_SPW_TOP|rx_data|Mux7~20_combout  & ( \A_SPW_TOP|rx_data|Selector451~0_combout  & ( (\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|SPW|RX|rx_data_flag [1]) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|Mux7~20_combout  & ( \A_SPW_TOP|rx_data|Selector451~0_combout  & ( (\A_SPW_TOP|SPW|RX|rx_data_flag [1] & !\A_SPW_TOP|rx_data|state_data_write.00~q ) ) ) ) # ( \A_SPW_TOP|rx_data|Mux7~20_combout  & ( 
// !\A_SPW_TOP|rx_data|Selector451~0_combout  & ( \A_SPW_TOP|rx_data|mem[48][1]~q  ) ) ) # ( !\A_SPW_TOP|rx_data|Mux7~20_combout  & ( !\A_SPW_TOP|rx_data|Selector451~0_combout  & ( \A_SPW_TOP|rx_data|mem[48][1]~q  ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|rx_data|mem[48][1]~q ),
        .datac(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(!\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .dataf(!\A_SPW_TOP|rx_data|Selector451~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector458~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector458~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector458~0 .lut_mask = 64'h333333330F000FFF;
defparam \A_SPW_TOP|rx_data|Selector458~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y4_N41
dffeas \A_SPW_TOP|rx_data|mem[48][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector458~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[48][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[48][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[48][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y4_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector476~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector476~0_combout  = ( \A_SPW_TOP|SPW|RX|rx_data_flag [1] & ( (!\A_SPW_TOP|rx_data|Selector469~0_combout  & (((\A_SPW_TOP|rx_data|mem[50][1]~q )))) # (\A_SPW_TOP|rx_data|Selector469~0_combout  & 
// (((!\A_SPW_TOP|rx_data|state_data_write.00~q )) # (\A_SPW_TOP|rx_data|Mux7~20_combout ))) ) ) # ( !\A_SPW_TOP|SPW|RX|rx_data_flag [1] & ( (!\A_SPW_TOP|rx_data|Selector469~0_combout  & (((\A_SPW_TOP|rx_data|mem[50][1]~q )))) # 
// (\A_SPW_TOP|rx_data|Selector469~0_combout  & (\A_SPW_TOP|rx_data|Mux7~20_combout  & (\A_SPW_TOP|rx_data|state_data_write.00~q ))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Selector469~0_combout ),
        .datab(!\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[50][1]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector476~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector476~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector476~0 .lut_mask = 64'h01AB01AB51FB51FB;
defparam \A_SPW_TOP|rx_data|Selector476~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X45_Y4_N47
dffeas \A_SPW_TOP|rx_data|mem[50][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector476~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[50][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[50][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[50][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y4_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux7~7 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux7~7_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [1] & ( \A_SPW_TOP|rx_data|mem[50][1]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [0]) # (\A_SPW_TOP|rx_data|mem[51][1]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [1] & ( 
// \A_SPW_TOP|rx_data|mem[50][1]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & ((\A_SPW_TOP|rx_data|mem[48][1]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|mem[49][1]~q )) ) ) ) # ( \A_SPW_TOP|rx_data|wr_ptr [1] & ( 
// !\A_SPW_TOP|rx_data|mem[50][1]~q  & ( (\A_SPW_TOP|rx_data|wr_ptr [0] & \A_SPW_TOP|rx_data|mem[51][1]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [1] & ( !\A_SPW_TOP|rx_data|mem[50][1]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & ((\A_SPW_TOP|rx_data|mem[48][1]~q 
// ))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|mem[49][1]~q )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[49][1]~q ),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datac(!\A_SPW_TOP|rx_data|mem[51][1]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[48][1]~q ),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .dataf(!\A_SPW_TOP|rx_data|mem[50][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux7~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux7~7 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux7~7 .lut_mask = 64'h11DD030311DDCFCF;
defparam \A_SPW_TOP|rx_data|Mux7~7 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y4_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux7~9 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux7~9_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [3] & ( \A_SPW_TOP|rx_data|Mux7~7_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & ((\A_SPW_TOP|rx_data|Mux7~6_combout ))) # (\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|Mux7~8_combout 
// )) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [3] & ( \A_SPW_TOP|rx_data|Mux7~7_combout  & ( (\A_SPW_TOP|rx_data|Mux7~5_combout ) # (\A_SPW_TOP|rx_data|wr_ptr [5]) ) ) ) # ( \A_SPW_TOP|rx_data|wr_ptr [3] & ( !\A_SPW_TOP|rx_data|Mux7~7_combout  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [5] & ((\A_SPW_TOP|rx_data|Mux7~6_combout ))) # (\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|Mux7~8_combout )) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [3] & ( !\A_SPW_TOP|rx_data|Mux7~7_combout  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [5] & \A_SPW_TOP|rx_data|Mux7~5_combout ) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datab(!\A_SPW_TOP|rx_data|Mux7~8_combout ),
        .datac(!\A_SPW_TOP|rx_data|Mux7~6_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux7~5_combout ),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .dataf(!\A_SPW_TOP|rx_data|Mux7~7_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux7~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux7~9 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux7~9 .lut_mask = 64'h00AA1B1B55FF1B1B;
defparam \A_SPW_TOP|rx_data|Mux7~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y4_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector116~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector116~0_combout  = ( \A_SPW_TOP|rx_data|Selector109~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [1]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux7~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector109~0_combout  & ( \A_SPW_TOP|rx_data|mem[10][1]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[10][1]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector109~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector116~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector116~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector116~0 .lut_mask = 64'h00FF00FF35353535;
defparam \A_SPW_TOP|rx_data|Selector116~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y4_N23
dffeas \A_SPW_TOP|rx_data|mem[10][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector116~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[10][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[10][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[10][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y4_N45
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector125~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector125~0_combout  = ( \A_SPW_TOP|rx_data|Selector118~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [1]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux7~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector118~0_combout  & ( \A_SPW_TOP|rx_data|mem[11][1]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datac(!\A_SPW_TOP|rx_data|mem[11][1]~q ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector118~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector125~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector125~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector125~0 .lut_mask = 64'h0F0F0F0F33553355;
defparam \A_SPW_TOP|rx_data|Selector125~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y4_N8
dffeas \A_SPW_TOP|rx_data|mem[11][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector125~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[11][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[11][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[11][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y4_N27
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector98~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector98~0_combout  = ( \A_SPW_TOP|rx_data|mem[8][1]~q  & ( (!\A_SPW_TOP|rx_data|Selector91~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [1]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux7~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[8][1]~q  & ( (\A_SPW_TOP|rx_data|Selector91~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [1]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux7~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datac(!\A_SPW_TOP|rx_data|Selector91~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[8][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector98~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector98~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector98~0 .lut_mask = 64'h03050305F3F5F3F5;
defparam \A_SPW_TOP|rx_data|Selector98~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y4_N53
dffeas \A_SPW_TOP|rx_data|mem[8][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector98~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[8][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[8][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[8][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y4_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux7~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux7~1_combout  = ( \A_SPW_TOP|rx_data|mem[11][1]~q  & ( \A_SPW_TOP|rx_data|mem[8][1]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & (((!\A_SPW_TOP|rx_data|wr_ptr [1]) # (\A_SPW_TOP|rx_data|mem[10][1]~q )))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & 
// (((\A_SPW_TOP|rx_data|wr_ptr [1])) # (\A_SPW_TOP|rx_data|mem[9][1]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[11][1]~q  & ( \A_SPW_TOP|rx_data|mem[8][1]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & (((!\A_SPW_TOP|rx_data|wr_ptr [1]) # 
// (\A_SPW_TOP|rx_data|mem[10][1]~q )))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|mem[9][1]~q  & ((!\A_SPW_TOP|rx_data|wr_ptr [1])))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[11][1]~q  & ( !\A_SPW_TOP|rx_data|mem[8][1]~q  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [0] & (((\A_SPW_TOP|rx_data|mem[10][1]~q  & \A_SPW_TOP|rx_data|wr_ptr [1])))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & (((\A_SPW_TOP|rx_data|wr_ptr [1])) # (\A_SPW_TOP|rx_data|mem[9][1]~q ))) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|mem[11][1]~q  & ( !\A_SPW_TOP|rx_data|mem[8][1]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & (((\A_SPW_TOP|rx_data|mem[10][1]~q  & \A_SPW_TOP|rx_data|wr_ptr [1])))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|mem[9][1]~q  & 
// ((!\A_SPW_TOP|rx_data|wr_ptr [1])))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[9][1]~q ),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datac(!\A_SPW_TOP|rx_data|mem[10][1]~q ),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datae(!\A_SPW_TOP|rx_data|mem[11][1]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[8][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux7~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux7~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux7~1 .lut_mask = 64'h110C113FDD0CDD3F;
defparam \A_SPW_TOP|rx_data|Mux7~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y4_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector395~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector395~0_combout  = ( \A_SPW_TOP|rx_data|mem[41][1]~q  & ( (!\A_SPW_TOP|rx_data|Selector388~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [1]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux7~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[41][1]~q  & ( (\A_SPW_TOP|rx_data|Selector388~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [1]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux7~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datac(!\A_SPW_TOP|rx_data|Selector388~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[41][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector395~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector395~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector395~0 .lut_mask = 64'h03050305F3F5F3F5;
defparam \A_SPW_TOP|rx_data|Selector395~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y4_N41
dffeas \A_SPW_TOP|rx_data|mem[41][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector395~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[41][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[41][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[41][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y4_N27
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector404~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector404~0_combout  = ( \A_SPW_TOP|rx_data|mem[42][1]~q  & ( (!\A_SPW_TOP|rx_data|Selector397~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [1])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux7~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[42][1]~q  & ( (\A_SPW_TOP|rx_data|Selector397~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [1])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux7~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Selector397~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[42][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector404~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector404~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector404~0 .lut_mask = 64'h04070407F4F7F4F7;
defparam \A_SPW_TOP|rx_data|Selector404~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y4_N35
dffeas \A_SPW_TOP|rx_data|mem[42][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector404~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[42][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[42][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[42][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y4_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector386~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector386~0_combout  = ( \A_SPW_TOP|rx_data|mem[40][1]~q  & ( (!\A_SPW_TOP|rx_data|Selector379~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [1])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux7~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[40][1]~q  & ( (\A_SPW_TOP|rx_data|Selector379~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [1])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux7~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .datad(!\A_SPW_TOP|rx_data|Selector379~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[40][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector386~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector386~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector386~0 .lut_mask = 64'h00470047FF47FF47;
defparam \A_SPW_TOP|rx_data|Selector386~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y4_N32
dffeas \A_SPW_TOP|rx_data|mem[40][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector386~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[40][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[40][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[40][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y4_N57
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector413~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector413~0_combout  = ( \A_SPW_TOP|rx_data|Selector406~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [1]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux7~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector406~0_combout  & ( \A_SPW_TOP|rx_data|mem[43][1]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datac(!\A_SPW_TOP|rx_data|mem[43][1]~q ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector406~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector413~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector413~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector413~0 .lut_mask = 64'h0F0F0F0F33553355;
defparam \A_SPW_TOP|rx_data|Selector413~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y4_N11
dffeas \A_SPW_TOP|rx_data|mem[43][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector413~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[43][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[43][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[43][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y4_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux7~3 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux7~3_combout  = ( \A_SPW_TOP|rx_data|mem[40][1]~q  & ( \A_SPW_TOP|rx_data|mem[43][1]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & (((!\A_SPW_TOP|rx_data|wr_ptr [1]) # (\A_SPW_TOP|rx_data|mem[42][1]~q )))) # (\A_SPW_TOP|rx_data|wr_ptr [0] 
// & (((\A_SPW_TOP|rx_data|wr_ptr [1])) # (\A_SPW_TOP|rx_data|mem[41][1]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[40][1]~q  & ( \A_SPW_TOP|rx_data|mem[43][1]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & (((\A_SPW_TOP|rx_data|mem[42][1]~q  & 
// \A_SPW_TOP|rx_data|wr_ptr [1])))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & (((\A_SPW_TOP|rx_data|wr_ptr [1])) # (\A_SPW_TOP|rx_data|mem[41][1]~q ))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[40][1]~q  & ( !\A_SPW_TOP|rx_data|mem[43][1]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr 
// [0] & (((!\A_SPW_TOP|rx_data|wr_ptr [1]) # (\A_SPW_TOP|rx_data|mem[42][1]~q )))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|mem[41][1]~q  & ((!\A_SPW_TOP|rx_data|wr_ptr [1])))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[40][1]~q  & ( 
// !\A_SPW_TOP|rx_data|mem[43][1]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & (((\A_SPW_TOP|rx_data|mem[42][1]~q  & \A_SPW_TOP|rx_data|wr_ptr [1])))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|mem[41][1]~q  & ((!\A_SPW_TOP|rx_data|wr_ptr [1])))) ) ) 
// )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datab(!\A_SPW_TOP|rx_data|mem[41][1]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[42][1]~q ),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datae(!\A_SPW_TOP|rx_data|mem[40][1]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[43][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux7~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux7~3 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux7~3 .lut_mask = 64'h110ABB0A115FBB5F;
defparam \A_SPW_TOP|rx_data|Mux7~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X35_Y4_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector44~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector44~0_combout  = ( \A_SPW_TOP|rx_data|mem[2][1]~q  & ( (!\A_SPW_TOP|rx_data|Selector37~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [1])) # (\A_SPW_TOP|rx_data|state_data_write.00~q 
//  & ((\A_SPW_TOP|rx_data|Mux7~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[2][1]~q  & ( (\A_SPW_TOP|rx_data|Selector37~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [1])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux7~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .datad(!\A_SPW_TOP|rx_data|Selector37~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[2][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector44~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector44~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector44~0 .lut_mask = 64'h00470047FF47FF47;
defparam \A_SPW_TOP|rx_data|Selector44~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X36_Y4_N47
dffeas \A_SPW_TOP|rx_data|mem[2][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector44~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[2][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[2][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[2][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X36_Y4_N57
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector35~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector35~0_combout  = ( \A_SPW_TOP|rx_data|Selector28~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [1]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux7~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector28~0_combout  & ( \A_SPW_TOP|rx_data|mem[1][1]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|mem[1][1]~q ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector28~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector35~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector35~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector35~0 .lut_mask = 64'h0F0F0F0F11BB11BB;
defparam \A_SPW_TOP|rx_data|Selector35~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X36_Y4_N11
dffeas \A_SPW_TOP|rx_data|mem[1][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector35~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[1][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[1][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[1][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X36_Y4_N39
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector53~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector53~0_combout  = ( \A_SPW_TOP|rx_data|mem[3][1]~q  & ( (!\A_SPW_TOP|rx_data|Selector46~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [1])) # (\A_SPW_TOP|rx_data|state_data_write.00~q 
//  & ((\A_SPW_TOP|rx_data|Mux7~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[3][1]~q  & ( (\A_SPW_TOP|rx_data|Selector46~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [1])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux7~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datab(!\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector46~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[3][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector53~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector53~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector53~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|rx_data|Selector53~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X36_Y4_N50
dffeas \A_SPW_TOP|rx_data|mem[3][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector53~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[3][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[3][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[3][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X36_Y4_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector26~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector26~0_combout  = ( \A_SPW_TOP|rx_data|mem[0][1]~q  & ( (!\A_SPW_TOP|rx_data|Selector19~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [1]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux7~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[0][1]~q  & ( (\A_SPW_TOP|rx_data|Selector19~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [1]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux7~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector19~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[0][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector26~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector26~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector26~0 .lut_mask = 64'h010B010BF1FBF1FB;
defparam \A_SPW_TOP|rx_data|Selector26~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X36_Y4_N44
dffeas \A_SPW_TOP|rx_data|mem[0][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector26~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[0][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[0][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[0][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X36_Y4_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux7~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux7~0_combout  = ( \A_SPW_TOP|rx_data|mem[3][1]~q  & ( \A_SPW_TOP|rx_data|mem[0][1]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & ((!\A_SPW_TOP|rx_data|wr_ptr [1]) # ((\A_SPW_TOP|rx_data|mem[2][1]~q )))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & 
// (((\A_SPW_TOP|rx_data|mem[1][1]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [1]))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[3][1]~q  & ( \A_SPW_TOP|rx_data|mem[0][1]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & ((!\A_SPW_TOP|rx_data|wr_ptr [1]) # 
// ((\A_SPW_TOP|rx_data|mem[2][1]~q )))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & (!\A_SPW_TOP|rx_data|wr_ptr [1] & ((\A_SPW_TOP|rx_data|mem[1][1]~q )))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[3][1]~q  & ( !\A_SPW_TOP|rx_data|mem[0][1]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr 
// [0] & (\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|mem[2][1]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & (((\A_SPW_TOP|rx_data|mem[1][1]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [1]))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[3][1]~q  & ( 
// !\A_SPW_TOP|rx_data|mem[0][1]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|mem[2][1]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & (!\A_SPW_TOP|rx_data|wr_ptr [1] & ((\A_SPW_TOP|rx_data|mem[1][1]~q )))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datac(!\A_SPW_TOP|rx_data|mem[2][1]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[1][1]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[3][1]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[0][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux7~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux7~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux7~0 .lut_mask = 64'h024613578ACE9BDF;
defparam \A_SPW_TOP|rx_data|Mux7~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y4_N39
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector332~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector332~0_combout  = ( \A_SPW_TOP|rx_data|Selector325~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [1]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux7~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector325~0_combout  & ( \A_SPW_TOP|rx_data|mem[34][1]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datad(!\A_SPW_TOP|rx_data|mem[34][1]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector325~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector332~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector332~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector332~0 .lut_mask = 64'h00FF00FF1D1D1D1D;
defparam \A_SPW_TOP|rx_data|Selector332~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y4_N5
dffeas \A_SPW_TOP|rx_data|mem[34][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector332~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[34][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[34][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[34][1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y4_N21
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector314~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector314~0_combout  = ( \A_SPW_TOP|rx_data|mem[32][1]~q  & ( (!\A_SPW_TOP|rx_data|Selector307~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [1]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux7~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[32][1]~q  & ( (\A_SPW_TOP|rx_data|Selector307~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [1]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux7~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Selector307~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[32][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector314~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector314~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector314~0 .lut_mask = 64'h010D010DF1FDF1FD;
defparam \A_SPW_TOP|rx_data|Selector314~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y4_N35
dffeas \A_SPW_TOP|rx_data|mem[32][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector314~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[32][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[32][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[32][1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y4_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector341~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector341~0_combout  = ( \A_SPW_TOP|rx_data|mem[35][1]~q  & ( (!\A_SPW_TOP|rx_data|Selector334~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [1]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux7~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[35][1]~q  & ( (\A_SPW_TOP|rx_data|Selector334~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [1]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux7~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Selector334~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[35][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector341~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector341~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector341~0 .lut_mask = 64'h010D010DF1FDF1FD;
defparam \A_SPW_TOP|rx_data|Selector341~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y4_N17
dffeas \A_SPW_TOP|rx_data|mem[35][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector341~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[35][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[35][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[35][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X36_Y4_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector323~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector323~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector316~0_combout  & ((\A_SPW_TOP|rx_data|mem[33][1]~q ))) # (\A_SPW_TOP|rx_data|Selector316~0_combout  & 
// (\A_SPW_TOP|rx_data|Mux7~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector316~0_combout  & ((\A_SPW_TOP|rx_data|mem[33][1]~q ))) # (\A_SPW_TOP|rx_data|Selector316~0_combout  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [1])) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datab(!\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|mem[33][1]~q ),
        .datad(!\A_SPW_TOP|rx_data|Selector316~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector323~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector323~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector323~0 .lut_mask = 64'h0F550F550F330F33;
defparam \A_SPW_TOP|rx_data|Selector323~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X37_Y4_N53
dffeas \A_SPW_TOP|rx_data|mem[33][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector323~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[33][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[33][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[33][1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X37_Y4_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux7~2 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux7~2_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [0] & ( \A_SPW_TOP|rx_data|mem[33][1]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [1]) # (\A_SPW_TOP|rx_data|mem[35][1]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [0] & ( 
// \A_SPW_TOP|rx_data|mem[33][1]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & ((\A_SPW_TOP|rx_data|mem[32][1]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|mem[34][1]~q )) ) ) ) # ( \A_SPW_TOP|rx_data|wr_ptr [0] & ( 
// !\A_SPW_TOP|rx_data|mem[33][1]~q  & ( (\A_SPW_TOP|rx_data|wr_ptr [1] & \A_SPW_TOP|rx_data|mem[35][1]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [0] & ( !\A_SPW_TOP|rx_data|mem[33][1]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & ((\A_SPW_TOP|rx_data|mem[32][1]~q 
// ))) # (\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|mem[34][1]~q )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[34][1]~q ),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datac(!\A_SPW_TOP|rx_data|mem[32][1]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[35][1]~q ),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .dataf(!\A_SPW_TOP|rx_data|mem[33][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux7~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux7~2 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux7~2 .lut_mask = 64'h1D1D00331D1DCCFF;
defparam \A_SPW_TOP|rx_data|Mux7~2 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y4_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux7~4 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux7~4_combout  = ( \A_SPW_TOP|rx_data|Mux7~0_combout  & ( \A_SPW_TOP|rx_data|Mux7~2_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [3]) # ((!\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|Mux7~1_combout )) # (\A_SPW_TOP|rx_data|wr_ptr 
// [5] & ((\A_SPW_TOP|rx_data|Mux7~3_combout )))) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux7~0_combout  & ( \A_SPW_TOP|rx_data|Mux7~2_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [3] & (((\A_SPW_TOP|rx_data|wr_ptr [5])))) # (\A_SPW_TOP|rx_data|wr_ptr [3] & 
// ((!\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|Mux7~1_combout )) # (\A_SPW_TOP|rx_data|wr_ptr [5] & ((\A_SPW_TOP|rx_data|Mux7~3_combout ))))) ) ) ) # ( \A_SPW_TOP|rx_data|Mux7~0_combout  & ( !\A_SPW_TOP|rx_data|Mux7~2_combout  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [3] & (((!\A_SPW_TOP|rx_data|wr_ptr [5])))) # (\A_SPW_TOP|rx_data|wr_ptr [3] & ((!\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|Mux7~1_combout )) # (\A_SPW_TOP|rx_data|wr_ptr [5] & ((\A_SPW_TOP|rx_data|Mux7~3_combout 
// ))))) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux7~0_combout  & ( !\A_SPW_TOP|rx_data|Mux7~2_combout  & ( (\A_SPW_TOP|rx_data|wr_ptr [3] & ((!\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|Mux7~1_combout )) # (\A_SPW_TOP|rx_data|wr_ptr [5] & 
// ((\A_SPW_TOP|rx_data|Mux7~3_combout ))))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux7~1_combout ),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datad(!\A_SPW_TOP|rx_data|Mux7~3_combout ),
        .datae(!\A_SPW_TOP|rx_data|Mux7~0_combout ),
        .dataf(!\A_SPW_TOP|rx_data|Mux7~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux7~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux7~4 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux7~4 .lut_mask = 64'h1013D0D31C1FDCDF;
defparam \A_SPW_TOP|rx_data|Mux7~4 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y4_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux7~20 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux7~20_combout  = ( \A_SPW_TOP|rx_data|Mux7~9_combout  & ( \A_SPW_TOP|rx_data|Mux7~4_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2]) # ((!\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|Mux7~14_combout ))) # 
// (\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|Mux7~19_combout ))) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux7~9_combout  & ( \A_SPW_TOP|rx_data|Mux7~4_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & (((!\A_SPW_TOP|rx_data|wr_ptr [4])))) # 
// (\A_SPW_TOP|rx_data|wr_ptr [2] & ((!\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|Mux7~14_combout ))) # (\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|Mux7~19_combout )))) ) ) ) # ( \A_SPW_TOP|rx_data|Mux7~9_combout  & ( 
// !\A_SPW_TOP|rx_data|Mux7~4_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & (((\A_SPW_TOP|rx_data|wr_ptr [4])))) # (\A_SPW_TOP|rx_data|wr_ptr [2] & ((!\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|Mux7~14_combout ))) # (\A_SPW_TOP|rx_data|wr_ptr [4] 
// & (\A_SPW_TOP|rx_data|Mux7~19_combout )))) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux7~9_combout  & ( !\A_SPW_TOP|rx_data|Mux7~4_combout  & ( (\A_SPW_TOP|rx_data|wr_ptr [2] & ((!\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|Mux7~14_combout ))) # 
// (\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|Mux7~19_combout )))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux7~19_combout ),
        .datab(!\A_SPW_TOP|rx_data|Mux7~14_combout ),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datae(!\A_SPW_TOP|rx_data|Mux7~9_combout ),
        .dataf(!\A_SPW_TOP|rx_data|Mux7~4_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux7~20 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux7~20 .lut_mask = 64'h030503F5F305F3F5;
defparam \A_SPW_TOP|rx_data|Mux7~20 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y4_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector107~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector107~0_combout  = ( \A_SPW_TOP|rx_data|Mux7~20_combout  & ( (!\A_SPW_TOP|rx_data|Selector100~0_combout  & (((\A_SPW_TOP|rx_data|mem[9][1]~q )))) # (\A_SPW_TOP|rx_data|Selector100~0_combout  & (((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [1])) # (\A_SPW_TOP|rx_data|state_data_write.00~q ))) ) ) # ( !\A_SPW_TOP|rx_data|Mux7~20_combout  & ( (!\A_SPW_TOP|rx_data|Selector100~0_combout  & (((\A_SPW_TOP|rx_data|mem[9][1]~q )))) # (\A_SPW_TOP|rx_data|Selector100~0_combout  & 
// (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [1]))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
        .datac(!\A_SPW_TOP|rx_data|Selector100~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[9][1]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Mux7~20_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector107~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector107~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector107~0 .lut_mask = 64'h02F202F207F707F7;
defparam \A_SPW_TOP|rx_data|Selector107~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X38_Y4_N38
dffeas \A_SPW_TOP|rx_data|mem[9][1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector107~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[9][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[9][1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[9][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X38_Y4_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux16~7 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux16~7_combout  = ( \A_SPW_TOP|rx_data|mem[13][1]~q  & ( \A_SPW_TOP|rx_data|rd_ptr [2] & ( (!\A_SPW_TOP|rx_data|rd_ptr [1]) # (\A_SPW_TOP|rx_data|mem[15][1]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[13][1]~q  & ( \A_SPW_TOP|rx_data|rd_ptr 
// [2] & ( (\A_SPW_TOP|rx_data|mem[15][1]~q  & \A_SPW_TOP|rx_data|rd_ptr [1]) ) ) ) # ( \A_SPW_TOP|rx_data|mem[13][1]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [2] & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|mem[9][1]~q )) # (\A_SPW_TOP|rx_data|rd_ptr 
// [1] & ((\A_SPW_TOP|rx_data|mem[11][1]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[13][1]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [2] & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|mem[9][1]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [1] & 
// ((\A_SPW_TOP|rx_data|mem[11][1]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[9][1]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[11][1]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[15][1]~q ),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datae(!\A_SPW_TOP|rx_data|mem[13][1]~q ),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux16~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux16~7 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux16~7 .lut_mask = 64'h55335533000FFF0F;
defparam \A_SPW_TOP|rx_data|Mux16~7 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X36_Y4_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux16~5 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux16~5_combout  = ( \A_SPW_TOP|rx_data|mem[5][1]~q  & ( \A_SPW_TOP|rx_data|rd_ptr [2] & ( (!\A_SPW_TOP|rx_data|rd_ptr [1]) # (\A_SPW_TOP|rx_data|mem[7][1]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[5][1]~q  & ( \A_SPW_TOP|rx_data|rd_ptr [2] 
// & ( (\A_SPW_TOP|rx_data|rd_ptr [1] & \A_SPW_TOP|rx_data|mem[7][1]~q ) ) ) ) # ( \A_SPW_TOP|rx_data|mem[5][1]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [2] & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & ((\A_SPW_TOP|rx_data|mem[1][1]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [1] 
// & (\A_SPW_TOP|rx_data|mem[3][1]~q )) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[5][1]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [2] & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & ((\A_SPW_TOP|rx_data|mem[1][1]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [1] & 
// (\A_SPW_TOP|rx_data|mem[3][1]~q )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[3][1]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[1][1]~q ),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datad(!\A_SPW_TOP|rx_data|mem[7][1]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[5][1]~q ),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux16~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux16~5 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux16~5 .lut_mask = 64'h35353535000FF0FF;
defparam \A_SPW_TOP|rx_data|Mux16~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y4_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux16~6 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux16~6_combout  = ( \A_SPW_TOP|rx_data|mem[23][1]~q  & ( \A_SPW_TOP|rx_data|mem[17][1]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & (((!\A_SPW_TOP|rx_data|rd_ptr [2]) # (\A_SPW_TOP|rx_data|mem[21][1]~q )))) # (\A_SPW_TOP|rx_data|rd_ptr [1] 
// & (((\A_SPW_TOP|rx_data|rd_ptr [2])) # (\A_SPW_TOP|rx_data|mem[19][1]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[23][1]~q  & ( \A_SPW_TOP|rx_data|mem[17][1]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & (((!\A_SPW_TOP|rx_data|rd_ptr [2]) # 
// (\A_SPW_TOP|rx_data|mem[21][1]~q )))) # (\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|mem[19][1]~q  & (!\A_SPW_TOP|rx_data|rd_ptr [2]))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[23][1]~q  & ( !\A_SPW_TOP|rx_data|mem[17][1]~q  & ( 
// (!\A_SPW_TOP|rx_data|rd_ptr [1] & (((\A_SPW_TOP|rx_data|rd_ptr [2] & \A_SPW_TOP|rx_data|mem[21][1]~q )))) # (\A_SPW_TOP|rx_data|rd_ptr [1] & (((\A_SPW_TOP|rx_data|rd_ptr [2])) # (\A_SPW_TOP|rx_data|mem[19][1]~q ))) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|mem[23][1]~q  & ( !\A_SPW_TOP|rx_data|mem[17][1]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & (((\A_SPW_TOP|rx_data|rd_ptr [2] & \A_SPW_TOP|rx_data|mem[21][1]~q )))) # (\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|mem[19][1]~q  & 
// (!\A_SPW_TOP|rx_data|rd_ptr [2]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[19][1]~q ),
        .datab(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datad(!\A_SPW_TOP|rx_data|mem[21][1]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[23][1]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[17][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux16~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux16~6 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux16~6 .lut_mask = 64'h101C131FD0DCD3DF;
defparam \A_SPW_TOP|rx_data|Mux16~6 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y4_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux16~8 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux16~8_combout  = ( \A_SPW_TOP|rx_data|rd_ptr [2] & ( \A_SPW_TOP|rx_data|mem[31][1]~q  & ( (\A_SPW_TOP|rx_data|rd_ptr [1]) # (\A_SPW_TOP|rx_data|mem[29][1]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [2] & ( 
// \A_SPW_TOP|rx_data|mem[31][1]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & ((\A_SPW_TOP|rx_data|mem[25][1]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|mem[27][1]~q )) ) ) ) # ( \A_SPW_TOP|rx_data|rd_ptr [2] & ( 
// !\A_SPW_TOP|rx_data|mem[31][1]~q  & ( (\A_SPW_TOP|rx_data|mem[29][1]~q  & !\A_SPW_TOP|rx_data|rd_ptr [1]) ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [2] & ( !\A_SPW_TOP|rx_data|mem[31][1]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & 
// ((\A_SPW_TOP|rx_data|mem[25][1]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|mem[27][1]~q )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[27][1]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[29][1]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[25][1]~q ),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datae(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .dataf(!\A_SPW_TOP|rx_data|mem[31][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux16~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux16~8 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux16~8 .lut_mask = 64'h0F5533000F5533FF;
defparam \A_SPW_TOP|rx_data|Mux16~8 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y4_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux16~9 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux16~9_combout  = ( \A_SPW_TOP|rx_data|Mux16~8_combout  & ( \A_SPW_TOP|rx_data|rd_ptr [3] & ( (\A_SPW_TOP|rx_data|rd_ptr [4]) # (\A_SPW_TOP|rx_data|Mux16~7_combout ) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux16~8_combout  & ( 
// \A_SPW_TOP|rx_data|rd_ptr [3] & ( (\A_SPW_TOP|rx_data|Mux16~7_combout  & !\A_SPW_TOP|rx_data|rd_ptr [4]) ) ) ) # ( \A_SPW_TOP|rx_data|Mux16~8_combout  & ( !\A_SPW_TOP|rx_data|rd_ptr [3] & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & 
// (\A_SPW_TOP|rx_data|Mux16~5_combout )) # (\A_SPW_TOP|rx_data|rd_ptr [4] & ((\A_SPW_TOP|rx_data|Mux16~6_combout ))) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux16~8_combout  & ( !\A_SPW_TOP|rx_data|rd_ptr [3] & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & 
// (\A_SPW_TOP|rx_data|Mux16~5_combout )) # (\A_SPW_TOP|rx_data|rd_ptr [4] & ((\A_SPW_TOP|rx_data|Mux16~6_combout ))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux16~7_combout ),
        .datab(!\A_SPW_TOP|rx_data|Mux16~5_combout ),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [4]),
        .datad(!\A_SPW_TOP|rx_data|Mux16~6_combout ),
        .datae(!\A_SPW_TOP|rx_data|Mux16~8_combout ),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux16~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux16~9 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux16~9 .lut_mask = 64'h303F303F50505F5F;
defparam \A_SPW_TOP|rx_data|Mux16~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y4_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux16~13 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux16~13_combout  = ( \A_SPW_TOP|rx_data|mem[60][1]~q  & ( \A_SPW_TOP|rx_data|mem[56][1]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [1]) # ((!\A_SPW_TOP|rx_data|rd_ptr [2] & ((\A_SPW_TOP|rx_data|mem[58][1]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [2] 
// & (\A_SPW_TOP|rx_data|mem[62][1]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[60][1]~q  & ( \A_SPW_TOP|rx_data|mem[56][1]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [2] & (((!\A_SPW_TOP|rx_data|rd_ptr [1]) # (\A_SPW_TOP|rx_data|mem[58][1]~q )))) # 
// (\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|mem[62][1]~q  & (\A_SPW_TOP|rx_data|rd_ptr [1]))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[60][1]~q  & ( !\A_SPW_TOP|rx_data|mem[56][1]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [2] & (((\A_SPW_TOP|rx_data|rd_ptr [1] 
// & \A_SPW_TOP|rx_data|mem[58][1]~q )))) # (\A_SPW_TOP|rx_data|rd_ptr [2] & (((!\A_SPW_TOP|rx_data|rd_ptr [1])) # (\A_SPW_TOP|rx_data|mem[62][1]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[60][1]~q  & ( !\A_SPW_TOP|rx_data|mem[56][1]~q  & ( 
// (\A_SPW_TOP|rx_data|rd_ptr [1] & ((!\A_SPW_TOP|rx_data|rd_ptr [2] & ((\A_SPW_TOP|rx_data|mem[58][1]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|mem[62][1]~q )))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[62][1]~q ),
        .datab(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datad(!\A_SPW_TOP|rx_data|mem[58][1]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[60][1]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[56][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux16~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux16~13 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux16~13 .lut_mask = 64'h010D313DC1CDF1FD;
defparam \A_SPW_TOP|rx_data|Mux16~13 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y4_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux16~10 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux16~10_combout  = ( \A_SPW_TOP|rx_data|mem[36][1]~q  & ( \A_SPW_TOP|rx_data|mem[32][1]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [1]) # ((!\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|mem[34][1]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [2] & 
// ((\A_SPW_TOP|rx_data|mem[38][1]~q )))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[36][1]~q  & ( \A_SPW_TOP|rx_data|mem[32][1]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [2] & (((!\A_SPW_TOP|rx_data|rd_ptr [1])) # (\A_SPW_TOP|rx_data|mem[34][1]~q ))) # 
// (\A_SPW_TOP|rx_data|rd_ptr [2] & (((\A_SPW_TOP|rx_data|mem[38][1]~q  & \A_SPW_TOP|rx_data|rd_ptr [1])))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[36][1]~q  & ( !\A_SPW_TOP|rx_data|mem[32][1]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [2] & 
// (\A_SPW_TOP|rx_data|mem[34][1]~q  & ((\A_SPW_TOP|rx_data|rd_ptr [1])))) # (\A_SPW_TOP|rx_data|rd_ptr [2] & (((!\A_SPW_TOP|rx_data|rd_ptr [1]) # (\A_SPW_TOP|rx_data|mem[38][1]~q )))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[36][1]~q  & ( 
// !\A_SPW_TOP|rx_data|mem[32][1]~q  & ( (\A_SPW_TOP|rx_data|rd_ptr [1] & ((!\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|mem[34][1]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [2] & ((\A_SPW_TOP|rx_data|mem[38][1]~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[34][1]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[38][1]~q ),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datae(!\A_SPW_TOP|rx_data|mem[36][1]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[32][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux16~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux16~10 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux16~10 .lut_mask = 64'h00530F53F053FF53;
defparam \A_SPW_TOP|rx_data|Mux16~10 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y4_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux16~11 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux16~11_combout  = ( \A_SPW_TOP|rx_data|mem[52][1]~q  & ( \A_SPW_TOP|rx_data|mem[54][1]~q  & ( ((!\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|mem[48][1]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [1] & ((\A_SPW_TOP|rx_data|mem[50][1]~q 
// )))) # (\A_SPW_TOP|rx_data|rd_ptr [2]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[52][1]~q  & ( \A_SPW_TOP|rx_data|mem[54][1]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [2] & ((!\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|mem[48][1]~q )) # 
// (\A_SPW_TOP|rx_data|rd_ptr [1] & ((\A_SPW_TOP|rx_data|mem[50][1]~q ))))) # (\A_SPW_TOP|rx_data|rd_ptr [2] & (((\A_SPW_TOP|rx_data|rd_ptr [1])))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[52][1]~q  & ( !\A_SPW_TOP|rx_data|mem[54][1]~q  & ( 
// (!\A_SPW_TOP|rx_data|rd_ptr [2] & ((!\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|mem[48][1]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [1] & ((\A_SPW_TOP|rx_data|mem[50][1]~q ))))) # (\A_SPW_TOP|rx_data|rd_ptr [2] & (((!\A_SPW_TOP|rx_data|rd_ptr [1])))) ) 
// ) ) # ( !\A_SPW_TOP|rx_data|mem[52][1]~q  & ( !\A_SPW_TOP|rx_data|mem[54][1]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [2] & ((!\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|mem[48][1]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [1] & 
// ((\A_SPW_TOP|rx_data|mem[50][1]~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datab(!\A_SPW_TOP|rx_data|mem[48][1]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[50][1]~q ),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datae(!\A_SPW_TOP|rx_data|mem[52][1]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[54][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux16~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux16~11 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux16~11 .lut_mask = 64'h220A770A225F775F;
defparam \A_SPW_TOP|rx_data|Mux16~11 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y4_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux16~12 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux16~12_combout  = ( \A_SPW_TOP|rx_data|mem[46][1]~q  & ( \A_SPW_TOP|rx_data|rd_ptr [2] & ( (\A_SPW_TOP|rx_data|mem[44][1]~q ) # (\A_SPW_TOP|rx_data|rd_ptr [1]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[46][1]~q  & ( \A_SPW_TOP|rx_data|rd_ptr 
// [2] & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & \A_SPW_TOP|rx_data|mem[44][1]~q ) ) ) ) # ( \A_SPW_TOP|rx_data|mem[46][1]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [2] & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & ((\A_SPW_TOP|rx_data|mem[40][1]~q ))) # 
// (\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|mem[42][1]~q )) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[46][1]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [2] & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & ((\A_SPW_TOP|rx_data|mem[40][1]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr 
// [1] & (\A_SPW_TOP|rx_data|mem[42][1]~q )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[42][1]~q ),
        .datab(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datac(!\A_SPW_TOP|rx_data|mem[44][1]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[40][1]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[46][1]~q ),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux16~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux16~12 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux16~12 .lut_mask = 64'h11DD11DD0C0C3F3F;
defparam \A_SPW_TOP|rx_data|Mux16~12 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y4_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux16~14 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux16~14_combout  = ( \A_SPW_TOP|rx_data|Mux16~11_combout  & ( \A_SPW_TOP|rx_data|Mux16~12_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & (((\A_SPW_TOP|rx_data|rd_ptr [3]) # (\A_SPW_TOP|rx_data|Mux16~10_combout )))) # 
// (\A_SPW_TOP|rx_data|rd_ptr [4] & (((!\A_SPW_TOP|rx_data|rd_ptr [3])) # (\A_SPW_TOP|rx_data|Mux16~13_combout ))) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux16~11_combout  & ( \A_SPW_TOP|rx_data|Mux16~12_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & 
// (((\A_SPW_TOP|rx_data|rd_ptr [3]) # (\A_SPW_TOP|rx_data|Mux16~10_combout )))) # (\A_SPW_TOP|rx_data|rd_ptr [4] & (\A_SPW_TOP|rx_data|Mux16~13_combout  & ((\A_SPW_TOP|rx_data|rd_ptr [3])))) ) ) ) # ( \A_SPW_TOP|rx_data|Mux16~11_combout  & ( 
// !\A_SPW_TOP|rx_data|Mux16~12_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & (((\A_SPW_TOP|rx_data|Mux16~10_combout  & !\A_SPW_TOP|rx_data|rd_ptr [3])))) # (\A_SPW_TOP|rx_data|rd_ptr [4] & (((!\A_SPW_TOP|rx_data|rd_ptr [3])) # 
// (\A_SPW_TOP|rx_data|Mux16~13_combout ))) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux16~11_combout  & ( !\A_SPW_TOP|rx_data|Mux16~12_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & (((\A_SPW_TOP|rx_data|Mux16~10_combout  & !\A_SPW_TOP|rx_data|rd_ptr [3])))) # 
// (\A_SPW_TOP|rx_data|rd_ptr [4] & (\A_SPW_TOP|rx_data|Mux16~13_combout  & ((\A_SPW_TOP|rx_data|rd_ptr [3])))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux16~13_combout ),
        .datab(!\A_SPW_TOP|rx_data|Mux16~10_combout ),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [4]),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [3]),
        .datae(!\A_SPW_TOP|rx_data|Mux16~11_combout ),
        .dataf(!\A_SPW_TOP|rx_data|Mux16~12_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux16~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux16~14 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux16~14 .lut_mask = 64'h30053F0530F53FF5;
defparam \A_SPW_TOP|rx_data|Mux16~14 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y4_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux16~16 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux16~16_combout  = ( \A_SPW_TOP|rx_data|mem[57][1]~q  & ( \A_SPW_TOP|rx_data|mem[61][1]~q  & ( ((!\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|mem[49][1]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [2] & ((\A_SPW_TOP|rx_data|mem[53][1]~q 
// )))) # (\A_SPW_TOP|rx_data|rd_ptr [3]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[57][1]~q  & ( \A_SPW_TOP|rx_data|mem[61][1]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [2] & (!\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|mem[49][1]~q ))) # 
// (\A_SPW_TOP|rx_data|rd_ptr [2] & (((\A_SPW_TOP|rx_data|mem[53][1]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [3]))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[57][1]~q  & ( !\A_SPW_TOP|rx_data|mem[61][1]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [2] & 
// (((\A_SPW_TOP|rx_data|mem[49][1]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [3]))) # (\A_SPW_TOP|rx_data|rd_ptr [2] & (!\A_SPW_TOP|rx_data|rd_ptr [3] & ((\A_SPW_TOP|rx_data|mem[53][1]~q )))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[57][1]~q  & ( 
// !\A_SPW_TOP|rx_data|mem[61][1]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [3] & ((!\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|mem[49][1]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [2] & ((\A_SPW_TOP|rx_data|mem[53][1]~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datab(!\A_SPW_TOP|rx_data|rd_ptr [3]),
        .datac(!\A_SPW_TOP|rx_data|mem[49][1]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[53][1]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[57][1]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[61][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux16~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux16~16 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux16~16 .lut_mask = 64'h084C2A6E195D3B7F;
defparam \A_SPW_TOP|rx_data|Mux16~16 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y4_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux16~18 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux16~18_combout  = ( \A_SPW_TOP|rx_data|mem[59][1]~q  & ( \A_SPW_TOP|rx_data|rd_ptr [2] & ( (!\A_SPW_TOP|rx_data|rd_ptr [3] & ((\A_SPW_TOP|rx_data|mem[55][1]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|mem[63][1]~q )) 
// ) ) ) # ( !\A_SPW_TOP|rx_data|mem[59][1]~q  & ( \A_SPW_TOP|rx_data|rd_ptr [2] & ( (!\A_SPW_TOP|rx_data|rd_ptr [3] & ((\A_SPW_TOP|rx_data|mem[55][1]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|mem[63][1]~q )) ) ) ) # ( 
// \A_SPW_TOP|rx_data|mem[59][1]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [2] & ( (\A_SPW_TOP|rx_data|rd_ptr [3]) # (\A_SPW_TOP|rx_data|mem[51][1]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[59][1]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [2] & ( 
// (\A_SPW_TOP|rx_data|mem[51][1]~q  & !\A_SPW_TOP|rx_data|rd_ptr [3]) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[63][1]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[51][1]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[55][1]~q ),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [3]),
        .datae(!\A_SPW_TOP|rx_data|mem[59][1]~q ),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux16~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux16~18 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux16~18 .lut_mask = 64'h330033FF0F550F55;
defparam \A_SPW_TOP|rx_data|Mux16~18 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y4_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux16~15 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux16~15_combout  = ( \A_SPW_TOP|rx_data|mem[41][1]~q  & ( \A_SPW_TOP|rx_data|mem[33][1]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [2]) # ((!\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|mem[37][1]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [3] & 
// ((\A_SPW_TOP|rx_data|mem[45][1]~q )))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[41][1]~q  & ( \A_SPW_TOP|rx_data|mem[33][1]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [2] & (((!\A_SPW_TOP|rx_data|rd_ptr [3])))) # (\A_SPW_TOP|rx_data|rd_ptr [2] & 
// ((!\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|mem[37][1]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [3] & ((\A_SPW_TOP|rx_data|mem[45][1]~q ))))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[41][1]~q  & ( !\A_SPW_TOP|rx_data|mem[33][1]~q  & ( 
// (!\A_SPW_TOP|rx_data|rd_ptr [2] & (((\A_SPW_TOP|rx_data|rd_ptr [3])))) # (\A_SPW_TOP|rx_data|rd_ptr [2] & ((!\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|mem[37][1]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [3] & ((\A_SPW_TOP|rx_data|mem[45][1]~q ))))) ) ) 
// ) # ( !\A_SPW_TOP|rx_data|mem[41][1]~q  & ( !\A_SPW_TOP|rx_data|mem[33][1]~q  & ( (\A_SPW_TOP|rx_data|rd_ptr [2] & ((!\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|mem[37][1]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [3] & ((\A_SPW_TOP|rx_data|mem[45][1]~q 
// ))))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[37][1]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[45][1]~q ),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [3]),
        .datae(!\A_SPW_TOP|rx_data|mem[41][1]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[33][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux16~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux16~15 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux16~15 .lut_mask = 64'h050305F3F503F5F3;
defparam \A_SPW_TOP|rx_data|Mux16~15 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X37_Y4_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux16~17 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux16~17_combout  = ( \A_SPW_TOP|rx_data|mem[43][1]~q  & ( \A_SPW_TOP|rx_data|mem[39][1]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [2] & (((\A_SPW_TOP|rx_data|rd_ptr [3]) # (\A_SPW_TOP|rx_data|mem[35][1]~q )))) # (\A_SPW_TOP|rx_data|rd_ptr [2] 
// & (((!\A_SPW_TOP|rx_data|rd_ptr [3])) # (\A_SPW_TOP|rx_data|mem[47][1]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[43][1]~q  & ( \A_SPW_TOP|rx_data|mem[39][1]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [2] & (((\A_SPW_TOP|rx_data|mem[35][1]~q  & 
// !\A_SPW_TOP|rx_data|rd_ptr [3])))) # (\A_SPW_TOP|rx_data|rd_ptr [2] & (((!\A_SPW_TOP|rx_data|rd_ptr [3])) # (\A_SPW_TOP|rx_data|mem[47][1]~q ))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[43][1]~q  & ( !\A_SPW_TOP|rx_data|mem[39][1]~q  & ( 
// (!\A_SPW_TOP|rx_data|rd_ptr [2] & (((\A_SPW_TOP|rx_data|rd_ptr [3]) # (\A_SPW_TOP|rx_data|mem[35][1]~q )))) # (\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|mem[47][1]~q  & ((\A_SPW_TOP|rx_data|rd_ptr [3])))) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|mem[43][1]~q  & ( !\A_SPW_TOP|rx_data|mem[39][1]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [2] & (((\A_SPW_TOP|rx_data|mem[35][1]~q  & !\A_SPW_TOP|rx_data|rd_ptr [3])))) # (\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|mem[47][1]~q  & 
// ((\A_SPW_TOP|rx_data|rd_ptr [3])))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[47][1]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[35][1]~q ),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [3]),
        .datae(!\A_SPW_TOP|rx_data|mem[43][1]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[39][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux16~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux16~17 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux16~17 .lut_mask = 64'h300530F53F053FF5;
defparam \A_SPW_TOP|rx_data|Mux16~17 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y4_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux16~19 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux16~19_combout  = ( \A_SPW_TOP|rx_data|Mux16~17_combout  & ( \A_SPW_TOP|rx_data|rd_ptr [1] & ( (!\A_SPW_TOP|rx_data|rd_ptr [4]) # (\A_SPW_TOP|rx_data|Mux16~18_combout ) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux16~17_combout  & ( 
// \A_SPW_TOP|rx_data|rd_ptr [1] & ( (\A_SPW_TOP|rx_data|rd_ptr [4] & \A_SPW_TOP|rx_data|Mux16~18_combout ) ) ) ) # ( \A_SPW_TOP|rx_data|Mux16~17_combout  & ( !\A_SPW_TOP|rx_data|rd_ptr [1] & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & 
// ((\A_SPW_TOP|rx_data|Mux16~15_combout ))) # (\A_SPW_TOP|rx_data|rd_ptr [4] & (\A_SPW_TOP|rx_data|Mux16~16_combout )) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux16~17_combout  & ( !\A_SPW_TOP|rx_data|rd_ptr [1] & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & 
// ((\A_SPW_TOP|rx_data|Mux16~15_combout ))) # (\A_SPW_TOP|rx_data|rd_ptr [4] & (\A_SPW_TOP|rx_data|Mux16~16_combout )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [4]),
        .datab(!\A_SPW_TOP|rx_data|Mux16~16_combout ),
        .datac(!\A_SPW_TOP|rx_data|Mux16~18_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux16~15_combout ),
        .datae(!\A_SPW_TOP|rx_data|Mux16~17_combout ),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux16~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux16~19 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux16~19 .lut_mask = 64'h11BB11BB0505AFAF;
defparam \A_SPW_TOP|rx_data|Mux16~19 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y4_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux16~3 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux16~3_combout  = ( \A_SPW_TOP|rx_data|mem[26][1]~q  & ( \A_SPW_TOP|rx_data|mem[30][1]~q  & ( ((!\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|mem[24][1]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [2] & ((\A_SPW_TOP|rx_data|mem[28][1]~q 
// )))) # (\A_SPW_TOP|rx_data|rd_ptr [1]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[26][1]~q  & ( \A_SPW_TOP|rx_data|mem[30][1]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & ((!\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|mem[24][1]~q )) # 
// (\A_SPW_TOP|rx_data|rd_ptr [2] & ((\A_SPW_TOP|rx_data|mem[28][1]~q ))))) # (\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|rd_ptr [2])) ) ) ) # ( \A_SPW_TOP|rx_data|mem[26][1]~q  & ( !\A_SPW_TOP|rx_data|mem[30][1]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr 
// [1] & ((!\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|mem[24][1]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [2] & ((\A_SPW_TOP|rx_data|mem[28][1]~q ))))) # (\A_SPW_TOP|rx_data|rd_ptr [1] & (!\A_SPW_TOP|rx_data|rd_ptr [2])) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|mem[26][1]~q  & ( !\A_SPW_TOP|rx_data|mem[30][1]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & ((!\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|mem[24][1]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [2] & ((\A_SPW_TOP|rx_data|mem[28][1]~q ))))) 
// ) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datab(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datac(!\A_SPW_TOP|rx_data|mem[24][1]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[28][1]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[26][1]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[30][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux16~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux16~3 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux16~3 .lut_mask = 64'h082A4C6E193B5D7F;
defparam \A_SPW_TOP|rx_data|Mux16~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X38_Y4_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux16~2 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux16~2_combout  = ( \A_SPW_TOP|rx_data|mem[14][1]~q  & ( \A_SPW_TOP|rx_data|rd_ptr [2] & ( (\A_SPW_TOP|rx_data|rd_ptr [1]) # (\A_SPW_TOP|rx_data|mem[12][1]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[14][1]~q  & ( \A_SPW_TOP|rx_data|rd_ptr 
// [2] & ( (\A_SPW_TOP|rx_data|mem[12][1]~q  & !\A_SPW_TOP|rx_data|rd_ptr [1]) ) ) ) # ( \A_SPW_TOP|rx_data|mem[14][1]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [2] & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & ((\A_SPW_TOP|rx_data|mem[8][1]~q ))) # 
// (\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|mem[10][1]~q )) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[14][1]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [2] & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & ((\A_SPW_TOP|rx_data|mem[8][1]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [1] 
// & (\A_SPW_TOP|rx_data|mem[10][1]~q )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[10][1]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[12][1]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[8][1]~q ),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datae(!\A_SPW_TOP|rx_data|mem[14][1]~q ),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux16~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux16~2 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux16~2 .lut_mask = 64'h0F550F55330033FF;
defparam \A_SPW_TOP|rx_data|Mux16~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X36_Y4_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux16~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux16~0_combout  = ( \A_SPW_TOP|rx_data|mem[6][1]~q  & ( \A_SPW_TOP|rx_data|mem[4][1]~q  & ( ((!\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|mem[0][1]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [1] & ((\A_SPW_TOP|rx_data|mem[2][1]~q )))) 
// # (\A_SPW_TOP|rx_data|rd_ptr [2]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[6][1]~q  & ( \A_SPW_TOP|rx_data|mem[4][1]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & (((\A_SPW_TOP|rx_data|rd_ptr [2])) # (\A_SPW_TOP|rx_data|mem[0][1]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr 
// [1] & (((!\A_SPW_TOP|rx_data|rd_ptr [2] & \A_SPW_TOP|rx_data|mem[2][1]~q )))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[6][1]~q  & ( !\A_SPW_TOP|rx_data|mem[4][1]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|mem[0][1]~q  & 
// (!\A_SPW_TOP|rx_data|rd_ptr [2]))) # (\A_SPW_TOP|rx_data|rd_ptr [1] & (((\A_SPW_TOP|rx_data|mem[2][1]~q ) # (\A_SPW_TOP|rx_data|rd_ptr [2])))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[6][1]~q  & ( !\A_SPW_TOP|rx_data|mem[4][1]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr 
// [2] & ((!\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|mem[0][1]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [1] & ((\A_SPW_TOP|rx_data|mem[2][1]~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datab(!\A_SPW_TOP|rx_data|mem[0][1]~q ),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datad(!\A_SPW_TOP|rx_data|mem[2][1]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[6][1]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[4][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux16~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux16~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux16~0 .lut_mask = 64'h207025752A7A2F7F;
defparam \A_SPW_TOP|rx_data|Mux16~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y4_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux16~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux16~1_combout  = ( \A_SPW_TOP|rx_data|mem[22][1]~q  & ( \A_SPW_TOP|rx_data|mem[20][1]~q  & ( ((!\A_SPW_TOP|rx_data|rd_ptr [1] & ((\A_SPW_TOP|rx_data|mem[16][1]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|mem[18][1]~q 
// ))) # (\A_SPW_TOP|rx_data|rd_ptr [2]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[22][1]~q  & ( \A_SPW_TOP|rx_data|mem[20][1]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [2] & ((!\A_SPW_TOP|rx_data|rd_ptr [1] & ((\A_SPW_TOP|rx_data|mem[16][1]~q ))) # 
// (\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|mem[18][1]~q )))) # (\A_SPW_TOP|rx_data|rd_ptr [2] & (((!\A_SPW_TOP|rx_data|rd_ptr [1])))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[22][1]~q  & ( !\A_SPW_TOP|rx_data|mem[20][1]~q  & ( 
// (!\A_SPW_TOP|rx_data|rd_ptr [2] & ((!\A_SPW_TOP|rx_data|rd_ptr [1] & ((\A_SPW_TOP|rx_data|mem[16][1]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|mem[18][1]~q )))) # (\A_SPW_TOP|rx_data|rd_ptr [2] & (((\A_SPW_TOP|rx_data|rd_ptr [1])))) ) ) 
// ) # ( !\A_SPW_TOP|rx_data|mem[22][1]~q  & ( !\A_SPW_TOP|rx_data|mem[20][1]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [2] & ((!\A_SPW_TOP|rx_data|rd_ptr [1] & ((\A_SPW_TOP|rx_data|mem[16][1]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [1] & 
// (\A_SPW_TOP|rx_data|mem[18][1]~q )))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datab(!\A_SPW_TOP|rx_data|mem[18][1]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[16][1]~q ),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datae(!\A_SPW_TOP|rx_data|mem[22][1]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[20][1]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux16~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux16~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux16~1 .lut_mask = 64'h0A220A775F225F77;
defparam \A_SPW_TOP|rx_data|Mux16~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y4_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux16~4 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux16~4_combout  = ( \A_SPW_TOP|rx_data|Mux16~1_combout  & ( \A_SPW_TOP|rx_data|rd_ptr [4] & ( (!\A_SPW_TOP|rx_data|rd_ptr [3]) # (\A_SPW_TOP|rx_data|Mux16~3_combout ) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux16~1_combout  & ( 
// \A_SPW_TOP|rx_data|rd_ptr [4] & ( (\A_SPW_TOP|rx_data|Mux16~3_combout  & \A_SPW_TOP|rx_data|rd_ptr [3]) ) ) ) # ( \A_SPW_TOP|rx_data|Mux16~1_combout  & ( !\A_SPW_TOP|rx_data|rd_ptr [4] & ( (!\A_SPW_TOP|rx_data|rd_ptr [3] & 
// ((\A_SPW_TOP|rx_data|Mux16~0_combout ))) # (\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|Mux16~2_combout )) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux16~1_combout  & ( !\A_SPW_TOP|rx_data|rd_ptr [4] & ( (!\A_SPW_TOP|rx_data|rd_ptr [3] & 
// ((\A_SPW_TOP|rx_data|Mux16~0_combout ))) # (\A_SPW_TOP|rx_data|rd_ptr [3] & (\A_SPW_TOP|rx_data|Mux16~2_combout )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux16~3_combout ),
        .datab(!\A_SPW_TOP|rx_data|Mux16~2_combout ),
        .datac(!\A_SPW_TOP|rx_data|Mux16~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [3]),
        .datae(!\A_SPW_TOP|rx_data|Mux16~1_combout ),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux16~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux16~4 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux16~4 .lut_mask = 64'h0F330F330055FF55;
defparam \A_SPW_TOP|rx_data|Mux16~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X40_Y4_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux16~20 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux16~20_combout  = ( \A_SPW_TOP|rx_data|Mux16~19_combout  & ( \A_SPW_TOP|rx_data|Mux16~4_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & (((!\A_SPW_TOP|rx_data|rd_ptr [5]) # (\A_SPW_TOP|rx_data|Mux16~14_combout )))) # 
// (\A_SPW_TOP|rx_data|rd_ptr [0] & (((\A_SPW_TOP|rx_data|rd_ptr [5])) # (\A_SPW_TOP|rx_data|Mux16~9_combout ))) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux16~19_combout  & ( \A_SPW_TOP|rx_data|Mux16~4_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & 
// (((!\A_SPW_TOP|rx_data|rd_ptr [5]) # (\A_SPW_TOP|rx_data|Mux16~14_combout )))) # (\A_SPW_TOP|rx_data|rd_ptr [0] & (\A_SPW_TOP|rx_data|Mux16~9_combout  & ((!\A_SPW_TOP|rx_data|rd_ptr [5])))) ) ) ) # ( \A_SPW_TOP|rx_data|Mux16~19_combout  & ( 
// !\A_SPW_TOP|rx_data|Mux16~4_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & (((\A_SPW_TOP|rx_data|Mux16~14_combout  & \A_SPW_TOP|rx_data|rd_ptr [5])))) # (\A_SPW_TOP|rx_data|rd_ptr [0] & (((\A_SPW_TOP|rx_data|rd_ptr [5])) # 
// (\A_SPW_TOP|rx_data|Mux16~9_combout ))) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux16~19_combout  & ( !\A_SPW_TOP|rx_data|Mux16~4_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & (((\A_SPW_TOP|rx_data|Mux16~14_combout  & \A_SPW_TOP|rx_data|rd_ptr [5])))) # 
// (\A_SPW_TOP|rx_data|rd_ptr [0] & (\A_SPW_TOP|rx_data|Mux16~9_combout  & ((!\A_SPW_TOP|rx_data|rd_ptr [5])))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux16~9_combout ),
        .datab(!\A_SPW_TOP|rx_data|Mux16~14_combout ),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .datae(!\A_SPW_TOP|rx_data|Mux16~19_combout ),
        .dataf(!\A_SPW_TOP|rx_data|Mux16~4_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux16~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux16~20 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux16~20 .lut_mask = 64'h0530053FF530F53F;
defparam \A_SPW_TOP|rx_data|Mux16~20 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y4_N13
dffeas \A_SPW_TOP|rx_data|data_out[1] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|rx_data|Mux16~20_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|data_out [1]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|data_out[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|data_out[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y16_N33
cyclonev_lcell_comb \u0|data_flag_rx|read_mux_out[1] (
// Equation(s):
// \u0|data_flag_rx|read_mux_out [1] = ( \A_SPW_TOP|rx_data|data_out [1] & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|data_out [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|data_flag_rx|read_mux_out [1]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|data_flag_rx|read_mux_out[1] .extended_lut = "off";
defparam \u0|data_flag_rx|read_mux_out[1] .lut_mask = 64'h0000000088888888;
defparam \u0|data_flag_rx|read_mux_out[1] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y16_N35
dffeas \u0|data_flag_rx|readdata[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|data_flag_rx|read_mux_out [1]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|data_flag_rx|readdata [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|data_flag_rx|readdata[1] .is_wysiwyg = "true";
defparam \u0|data_flag_rx|readdata[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X23_Y16_N11
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|data_flag_rx|readdata [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X27_Y16_N17
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y16_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~1_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][1]~q  ) ) # ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [1] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [1]),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][1]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~1 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y16_N35
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y16_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~32 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~32_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][1]~q  & ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout  & ( 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout  & \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [1]) ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][1]~q  & ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout  & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout  & \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [1]) ) ) ) # ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][1]~q  & ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout  & ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout  ) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [1]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][1]~q ),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~32_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~32 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~32 .lut_mask = 64'h0000AAAA0A0A0A0A;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~32 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y16_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~33 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~33_combout  = ( \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~32_combout  ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~32_combout  & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~30_combout  & 
// (((!\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout  & \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~31_combout )))) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~30_combout  & (((!\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout 
//  & \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~31_combout )) # (\u0|mm_interconnect_0|rsp_demux|src1_valid~combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~30_combout ),
        .datab(!\u0|mm_interconnect_0|rsp_demux|src1_valid~combout ),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ),
        .datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~31_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~32_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~33_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~33 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~33 .lut_mask = 64'h11F111F1FFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~33 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y18_N48
cyclonev_lcell_comb \u0|timecode_tx_data|readdata[1] (
// Equation(s):
// \u0|timecode_tx_data|readdata [1] = ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( (\u0|timecode_tx_data|data_out [1] & 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]) ) )

        .dataa(gnd),
        .datab(!\u0|timecode_tx_data|data_out [1]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|timecode_tx_data|readdata [1]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|timecode_tx_data|readdata[1] .extended_lut = "off";
defparam \u0|timecode_tx_data|readdata[1] .lut_mask = 64'h3030303000000000;
defparam \u0|timecode_tx_data|readdata[1] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y18_N50
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|timecode_tx_data|readdata [1]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X28_Y16_N26
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y16_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~1_combout  = (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1] & (\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [1])) # 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1] & ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][1]~q )))

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [1]),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][1]~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~1 .lut_mask = 64'h4747474747474747;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y16_N23
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y16_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~37 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~37_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [1] & ( ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0] & 
// \u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][1]~q ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [1] & ( 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][1]~q  & ((!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0]) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0]))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][1]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~37_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~37 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~37 .lut_mask = 64'h00F500F50AFF0AFF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~37 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y17_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_payload~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|src_payload~1_combout  = ( \u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_WDATA [1] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_WDATA [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_018|src_payload~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|src_payload~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|src_payload~1 .lut_mask = 64'h000000000000FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_018|src_payload~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y17_N55
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_018|src_payload~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X59_Y13_N56
dffeas \u0|clock_sel|data_out[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|clock_sel|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|clock_sel|data_out [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|clock_sel|data_out[1] .is_wysiwyg = "true";
defparam \u0|clock_sel|data_out[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X59_Y10_N9
cyclonev_lcell_comb \u0|clock_sel|readdata[1]~1 (
// Equation(s):
// \u0|clock_sel|readdata[1]~1_combout  = ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & ( 
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( \u0|clock_sel|data_out [1] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|clock_sel|data_out [1]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|clock_sel|readdata[1]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|clock_sel|readdata[1]~1 .extended_lut = "off";
defparam \u0|clock_sel|readdata[1]~1 .lut_mask = 64'h0F0F000000000000;
defparam \u0|clock_sel|readdata[1]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X59_Y10_N11
dffeas \u0|mm_interconnect_0|clock_sel_s1_translator|av_readdata_pre[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|clock_sel|readdata[1]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_translator|av_readdata_pre [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_translator|av_readdata_pre[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_translator|av_readdata_pre[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X30_Y22_N59
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[1][1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[1][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[1][1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[1][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y22_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem~1 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem~1_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_translator|av_readdata_pre [1] & ( (!\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [1]) # 
// (\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[1][1]~q ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_translator|av_readdata_pre [1] & ( (\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[1][1]~q ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[1][1]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_translator|av_readdata_pre [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem~1 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y22_N7
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[0][1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[0][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[0][1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[0][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y22_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~38 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~38_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg [0] & ( (!\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [0] & 
// (\u0|mm_interconnect_0|clock_sel_s1_translator|av_readdata_pre [1])) # (\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [0] & ((\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[0][1]~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[0][1]~q  ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [0]),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_translator|av_readdata_pre [1]),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[0][1]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~38_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~38 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~38 .lut_mask = 64'h00FF00FF0C3F0C3F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~38 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X31_Y16_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~39 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~39_combout  = ( \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~38_combout  & ( ((\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~37_combout  & \u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout )) # 
// (\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout ) ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~38_combout  & ( (\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~37_combout  & \u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~37_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout ),
        .datad(!\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~38_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~39_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~39 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~39 .lut_mask = 64'h005500550F5F0F5F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~39 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y16_N23
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y16_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~1_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][1]~q  ) ) # ( 
// !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [1] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [1]),
        .datad(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][1]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~1 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y16_N43
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][1]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y16_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~238 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~238_combout  = ( !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout  & ( ((((\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout  & 
// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][1]~q )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~39_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~33_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~242_combout ) 
// ) ) # ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout  & ( ((((\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout  & \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [1])) # 
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~39_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~33_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~242_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~242_combout ),
        .datab(!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [1]),
        .datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~33_combout ),
        .datae(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout ),
        .dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~39_combout ),
        .datag(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][1]~q ),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~238_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~238 .extended_lut = "on";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~238 .lut_mask = 64'h57FF57FFFFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~238 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y25_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|read~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|read~0_combout  = ( \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [0] & 
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][129]~q ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg [0]) # 
// ((\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [0] & \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][129]~q )) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg [0]),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|read~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|read~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|read~0 .lut_mask = 64'hF0F5F0F500550055;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|read~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y25_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|read~1 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|read~1_combout  = ( \u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout  & ( (\u0|hps_0|fpga_interfaces|h2f_BREADY [0] & !\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|read~0_combout ) ) ) # 
// ( !\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout  & ( (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & !\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|read~0_combout ) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_BREADY [0]),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|read~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|read~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|read~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|read~1 .lut_mask = 64'h5050505030303030;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|read~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y25_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used[1]~1_combout  = ( \u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg [0] & ( (!\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|read~1_combout  & 
// ((\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used [1]) # (\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used [0]))) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg [0] & ( 
// (!\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|read~1_combout  & \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used [1]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|read~1_combout ),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used [0]),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used[1]~1 .lut_mask = 64'h00CC00CC0CCC0CCC;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used[1]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y25_N8
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y25_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used[0]~0_combout  = ( \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|read~1_combout ) # 
// (\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used [0]) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used [1] & ( (!\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used [0] & 
// (\u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|read~1_combout )) # (\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used [0] & 
// ((!\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|read~1_combout ) # (\u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg [0]))) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg [0]),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|read~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h5F055F0555FF55FF;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y25_N50
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X19_Y25_N23
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem[1][0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem[1][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem[1][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem[1][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y25_N15
cyclonev_lcell_comb \u0|auto_start|readdata[0]~0 (
// Equation(s):
// \u0|auto_start|readdata[0]~0_combout  = ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & ( 
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & \u0|auto_start|data_out~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datac(gnd),
        .datad(!\u0|auto_start|data_out~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|auto_start|readdata[0]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|auto_start|readdata[0]~0 .extended_lut = "off";
defparam \u0|auto_start|readdata[0]~0 .lut_mask = 64'h00CC00CC00000000;
defparam \u0|auto_start|readdata[0]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y25_N17
dffeas \u0|mm_interconnect_0|auto_start_s1_translator|av_readdata_pre[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|auto_start|readdata[0]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_translator|av_readdata_pre [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_translator|av_readdata_pre[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_translator|av_readdata_pre[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y25_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem~0_combout  = ( \u0|mm_interconnect_0|auto_start_s1_translator|av_readdata_pre [0] & ( (!\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used [1]) # 
// (\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem[1][0]~q ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_translator|av_readdata_pre [0] & ( (\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem[1][0]~q ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem[1][0]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_translator|av_readdata_pre [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem~0 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y25_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|always0~0_combout  = ( \u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ( (!\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used [0]) # 
// ((!\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|read~0_combout  & ((!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ) # (\u0|hps_0|fpga_interfaces|h2f_BREADY [0])))) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ( 
// (!\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used [0]) # ((!\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|read~0_combout  & (\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout  & \u0|hps_0|fpga_interfaces|h2f_BREADY [0]))) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used [0]),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|read~0_combout ),
        .datac(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_BREADY [0]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|always0~0 .lut_mask = 64'hAAAEAAAEEAEEEAEE;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y25_N32
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem[0][0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem[0][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem[0][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem[0][0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y25_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~0_combout  = ( \u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg [0] & ( (!\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used [0] & 
// ((\u0|mm_interconnect_0|auto_start_s1_translator|av_readdata_pre [0]))) # (\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used [0] & (\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem[0][0]~q )) ) ) # ( 
// !\u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem[0][0]~q  ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem[0][0]~q ),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_translator|av_readdata_pre [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~0 .lut_mask = 64'h0F0F0F0F05AF05AF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X31_Y14_N36
cyclonev_lcell_comb \u0|counter_rx_fifo|read_mux_out[0]~0 (
// Equation(s):
// \u0|counter_rx_fifo|read_mux_out[0]~0_combout  = ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & \A_SPW_TOP|rx_data|counter [0]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datac(!\A_SPW_TOP|rx_data|counter [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|counter_rx_fifo|read_mux_out[0]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|counter_rx_fifo|read_mux_out[0]~0 .extended_lut = "off";
defparam \u0|counter_rx_fifo|read_mux_out[0]~0 .lut_mask = 64'h0C0C0C0C00000000;
defparam \u0|counter_rx_fifo|read_mux_out[0]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y14_N38
dffeas \u0|counter_rx_fifo|readdata[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|counter_rx_fifo|read_mux_out[0]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|counter_rx_fifo|readdata [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|counter_rx_fifo|readdata[0] .is_wysiwyg = "true";
defparam \u0|counter_rx_fifo|readdata[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X31_Y15_N23
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|counter_rx_fifo|readdata [0]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X31_Y15_N25
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y15_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~0_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][0]~q  ) ) # ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [0] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [0]),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][0]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~0 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y15_N13
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y15_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~3 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~3_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0] & ( 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][0]~q  & !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ) ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0] & ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][0]~q  & !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ) ) ) ) # ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0] & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [0] & 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ) ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0] & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0] & ( 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][0]~q  & !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [0]),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][0]~q ),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ),
        .datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0]),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~3 .lut_mask = 64'h3300550033003300;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~3 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y25_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_008|src1_valid (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_008|src1_valid~combout  = ( !\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout  & ( !\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_demux_008|src1_valid~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_008|src1_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_008|src1_valid .lut_mask = 64'hF0F0F0F000000000;
defparam \u0|mm_interconnect_0|rsp_demux_008|src1_valid .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y14_N33
cyclonev_lcell_comb \u0|counter_tx_fifo|read_mux_out[0]~0 (
// Equation(s):
// \u0|counter_tx_fifo|read_mux_out[0]~0_combout  = ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( \A_SPW_TOP|tx_data|counter [0] ) ) )

        .dataa(!\A_SPW_TOP|tx_data|counter [0]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|counter_tx_fifo|read_mux_out[0]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|counter_tx_fifo|read_mux_out[0]~0 .extended_lut = "off";
defparam \u0|counter_tx_fifo|read_mux_out[0]~0 .lut_mask = 64'h5555000000000000;
defparam \u0|counter_tx_fifo|read_mux_out[0]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y14_N34
dffeas \u0|counter_tx_fifo|readdata[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|counter_tx_fifo|read_mux_out[0]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|counter_tx_fifo|readdata [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|counter_tx_fifo|readdata[0] .is_wysiwyg = "true";
defparam \u0|counter_tx_fifo|readdata[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X27_Y15_N23
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|counter_tx_fifo|readdata [0]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X27_Y15_N31
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y15_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~0_combout  = (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [1] & ((\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [0]))) # 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [1] & (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][0]~q ))

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][0]~q ),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [1]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [0]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~0 .lut_mask = 64'h11DD11DD11DD11DD;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y15_N17
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y15_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~2 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~2_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][0]~q  & ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout  ) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][0]~q  & ( 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout  & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0]) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [0]))) ) ) ) # ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0] & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][0]~q  & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [0] & 
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout  & \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0])) ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [0]),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0]),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~2 .lut_mask = 64'h04040000C4C4CCCC;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~2 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y15_N24
cyclonev_lcell_comb \u0|fsm_info|read_mux_out[0]~0 (
// Equation(s):
// \u0|fsm_info|read_mux_out[0]~0_combout  = ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( 
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & \A_SPW_TOP|SPW|FSM|state_fsm.error_wait~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datac(!\A_SPW_TOP|SPW|FSM|state_fsm.error_wait~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|fsm_info|read_mux_out[0]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|fsm_info|read_mux_out[0]~0 .extended_lut = "off";
defparam \u0|fsm_info|read_mux_out[0]~0 .lut_mask = 64'h0C0C0C0C00000000;
defparam \u0|fsm_info|read_mux_out[0]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y15_N25
dffeas \u0|fsm_info|readdata[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|fsm_info|read_mux_out[0]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|fsm_info|readdata [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|fsm_info|readdata[0] .is_wysiwyg = "true";
defparam \u0|fsm_info|readdata[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X25_Y15_N56
dffeas \u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|fsm_info|readdata [0]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X25_Y15_N32
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y15_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~0_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][0]~q  & ( (\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [1]) # 
// (\u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre [0]) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][0]~q  & ( (\u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre [0] & 
// !\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [1]) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~0 .lut_mask = 64'h505050505F5F5F5F;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y15_N44
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y15_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~1_combout  = ( !\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout  & ( \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0] & ( 
// (!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0] & (\u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre [0])) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0] & 
// ((\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][0]~q ))) ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout  & ( !\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0] & ( 
// \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][0]~q  ) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][0]~q ),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0]),
        .datae(!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout ),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~1 .lut_mask = 64'h0F0F0000550F0000;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y23_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~4 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~4_combout  = ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~2_combout  & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~1_combout  & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~3_combout  & 
// ((!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~0_combout ) # (!\u0|mm_interconnect_0|rsp_demux_008|src1_valid~combout ))) ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~0_combout ),
        .datac(!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~3_combout ),
        .datad(!\u0|mm_interconnect_0|rsp_demux_008|src1_valid~combout ),
        .datae(!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~2_combout ),
        .dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~4 .lut_mask = 64'hF0C0000000000000;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y30_N44
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y2_N12
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|rx_data_flag~12 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|rx_data_flag~12_combout  = ( !\A_SPW_TOP|SPW|RX|ready_control_p_r~q  & ( ((!\A_SPW_TOP|SPW|RX|data~0_combout  & (\A_SPW_TOP|SPW|RX|dta_timec_p [0])) # (\A_SPW_TOP|SPW|RX|data~0_combout  & (((\A_SPW_TOP|SPW|RX|rx_data_flag [0]))))) ) ) # 
// ( \A_SPW_TOP|SPW|RX|ready_control_p_r~q  & ( (!\A_SPW_TOP|SPW|RX|control_p_r [1] & (((\A_SPW_TOP|SPW|RX|rx_data_flag [0] & ((!\A_SPW_TOP|SPW|RX|control_p_r [2]) # (!\A_SPW_TOP|SPW|RX|control_p_r [0])))))) # (\A_SPW_TOP|SPW|RX|control_p_r [1] & 
// ((((\A_SPW_TOP|SPW|RX|control_p_r [2] & !\A_SPW_TOP|SPW|RX|control_p_r [0])) # (\A_SPW_TOP|SPW|RX|rx_data_flag [0])))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|control_p_r [1]),
        .datab(!\A_SPW_TOP|SPW|RX|dta_timec_p [0]),
        .datac(!\A_SPW_TOP|SPW|RX|control_p_r [2]),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .datae(!\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),
        .dataf(!\A_SPW_TOP|SPW|RX|control_p_r [0]),
        .datag(!\A_SPW_TOP|SPW|RX|data~0_combout ),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|rx_data_flag~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_data_flag~12 .extended_lut = "on";
defparam \A_SPW_TOP|SPW|RX|rx_data_flag~12 .lut_mask = 64'h303F05FF303F00F5;
defparam \A_SPW_TOP|SPW|RX|rx_data_flag~12 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y2_N14
dffeas \A_SPW_TOP|SPW|RX|rx_data_flag[0] (
        .clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(\A_SPW_TOP|SPW|RX|rx_data_flag~12_combout ),
        .asdata(vcc),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(!\A_SPW_TOP|SPW|RX|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_data_flag[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|rx_data_flag[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y6_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector486~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector486~0_combout  = ( \A_SPW_TOP|rx_data|mem[51][0]~q  & ( (!\A_SPW_TOP|rx_data|Selector478~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [0]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux8~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[51][0]~q  & ( (\A_SPW_TOP|rx_data|Selector478~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [0]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux8~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Selector478~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[51][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector486~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector486~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector486~0 .lut_mask = 64'h010D010DF1FDF1FD;
defparam \A_SPW_TOP|rx_data|Selector486~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y6_N32
dffeas \A_SPW_TOP|rx_data|mem[51][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector486~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[51][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[51][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[51][0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y7_N15
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector522~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector522~0_combout  = ( \A_SPW_TOP|rx_data|mem[55][0]~q  & ( (!\A_SPW_TOP|rx_data|Selector514~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [0])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux8~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[55][0]~q  & ( (\A_SPW_TOP|rx_data|Selector514~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [0])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux8~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Selector514~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[55][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector522~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector522~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector522~0 .lut_mask = 64'h04070407F4F7F4F7;
defparam \A_SPW_TOP|rx_data|Selector522~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y7_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|mem[55][0]~feeder (
// Equation(s):
// \A_SPW_TOP|rx_data|mem[55][0]~feeder_combout  = ( \A_SPW_TOP|rx_data|Selector522~0_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector522~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|mem[55][0]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[55][0]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|mem[55][0]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|rx_data|mem[55][0]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y7_N20
dffeas \A_SPW_TOP|rx_data|mem[55][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|rx_data|mem[55][0]~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[55][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[55][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[55][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y6_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector342~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector342~0_combout  = ( \A_SPW_TOP|SPW|RX|rx_data_flag [0] & ( (!\A_SPW_TOP|rx_data|Selector334~0_combout  & (((\A_SPW_TOP|rx_data|mem[35][0]~q )))) # (\A_SPW_TOP|rx_data|Selector334~0_combout  & 
// ((!\A_SPW_TOP|rx_data|state_data_write.00~q ) # ((\A_SPW_TOP|rx_data|Mux8~20_combout )))) ) ) # ( !\A_SPW_TOP|SPW|RX|rx_data_flag [0] & ( (!\A_SPW_TOP|rx_data|Selector334~0_combout  & (((\A_SPW_TOP|rx_data|mem[35][0]~q )))) # 
// (\A_SPW_TOP|rx_data|Selector334~0_combout  & (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux8~20_combout ))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|mem[35][0]~q ),
        .datad(!\A_SPW_TOP|rx_data|Selector334~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector342~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector342~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector342~0 .lut_mask = 64'h0F110F110FBB0FBB;
defparam \A_SPW_TOP|rx_data|Selector342~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y6_N26
dffeas \A_SPW_TOP|rx_data|mem[35][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector342~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[35][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[35][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[35][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y6_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux8~13 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux8~13_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [2] & ( \A_SPW_TOP|rx_data|mem[35][0]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|mem[39][0]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[55][0]~q )) ) 
// ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [2] & ( \A_SPW_TOP|rx_data|mem[35][0]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [4]) # (\A_SPW_TOP|rx_data|mem[51][0]~q ) ) ) ) # ( \A_SPW_TOP|rx_data|wr_ptr [2] & ( !\A_SPW_TOP|rx_data|mem[35][0]~q  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|mem[39][0]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[55][0]~q )) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [2] & ( !\A_SPW_TOP|rx_data|mem[35][0]~q  & ( 
// (\A_SPW_TOP|rx_data|mem[51][0]~q  & \A_SPW_TOP|rx_data|wr_ptr [4]) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[51][0]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[55][0]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[39][0]~q ),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .dataf(!\A_SPW_TOP|rx_data|mem[35][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux8~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux8~13 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux8~13 .lut_mask = 64'h00550F33FF550F33;
defparam \A_SPW_TOP|rx_data|Mux8~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y6_N21
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector477~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector477~0_combout  = ( \A_SPW_TOP|rx_data|Selector469~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [0])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux8~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector469~0_combout  & ( \A_SPW_TOP|rx_data|mem[50][0]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .datac(!\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[50][0]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector469~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector477~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector477~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector477~0 .lut_mask = 64'h00FF00FF27272727;
defparam \A_SPW_TOP|rx_data|Selector477~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y6_N29
dffeas \A_SPW_TOP|rx_data|mem[50][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector477~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[50][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[50][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[50][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y6_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector369~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector369~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( \A_SPW_TOP|rx_data|mem[38][0]~q  & ( (!\A_SPW_TOP|rx_data|Selector361~0_combout ) # (\A_SPW_TOP|rx_data|Mux8~20_combout ) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( \A_SPW_TOP|rx_data|mem[38][0]~q  & ( (!\A_SPW_TOP|rx_data|Selector361~0_combout ) # (\A_SPW_TOP|SPW|RX|rx_data_flag [0]) ) ) ) # ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( 
// !\A_SPW_TOP|rx_data|mem[38][0]~q  & ( (\A_SPW_TOP|rx_data|Mux8~20_combout  & \A_SPW_TOP|rx_data|Selector361~0_combout ) ) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( !\A_SPW_TOP|rx_data|mem[38][0]~q  & ( (\A_SPW_TOP|SPW|RX|rx_data_flag [0] & 
// \A_SPW_TOP|rx_data|Selector361~0_combout ) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .datac(!\A_SPW_TOP|rx_data|Selector361~0_combout ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[38][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector369~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector369~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector369~0 .lut_mask = 64'h03030505F3F3F5F5;
defparam \A_SPW_TOP|rx_data|Selector369~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y6_N35
dffeas \A_SPW_TOP|rx_data|mem[38][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector369~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[38][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[38][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[38][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y6_N51
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector513~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector513~0_combout  = ( \A_SPW_TOP|SPW|RX|rx_data_flag [0] & ( (!\A_SPW_TOP|rx_data|Selector505~0_combout  & (((\A_SPW_TOP|rx_data|mem[54][0]~q )))) # (\A_SPW_TOP|rx_data|Selector505~0_combout  & 
// ((!\A_SPW_TOP|rx_data|state_data_write.00~q ) # ((\A_SPW_TOP|rx_data|Mux8~20_combout )))) ) ) # ( !\A_SPW_TOP|SPW|RX|rx_data_flag [0] & ( (!\A_SPW_TOP|rx_data|Selector505~0_combout  & (((\A_SPW_TOP|rx_data|mem[54][0]~q )))) # 
// (\A_SPW_TOP|rx_data|Selector505~0_combout  & (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux8~20_combout ))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|mem[54][0]~q ),
        .datad(!\A_SPW_TOP|rx_data|Selector505~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector513~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector513~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector513~0 .lut_mask = 64'h0F110F110FBB0FBB;
defparam \A_SPW_TOP|rx_data|Selector513~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y6_N14
dffeas \A_SPW_TOP|rx_data|mem[54][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector513~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[54][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[54][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[54][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y6_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector333~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector333~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( \A_SPW_TOP|rx_data|Selector325~0_combout  & ( \A_SPW_TOP|rx_data|Mux8~20_combout  ) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( 
// \A_SPW_TOP|rx_data|Selector325~0_combout  & ( \A_SPW_TOP|SPW|RX|rx_data_flag [0] ) ) ) # ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( !\A_SPW_TOP|rx_data|Selector325~0_combout  & ( \A_SPW_TOP|rx_data|mem[34][0]~q  ) ) ) # ( 
// !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( !\A_SPW_TOP|rx_data|Selector325~0_combout  & ( \A_SPW_TOP|rx_data|mem[34][0]~q  ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .datac(!\A_SPW_TOP|rx_data|mem[34][0]~q ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .dataf(!\A_SPW_TOP|rx_data|Selector325~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector333~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector333~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector333~0 .lut_mask = 64'h0F0F0F0F33335555;
defparam \A_SPW_TOP|rx_data|Selector333~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y6_N41
dffeas \A_SPW_TOP|rx_data|mem[34][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector333~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[34][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[34][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[34][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y6_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux8~12 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux8~12_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [2] & ( \A_SPW_TOP|rx_data|mem[34][0]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[38][0]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|mem[54][0]~q ))) ) 
// ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [2] & ( \A_SPW_TOP|rx_data|mem[34][0]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [4]) # (\A_SPW_TOP|rx_data|mem[50][0]~q ) ) ) ) # ( \A_SPW_TOP|rx_data|wr_ptr [2] & ( !\A_SPW_TOP|rx_data|mem[34][0]~q  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[38][0]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|mem[54][0]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [2] & ( !\A_SPW_TOP|rx_data|mem[34][0]~q  & ( 
// (\A_SPW_TOP|rx_data|mem[50][0]~q  & \A_SPW_TOP|rx_data|wr_ptr [4]) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[50][0]~q ),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datac(!\A_SPW_TOP|rx_data|mem[38][0]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[54][0]~q ),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .dataf(!\A_SPW_TOP|rx_data|mem[34][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux8~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux8~12 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux8~12 .lut_mask = 64'h11110C3FDDDD0C3F;
defparam \A_SPW_TOP|rx_data|Mux8~12 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y6_N57
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector459~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector459~0_combout  = ( \A_SPW_TOP|rx_data|mem[48][0]~q  & ( (!\A_SPW_TOP|rx_data|Selector451~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [0]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux8~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[48][0]~q  & ( (\A_SPW_TOP|rx_data|Selector451~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [0]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux8~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|Selector451~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[48][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector459~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector459~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector459~0 .lut_mask = 64'h00350035FF35FF35;
defparam \A_SPW_TOP|rx_data|Selector459~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y6_N53
dffeas \A_SPW_TOP|rx_data|mem[48][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector459~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[48][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[48][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[48][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y6_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector495~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector495~0_combout  = ( \A_SPW_TOP|rx_data|Selector487~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [0]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux8~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector487~0_combout  & ( \A_SPW_TOP|rx_data|mem[52][0]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[52][0]~q ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector487~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector495~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector495~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector495~0 .lut_mask = 64'h0F0F0F0F11DD11DD;
defparam \A_SPW_TOP|rx_data|Selector495~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y6_N11
dffeas \A_SPW_TOP|rx_data|mem[52][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector495~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[52][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[52][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[52][0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y6_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector351~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector351~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector343~0_combout  & ((\A_SPW_TOP|rx_data|mem[36][0]~q ))) # (\A_SPW_TOP|rx_data|Selector343~0_combout  & 
// (\A_SPW_TOP|rx_data|Mux8~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector343~0_combout  & ((\A_SPW_TOP|rx_data|mem[36][0]~q ))) # (\A_SPW_TOP|rx_data|Selector343~0_combout  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [0])) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .datac(!\A_SPW_TOP|rx_data|Selector343~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[36][0]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector351~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector351~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector351~0 .lut_mask = 64'h03F303F305F505F5;
defparam \A_SPW_TOP|rx_data|Selector351~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y6_N29
dffeas \A_SPW_TOP|rx_data|mem[36][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector351~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[36][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[36][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[36][0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y6_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector315~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector315~0_combout  = ( \A_SPW_TOP|rx_data|mem[32][0]~q  & ( (!\A_SPW_TOP|rx_data|Selector307~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [0]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux8~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[32][0]~q  & ( (\A_SPW_TOP|rx_data|Selector307~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [0]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux8~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Selector307~0_combout ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[32][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector315~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector315~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector315~0 .lut_mask = 64'h01450145ABEFABEF;
defparam \A_SPW_TOP|rx_data|Selector315~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y6_N35
dffeas \A_SPW_TOP|rx_data|mem[32][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector315~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[32][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[32][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[32][0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y6_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux8~10 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux8~10_combout  = ( \A_SPW_TOP|rx_data|mem[36][0]~q  & ( \A_SPW_TOP|rx_data|mem[32][0]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [4]) # ((!\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|mem[48][0]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [2] & 
// ((\A_SPW_TOP|rx_data|mem[52][0]~q )))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[36][0]~q  & ( \A_SPW_TOP|rx_data|mem[32][0]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & (((!\A_SPW_TOP|rx_data|wr_ptr [4])) # (\A_SPW_TOP|rx_data|mem[48][0]~q ))) # 
// (\A_SPW_TOP|rx_data|wr_ptr [2] & (((\A_SPW_TOP|rx_data|mem[52][0]~q  & \A_SPW_TOP|rx_data|wr_ptr [4])))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[36][0]~q  & ( !\A_SPW_TOP|rx_data|mem[32][0]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & 
// (\A_SPW_TOP|rx_data|mem[48][0]~q  & ((\A_SPW_TOP|rx_data|wr_ptr [4])))) # (\A_SPW_TOP|rx_data|wr_ptr [2] & (((!\A_SPW_TOP|rx_data|wr_ptr [4]) # (\A_SPW_TOP|rx_data|mem[52][0]~q )))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[36][0]~q  & ( 
// !\A_SPW_TOP|rx_data|mem[32][0]~q  & ( (\A_SPW_TOP|rx_data|wr_ptr [4] & ((!\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|mem[48][0]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [2] & ((\A_SPW_TOP|rx_data|mem[52][0]~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datab(!\A_SPW_TOP|rx_data|mem[48][0]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[52][0]~q ),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datae(!\A_SPW_TOP|rx_data|mem[36][0]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[32][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux8~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux8~10 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux8~10 .lut_mask = 64'h00275527AA27FF27;
defparam \A_SPW_TOP|rx_data|Mux8~10 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y6_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector324~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector324~0_combout  = ( \A_SPW_TOP|rx_data|Selector316~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [0]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux8~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector316~0_combout  & ( \A_SPW_TOP|rx_data|mem[33][0]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[33][0]~q ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector316~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector324~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector324~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector324~0 .lut_mask = 64'h0F0F0F0F11DD11DD;
defparam \A_SPW_TOP|rx_data|Selector324~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y6_N23
dffeas \A_SPW_TOP|rx_data|mem[33][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector324~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[33][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[33][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[33][0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y6_N45
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector504~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector504~0_combout  = ( \A_SPW_TOP|rx_data|mem[53][0]~q  & ( (!\A_SPW_TOP|rx_data|Selector496~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [0]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux8~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[53][0]~q  & ( (\A_SPW_TOP|rx_data|Selector496~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [0]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux8~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .datad(!\A_SPW_TOP|rx_data|Selector496~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[53][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector504~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector504~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector504~0 .lut_mask = 64'h001D001DFF1DFF1D;
defparam \A_SPW_TOP|rx_data|Selector504~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y6_N11
dffeas \A_SPW_TOP|rx_data|mem[53][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector504~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[53][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[53][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[53][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y6_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector468~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector468~0_combout  = ( \A_SPW_TOP|rx_data|mem[49][0]~q  & ( (!\A_SPW_TOP|rx_data|Selector460~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [0]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux8~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[49][0]~q  & ( (\A_SPW_TOP|rx_data|Selector460~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [0]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux8~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|Selector460~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[49][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector468~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector468~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector468~0 .lut_mask = 64'h00350035FF35FF35;
defparam \A_SPW_TOP|rx_data|Selector468~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y6_N8
dffeas \A_SPW_TOP|rx_data|mem[49][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector468~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[49][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[49][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[49][0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y6_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector360~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector360~0_combout  = ( \A_SPW_TOP|rx_data|mem[37][0]~q  & ( (!\A_SPW_TOP|rx_data|Selector352~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [0]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux8~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[37][0]~q  & ( (\A_SPW_TOP|rx_data|Selector352~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [0]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux8~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .datac(!\A_SPW_TOP|rx_data|Selector352~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[37][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector360~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector360~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector360~0 .lut_mask = 64'h03050305F3F5F3F5;
defparam \A_SPW_TOP|rx_data|Selector360~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y6_N35
dffeas \A_SPW_TOP|rx_data|mem[37][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector360~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[37][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[37][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[37][0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y6_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux8~11 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux8~11_combout  = ( \A_SPW_TOP|rx_data|mem[49][0]~q  & ( \A_SPW_TOP|rx_data|mem[37][0]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [4] & (((\A_SPW_TOP|rx_data|wr_ptr [2])) # (\A_SPW_TOP|rx_data|mem[33][0]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [4] 
// & (((!\A_SPW_TOP|rx_data|wr_ptr [2]) # (\A_SPW_TOP|rx_data|mem[53][0]~q )))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[49][0]~q  & ( \A_SPW_TOP|rx_data|mem[37][0]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [4] & (((\A_SPW_TOP|rx_data|wr_ptr [2])) # 
// (\A_SPW_TOP|rx_data|mem[33][0]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [4] & (((\A_SPW_TOP|rx_data|wr_ptr [2] & \A_SPW_TOP|rx_data|mem[53][0]~q )))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[49][0]~q  & ( !\A_SPW_TOP|rx_data|mem[37][0]~q  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[33][0]~q  & (!\A_SPW_TOP|rx_data|wr_ptr [2]))) # (\A_SPW_TOP|rx_data|wr_ptr [4] & (((!\A_SPW_TOP|rx_data|wr_ptr [2]) # (\A_SPW_TOP|rx_data|mem[53][0]~q )))) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|mem[49][0]~q  & ( !\A_SPW_TOP|rx_data|mem[37][0]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[33][0]~q  & (!\A_SPW_TOP|rx_data|wr_ptr [2]))) # (\A_SPW_TOP|rx_data|wr_ptr [4] & (((\A_SPW_TOP|rx_data|wr_ptr [2] & 
// \A_SPW_TOP|rx_data|mem[53][0]~q )))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[33][0]~q ),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datad(!\A_SPW_TOP|rx_data|mem[53][0]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[49][0]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[37][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux8~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux8~11 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux8~11 .lut_mask = 64'h404370734C4F7C7F;
defparam \A_SPW_TOP|rx_data|Mux8~11 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y6_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux8~14 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux8~14_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [0] & ( \A_SPW_TOP|rx_data|Mux8~11_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [1]) # (\A_SPW_TOP|rx_data|Mux8~13_combout ) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [0] & ( 
// \A_SPW_TOP|rx_data|Mux8~11_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & ((\A_SPW_TOP|rx_data|Mux8~10_combout ))) # (\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|Mux8~12_combout )) ) ) ) # ( \A_SPW_TOP|rx_data|wr_ptr [0] & ( 
// !\A_SPW_TOP|rx_data|Mux8~11_combout  & ( (\A_SPW_TOP|rx_data|Mux8~13_combout  & \A_SPW_TOP|rx_data|wr_ptr [1]) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [0] & ( !\A_SPW_TOP|rx_data|Mux8~11_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & 
// ((\A_SPW_TOP|rx_data|Mux8~10_combout ))) # (\A_SPW_TOP|rx_data|wr_ptr [1] & (\A_SPW_TOP|rx_data|Mux8~12_combout )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux8~13_combout ),
        .datab(!\A_SPW_TOP|rx_data|Mux8~12_combout ),
        .datac(!\A_SPW_TOP|rx_data|Mux8~10_combout ),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .dataf(!\A_SPW_TOP|rx_data|Mux8~11_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux8~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux8~14 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux8~14 .lut_mask = 64'h0F3300550F33FF55;
defparam \A_SPW_TOP|rx_data|Mux8~14 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y5_N51
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector423~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector423~0_combout  = ( \A_SPW_TOP|SPW|RX|rx_data_flag [0] & ( (!\A_SPW_TOP|rx_data|Selector415~0_combout  & (((\A_SPW_TOP|rx_data|mem[44][0]~q )))) # (\A_SPW_TOP|rx_data|Selector415~0_combout  & 
// ((!\A_SPW_TOP|rx_data|state_data_write.00~q ) # ((\A_SPW_TOP|rx_data|Mux8~20_combout )))) ) ) # ( !\A_SPW_TOP|SPW|RX|rx_data_flag [0] & ( (!\A_SPW_TOP|rx_data|Selector415~0_combout  & (((\A_SPW_TOP|rx_data|mem[44][0]~q )))) # 
// (\A_SPW_TOP|rx_data|Selector415~0_combout  & (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux8~20_combout ))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|mem[44][0]~q ),
        .datad(!\A_SPW_TOP|rx_data|Selector415~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector423~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector423~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector423~0 .lut_mask = 64'h0F110F110FBB0FBB;
defparam \A_SPW_TOP|rx_data|Selector423~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y5_N29
dffeas \A_SPW_TOP|rx_data|mem[44][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector423~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[44][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[44][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[44][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y5_N33
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector567~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector567~0_combout  = ( \A_SPW_TOP|rx_data|mem[60][0]~q  & ( (!\A_SPW_TOP|rx_data|Selector559~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [0])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux8~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[60][0]~q  & ( (\A_SPW_TOP|rx_data|Selector559~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [0])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux8~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .datac(!\A_SPW_TOP|rx_data|Selector559~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[60][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector567~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector567~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector567~0 .lut_mask = 64'h02070207F2F7F2F7;
defparam \A_SPW_TOP|rx_data|Selector567~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X40_Y5_N14
dffeas \A_SPW_TOP|rx_data|mem[60][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector567~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[60][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[60][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[60][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y5_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector441~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector441~0_combout  = ( \A_SPW_TOP|rx_data|mem[46][0]~q  & ( (!\A_SPW_TOP|rx_data|Selector433~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [0])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux8~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[46][0]~q  & ( (\A_SPW_TOP|rx_data|Selector433~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [0])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux8~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .datac(!\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .datad(!\A_SPW_TOP|rx_data|Selector433~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[46][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector441~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector441~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector441~0 .lut_mask = 64'h00270027FF27FF27;
defparam \A_SPW_TOP|rx_data|Selector441~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y5_N26
dffeas \A_SPW_TOP|rx_data|mem[46][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector441~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[46][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[46][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[46][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y5_N57
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector585~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector585~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector577~0_combout  & ((\A_SPW_TOP|rx_data|mem[62][0]~q ))) # (\A_SPW_TOP|rx_data|Selector577~0_combout  & 
// (\A_SPW_TOP|rx_data|Mux8~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector577~0_combout  & ((\A_SPW_TOP|rx_data|mem[62][0]~q ))) # (\A_SPW_TOP|rx_data|Selector577~0_combout  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [0])) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .datac(!\A_SPW_TOP|rx_data|Selector577~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[62][0]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector585~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector585~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector585~0 .lut_mask = 64'h03F303F305F505F5;
defparam \A_SPW_TOP|rx_data|Selector585~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y5_N47
dffeas \A_SPW_TOP|rx_data|mem[62][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector585~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[62][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[62][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[62][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y5_N15
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux8~17 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux8~17_combout  = ( \A_SPW_TOP|rx_data|mem[62][0]~q  & ( \A_SPW_TOP|rx_data|wr_ptr [1] & ( (\A_SPW_TOP|rx_data|mem[46][0]~q ) # (\A_SPW_TOP|rx_data|wr_ptr [4]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[62][0]~q  & ( \A_SPW_TOP|rx_data|wr_ptr 
// [1] & ( (!\A_SPW_TOP|rx_data|wr_ptr [4] & \A_SPW_TOP|rx_data|mem[46][0]~q ) ) ) ) # ( \A_SPW_TOP|rx_data|mem[62][0]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [1] & ( (!\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[44][0]~q )) # 
// (\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|mem[60][0]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[62][0]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [1] & ( (!\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[44][0]~q )) # (\A_SPW_TOP|rx_data|wr_ptr 
// [4] & ((\A_SPW_TOP|rx_data|mem[60][0]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[44][0]~q ),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datac(!\A_SPW_TOP|rx_data|mem[60][0]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[46][0]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[62][0]~q ),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux8~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux8~17 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux8~17 .lut_mask = 64'h4747474700CC33FF;
defparam \A_SPW_TOP|rx_data|Mux8~17 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y5_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector387~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector387~0_combout  = ( \A_SPW_TOP|rx_data|Mux8~20_combout  & ( (!\A_SPW_TOP|rx_data|Selector379~0_combout  & (((\A_SPW_TOP|rx_data|mem[40][0]~q )))) # (\A_SPW_TOP|rx_data|Selector379~0_combout  & 
// (((\A_SPW_TOP|rx_data|state_data_write.00~q )) # (\A_SPW_TOP|SPW|RX|rx_data_flag [0]))) ) ) # ( !\A_SPW_TOP|rx_data|Mux8~20_combout  & ( (!\A_SPW_TOP|rx_data|Selector379~0_combout  & (((\A_SPW_TOP|rx_data|mem[40][0]~q )))) # 
// (\A_SPW_TOP|rx_data|Selector379~0_combout  & (\A_SPW_TOP|SPW|RX|rx_data_flag [0] & (!\A_SPW_TOP|rx_data|state_data_write.00~q ))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Selector379~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[40][0]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector387~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector387~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector387~0 .lut_mask = 64'h04F404F407F707F7;
defparam \A_SPW_TOP|rx_data|Selector387~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y5_N21
cyclonev_lcell_comb \A_SPW_TOP|rx_data|mem[40][0]~feeder (
// Equation(s):
// \A_SPW_TOP|rx_data|mem[40][0]~feeder_combout  = ( \A_SPW_TOP|rx_data|Selector387~0_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector387~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|mem[40][0]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[40][0]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|mem[40][0]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|rx_data|mem[40][0]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X45_Y5_N23
dffeas \A_SPW_TOP|rx_data|mem[40][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|rx_data|mem[40][0]~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[40][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[40][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[40][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y5_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector549~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector549~0_combout  = ( \A_SPW_TOP|rx_data|mem[58][0]~q  & ( (!\A_SPW_TOP|rx_data|Selector541~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [0])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux8~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[58][0]~q  & ( (\A_SPW_TOP|rx_data|Selector541~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [0])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux8~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .datac(!\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .datad(!\A_SPW_TOP|rx_data|Selector541~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[58][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector549~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector549~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector549~0 .lut_mask = 64'h00270027FF27FF27;
defparam \A_SPW_TOP|rx_data|Selector549~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y5_N8
dffeas \A_SPW_TOP|rx_data|mem[58][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector549~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[58][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[58][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[58][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y5_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector405~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector405~0_combout  = ( \A_SPW_TOP|rx_data|Mux8~20_combout  & ( (!\A_SPW_TOP|rx_data|Selector397~0_combout  & (((\A_SPW_TOP|rx_data|mem[42][0]~q )))) # (\A_SPW_TOP|rx_data|Selector397~0_combout  & 
// (((\A_SPW_TOP|rx_data|state_data_write.00~q )) # (\A_SPW_TOP|SPW|RX|rx_data_flag [0]))) ) ) # ( !\A_SPW_TOP|rx_data|Mux8~20_combout  & ( (!\A_SPW_TOP|rx_data|Selector397~0_combout  & (((\A_SPW_TOP|rx_data|mem[42][0]~q )))) # 
// (\A_SPW_TOP|rx_data|Selector397~0_combout  & (\A_SPW_TOP|SPW|RX|rx_data_flag [0] & (!\A_SPW_TOP|rx_data|state_data_write.00~q ))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Selector397~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[42][0]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector405~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector405~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector405~0 .lut_mask = 64'h04F404F407F707F7;
defparam \A_SPW_TOP|rx_data|Selector405~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y5_N56
dffeas \A_SPW_TOP|rx_data|mem[42][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector405~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[42][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[42][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[42][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y5_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector531~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector531~0_combout  = ( \A_SPW_TOP|rx_data|mem[56][0]~q  & ( (!\A_SPW_TOP|rx_data|Selector523~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [0])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux8~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[56][0]~q  & ( (\A_SPW_TOP|rx_data|Selector523~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [0])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux8~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .datac(!\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .datad(!\A_SPW_TOP|rx_data|Selector523~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[56][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector531~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector531~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector531~0 .lut_mask = 64'h00270027FF27FF27;
defparam \A_SPW_TOP|rx_data|Selector531~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y5_N44
dffeas \A_SPW_TOP|rx_data|mem[56][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector531~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[56][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[56][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[56][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y5_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux8~15 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux8~15_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [1] & ( \A_SPW_TOP|rx_data|mem[56][0]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|mem[42][0]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[58][0]~q )) ) 
// ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [1] & ( \A_SPW_TOP|rx_data|mem[56][0]~q  & ( (\A_SPW_TOP|rx_data|wr_ptr [4]) # (\A_SPW_TOP|rx_data|mem[40][0]~q ) ) ) ) # ( \A_SPW_TOP|rx_data|wr_ptr [1] & ( !\A_SPW_TOP|rx_data|mem[56][0]~q  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|mem[42][0]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[58][0]~q )) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [1] & ( !\A_SPW_TOP|rx_data|mem[56][0]~q  & ( 
// (\A_SPW_TOP|rx_data|mem[40][0]~q  & !\A_SPW_TOP|rx_data|wr_ptr [4]) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[40][0]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[58][0]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[42][0]~q ),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .dataf(!\A_SPW_TOP|rx_data|mem[56][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux8~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux8~15 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux8~15 .lut_mask = 64'h55000F3355FF0F33;
defparam \A_SPW_TOP|rx_data|Mux8~15 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y5_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector396~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector396~0_combout  = ( \A_SPW_TOP|rx_data|Selector388~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [0]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux8~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector388~0_combout  & ( \A_SPW_TOP|rx_data|mem[41][0]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|mem[41][0]~q ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector388~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector396~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector396~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector396~0 .lut_mask = 64'h0F0F0F0F11BB11BB;
defparam \A_SPW_TOP|rx_data|Selector396~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y5_N20
dffeas \A_SPW_TOP|rx_data|mem[41][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector396~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[41][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[41][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[41][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y5_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector414~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector414~0_combout  = ( \A_SPW_TOP|rx_data|Selector406~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [0]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux8~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector406~0_combout  & ( \A_SPW_TOP|rx_data|mem[43][0]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[43][0]~q ),
        .datae(!\A_SPW_TOP|rx_data|Selector406~0_combout ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector414~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector414~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector414~0 .lut_mask = 64'h00FF353500FF3535;
defparam \A_SPW_TOP|rx_data|Selector414~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y5_N11
dffeas \A_SPW_TOP|rx_data|mem[43][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector414~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[43][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[43][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[43][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y5_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector558~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector558~0_combout  = ( \A_SPW_TOP|rx_data|mem[59][0]~q  & ( \A_SPW_TOP|SPW|RX|rx_data_flag [0] & ( (!\A_SPW_TOP|rx_data|Selector550~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|rx_data|Mux8~20_combout )) 
// ) ) ) # ( !\A_SPW_TOP|rx_data|mem[59][0]~q  & ( \A_SPW_TOP|SPW|RX|rx_data_flag [0] & ( (\A_SPW_TOP|rx_data|Selector550~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|rx_data|Mux8~20_combout ))) ) ) ) # ( 
// \A_SPW_TOP|rx_data|mem[59][0]~q  & ( !\A_SPW_TOP|SPW|RX|rx_data_flag [0] & ( (!\A_SPW_TOP|rx_data|Selector550~0_combout ) # ((\A_SPW_TOP|rx_data|Mux8~20_combout  & \A_SPW_TOP|rx_data|state_data_write.00~q )) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[59][0]~q  & ( 
// !\A_SPW_TOP|SPW|RX|rx_data_flag [0] & ( (\A_SPW_TOP|rx_data|Selector550~0_combout  & (\A_SPW_TOP|rx_data|Mux8~20_combout  & \A_SPW_TOP|rx_data|state_data_write.00~q )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Selector550~0_combout ),
        .datab(!\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .datac(gnd),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[59][0]~q ),
        .dataf(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector558~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector558~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector558~0 .lut_mask = 64'h0011AABB5511FFBB;
defparam \A_SPW_TOP|rx_data|Selector558~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X45_Y5_N2
dffeas \A_SPW_TOP|rx_data|mem[59][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector558~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[59][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[59][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[59][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y5_N27
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector540~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector540~0_combout  = ( \A_SPW_TOP|SPW|RX|rx_data_flag [0] & ( \A_SPW_TOP|rx_data|Selector532~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|rx_data|Mux8~20_combout ) ) ) ) # ( 
// !\A_SPW_TOP|SPW|RX|rx_data_flag [0] & ( \A_SPW_TOP|rx_data|Selector532~0_combout  & ( (\A_SPW_TOP|rx_data|Mux8~20_combout  & \A_SPW_TOP|rx_data|state_data_write.00~q ) ) ) ) # ( \A_SPW_TOP|SPW|RX|rx_data_flag [0] & ( 
// !\A_SPW_TOP|rx_data|Selector532~0_combout  & ( \A_SPW_TOP|rx_data|mem[57][0]~q  ) ) ) # ( !\A_SPW_TOP|SPW|RX|rx_data_flag [0] & ( !\A_SPW_TOP|rx_data|Selector532~0_combout  & ( \A_SPW_TOP|rx_data|mem[57][0]~q  ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .datab(!\A_SPW_TOP|rx_data|mem[57][0]~q ),
        .datac(gnd),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .dataf(!\A_SPW_TOP|rx_data|Selector532~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector540~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector540~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector540~0 .lut_mask = 64'h333333330055FF55;
defparam \A_SPW_TOP|rx_data|Selector540~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y5_N41
dffeas \A_SPW_TOP|rx_data|mem[57][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector540~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[57][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[57][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[57][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y5_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux8~16 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux8~16_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [1] & ( \A_SPW_TOP|rx_data|mem[57][0]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[43][0]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|mem[59][0]~q ))) ) 
// ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [1] & ( \A_SPW_TOP|rx_data|mem[57][0]~q  & ( (\A_SPW_TOP|rx_data|wr_ptr [4]) # (\A_SPW_TOP|rx_data|mem[41][0]~q ) ) ) ) # ( \A_SPW_TOP|rx_data|wr_ptr [1] & ( !\A_SPW_TOP|rx_data|mem[57][0]~q  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[43][0]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|mem[59][0]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [1] & ( !\A_SPW_TOP|rx_data|mem[57][0]~q  & ( 
// (\A_SPW_TOP|rx_data|mem[41][0]~q  & !\A_SPW_TOP|rx_data|wr_ptr [4]) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[41][0]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[43][0]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[59][0]~q ),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .dataf(!\A_SPW_TOP|rx_data|mem[57][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux8~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux8~16 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux8~16 .lut_mask = 64'h5500330F55FF330F;
defparam \A_SPW_TOP|rx_data|Mux8~16 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y5_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector450~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector450~0_combout  = ( \A_SPW_TOP|rx_data|Selector442~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [0]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux8~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector442~0_combout  & ( \A_SPW_TOP|rx_data|mem[47][0]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[47][0]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector442~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector450~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector450~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector450~0 .lut_mask = 64'h00FF00FF35353535;
defparam \A_SPW_TOP|rx_data|Selector450~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y5_N23
dffeas \A_SPW_TOP|rx_data|mem[47][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector450~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[47][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[47][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[47][0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y5_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector594~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector594~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector586~0_combout  & ((\A_SPW_TOP|rx_data|mem[63][0]~q ))) # (\A_SPW_TOP|rx_data|Selector586~0_combout  & 
// (\A_SPW_TOP|rx_data|Mux8~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector586~0_combout  & ((\A_SPW_TOP|rx_data|mem[63][0]~q ))) # (\A_SPW_TOP|rx_data|Selector586~0_combout  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [0])) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .datab(!\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector586~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[63][0]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector594~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector594~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector594~0 .lut_mask = 64'h05F505F503F303F3;
defparam \A_SPW_TOP|rx_data|Selector594~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y5_N14
dffeas \A_SPW_TOP|rx_data|mem[63][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector594~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[63][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[63][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[63][0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y5_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector432~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector432~0_combout  = ( \A_SPW_TOP|rx_data|mem[45][0]~q  & ( (!\A_SPW_TOP|rx_data|Selector424~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [0])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux8~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[45][0]~q  & ( (\A_SPW_TOP|rx_data|Selector424~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [0])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux8~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .datab(!\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector424~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[45][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector432~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector432~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector432~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|rx_data|Selector432~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y5_N20
dffeas \A_SPW_TOP|rx_data|mem[45][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector432~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[45][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[45][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[45][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y5_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector576~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector576~0_combout  = ( \A_SPW_TOP|rx_data|mem[61][0]~q  & ( \A_SPW_TOP|rx_data|Mux8~20_combout  & ( ((!\A_SPW_TOP|rx_data|Selector568~0_combout ) # (\A_SPW_TOP|rx_data|state_data_write.00~q )) # (\A_SPW_TOP|SPW|RX|rx_data_flag [0]) 
// ) ) ) # ( !\A_SPW_TOP|rx_data|mem[61][0]~q  & ( \A_SPW_TOP|rx_data|Mux8~20_combout  & ( (\A_SPW_TOP|rx_data|Selector568~0_combout  & ((\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|SPW|RX|rx_data_flag [0]))) ) ) ) # ( 
// \A_SPW_TOP|rx_data|mem[61][0]~q  & ( !\A_SPW_TOP|rx_data|Mux8~20_combout  & ( (!\A_SPW_TOP|rx_data|Selector568~0_combout ) # ((\A_SPW_TOP|SPW|RX|rx_data_flag [0] & !\A_SPW_TOP|rx_data|state_data_write.00~q )) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[61][0]~q  & 
// ( !\A_SPW_TOP|rx_data|Mux8~20_combout  & ( (\A_SPW_TOP|SPW|RX|rx_data_flag [0] & (!\A_SPW_TOP|rx_data|state_data_write.00~q  & \A_SPW_TOP|rx_data|Selector568~0_combout )) ) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Selector568~0_combout ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|rx_data|mem[61][0]~q ),
        .dataf(!\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector576~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector576~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector576~0 .lut_mask = 64'h0404F4F40707F7F7;
defparam \A_SPW_TOP|rx_data|Selector576~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X45_Y5_N47
dffeas \A_SPW_TOP|rx_data|mem[61][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector576~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[61][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[61][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[61][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y5_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux8~18 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux8~18_combout  = ( \A_SPW_TOP|rx_data|mem[45][0]~q  & ( \A_SPW_TOP|rx_data|mem[61][0]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [1]) # ((!\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[47][0]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [4] & 
// ((\A_SPW_TOP|rx_data|mem[63][0]~q )))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[45][0]~q  & ( \A_SPW_TOP|rx_data|mem[61][0]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [1] & (((\A_SPW_TOP|rx_data|wr_ptr [4])))) # (\A_SPW_TOP|rx_data|wr_ptr [1] & 
// ((!\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[47][0]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|mem[63][0]~q ))))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[45][0]~q  & ( !\A_SPW_TOP|rx_data|mem[61][0]~q  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [1] & (((!\A_SPW_TOP|rx_data|wr_ptr [4])))) # (\A_SPW_TOP|rx_data|wr_ptr [1] & ((!\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[47][0]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|mem[63][0]~q ))))) ) 
// ) ) # ( !\A_SPW_TOP|rx_data|mem[45][0]~q  & ( !\A_SPW_TOP|rx_data|mem[61][0]~q  & ( (\A_SPW_TOP|rx_data|wr_ptr [1] & ((!\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[47][0]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [4] & 
// ((\A_SPW_TOP|rx_data|mem[63][0]~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[47][0]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[63][0]~q ),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datae(!\A_SPW_TOP|rx_data|mem[45][0]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[61][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux8~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux8~18 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux8~18 .lut_mask = 64'h0503F50305F3F5F3;
defparam \A_SPW_TOP|rx_data|Mux8~18 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y5_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux8~19 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux8~19_combout  = ( \A_SPW_TOP|rx_data|Mux8~18_combout  & ( \A_SPW_TOP|rx_data|wr_ptr [2] & ( (\A_SPW_TOP|rx_data|Mux8~17_combout ) # (\A_SPW_TOP|rx_data|wr_ptr [0]) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux8~18_combout  & ( 
// \A_SPW_TOP|rx_data|wr_ptr [2] & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & \A_SPW_TOP|rx_data|Mux8~17_combout ) ) ) ) # ( \A_SPW_TOP|rx_data|Mux8~18_combout  & ( !\A_SPW_TOP|rx_data|wr_ptr [2] & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & 
// (\A_SPW_TOP|rx_data|Mux8~15_combout )) # (\A_SPW_TOP|rx_data|wr_ptr [0] & ((\A_SPW_TOP|rx_data|Mux8~16_combout ))) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux8~18_combout  & ( !\A_SPW_TOP|rx_data|wr_ptr [2] & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & 
// (\A_SPW_TOP|rx_data|Mux8~15_combout )) # (\A_SPW_TOP|rx_data|wr_ptr [0] & ((\A_SPW_TOP|rx_data|Mux8~16_combout ))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datab(!\A_SPW_TOP|rx_data|Mux8~17_combout ),
        .datac(!\A_SPW_TOP|rx_data|Mux8~15_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux8~16_combout ),
        .datae(!\A_SPW_TOP|rx_data|Mux8~18_combout ),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux8~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux8~19 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux8~19 .lut_mask = 64'h0A5F0A5F22227777;
defparam \A_SPW_TOP|rx_data|Mux8~19 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y5_N39
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector144~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector144~0_combout  = ( \A_SPW_TOP|rx_data|mem[13][0]~q  & ( (!\A_SPW_TOP|rx_data|Selector136~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [0])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux8~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[13][0]~q  & ( (\A_SPW_TOP|rx_data|Selector136~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [0])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux8~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .datab(!\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector136~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[13][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector144~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector144~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector144~0 .lut_mask = 64'h05030503F5F3F5F3;
defparam \A_SPW_TOP|rx_data|Selector144~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y5_N53
dffeas \A_SPW_TOP|rx_data|mem[13][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector144~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[13][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[13][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[13][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y5_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector108~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector108~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector100~0_combout  & ((\A_SPW_TOP|rx_data|mem[9][0]~q ))) # (\A_SPW_TOP|rx_data|Selector100~0_combout  & 
// (\A_SPW_TOP|rx_data|Mux8~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector100~0_combout  & ((\A_SPW_TOP|rx_data|mem[9][0]~q ))) # (\A_SPW_TOP|rx_data|Selector100~0_combout  & (\A_SPW_TOP|SPW|RX|rx_data_flag 
// [0])) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .datab(!\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|Selector100~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[9][0]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector108~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector108~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector108~0 .lut_mask = 64'h05F505F503F303F3;
defparam \A_SPW_TOP|rx_data|Selector108~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y5_N23
dffeas \A_SPW_TOP|rx_data|mem[9][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector108~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[9][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[9][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[9][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y5_N45
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector252~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector252~0_combout  = ( \A_SPW_TOP|rx_data|Selector244~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [0]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux8~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector244~0_combout  & ( \A_SPW_TOP|rx_data|mem[25][0]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[25][0]~q ),
        .datac(!\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .datae(!\A_SPW_TOP|rx_data|Selector244~0_combout ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector252~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector252~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector252~0 .lut_mask = 64'h333305AF333305AF;
defparam \A_SPW_TOP|rx_data|Selector252~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y5_N11
dffeas \A_SPW_TOP|rx_data|mem[25][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector252~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[25][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[25][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[25][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y5_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector288~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector288~0_combout  = ( \A_SPW_TOP|rx_data|mem[29][0]~q  & ( (!\A_SPW_TOP|rx_data|Selector280~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [0]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux8~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[29][0]~q  & ( (\A_SPW_TOP|rx_data|Selector280~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [0]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux8~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .datad(!\A_SPW_TOP|rx_data|Selector280~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[29][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector288~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector288~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector288~0 .lut_mask = 64'h001D001DFF1DFF1D;
defparam \A_SPW_TOP|rx_data|Selector288~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y5_N8
dffeas \A_SPW_TOP|rx_data|mem[29][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector288~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[29][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[29][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[29][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y5_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux8~6 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux8~6_combout  = ( \A_SPW_TOP|rx_data|mem[29][0]~q  & ( \A_SPW_TOP|rx_data|wr_ptr [4] & ( (\A_SPW_TOP|rx_data|mem[25][0]~q ) # (\A_SPW_TOP|rx_data|wr_ptr [2]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[29][0]~q  & ( \A_SPW_TOP|rx_data|wr_ptr 
// [4] & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & \A_SPW_TOP|rx_data|mem[25][0]~q ) ) ) ) # ( \A_SPW_TOP|rx_data|mem[29][0]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [4] & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & ((\A_SPW_TOP|rx_data|mem[9][0]~q ))) # 
// (\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|mem[13][0]~q )) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[29][0]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [4] & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & ((\A_SPW_TOP|rx_data|mem[9][0]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [2] 
// & (\A_SPW_TOP|rx_data|mem[13][0]~q )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[13][0]~q ),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datac(!\A_SPW_TOP|rx_data|mem[9][0]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[25][0]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[29][0]~q ),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux8~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux8~6 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux8~6 .lut_mask = 64'h1D1D1D1D00CC33FF;
defparam \A_SPW_TOP|rx_data|Mux8~6 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y4_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector261~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector261~0_combout  = ( \A_SPW_TOP|rx_data|mem[26][0]~q  & ( (!\A_SPW_TOP|rx_data|Selector253~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [0]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux8~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[26][0]~q  & ( (\A_SPW_TOP|rx_data|Selector253~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [0]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux8~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|Selector253~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[26][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector261~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector261~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector261~0 .lut_mask = 64'h00350035FF35FF35;
defparam \A_SPW_TOP|rx_data|Selector261~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y4_N32
dffeas \A_SPW_TOP|rx_data|mem[26][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector261~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[26][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[26][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[26][0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y4_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector117~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector117~0_combout  = ( \A_SPW_TOP|rx_data|Selector109~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [0]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux8~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector109~0_combout  & ( \A_SPW_TOP|rx_data|mem[10][0]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .datac(!\A_SPW_TOP|rx_data|mem[10][0]~q ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector109~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector117~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector117~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector117~0 .lut_mask = 64'h0F0F0F0F33553355;
defparam \A_SPW_TOP|rx_data|Selector117~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y4_N53
dffeas \A_SPW_TOP|rx_data|mem[10][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector117~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[10][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[10][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[10][0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y4_N21
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector153~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector153~0_combout  = ( \A_SPW_TOP|rx_data|Selector145~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [0]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux8~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector145~0_combout  & ( \A_SPW_TOP|rx_data|mem[14][0]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .datac(!\A_SPW_TOP|rx_data|mem[14][0]~q ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector145~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector153~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector153~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector153~0 .lut_mask = 64'h0F0F0F0F33553355;
defparam \A_SPW_TOP|rx_data|Selector153~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y4_N11
dffeas \A_SPW_TOP|rx_data|mem[14][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector153~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[14][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[14][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[14][0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y4_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector297~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector297~0_combout  = ( \A_SPW_TOP|rx_data|mem[30][0]~q  & ( (!\A_SPW_TOP|rx_data|Selector289~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [0]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux8~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[30][0]~q  & ( (\A_SPW_TOP|rx_data|Selector289~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [0]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux8~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .datac(!\A_SPW_TOP|rx_data|Selector289~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[30][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector297~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector297~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector297~0 .lut_mask = 64'h03050305F3F5F3F5;
defparam \A_SPW_TOP|rx_data|Selector297~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y4_N14
dffeas \A_SPW_TOP|rx_data|mem[30][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector297~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[30][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[30][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[30][0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y4_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux8~7 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux8~7_combout  = ( \A_SPW_TOP|rx_data|mem[30][0]~q  & ( \A_SPW_TOP|rx_data|wr_ptr [4] & ( (\A_SPW_TOP|rx_data|mem[26][0]~q ) # (\A_SPW_TOP|rx_data|wr_ptr [2]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[30][0]~q  & ( \A_SPW_TOP|rx_data|wr_ptr 
// [4] & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & \A_SPW_TOP|rx_data|mem[26][0]~q ) ) ) ) # ( \A_SPW_TOP|rx_data|mem[30][0]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [4] & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|mem[10][0]~q )) # 
// (\A_SPW_TOP|rx_data|wr_ptr [2] & ((\A_SPW_TOP|rx_data|mem[14][0]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[30][0]~q  & ( !\A_SPW_TOP|rx_data|wr_ptr [4] & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|mem[10][0]~q )) # (\A_SPW_TOP|rx_data|wr_ptr 
// [2] & ((\A_SPW_TOP|rx_data|mem[14][0]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datab(!\A_SPW_TOP|rx_data|mem[26][0]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[10][0]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[14][0]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[30][0]~q ),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux8~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux8~7 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux8~7 .lut_mask = 64'h0A5F0A5F22227777;
defparam \A_SPW_TOP|rx_data|Mux8~7 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y5_N27
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector243~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector243~0_combout  = ( \A_SPW_TOP|SPW|RX|rx_data_flag [0] & ( (!\A_SPW_TOP|rx_data|Selector235~0_combout  & (((\A_SPW_TOP|rx_data|mem[24][0]~q )))) # (\A_SPW_TOP|rx_data|Selector235~0_combout  & 
// (((!\A_SPW_TOP|rx_data|state_data_write.00~q )) # (\A_SPW_TOP|rx_data|Mux8~20_combout ))) ) ) # ( !\A_SPW_TOP|SPW|RX|rx_data_flag [0] & ( (!\A_SPW_TOP|rx_data|Selector235~0_combout  & (((\A_SPW_TOP|rx_data|mem[24][0]~q )))) # 
// (\A_SPW_TOP|rx_data|Selector235~0_combout  & (\A_SPW_TOP|rx_data|Mux8~20_combout  & (\A_SPW_TOP|rx_data|state_data_write.00~q ))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Selector235~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[24][0]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector243~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector243~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector243~0 .lut_mask = 64'h01F101F10DFD0DFD;
defparam \A_SPW_TOP|rx_data|Selector243~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y5_N5
dffeas \A_SPW_TOP|rx_data|mem[24][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector243~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[24][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[24][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[24][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y5_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector99~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector99~0_combout  = ( \A_SPW_TOP|rx_data|mem[8][0]~q  & ( (!\A_SPW_TOP|rx_data|Selector91~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [0]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux8~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[8][0]~q  & ( (\A_SPW_TOP|rx_data|Selector91~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [0]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux8~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .datac(!\A_SPW_TOP|rx_data|Selector91~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[8][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector99~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector99~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector99~0 .lut_mask = 64'h03050305F3F5F3F5;
defparam \A_SPW_TOP|rx_data|Selector99~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y5_N17
dffeas \A_SPW_TOP|rx_data|mem[8][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector99~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[8][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[8][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[8][0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y5_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector279~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector279~0_combout  = ( \A_SPW_TOP|rx_data|Selector271~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [0]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux8~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector271~0_combout  & ( \A_SPW_TOP|rx_data|mem[28][0]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .datac(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .datad(!\A_SPW_TOP|rx_data|mem[28][0]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector271~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector279~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector279~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector279~0 .lut_mask = 64'h00FF00FF1B1B1B1B;
defparam \A_SPW_TOP|rx_data|Selector279~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y5_N59
dffeas \A_SPW_TOP|rx_data|mem[28][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector279~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[28][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[28][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[28][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X41_Y5_N51
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector135~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector135~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector127~0_combout  & ((\A_SPW_TOP|rx_data|mem[12][0]~q ))) # (\A_SPW_TOP|rx_data|Selector127~0_combout  & 
// (\A_SPW_TOP|rx_data|Mux8~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector127~0_combout  & ((\A_SPW_TOP|rx_data|mem[12][0]~q ))) # (\A_SPW_TOP|rx_data|Selector127~0_combout  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [0])) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .datac(!\A_SPW_TOP|rx_data|mem[12][0]~q ),
        .datad(!\A_SPW_TOP|rx_data|Selector127~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector135~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector135~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector135~0 .lut_mask = 64'h0F330F330F550F55;
defparam \A_SPW_TOP|rx_data|Selector135~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X41_Y5_N38
dffeas \A_SPW_TOP|rx_data|mem[12][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector135~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[12][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[12][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[12][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y5_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux8~5 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux8~5_combout  = ( \A_SPW_TOP|rx_data|mem[28][0]~q  & ( \A_SPW_TOP|rx_data|mem[12][0]~q  & ( ((!\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|mem[8][0]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[24][0]~q 
// ))) # (\A_SPW_TOP|rx_data|wr_ptr [2]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[28][0]~q  & ( \A_SPW_TOP|rx_data|mem[12][0]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & ((!\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|mem[8][0]~q ))) # 
// (\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[24][0]~q )))) # (\A_SPW_TOP|rx_data|wr_ptr [2] & (((!\A_SPW_TOP|rx_data|wr_ptr [4])))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[28][0]~q  & ( !\A_SPW_TOP|rx_data|mem[12][0]~q  & ( 
// (!\A_SPW_TOP|rx_data|wr_ptr [2] & ((!\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|mem[8][0]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[24][0]~q )))) # (\A_SPW_TOP|rx_data|wr_ptr [2] & (((\A_SPW_TOP|rx_data|wr_ptr [4])))) ) ) 
// ) # ( !\A_SPW_TOP|rx_data|mem[28][0]~q  & ( !\A_SPW_TOP|rx_data|mem[12][0]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & ((!\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|mem[8][0]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[24][0]~q 
// )))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[24][0]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[8][0]~q ),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datae(!\A_SPW_TOP|rx_data|mem[28][0]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[12][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux8~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux8~5 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux8~5 .lut_mask = 64'h3050305F3F503F5F;
defparam \A_SPW_TOP|rx_data|Mux8~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y5_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector126~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector126~0_combout  = ( \A_SPW_TOP|rx_data|Selector118~0_combout  & ( \A_SPW_TOP|SPW|RX|rx_data_flag [0] & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|rx_data|Mux8~20_combout ) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|Selector118~0_combout  & ( \A_SPW_TOP|SPW|RX|rx_data_flag [0] & ( \A_SPW_TOP|rx_data|mem[11][0]~q  ) ) ) # ( \A_SPW_TOP|rx_data|Selector118~0_combout  & ( !\A_SPW_TOP|SPW|RX|rx_data_flag [0] & ( (\A_SPW_TOP|rx_data|Mux8~20_combout  & 
// \A_SPW_TOP|rx_data|state_data_write.00~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|Selector118~0_combout  & ( !\A_SPW_TOP|SPW|RX|rx_data_flag [0] & ( \A_SPW_TOP|rx_data|mem[11][0]~q  ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .datac(!\A_SPW_TOP|rx_data|mem[11][0]~q ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(!\A_SPW_TOP|rx_data|Selector118~0_combout ),
        .dataf(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector126~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector126~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector126~0 .lut_mask = 64'h0F0F00330F0FFF33;
defparam \A_SPW_TOP|rx_data|Selector126~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y5_N44
dffeas \A_SPW_TOP|rx_data|mem[11][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector126~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[11][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[11][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[11][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y5_N33
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector270~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector270~0_combout  = ( \A_SPW_TOP|rx_data|Mux8~20_combout  & ( (!\A_SPW_TOP|rx_data|Selector262~0_combout  & (((\A_SPW_TOP|rx_data|mem[27][0]~q )))) # (\A_SPW_TOP|rx_data|Selector262~0_combout  & 
// (((\A_SPW_TOP|rx_data|state_data_write.00~q )) # (\A_SPW_TOP|SPW|RX|rx_data_flag [0]))) ) ) # ( !\A_SPW_TOP|rx_data|Mux8~20_combout  & ( (!\A_SPW_TOP|rx_data|Selector262~0_combout  & (((\A_SPW_TOP|rx_data|mem[27][0]~q )))) # 
// (\A_SPW_TOP|rx_data|Selector262~0_combout  & (\A_SPW_TOP|SPW|RX|rx_data_flag [0] & (!\A_SPW_TOP|rx_data|state_data_write.00~q ))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Selector262~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[27][0]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector270~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector270~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector270~0 .lut_mask = 64'h04F404F407F707F7;
defparam \A_SPW_TOP|rx_data|Selector270~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y5_N57
cyclonev_lcell_comb \A_SPW_TOP|rx_data|mem[27][0]~feeder (
// Equation(s):
// \A_SPW_TOP|rx_data|mem[27][0]~feeder_combout  = ( \A_SPW_TOP|rx_data|Selector270~0_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector270~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|mem[27][0]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[27][0]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|mem[27][0]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|rx_data|mem[27][0]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X45_Y5_N59
dffeas \A_SPW_TOP|rx_data|mem[27][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|rx_data|mem[27][0]~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[27][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[27][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[27][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y5_N33
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector306~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector306~0_combout  = ( \A_SPW_TOP|rx_data|Mux8~20_combout  & ( (!\A_SPW_TOP|rx_data|Selector298~0_combout  & (((\A_SPW_TOP|rx_data|mem[31][0]~q )))) # (\A_SPW_TOP|rx_data|Selector298~0_combout  & 
// (((\A_SPW_TOP|rx_data|state_data_write.00~q )) # (\A_SPW_TOP|SPW|RX|rx_data_flag [0]))) ) ) # ( !\A_SPW_TOP|rx_data|Mux8~20_combout  & ( (!\A_SPW_TOP|rx_data|Selector298~0_combout  & (((\A_SPW_TOP|rx_data|mem[31][0]~q )))) # 
// (\A_SPW_TOP|rx_data|Selector298~0_combout  & (\A_SPW_TOP|SPW|RX|rx_data_flag [0] & (!\A_SPW_TOP|rx_data|state_data_write.00~q ))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Selector298~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[31][0]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector306~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector306~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector306~0 .lut_mask = 64'h04F404F407F707F7;
defparam \A_SPW_TOP|rx_data|Selector306~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y5_N2
dffeas \A_SPW_TOP|rx_data|mem[31][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector306~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[31][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[31][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[31][0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y5_N33
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector162~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector162~0_combout  = ( \A_SPW_TOP|rx_data|Selector154~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [0]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux8~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector154~0_combout  & ( \A_SPW_TOP|rx_data|mem[15][0]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .datac(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .datad(!\A_SPW_TOP|rx_data|mem[15][0]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector154~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector162~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector162~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector162~0 .lut_mask = 64'h00FF00FF1B1B1B1B;
defparam \A_SPW_TOP|rx_data|Selector162~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y5_N17
dffeas \A_SPW_TOP|rx_data|mem[15][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector162~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[15][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[15][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[15][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y5_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux8~8 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux8~8_combout  = ( \A_SPW_TOP|rx_data|mem[31][0]~q  & ( \A_SPW_TOP|rx_data|mem[15][0]~q  & ( ((!\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[11][0]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|mem[27][0]~q 
// )))) # (\A_SPW_TOP|rx_data|wr_ptr [2]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[31][0]~q  & ( \A_SPW_TOP|rx_data|mem[15][0]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & ((!\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[11][0]~q )) # 
// (\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|mem[27][0]~q ))))) # (\A_SPW_TOP|rx_data|wr_ptr [2] & (!\A_SPW_TOP|rx_data|wr_ptr [4])) ) ) ) # ( \A_SPW_TOP|rx_data|mem[31][0]~q  & ( !\A_SPW_TOP|rx_data|mem[15][0]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr 
// [2] & ((!\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[11][0]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|mem[27][0]~q ))))) # (\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|wr_ptr [4])) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|mem[31][0]~q  & ( !\A_SPW_TOP|rx_data|mem[15][0]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & ((!\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[11][0]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|mem[27][0]~q ))))) 
// ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datac(!\A_SPW_TOP|rx_data|mem[11][0]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[27][0]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[31][0]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[15][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux8~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux8~8 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux8~8 .lut_mask = 64'h082A193B4C6E5D7F;
defparam \A_SPW_TOP|rx_data|Mux8~8 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y5_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux8~9 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux8~9_combout  = ( \A_SPW_TOP|rx_data|Mux8~8_combout  & ( \A_SPW_TOP|rx_data|wr_ptr [1] & ( (\A_SPW_TOP|rx_data|wr_ptr [0]) # (\A_SPW_TOP|rx_data|Mux8~7_combout ) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux8~8_combout  & ( 
// \A_SPW_TOP|rx_data|wr_ptr [1] & ( (\A_SPW_TOP|rx_data|Mux8~7_combout  & !\A_SPW_TOP|rx_data|wr_ptr [0]) ) ) ) # ( \A_SPW_TOP|rx_data|Mux8~8_combout  & ( !\A_SPW_TOP|rx_data|wr_ptr [1] & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & 
// ((\A_SPW_TOP|rx_data|Mux8~5_combout ))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|Mux8~6_combout )) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux8~8_combout  & ( !\A_SPW_TOP|rx_data|wr_ptr [1] & ( (!\A_SPW_TOP|rx_data|wr_ptr [0] & 
// ((\A_SPW_TOP|rx_data|Mux8~5_combout ))) # (\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|Mux8~6_combout )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux8~6_combout ),
        .datab(!\A_SPW_TOP|rx_data|Mux8~7_combout ),
        .datac(!\A_SPW_TOP|rx_data|Mux8~5_combout ),
        .datad(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .datae(!\A_SPW_TOP|rx_data|Mux8~8_combout ),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux8~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux8~9 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux8~9 .lut_mask = 64'h0F550F55330033FF;
defparam \A_SPW_TOP|rx_data|Mux8~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y6_N39
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector207~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector207~0_combout  = ( \A_SPW_TOP|rx_data|mem[20][0]~q  & ( (!\A_SPW_TOP|rx_data|Selector199~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [0]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux8~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[20][0]~q  & ( (\A_SPW_TOP|rx_data|Selector199~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [0]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux8~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .datac(!\A_SPW_TOP|rx_data|Selector199~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[20][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector207~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector207~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector207~0 .lut_mask = 64'h03050305F3F5F3F5;
defparam \A_SPW_TOP|rx_data|Selector207~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y6_N20
dffeas \A_SPW_TOP|rx_data|mem[20][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector207~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[20][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[20][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[20][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y6_N21
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector63~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector63~0_combout  = ( \A_SPW_TOP|rx_data|Mux8~20_combout  & ( \A_SPW_TOP|rx_data|mem[4][0]~q  & ( (!\A_SPW_TOP|rx_data|Selector55~0_combout ) # ((\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|SPW|RX|rx_data_flag [0])) ) ) 
// ) # ( !\A_SPW_TOP|rx_data|Mux8~20_combout  & ( \A_SPW_TOP|rx_data|mem[4][0]~q  & ( (!\A_SPW_TOP|rx_data|Selector55~0_combout ) # ((\A_SPW_TOP|SPW|RX|rx_data_flag [0] & !\A_SPW_TOP|rx_data|state_data_write.00~q )) ) ) ) # ( 
// \A_SPW_TOP|rx_data|Mux8~20_combout  & ( !\A_SPW_TOP|rx_data|mem[4][0]~q  & ( (\A_SPW_TOP|rx_data|Selector55~0_combout  & ((\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|SPW|RX|rx_data_flag [0]))) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux8~20_combout  & 
// ( !\A_SPW_TOP|rx_data|mem[4][0]~q  & ( (\A_SPW_TOP|rx_data|Selector55~0_combout  & (\A_SPW_TOP|SPW|RX|rx_data_flag [0] & !\A_SPW_TOP|rx_data|state_data_write.00~q )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Selector55~0_combout ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(!\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .dataf(!\A_SPW_TOP|rx_data|mem[4][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector63~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector63~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector63~0 .lut_mask = 64'h05000555AFAAAFFF;
defparam \A_SPW_TOP|rx_data|Selector63~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y6_N26
dffeas \A_SPW_TOP|rx_data|mem[4][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector63~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[4][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[4][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[4][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y6_N15
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector171~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector171~0_combout  = ( \A_SPW_TOP|rx_data|Mux8~20_combout  & ( (!\A_SPW_TOP|rx_data|Selector163~0_combout  & (((\A_SPW_TOP|rx_data|mem[16][0]~q )))) # (\A_SPW_TOP|rx_data|Selector163~0_combout  & 
// (((\A_SPW_TOP|rx_data|state_data_write.00~q )) # (\A_SPW_TOP|SPW|RX|rx_data_flag [0]))) ) ) # ( !\A_SPW_TOP|rx_data|Mux8~20_combout  & ( (!\A_SPW_TOP|rx_data|Selector163~0_combout  & (((\A_SPW_TOP|rx_data|mem[16][0]~q )))) # 
// (\A_SPW_TOP|rx_data|Selector163~0_combout  & (\A_SPW_TOP|SPW|RX|rx_data_flag [0] & ((!\A_SPW_TOP|rx_data|state_data_write.00~q )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Selector163~0_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .datac(!\A_SPW_TOP|rx_data|mem[16][0]~q ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(!\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector171~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector171~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector171~0 .lut_mask = 64'h1B0A1B5F1B0A1B5F;
defparam \A_SPW_TOP|rx_data|Selector171~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y6_N14
dffeas \A_SPW_TOP|rx_data|mem[16][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector171~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[16][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[16][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[16][0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y6_N57
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector27~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector27~0_combout  = ( \A_SPW_TOP|rx_data|mem[0][0]~q  & ( (!\A_SPW_TOP|rx_data|Selector19~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [0]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux8~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[0][0]~q  & ( (\A_SPW_TOP|rx_data|Selector19~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [0]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux8~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .datad(!\A_SPW_TOP|rx_data|Selector19~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[0][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector27~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector27~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector27~0 .lut_mask = 64'h001D001DFF1DFF1D;
defparam \A_SPW_TOP|rx_data|Selector27~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y6_N17
dffeas \A_SPW_TOP|rx_data|mem[0][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector27~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[0][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[0][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[0][0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y6_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux8~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux8~0_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [4] & ( \A_SPW_TOP|rx_data|mem[0][0]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & ((\A_SPW_TOP|rx_data|mem[16][0]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|mem[20][0]~q )) ) ) 
// ) # ( !\A_SPW_TOP|rx_data|wr_ptr [4] & ( \A_SPW_TOP|rx_data|mem[0][0]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2]) # (\A_SPW_TOP|rx_data|mem[4][0]~q ) ) ) ) # ( \A_SPW_TOP|rx_data|wr_ptr [4] & ( !\A_SPW_TOP|rx_data|mem[0][0]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr 
// [2] & ((\A_SPW_TOP|rx_data|mem[16][0]~q ))) # (\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|mem[20][0]~q )) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [4] & ( !\A_SPW_TOP|rx_data|mem[0][0]~q  & ( (\A_SPW_TOP|rx_data|wr_ptr [2] & 
// \A_SPW_TOP|rx_data|mem[4][0]~q ) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datab(!\A_SPW_TOP|rx_data|mem[20][0]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[4][0]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[16][0]~q ),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .dataf(!\A_SPW_TOP|rx_data|mem[0][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux8~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux8~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux8~0 .lut_mask = 64'h050511BBAFAF11BB;
defparam \A_SPW_TOP|rx_data|Mux8~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y7_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector54~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector54~0_combout  = ( \A_SPW_TOP|rx_data|mem[3][0]~q  & ( (!\A_SPW_TOP|rx_data|Selector46~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [0])) # (\A_SPW_TOP|rx_data|state_data_write.00~q 
//  & ((\A_SPW_TOP|rx_data|Mux8~20_combout )))) ) ) # ( !\A_SPW_TOP|rx_data|mem[3][0]~q  & ( (\A_SPW_TOP|rx_data|Selector46~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [0])) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|rx_data|Mux8~20_combout ))))) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Selector46~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[3][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector54~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector54~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector54~0 .lut_mask = 64'h04070407F4F7F4F7;
defparam \A_SPW_TOP|rx_data|Selector54~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y7_N9
cyclonev_lcell_comb \A_SPW_TOP|rx_data|mem[3][0]~feeder (
// Equation(s):
// \A_SPW_TOP|rx_data|mem[3][0]~feeder_combout  = ( \A_SPW_TOP|rx_data|Selector54~0_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector54~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|mem[3][0]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[3][0]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|mem[3][0]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|rx_data|mem[3][0]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y7_N11
dffeas \A_SPW_TOP|rx_data|mem[3][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|rx_data|mem[3][0]~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[3][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[3][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[3][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y6_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector234~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector234~0_combout  = ( \A_SPW_TOP|rx_data|Selector226~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|SPW|RX|rx_data_flag [0])) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// ((\A_SPW_TOP|rx_data|Mux8~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|Selector226~0_combout  & ( \A_SPW_TOP|rx_data|mem[23][0]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .datac(!\A_SPW_TOP|rx_data|mem[23][0]~q ),
        .datad(!\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector226~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector234~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector234~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector234~0 .lut_mask = 64'h0F0F0F0F22772277;
defparam \A_SPW_TOP|rx_data|Selector234~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y6_N56
dffeas \A_SPW_TOP|rx_data|mem[23][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector234~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[23][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[23][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[23][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y6_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector90~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector90~0_combout  = ( \A_SPW_TOP|rx_data|mem[7][0]~q  & ( (!\A_SPW_TOP|rx_data|Selector82~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [0]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux8~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[7][0]~q  & ( (\A_SPW_TOP|rx_data|Selector82~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [0]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux8~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .datab(!\A_SPW_TOP|rx_data|Selector82~0_combout ),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .datae(!\A_SPW_TOP|rx_data|mem[7][0]~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector90~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector90~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector90~0 .lut_mask = 64'h0131CDFD0131CDFD;
defparam \A_SPW_TOP|rx_data|Selector90~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y6_N44
dffeas \A_SPW_TOP|rx_data|mem[7][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector90~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[7][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[7][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[7][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y6_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector198~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector198~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector190~0_combout  & (\A_SPW_TOP|rx_data|mem[19][0]~q )) # (\A_SPW_TOP|rx_data|Selector190~0_combout  & 
// ((\A_SPW_TOP|rx_data|Mux8~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector190~0_combout  & (\A_SPW_TOP|rx_data|mem[19][0]~q )) # (\A_SPW_TOP|rx_data|Selector190~0_combout  & 
// ((\A_SPW_TOP|SPW|RX|rx_data_flag [0]))) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[19][0]~q ),
        .datab(!\A_SPW_TOP|rx_data|Selector190~0_combout ),
        .datac(!\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .datae(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector198~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector198~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector198~0 .lut_mask = 64'h4477474744774747;
defparam \A_SPW_TOP|rx_data|Selector198~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y6_N8
dffeas \A_SPW_TOP|rx_data|mem[19][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector198~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[19][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[19][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[19][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y6_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux8~3 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux8~3_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [4] & ( \A_SPW_TOP|rx_data|mem[19][0]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2]) # (\A_SPW_TOP|rx_data|mem[23][0]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [4] & ( 
// \A_SPW_TOP|rx_data|mem[19][0]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|mem[3][0]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [2] & ((\A_SPW_TOP|rx_data|mem[7][0]~q ))) ) ) ) # ( \A_SPW_TOP|rx_data|wr_ptr [4] & ( !\A_SPW_TOP|rx_data|mem[19][0]~q  
// & ( (\A_SPW_TOP|rx_data|wr_ptr [2] & \A_SPW_TOP|rx_data|mem[23][0]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [4] & ( !\A_SPW_TOP|rx_data|mem[19][0]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|mem[3][0]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [2] 
// & ((\A_SPW_TOP|rx_data|mem[7][0]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datab(!\A_SPW_TOP|rx_data|mem[3][0]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[23][0]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[7][0]~q ),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .dataf(!\A_SPW_TOP|rx_data|mem[19][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux8~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux8~3 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux8~3 .lut_mask = 64'h227705052277AFAF;
defparam \A_SPW_TOP|rx_data|Mux8~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y6_N45
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector45~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector45~0_combout  = ( \A_SPW_TOP|rx_data|mem[2][0]~q  & ( (!\A_SPW_TOP|rx_data|Selector37~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [0]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux8~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[2][0]~q  & ( (\A_SPW_TOP|rx_data|Selector37~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [0]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux8~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(!\A_SPW_TOP|rx_data|Selector37~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[2][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector45~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector45~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector45~0 .lut_mask = 64'h00350035FF35FF35;
defparam \A_SPW_TOP|rx_data|Selector45~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y6_N47
dffeas \A_SPW_TOP|rx_data|mem[2][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector45~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[2][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[2][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[2][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y6_N57
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector189~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector189~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector181~0_combout  & ((\A_SPW_TOP|rx_data|mem[18][0]~q ))) # (\A_SPW_TOP|rx_data|Selector181~0_combout  & 
// (\A_SPW_TOP|rx_data|Mux8~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector181~0_combout  & ((\A_SPW_TOP|rx_data|mem[18][0]~q ))) # (\A_SPW_TOP|rx_data|Selector181~0_combout  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [0])) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .datac(!\A_SPW_TOP|rx_data|mem[18][0]~q ),
        .datad(!\A_SPW_TOP|rx_data|Selector181~0_combout ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector189~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector189~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector189~0 .lut_mask = 64'h0F330F330F550F55;
defparam \A_SPW_TOP|rx_data|Selector189~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y6_N44
dffeas \A_SPW_TOP|rx_data|mem[18][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector189~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[18][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[18][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[18][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y6_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector81~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector81~0_combout  = ( \A_SPW_TOP|rx_data|Selector73~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [0]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux8~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector73~0_combout  & ( \A_SPW_TOP|rx_data|mem[6][0]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .datac(!\A_SPW_TOP|rx_data|mem[6][0]~q ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector73~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector81~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector81~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector81~0 .lut_mask = 64'h0F0F0F0F33553355;
defparam \A_SPW_TOP|rx_data|Selector81~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y6_N5
dffeas \A_SPW_TOP|rx_data|mem[6][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector81~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[6][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[6][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[6][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y6_N57
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector225~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector225~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector217~0_combout  & (\A_SPW_TOP|rx_data|mem[22][0]~q )) # (\A_SPW_TOP|rx_data|Selector217~0_combout  & 
// ((\A_SPW_TOP|rx_data|Mux8~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector217~0_combout  & ((\A_SPW_TOP|rx_data|mem[22][0]~q ))) # (\A_SPW_TOP|rx_data|Selector217~0_combout  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [0])) ) )

        .dataa(!\A_SPW_TOP|rx_data|Selector217~0_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .datac(!\A_SPW_TOP|rx_data|mem[22][0]~q ),
        .datad(!\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .datae(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector225~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector225~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector225~0 .lut_mask = 64'h1B1B0A5F1B1B0A5F;
defparam \A_SPW_TOP|rx_data|Selector225~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y6_N17
dffeas \A_SPW_TOP|rx_data|mem[22][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector225~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[22][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[22][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[22][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X46_Y6_N9
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux8~2 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux8~2_combout  = ( \A_SPW_TOP|rx_data|mem[6][0]~q  & ( \A_SPW_TOP|rx_data|mem[22][0]~q  & ( ((!\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[2][0]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|mem[18][0]~q )))) 
// # (\A_SPW_TOP|rx_data|wr_ptr [2]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[6][0]~q  & ( \A_SPW_TOP|rx_data|mem[22][0]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & ((!\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[2][0]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [4] 
// & ((\A_SPW_TOP|rx_data|mem[18][0]~q ))))) # (\A_SPW_TOP|rx_data|wr_ptr [2] & (((\A_SPW_TOP|rx_data|wr_ptr [4])))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[6][0]~q  & ( !\A_SPW_TOP|rx_data|mem[22][0]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & 
// ((!\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[2][0]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|mem[18][0]~q ))))) # (\A_SPW_TOP|rx_data|wr_ptr [2] & (((!\A_SPW_TOP|rx_data|wr_ptr [4])))) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|mem[6][0]~q  & ( !\A_SPW_TOP|rx_data|mem[22][0]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & ((!\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[2][0]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|mem[18][0]~q ))))) ) 
// ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datab(!\A_SPW_TOP|rx_data|mem[2][0]~q ),
        .datac(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datad(!\A_SPW_TOP|rx_data|mem[18][0]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[6][0]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[22][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux8~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux8~2 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux8~2 .lut_mask = 64'h202A707A252F757F;
defparam \A_SPW_TOP|rx_data|Mux8~2 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y7_N39
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector36~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector36~0_combout  = ( \A_SPW_TOP|rx_data|Mux8~20_combout  & ( \A_SPW_TOP|rx_data|mem[1][0]~q  & ( ((!\A_SPW_TOP|rx_data|Selector28~0_combout ) # (\A_SPW_TOP|rx_data|state_data_write.00~q )) # (\A_SPW_TOP|SPW|RX|rx_data_flag [0]) ) ) 
// ) # ( !\A_SPW_TOP|rx_data|Mux8~20_combout  & ( \A_SPW_TOP|rx_data|mem[1][0]~q  & ( (!\A_SPW_TOP|rx_data|Selector28~0_combout ) # ((\A_SPW_TOP|SPW|RX|rx_data_flag [0] & !\A_SPW_TOP|rx_data|state_data_write.00~q )) ) ) ) # ( 
// \A_SPW_TOP|rx_data|Mux8~20_combout  & ( !\A_SPW_TOP|rx_data|mem[1][0]~q  & ( (\A_SPW_TOP|rx_data|Selector28~0_combout  & ((\A_SPW_TOP|rx_data|state_data_write.00~q ) # (\A_SPW_TOP|SPW|RX|rx_data_flag [0]))) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux8~20_combout  & 
// ( !\A_SPW_TOP|rx_data|mem[1][0]~q  & ( (\A_SPW_TOP|SPW|RX|rx_data_flag [0] & (\A_SPW_TOP|rx_data|Selector28~0_combout  & !\A_SPW_TOP|rx_data|state_data_write.00~q )) ) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .datab(!\A_SPW_TOP|rx_data|Selector28~0_combout ),
        .datac(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .dataf(!\A_SPW_TOP|rx_data|mem[1][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector36~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector36~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector36~0 .lut_mask = 64'h10101313DCDCDFDF;
defparam \A_SPW_TOP|rx_data|Selector36~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y7_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|mem[1][0]~feeder (
// Equation(s):
// \A_SPW_TOP|rx_data|mem[1][0]~feeder_combout  = ( \A_SPW_TOP|rx_data|Selector36~0_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector36~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|mem[1][0]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[1][0]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|mem[1][0]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|rx_data|mem[1][0]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y7_N50
dffeas \A_SPW_TOP|rx_data|mem[1][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(\A_SPW_TOP|rx_data|mem[1][0]~feeder_combout ),
        .asdata(vcc),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[1][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[1][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[1][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y6_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector180~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector180~0_combout  = ( \A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector172~0_combout  & ((\A_SPW_TOP|rx_data|mem[17][0]~q ))) # (\A_SPW_TOP|rx_data|Selector172~0_combout  & 
// (\A_SPW_TOP|rx_data|Mux8~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|state_data_write.00~q  & ( (!\A_SPW_TOP|rx_data|Selector172~0_combout  & ((\A_SPW_TOP|rx_data|mem[17][0]~q ))) # (\A_SPW_TOP|rx_data|Selector172~0_combout  & 
// (\A_SPW_TOP|SPW|RX|rx_data_flag [0])) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .datac(!\A_SPW_TOP|rx_data|Selector172~0_combout ),
        .datad(!\A_SPW_TOP|rx_data|mem[17][0]~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector180~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector180~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector180~0 .lut_mask = 64'h03F303F305F505F5;
defparam \A_SPW_TOP|rx_data|Selector180~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y6_N29
dffeas \A_SPW_TOP|rx_data|mem[17][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector180~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[17][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[17][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[17][0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y6_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector216~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector216~0_combout  = ( \A_SPW_TOP|rx_data|mem[21][0]~q  & ( (!\A_SPW_TOP|rx_data|Selector208~0_combout ) # ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [0]))) # 
// (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux8~20_combout ))) ) ) # ( !\A_SPW_TOP|rx_data|mem[21][0]~q  & ( (\A_SPW_TOP|rx_data|Selector208~0_combout  & ((!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag 
// [0]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & (\A_SPW_TOP|rx_data|Mux8~20_combout )))) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .datab(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datac(!\A_SPW_TOP|rx_data|Selector208~0_combout ),
        .datad(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|mem[21][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector216~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector216~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector216~0 .lut_mask = 64'h010D010DF1FDF1FD;
defparam \A_SPW_TOP|rx_data|Selector216~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X42_Y6_N8
dffeas \A_SPW_TOP|rx_data|mem[21][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector216~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[21][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[21][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[21][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X43_Y6_N33
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector72~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector72~0_combout  = ( \A_SPW_TOP|rx_data|Selector64~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [0]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux8~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector64~0_combout  & ( \A_SPW_TOP|rx_data|mem[5][0]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .datab(!\A_SPW_TOP|rx_data|mem[5][0]~q ),
        .datac(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(!\A_SPW_TOP|rx_data|Selector64~0_combout ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector72~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector72~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector72~0 .lut_mask = 64'h33330F5533330F55;
defparam \A_SPW_TOP|rx_data|Selector72~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X43_Y6_N47
dffeas \A_SPW_TOP|rx_data|mem[5][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector72~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[5][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[5][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[5][0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X42_Y6_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux8~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux8~1_combout  = ( \A_SPW_TOP|rx_data|mem[21][0]~q  & ( \A_SPW_TOP|rx_data|mem[5][0]~q  & ( ((!\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[1][0]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|mem[17][0]~q )))) 
// # (\A_SPW_TOP|rx_data|wr_ptr [2]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[21][0]~q  & ( \A_SPW_TOP|rx_data|mem[5][0]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & ((!\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[1][0]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [4] 
// & ((\A_SPW_TOP|rx_data|mem[17][0]~q ))))) # (\A_SPW_TOP|rx_data|wr_ptr [2] & (!\A_SPW_TOP|rx_data|wr_ptr [4])) ) ) ) # ( \A_SPW_TOP|rx_data|mem[21][0]~q  & ( !\A_SPW_TOP|rx_data|mem[5][0]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & 
// ((!\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[1][0]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|mem[17][0]~q ))))) # (\A_SPW_TOP|rx_data|wr_ptr [2] & (\A_SPW_TOP|rx_data|wr_ptr [4])) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[21][0]~q 
//  & ( !\A_SPW_TOP|rx_data|mem[5][0]~q  & ( (!\A_SPW_TOP|rx_data|wr_ptr [2] & ((!\A_SPW_TOP|rx_data|wr_ptr [4] & (\A_SPW_TOP|rx_data|mem[1][0]~q )) # (\A_SPW_TOP|rx_data|wr_ptr [4] & ((\A_SPW_TOP|rx_data|mem[17][0]~q ))))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [2]),
        .datab(!\A_SPW_TOP|rx_data|wr_ptr [4]),
        .datac(!\A_SPW_TOP|rx_data|mem[1][0]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[17][0]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[21][0]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[5][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux8~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux8~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux8~1 .lut_mask = 64'h082A193B4C6E5D7F;
defparam \A_SPW_TOP|rx_data|Mux8~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y6_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux8~4 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux8~4_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [0] & ( \A_SPW_TOP|rx_data|wr_ptr [1] & ( \A_SPW_TOP|rx_data|Mux8~3_combout  ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [0] & ( \A_SPW_TOP|rx_data|wr_ptr [1] & ( \A_SPW_TOP|rx_data|Mux8~2_combout  
// ) ) ) # ( \A_SPW_TOP|rx_data|wr_ptr [0] & ( !\A_SPW_TOP|rx_data|wr_ptr [1] & ( \A_SPW_TOP|rx_data|Mux8~1_combout  ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [0] & ( !\A_SPW_TOP|rx_data|wr_ptr [1] & ( \A_SPW_TOP|rx_data|Mux8~0_combout  ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux8~0_combout ),
        .datab(!\A_SPW_TOP|rx_data|Mux8~3_combout ),
        .datac(!\A_SPW_TOP|rx_data|Mux8~2_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux8~1_combout ),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [0]),
        .dataf(!\A_SPW_TOP|rx_data|wr_ptr [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux8~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux8~4 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux8~4 .lut_mask = 64'h555500FF0F0F3333;
defparam \A_SPW_TOP|rx_data|Mux8~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y6_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux8~20 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux8~20_combout  = ( \A_SPW_TOP|rx_data|wr_ptr [3] & ( \A_SPW_TOP|rx_data|Mux8~4_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & ((\A_SPW_TOP|rx_data|Mux8~9_combout ))) # (\A_SPW_TOP|rx_data|wr_ptr [5] & 
// (\A_SPW_TOP|rx_data|Mux8~19_combout )) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [3] & ( \A_SPW_TOP|rx_data|Mux8~4_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [5]) # (\A_SPW_TOP|rx_data|Mux8~14_combout ) ) ) ) # ( \A_SPW_TOP|rx_data|wr_ptr [3] & ( 
// !\A_SPW_TOP|rx_data|Mux8~4_combout  & ( (!\A_SPW_TOP|rx_data|wr_ptr [5] & ((\A_SPW_TOP|rx_data|Mux8~9_combout ))) # (\A_SPW_TOP|rx_data|wr_ptr [5] & (\A_SPW_TOP|rx_data|Mux8~19_combout )) ) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [3] & ( 
// !\A_SPW_TOP|rx_data|Mux8~4_combout  & ( (\A_SPW_TOP|rx_data|wr_ptr [5] & \A_SPW_TOP|rx_data|Mux8~14_combout ) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|wr_ptr [5]),
        .datab(!\A_SPW_TOP|rx_data|Mux8~14_combout ),
        .datac(!\A_SPW_TOP|rx_data|Mux8~19_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux8~9_combout ),
        .datae(!\A_SPW_TOP|rx_data|wr_ptr [3]),
        .dataf(!\A_SPW_TOP|rx_data|Mux8~4_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux8~20 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux8~20 .lut_mask = 64'h111105AFBBBB05AF;
defparam \A_SPW_TOP|rx_data|Mux8~20 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y6_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Selector378~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Selector378~0_combout  = ( \A_SPW_TOP|rx_data|Selector370~0_combout  & ( (!\A_SPW_TOP|rx_data|state_data_write.00~q  & ((\A_SPW_TOP|SPW|RX|rx_data_flag [0]))) # (\A_SPW_TOP|rx_data|state_data_write.00~q  & 
// (\A_SPW_TOP|rx_data|Mux8~20_combout )) ) ) # ( !\A_SPW_TOP|rx_data|Selector370~0_combout  & ( \A_SPW_TOP|rx_data|mem[39][0]~q  ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux8~20_combout ),
        .datab(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
        .datac(!\A_SPW_TOP|rx_data|mem[39][0]~q ),
        .datad(!\A_SPW_TOP|rx_data|state_data_write.00~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|rx_data|Selector370~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Selector378~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Selector378~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Selector378~0 .lut_mask = 64'h0F0F0F0F33553355;
defparam \A_SPW_TOP|rx_data|Selector378~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X46_Y6_N2
dffeas \A_SPW_TOP|rx_data|mem[39][0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Selector378~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|mem[39][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem[39][0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem[39][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X45_Y6_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux17~3 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux17~3_combout  = ( \A_SPW_TOP|rx_data|mem[6][0]~q  & ( \A_SPW_TOP|rx_data|rd_ptr [0] & ( (!\A_SPW_TOP|rx_data|rd_ptr [5] & ((\A_SPW_TOP|rx_data|mem[7][0]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [5] & (\A_SPW_TOP|rx_data|mem[39][0]~q )) ) ) 
// ) # ( !\A_SPW_TOP|rx_data|mem[6][0]~q  & ( \A_SPW_TOP|rx_data|rd_ptr [0] & ( (!\A_SPW_TOP|rx_data|rd_ptr [5] & ((\A_SPW_TOP|rx_data|mem[7][0]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [5] & (\A_SPW_TOP|rx_data|mem[39][0]~q )) ) ) ) # ( 
// \A_SPW_TOP|rx_data|mem[6][0]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [0] & ( (!\A_SPW_TOP|rx_data|rd_ptr [5]) # (\A_SPW_TOP|rx_data|mem[38][0]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[6][0]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [0] & ( (\A_SPW_TOP|rx_data|mem[38][0]~q 
//  & \A_SPW_TOP|rx_data|rd_ptr [5]) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[39][0]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[7][0]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[38][0]~q ),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .datae(!\A_SPW_TOP|rx_data|mem[6][0]~q ),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux17~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux17~3 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux17~3 .lut_mask = 64'h000FFF0F33553355;
defparam \A_SPW_TOP|rx_data|Mux17~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y6_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux17~2 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux17~2_combout  = ( \A_SPW_TOP|rx_data|mem[2][0]~q  & ( \A_SPW_TOP|rx_data|mem[3][0]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [5]) # ((!\A_SPW_TOP|rx_data|rd_ptr [0] & ((\A_SPW_TOP|rx_data|mem[34][0]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [0] & 
// (\A_SPW_TOP|rx_data|mem[35][0]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[2][0]~q  & ( \A_SPW_TOP|rx_data|mem[3][0]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [5] & (((\A_SPW_TOP|rx_data|rd_ptr [0])))) # (\A_SPW_TOP|rx_data|rd_ptr [5] & ((!\A_SPW_TOP|rx_data|rd_ptr 
// [0] & ((\A_SPW_TOP|rx_data|mem[34][0]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [0] & (\A_SPW_TOP|rx_data|mem[35][0]~q )))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[2][0]~q  & ( !\A_SPW_TOP|rx_data|mem[3][0]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [5] & 
// (((!\A_SPW_TOP|rx_data|rd_ptr [0])))) # (\A_SPW_TOP|rx_data|rd_ptr [5] & ((!\A_SPW_TOP|rx_data|rd_ptr [0] & ((\A_SPW_TOP|rx_data|mem[34][0]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [0] & (\A_SPW_TOP|rx_data|mem[35][0]~q )))) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|mem[2][0]~q  & ( !\A_SPW_TOP|rx_data|mem[3][0]~q  & ( (\A_SPW_TOP|rx_data|rd_ptr [5] & ((!\A_SPW_TOP|rx_data|rd_ptr [0] & ((\A_SPW_TOP|rx_data|mem[34][0]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [0] & (\A_SPW_TOP|rx_data|mem[35][0]~q )))) ) 
// ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[35][0]~q ),
        .datab(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .datad(!\A_SPW_TOP|rx_data|mem[34][0]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[2][0]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[3][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux17~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux17~2 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux17~2 .lut_mask = 64'h0131C1F10D3DCDFD;
defparam \A_SPW_TOP|rx_data|Mux17~2 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y6_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux17~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux17~0_combout  = ( \A_SPW_TOP|rx_data|mem[33][0]~q  & ( \A_SPW_TOP|rx_data|mem[1][0]~q  & ( ((!\A_SPW_TOP|rx_data|rd_ptr [5] & ((\A_SPW_TOP|rx_data|mem[0][0]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [5] & (\A_SPW_TOP|rx_data|mem[32][0]~q 
// ))) # (\A_SPW_TOP|rx_data|rd_ptr [0]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[33][0]~q  & ( \A_SPW_TOP|rx_data|mem[1][0]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [5] & (((\A_SPW_TOP|rx_data|rd_ptr [0]) # (\A_SPW_TOP|rx_data|mem[0][0]~q )))) # 
// (\A_SPW_TOP|rx_data|rd_ptr [5] & (\A_SPW_TOP|rx_data|mem[32][0]~q  & ((!\A_SPW_TOP|rx_data|rd_ptr [0])))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[33][0]~q  & ( !\A_SPW_TOP|rx_data|mem[1][0]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [5] & 
// (((\A_SPW_TOP|rx_data|mem[0][0]~q  & !\A_SPW_TOP|rx_data|rd_ptr [0])))) # (\A_SPW_TOP|rx_data|rd_ptr [5] & (((\A_SPW_TOP|rx_data|rd_ptr [0])) # (\A_SPW_TOP|rx_data|mem[32][0]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[33][0]~q  & ( 
// !\A_SPW_TOP|rx_data|mem[1][0]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & ((!\A_SPW_TOP|rx_data|rd_ptr [5] & ((\A_SPW_TOP|rx_data|mem[0][0]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [5] & (\A_SPW_TOP|rx_data|mem[32][0]~q )))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[32][0]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[0][0]~q ),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .datae(!\A_SPW_TOP|rx_data|mem[33][0]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[1][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux17~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux17~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux17~0 .lut_mask = 64'h3500350F35F035FF;
defparam \A_SPW_TOP|rx_data|Mux17~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y6_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux17~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux17~1_combout  = ( \A_SPW_TOP|rx_data|mem[4][0]~q  & ( \A_SPW_TOP|rx_data|mem[37][0]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [5] & (((!\A_SPW_TOP|rx_data|rd_ptr [0]) # (\A_SPW_TOP|rx_data|mem[5][0]~q )))) # (\A_SPW_TOP|rx_data|rd_ptr [5] & 
// (((\A_SPW_TOP|rx_data|rd_ptr [0])) # (\A_SPW_TOP|rx_data|mem[36][0]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[4][0]~q  & ( \A_SPW_TOP|rx_data|mem[37][0]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [5] & (((\A_SPW_TOP|rx_data|rd_ptr [0] & 
// \A_SPW_TOP|rx_data|mem[5][0]~q )))) # (\A_SPW_TOP|rx_data|rd_ptr [5] & (((\A_SPW_TOP|rx_data|rd_ptr [0])) # (\A_SPW_TOP|rx_data|mem[36][0]~q ))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[4][0]~q  & ( !\A_SPW_TOP|rx_data|mem[37][0]~q  & ( 
// (!\A_SPW_TOP|rx_data|rd_ptr [5] & (((!\A_SPW_TOP|rx_data|rd_ptr [0]) # (\A_SPW_TOP|rx_data|mem[5][0]~q )))) # (\A_SPW_TOP|rx_data|rd_ptr [5] & (\A_SPW_TOP|rx_data|mem[36][0]~q  & (!\A_SPW_TOP|rx_data|rd_ptr [0]))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[4][0]~q 
//  & ( !\A_SPW_TOP|rx_data|mem[37][0]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [5] & (((\A_SPW_TOP|rx_data|rd_ptr [0] & \A_SPW_TOP|rx_data|mem[5][0]~q )))) # (\A_SPW_TOP|rx_data|rd_ptr [5] & (\A_SPW_TOP|rx_data|mem[36][0]~q  & (!\A_SPW_TOP|rx_data|rd_ptr [0]))) ) 
// ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .datab(!\A_SPW_TOP|rx_data|mem[36][0]~q ),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .datad(!\A_SPW_TOP|rx_data|mem[5][0]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[4][0]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[37][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux17~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux17~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux17~1 .lut_mask = 64'h101AB0BA151FB5BF;
defparam \A_SPW_TOP|rx_data|Mux17~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y6_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux17~4 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux17~4_combout  = ( \A_SPW_TOP|rx_data|rd_ptr [2] & ( \A_SPW_TOP|rx_data|Mux17~1_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [1]) # (\A_SPW_TOP|rx_data|Mux17~3_combout ) ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [2] & ( 
// \A_SPW_TOP|rx_data|Mux17~1_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & ((\A_SPW_TOP|rx_data|Mux17~0_combout ))) # (\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|Mux17~2_combout )) ) ) ) # ( \A_SPW_TOP|rx_data|rd_ptr [2] & ( 
// !\A_SPW_TOP|rx_data|Mux17~1_combout  & ( (\A_SPW_TOP|rx_data|Mux17~3_combout  & \A_SPW_TOP|rx_data|rd_ptr [1]) ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [2] & ( !\A_SPW_TOP|rx_data|Mux17~1_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & 
// ((\A_SPW_TOP|rx_data|Mux17~0_combout ))) # (\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|Mux17~2_combout )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux17~3_combout ),
        .datab(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datac(!\A_SPW_TOP|rx_data|Mux17~2_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux17~0_combout ),
        .datae(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .dataf(!\A_SPW_TOP|rx_data|Mux17~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux17~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux17~4 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux17~4 .lut_mask = 64'h03CF111103CFDDDD;
defparam \A_SPW_TOP|rx_data|Mux17~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y5_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux17~16 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux17~16_combout  = ( \A_SPW_TOP|rx_data|mem[27][0]~q  & ( \A_SPW_TOP|rx_data|mem[29][0]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & (((\A_SPW_TOP|rx_data|rd_ptr [2])) # (\A_SPW_TOP|rx_data|mem[25][0]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [1] 
// & (((!\A_SPW_TOP|rx_data|rd_ptr [2]) # (\A_SPW_TOP|rx_data|mem[31][0]~q )))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[27][0]~q  & ( \A_SPW_TOP|rx_data|mem[29][0]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & (((\A_SPW_TOP|rx_data|rd_ptr [2])) # 
// (\A_SPW_TOP|rx_data|mem[25][0]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [1] & (((\A_SPW_TOP|rx_data|mem[31][0]~q  & \A_SPW_TOP|rx_data|rd_ptr [2])))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[27][0]~q  & ( !\A_SPW_TOP|rx_data|mem[29][0]~q  & ( 
// (!\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|mem[25][0]~q  & ((!\A_SPW_TOP|rx_data|rd_ptr [2])))) # (\A_SPW_TOP|rx_data|rd_ptr [1] & (((!\A_SPW_TOP|rx_data|rd_ptr [2]) # (\A_SPW_TOP|rx_data|mem[31][0]~q )))) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|mem[27][0]~q  & ( !\A_SPW_TOP|rx_data|mem[29][0]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|mem[25][0]~q  & ((!\A_SPW_TOP|rx_data|rd_ptr [2])))) # (\A_SPW_TOP|rx_data|rd_ptr [1] & (((\A_SPW_TOP|rx_data|mem[31][0]~q  & 
// \A_SPW_TOP|rx_data|rd_ptr [2])))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datab(!\A_SPW_TOP|rx_data|mem[25][0]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[31][0]~q ),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datae(!\A_SPW_TOP|rx_data|mem[27][0]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[29][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux17~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux17~16 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux17~16 .lut_mask = 64'h2205770522AF77AF;
defparam \A_SPW_TOP|rx_data|Mux17~16 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y5_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux17~18 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux17~18_combout  = ( \A_SPW_TOP|rx_data|mem[61][0]~q  & ( \A_SPW_TOP|rx_data|mem[57][0]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [1]) # ((!\A_SPW_TOP|rx_data|rd_ptr [2] & ((\A_SPW_TOP|rx_data|mem[59][0]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [2] 
// & (\A_SPW_TOP|rx_data|mem[63][0]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[61][0]~q  & ( \A_SPW_TOP|rx_data|mem[57][0]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & (((!\A_SPW_TOP|rx_data|rd_ptr [2])))) # (\A_SPW_TOP|rx_data|rd_ptr [1] & 
// ((!\A_SPW_TOP|rx_data|rd_ptr [2] & ((\A_SPW_TOP|rx_data|mem[59][0]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|mem[63][0]~q )))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[61][0]~q  & ( !\A_SPW_TOP|rx_data|mem[57][0]~q  & ( 
// (!\A_SPW_TOP|rx_data|rd_ptr [1] & (((\A_SPW_TOP|rx_data|rd_ptr [2])))) # (\A_SPW_TOP|rx_data|rd_ptr [1] & ((!\A_SPW_TOP|rx_data|rd_ptr [2] & ((\A_SPW_TOP|rx_data|mem[59][0]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|mem[63][0]~q )))) ) ) 
// ) # ( !\A_SPW_TOP|rx_data|mem[61][0]~q  & ( !\A_SPW_TOP|rx_data|mem[57][0]~q  & ( (\A_SPW_TOP|rx_data|rd_ptr [1] & ((!\A_SPW_TOP|rx_data|rd_ptr [2] & ((\A_SPW_TOP|rx_data|mem[59][0]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|mem[63][0]~q 
// )))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[63][0]~q ),
        .datab(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datac(!\A_SPW_TOP|rx_data|mem[59][0]~q ),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datae(!\A_SPW_TOP|rx_data|mem[61][0]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[57][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux17~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux17~18 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux17~18 .lut_mask = 64'h031103DDCF11CFDD;
defparam \A_SPW_TOP|rx_data|Mux17~18 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X41_Y5_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux17~17 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux17~17_combout  = ( \A_SPW_TOP|rx_data|mem[56][0]~q  & ( \A_SPW_TOP|rx_data|mem[58][0]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [2]) # ((!\A_SPW_TOP|rx_data|rd_ptr [1] & ((\A_SPW_TOP|rx_data|mem[60][0]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [1] 
// & (\A_SPW_TOP|rx_data|mem[62][0]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[56][0]~q  & ( \A_SPW_TOP|rx_data|mem[58][0]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [2] & (((\A_SPW_TOP|rx_data|rd_ptr [1])))) # (\A_SPW_TOP|rx_data|rd_ptr [2] & 
// ((!\A_SPW_TOP|rx_data|rd_ptr [1] & ((\A_SPW_TOP|rx_data|mem[60][0]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|mem[62][0]~q )))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[56][0]~q  & ( !\A_SPW_TOP|rx_data|mem[58][0]~q  & ( 
// (!\A_SPW_TOP|rx_data|rd_ptr [2] & (((!\A_SPW_TOP|rx_data|rd_ptr [1])))) # (\A_SPW_TOP|rx_data|rd_ptr [2] & ((!\A_SPW_TOP|rx_data|rd_ptr [1] & ((\A_SPW_TOP|rx_data|mem[60][0]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|mem[62][0]~q )))) ) 
// ) ) # ( !\A_SPW_TOP|rx_data|mem[56][0]~q  & ( !\A_SPW_TOP|rx_data|mem[58][0]~q  & ( (\A_SPW_TOP|rx_data|rd_ptr [2] & ((!\A_SPW_TOP|rx_data|rd_ptr [1] & ((\A_SPW_TOP|rx_data|mem[60][0]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [1] & 
// (\A_SPW_TOP|rx_data|mem[62][0]~q )))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datab(!\A_SPW_TOP|rx_data|mem[62][0]~q ),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datad(!\A_SPW_TOP|rx_data|mem[60][0]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[56][0]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[58][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux17~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux17~17 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux17~17 .lut_mask = 64'h0151A1F10B5BABFB;
defparam \A_SPW_TOP|rx_data|Mux17~17 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y5_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux17~15 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux17~15_combout  = ( \A_SPW_TOP|rx_data|mem[24][0]~q  & ( \A_SPW_TOP|rx_data|mem[30][0]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & (((!\A_SPW_TOP|rx_data|rd_ptr [2]) # (\A_SPW_TOP|rx_data|mem[28][0]~q )))) # (\A_SPW_TOP|rx_data|rd_ptr 
// [1] & (((\A_SPW_TOP|rx_data|rd_ptr [2])) # (\A_SPW_TOP|rx_data|mem[26][0]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[24][0]~q  & ( \A_SPW_TOP|rx_data|mem[30][0]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & (((\A_SPW_TOP|rx_data|rd_ptr [2] & 
// \A_SPW_TOP|rx_data|mem[28][0]~q )))) # (\A_SPW_TOP|rx_data|rd_ptr [1] & (((\A_SPW_TOP|rx_data|rd_ptr [2])) # (\A_SPW_TOP|rx_data|mem[26][0]~q ))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[24][0]~q  & ( !\A_SPW_TOP|rx_data|mem[30][0]~q  & ( 
// (!\A_SPW_TOP|rx_data|rd_ptr [1] & (((!\A_SPW_TOP|rx_data|rd_ptr [2]) # (\A_SPW_TOP|rx_data|mem[28][0]~q )))) # (\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|mem[26][0]~q  & (!\A_SPW_TOP|rx_data|rd_ptr [2]))) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|mem[24][0]~q  & ( !\A_SPW_TOP|rx_data|mem[30][0]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & (((\A_SPW_TOP|rx_data|rd_ptr [2] & \A_SPW_TOP|rx_data|mem[28][0]~q )))) # (\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|mem[26][0]~q  & 
// (!\A_SPW_TOP|rx_data|rd_ptr [2]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[26][0]~q ),
        .datab(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datad(!\A_SPW_TOP|rx_data|mem[28][0]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[24][0]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[30][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux17~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux17~15 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux17~15 .lut_mask = 64'h101CD0DC131FD3DF;
defparam \A_SPW_TOP|rx_data|Mux17~15 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y5_N57
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux17~19 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux17~19_combout  = ( \A_SPW_TOP|rx_data|Mux17~17_combout  & ( \A_SPW_TOP|rx_data|Mux17~15_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [0]) # ((!\A_SPW_TOP|rx_data|rd_ptr [5] & (\A_SPW_TOP|rx_data|Mux17~16_combout )) # 
// (\A_SPW_TOP|rx_data|rd_ptr [5] & ((\A_SPW_TOP|rx_data|Mux17~18_combout )))) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux17~17_combout  & ( \A_SPW_TOP|rx_data|Mux17~15_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [5] & ((!\A_SPW_TOP|rx_data|rd_ptr [0]) # 
// ((\A_SPW_TOP|rx_data|Mux17~16_combout )))) # (\A_SPW_TOP|rx_data|rd_ptr [5] & (\A_SPW_TOP|rx_data|rd_ptr [0] & ((\A_SPW_TOP|rx_data|Mux17~18_combout )))) ) ) ) # ( \A_SPW_TOP|rx_data|Mux17~17_combout  & ( !\A_SPW_TOP|rx_data|Mux17~15_combout  & ( 
// (!\A_SPW_TOP|rx_data|rd_ptr [5] & (\A_SPW_TOP|rx_data|rd_ptr [0] & (\A_SPW_TOP|rx_data|Mux17~16_combout ))) # (\A_SPW_TOP|rx_data|rd_ptr [5] & ((!\A_SPW_TOP|rx_data|rd_ptr [0]) # ((\A_SPW_TOP|rx_data|Mux17~18_combout )))) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|Mux17~17_combout  & ( !\A_SPW_TOP|rx_data|Mux17~15_combout  & ( (\A_SPW_TOP|rx_data|rd_ptr [0] & ((!\A_SPW_TOP|rx_data|rd_ptr [5] & (\A_SPW_TOP|rx_data|Mux17~16_combout )) # (\A_SPW_TOP|rx_data|rd_ptr [5] & 
// ((\A_SPW_TOP|rx_data|Mux17~18_combout ))))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .datab(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .datac(!\A_SPW_TOP|rx_data|Mux17~16_combout ),
        .datad(!\A_SPW_TOP|rx_data|Mux17~18_combout ),
        .datae(!\A_SPW_TOP|rx_data|Mux17~17_combout ),
        .dataf(!\A_SPW_TOP|rx_data|Mux17~15_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux17~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux17~19 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux17~19 .lut_mask = 64'h021346578A9BCEDF;
defparam \A_SPW_TOP|rx_data|Mux17~19 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y5_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux17~13 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux17~13_combout  = ( \A_SPW_TOP|rx_data|rd_ptr [0] & ( \A_SPW_TOP|rx_data|mem[14][0]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [5] & (\A_SPW_TOP|rx_data|mem[15][0]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [5] & ((\A_SPW_TOP|rx_data|mem[47][0]~q ))) 
// ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [0] & ( \A_SPW_TOP|rx_data|mem[14][0]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [5]) # (\A_SPW_TOP|rx_data|mem[46][0]~q ) ) ) ) # ( \A_SPW_TOP|rx_data|rd_ptr [0] & ( !\A_SPW_TOP|rx_data|mem[14][0]~q  & ( 
// (!\A_SPW_TOP|rx_data|rd_ptr [5] & (\A_SPW_TOP|rx_data|mem[15][0]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [5] & ((\A_SPW_TOP|rx_data|mem[47][0]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [0] & ( !\A_SPW_TOP|rx_data|mem[14][0]~q  & ( (\A_SPW_TOP|rx_data|rd_ptr 
// [5] & \A_SPW_TOP|rx_data|mem[46][0]~q ) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[15][0]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[47][0]~q ),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .datad(!\A_SPW_TOP|rx_data|mem[46][0]~q ),
        .datae(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .dataf(!\A_SPW_TOP|rx_data|mem[14][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux17~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux17~13 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux17~13 .lut_mask = 64'h000F5353F0FF5353;
defparam \A_SPW_TOP|rx_data|Mux17~13 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y5_N9
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux17~10 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux17~10_combout  = ( \A_SPW_TOP|rx_data|mem[40][0]~q  & ( \A_SPW_TOP|rx_data|rd_ptr [5] & ( (!\A_SPW_TOP|rx_data|rd_ptr [0]) # (\A_SPW_TOP|rx_data|mem[41][0]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[40][0]~q  & ( \A_SPW_TOP|rx_data|rd_ptr 
// [5] & ( (\A_SPW_TOP|rx_data|mem[41][0]~q  & \A_SPW_TOP|rx_data|rd_ptr [0]) ) ) ) # ( \A_SPW_TOP|rx_data|mem[40][0]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [5] & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & (\A_SPW_TOP|rx_data|mem[8][0]~q )) # (\A_SPW_TOP|rx_data|rd_ptr 
// [0] & ((\A_SPW_TOP|rx_data|mem[9][0]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[40][0]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [5] & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & (\A_SPW_TOP|rx_data|mem[8][0]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [0] & 
// ((\A_SPW_TOP|rx_data|mem[9][0]~q ))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[41][0]~q ),
        .datab(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .datac(!\A_SPW_TOP|rx_data|mem[8][0]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[9][0]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[40][0]~q ),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux17~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux17~10 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux17~10 .lut_mask = 64'h0C3F0C3F1111DDDD;
defparam \A_SPW_TOP|rx_data|Mux17~10 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y5_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux17~12 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux17~12_combout  = ( \A_SPW_TOP|rx_data|mem[42][0]~q  & ( \A_SPW_TOP|rx_data|rd_ptr [5] & ( (!\A_SPW_TOP|rx_data|rd_ptr [0]) # (\A_SPW_TOP|rx_data|mem[43][0]~q ) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[42][0]~q  & ( \A_SPW_TOP|rx_data|rd_ptr 
// [5] & ( (\A_SPW_TOP|rx_data|rd_ptr [0] & \A_SPW_TOP|rx_data|mem[43][0]~q ) ) ) ) # ( \A_SPW_TOP|rx_data|mem[42][0]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [5] & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & ((\A_SPW_TOP|rx_data|mem[10][0]~q ))) # 
// (\A_SPW_TOP|rx_data|rd_ptr [0] & (\A_SPW_TOP|rx_data|mem[11][0]~q )) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[42][0]~q  & ( !\A_SPW_TOP|rx_data|rd_ptr [5] & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & ((\A_SPW_TOP|rx_data|mem[10][0]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr 
// [0] & (\A_SPW_TOP|rx_data|mem[11][0]~q )) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .datab(!\A_SPW_TOP|rx_data|mem[43][0]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[11][0]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[10][0]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[42][0]~q ),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux17~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux17~12 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux17~12 .lut_mask = 64'h05AF05AF1111BBBB;
defparam \A_SPW_TOP|rx_data|Mux17~12 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y5_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux17~11 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux17~11_combout  = ( \A_SPW_TOP|rx_data|mem[12][0]~q  & ( \A_SPW_TOP|rx_data|mem[45][0]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [5] & (((!\A_SPW_TOP|rx_data|rd_ptr [0])) # (\A_SPW_TOP|rx_data|mem[13][0]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr 
// [5] & (((\A_SPW_TOP|rx_data|rd_ptr [0]) # (\A_SPW_TOP|rx_data|mem[44][0]~q )))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[12][0]~q  & ( \A_SPW_TOP|rx_data|mem[45][0]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [5] & (\A_SPW_TOP|rx_data|mem[13][0]~q  & 
// ((\A_SPW_TOP|rx_data|rd_ptr [0])))) # (\A_SPW_TOP|rx_data|rd_ptr [5] & (((\A_SPW_TOP|rx_data|rd_ptr [0]) # (\A_SPW_TOP|rx_data|mem[44][0]~q )))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[12][0]~q  & ( !\A_SPW_TOP|rx_data|mem[45][0]~q  & ( 
// (!\A_SPW_TOP|rx_data|rd_ptr [5] & (((!\A_SPW_TOP|rx_data|rd_ptr [0])) # (\A_SPW_TOP|rx_data|mem[13][0]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [5] & (((\A_SPW_TOP|rx_data|mem[44][0]~q  & !\A_SPW_TOP|rx_data|rd_ptr [0])))) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|mem[12][0]~q  & ( !\A_SPW_TOP|rx_data|mem[45][0]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [5] & (\A_SPW_TOP|rx_data|mem[13][0]~q  & ((\A_SPW_TOP|rx_data|rd_ptr [0])))) # (\A_SPW_TOP|rx_data|rd_ptr [5] & (((\A_SPW_TOP|rx_data|mem[44][0]~q  & 
// !\A_SPW_TOP|rx_data|rd_ptr [0])))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[13][0]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[44][0]~q ),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .datae(!\A_SPW_TOP|rx_data|mem[12][0]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[45][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux17~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux17~11 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux17~11 .lut_mask = 64'h0350F350035FF35F;
defparam \A_SPW_TOP|rx_data|Mux17~11 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y5_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux17~14 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux17~14_combout  = ( \A_SPW_TOP|rx_data|Mux17~12_combout  & ( \A_SPW_TOP|rx_data|Mux17~11_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & (((\A_SPW_TOP|rx_data|Mux17~10_combout ) # (\A_SPW_TOP|rx_data|rd_ptr [2])))) # 
// (\A_SPW_TOP|rx_data|rd_ptr [1] & (((!\A_SPW_TOP|rx_data|rd_ptr [2])) # (\A_SPW_TOP|rx_data|Mux17~13_combout ))) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux17~12_combout  & ( \A_SPW_TOP|rx_data|Mux17~11_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & 
// (((\A_SPW_TOP|rx_data|Mux17~10_combout ) # (\A_SPW_TOP|rx_data|rd_ptr [2])))) # (\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|Mux17~13_combout  & (\A_SPW_TOP|rx_data|rd_ptr [2]))) ) ) ) # ( \A_SPW_TOP|rx_data|Mux17~12_combout  & ( 
// !\A_SPW_TOP|rx_data|Mux17~11_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & (((!\A_SPW_TOP|rx_data|rd_ptr [2] & \A_SPW_TOP|rx_data|Mux17~10_combout )))) # (\A_SPW_TOP|rx_data|rd_ptr [1] & (((!\A_SPW_TOP|rx_data|rd_ptr [2])) # 
// (\A_SPW_TOP|rx_data|Mux17~13_combout ))) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux17~12_combout  & ( !\A_SPW_TOP|rx_data|Mux17~11_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & (((!\A_SPW_TOP|rx_data|rd_ptr [2] & \A_SPW_TOP|rx_data|Mux17~10_combout )))) # 
// (\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|Mux17~13_combout  & (\A_SPW_TOP|rx_data|rd_ptr [2]))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux17~13_combout ),
        .datab(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datad(!\A_SPW_TOP|rx_data|Mux17~10_combout ),
        .datae(!\A_SPW_TOP|rx_data|Mux17~12_combout ),
        .dataf(!\A_SPW_TOP|rx_data|Mux17~11_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux17~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux17~14 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux17~14 .lut_mask = 64'h01C131F10DCD3DFD;
defparam \A_SPW_TOP|rx_data|Mux17~14 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X45_Y6_N15
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux17~7 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux17~7_combout  = ( \A_SPW_TOP|rx_data|rd_ptr [0] & ( \A_SPW_TOP|rx_data|rd_ptr [5] & ( \A_SPW_TOP|rx_data|mem[51][0]~q  ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [0] & ( \A_SPW_TOP|rx_data|rd_ptr [5] & ( \A_SPW_TOP|rx_data|mem[50][0]~q  ) 
// ) ) # ( \A_SPW_TOP|rx_data|rd_ptr [0] & ( !\A_SPW_TOP|rx_data|rd_ptr [5] & ( \A_SPW_TOP|rx_data|mem[19][0]~q  ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [0] & ( !\A_SPW_TOP|rx_data|rd_ptr [5] & ( \A_SPW_TOP|rx_data|mem[18][0]~q  ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[50][0]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[51][0]~q ),
        .datac(!\A_SPW_TOP|rx_data|mem[18][0]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[19][0]~q ),
        .datae(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux17~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux17~7 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux17~7 .lut_mask = 64'h0F0F00FF55553333;
defparam \A_SPW_TOP|rx_data|Mux17~7 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X46_Y6_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux17~8 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux17~8_combout  = ( \A_SPW_TOP|rx_data|mem[23][0]~q  & ( \A_SPW_TOP|rx_data|mem[22][0]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [5]) # ((!\A_SPW_TOP|rx_data|rd_ptr [0] & ((\A_SPW_TOP|rx_data|mem[54][0]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [0] 
// & (\A_SPW_TOP|rx_data|mem[55][0]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[23][0]~q  & ( \A_SPW_TOP|rx_data|mem[22][0]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & (((!\A_SPW_TOP|rx_data|rd_ptr [5]) # (\A_SPW_TOP|rx_data|mem[54][0]~q )))) # 
// (\A_SPW_TOP|rx_data|rd_ptr [0] & (\A_SPW_TOP|rx_data|mem[55][0]~q  & ((\A_SPW_TOP|rx_data|rd_ptr [5])))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[23][0]~q  & ( !\A_SPW_TOP|rx_data|mem[22][0]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & 
// (((\A_SPW_TOP|rx_data|mem[54][0]~q  & \A_SPW_TOP|rx_data|rd_ptr [5])))) # (\A_SPW_TOP|rx_data|rd_ptr [0] & (((!\A_SPW_TOP|rx_data|rd_ptr [5])) # (\A_SPW_TOP|rx_data|mem[55][0]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[23][0]~q  & ( 
// !\A_SPW_TOP|rx_data|mem[22][0]~q  & ( (\A_SPW_TOP|rx_data|rd_ptr [5] & ((!\A_SPW_TOP|rx_data|rd_ptr [0] & ((\A_SPW_TOP|rx_data|mem[54][0]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [0] & (\A_SPW_TOP|rx_data|mem[55][0]~q )))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|mem[55][0]~q ),
        .datab(!\A_SPW_TOP|rx_data|mem[54][0]~q ),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .datae(!\A_SPW_TOP|rx_data|mem[23][0]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[22][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux17~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux17~8 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux17~8 .lut_mask = 64'h00350F35F035FF35;
defparam \A_SPW_TOP|rx_data|Mux17~8 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y6_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux17~6 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux17~6_combout  = ( \A_SPW_TOP|rx_data|mem[52][0]~q  & ( \A_SPW_TOP|rx_data|mem[53][0]~q  & ( ((!\A_SPW_TOP|rx_data|rd_ptr [0] & (\A_SPW_TOP|rx_data|mem[20][0]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [0] & ((\A_SPW_TOP|rx_data|mem[21][0]~q 
// )))) # (\A_SPW_TOP|rx_data|rd_ptr [5]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[52][0]~q  & ( \A_SPW_TOP|rx_data|mem[53][0]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [5] & ((!\A_SPW_TOP|rx_data|rd_ptr [0] & (\A_SPW_TOP|rx_data|mem[20][0]~q )) # 
// (\A_SPW_TOP|rx_data|rd_ptr [0] & ((\A_SPW_TOP|rx_data|mem[21][0]~q ))))) # (\A_SPW_TOP|rx_data|rd_ptr [5] & (\A_SPW_TOP|rx_data|rd_ptr [0])) ) ) ) # ( \A_SPW_TOP|rx_data|mem[52][0]~q  & ( !\A_SPW_TOP|rx_data|mem[53][0]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr 
// [5] & ((!\A_SPW_TOP|rx_data|rd_ptr [0] & (\A_SPW_TOP|rx_data|mem[20][0]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [0] & ((\A_SPW_TOP|rx_data|mem[21][0]~q ))))) # (\A_SPW_TOP|rx_data|rd_ptr [5] & (!\A_SPW_TOP|rx_data|rd_ptr [0])) ) ) ) # ( 
// !\A_SPW_TOP|rx_data|mem[52][0]~q  & ( !\A_SPW_TOP|rx_data|mem[53][0]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [5] & ((!\A_SPW_TOP|rx_data|rd_ptr [0] & (\A_SPW_TOP|rx_data|mem[20][0]~q )) # (\A_SPW_TOP|rx_data|rd_ptr [0] & ((\A_SPW_TOP|rx_data|mem[21][0]~q ))))) 
// ) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .datab(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .datac(!\A_SPW_TOP|rx_data|mem[20][0]~q ),
        .datad(!\A_SPW_TOP|rx_data|mem[21][0]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[52][0]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[53][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux17~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux17~6 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux17~6 .lut_mask = 64'h082A4C6E193B5D7F;
defparam \A_SPW_TOP|rx_data|Mux17~6 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y6_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux17~5 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux17~5_combout  = ( \A_SPW_TOP|rx_data|mem[49][0]~q  & ( \A_SPW_TOP|rx_data|mem[48][0]~q  & ( ((!\A_SPW_TOP|rx_data|rd_ptr [0] & ((\A_SPW_TOP|rx_data|mem[16][0]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [0] & (\A_SPW_TOP|rx_data|mem[17][0]~q 
// ))) # (\A_SPW_TOP|rx_data|rd_ptr [5]) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[49][0]~q  & ( \A_SPW_TOP|rx_data|mem[48][0]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & (((\A_SPW_TOP|rx_data|mem[16][0]~q ) # (\A_SPW_TOP|rx_data|rd_ptr [5])))) # 
// (\A_SPW_TOP|rx_data|rd_ptr [0] & (\A_SPW_TOP|rx_data|mem[17][0]~q  & (!\A_SPW_TOP|rx_data|rd_ptr [5]))) ) ) ) # ( \A_SPW_TOP|rx_data|mem[49][0]~q  & ( !\A_SPW_TOP|rx_data|mem[48][0]~q  & ( (!\A_SPW_TOP|rx_data|rd_ptr [0] & (((!\A_SPW_TOP|rx_data|rd_ptr 
// [5] & \A_SPW_TOP|rx_data|mem[16][0]~q )))) # (\A_SPW_TOP|rx_data|rd_ptr [0] & (((\A_SPW_TOP|rx_data|rd_ptr [5])) # (\A_SPW_TOP|rx_data|mem[17][0]~q ))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem[49][0]~q  & ( !\A_SPW_TOP|rx_data|mem[48][0]~q  & ( 
// (!\A_SPW_TOP|rx_data|rd_ptr [5] & ((!\A_SPW_TOP|rx_data|rd_ptr [0] & ((\A_SPW_TOP|rx_data|mem[16][0]~q ))) # (\A_SPW_TOP|rx_data|rd_ptr [0] & (\A_SPW_TOP|rx_data|mem[17][0]~q )))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|rd_ptr [0]),
        .datab(!\A_SPW_TOP|rx_data|mem[17][0]~q ),
        .datac(!\A_SPW_TOP|rx_data|rd_ptr [5]),
        .datad(!\A_SPW_TOP|rx_data|mem[16][0]~q ),
        .datae(!\A_SPW_TOP|rx_data|mem[49][0]~q ),
        .dataf(!\A_SPW_TOP|rx_data|mem[48][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux17~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux17~5 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux17~5 .lut_mask = 64'h10B015B51ABA1FBF;
defparam \A_SPW_TOP|rx_data|Mux17~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X43_Y6_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux17~9 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux17~9_combout  = ( \A_SPW_TOP|rx_data|Mux17~6_combout  & ( \A_SPW_TOP|rx_data|Mux17~5_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [1]) # ((!\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|Mux17~7_combout )) # 
// (\A_SPW_TOP|rx_data|rd_ptr [2] & ((\A_SPW_TOP|rx_data|Mux17~8_combout )))) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux17~6_combout  & ( \A_SPW_TOP|rx_data|Mux17~5_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & (((!\A_SPW_TOP|rx_data|rd_ptr [2])))) # 
// (\A_SPW_TOP|rx_data|rd_ptr [1] & ((!\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|Mux17~7_combout )) # (\A_SPW_TOP|rx_data|rd_ptr [2] & ((\A_SPW_TOP|rx_data|Mux17~8_combout ))))) ) ) ) # ( \A_SPW_TOP|rx_data|Mux17~6_combout  & ( 
// !\A_SPW_TOP|rx_data|Mux17~5_combout  & ( (!\A_SPW_TOP|rx_data|rd_ptr [1] & (((\A_SPW_TOP|rx_data|rd_ptr [2])))) # (\A_SPW_TOP|rx_data|rd_ptr [1] & ((!\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|Mux17~7_combout )) # (\A_SPW_TOP|rx_data|rd_ptr [2] & 
// ((\A_SPW_TOP|rx_data|Mux17~8_combout ))))) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux17~6_combout  & ( !\A_SPW_TOP|rx_data|Mux17~5_combout  & ( (\A_SPW_TOP|rx_data|rd_ptr [1] & ((!\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|Mux17~7_combout )) # 
// (\A_SPW_TOP|rx_data|rd_ptr [2] & ((\A_SPW_TOP|rx_data|Mux17~8_combout ))))) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux17~7_combout ),
        .datab(!\A_SPW_TOP|rx_data|rd_ptr [1]),
        .datac(!\A_SPW_TOP|rx_data|Mux17~8_combout ),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [2]),
        .datae(!\A_SPW_TOP|rx_data|Mux17~6_combout ),
        .dataf(!\A_SPW_TOP|rx_data|Mux17~5_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux17~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux17~9 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux17~9 .lut_mask = 64'h110311CFDD03DDCF;
defparam \A_SPW_TOP|rx_data|Mux17~9 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X42_Y5_N39
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Mux17~20 (
// Equation(s):
// \A_SPW_TOP|rx_data|Mux17~20_combout  = ( \A_SPW_TOP|rx_data|Mux17~9_combout  & ( \A_SPW_TOP|rx_data|rd_ptr [3] & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & ((\A_SPW_TOP|rx_data|Mux17~14_combout ))) # (\A_SPW_TOP|rx_data|rd_ptr [4] & 
// (\A_SPW_TOP|rx_data|Mux17~19_combout )) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux17~9_combout  & ( \A_SPW_TOP|rx_data|rd_ptr [3] & ( (!\A_SPW_TOP|rx_data|rd_ptr [4] & ((\A_SPW_TOP|rx_data|Mux17~14_combout ))) # (\A_SPW_TOP|rx_data|rd_ptr [4] & 
// (\A_SPW_TOP|rx_data|Mux17~19_combout )) ) ) ) # ( \A_SPW_TOP|rx_data|Mux17~9_combout  & ( !\A_SPW_TOP|rx_data|rd_ptr [3] & ( (\A_SPW_TOP|rx_data|rd_ptr [4]) # (\A_SPW_TOP|rx_data|Mux17~4_combout ) ) ) ) # ( !\A_SPW_TOP|rx_data|Mux17~9_combout  & ( 
// !\A_SPW_TOP|rx_data|rd_ptr [3] & ( (\A_SPW_TOP|rx_data|Mux17~4_combout  & !\A_SPW_TOP|rx_data|rd_ptr [4]) ) ) )

        .dataa(!\A_SPW_TOP|rx_data|Mux17~4_combout ),
        .datab(!\A_SPW_TOP|rx_data|Mux17~19_combout ),
        .datac(!\A_SPW_TOP|rx_data|Mux17~14_combout ),
        .datad(!\A_SPW_TOP|rx_data|rd_ptr [4]),
        .datae(!\A_SPW_TOP|rx_data|Mux17~9_combout ),
        .dataf(!\A_SPW_TOP|rx_data|rd_ptr [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|rx_data|Mux17~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Mux17~20 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Mux17~20 .lut_mask = 64'h550055FF0F330F33;
defparam \A_SPW_TOP|rx_data|Mux17~20 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y5_N1
dffeas \A_SPW_TOP|rx_data|data_out[0] (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|rx_data|Mux17~20_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|rx_data|data_out [0]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|data_out[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|data_out[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y16_N51
cyclonev_lcell_comb \u0|data_flag_rx|read_mux_out[0] (
// Equation(s):
// \u0|data_flag_rx|read_mux_out [0] = ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & ( (\A_SPW_TOP|rx_data|data_out [0] & 
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]) ) )

        .dataa(!\A_SPW_TOP|rx_data|data_out [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|data_flag_rx|read_mux_out [0]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|data_flag_rx|read_mux_out[0] .extended_lut = "off";
defparam \u0|data_flag_rx|read_mux_out[0] .lut_mask = 64'h5050000050500000;
defparam \u0|data_flag_rx|read_mux_out[0] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y16_N53
dffeas \u0|data_flag_rx|readdata[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|data_flag_rx|read_mux_out [0]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|data_flag_rx|readdata [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|data_flag_rx|readdata[0] .is_wysiwyg = "true";
defparam \u0|data_flag_rx|readdata[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X23_Y16_N50
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|data_flag_rx|readdata [0]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y30_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~0_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [0] & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1]) # 
// (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][0]~q ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [0] & ( (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][0]~q ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][0]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~0 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y30_N53
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y30_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~13 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~13_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [0] & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout  & 
// ((\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout ) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][0]~q ))) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [0] & ( 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout  & (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][0]~q  & !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][0]~q ),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~13 .lut_mask = 64'h0A000A000AAA0AAA;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y28_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_002|src_payload~14 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_002|src_payload~14_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] & ( \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_002|src_payload~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~14 .lut_mask = 64'h0000000000FF00FF;
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~14 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y28_N17
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_002|src_payload~14_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y28_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_002|src_payload~15 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_002|src_payload~15_combout  = ( \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_002|src_payload~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~15 .lut_mask = 64'h0000000000FF00FF;
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~15 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y28_N17
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_002|src_payload~15_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y28_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_002|src_payload~16 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_002|src_payload~16_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & ( \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_002|src_payload~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~16 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~16 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y28_N44
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_002|src_payload~16_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y28_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & ( 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2])) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((!\u0|mm_interconnect_0|cmd_mux_002|src_payload~15_combout  & \u0|mm_interconnect_0|cmd_mux_002|src_payload~16_combout )))) ) ) # 
// ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (!\u0|mm_interconnect_0|cmd_mux_002|src_payload~15_combout  & \u0|mm_interconnect_0|cmd_mux_002|src_payload~16_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_002|src_payload~15_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_002|src_payload~16_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .lut_mask = 64'h0050005088D888D8;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y28_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  
// & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]))) 
// # (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|cmd_mux_002|src_payload~14_combout )) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_002|src_payload~14_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .lut_mask = 64'h00000000FC0CFC0C;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y28_N55
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .power_up = "low";
// synopsys translate_on

// Location: FF_X14_Y28_N20
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y28_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & ( 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|cmd_mux_002|src_payload~16_combout  & !\u0|mm_interconnect_0|cmd_mux_002|src_payload~15_combout )) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2])) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((!\u0|mm_interconnect_0|cmd_mux_002|src_payload~16_combout  & !\u0|mm_interconnect_0|cmd_mux_002|src_payload~15_combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_002|src_payload~16_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_002|src_payload~15_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .lut_mask = 64'hD888D88850005000;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y28_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  
// & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]))) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|cmd_mux_002|src_payload~14_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_002|src_payload~14_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .lut_mask = 64'h0000000005AF05AF;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y28_N10
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y28_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & ( 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [1] & (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & !\u0|hps_0|fpga_interfaces|h2f_ARSIZE 
// [2]))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [1]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .lut_mask = 64'h0000000010001000;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y28_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  = ( 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]))) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|cmd_mux_002|src_payload~14_combout )) ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_002|src_payload~14_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .lut_mask = 64'hFFFFFFFF05AF05AF;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y28_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout  = ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .lut_mask = 64'hFFFFFFFF00000000;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y28_N29
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y28_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout  = SUM(( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg 
// [0] ) + ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) + ( !VCC ))
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14  = CARRY(( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] 
// ) + ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) + ( !VCC ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
        .cout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y28_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_002|src_payload~18 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_002|src_payload~18_combout  = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~2_combout  & ( \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_002|src_payload~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~18 .lut_mask = 64'h3333333300000000;
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~18 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y28_N53
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_002|src_payload~18_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y28_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0] = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  
// & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg 
// [0])) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|cmd_mux_002|src_payload~18_combout ))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_002|src_payload~18_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .lut_mask = 64'h00000000F3C0F3C0;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y28_N14
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y28_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  = ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( ((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout  & 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]))) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg 
// [0]) ) ) # ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// (((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [0] & \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1])))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [0]),
        .datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
        .datag(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .extended_lut = "on";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .lut_mask = 64'h37370000373700F0;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y28_N31
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y28_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout  = SUM(( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] 
// ) + ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 
//  ))
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10  = CARRY(( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + 
// ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14  ))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
        .cout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .lut_mask = 64'h0000CCCC00000F0F;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y28_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_002|src_payload~17 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_002|src_payload~17_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~1_combout  & ( \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_002|src_payload~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~17 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~17 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y28_N44
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_002|src_payload~17_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y28_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1] = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout  
// & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg 
// [1])) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|cmd_mux_002|src_payload~17_combout ))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_002|src_payload~17_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .lut_mask = 64'h00000000F3C0F3C0;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y28_N58
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y28_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout  = ( 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1] & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1] & ( ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout  & \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]))) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .lut_mask = 64'h555D555DDDDDDDDD;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y28_N55
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y28_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout  = SUM(( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] 
// ) + ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 
//  ))
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6  = CARRY(( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + 
// ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10  ))

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
        .cout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .lut_mask = 64'h0000AAAA00000F0F;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y28_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_002|src_payload~13 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_002|src_payload~13_combout  = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout  & ( \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_002|src_payload~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~13 .lut_mask = 64'h0F0F0F0F00000000;
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~13 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y28_N47
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_002|src_payload~13_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y28_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2] = ( \u0|mm_interconnect_0|cmd_mux_002|src_payload~13_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] & 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_002|src_payload~13_combout  & ( 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout  & ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg 
// [2]) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_002|src_payload~13_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .lut_mask = 64'h00F300F300C000C0;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y28_N17
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y28_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg 
// [2] & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( (\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [2]) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// (\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [2]) ) ) ) # ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] & ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ) ) ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg 
// [2] & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg 
// [2] ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [2]),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
        .datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .lut_mask = 64'h00FF33FF05050505;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y28_N40
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X48_Y3_N24
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|rx_tick_out~0 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|rx_tick_out~0_combout  = ( !\A_SPW_TOP|SPW|RX|ready_data_p_r~q  & ( \A_SPW_TOP|SPW|RX|last_is_timec~q  & ( (!\A_SPW_TOP|SPW|RX|ready_control_p_r~q  & (!\A_SPW_TOP|SPW|RX|ready_data~combout  & !\A_SPW_TOP|SPW|RX|always1~0_combout )) ) ) ) 
// # ( !\A_SPW_TOP|SPW|RX|ready_data_p_r~q  & ( !\A_SPW_TOP|SPW|RX|last_is_timec~q  & ( (!\A_SPW_TOP|SPW|RX|ready_control_p_r~q  & (!\A_SPW_TOP|SPW|RX|ready_data~combout  & (\A_SPW_TOP|SPW|RX|rx_tick_out~q  & !\A_SPW_TOP|SPW|RX|always1~0_combout ))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),
        .datab(!\A_SPW_TOP|SPW|RX|ready_data~combout ),
        .datac(!\A_SPW_TOP|SPW|RX|rx_tick_out~q ),
        .datad(!\A_SPW_TOP|SPW|RX|always1~0_combout ),
        .datae(!\A_SPW_TOP|SPW|RX|ready_data_p_r~q ),
        .dataf(!\A_SPW_TOP|SPW|RX|last_is_timec~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|rx_tick_out~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_tick_out~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|rx_tick_out~0 .lut_mask = 64'h0800000088000000;
defparam \A_SPW_TOP|SPW|RX|rx_tick_out~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y3_N33
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|rx_tick_out~feeder (
// Equation(s):
// \A_SPW_TOP|SPW|RX|rx_tick_out~feeder_combout  = ( \A_SPW_TOP|SPW|RX|rx_tick_out~0_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|rx_tick_out~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|rx_tick_out~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_tick_out~feeder .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|rx_tick_out~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|SPW|RX|rx_tick_out~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y3_N35
dffeas \A_SPW_TOP|SPW|RX|rx_tick_out (
        .clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(\A_SPW_TOP|SPW|RX|rx_tick_out~feeder_combout ),
        .asdata(vcc),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|rx_tick_out~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_tick_out .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|rx_tick_out .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y28_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_002|src_payload~12 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_002|src_payload~12_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout  & ( \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_002|src_payload~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~12 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~12 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y28_N50
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_002|src_payload~12_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .power_up = "low";
// synopsys translate_on

// Location: FF_X14_Y28_N37
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y28_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  
// & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((\u0|mm_interconnect_0|cmd_mux_002|src_payload~14_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_002|src_payload~14_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .lut_mask = 64'h0000000053535353;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y28_N31
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y28_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout  = SUM(( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3] 
// ) + ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3] ) + ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6  
// ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .lut_mask = 64'h0000FF0000000F0F;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y28_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3] = ( \u0|mm_interconnect_0|cmd_mux_002|src_payload~12_combout  & ( 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout  & (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3])) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_002|src_payload~12_combout  & ( 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout  & ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg 
// [3]) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_002|src_payload~12_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .lut_mask = 64'h5151515140404040;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y28_N26
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y28_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [3] & ( \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & ( 
// (((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3] & \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout )) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]) ) 
// ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [3] & ( \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3] & \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout )) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]))) ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [3] & ( !\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & ( 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3] & 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout )) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]))) ) ) 
// ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [3] & ( !\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3] & \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout )) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]))) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [3]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .lut_mask = 64'h1F001F001F001FFF;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y28_N22
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y27_N0
cyclonev_lcell_comb \u0|timecode_ready_rx|read_mux_out (
// Equation(s):
// \u0|timecode_ready_rx|read_mux_out~combout  = ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & \A_SPW_TOP|SPW|RX|rx_tick_out~q ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datad(!\A_SPW_TOP|SPW|RX|rx_tick_out~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|timecode_ready_rx|read_mux_out~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|timecode_ready_rx|read_mux_out .extended_lut = "off";
defparam \u0|timecode_ready_rx|read_mux_out .lut_mask = 64'h00F000F000000000;
defparam \u0|timecode_ready_rx|read_mux_out .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y27_N1
dffeas \u0|timecode_ready_rx|readdata[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|timecode_ready_rx|read_mux_out~combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|timecode_ready_rx|readdata [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|timecode_ready_rx|readdata[0] .is_wysiwyg = "true";
defparam \u0|timecode_ready_rx|readdata[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X19_Y27_N17
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|av_readdata_pre[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|timecode_ready_rx|readdata [0]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|av_readdata_pre [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|av_readdata_pre[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|av_readdata_pre[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X19_Y27_N23
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem[1][0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem[1][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem[1][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem[1][0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y27_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem~0_combout  = (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [1] & (\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|av_readdata_pre [0])) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [1] & ((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem[1][0]~q )))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|av_readdata_pre [0]),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem[1][0]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem~0 .lut_mask = 64'h0C3F0C3F0C3F0C3F;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y27_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|always0~0_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|read~0_combout  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0] )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|read~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|always0~0 .lut_mask = 64'hFFFFFFFF0F0F0F0F;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y27_N50
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem[0][0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem[0][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem[0][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem[0][0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y27_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~17 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~17_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q  & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0] & ( 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem[0][0]~q  ) ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q  & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0] & ( 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem[0][0]~q  ) ) ) # ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q  & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0] & ( 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0] & (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem[0][0]~q  & (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0]))) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0] & (((\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|av_readdata_pre [0])))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q  & ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|av_readdata_pre [0] & \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem[0][0]~q ),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0]),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|av_readdata_pre [0]),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]),
        .datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q ),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~17 .lut_mask = 64'h000F110F55555555;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~17 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y17_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|src_payload~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|src_payload~0_combout  = ( \u0|mm_interconnect_0|cmd_mux|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_WDATA [0] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_WDATA [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux|src_payload~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|src_payload~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|src_payload~0 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux|src_payload~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y17_N47
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux|src_payload~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X25_Y17_N32
dffeas \u0|led_pio_test|data_out[0]~_Duplicate_1 (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [0]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|led_pio_test|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|led_pio_test|data_out[0]~_Duplicate_1_q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|led_pio_test|data_out[0]~_Duplicate_1 .is_wysiwyg = "true";
defparam \u0|led_pio_test|data_out[0]~_Duplicate_1 .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y17_N3
cyclonev_lcell_comb \u0|led_pio_test|readdata[0] (
// Equation(s):
// \u0|led_pio_test|readdata [0] = ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( \u0|led_pio_test|data_out[0]~_Duplicate_1_q  ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|led_pio_test|data_out[0]~_Duplicate_1_q ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|led_pio_test|readdata [0]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|led_pio_test|readdata[0] .extended_lut = "off";
defparam \u0|led_pio_test|readdata[0] .lut_mask = 64'h0F0F000000000000;
defparam \u0|led_pio_test|readdata[0] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y17_N5
dffeas \u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|led_pio_test|readdata [0]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X25_Y17_N29
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y17_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~0_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][0]~q  ) ) # ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre [0] ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre [0]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][0]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~0 .lut_mask = 64'h5555555500FF00FF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y17_N11
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y17_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~15 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~15_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][0]~q  ) ) # ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg [0] & ((\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][0]~q ))) # 
// (\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg [0] & (\u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre [0])) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre [0]),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][0]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~15 .lut_mask = 64'h05AF05AF00FF00FF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~15 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y2_N15
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|timecode~1 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|timecode~1_combout  = ( \A_SPW_TOP|SPW|RX|dta_timec_p [0] & ( (\A_SPW_TOP|SPW|RX|timecode [0]) # (\A_SPW_TOP|SPW|RX|timecode~0_combout ) ) ) # ( !\A_SPW_TOP|SPW|RX|dta_timec_p [0] & ( (!\A_SPW_TOP|SPW|RX|timecode~0_combout  & 
// \A_SPW_TOP|SPW|RX|timecode [0]) ) )

        .dataa(!\A_SPW_TOP|SPW|RX|timecode~0_combout ),
        .datab(gnd),
        .datac(!\A_SPW_TOP|SPW|RX|timecode [0]),
        .datad(gnd),
        .datae(!\A_SPW_TOP|SPW|RX|dta_timec_p [0]),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|timecode~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|timecode~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|timecode~1 .lut_mask = 64'h0A0A5F5F0A0A5F5F;
defparam \A_SPW_TOP|SPW|RX|timecode~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X48_Y2_N6
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|timecode[0]~feeder (
// Equation(s):
// \A_SPW_TOP|SPW|RX|timecode[0]~feeder_combout  = ( \A_SPW_TOP|SPW|RX|timecode~1_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|RX|timecode~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|RX|timecode[0]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|timecode[0]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|timecode[0]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|SPW|RX|timecode[0]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X48_Y2_N8
dffeas \A_SPW_TOP|SPW|RX|timecode[0] (
        .clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
        .d(\A_SPW_TOP|SPW|RX|timecode[0]~feeder_combout ),
        .asdata(vcc),
        .clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(!\A_SPW_TOP|SPW|RX|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|RX|timecode [0]),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|timecode[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|timecode[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y14_N12
cyclonev_lcell_comb \u0|timecode_rx|read_mux_out[0] (
// Equation(s):
// \u0|timecode_rx|read_mux_out [0] = ( \A_SPW_TOP|SPW|RX|timecode [0] & ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datad(gnd),
        .datae(!\A_SPW_TOP|SPW|RX|timecode [0]),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|timecode_rx|read_mux_out [0]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|timecode_rx|read_mux_out[0] .extended_lut = "off";
defparam \u0|timecode_rx|read_mux_out[0] .lut_mask = 64'h0000F0F000000000;
defparam \u0|timecode_rx|read_mux_out[0] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y14_N13
dffeas \u0|timecode_rx|readdata[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|timecode_rx|read_mux_out [0]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|timecode_rx|readdata [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|timecode_rx|readdata[0] .is_wysiwyg = "true";
defparam \u0|timecode_rx|readdata[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X11_Y21_N32
dffeas \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|timecode_rx|readdata [0]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X11_Y21_N35
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y21_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~0_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][0]~q  & ( (\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [0]) # 
// (\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][0]~q  & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [0]) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [0]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][0]~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~0 .lut_mask = 64'h0A0A5F5F0A0A5F5F;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y21_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][0]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][0]~feeder_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~0_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][0]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][0]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][0]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][0]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y21_N38
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][0]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y21_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~16 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~16_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][0]~q  & ( \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0] & ( 
// (\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [0]) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0]) ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][0]~q  & ( 
// \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0] & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0] & \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [0]) ) ) ) # ( 
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][0]~q  & ( !\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0]),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [0]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][0]~q ),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~16 .lut_mask = 64'h0000FFFF0C0C3F3F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~16 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y27_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~18 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~18_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout  & ( \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~16_combout  & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~17_combout  & 
// \u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ) ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout  & ( \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~16_combout  & ( 
// (!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~17_combout  & (\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout  & ((!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~15_combout ) # (\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout )))) ) ) ) 
// # ( \u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout  & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~16_combout  & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~17_combout  ) ) ) # ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout  & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~16_combout  & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~17_combout  & ((!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~15_combout ) # 
// (\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ),
        .datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~17_combout ),
        .datac(!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~15_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ),
        .datae(!\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ),
        .dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~16_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~18 .lut_mask = 64'hC4C4CCCC00C400CC;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~18 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X9_Y32_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_005|src_payload~12 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_005|src_payload~12_combout  = ( \u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_005|src_payload~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~12 .lut_mask = 64'h000000000000FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~12 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X9_Y32_N32
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_005|src_payload~12_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X9_Y32_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3] = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout  & 
// ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg 
// [3]))) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|cmd_mux_005|src_payload~12_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_005|src_payload~12_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .lut_mask = 64'h00000000CACACACA;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X9_Y32_N50
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .power_up = "low";
// synopsys translate_on

// Location: FF_X8_Y32_N49
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y32_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_005|src_payload~14 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_005|src_payload~14_combout  = ( \u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_005|src_payload~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~14 .lut_mask = 64'h000000000000FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~14 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X8_Y32_N56
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_005|src_payload~14_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y32_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_005|src_payload~16 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_005|src_payload~16_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & ( \u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_005|src_payload~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~16 .lut_mask = 64'h000000000000FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~16 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X9_Y32_N35
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_005|src_payload~16_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X9_Y32_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_005|src_payload~15 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_005|src_payload~15_combout  = ( \u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_005|src_payload~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~15 .lut_mask = 64'h000000000000FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~15 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X9_Y32_N41
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_005|src_payload~15_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X9_Y32_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & 
// ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|cmd_mux_005|src_payload~15_combout  & \u0|mm_interconnect_0|cmd_mux_005|src_payload~16_combout )) ) ) # 
// ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1])) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((!\u0|mm_interconnect_0|cmd_mux_005|src_payload~15_combout  & \u0|mm_interconnect_0|cmd_mux_005|src_payload~16_combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_005|src_payload~15_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_005|src_payload~16_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .lut_mask = 64'h4474447400300030;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X8_Y32_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout  = ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q 
//  & (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ((\u0|mm_interconnect_0|cmd_mux_005|src_payload~14_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_005|src_payload~14_combout ),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .lut_mask = 64'h0000000055335533;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X8_Y32_N23
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X8_Y32_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_005|src_payload~13 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_005|src_payload~13_combout  = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout  & ( \u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_005|src_payload~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~13 .lut_mask = 64'h0F0F0F0F00000000;
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~13 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X8_Y32_N32
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_005|src_payload~13_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X8_Y32_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout  = ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q 
//  & (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  
// & ((!\u0|mm_interconnect_0|cmd_mux_005|src_payload~14_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_005|src_payload~14_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .lut_mask = 64'h00000000ACACACAC;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X8_Y32_N20
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X9_Y32_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_005|src_payload~17 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_005|src_payload~17_combout  = (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~1_combout  & \u0|mm_interconnect_0|cmd_mux_005|saved_grant [1])

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~1_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_005|src_payload~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~17 .lut_mask = 64'h000F000F000F000F;
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~17 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X9_Y32_N8
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_005|src_payload~17_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X9_Y32_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout  = ( !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [1] & 
// (\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] & (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]))) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [1]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .lut_mask = 64'h0100010000000000;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X9_Y32_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  = ( !\u0|mm_interconnect_0|cmd_mux_005|src_payload~16_combout  & ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// !\u0|mm_interconnect_0|cmd_mux_005|src_payload~15_combout ) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_005|src_payload~16_combout  & ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] 
// & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]) 
// ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_005|src_payload~16_combout  & ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & ( 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]))) 
// # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|cmd_mux_005|src_payload~15_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_005|src_payload~15_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .datae(!\u0|mm_interconnect_0|cmd_mux_005|src_payload~16_combout ),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .lut_mask = 64'hFA50AA0050500000;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X8_Y32_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  
// & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  & ( \u0|mm_interconnect_0|cmd_mux_005|src_payload~14_combout  ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  
// & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_005|src_payload~14_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .lut_mask = 64'h0000000000FF0F0F;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X8_Y32_N17
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X8_Y32_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  = ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q 
//  & ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]))) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  
// & (\u0|mm_interconnect_0|cmd_mux_005|src_payload~14_combout )) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_005|src_payload~14_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .lut_mask = 64'hFFFFFFFF1B1B1B1B;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X8_Y32_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout  = ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .lut_mask = 64'hFFFFFFFF00000000;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X8_Y32_N53
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X8_Y32_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout  = SUM(( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) + ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14  = CARRY(( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] 
// ) + ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
        .cout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .lut_mask = 64'h0000F0F000003333;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X9_Y32_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_005|src_payload~18 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_005|src_payload~18_combout  = ( \u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~2_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_005|src_payload~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~18 .lut_mask = 64'h0000FFFF00000000;
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~18 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X8_Y32_N5
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_005|src_payload~18_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X8_Y32_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0] = ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg 
// [0]))) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|cmd_mux_005|src_payload~18_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_005|src_payload~18_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .lut_mask = 64'h00000000E4E4E4E4;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X8_Y32_N37
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X8_Y32_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  = ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout  & 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]))) # 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]) ) ) # ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// (((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [0] & \u0|mm_interconnect_0|cmd_mux_005|saved_grant [1])))) ) 
// )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [0]),
        .datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
        .datag(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .extended_lut = "on";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .lut_mask = 64'h37370000373700F0;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X8_Y32_N25
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X8_Y32_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout  = SUM(( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly 
// [1] ) + ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14  ))
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10  = CARRY(( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] 
// ) + ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
        .cout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .lut_mask = 64'h0000FF0000000F0F;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X9_Y32_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1] = ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg 
// [1])) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|cmd_mux_005|src_payload~17_combout ))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_005|src_payload~17_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .lut_mask = 64'h00000000CCF0CCF0;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X9_Y32_N14
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X9_Y32_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout  = ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1] & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q 
// ) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1] & ( 
// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1] 
// & \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ))) # 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .lut_mask = 64'h0F2F0F2FAFAFAFAF;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X8_Y32_N13
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X8_Y32_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout  = SUM(( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly 
// [2] ) + ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10  ))
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6  = CARRY(( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] 
// ) + ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10  ))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
        .cout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .lut_mask = 64'h0000F0F000003333;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X8_Y32_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2] = ( \u0|mm_interconnect_0|cmd_mux_005|src_payload~13_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] 
// & \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_005|src_payload~13_combout  & ( 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout  & 
// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q 
// ))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_005|src_payload~13_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .lut_mask = 64'h00F500F500A000A0;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X8_Y32_N40
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X8_Y32_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout  = ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [2] & ( 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # (\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]) ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [2] & ( 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg 
// [2] & \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout )))) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q 
//  & (\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1])) ) ) ) # ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [2] & ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [2] & ( 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] & (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  
// & \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
        .datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .lut_mask = 64'h0030F0F00535F5F5;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X8_Y32_N44
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X8_Y32_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout  = SUM(( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3] ) + ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3] ) + ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X9_Y32_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] & ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout  & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]) # 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3])))) # 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [3])) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] & ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout  & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg 
// [3]))) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] & ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout  & ( 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg 
// [3]))) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [3])) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] & ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout  & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3] & 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [3]),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .lut_mask = 64'h0F000F553F003F55;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X9_Y32_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3]~feeder_combout  = ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X9_Y32_N4
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .power_up = "low";
// synopsys translate_on

// Location: FF_X9_Y32_N43
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y32_N48
cyclonev_lcell_comb \u0|fifo_full_rx_status|read_mux_out (
// Equation(s):
// \u0|fifo_full_rx_status|read_mux_out~combout  = ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & ( \A_SPW_TOP|rx_data|f_full~q  & ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .dataf(!\A_SPW_TOP|rx_data|f_full~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|fifo_full_rx_status|read_mux_out~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|fifo_full_rx_status|read_mux_out .extended_lut = "off";
defparam \u0|fifo_full_rx_status|read_mux_out .lut_mask = 64'h00000000FF000000;
defparam \u0|fifo_full_rx_status|read_mux_out .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y32_N49
dffeas \u0|fifo_full_rx_status|readdata[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|fifo_full_rx_status|read_mux_out~combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|fifo_full_rx_status|readdata [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|fifo_full_rx_status|readdata[0] .is_wysiwyg = "true";
defparam \u0|fifo_full_rx_status|readdata[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X6_Y31_N32
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|av_readdata_pre[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|fifo_full_rx_status|readdata [0]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|av_readdata_pre [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|av_readdata_pre[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|av_readdata_pre[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X6_Y31_N38
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X6_Y31_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem~0_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][0]~q  & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|av_readdata_pre [0]) # 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][0]~q  & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|av_readdata_pre [0]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [1]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|av_readdata_pre [0]),
        .datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][0]~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem~0 .lut_mask = 64'h00CC33FF00CC33FF;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X6_Y31_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|always0~0_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|read~0_combout  ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|read~0_combout  & ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0] ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|read~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|always0~0 .lut_mask = 64'hAAAAAAAAFFFFFFFF;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X6_Y31_N55
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X6_Y31_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~20 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~20_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0] & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][129]~q  & ( 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg [0] & (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][0]~q )) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg [0] & 
// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0] & ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|av_readdata_pre [0]))) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0] & 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][0]~q )))) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0] & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][129]~q  & ( 
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0] & (\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg [0] & ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|av_readdata_pre [0])))) # 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0] & (((\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][0]~q )))) ) ) ) # ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0] & ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][129]~q  & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0] & (\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg [0] & 
// ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|av_readdata_pre [0])))) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0] & (((\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][0]~q )))) ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0] & ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][129]~q  & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0] & 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg [0] & ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|av_readdata_pre [0])))) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0] & 
// (((\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][0]~q )))) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg [0]),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][0]~q ),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|av_readdata_pre [0]),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0]),
        .datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0]),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~20 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~20 .lut_mask = 64'h0533053305332733;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~20 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y29_N53
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem[1][0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem[1][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem[1][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem[1][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y29_N48
cyclonev_lcell_comb \u0|data_read_en_rx|readdata[0]~0 (
// Equation(s):
// \u0|data_read_en_rx|readdata[0]~0_combout  = ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & ( (\u0|data_read_en_rx|data_out~q  & 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|data_read_en_rx|data_out~q ),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|data_read_en_rx|readdata[0]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|data_read_en_rx|readdata[0]~0 .extended_lut = "off";
defparam \u0|data_read_en_rx|readdata[0]~0 .lut_mask = 64'h0F000F0000000000;
defparam \u0|data_read_en_rx|readdata[0]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y29_N50
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_translator|av_readdata_pre[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|data_read_en_rx|readdata[0]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_translator|av_readdata_pre [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|av_readdata_pre[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|av_readdata_pre[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y29_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem~0_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_translator|av_readdata_pre [0] & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [1]) # 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem[1][0]~q ) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_translator|av_readdata_pre [0] & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem[1][0]~q ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem[1][0]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|av_readdata_pre [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem~0 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y29_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem[0][0]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem[0][0]~feeder_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem~0_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem[0][0]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem[0][0]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem[0][0]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem[0][0]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y29_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|always0~0_combout  = ( \u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [0]) # 
// ((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~0_combout  & ((!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ) # (\u0|hps_0|fpga_interfaces|h2f_BREADY [0])))) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ( 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [0]) # ((\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout  & (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~0_combout  & \u0|hps_0|fpga_interfaces|h2f_BREADY 
// [0]))) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [0]),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~0_combout ),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_BREADY [0]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|always0~0 .lut_mask = 64'hCCDCCCDCECFCECFC;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y29_N35
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem[0][0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem[0][0]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem[0][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem[0][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem[0][0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y29_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~19 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~19_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|data_read_en_rx_s1_translator|av_readdata_pre [0] & ( 
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem[0][0]~q  ) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|data_read_en_rx_s1_translator|av_readdata_pre [0] & ( 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg [0]) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem[0][0]~q ) ) ) ) # ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [0] & ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_translator|av_readdata_pre [0] & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem[0][0]~q  ) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [0] & ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_translator|av_readdata_pre [0] & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem[0][0]~q  & !\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg [0]) ) ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem[0][0]~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg [0]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [0]),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|av_readdata_pre [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~19 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~19 .lut_mask = 64'h505055555F5F5555;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~19 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X10_Y33_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_012|src_payload~14 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_012|src_payload~14_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] & ( \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_012|src_payload~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~14 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~14 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y33_N50
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_012|src_payload~14_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y32_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_012|src_payload~16 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_012|src_payload~16_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & ( \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_012|src_payload~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~16 .lut_mask = 64'h000000000000FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~16 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y32_N23
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_012|src_payload~16_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y32_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_012|src_payload~15 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_012|src_payload~15_combout  = ( \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_012|src_payload~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~15 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~15 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y32_N32
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_012|src_payload~15_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y32_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_012|src_payload~16_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]))) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((!\u0|mm_interconnect_0|cmd_mux_012|src_payload~15_combout )))) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_012|src_payload~16_combout  & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg 
// [1] & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q 
// )) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_012|src_payload~15_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_012|src_payload~16_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .lut_mask = 64'h404040404F404F40;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X10_Y33_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout  = ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q 
//  & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]))) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q 
//  & (!\u0|mm_interconnect_0|cmd_mux_012|src_payload~14_combout )) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_012|src_payload~14_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .lut_mask = 64'h00000000F0CCF0CC;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y33_N20
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .power_up = "low";
// synopsys translate_on

// Location: FF_X10_Y33_N26
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y32_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & 
// ( (!\u0|mm_interconnect_0|cmd_mux_012|src_payload~16_combout  & (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & !\u0|mm_interconnect_0|cmd_mux_012|src_payload~15_combout )) ) ) 
// # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  
// & (((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1])))) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|cmd_mux_012|src_payload~16_combout  & ((!\u0|mm_interconnect_0|cmd_mux_012|src_payload~15_combout )))) ) 
// )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_012|src_payload~16_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_012|src_payload~15_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .lut_mask = 64'hE2C0E2C022002200;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X10_Y33_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout  = ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q 
//  & (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ((\u0|mm_interconnect_0|cmd_mux_012|src_payload~14_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_012|src_payload~14_combout ),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .lut_mask = 64'h0000000055335533;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y33_N47
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X9_Y33_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_012|src_payload~17 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_012|src_payload~17_combout  = ( \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~1_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_012|src_payload~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~17 .lut_mask = 64'h000000000000FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~17 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X9_Y33_N59
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_012|src_payload~17_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X9_Y33_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1] = ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg 
// [1])) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|cmd_mux_012|src_payload~17_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_012|src_payload~17_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .lut_mask = 64'h00000000F5A0F5A0;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X9_Y33_N53
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X9_Y33_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout  = ( !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [1] & 
// \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1])) ) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [1]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .lut_mask = 64'h00000000000A0000;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X10_Y33_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  = ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q 
//  & ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]))) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  
// & (\u0|mm_interconnect_0|cmd_mux_012|src_payload~14_combout )) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_012|src_payload~14_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .lut_mask = 64'hFFFFFFFF0F330F33;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X10_Y33_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout  = ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .lut_mask = 64'hFFFFFFFF00000000;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y33_N5
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y33_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout  = SUM(( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) + ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14  = CARRY(( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] 
// ) + ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
        .cout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .lut_mask = 64'h0000F0F000003333;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X10_Y33_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_012|src_payload~18 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_012|src_payload~18_combout  = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~2_combout  & ( \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_012|src_payload~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~18 .lut_mask = 64'h5555555500000000;
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~18 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y33_N53
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_012|src_payload~18_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y33_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0] = 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  & 
// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg 
// [0])) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|cmd_mux_012|src_payload~18_combout )))))

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_012|src_payload~18_combout ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .lut_mask = 64'h3120312031203120;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y33_N8
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y33_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  = ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( (((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout  & 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]))) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0])) ) ) # ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [0] & 
// (((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  & ((\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1])))))) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [0]),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
        .datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
        .datag(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .extended_lut = "on";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .lut_mask = 64'h03FF000003FF5050;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y33_N13
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y33_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout  = SUM(( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly 
// [1] ) + ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14  ))
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10  = CARRY(( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] 
// ) + ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
        .cout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X9_Y33_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout  = ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout  & ( ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg 
// [1])))) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout  & ( ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1])) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .lut_mask = 64'h0AFF0AFF2AFF2AFF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X9_Y33_N49
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y33_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout  = SUM(( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10  ))
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6  = CARRY(( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg 
// [2] ) + ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
        .cout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .lut_mask = 64'h0000FF0000000F0F;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X9_Y33_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_012|src_payload~13 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_012|src_payload~13_combout  = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout  & ( \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_012|src_payload~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~13 .lut_mask = 64'h5555000055550000;
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~13 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X9_Y33_N41
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_012|src_payload~13_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y33_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2] = ( \u0|mm_interconnect_0|cmd_mux_012|src_payload~13_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout  & 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2])) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_012|src_payload~13_combout  & ( 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout  & 
// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q 
// ))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_012|src_payload~13_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .lut_mask = 64'h3131313120202020;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y33_N1
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y33_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout  = ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg 
// [2] & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # ((\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [2])) ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg 
// [2] & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout )))) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [2]))) ) ) ) # ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q 
// ) # ((\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [2])) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] & ( (\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [2] & 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [2]),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
        .datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .lut_mask = 64'h0101F1F101F1F1F1;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y33_N28
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y33_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout  = ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q 
//  & (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ((\u0|mm_interconnect_0|cmd_mux_012|src_payload~14_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_012|src_payload~14_combout ),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .lut_mask = 64'h0000000055335533;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y33_N23
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .power_up = "low";
// synopsys translate_on

// Location: FF_X10_Y33_N56
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y33_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout  = SUM(( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly 
// [3] ) + ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3] ) + ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6  ))

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .lut_mask = 64'h0000AAAA000000FF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y32_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_012|src_payload~12 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_012|src_payload~12_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout  & ( \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_012|src_payload~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~12 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~12 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y32_N41
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_012|src_payload~12_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y33_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3] = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3] & ( 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|cmd_mux_012|src_payload~12_combout  & 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout )) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3] & ( 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout  & 
// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # (!\u0|mm_interconnect_0|cmd_mux_012|src_payload~12_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_012|src_payload~12_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .lut_mask = 64'h00FA00FA00500050;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y33_N10
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y33_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout  = ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3] & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg 
// [3] & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # ((\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [3])) ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3] & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg 
// [3] & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout )))) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & ((\u0|hps_0|fpga_interfaces|h2f_ARADDR [3])))) ) ) ) # ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3] & ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3] & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q 
// ) # ((\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [3])) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3] & ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3] & ( (\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & \u0|hps_0|fpga_interfaces|h2f_ARADDR [3])) ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [3]),
        .datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .lut_mask = 64'h0005F0F53035F0F5;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y33_N58
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y33_N3
cyclonev_lcell_comb \u0|fifo_full_tx_status|read_mux_out (
// Equation(s):
// \u0|fifo_full_tx_status|read_mux_out~combout  = ( \A_SPW_TOP|tx_data|f_full~q  & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\A_SPW_TOP|tx_data|f_full~q ),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|fifo_full_tx_status|read_mux_out~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|fifo_full_tx_status|read_mux_out .extended_lut = "off";
defparam \u0|fifo_full_tx_status|read_mux_out .lut_mask = 64'h0000AAAA00000000;
defparam \u0|fifo_full_tx_status|read_mux_out .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y33_N4
dffeas \u0|fifo_full_tx_status|readdata[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|fifo_full_tx_status|read_mux_out~combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|fifo_full_tx_status|readdata [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|fifo_full_tx_status|readdata[0] .is_wysiwyg = "true";
defparam \u0|fifo_full_tx_status|readdata[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X15_Y31_N32
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|av_readdata_pre[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|fifo_full_tx_status|readdata [0]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|av_readdata_pre [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|av_readdata_pre[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|av_readdata_pre[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X15_Y31_N35
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y31_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem~0_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][0]~q  ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|av_readdata_pre [0] ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|av_readdata_pre [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][0]~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem~0 .lut_mask = 64'h555555550F0F0F0F;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y31_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][0]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][0]~feeder_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem~0_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][0]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][0]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][0]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][0]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y31_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|always0~0_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|read~0_combout  ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|read~0_combout  & ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0]),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|read~0_combout ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|always0~0 .lut_mask = 64'hCCCCFFFFCCCCFFFF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y31_N26
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][0]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y31_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~22 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~22_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][0]~q  ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][0]~q  & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0] & 
// (((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][129]~q  & \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0])))) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0] & 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|av_readdata_pre [0])) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0] & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][0]~q  & ( 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|av_readdata_pre [0] & \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0]) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|av_readdata_pre [0]),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0]),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0]),
        .datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0]),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~22_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~22 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~22 .lut_mask = 64'h11110000111DFFFF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~22 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X10_Y35_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_006|src_payload~14 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_006|src_payload~14_combout  = ( \u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_006|src_payload~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~14 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~14 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y35_N35
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_006|src_payload~14_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y35_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_006|src_payload~16 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_006|src_payload~16_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & ( \u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_006|src_payload~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~16 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~16 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y35_N44
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_006|src_payload~16_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y35_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_006|src_payload~15 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_006|src_payload~15_combout  = ( \u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_006|src_payload~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~15 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~15 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y35_N59
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_006|src_payload~15_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y35_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_006|src_payload~16_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]))) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  
// & (((!\u0|mm_interconnect_0|cmd_mux_006|src_payload~15_combout )))) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_006|src_payload~16_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2])) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_006|src_payload~15_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_006|src_payload~16_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .lut_mask = 64'h2020202075207520;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X10_Y35_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout  = ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((\u0|mm_interconnect_0|cmd_mux_006|src_payload~14_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_006|src_payload~14_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .lut_mask = 64'h00000000550F550F;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y35_N41
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .power_up = "low";
// synopsys translate_on

// Location: FF_X9_Y35_N55
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X9_Y35_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_006|src_payload~13 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_006|src_payload~13_combout  = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout  & ( \u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_006|src_payload~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~13 .lut_mask = 64'h0F0F0F0F00000000;
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~13 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X9_Y35_N26
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_006|src_payload~13_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y35_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout  = ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) 
// # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|cmd_mux_006|src_payload~14_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_006|src_payload~14_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .lut_mask = 64'h00000000F5A0F5A0;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y35_N1
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X9_Y35_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_006|src_payload~17 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_006|src_payload~17_combout  = (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~1_combout  & \u0|mm_interconnect_0|cmd_mux_006|saved_grant [1])

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~1_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_006|src_payload~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~17 .lut_mask = 64'h000F000F000F000F;
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~17 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X9_Y35_N29
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_006|src_payload~17_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y35_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout  = ( !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & ( 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [1] & 
// !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [1]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .lut_mask = 64'h0100010000000000;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X10_Y35_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] 
// & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & ( (!\u0|mm_interconnect_0|cmd_mux_006|src_payload~15_combout  & (!\u0|mm_interconnect_0|cmd_mux_006|src_payload~16_combout  & 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg 
// [2] & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & ( (!\u0|mm_interconnect_0|cmd_mux_006|src_payload~15_combout  & (!\u0|mm_interconnect_0|cmd_mux_006|src_payload~16_combout 
//  & \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) ) # ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & ( 
// (!\u0|mm_interconnect_0|cmd_mux_006|src_payload~15_combout  & (!\u0|mm_interconnect_0|cmd_mux_006|src_payload~16_combout  & \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) ) 
// # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] 
// & ( (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # ((!\u0|mm_interconnect_0|cmd_mux_006|src_payload~15_combout  & !\u0|mm_interconnect_0|cmd_mux_006|src_payload~16_combout 
// )) ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_006|src_payload~15_combout ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_006|src_payload~16_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .lut_mask = 64'hF8F8080808080808;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X10_Y35_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout  = ( \u0|mm_interconnect_0|cmd_mux_006|src_payload~14_combout  & ( 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  & 
// ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]))) 
// ) ) # ( !\u0|mm_interconnect_0|cmd_mux_006|src_payload~14_combout  & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] & 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  & !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q 
// )) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_006|src_payload~14_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .lut_mask = 64'h1100110011331133;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y35_N29
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y35_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  = 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ) # 
// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) 
// # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((\u0|mm_interconnect_0|cmd_mux_006|src_payload~14_combout ))))

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_006|src_payload~14_combout ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .lut_mask = 64'hDCDFDCDFDCDFDCDF;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X10_Y35_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout  = ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .lut_mask = 64'hFFFFFFFF00000000;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y35_N7
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X9_Y35_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout  = SUM(( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) + ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14  = CARRY(( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly 
// [0] ) + ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
        .cout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X9_Y35_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_006|src_payload~18 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_006|src_payload~18_combout  = ( \u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~2_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~2_combout ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_006|src_payload~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~18 .lut_mask = 64'h0000F0F00000F0F0;
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~18 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X9_Y35_N17
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_006|src_payload~18_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X9_Y35_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0] = ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg 
// [0]))) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|cmd_mux_006|src_payload~18_combout )) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_006|src_payload~18_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .lut_mask = 64'h00000000F0CCF0CC;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X9_Y35_N34
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X9_Y35_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  = ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout  & 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]))) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]) ) ) # ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// (((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [0] & \u0|mm_interconnect_0|cmd_mux_006|saved_grant [1])))) ) 
// )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [0]),
        .datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
        .datag(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .extended_lut = "on";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .lut_mask = 64'h37370000373700F0;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X9_Y35_N43
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X9_Y35_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout  = SUM(( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14  
// ))
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10  = CARRY(( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14  
// ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
        .cout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X9_Y35_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1] = ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg 
// [1]))) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|cmd_mux_006|src_payload~17_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_006|src_payload~17_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .lut_mask = 64'h00000000F0AAF0AA;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X9_Y35_N32
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X9_Y35_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout  = ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1] & ( 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1] & ( 
// ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1] & 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ))) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .lut_mask = 64'h0F4F0F4FCFCFCFCF;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X9_Y35_N40
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X9_Y35_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout  = SUM(( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 
//  ))
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6  = CARRY(( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly 
// [2] ) + ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10  ))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
        .cout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .lut_mask = 64'h0000F0F000003333;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X9_Y35_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2] = (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout  & 
// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg 
// [2]))) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|cmd_mux_006|src_payload~13_combout ))))

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_006|src_payload~13_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .lut_mask = 64'h5044504450445044;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X9_Y35_N37
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X9_Y35_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout  = ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  
// & ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [2] & \u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]) ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [2] & \u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]) ) ) ) # ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q 
//  ) ) # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg 
// [2] & \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [2]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
        .datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .lut_mask = 64'h1111FFFF000F000F;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X9_Y35_N19
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X9_Y35_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout  = SUM(( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3] ) + ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3] ) + ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6  
// ))

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .lut_mask = 64'h0000AAAA00000F0F;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X9_Y35_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_006|src_payload~12 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_006|src_payload~12_combout  = ( \u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_006|src_payload~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~12 .lut_mask = 64'h0000000000FF00FF;
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~12 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X9_Y35_N14
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_006|src_payload~12_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X9_Y35_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3] = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout  & !\u0|mm_interconnect_0|cmd_mux_006|src_payload~12_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout  & 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|cmd_mux_006|src_payload~12_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .lut_mask = 64'h4444444455005500;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X9_Y35_N53
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X9_Y35_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [3] ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout  & 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3])) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout  & 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3])) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]) ) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [3]),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .datae(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .lut_mask = 64'h0F3F0F3F00005555;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X9_Y35_N58
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .power_up = "low";
// synopsys translate_on

// Location: FF_X9_Y35_N22
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y31_N45
cyclonev_lcell_comb \u0|fifo_empty_rx_status|read_mux_out (
// Equation(s):
// \u0|fifo_empty_rx_status|read_mux_out~combout  = ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & ( 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & \A_SPW_TOP|rx_data|f_empty~q ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datab(gnd),
        .datac(!\A_SPW_TOP|rx_data|f_empty~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|fifo_empty_rx_status|read_mux_out~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|fifo_empty_rx_status|read_mux_out .extended_lut = "off";
defparam \u0|fifo_empty_rx_status|read_mux_out .lut_mask = 64'h0A0A0A0A00000000;
defparam \u0|fifo_empty_rx_status|read_mux_out .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y31_N47
dffeas \u0|fifo_empty_rx_status|readdata[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|fifo_empty_rx_status|read_mux_out~combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|fifo_empty_rx_status|readdata [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|fifo_empty_rx_status|readdata[0] .is_wysiwyg = "true";
defparam \u0|fifo_empty_rx_status|readdata[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X10_Y31_N46
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|av_readdata_pre[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|fifo_empty_rx_status|readdata [0]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|av_readdata_pre [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|av_readdata_pre[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|av_readdata_pre[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X13_Y33_N59
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y33_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem~0_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][0]~q  ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|av_readdata_pre [0] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|av_readdata_pre [0]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][0]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem~0 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y35_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|always0~0_combout  = (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|read~0_combout )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|read~0_combout ),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|always0~0 .lut_mask = 64'hFF55FF55FF55FF55;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y33_N20
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y33_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~21 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~21_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][0]~q  ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][0]~q  & ( (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0] & 
// (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q  & \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0])))) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0] & 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|av_readdata_pre [0])) ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0] & ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][0]~q  & ( 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0] & \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|av_readdata_pre [0]) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|av_readdata_pre [0]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]),
        .datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~21_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~21 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~21 .lut_mask = 64'h11110000111BFFFF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~21 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y29_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~23 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~23_combout  = ( \u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout  & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~21_combout  & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~20_combout  & 
// !\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~22_combout ) ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout  & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~21_combout  & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~20_combout  
// & (!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~22_combout  & ((!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~19_combout ) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout )))) ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~20_combout ),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ),
        .datac(!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~19_combout ),
        .datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~22_combout ),
        .datae(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ),
        .dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~21_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~23_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~23 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~23 .lut_mask = 64'hA200AA0000000000;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~23 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y36_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_016|src_payload~13 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_016|src_payload~13_combout  = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout  & ( \u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_016|src_payload~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~13 .lut_mask = 64'h0F0F0F0F00000000;
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~13 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y36_N50
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_016|src_payload~13_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y36_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_016|src_payload~14 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_016|src_payload~14_combout  = ( \u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_016|src_payload~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~14 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~14 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y36_N50
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_016|src_payload~14_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y36_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_016|src_payload~15 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_016|src_payload~15_combout  = ( \u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] ) )

        .dataa(gnd),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_016|src_payload~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~15 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~15 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y36_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_016|src_payload~16 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_016|src_payload~16_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & ( \u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_016|src_payload~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~16 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~16 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y36_N32
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_016|src_payload~16_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X17_Y36_N44
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_016|src_payload~15_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y36_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & ( 
// (!\u0|mm_interconnect_0|cmd_mux_016|src_payload~15_combout  & (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & \u0|mm_interconnect_0|cmd_mux_016|src_payload~16_combout )) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1])))) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (!\u0|mm_interconnect_0|cmd_mux_016|src_payload~15_combout  & ((\u0|mm_interconnect_0|cmd_mux_016|src_payload~16_combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_016|src_payload~15_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_016|src_payload~16_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .lut_mask = 64'h303A303A000A000A;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y36_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  
// & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) # 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|cmd_mux_016|src_payload~14_combout ))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_016|src_payload~14_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .lut_mask = 64'h00000000CFC0CFC0;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y36_N43
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .power_up = "low";
// synopsys translate_on

// Location: FF_X21_Y36_N1
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y36_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_016|src_payload~17 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_016|src_payload~17_combout  = (\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~1_combout )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~1_combout ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_016|src_payload~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~17 .lut_mask = 64'h000F000F000F000F;
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~17 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y36_N53
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_016|src_payload~17_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y36_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout  = ( 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [1] & (\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] & 
// (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]))) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [1]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .lut_mask = 64'h0000000010001000;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y36_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  = ( \u0|mm_interconnect_0|cmd_mux_016|src_payload~16_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1])) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_016|src_payload~16_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & 
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]))) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((!\u0|mm_interconnect_0|cmd_mux_016|src_payload~15_combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_016|src_payload~15_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_016|src_payload~16_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .lut_mask = 64'hD580D58080808080;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y36_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  
// & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) # 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((\u0|mm_interconnect_0|cmd_mux_016|src_payload~14_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_016|src_payload~14_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .lut_mask = 64'h000000000A5F0A5F;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y36_N37
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y36_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_016|src_payload~14_combout  & ( 
// ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) 
// # (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_016|src_payload~14_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ) # ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  
// & \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_016|src_payload~14_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .lut_mask = 64'hF0FAF0FAF5FFF5FF;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y36_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout  = 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout 

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .lut_mask = 64'hFF00FF00FF00FF00;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y36_N17
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y36_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_016|src_payload~18 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_016|src_payload~18_combout  = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~2_combout  & ( \u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_016|src_payload~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~18 .lut_mask = 64'h3333333300000000;
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~18 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y36_N44
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_016|src_payload~18_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y36_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0] = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  
// & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg 
// [0]))) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|cmd_mux_016|src_payload~18_combout )) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_016|src_payload~18_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .lut_mask = 64'h00000000FC30FC30;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y36_N20
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y36_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout  = SUM(( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly 
// [0] ) + ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14  = CARRY(( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) + 
// ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
        .cout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .lut_mask = 64'h0000CCCC00000F0F;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y36_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  = ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( (((\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0] & 
// ((\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ))))) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]) 
// ) ) # ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( ((\u0|hps_0|fpga_interfaces|h2f_ARADDR [0] & 
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  & (\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1])))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [0]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
        .datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
        .datag(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .extended_lut = "on";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .lut_mask = 64'h555500305F5F0030;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y36_N7
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y36_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout  = SUM(( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg 
// [1] ) + ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + ( 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14  ))
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10  = CARRY(( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] 
// ) + ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14  
// ))

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
        .cout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .lut_mask = 64'h0000AAAA000000FF;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y36_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1] = ( \u0|mm_interconnect_0|cmd_mux_016|src_payload~17_combout  & ( 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout  & 
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1] & !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) 
// ) # ( !\u0|mm_interconnect_0|cmd_mux_016|src_payload~17_combout  & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout  & 
// ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) 
// ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_016|src_payload~17_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .lut_mask = 64'h3033303330003000;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y36_N13
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y36_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout  = ( 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1] & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1] & ( ((\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg 
// [1] & (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout  & !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) # 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .lut_mask = 64'h37333733FF33FF33;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y36_N28
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y36_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout  = SUM(( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] 
// ) + ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 
//  ))
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6  = CARRY(( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + 
// ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
        .cout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y36_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2] = (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout  & 
// ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg 
// [2]))) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|cmd_mux_016|src_payload~13_combout ))))

        .dataa(!\u0|mm_interconnect_0|cmd_mux_016|src_payload~13_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .lut_mask = 64'h00E200E200E200E2;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y36_N25
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y36_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout  & ( 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # 
// ((\u0|hps_0|fpga_interfaces|h2f_ARADDR [2] & \u0|mm_interconnect_0|cmd_mux_016|saved_grant [1])) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout  & ( 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # 
// ((\u0|hps_0|fpga_interfaces|h2f_ARADDR [2] & \u0|mm_interconnect_0|cmd_mux_016|saved_grant [1])) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout  & ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2])))) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  
// & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [2] & ((\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1])))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout  & ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [2] & 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & \u0|mm_interconnect_0|cmd_mux_016|saved_grant [1])) ) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [2]),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
        .datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .lut_mask = 64'h00110C1DCCDDCCDD;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y36_N4
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .power_up = "low";
// synopsys translate_on

// Location: FF_X21_Y36_N55
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y36_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  
// & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) # 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((\u0|mm_interconnect_0|cmd_mux_016|src_payload~14_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_016|src_payload~14_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .lut_mask = 64'h000000000A5F0A5F;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y36_N46
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y36_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout  = SUM(( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg 
// [3] ) + ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3] ) + ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 
//  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y36_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_016|src_payload~12 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_016|src_payload~12_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout  & ( \u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_016|src_payload~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~12 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~12 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y36_N47
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_016|src_payload~12_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y36_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3] = ( \u0|mm_interconnect_0|cmd_mux_016|src_payload~12_combout  & ( 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout  & (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3])) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_016|src_payload~12_combout  & ( 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout  & ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg 
// [3]) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_016|src_payload~12_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .lut_mask = 64'h5151515140404040;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y36_N22
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y36_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3] & ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [3] & \u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3] ) ) 
// # ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3] 
// & ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [3] & \u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3] & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout  & 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]) ) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [3]),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .lut_mask = 64'h00330505FFFF0505;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y36_N58
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X51_Y6_N12
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector61~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector61~0_combout  = ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct_c~q  & ( \A_SPW_TOP|SPW|TX|state_tx~19_combout  & ( (\A_SPW_TOP|SPW|TX|Equal0~4_combout  & ((!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_c~q ) # 
// (\A_SPW_TOP|SPW|TX|Equal0~1_combout ))) ) ) ) # ( !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct_c~q  & ( \A_SPW_TOP|SPW|TX|state_tx~19_combout  & ( (\A_SPW_TOP|SPW|TX|Equal0~4_combout  & ((!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_c~q ) # 
// (\A_SPW_TOP|SPW|TX|Equal0~1_combout ))) ) ) ) # ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct_c~q  & ( !\A_SPW_TOP|SPW|TX|state_tx~19_combout  & ( (\A_SPW_TOP|SPW|TX|Equal0~4_combout  & ((!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_c~q ) # 
// (\A_SPW_TOP|SPW|TX|Equal0~1_combout ))) ) ) ) # ( !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct_c~q  & ( !\A_SPW_TOP|SPW|TX|state_tx~19_combout  & ( (!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_c~q ) # (\A_SPW_TOP|SPW|TX|Equal0~1_combout ) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|Equal0~1_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|Equal0~4_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_c~q ),
        .datad(gnd),
        .datae(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct_c~q ),
        .dataf(!\A_SPW_TOP|SPW|TX|state_tx~19_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector61~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector61~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector61~0 .lut_mask = 64'hF5F5313131313131;
defparam \A_SPW_TOP|SPW|TX|Selector61~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X51_Y6_N36
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector61~1 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector61~1_combout  = ( \A_SPW_TOP|SPW|TX|Equal0~5_combout  & ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c~q  & ( ((!\A_SPW_TOP|SPW|TX|Selector61~0_combout  & \A_SPW_TOP|SPW|TX|ready_tx_timecode~q )) # 
// (\A_SPW_TOP|SPW|TX|Equal0~3_combout ) ) ) ) # ( !\A_SPW_TOP|SPW|TX|Equal0~5_combout  & ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c~q  & ( ((\A_SPW_TOP|SPW|TX|ready_tx_timecode~q  & ((!\A_SPW_TOP|SPW|TX|Selector61~0_combout ) # 
// (\A_SPW_TOP|SPW|TX|Selector63~0_combout )))) # (\A_SPW_TOP|SPW|TX|Equal0~3_combout ) ) ) ) # ( \A_SPW_TOP|SPW|TX|Equal0~5_combout  & ( !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c~q  & ( (!\A_SPW_TOP|SPW|TX|Selector61~0_combout  & 
// \A_SPW_TOP|SPW|TX|ready_tx_timecode~q ) ) ) ) # ( !\A_SPW_TOP|SPW|TX|Equal0~5_combout  & ( !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c~q  & ( (\A_SPW_TOP|SPW|TX|ready_tx_timecode~q  & ((!\A_SPW_TOP|SPW|TX|Selector61~0_combout ) # 
// (\A_SPW_TOP|SPW|TX|Selector63~0_combout ))) ) ) )

        .dataa(!\A_SPW_TOP|SPW|TX|Equal0~3_combout ),
        .datab(!\A_SPW_TOP|SPW|TX|Selector61~0_combout ),
        .datac(!\A_SPW_TOP|SPW|TX|ready_tx_timecode~q ),
        .datad(!\A_SPW_TOP|SPW|TX|Selector63~0_combout ),
        .datae(!\A_SPW_TOP|SPW|TX|Equal0~5_combout ),
        .dataf(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|Selector61~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector61~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector61~1 .lut_mask = 64'h0C0F0C0C5D5F5D5D;
defparam \A_SPW_TOP|SPW|TX|Selector61~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X54_Y6_N56
dffeas \A_SPW_TOP|SPW|TX|ready_tx_timecode (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|Selector61~1_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|ready_tx_timecode~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|ready_tx_timecode .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|ready_tx_timecode .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y36_N6
cyclonev_lcell_comb \u0|timecode_tx_ready|read_mux_out (
// Equation(s):
// \u0|timecode_tx_ready|read_mux_out~combout  = ( \A_SPW_TOP|SPW|TX|ready_tx_timecode~q  & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|ready_tx_timecode~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|timecode_tx_ready|read_mux_out~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|timecode_tx_ready|read_mux_out .extended_lut = "off";
defparam \u0|timecode_tx_ready|read_mux_out .lut_mask = 64'h00000000CC00CC00;
defparam \u0|timecode_tx_ready|read_mux_out .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y36_N7
dffeas \u0|timecode_tx_ready|readdata[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|timecode_tx_ready|read_mux_out~combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|timecode_tx_ready|readdata [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|timecode_tx_ready|readdata[0] .is_wysiwyg = "true";
defparam \u0|timecode_tx_ready|readdata[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X17_Y35_N17
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|av_readdata_pre[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|timecode_tx_ready|readdata [0]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|av_readdata_pre [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|av_readdata_pre[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|av_readdata_pre[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X17_Y35_N2
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem[1][0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem[1][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem[1][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem[1][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y35_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem~0_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem[1][0]~q  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|av_readdata_pre [0] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|av_readdata_pre [0]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem[1][0]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem~0 .lut_mask = 64'h3333333300FF00FF;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y35_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|always0~0_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|read~0_combout  ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|read~0_combout  & ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [0] ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [0]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|read~0_combout ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|always0~0 .lut_mask = 64'hAAAAFFFFAAAAFFFF;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y35_N50
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem[0][0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem[0][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem[0][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem[0][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y35_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~26 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~26_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [0] & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|av_readdata_pre [0] & ( 
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [0] & (((\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem[0][0]~q  & \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][129]~q )) # 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg [0]))) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [0] & (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem[0][0]~q )) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [0] & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|av_readdata_pre [0] & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [0] & 
// ((\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg [0]))) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [0] & (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem[0][0]~q )) ) ) ) # ( 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [0] & ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|av_readdata_pre [0] & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem[0][0]~q  & 
// (((!\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg [0] & \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][129]~q )) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [0]))) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [0] & ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|av_readdata_pre [0] & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem[0][0]~q  & 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [0]) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem[0][0]~q ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg [0]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [0]),
        .datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [0]),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|av_readdata_pre [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~26_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~26 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~26 .lut_mask = 64'h0055045533553755;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~26 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y37_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_013|src_payload~12 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_013|src_payload~12_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout  & ( \u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_013|src_payload~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~12 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~12 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y37_N44
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_013|src_payload~12_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y37_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3] = ( \u0|mm_interconnect_0|cmd_mux_013|src_payload~12_combout  & ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3] & !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q 
// ) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_013|src_payload~12_combout  & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]) # 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_013|src_payload~12_combout ),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .lut_mask = 64'h00000000CFCFC0C0;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y37_N50
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .power_up = "low";
// synopsys translate_on

// Location: FF_X21_Y37_N59
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y37_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_013|src_payload~14 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_013|src_payload~14_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] & ( \u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_013|src_payload~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~14 .lut_mask = 64'h000000000000FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~14 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y37_N11
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_013|src_payload~14_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y37_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_013|src_payload~15 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_013|src_payload~15_combout  = ( \u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_013|src_payload~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~15 .lut_mask = 64'h0000000000FF00FF;
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~15 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y37_N38
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_013|src_payload~15_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y37_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_013|src_payload~16 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_013|src_payload~16_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & ( \u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_013|src_payload~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~16 .lut_mask = 64'h000000000000FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~16 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y37_N41
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_013|src_payload~16_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y37_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] 
// & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg 
// [2])) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((!\u0|mm_interconnect_0|cmd_mux_013|src_payload~15_combout  & \u0|mm_interconnect_0|cmd_mux_013|src_payload~16_combout 
// )))) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & ( 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|cmd_mux_013|src_payload~15_combout  & \u0|mm_interconnect_0|cmd_mux_013|src_payload~16_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_013|src_payload~15_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_013|src_payload~16_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .lut_mask = 64'h0030003088B888B8;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y37_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout  = ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) # 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((\u0|mm_interconnect_0|cmd_mux_013|src_payload~14_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_013|src_payload~14_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .lut_mask = 64'h0000000027272727;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y37_N55
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y37_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout  = ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) 
// # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|cmd_mux_013|src_payload~14_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_013|src_payload~14_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .lut_mask = 64'h00000000F5A0F5A0;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y37_N58
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y37_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_013|src_payload~13 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_013|src_payload~13_combout  = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout  & ( \u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_013|src_payload~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~13 .lut_mask = 64'h0F0F00000F0F0000;
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~13 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y37_N35
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_013|src_payload~13_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y37_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] 
// & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  
// & (!\u0|mm_interconnect_0|cmd_mux_013|src_payload~16_combout  & !\u0|mm_interconnect_0|cmd_mux_013|src_payload~15_combout )) ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg 
// [2] & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & ( 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|cmd_mux_013|src_payload~16_combout  & !\u0|mm_interconnect_0|cmd_mux_013|src_payload~15_combout )) ) ) ) 
// # ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] 
// & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|cmd_mux_013|src_payload~16_combout  & !\u0|mm_interconnect_0|cmd_mux_013|src_payload~15_combout )) ) 
// ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg 
// [1] & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # ((!\u0|mm_interconnect_0|cmd_mux_013|src_payload~16_combout  & 
// !\u0|mm_interconnect_0|cmd_mux_013|src_payload~15_combout )) ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_013|src_payload~16_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_013|src_payload~15_combout ),
        .datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .lut_mask = 64'hFCCC300030003000;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y37_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout  = ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) # 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((\u0|mm_interconnect_0|cmd_mux_013|src_payload~14_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_013|src_payload~14_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .lut_mask = 64'h000000000A5F0A5F;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y37_N4
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y37_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_013|src_payload~17 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_013|src_payload~17_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~1_combout  & ( \u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_013|src_payload~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~17 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~17 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y37_N32
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_013|src_payload~17_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y37_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1] = ( \u0|mm_interconnect_0|cmd_mux_013|src_payload~17_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg 
// [1] & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_013|src_payload~17_combout  & ( 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout  & 
// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]) # 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_013|src_payload~17_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .lut_mask = 64'h00F500F500A000A0;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y37_N53
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y37_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  = ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) # 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((\u0|mm_interconnect_0|cmd_mux_013|src_payload~14_combout ))) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout  )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_013|src_payload~14_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .lut_mask = 64'hFFFFFFFF303F303F;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y37_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout  = ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .lut_mask = 64'hFFFF0000FFFF0000;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y37_N38
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y37_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout  = SUM(( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) + ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14  = CARRY(( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly 
// [0] ) + ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
        .cout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y37_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_013|src_payload~18 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_013|src_payload~18_combout  = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~2_combout  & ( \u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_013|src_payload~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~18 .lut_mask = 64'h3333333300000000;
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~18 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y37_N14
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_013|src_payload~18_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y37_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0] = ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg 
// [0])) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((!\u0|mm_interconnect_0|cmd_mux_013|src_payload~18_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_013|src_payload~18_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .lut_mask = 64'h00000000F5A0F5A0;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y37_N28
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y37_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout  = ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( ((((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout  
// & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0])) # 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]))) ) ) # ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( ((\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout  & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [0])))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [0]),
        .datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
        .datag(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .extended_lut = "on";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .lut_mask = 64'h05050030FFFF0030;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y37_N43
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y37_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout  = SUM(( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 
//  ))
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10  = CARRY(( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly 
// [1] ) + ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
        .cout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y37_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout  = ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [1] & ( (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & 
// (\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]))) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .lut_mask = 64'h0000000002000200;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y37_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout  = ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout  ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg 
// [1] & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout )) # 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .lut_mask = 64'h0A2A0A2AFFFFFFFF;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y37_N49
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y37_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout  = SUM(( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 
//  ))
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6  = CARRY(( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly 
// [2] ) + ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
        .cout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y37_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2] = ( \u0|mm_interconnect_0|cmd_mux_013|src_payload~13_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg 
// [2] & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_013|src_payload~13_combout  & ( 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout  & 
// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]) # 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_013|src_payload~13_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .lut_mask = 64'h00F500F500A000A0;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y37_N25
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y37_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout  = ( \u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [2]) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q 
//  ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg 
// [2] & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout )))) # 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [2])) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg 
// [2] & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout )) ) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [2]),
        .datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
        .datae(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .lut_mask = 64'h000C111DCCCCDDDD;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y37_N55
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y37_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout  = SUM(( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3] ) + ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3] ) + ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y37_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout  = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout 
//  & ( \u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// (((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]) # 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3])))) # 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [3])) ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout  & ( \u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & ( 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg 
// [3]))) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [3])) ) ) ) # ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout  & ( !\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & ( 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg 
// [3]) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]))) ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout  & ( !\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & ( 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg 
// [3]) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [3]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
        .datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .lut_mask = 64'h0A0A0AAA1B1B1BBB;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y37_N19
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .power_up = "low";
// synopsys translate_on

// Location: FF_X21_Y37_N22
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y34_N15
cyclonev_lcell_comb \u0|fifo_empty_tx_status|read_mux_out (
// Equation(s):
// \u0|fifo_empty_tx_status|read_mux_out~combout  = ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & ( 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & \A_SPW_TOP|tx_data|f_empty~q ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\A_SPW_TOP|tx_data|f_empty~q ),
        .datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|fifo_empty_tx_status|read_mux_out~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|fifo_empty_tx_status|read_mux_out .extended_lut = "off";
defparam \u0|fifo_empty_tx_status|read_mux_out .lut_mask = 64'h00AA000000AA0000;
defparam \u0|fifo_empty_tx_status|read_mux_out .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y34_N16
dffeas \u0|fifo_empty_tx_status|readdata[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|fifo_empty_tx_status|read_mux_out~combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|fifo_empty_tx_status|readdata [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|fifo_empty_tx_status|readdata[0] .is_wysiwyg = "true";
defparam \u0|fifo_empty_tx_status|readdata[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X17_Y35_N58
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|av_readdata_pre[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|fifo_empty_tx_status|readdata [0]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|av_readdata_pre [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|av_readdata_pre[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|av_readdata_pre[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X17_Y35_N8
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y35_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem~0_combout  = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][0]~q  ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|av_readdata_pre [0] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|av_readdata_pre [0]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][0]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem~0 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y38_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|always0~0_combout  = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|read~0_combout  ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|read~0_combout  & ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|read~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|always0~0 .lut_mask = 64'hCCCCCCCCFFFFFFFF;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y35_N32
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y35_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~25 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~25_combout  = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|av_readdata_pre [0] & ( ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0] & 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][0]~q ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|av_readdata_pre [0] & ( 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][0]~q  & ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg [0]) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0]))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][0]~q ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|av_readdata_pre [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~25_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~25 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~25 .lut_mask = 64'h0F050F050FAF0FAF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~25 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y29_N33
cyclonev_lcell_comb \u0|link_start|readdata[0]~0 (
// Equation(s):
// \u0|link_start|readdata[0]~0_combout  = ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & ( (\u0|link_start|data_out~q  & 
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|link_start|data_out~q ),
        .datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|link_start|readdata[0]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|link_start|readdata[0]~0 .extended_lut = "off";
defparam \u0|link_start|readdata[0]~0 .lut_mask = 64'h0F000F0000000000;
defparam \u0|link_start|readdata[0]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y29_N35
dffeas \u0|mm_interconnect_0|link_start_s1_translator|av_readdata_pre[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|link_start|readdata[0]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_translator|av_readdata_pre [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_translator|av_readdata_pre[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_translator|av_readdata_pre[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X22_Y29_N32
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem[1][0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem[1][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem[1][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem[1][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y29_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem~0_combout  = (!\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [1] & (\u0|mm_interconnect_0|link_start_s1_translator|av_readdata_pre [0])) # 
// (\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [1] & ((\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem[1][0]~q )))

        .dataa(!\u0|mm_interconnect_0|link_start_s1_translator|av_readdata_pre [0]),
        .datab(!\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem[1][0]~q ),
        .datac(!\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem~0 .lut_mask = 64'h5353535353535353;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y29_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|always0~0_combout  = ( \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~0_combout  & ( !\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [0] ) ) # ( 
// !\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~0_combout  & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [0]) # ((!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout  & (\u0|hps_0|fpga_interfaces|h2f_RREADY [0])) # 
// (\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout  & ((\u0|hps_0|fpga_interfaces|h2f_BREADY [0])))) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
        .datac(!\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [0]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_BREADY [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|always0~0 .lut_mask = 64'hF2F7F2F7F0F0F0F0;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y29_N1
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem[0][0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem[0][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem[0][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem[0][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y29_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~24 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~24_combout  = ( \u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg [0] & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [0] & 
// (\u0|mm_interconnect_0|link_start_s1_translator|av_readdata_pre [0])) # (\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [0] & ((\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem[0][0]~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem[0][0]~q  ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_translator|av_readdata_pre [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [0]),
        .datad(!\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem[0][0]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~24_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~24 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~24 .lut_mask = 64'h00FF00FF505F505F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~24 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y31_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~27 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~27_combout  = ( \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~24_combout  & ( \u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout  & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~26_combout  & 
// ((!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~25_combout ) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout ))) ) ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~24_combout  & ( 
// \u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout  & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~26_combout  & ((!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~25_combout ) # 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout ))) ) ) ) # ( \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~24_combout  & ( !\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout  & ( 
// (\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout  & (!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~26_combout  & ((!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~25_combout ) # 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout )))) ) ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~24_combout  & ( !\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout  & ( 
// (!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~26_combout  & ((!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~25_combout ) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout ),
        .datab(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ),
        .datac(!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~26_combout ),
        .datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~25_combout ),
        .datae(!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~24_combout ),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~27_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~27 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~27 .lut_mask = 64'hF0503010F050F050;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~27 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X54_Y9_N33
cyclonev_lcell_comb \m_x|rx_got_fct~0 (
// Equation(s):
// \m_x|rx_got_fct~0_combout  = (!\m_x|always10~0_combout  & (((!\m_x|last_is_data~q  & \m_x|rx_got_fct~q )))) # (\m_x|always10~0_combout  & (!\m_x|always10~1_combout ))

        .dataa(!\m_x|always10~0_combout ),
        .datab(!\m_x|always10~1_combout ),
        .datac(!\m_x|last_is_data~q ),
        .datad(!\m_x|rx_got_fct~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\m_x|rx_got_fct~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \m_x|rx_got_fct~0 .extended_lut = "off";
defparam \m_x|rx_got_fct~0 .lut_mask = 64'h44E444E444E444E4;
defparam \m_x|rx_got_fct~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X54_Y9_N53
dffeas \m_x|rx_got_fct (
        .clk(!\m_x|always3~0_combout ),
        .d(gnd),
        .asdata(\m_x|rx_got_fct~0_combout ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|rx_got_fct~q ),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|rx_got_fct .is_wysiwyg = "true";
defparam \m_x|rx_got_fct .power_up = "low";
// synopsys translate_on

// Location: FF_X53_Y9_N46
dffeas \m_x|info[0] (
        .clk(!\m_x|always3~0_combout ),
        .d(gnd),
        .asdata(\m_x|rx_got_fct~q ),
        .clrn(!\db_system_spwulight_b|aux_pb~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\m_x|state_data_process.01~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\m_x|info [0]),
        .prn(vcc));
// synopsys translate_off
defparam \m_x|info[0] .is_wysiwyg = "true";
defparam \m_x|info[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X31_Y13_N12
cyclonev_lcell_comb \u0|data_info|read_mux_out[0] (
// Equation(s):
// \u0|data_info|read_mux_out [0] = ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( 
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & \m_x|info [0]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datac(!\m_x|info [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|data_info|read_mux_out [0]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|data_info|read_mux_out[0] .extended_lut = "off";
defparam \u0|data_info|read_mux_out[0] .lut_mask = 64'h0C0C0C0C00000000;
defparam \u0|data_info|read_mux_out[0] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X31_Y13_N14
dffeas \u0|data_info|readdata[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|data_info|read_mux_out [0]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|data_info|readdata [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|data_info|readdata[0] .is_wysiwyg = "true";
defparam \u0|data_info|readdata[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X19_Y27_N41
dffeas \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|data_info|readdata [0]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X19_Y27_N29
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y27_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~0_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][0]~q  ) ) # ( 
// !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [0] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [0]),
        .datad(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][0]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~0 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y27_N17
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y27_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~14 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~14_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][0]~q  & ( (!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout ) # 
// (\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [0]) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][0]~q  & ( (\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [0] & 
// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [0]),
        .datac(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~14 .lut_mask = 64'h03030303F3F3F3F3;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~14 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y27_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~28 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~28_combout  = ( \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~27_combout  & ( \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~14_combout  & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~13_combout  & 
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~18_combout  & (!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout  & \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~23_combout ))) ) ) ) # ( \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~27_combout  & 
// ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~14_combout  & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~13_combout  & (\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~18_combout  & \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~23_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~13_combout ),
        .datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~18_combout ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ),
        .datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~23_combout ),
        .datae(!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~27_combout ),
        .dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~14_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~28_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~28 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~28 .lut_mask = 64'h0000002200000020;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~28 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y18_N50
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem[1][0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem[1][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem[1][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem[1][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y20_N18
cyclonev_lcell_comb \u0|write_en_tx|readdata[0]~0 (
// Equation(s):
// \u0|write_en_tx|readdata[0]~0_combout  = ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & ( (\u0|write_en_tx|data_out~q  & 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|write_en_tx|data_out~q ),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|write_en_tx|readdata[0]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|write_en_tx|readdata[0]~0 .extended_lut = "off";
defparam \u0|write_en_tx|readdata[0]~0 .lut_mask = 64'h0F000F0000000000;
defparam \u0|write_en_tx|readdata[0]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y20_N20
dffeas \u0|mm_interconnect_0|write_en_tx_s1_translator|av_readdata_pre[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|write_en_tx|readdata[0]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_translator|av_readdata_pre [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_translator|av_readdata_pre[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_translator|av_readdata_pre[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y18_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem~0_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_translator|av_readdata_pre [0] & ( (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used [1]) # 
// (\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem[1][0]~q ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_translator|av_readdata_pre [0] & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem[1][0]~q ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem[1][0]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_translator|av_readdata_pre [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem~0 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y18_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|always0~0_combout  = ( \u0|hps_0|fpga_interfaces|h2f_BREADY [0] & ( (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used [0]) # 
// ((!\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|read~0_combout  & ((\u0|mm_interconnect_0|rsp_demux_011|src0_valid~0_combout ) # (\u0|hps_0|fpga_interfaces|h2f_RREADY [0])))) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_BREADY [0] & ( 
// (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used [0]) # ((\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & (!\u0|mm_interconnect_0|rsp_demux_011|src0_valid~0_combout  & !\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|read~0_combout ))) ) 
// )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
        .datab(!\u0|mm_interconnect_0|rsp_demux_011|src0_valid~0_combout ),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used [0]),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|read~0_combout ),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_BREADY [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|always0~0 .lut_mask = 64'hF4F0F4F0F7F0F7F0;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y18_N32
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem[0][0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem[0][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem[0][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem[0][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y18_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~7 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~7_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg [0] & ( (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used [0] & 
// ((\u0|mm_interconnect_0|write_en_tx_s1_translator|av_readdata_pre [0]))) # (\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used [0] & (\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem[0][0]~q )) ) ) # ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem[0][0]~q  ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used [0]),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem[0][0]~q ),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_translator|av_readdata_pre [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~7 .lut_mask = 64'h0F0F0F0F03CF03CF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~7 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y18_N39
cyclonev_lcell_comb \u0|timecode_tx_data|readdata[0] (
// Equation(s):
// \u0|timecode_tx_data|readdata [0] = ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & \u0|timecode_tx_data|data_out [0]) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datab(gnd),
        .datac(!\u0|timecode_tx_data|data_out [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|timecode_tx_data|readdata [0]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|timecode_tx_data|readdata[0] .extended_lut = "off";
defparam \u0|timecode_tx_data|readdata[0] .lut_mask = 64'h0A0A0A0A00000000;
defparam \u0|timecode_tx_data|readdata[0] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y18_N41
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|timecode_tx_data|readdata [0]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X28_Y16_N4
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y16_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~0_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][0]~q  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [0] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [0]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][0]~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~0 .lut_mask = 64'h333333330F0F0F0F;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y16_N53
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y16_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~8 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~8_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][0]~q  & ( ((!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0]) # 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [0]) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][0]~q  & ( 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [0] & (\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [0]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][0]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~8 .lut_mask = 64'h03000300F3FFF3FF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~8 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y18_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~9 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~9_combout  = ( \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~8_combout  & ( ((\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~7_combout  & \u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout )) # 
// (\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout ) ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~8_combout  & ( (\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~7_combout  & \u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~7_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout ),
        .datad(!\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~8_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~9 .lut_mask = 64'h0505050505FF05FF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~9 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y19_N18
cyclonev_lcell_comb \u0|timecode_tx_enable|readdata[0]~0 (
// Equation(s):
// \u0|timecode_tx_enable|readdata[0]~0_combout  = ( \u0|timecode_tx_enable|data_out~q  & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|timecode_tx_enable|data_out~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|timecode_tx_enable|readdata[0]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|timecode_tx_enable|readdata[0]~0 .extended_lut = "off";
defparam \u0|timecode_tx_enable|readdata[0]~0 .lut_mask = 64'h00000000A0A0A0A0;
defparam \u0|timecode_tx_enable|readdata[0]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y19_N20
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|av_readdata_pre[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|timecode_tx_enable|readdata[0]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|av_readdata_pre [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|av_readdata_pre[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|av_readdata_pre[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X19_Y19_N26
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem[1][0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem[1][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem[1][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem[1][0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y19_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem~0_combout  = (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [1] & (\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|av_readdata_pre [0])) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [1] & ((\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem[1][0]~q )))

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|av_readdata_pre [0]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem[1][0]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem~0 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y19_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|always0~0_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|read~0_combout  & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [0] ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|read~0_combout  & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [0]) # ((!\u0|mm_interconnect_0|rsp_demux_015|src0_valid~0_combout  & 
// ((\u0|hps_0|fpga_interfaces|h2f_RREADY [0]))) # (\u0|mm_interconnect_0|rsp_demux_015|src0_valid~0_combout  & (\u0|hps_0|fpga_interfaces|h2f_BREADY [0]))) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_BREADY [0]),
        .datab(!\u0|mm_interconnect_0|rsp_demux_015|src0_valid~0_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [0]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|read~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|always0~0 .lut_mask = 64'hF1FDF1FDF0F0F0F0;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y19_N10
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem[0][0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem[0][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem[0][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem[0][0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y19_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~10 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~10_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|av_readdata_pre [0] & ( ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [0] & 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem[0][0]~q ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|av_readdata_pre [0] & ( 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem[0][0]~q  & ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg [0]) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [0]))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [0]),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg [0]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem[0][0]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|av_readdata_pre [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~10 .lut_mask = 64'h00DD00DD22FF22FF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~10 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y22_N55
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[1][0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[1][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[1][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[1][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X59_Y10_N33
cyclonev_lcell_comb \u0|clock_sel|readdata[0]~0 (
// Equation(s):
// \u0|clock_sel|readdata[0]~0_combout  = ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & ( 
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( \u0|clock_sel|data_out [0] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|clock_sel|data_out [0]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|clock_sel|readdata[0]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|clock_sel|readdata[0]~0 .extended_lut = "off";
defparam \u0|clock_sel|readdata[0]~0 .lut_mask = 64'h0F0F000000000000;
defparam \u0|clock_sel|readdata[0]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X59_Y10_N35
dffeas \u0|mm_interconnect_0|clock_sel_s1_translator|av_readdata_pre[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|clock_sel|readdata[0]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_translator|av_readdata_pre [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_translator|av_readdata_pre[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_translator|av_readdata_pre[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y22_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem~0_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_translator|av_readdata_pre [0] & ( (!\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [1]) # 
// (\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[1][0]~q ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_translator|av_readdata_pre [0] & ( (\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[1][0]~q  & 
// \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [1]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[1][0]~q ),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_translator|av_readdata_pre [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem~0 .lut_mask = 64'h03030303F3F3F3F3;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y22_N10
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[0][0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[0][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[0][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[0][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y22_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~11 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~11_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_translator|av_readdata_pre [0] & ( ((\u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg [0] & 
// !\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[0][0]~q ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_translator|av_readdata_pre [0] & ( 
// (\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[0][0]~q  & ((!\u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg [0]) # (\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [0]))) ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg [0]),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[0][0]~q ),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_translator|av_readdata_pre [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~11 .lut_mask = 64'h2323232373737373;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~11 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y22_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~12 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~12_combout  = ( \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~11_combout  & ( \u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout  & ( (\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout ) # 
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~10_combout ) ) ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~11_combout  & ( \u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout  & ( \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~10_combout  ) ) 
// ) # ( \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~11_combout  & ( !\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout  & ( \u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout  ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~10_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~11_combout ),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~12 .lut_mask = 64'h00000F0F55555F5F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~12 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y15_N18
cyclonev_lcell_comb \u0|write_data_fifo_tx|readdata[0] (
// Equation(s):
// \u0|write_data_fifo_tx|readdata [0] = ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( \u0|write_data_fifo_tx|data_out [0] & ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .dataf(!\u0|write_data_fifo_tx|data_out [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|write_data_fifo_tx|readdata [0]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|write_data_fifo_tx|readdata[0] .extended_lut = "off";
defparam \u0|write_data_fifo_tx|readdata[0] .lut_mask = 64'h00000000CCCC0000;
defparam \u0|write_data_fifo_tx|readdata[0] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y15_N20
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|write_data_fifo_tx|readdata [0]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y20_N6
cyclonev_lcell_comb \u0|link_disable|readdata[0]~0 (
// Equation(s):
// \u0|link_disable|readdata[0]~0_combout  = ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( (\u0|link_disable|data_out~q  & 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]) ) )

        .dataa(gnd),
        .datab(!\u0|link_disable|data_out~q ),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|link_disable|readdata[0]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|link_disable|readdata[0]~0 .extended_lut = "off";
defparam \u0|link_disable|readdata[0]~0 .lut_mask = 64'h3030303000000000;
defparam \u0|link_disable|readdata[0]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y20_N8
dffeas \u0|mm_interconnect_0|link_disable_s1_translator|av_readdata_pre[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|link_disable|readdata[0]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_translator|av_readdata_pre [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_translator|av_readdata_pre[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_translator|av_readdata_pre[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X11_Y20_N11
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem[1][0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem[1][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem[1][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem[1][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y20_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem~0_combout  = ( \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem[1][0]~q  ) ) # ( 
// !\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|link_disable_s1_translator|av_readdata_pre [0] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_translator|av_readdata_pre [0]),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem[1][0]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem~0 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y20_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem[0][0]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem[0][0]~feeder_combout  = ( \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem~0_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem[0][0]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem[0][0]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem[0][0]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem[0][0]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y22_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|always0~0_combout  = ( \u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ( (!\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [0]) # 
// ((!\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|read~0_combout  & ((!\u0|mm_interconnect_0|rsp_demux_009|src0_valid~0_combout ) # (\u0|hps_0|fpga_interfaces|h2f_BREADY [0])))) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ( 
// (!\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [0]) # ((\u0|hps_0|fpga_interfaces|h2f_BREADY [0] & (!\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|read~0_combout  & \u0|mm_interconnect_0|rsp_demux_009|src0_valid~0_combout ))) ) 
// )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_BREADY [0]),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|read~0_combout ),
        .datac(!\u0|mm_interconnect_0|rsp_demux_009|src0_valid~0_combout ),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [0]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|always0~0 .lut_mask = 64'hFF04FF04FFC4FFC4;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y20_N59
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem[0][0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem[0][0]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem[0][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem[0][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem[0][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y20_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~5 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~5_combout  = ( \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem[0][0]~q  & ( \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [0] ) ) # ( 
// \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem[0][0]~q  & ( !\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg [0]) # 
// (\u0|mm_interconnect_0|link_disable_s1_translator|av_readdata_pre [0]) ) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem[0][0]~q  & ( !\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [0] & ( 
// (\u0|mm_interconnect_0|link_disable_s1_translator|av_readdata_pre [0] & \u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg [0]) ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_translator|av_readdata_pre [0]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg [0]),
        .datae(!\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem[0][0]~q ),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~5 .lut_mask = 64'h0033FF330000FFFF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y16_N8
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y16_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~0_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][0]~q  & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1]) # 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [0]) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][0]~q  & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [0] & 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [0]),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][0]~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~0 .lut_mask = 64'h30303F3F30303F3F;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y16_N8
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][0]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y16_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~6 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~6_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][0]~q  & ( \u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout  & ( ((\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout 
//  & ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout ) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [0])))) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~5_combout ) ) ) ) # ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][0]~q  & ( \u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout  & ( ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout  & 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [0] & \u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ))) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~5_combout ) ) ) ) # ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][0]~q  & ( !\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout  & ( (\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout  & 
// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout ) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [0]))) ) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][0]~q  & ( 
// !\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout  & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout  & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [0] & 
// \u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout ),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [0]),
        .datac(!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~5_combout ),
        .datad(!\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ),
        .datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][0]~q ),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~6 .lut_mask = 64'h001100BB0F1F0FBF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~6 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y27_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~29 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~29_combout  = ( \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~12_combout  & ( \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~6_combout  ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~12_combout  & ( 
// \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~6_combout  ) ) # ( \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~12_combout  & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~6_combout  ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~12_combout  & ( 
// !\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~6_combout  & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~4_combout ) # ((!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~28_combout ) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~9_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~4_combout ),
        .datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~28_combout ),
        .datac(!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~9_combout ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~12_combout ),
        .dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~6_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~29_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~29 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~29 .lut_mask = 64'hEFEFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~29 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y25_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_data[116] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|src_data [116] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [11] & ( ((\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [11])) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_ARID [11] & ( (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [11]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [11]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_008|src_data [116]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[116] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[116] .lut_mask = 64'h0505050505FF05FF;
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[116] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y25_N1
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_008|src_data [116]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";
// synopsys translate_on

// Location: FF_X18_Y25_N35
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~21_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][116]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y25_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~21 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~21_combout  = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][116]~q  & ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] ) ) # ( 
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][116]~q  & ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] ) 
// ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][116]~q  & ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ( 
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][116]~q ),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~21_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~21 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~21 .lut_mask = 64'h0F0F0F0F0000FFFF;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~21 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y29_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][116]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][116]~feeder_combout  = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~21_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~21_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][116]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][116]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][116]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][116]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y29_N35
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][116] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][116]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][116]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y28_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_007|src0_valid~1 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout  = ( !\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout  & ( \u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_007|src0_valid~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_007|src0_valid~1 .lut_mask = 64'h0F0F0F0F00000000;
defparam \u0|mm_interconnect_0|rsp_demux_007|src0_valid~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y25_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_008|src0_valid~1 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout  = ( !\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout  & ( \u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_008|src0_valid~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_008|src0_valid~1 .lut_mask = 64'h0F0F0F0F00000000;
defparam \u0|mm_interconnect_0|rsp_demux_008|src0_valid~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y29_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[116]~56 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[116]~56_combout  = ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][116]~q  & ( \u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout  & ( (\u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout ) # 
// (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][116]~q ) ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][116]~q  & ( \u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout  & ( 
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][116]~q  ) ) ) # ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][116]~q  & ( !\u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout  & ( 
// \u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout  ) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][116]~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][116]~q ),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data[116]~56_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[116]~56 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[116]~56 .lut_mask = 64'h00000F0F55555F5F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[116]~56 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y22_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_018|src0_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout  = ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][66]~q  & ( (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][69]~q  & 
// (!\u0|mm_interconnect_0|clock_sel_s1_agent|rp_valid~combout  & \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][68]~q )) ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][69]~q ),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_agent|rp_valid~combout ),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][68]~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][66]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_018|src0_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_018|src0_valid~0 .lut_mask = 64'h0808080800000000;
defparam \u0|mm_interconnect_0|rsp_demux_018|src0_valid~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y26_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[116]~59 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[116]~59_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][116]~q  & ( \u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout  ) ) # ( 
// !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][116]~q  & ( \u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout  & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][116]~q  & 
// \u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout ) ) ) ) # ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][116]~q  & ( !\u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout  & ( 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][116]~q  & \u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout ) ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][116]~q  & ( 
// !\u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout  & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][116]~q  & \u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout ) ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][116]~q ),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout ),
        .datae(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][116]~q ),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data[116]~59_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[116]~59 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[116]~59 .lut_mask = 64'h003300330033FFFF;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[116]~59 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y29_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_004|src0_valid~1 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout  = ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout  & ( \u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout  ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_004|src0_valid~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_004|src0_valid~1 .lut_mask = 64'h5555555500000000;
defparam \u0|mm_interconnect_0|rsp_demux_004|src0_valid~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y26_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[116]~55 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[116]~55_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][116]~q  & ( ((\u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout  & 
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][116]~q )) # (\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout ) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][116]~q  & ( 
// (\u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout  & \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][116]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout ),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][116]~q ),
        .datac(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][116]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data[116]~55_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[116]~55 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[116]~55 .lut_mask = 64'h111111111F1F1F1F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[116]~55 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y19_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_014|src0_valid~1 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout  = ( \u0|mm_interconnect_0|rsp_demux_014|src0_valid~0_combout  & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|rp_valid~combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|rsp_demux_014|src0_valid~0_combout ),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|rp_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_014|src0_valid~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_014|src0_valid~1 .lut_mask = 64'h0000FFFF00000000;
defparam \u0|mm_interconnect_0|rsp_demux_014|src0_valid~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y23_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[116]~58 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[116]~58_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][116]~q  & ( ((\u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout  & 
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][116]~q )) # (\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][116]~q  & ( 
// (\u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout  & \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][116]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout ),
        .datac(!\u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout ),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][116]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][116]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data[116]~58_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[116]~58 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[116]~58 .lut_mask = 64'h000F000F333F333F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[116]~58 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y24_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_009|src0_valid~1 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout  = ( \u0|mm_interconnect_0|rsp_demux_009|src0_valid~0_combout  & ( !\u0|mm_interconnect_0|link_disable_s1_agent|rp_valid~combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_agent|rp_valid~combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_009|src0_valid~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_009|src0_valid~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_009|src0_valid~1 .lut_mask = 64'h00000000F0F0F0F0;
defparam \u0|mm_interconnect_0|rsp_demux_009|src0_valid~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y24_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[116]~57 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[116]~57_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][116]~q  & ( ((\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][116]~q  & 
// \u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout )) # (\u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout ) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][116]~q  & ( 
// (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][116]~q  & \u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][116]~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout ),
        .datad(!\u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][116]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data[116]~57_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[116]~57 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[116]~57 .lut_mask = 64'h0505050505FF05FF;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[116]~57 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y26_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[116] (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data [116] = ( \u0|mm_interconnect_0|rsp_mux|src_data[116]~58_combout  & ( \u0|mm_interconnect_0|rsp_mux|src_data[116]~57_combout  ) ) # ( !\u0|mm_interconnect_0|rsp_mux|src_data[116]~58_combout  & ( 
// \u0|mm_interconnect_0|rsp_mux|src_data[116]~57_combout  ) ) # ( \u0|mm_interconnect_0|rsp_mux|src_data[116]~58_combout  & ( !\u0|mm_interconnect_0|rsp_mux|src_data[116]~57_combout  ) ) # ( !\u0|mm_interconnect_0|rsp_mux|src_data[116]~58_combout  & ( 
// !\u0|mm_interconnect_0|rsp_mux|src_data[116]~57_combout  & ( ((\u0|mm_interconnect_0|rsp_mux|src_data[116]~55_combout ) # (\u0|mm_interconnect_0|rsp_mux|src_data[116]~59_combout )) # (\u0|mm_interconnect_0|rsp_mux|src_data[116]~56_combout ) ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|rsp_mux|src_data[116]~56_combout ),
        .datac(!\u0|mm_interconnect_0|rsp_mux|src_data[116]~59_combout ),
        .datad(!\u0|mm_interconnect_0|rsp_mux|src_data[116]~55_combout ),
        .datae(!\u0|mm_interconnect_0|rsp_mux|src_data[116]~58_combout ),
        .dataf(!\u0|mm_interconnect_0|rsp_mux|src_data[116]~57_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data [116]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[116] .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[116] .lut_mask = 64'h3FFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[116] .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y31_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal1~0 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal1~0_combout  = ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [5] & ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [8] & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [6] & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [7] & 
// (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [4] & !\u0|hps_0|fpga_interfaces|h2f_ARADDR [9]))) ) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [6]),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [7]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [4]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [9]),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [5]),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [8]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router_001|Equal1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal1~0 .lut_mask = 64'h8000000000000000;
defparam \u0|mm_interconnect_0|router_001|Equal1~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y31_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal21~0 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal21~0_combout  = ( \u0|mm_interconnect_0|router_001|Equal19~0_combout  & ( \u0|mm_interconnect_0|router_001|Equal1~1_combout  & ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & 
// (\u0|mm_interconnect_0|router_001|Equal1~2_combout  & (\u0|mm_interconnect_0|router_001|Equal1~0_combout  & \u0|hps_0|fpga_interfaces|h2f_ARADDR [17]))) ) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),
        .datab(!\u0|mm_interconnect_0|router_001|Equal1~2_combout ),
        .datac(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),
        .datae(!\u0|mm_interconnect_0|router_001|Equal19~0_combout ),
        .dataf(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router_001|Equal21~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal21~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal21~0 .lut_mask = 64'h0000000000000001;
defparam \u0|mm_interconnect_0|router_001|Equal21~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y27_N59
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[15] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|router_001|Equal21~0_combout ),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [15]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[15] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[15] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y23_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|src15_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|src15_valid~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [15] & ( \u0|mm_interconnect_0|router_001|Equal21~0_combout  & ( \u0|hps_0|fpga_interfaces|h2f_ARVALID [0] ) ) ) # ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [15] & ( \u0|mm_interconnect_0|router_001|Equal21~0_combout  & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q  & \u0|hps_0|fpga_interfaces|h2f_ARVALID 
// [0]) ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [15]),
        .dataf(!\u0|mm_interconnect_0|router_001|Equal21~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux_001|src15_valid~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|src15_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|src15_valid~0 .lut_mask = 64'h000000000C0C0F0F;
defparam \u0|mm_interconnect_0|cmd_demux_001|src15_valid~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y24_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg~0_combout  = ( !\u0|mm_interconnect_0|cmd_demux|src15_valid~1_combout  & ( !\u0|mm_interconnect_0|cmd_demux_001|src15_valid~0_combout  ) )

        .dataa(!\u0|mm_interconnect_0|cmd_demux_001|src15_valid~0_combout ),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_demux|src15_valid~1_combout ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg~0 .lut_mask = 64'hAAAA0000AAAA0000;
defparam \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y23_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|packet_in_progress~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|packet_in_progress~0_combout  = ( !\u0|mm_interconnect_0|cmd_mux_015|update_grant~0_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_015|update_grant~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_015|packet_in_progress~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|packet_in_progress~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_015|packet_in_progress~0 .lut_mask = 64'hFFFFFFFF00000000;
defparam \u0|mm_interconnect_0|cmd_mux_015|packet_in_progress~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y23_N20
dffeas \u0|mm_interconnect_0|cmd_mux_015|packet_in_progress (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_015|packet_in_progress~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_015|packet_in_progress~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|packet_in_progress .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_015|packet_in_progress .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y23_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  = ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .lut_mask = 64'hFF00FF0000000000;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y23_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|update_grant~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|update_grant~0_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & ( \u0|mm_interconnect_0|cmd_demux|src15_valid~1_combout  & ( 
// (!\u0|mm_interconnect_0|cmd_mux_015|src_valid~0_combout  & (!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & !\u0|mm_interconnect_0|cmd_mux_015|packet_in_progress~q )) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & ( \u0|mm_interconnect_0|cmd_demux|src15_valid~1_combout  & ( (!\u0|mm_interconnect_0|cmd_mux_015|src_valid~0_combout  & 
// ((!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & ((!\u0|mm_interconnect_0|cmd_mux_015|packet_in_progress~q ))) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & (\u0|mm_interconnect_0|cmd_mux_015|src_payload [0])))) # 
// (\u0|mm_interconnect_0|cmd_mux_015|src_valid~0_combout  & (((\u0|mm_interconnect_0|cmd_mux_015|src_payload [0])))) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & 
// ( !\u0|mm_interconnect_0|cmd_demux|src15_valid~1_combout  & ( (!\u0|mm_interconnect_0|cmd_mux_015|src_valid~0_combout  & !\u0|mm_interconnect_0|cmd_mux_015|packet_in_progress~q ) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & ( !\u0|mm_interconnect_0|cmd_demux|src15_valid~1_combout  & ( (!\u0|mm_interconnect_0|cmd_mux_015|src_valid~0_combout  & 
// ((!\u0|mm_interconnect_0|cmd_mux_015|packet_in_progress~q ))) # (\u0|mm_interconnect_0|cmd_mux_015|src_valid~0_combout  & (\u0|mm_interconnect_0|cmd_mux_015|src_payload [0])) ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_015|src_valid~0_combout ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
        .datac(!\u0|mm_interconnect_0|cmd_mux_015|src_payload [0]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_015|packet_in_progress~q ),
        .datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .dataf(!\u0|mm_interconnect_0|cmd_demux|src15_valid~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_015|update_grant~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|update_grant~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_015|update_grant~0 .lut_mask = 64'hAF05AA008F078800;
defparam \u0|mm_interconnect_0|cmd_mux_015|update_grant~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y24_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg~1_combout  = (!\u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg~0_combout  & ((!\u0|mm_interconnect_0|cmd_mux_015|update_grant~0_combout  & 
// ((\u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg [1]))) # (\u0|mm_interconnect_0|cmd_mux_015|update_grant~0_combout  & (\u0|mm_interconnect_0|cmd_mux_015|arb|grant[0]~1_combout )))) # 
// (\u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg~0_combout  & (((\u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg [1]))))

        .dataa(!\u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg~0_combout ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_015|update_grant~0_combout ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_015|arb|grant[0]~1_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg [1]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg~1 .lut_mask = 64'h02DF02DF02DF02DF;
defparam \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y24_N38
dffeas \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y24_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg~2 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg~2_combout  = ( \u0|mm_interconnect_0|cmd_mux_015|arb|grant[1]~0_combout  & ( (\u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg [0] & ((!\u0|mm_interconnect_0|cmd_mux_015|update_grant~0_combout ) 
// # (\u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg~0_combout ))) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_015|arb|grant[1]~0_combout  & ( ((!\u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg~0_combout  & 
// \u0|mm_interconnect_0|cmd_mux_015|update_grant~0_combout )) # (\u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg [0]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg~0_combout ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_015|update_grant~0_combout ),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_015|arb|grant[1]~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg~2 .lut_mask = 64'h22FF22FF00DD00DD;
defparam \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y24_N41
dffeas \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y24_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|arb|grant[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|arb|grant[1]~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg [1] & ( \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg [0] & ( \u0|mm_interconnect_0|cmd_demux_001|src15_valid~0_combout  ) ) ) # 
// ( \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg [1] & ( !\u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg [0] & ( \u0|mm_interconnect_0|cmd_demux_001|src15_valid~0_combout  ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg 
// [1] & ( !\u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg [0] & ( (\u0|mm_interconnect_0|cmd_demux_001|src15_valid~0_combout  & !\u0|mm_interconnect_0|cmd_demux|src15_valid~1_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_demux_001|src15_valid~0_combout ),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|cmd_demux|src15_valid~1_combout ),
        .datae(!\u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg [1]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_015|arb|grant[1]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|arb|grant[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_015|arb|grant[1]~0 .lut_mask = 64'h5500555500005555;
defparam \u0|mm_interconnect_0|cmd_mux_015|arb|grant[1]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y24_N2
dffeas \u0|mm_interconnect_0|cmd_mux_015|saved_grant[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_015|arb|grant[1]~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|cmd_mux_015|update_grant~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|saved_grant[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_015|saved_grant[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X21_Y21_N44
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";
// synopsys translate_on

// Location: FF_X21_Y21_N59
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][66]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y21_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~3_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][66]~q  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][66]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y21_N8
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~3_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][66]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";
// synopsys translate_on

// Location: FF_X21_Y21_N1
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][69] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][69]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][69] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y21_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~1_combout  = (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & 
// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]))) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][69]~q ))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][69]~q ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h03CF03CF03CF03CF;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y21_N50
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][69] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][69]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][69] .power_up = "low";
// synopsys translate_on

// Location: FF_X21_Y21_N5
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][68] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][68]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][68] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][68] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y21_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~2_combout  = (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68])) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & 
// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][68]~q )))

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][68]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~2 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y21_N22
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][68] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~2_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][68]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][68] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][68] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y21_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_015|src0_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_015|src0_valid~0_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][68]~q  & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][66]~q  & 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][69]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][66]~q ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][69]~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][68]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_demux_015|src0_valid~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_015|src0_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_015|src0_valid~0 .lut_mask = 64'h00000000C0C0C0C0;
defparam \u0|mm_interconnect_0|rsp_demux_015|src0_valid~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y22_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_015|src0_valid~1 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout  = ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|rp_valid~combout  & ( \u0|mm_interconnect_0|rsp_demux_015|src0_valid~0_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|rsp_demux_015|src0_valid~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|rp_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_015|src0_valid~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_015|src0_valid~1 .lut_mask = 64'h0F0F0F0F00000000;
defparam \u0|mm_interconnect_0|rsp_demux_015|src0_valid~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y26_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[115]~54 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[115]~54_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][115]~q  & ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][115]~q  & ( 
// (\u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout ) # (\u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout ) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][115]~q  & ( 
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][115]~q  & ( \u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout  ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][115]~q  & ( 
// !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][115]~q  & ( \u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout  ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout ),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout ),
        .datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][115]~q ),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][115]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data[115]~54_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[115]~54 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[115]~54 .lut_mask = 64'h0000333300FF33FF;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[115]~54 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y28_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[115]~51 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[115]~51_combout  = ( \u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout  & ( ((\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][115]~q  & \u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout )) # 
// (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][115]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout  & ( (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][115]~q  & 
// \u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][115]~q ),
        .datab(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout ),
        .datac(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][115]~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data[115]~51_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[115]~51 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[115]~51 .lut_mask = 64'h111111111F1F1F1F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[115]~51 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y26_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[115]~50 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[115]~50_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][115]~q  & ( ((\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout  & 
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][115]~q )) # (\u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][115]~q  & ( 
// (\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout  & \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][115]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout ),
        .datab(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout ),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][115]~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][115]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data[115]~50_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[115]~50 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[115]~50 .lut_mask = 64'h0303030357575757;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[115]~50 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y22_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[115]~53 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[115]~53_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][115]~q  & ( \u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout  & ( (\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout 
// ) # (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][115]~q ) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][115]~q  & ( \u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout  & ( 
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][115]~q  ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][115]~q  & ( !\u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout  & ( 
// \u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout  ) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][115]~q ),
        .datab(!\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout ),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][115]~q ),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data[115]~53_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[115]~53 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[115]~53 .lut_mask = 64'h0000333355557777;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[115]~53 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y24_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[115]~52 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[115]~52_combout  = ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][115]~q  & ( ((\u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout  & 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][115]~q )) # (\u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout ) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][115]~q  & ( 
// (\u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout  & \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][115]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout ),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][115]~q ),
        .datae(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][115]~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data[115]~52_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[115]~52 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[115]~52 .lut_mask = 64'h00550F5F00550F5F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[115]~52 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y26_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[115] (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data [115] = ( \u0|mm_interconnect_0|rsp_mux|src_data[115]~53_combout  & ( \u0|mm_interconnect_0|rsp_mux|src_data[115]~52_combout  ) ) # ( !\u0|mm_interconnect_0|rsp_mux|src_data[115]~53_combout  & ( 
// \u0|mm_interconnect_0|rsp_mux|src_data[115]~52_combout  ) ) # ( \u0|mm_interconnect_0|rsp_mux|src_data[115]~53_combout  & ( !\u0|mm_interconnect_0|rsp_mux|src_data[115]~52_combout  ) ) # ( !\u0|mm_interconnect_0|rsp_mux|src_data[115]~53_combout  & ( 
// !\u0|mm_interconnect_0|rsp_mux|src_data[115]~52_combout  & ( ((\u0|mm_interconnect_0|rsp_mux|src_data[115]~50_combout ) # (\u0|mm_interconnect_0|rsp_mux|src_data[115]~51_combout )) # (\u0|mm_interconnect_0|rsp_mux|src_data[115]~54_combout ) ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|rsp_mux|src_data[115]~54_combout ),
        .datac(!\u0|mm_interconnect_0|rsp_mux|src_data[115]~51_combout ),
        .datad(!\u0|mm_interconnect_0|rsp_mux|src_data[115]~50_combout ),
        .datae(!\u0|mm_interconnect_0|rsp_mux|src_data[115]~53_combout ),
        .dataf(!\u0|mm_interconnect_0|rsp_mux|src_data[115]~52_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data [115]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[115] .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[115] .lut_mask = 64'h3FFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[115] .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y27_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3_combout  & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~0_combout  ) ) # ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3_combout  & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~0_combout  $ (((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~4_combout ) # 
// ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~1_combout ) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~0_combout ),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~4_combout ),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout ),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~0 .lut_mask = 64'h6555655555555555;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y27_N17
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y27_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount [6] & ( ((\u0|hps_0|fpga_interfaces|h2f_AWLEN [3] & 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add6~0_combout )) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount [6] & ( 
// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (\u0|hps_0|fpga_interfaces|h2f_AWLEN [3] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add6~0_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [3]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add6~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount [6]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~0 .lut_mask = 64'h000A000A555F555F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y21_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout  = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3_combout  & ( 
// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~0_combout  & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~4_combout  & (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~1_combout  & 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~0_combout ),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~4_combout ),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~1_combout ),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .lut_mask = 64'h2000200000000000;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y18_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~1 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~1_combout  = ( \u0|mm_interconnect_0|cmd_mux|saved_grant [0] & ( 
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout  & ( !\u0|mm_interconnect_0|cmd_mux|saved_grant [1] ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux|saved_grant [0] & ( 
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout  & ( !\u0|mm_interconnect_0|cmd_mux|saved_grant [1] ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux|saved_grant [0] & ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout  & ( !\u0|mm_interconnect_0|cmd_mux|saved_grant [1] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~1 .lut_mask = 64'hF0F00000F0F0F0F0;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y18_N47
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y17_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~1_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~0_combout  & ( (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & 
// ((!\u0|mm_interconnect_0|led_pio_test_s1_agent|local_write~0_combout  $ (!\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [0])) # (\u0|mm_interconnect_0|led_pio_test_s1_agent|WideOr0~0_combout ))) ) ) # ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~0_combout  & ( (\u0|mm_interconnect_0|led_pio_test_s1_agent|WideOr0~0_combout  & !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent|WideOr0~0_combout ),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent|local_write~0_combout ),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [0]),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~1 .lut_mask = 64'h550055007D007D00;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y17_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & (((\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q )))) # 
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & (((\u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~1_combout )) # 
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ))) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ( (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & (((\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q )))) # 
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q  & 
// ((!\u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~1_combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .lut_mask = 64'h1D0C1D0C1D3F1D3F;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y17_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout  & ( 
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) ) # 
// ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout  )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .lut_mask = 64'hFFFFFFFF50505050;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y17_N53
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y17_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~0_combout  & ( 
// \u0|mm_interconnect_0|led_pio_test_s1_agent|WideOr0~0_combout  & ( (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used 
// [1]) ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~0_combout  & ( \u0|mm_interconnect_0|led_pio_test_s1_agent|WideOr0~0_combout  & ( 
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # ( 
// \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~0_combout  & ( !\u0|mm_interconnect_0|led_pio_test_s1_agent|WideOr0~0_combout  & ( (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) 
// # ((!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] $ 
// (!\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [0])))) ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~0_combout  & ( !\u0|mm_interconnect_0|led_pio_test_s1_agent|WideOr0~0_combout  & ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  ) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [0]),
        .datae(!\u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~0_combout ),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent|WideOr0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hAAAAAEEAEEEEEEEE;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y19_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  & ( 
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  
// & \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout  
// & ( (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & ((\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) 
// # (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .lut_mask = 64'h030F030F000C000C;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y19_N26
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y19_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & ( 
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  $ 
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) # (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & ( 
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .lut_mask = 64'hA000A0005AA05AA0;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y19_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout  & ( (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) ) ) # ( 
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout  & ( 
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & ((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout 
// ) # (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ))) ) ) ) # ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout  & ( 
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ))) ) 
// ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datae(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h0100554400004444;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y19_N44
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y17_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  = ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( 
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ))) ) ) # ( 
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( (((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # 
// ((\u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~1_combout  & \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )))) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~1_combout ),
        .datae(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .extended_lut = "on";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .lut_mask = 64'h0808F0F00808F0FF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y19_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q 
//  & ( (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout 
// ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'h000A000A0A0A0A0A;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y24_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  = ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .lut_mask = 64'hAAAAAAAA00000000;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y24_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|update_grant~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|update_grant~0_combout  = ( \u0|mm_interconnect_0|cmd_mux|src_valid~0_combout  & ( \u0|mm_interconnect_0|cmd_mux|saved_grant [0] & ( (\u0|mm_interconnect_0|cmd_mux|src_payload [0] & 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux|src_valid~0_combout  & ( \u0|mm_interconnect_0|cmd_mux|saved_grant [0] & ( 
// (!\u0|mm_interconnect_0|cmd_demux|src0_valid~3_combout  & (((!\u0|mm_interconnect_0|cmd_mux|packet_in_progress~q )))) # (\u0|mm_interconnect_0|cmd_demux|src0_valid~3_combout  & (\u0|mm_interconnect_0|cmd_mux|src_payload [0] & 
// ((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout )))) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux|src_valid~0_combout  & ( !\u0|mm_interconnect_0|cmd_mux|saved_grant [0] & ( 
// (\u0|mm_interconnect_0|cmd_mux|src_payload [0] & !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux|src_valid~0_combout  & ( 
// !\u0|mm_interconnect_0|cmd_mux|saved_grant [0] & ( !\u0|mm_interconnect_0|cmd_mux|packet_in_progress~q  ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux|src_payload [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux|packet_in_progress~q ),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_demux|src0_valid~3_combout ),
        .datae(!\u0|mm_interconnect_0|cmd_mux|src_valid~0_combout ),
        .dataf(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux|update_grant~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|update_grant~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|update_grant~0 .lut_mask = 64'hCCCC5050CC505050;
defparam \u0|mm_interconnect_0|cmd_mux|update_grant~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y24_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg~2 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg~2_combout  = ( \u0|mm_interconnect_0|cmd_mux|update_grant~0_combout  & ( (!\u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg~0_combout  & (!\u0|mm_interconnect_0|cmd_mux|arb|grant[1]~0_combout )) # 
// (\u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg~0_combout  & ((\u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg [0]))) ) ) # ( !\u0|mm_interconnect_0|cmd_mux|update_grant~0_combout  & ( \u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg [0] ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux|arb|grant[1]~0_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux|update_grant~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg~2 .lut_mask = 64'h00FF00FFA0F5A0F5;
defparam \u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y24_N47
dffeas \u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y24_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|arb|grant[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|arb|grant[1]~0_combout  = ( \u0|mm_interconnect_0|cmd_demux|src0_valid~3_combout  & ( (\u0|mm_interconnect_0|cmd_demux_001|src0_valid~1_combout  & \u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg [1]) ) ) # ( 
// !\u0|mm_interconnect_0|cmd_demux|src0_valid~3_combout  & ( (\u0|mm_interconnect_0|cmd_demux_001|src0_valid~1_combout  & ((!\u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg [0]) # (\u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg [1]))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg [0]),
        .datac(!\u0|mm_interconnect_0|cmd_demux_001|src0_valid~1_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_demux|src0_valid~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux|arb|grant[1]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|arb|grant[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|arb|grant[1]~0 .lut_mask = 64'h0C0F0C0F000F000F;
defparam \u0|mm_interconnect_0|cmd_mux|arb|grant[1]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y24_N14
dffeas \u0|mm_interconnect_0|cmd_mux|saved_grant[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux|arb|grant[1]~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|cmd_mux|update_grant~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|saved_grant[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux|saved_grant[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X28_Y17_N23
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y17_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~1 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~1_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & ( (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used 
// [1]) # (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][69]~q ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & ( 
// (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][69]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][69]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y17_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][69]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][69]~feeder_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~1_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][69]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][69]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][69]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][69]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y17_N50
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][69] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][69]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][69]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][69] .power_up = "low";
// synopsys translate_on

// Location: FF_X27_Y17_N41
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][68] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][68]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][68] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][68] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y17_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~2 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~2_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] & ( (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used 
// [1]) # (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][68]~q ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] & ( 
// (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][68]~q ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][68]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~2 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y17_N32
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][68] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~2_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][68]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][68] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][68] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y17_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux|src0_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout  = ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][66]~q  & ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][68]~q  & ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][69]~q  ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][69]~q ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][66]~q ),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][68]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux|src0_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux|src0_valid~0 .lut_mask = 64'h00000000F0F00000;
defparam \u0|mm_interconnect_0|rsp_demux|src0_valid~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y26_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux|src0_valid~1 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout  = ( !\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout  & ( \u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout  ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux|src0_valid~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux|src0_valid~1 .lut_mask = 64'h5555000055550000;
defparam \u0|mm_interconnect_0|rsp_demux|src0_valid~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y26_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[114]~45 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[114]~45_combout  = (!\u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout  & (\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout  & ((\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][114]~q )))) # 
// (\u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout  & (((\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout  & \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][114]~q )) # 
// (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][114]~q )))

        .dataa(!\u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout ),
        .datab(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout ),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][114]~q ),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][114]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data[114]~45_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[114]~45 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[114]~45 .lut_mask = 64'h0537053705370537;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[114]~45 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y24_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[114]~47 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[114]~47_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][114]~q  & ( \u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout  & ( 
// (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][114]~q ) # (\u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout ) ) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][114]~q  & ( 
// \u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout  & ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][114]~q  ) ) ) # ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][114]~q  & ( 
// !\u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout  & ( \u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout  ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout ),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][114]~q ),
        .datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][114]~q ),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data[114]~47_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[114]~47 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[114]~47 .lut_mask = 64'h0000555500FF55FF;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[114]~47 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y22_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[114]~48 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[114]~48_combout  = ( \u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout  & ( ((\u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout  & \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][114]~q )) # 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][114]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout  & ( (\u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout  & 
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][114]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][114]~q ),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][114]~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data[114]~48_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[114]~48 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[114]~48 .lut_mask = 64'h0505050537373737;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[114]~48 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y28_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[114]~46 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[114]~46_combout  = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][114]~q  & ( \u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout  & ( 
// (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][114]~q ) # (\u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout ) ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][114]~q  & ( 
// \u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout  & ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][114]~q  ) ) ) # ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][114]~q  & ( 
// !\u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout  & ( \u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout  ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][114]~q ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][114]~q ),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data[114]~46_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[114]~46 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[114]~46 .lut_mask = 64'h000055550F0F5F5F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[114]~46 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y26_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[114]~49 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[114]~49_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][114]~q  & ( \u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout  ) ) # ( 
// !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][114]~q  & ( \u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout  & ( (\u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout  & 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][114]~q ) ) ) ) # ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][114]~q  & ( !\u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout  & ( 
// (\u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout  & \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][114]~q ) ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][114]~q  & ( 
// !\u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout  & ( (\u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout  & \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][114]~q ) ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][114]~q ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][114]~q ),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data[114]~49_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[114]~49 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[114]~49 .lut_mask = 64'h030303030303FFFF;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[114]~49 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y26_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[114] (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data [114] = ( \u0|mm_interconnect_0|rsp_mux|src_data[114]~49_combout  ) # ( !\u0|mm_interconnect_0|rsp_mux|src_data[114]~49_combout  & ( (((\u0|mm_interconnect_0|rsp_mux|src_data[114]~46_combout ) # 
// (\u0|mm_interconnect_0|rsp_mux|src_data[114]~48_combout )) # (\u0|mm_interconnect_0|rsp_mux|src_data[114]~47_combout )) # (\u0|mm_interconnect_0|rsp_mux|src_data[114]~45_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_mux|src_data[114]~45_combout ),
        .datab(!\u0|mm_interconnect_0|rsp_mux|src_data[114]~47_combout ),
        .datac(!\u0|mm_interconnect_0|rsp_mux|src_data[114]~48_combout ),
        .datad(!\u0|mm_interconnect_0|rsp_mux|src_data[114]~46_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_mux|src_data[114]~49_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data [114]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[114] .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[114] .lut_mask = 64'h7FFF7FFFFFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[114] .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y26_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_data[113] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|src_data [113] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [8] & ( ((\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [8])) # (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_ARID [8] & ( (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [8]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [8]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [8]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_018|src_data [113]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[113] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[113] .lut_mask = 64'h0505050537373737;
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[113] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y26_N35
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_018|src_data [113]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .power_up = "low";
// synopsys translate_on

// Location: FF_X30_Y26_N14
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~18_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][113]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][113] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y26_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~18 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~18_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][113]~q  ) ) # ( 
// !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][113]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~18 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~18 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y26_N14
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][113] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~18_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][113]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][113] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y26_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[113]~44 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[113]~44_combout  = ( \u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout  & ( ((\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][113]~q  & 
// \u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout )) # (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][113]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout  & ( 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][113]~q  & \u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][113]~q ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][113]~q ),
        .datad(!\u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data[113]~44_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[113]~44 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[113]~44 .lut_mask = 64'h000F000F333F333F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[113]~44 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y22_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[113]~43 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[113]~43_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][113]~q  & ( ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][113]~q  & 
// \u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout )) # (\u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][113]~q  & ( 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][113]~q  & \u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][113]~q ),
        .datab(!\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout ),
        .datac(!\u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][113]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data[113]~43_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[113]~43 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[113]~43 .lut_mask = 64'h111111111F1F1F1F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[113]~43 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y26_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[113]~40 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[113]~40_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][113]~q  & ( ((\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][113]~q  & 
// \u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout )) # (\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout ) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][113]~q  & ( 
// (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][113]~q  & \u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][113]~q ),
        .datab(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout ),
        .datac(!\u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][113]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data[113]~40_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[113]~40 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[113]~40 .lut_mask = 64'h0505050537373737;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[113]~40 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y24_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[113]~42 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[113]~42_combout  = ( \u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout  & ( ((\u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout  & 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][113]~q )) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][113]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout  & ( 
// (\u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout  & \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][113]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][113]~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout ),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][113]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data[113]~42_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[113]~42 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[113]~42 .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[113]~42 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y28_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[113]~41 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[113]~41_combout  = ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][113]~q  & ( ((\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][113]~q  & 
// \u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout )) # (\u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][113]~q  & ( 
// (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][113]~q  & \u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout ),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][113]~q ),
        .datad(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][113]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data[113]~41_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[113]~41 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[113]~41 .lut_mask = 64'h000F000F333F333F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[113]~41 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y26_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[113] (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data [113] = ( \u0|mm_interconnect_0|rsp_mux|src_data[113]~42_combout  & ( \u0|mm_interconnect_0|rsp_mux|src_data[113]~41_combout  ) ) # ( !\u0|mm_interconnect_0|rsp_mux|src_data[113]~42_combout  & ( 
// \u0|mm_interconnect_0|rsp_mux|src_data[113]~41_combout  ) ) # ( \u0|mm_interconnect_0|rsp_mux|src_data[113]~42_combout  & ( !\u0|mm_interconnect_0|rsp_mux|src_data[113]~41_combout  ) ) # ( !\u0|mm_interconnect_0|rsp_mux|src_data[113]~42_combout  & ( 
// !\u0|mm_interconnect_0|rsp_mux|src_data[113]~41_combout  & ( ((\u0|mm_interconnect_0|rsp_mux|src_data[113]~40_combout ) # (\u0|mm_interconnect_0|rsp_mux|src_data[113]~43_combout )) # (\u0|mm_interconnect_0|rsp_mux|src_data[113]~44_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_mux|src_data[113]~44_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|rsp_mux|src_data[113]~43_combout ),
        .datad(!\u0|mm_interconnect_0|rsp_mux|src_data[113]~40_combout ),
        .datae(!\u0|mm_interconnect_0|rsp_mux|src_data[113]~42_combout ),
        .dataf(!\u0|mm_interconnect_0|rsp_mux|src_data[113]~41_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data [113]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[113] .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[113] .lut_mask = 64'h5FFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[113] .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y30_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|src0_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|src0_valid~0_combout  = ( \u0|mm_interconnect_0|router_001|Equal2~1_combout  & ( \u0|mm_interconnect_0|router_001|Equal1~3_combout  & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & 
// (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & !\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]))) ) ) ) # ( !\u0|mm_interconnect_0|router_001|Equal2~1_combout  & ( \u0|mm_interconnect_0|router_001|Equal1~3_combout  
// & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & !\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]))) ) ) ) # ( \u0|mm_interconnect_0|router_001|Equal2~1_combout  & ( 
// !\u0|mm_interconnect_0|router_001|Equal1~3_combout  & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & !\u0|hps_0|fpga_interfaces|h2f_ARADDR [18])) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & 
// (\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [18])) ) ) ) # ( !\u0|mm_interconnect_0|router_001|Equal2~1_combout  & ( !\u0|mm_interconnect_0|router_001|Equal1~3_combout  ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),
        .datae(!\u0|mm_interconnect_0|router_001|Equal2~1_combout ),
        .dataf(!\u0|mm_interconnect_0|router_001|Equal1~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux_001|src0_valid~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|src0_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|src0_valid~0 .lut_mask = 64'hFFFF818180008000;
defparam \u0|mm_interconnect_0|cmd_demux_001|src0_valid~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y30_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|src0_valid~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|src0_valid~1_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [0] & ( (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & \u0|mm_interconnect_0|cmd_demux_001|src0_valid~0_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [0] & ( (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & (\u0|mm_interconnect_0|cmd_demux_001|src0_valid~0_combout  & 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q )) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_demux_001|src0_valid~0_combout ),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux_001|src0_valid~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|src0_valid~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|src0_valid~1 .lut_mask = 64'h0500050005050505;
defparam \u0|mm_interconnect_0|cmd_demux_001|src0_valid~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y24_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg~0_combout  = ( !\u0|mm_interconnect_0|cmd_demux|src0_valid~3_combout  & ( !\u0|mm_interconnect_0|cmd_demux_001|src0_valid~1_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_demux_001|src0_valid~1_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_demux|src0_valid~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg~0 .lut_mask = 64'hF0F0F0F000000000;
defparam \u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y24_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg~1_combout  = ( \u0|mm_interconnect_0|cmd_mux|update_grant~0_combout  & ( (!\u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg~0_combout  & (\u0|mm_interconnect_0|cmd_mux|arb|grant[0]~1_combout )) # 
// (\u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg~0_combout  & ((\u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg [1]))) ) ) # ( !\u0|mm_interconnect_0|cmd_mux|update_grant~0_combout  & ( \u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg [1] ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux|arb|grant[0]~1_combout ),
        .datac(!\u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg~0_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux|update_grant~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg~1 .lut_mask = 64'h00FF00FF303F303F;
defparam \u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y24_N2
dffeas \u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y24_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|arb|grant[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|arb|grant[0]~1_combout  = ( \u0|mm_interconnect_0|cmd_demux|src0_valid~3_combout  & ( (!\u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg [0]) # ((\u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg [1] & 
// !\u0|mm_interconnect_0|cmd_demux_001|src0_valid~1_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg [0]),
        .datad(!\u0|mm_interconnect_0|cmd_demux_001|src0_valid~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_demux|src0_valid~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux|arb|grant[0]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|arb|grant[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|arb|grant[0]~1 .lut_mask = 64'h00000000F5F0F5F0;
defparam \u0|mm_interconnect_0|cmd_mux|arb|grant[0]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y24_N17
dffeas \u0|mm_interconnect_0|cmd_mux|saved_grant[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux|arb|grant[0]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|cmd_mux|update_grant~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|saved_grant[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux|saved_grant[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y26_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|src_data[112] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|src_data [112] = (!\u0|mm_interconnect_0|cmd_mux|saved_grant [0] & (\u0|mm_interconnect_0|cmd_mux|saved_grant [1] & ((\u0|hps_0|fpga_interfaces|h2f_ARID [7])))) # (\u0|mm_interconnect_0|cmd_mux|saved_grant [0] & 
// (((\u0|mm_interconnect_0|cmd_mux|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [7])) # (\u0|hps_0|fpga_interfaces|h2f_AWID [7])))

        .dataa(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [7]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [7]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux|src_data [112]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|src_data[112] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|src_data[112] .lut_mask = 64'h0537053705370537;
defparam \u0|mm_interconnect_0|cmd_mux|src_data[112] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y26_N50
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux|src_data [112]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .power_up = "low";
// synopsys translate_on

// Location: FF_X23_Y26_N35
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~17_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][112]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][112] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y26_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~17 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~17_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][112]~q  & ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] ) ) # ( 
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][112]~q  & ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg 
// [112] ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][112]~q  & ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & ( 
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112] ) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][112]~q ),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~17 .lut_mask = 64'h555555550000FFFF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~17 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y26_N11
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][112] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~17_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][112]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][112] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y26_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[112]~35 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[112]~35_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][112]~q  & ( ((\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][112]~q  & 
// \u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout )) # (\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout ) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][112]~q  & ( 
// (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][112]~q  & \u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][112]~q ),
        .datac(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout ),
        .datad(!\u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][112]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data[112]~35_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[112]~35 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[112]~35 .lut_mask = 64'h003300330F3F0F3F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[112]~35 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y28_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[112]~36 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[112]~36_combout  = ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][112]~q  & ( ((\u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout  & 
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][112]~q )) # (\u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][112]~q  & ( 
// (\u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout  & \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][112]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout ),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][112]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][112]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data[112]~36_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[112]~36 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[112]~36 .lut_mask = 64'h005500550F5F0F5F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[112]~36 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y23_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[112]~38 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[112]~38_combout  = ( \u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout  & ( ((\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout  & \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][112]~q 
// )) # (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][112]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout  & ( (\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout  & 
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][112]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout ),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][112]~q ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][112]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data[112]~38_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[112]~38 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[112]~38 .lut_mask = 64'h003300330F3F0F3F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[112]~38 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y24_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[112]~37 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[112]~37_combout  = ( \u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout  & ( ((\u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout  & 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][112]~q )) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][112]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout  & ( 
// (\u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout  & \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][112]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][112]~q ),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][112]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data[112]~37_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[112]~37 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[112]~37 .lut_mask = 64'h005500550F5F0F5F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[112]~37 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y26_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[112]~39 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[112]~39_combout  = ( \u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout  & ( ((\u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout  & \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][112]~q )) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][112]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout  & ( (\u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout  & 
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][112]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][112]~q ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][112]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data[112]~39_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[112]~39 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[112]~39 .lut_mask = 64'h0505050505FF05FF;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[112]~39 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y26_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[112] (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data [112] = ( \u0|mm_interconnect_0|rsp_mux|src_data[112]~39_combout  ) # ( !\u0|mm_interconnect_0|rsp_mux|src_data[112]~39_combout  & ( (((\u0|mm_interconnect_0|rsp_mux|src_data[112]~37_combout ) # 
// (\u0|mm_interconnect_0|rsp_mux|src_data[112]~38_combout )) # (\u0|mm_interconnect_0|rsp_mux|src_data[112]~36_combout )) # (\u0|mm_interconnect_0|rsp_mux|src_data[112]~35_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_mux|src_data[112]~35_combout ),
        .datab(!\u0|mm_interconnect_0|rsp_mux|src_data[112]~36_combout ),
        .datac(!\u0|mm_interconnect_0|rsp_mux|src_data[112]~38_combout ),
        .datad(!\u0|mm_interconnect_0|rsp_mux|src_data[112]~37_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_mux|src_data[112]~39_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data [112]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[112] .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[112] .lut_mask = 64'h7FFF7FFFFFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[112] .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y31_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal1~2 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal1~2_combout  = ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [15] & ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [13] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [13]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [15]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router_001|Equal1~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal1~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal1~2 .lut_mask = 64'hF0F0F0F000000000;
defparam \u0|mm_interconnect_0|router_001|Equal1~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y31_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal3~0 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal3~0_combout  = ( \u0|mm_interconnect_0|router_001|Equal1~1_combout  & ( \u0|mm_interconnect_0|router_001|Equal1~0_combout  & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & 
// (\u0|mm_interconnect_0|router_001|Equal1~2_combout  & \u0|hps_0|fpga_interfaces|h2f_ARADDR [17])) ) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|router_001|Equal1~2_combout ),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),
        .datae(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),
        .dataf(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router_001|Equal3~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal3~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal3~0 .lut_mask = 64'h000000000000000A;
defparam \u0|mm_interconnect_0|router_001|Equal3~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y31_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|src10_valid~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|src10_valid~1_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [10] & ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & ( (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & 
// (\u0|mm_interconnect_0|router_001|Equal3~0_combout  & !\u0|hps_0|fpga_interfaces|h2f_ARADDR [18])) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [10] & ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & ( 
// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q  & (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & (\u0|mm_interconnect_0|router_001|Equal3~0_combout  & !\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]))) ) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
        .datac(!\u0|mm_interconnect_0|router_001|Equal3~0_combout ),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),
        .datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [10]),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux_001|src10_valid~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|src10_valid~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|src10_valid~1 .lut_mask = 64'h0000000002000300;
defparam \u0|mm_interconnect_0|cmd_demux_001|src10_valid~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y23_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|packet_in_progress~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|packet_in_progress~0_combout  = ( !\u0|mm_interconnect_0|cmd_mux_010|update_grant~0_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_010|update_grant~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_010|packet_in_progress~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|packet_in_progress~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|packet_in_progress~0 .lut_mask = 64'hFFFFFFFF00000000;
defparam \u0|mm_interconnect_0|cmd_mux_010|packet_in_progress~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y23_N40
dffeas \u0|mm_interconnect_0|cmd_mux_010|packet_in_progress (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_010|packet_in_progress~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_010|packet_in_progress~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|packet_in_progress .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_010|packet_in_progress .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y23_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|update_grant~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|update_grant~0_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & ( \u0|mm_interconnect_0|cmd_mux_010|src_valid~1_combout  & ( 
// \u0|mm_interconnect_0|cmd_mux_010|src_payload [0] ) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & ( \u0|mm_interconnect_0|cmd_mux_010|src_valid~1_combout  & ( 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & \u0|mm_interconnect_0|cmd_mux_010|src_payload [0]) ) ) ) # ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & ( !\u0|mm_interconnect_0|cmd_mux_010|src_valid~1_combout  & ( (!\u0|mm_interconnect_0|cmd_mux_010|src_valid~0_combout  & 
// (!\u0|mm_interconnect_0|cmd_mux_010|packet_in_progress~q )) # (\u0|mm_interconnect_0|cmd_mux_010|src_valid~0_combout  & ((\u0|mm_interconnect_0|cmd_mux_010|src_payload [0]))) ) ) ) # ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & ( !\u0|mm_interconnect_0|cmd_mux_010|src_valid~1_combout  & ( (!\u0|mm_interconnect_0|cmd_mux_010|src_valid~0_combout  & 
// (!\u0|mm_interconnect_0|cmd_mux_010|packet_in_progress~q )) # (\u0|mm_interconnect_0|cmd_mux_010|src_valid~0_combout  & (((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & 
// \u0|mm_interconnect_0|cmd_mux_010|src_payload [0])))) ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_010|packet_in_progress~q ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_010|src_valid~0_combout ),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_010|src_payload [0]),
        .datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_010|src_valid~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_010|update_grant~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|update_grant~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|update_grant~0 .lut_mask = 64'h888B88BB000F00FF;
defparam \u0|mm_interconnect_0|cmd_mux_010|update_grant~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y22_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_010|update_grant~0_combout  & ( ((\u0|mm_interconnect_0|cmd_demux|src10_valid~0_combout  & \u0|mm_interconnect_0|router|Equal16~0_combout )) # 
// (\u0|mm_interconnect_0|cmd_demux_001|src10_valid~1_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_demux_001|src10_valid~1_combout ),
        .datab(!\u0|mm_interconnect_0|cmd_demux|src10_valid~0_combout ),
        .datac(!\u0|mm_interconnect_0|router|Equal16~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_010|update_grant~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg~0 .lut_mask = 64'h0000000057575757;
defparam \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y22_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg~2 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg~2_combout  = ( \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg~0_combout  & ( !\u0|mm_interconnect_0|cmd_mux_010|arb|grant[1]~0_combout  ) ) # ( 
// !\u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg~0_combout  & ( \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg [0] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_010|arb|grant[1]~0_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg~2 .lut_mask = 64'h00FF00FFF0F0F0F0;
defparam \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y22_N44
dffeas \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y22_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg~1_combout  = ( \u0|mm_interconnect_0|cmd_mux_010|arb|grant[0]~1_combout  & ( (\u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg [1]) # 
// (\u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg~0_combout ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_010|arb|grant[0]~1_combout  & ( (!\u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg~0_combout  & 
// \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg [1]) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg~0_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_010|arb|grant[0]~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg~1 .lut_mask = 64'h00F000F00FFF0FFF;
defparam \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y22_N11
dffeas \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y22_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|arb|grant[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|arb|grant[1]~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg [1] & ( \u0|mm_interconnect_0|cmd_demux_001|src10_valid~1_combout  ) ) # ( !\u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg [1] & ( 
// (\u0|mm_interconnect_0|cmd_demux_001|src10_valid~1_combout  & (!\u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg [0] & ((!\u0|mm_interconnect_0|cmd_demux|src10_valid~0_combout ) # (!\u0|mm_interconnect_0|router|Equal16~0_combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_demux_001|src10_valid~1_combout ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg [0]),
        .datac(!\u0|mm_interconnect_0|cmd_demux|src10_valid~0_combout ),
        .datad(!\u0|mm_interconnect_0|router|Equal16~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_010|arb|grant[1]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|arb|grant[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|arb|grant[1]~0 .lut_mask = 64'h4440444055555555;
defparam \u0|mm_interconnect_0|cmd_mux_010|arb|grant[1]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y22_N41
dffeas \u0|mm_interconnect_0|cmd_mux_010|saved_grant[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_010|arb|grant[1]~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|cmd_mux_010|update_grant~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|saved_grant[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_010|saved_grant[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y24_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_data[111] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_data [111] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [6] & ( ((\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [6])) # (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_ARID [6] & ( (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [6]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [6]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [6]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_010|src_data [111]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[111] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[111] .lut_mask = 64'h0505050537373737;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[111] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y24_N35
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_010|src_data [111]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .power_up = "low";
// synopsys translate_on

// Location: FF_X22_Y24_N11
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~16_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][111]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][111] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y24_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~16 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~16_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][111]~q  & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] ) ) # ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][111]~q  & ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] ) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][111]~q  & ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
        .datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][111]~q ),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~16 .lut_mask = 64'h00FF00FF0000FFFF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~16 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y24_N38
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][111] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~16_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][111]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][111] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y24_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[111]~32 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[111]~32_combout  = ( \u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout  & ( ((\u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout  & 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][111]~q )) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][111]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout  & ( 
// (\u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout  & \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][111]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout ),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][111]~q ),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][111]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data[111]~32_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[111]~32 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[111]~32 .lut_mask = 64'h0303030303FF03FF;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[111]~32 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y29_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[111]~31 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[111]~31_combout  = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][111]~q  & ( ((\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][111]~q  & 
// \u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout )) # (\u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][111]~q  & ( 
// (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][111]~q  & \u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][111]~q ),
        .datab(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout ),
        .datac(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][111]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data[111]~31_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[111]~31 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[111]~31 .lut_mask = 64'h111111111F1F1F1F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[111]~31 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y26_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[111]~30 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[111]~30_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][111]~q  & ( \u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout  ) ) # ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][111]~q  & ( \u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout  & ( (\u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout  & 
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][111]~q ) ) ) ) # ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][111]~q  & ( !\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout  & ( 
// (\u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout  & \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][111]~q ) ) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][111]~q  & ( 
// !\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout  & ( (\u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout  & \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][111]~q ) ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout ),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][111]~q ),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][111]~q ),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data[111]~30_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[111]~30 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[111]~30 .lut_mask = 64'h111111111111FFFF;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[111]~30 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y26_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[111]~34 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[111]~34_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][111]~q  & ( ((\u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout  & 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][111]~q )) # (\u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][111]~q  & ( 
// (\u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout  & \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][111]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][111]~q ),
        .datae(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][111]~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data[111]~34_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[111]~34 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[111]~34 .lut_mask = 64'h000F555F000F555F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[111]~34 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y23_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[111]~33 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[111]~33_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][111]~q  & ( ((\u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout  & 
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][111]~q )) # (\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][111]~q  & ( 
// (\u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout  & \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][111]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout ),
        .datac(!\u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout ),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][111]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][111]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data[111]~33_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[111]~33 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[111]~33 .lut_mask = 64'h000F000F333F333F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[111]~33 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y26_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[111] (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data [111] = ( \u0|mm_interconnect_0|rsp_mux|src_data[111]~33_combout  ) # ( !\u0|mm_interconnect_0|rsp_mux|src_data[111]~33_combout  & ( (((\u0|mm_interconnect_0|rsp_mux|src_data[111]~34_combout ) # 
// (\u0|mm_interconnect_0|rsp_mux|src_data[111]~30_combout )) # (\u0|mm_interconnect_0|rsp_mux|src_data[111]~31_combout )) # (\u0|mm_interconnect_0|rsp_mux|src_data[111]~32_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_mux|src_data[111]~32_combout ),
        .datab(!\u0|mm_interconnect_0|rsp_mux|src_data[111]~31_combout ),
        .datac(!\u0|mm_interconnect_0|rsp_mux|src_data[111]~30_combout ),
        .datad(!\u0|mm_interconnect_0|rsp_mux|src_data[111]~34_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_mux|src_data[111]~33_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data [111]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[111] .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[111] .lut_mask = 64'h7FFF7FFFFFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[111] .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y24_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_data[110] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_data [110] = ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_AWID [5] & ( (\u0|hps_0|fpga_interfaces|h2f_ARID [5]) # (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]) ) ) ) # ( 
// !\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_AWID [5] & ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & ( !\u0|hps_0|fpga_interfaces|h2f_AWID [5] & ( 
// \u0|hps_0|fpga_interfaces|h2f_ARID [5] ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARID [5]),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_010|src_data [110]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[110] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[110] .lut_mask = 64'h0000333355557777;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[110] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y24_N34
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_010|src_data [110]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y24_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~15 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~15_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110] & ( 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][110]~q ) ) ) # ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110] & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][110]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][110]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~15 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~15 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y24_N53
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][110] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~15_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][110]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][110] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y24_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[110]~27 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[110]~27_combout  = ( \u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout  & ( ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][110]~q  & 
// \u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout )) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][110]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout  & ( 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][110]~q  & \u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][110]~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout ),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][110]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data[110]~27_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[110]~27 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[110]~27 .lut_mask = 64'h0505050505FF05FF;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[110]~27 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y26_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[110]~29 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[110]~29_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][110]~q  & ( ((\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][110]~q  & 
// \u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout )) # (\u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][110]~q  & ( 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][110]~q  & \u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][110]~q ),
        .datad(!\u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][110]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data[110]~29_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[110]~29 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[110]~29 .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[110]~29 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y26_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[110]~25 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[110]~25_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][110]~q  & ( ((\u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout  & 
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][110]~q )) # (\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout ) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][110]~q  & ( 
// (\u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout  & \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][110]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout ),
        .datac(!\u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout ),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][110]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][110]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data[110]~25_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[110]~25 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[110]~25 .lut_mask = 64'h000F000F333F333F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[110]~25 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y28_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[110]~26 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[110]~26_combout  = ( \u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout  & ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][110]~q  & ( (\u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout ) # 
// (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][110]~q ) ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout  & ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][110]~q  & ( 
// \u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout  ) ) ) # ( \u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout  & ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][110]~q  & ( 
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][110]~q  ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][110]~q ),
        .datac(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout ),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][110]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data[110]~26_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[110]~26 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[110]~26 .lut_mask = 64'h000033330F0F3F3F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[110]~26 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y23_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[110]~28 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[110]~28_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][110]~q  & ( ((\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout  & 
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][110]~q )) # (\u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][110]~q  & ( 
// (\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout  & \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][110]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][110]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][110]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data[110]~28_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[110]~28 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[110]~28 .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[110]~28 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y26_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[110] (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data [110] = ( \u0|mm_interconnect_0|rsp_mux|src_data[110]~28_combout  ) # ( !\u0|mm_interconnect_0|rsp_mux|src_data[110]~28_combout  & ( (((\u0|mm_interconnect_0|rsp_mux|src_data[110]~26_combout ) # 
// (\u0|mm_interconnect_0|rsp_mux|src_data[110]~25_combout )) # (\u0|mm_interconnect_0|rsp_mux|src_data[110]~29_combout )) # (\u0|mm_interconnect_0|rsp_mux|src_data[110]~27_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_mux|src_data[110]~27_combout ),
        .datab(!\u0|mm_interconnect_0|rsp_mux|src_data[110]~29_combout ),
        .datac(!\u0|mm_interconnect_0|rsp_mux|src_data[110]~25_combout ),
        .datad(!\u0|mm_interconnect_0|rsp_mux|src_data[110]~26_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_mux|src_data[110]~28_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data [110]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[110] .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[110] .lut_mask = 64'h7FFF7FFFFFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[110] .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y28_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector11~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector11~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~57_sumout  & ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~3_combout  ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~57_sumout  & ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~3_combout  & ( !\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] ) ) ) # ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~57_sumout  & ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~3_combout  & ( \u0|hps_0|fpga_interfaces|h2f_AWBURST [0] ) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~57_sumout ),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector11~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector11~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector11~0 .lut_mask = 64'h00005555AAAAFFFF;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector11~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y28_N47
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[18] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector11~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [18]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[18] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[18] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y28_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~3 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~3_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [18] & ( \u0|hps_0|fpga_interfaces|h2f_AWADDR [18] ) ) # ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [18] & ( \u0|hps_0|fpga_interfaces|h2f_AWADDR [18] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  ) ) ) # ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [18] & ( !\u0|hps_0|fpga_interfaces|h2f_AWADDR [18] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [18]),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [18]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~3 .lut_mask = 64'h00000F0FF0F0FFFF;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y25_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|router|Equal13~0 (
// Equation(s):
// \u0|mm_interconnect_0|router|Equal13~0_combout  = ( \u0|mm_interconnect_0|router|Equal6~5_combout  & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout  & (\u0|mm_interconnect_0|router|Equal7~1_combout  & 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~3_combout )) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout ),
        .datac(!\u0|mm_interconnect_0|router|Equal7~1_combout ),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~3_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|router|Equal6~5_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router|Equal13~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router|Equal13~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router|Equal13~0 .lut_mask = 64'h0000000000030003;
defparam \u0|mm_interconnect_0|router|Equal13~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y25_N49
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[7] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|router|Equal13~0_combout ),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [7]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y25_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|src7_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|src7_valid~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout  & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q ) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [7]) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [7]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux|src7_valid~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|src7_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|src7_valid~0 .lut_mask = 64'h00000000FF0FFF0F;
defparam \u0|mm_interconnect_0|cmd_demux|src7_valid~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y27_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|arb|grant[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|arb|grant[0]~1_combout  = ( \u0|mm_interconnect_0|router|Equal13~0_combout  & ( (\u0|mm_interconnect_0|cmd_demux|src7_valid~0_combout  & ((!\u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg [0]) # 
// ((!\u0|mm_interconnect_0|cmd_demux_001|src7_valid~0_combout  & \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg [1])))) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg [0]),
        .datab(!\u0|mm_interconnect_0|cmd_demux_001|src7_valid~0_combout ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg [1]),
        .datad(!\u0|mm_interconnect_0|cmd_demux|src7_valid~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|router|Equal13~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_007|arb|grant[0]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|arb|grant[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|arb|grant[0]~1 .lut_mask = 64'h0000000000AE00AE;
defparam \u0|mm_interconnect_0|cmd_mux_007|arb|grant[0]~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y29_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|packet_in_progress~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|packet_in_progress~0_combout  = ( !\u0|mm_interconnect_0|cmd_mux_007|update_grant~0_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_007|update_grant~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_007|packet_in_progress~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|packet_in_progress~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|packet_in_progress~0 .lut_mask = 64'hFFFFFFFF00000000;
defparam \u0|mm_interconnect_0|cmd_mux_007|packet_in_progress~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y29_N37
dffeas \u0|mm_interconnect_0|cmd_mux_007|packet_in_progress (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_007|packet_in_progress~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_007|packet_in_progress~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|packet_in_progress .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_007|packet_in_progress .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y29_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|update_grant~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|update_grant~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_007|src_valid~0_combout  & ( \u0|mm_interconnect_0|cmd_mux_007|src_valid~1_combout  & ( (\u0|mm_interconnect_0|cmd_mux_007|src_payload [0] & 
// ((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ) # (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ))) ) ) 
// ) # ( !\u0|mm_interconnect_0|cmd_mux_007|src_valid~0_combout  & ( \u0|mm_interconnect_0|cmd_mux_007|src_valid~1_combout  & ( (\u0|mm_interconnect_0|cmd_mux_007|src_payload [0] & 
// ((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ) # (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ))) ) ) 
// ) # ( \u0|mm_interconnect_0|cmd_mux_007|src_valid~0_combout  & ( !\u0|mm_interconnect_0|cmd_mux_007|src_valid~1_combout  & ( (\u0|mm_interconnect_0|cmd_mux_007|src_payload [0] & 
// ((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ) # (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ))) ) ) 
// ) # ( !\u0|mm_interconnect_0|cmd_mux_007|src_valid~0_combout  & ( !\u0|mm_interconnect_0|cmd_mux_007|src_valid~1_combout  & ( !\u0|mm_interconnect_0|cmd_mux_007|packet_in_progress~q  ) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_007|src_payload [0]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_007|packet_in_progress~q ),
        .datae(!\u0|mm_interconnect_0|cmd_mux_007|src_valid~0_combout ),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_007|src_valid~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_007|update_grant~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|update_grant~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|update_grant~0 .lut_mask = 64'hFF00070707070707;
defparam \u0|mm_interconnect_0|cmd_mux_007|update_grant~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y27_N32
dffeas \u0|mm_interconnect_0|cmd_mux_007|saved_grant[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_007|arb|grant[0]~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|cmd_mux_007|update_grant~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|saved_grant[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_007|saved_grant[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y29_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|src_data[109] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|src_data [109] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [4] & ( ((\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [4])) # (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_AWID [4] & ( (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [4]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
        .datac(gnd),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [4]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_007|src_data [109]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[109] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[109] .lut_mask = 64'h0055005533773377;
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[109] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y29_N50
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_007|src_data [109]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .power_up = "low";
// synopsys translate_on

// Location: FF_X21_Y29_N2
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~14_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][109]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][109] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y29_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~14 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~14_combout  = (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109])) 
// # (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][109]~q )))

        .dataa(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
        .datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][109]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~14 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~14 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y29_N50
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][109] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~14_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][109]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][109] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y28_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[109]~21 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[109]~21_combout  = ( \u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout  & ( ((\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][109]~q  & \u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout )) # 
// (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][109]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout  & ( (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][109]~q  & 
// \u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][109]~q ),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][109]~q ),
        .datac(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data[109]~21_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[109]~21 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[109]~21 .lut_mask = 64'h0303030357575757;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[109]~21 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y26_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[109]~20 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[109]~20_combout  = ( \u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout  & ( ((\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout  & \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][109]~q )) # 
// (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][109]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout  & ( (\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout  & 
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][109]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][109]~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout ),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][109]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data[109]~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[109]~20 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[109]~20 .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[109]~20 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y26_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[109]~24 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[109]~24_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][109]~q  & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][109]~q  & ( 
// (\u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout ) # (\u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout ) ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][109]~q  & ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][109]~q  & ( \u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout  ) ) ) # ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][109]~q  & ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][109]~q  & ( \u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout  ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout ),
        .datac(!\u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][109]~q ),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][109]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data[109]~24_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[109]~24 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[109]~24 .lut_mask = 64'h000033330F0F3F3F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[109]~24 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y24_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[109]~22 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[109]~22_combout  = ( \u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout  & ( ((\u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout  & 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][109]~q )) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][109]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout  & ( 
// (\u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout  & \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][109]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][109]~q ),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][109]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data[109]~22_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[109]~22 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[109]~22 .lut_mask = 64'h005500550F5F0F5F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[109]~22 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y23_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[109]~23 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[109]~23_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][109]~q  & ( ((\u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout  & 
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][109]~q )) # (\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][109]~q  & ( 
// (\u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout  & \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][109]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout ),
        .datac(!\u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout ),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][109]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][109]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data[109]~23_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[109]~23 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[109]~23 .lut_mask = 64'h000F000F333F333F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[109]~23 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y26_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[109] (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data [109] = ( \u0|mm_interconnect_0|rsp_mux|src_data[109]~22_combout  & ( \u0|mm_interconnect_0|rsp_mux|src_data[109]~23_combout  ) ) # ( !\u0|mm_interconnect_0|rsp_mux|src_data[109]~22_combout  & ( 
// \u0|mm_interconnect_0|rsp_mux|src_data[109]~23_combout  ) ) # ( \u0|mm_interconnect_0|rsp_mux|src_data[109]~22_combout  & ( !\u0|mm_interconnect_0|rsp_mux|src_data[109]~23_combout  ) ) # ( !\u0|mm_interconnect_0|rsp_mux|src_data[109]~22_combout  & ( 
// !\u0|mm_interconnect_0|rsp_mux|src_data[109]~23_combout  & ( ((\u0|mm_interconnect_0|rsp_mux|src_data[109]~24_combout ) # (\u0|mm_interconnect_0|rsp_mux|src_data[109]~20_combout )) # (\u0|mm_interconnect_0|rsp_mux|src_data[109]~21_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_mux|src_data[109]~21_combout ),
        .datab(!\u0|mm_interconnect_0|rsp_mux|src_data[109]~20_combout ),
        .datac(!\u0|mm_interconnect_0|rsp_mux|src_data[109]~24_combout ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|rsp_mux|src_data[109]~22_combout ),
        .dataf(!\u0|mm_interconnect_0|rsp_mux|src_data[109]~23_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data [109]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[109] .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[109] .lut_mask = 64'h7F7FFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[109] .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y28_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector14~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector14~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [15] & ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~45_sumout  & ( ((\u0|hps_0|fpga_interfaces|h2f_AWADDR [15]) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q )) # (\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]) ) ) ) 
// # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [15] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~45_sumout  & ( ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  
// & \u0|hps_0|fpga_interfaces|h2f_AWADDR [15])) # (\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]) ) ) ) # ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [15] & ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~45_sumout  & ( (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & ((\u0|hps_0|fpga_interfaces|h2f_AWADDR [15]) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ))) ) ) 
// ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [15] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~45_sumout  & ( (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & 
// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & \u0|hps_0|fpga_interfaces|h2f_AWADDR [15])) ) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [15]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [15]),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~45_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector14~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector14~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector14~0 .lut_mask = 64'h08082A2A5D5D7F7F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector14~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y28_N5
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[15] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector14~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [15]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[15] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[15] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y28_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|router|Equal7~0 (
// Equation(s):
// \u0|mm_interconnect_0|router|Equal7~0_combout  = ( !\u0|hps_0|fpga_interfaces|h2f_AWADDR [13] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [13] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q 
//  & !\u0|hps_0|fpga_interfaces|h2f_AWADDR [15]) ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_AWADDR [13] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [13] & ( 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [15]) ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_AWADDR [13] & ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [13] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ((!\u0|hps_0|fpga_interfaces|h2f_AWADDR [15]))) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [15])) ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [15]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [15]),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [13]),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [13]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router|Equal7~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router|Equal7~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router|Equal7~0 .lut_mask = 64'hFC303030CC000000;
defparam \u0|mm_interconnect_0|router|Equal7~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y28_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|router|Equal6~4 (
// Equation(s):
// \u0|mm_interconnect_0|router|Equal6~4_combout  = ( \u0|hps_0|fpga_interfaces|h2f_AWADDR [10] & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [11] 
// & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [10])) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_AWADDR [10] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (!\u0|hps_0|fpga_interfaces|h2f_AWADDR 
// [11])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [11] & 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [10])))) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [11]),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [11]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [10]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [10]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router|Equal6~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router|Equal6~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router|Equal6~4 .lut_mask = 64'hB888B88830003000;
defparam \u0|mm_interconnect_0|router|Equal6~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y29_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|router|Equal6~1 (
// Equation(s):
// \u0|mm_interconnect_0|router|Equal6~1_combout  = ( \u0|hps_0|fpga_interfaces|h2f_AWADDR [7] & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [7] & 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [6])) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_AWADDR [7] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (!\u0|hps_0|fpga_interfaces|h2f_AWADDR 
// [6])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [7] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst 
// [6])))) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [6]),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [7]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [6]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [7]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router|Equal6~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router|Equal6~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router|Equal6~1 .lut_mask = 64'hD888D88850005000;
defparam \u0|mm_interconnect_0|router|Equal6~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y29_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|router|Equal6~2 (
// Equation(s):
// \u0|mm_interconnect_0|router|Equal6~2_combout  = ( \u0|hps_0|fpga_interfaces|h2f_AWADDR [9] & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [9] & 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [8])) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_AWADDR [9] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (!\u0|hps_0|fpga_interfaces|h2f_AWADDR 
// [8])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [9] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst 
// [8])))) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [8]),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [9]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [8]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [9]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router|Equal6~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router|Equal6~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router|Equal6~2 .lut_mask = 64'hD888D88850005000;
defparam \u0|mm_interconnect_0|router|Equal6~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y28_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|router|Equal6~3 (
// Equation(s):
// \u0|mm_interconnect_0|router|Equal6~3_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [12] & ( (!\u0|hps_0|fpga_interfaces|h2f_AWADDR [14] & (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  
// & !\u0|hps_0|fpga_interfaces|h2f_AWADDR [12])) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [12] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (!\u0|hps_0|fpga_interfaces|h2f_AWADDR 
// [14] & (!\u0|hps_0|fpga_interfaces|h2f_AWADDR [12]))) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [14])))) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [14]),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [12]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [14]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [12]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router|Equal6~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router|Equal6~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router|Equal6~3 .lut_mask = 64'hB380B38080808080;
defparam \u0|mm_interconnect_0|router|Equal6~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y25_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|router|Equal7~1 (
// Equation(s):
// \u0|mm_interconnect_0|router|Equal7~1_combout  = ( \u0|mm_interconnect_0|router|Equal6~2_combout  & ( \u0|mm_interconnect_0|router|Equal6~3_combout  & ( (\u0|mm_interconnect_0|router|Equal6~0_combout  & (\u0|mm_interconnect_0|router|Equal7~0_combout  & 
// (\u0|mm_interconnect_0|router|Equal6~4_combout  & \u0|mm_interconnect_0|router|Equal6~1_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|router|Equal6~0_combout ),
        .datab(!\u0|mm_interconnect_0|router|Equal7~0_combout ),
        .datac(!\u0|mm_interconnect_0|router|Equal6~4_combout ),
        .datad(!\u0|mm_interconnect_0|router|Equal6~1_combout ),
        .datae(!\u0|mm_interconnect_0|router|Equal6~2_combout ),
        .dataf(!\u0|mm_interconnect_0|router|Equal6~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router|Equal7~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router|Equal7~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router|Equal7~1 .lut_mask = 64'h0000000000000001;
defparam \u0|mm_interconnect_0|router|Equal7~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y25_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|router|Equal16~0 (
// Equation(s):
// \u0|mm_interconnect_0|router|Equal16~0_combout  = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout  & ( (\u0|mm_interconnect_0|router|Equal14~0_combout  & (\u0|mm_interconnect_0|router|Equal7~1_combout  & 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|router|Equal14~0_combout ),
        .datab(!\u0|mm_interconnect_0|router|Equal7~1_combout ),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router|Equal16~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router|Equal16~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router|Equal16~0 .lut_mask = 64'h0101010100000000;
defparam \u0|mm_interconnect_0|router|Equal16~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y25_N40
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[10] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|router|Equal16~0_combout ),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [10]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[10] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[10] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y23_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|src10_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|src10_valid~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout  & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q ) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [10]) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [10]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux|src10_valid~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|src10_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|src10_valid~0 .lut_mask = 64'h00000000FF0FFF0F;
defparam \u0|mm_interconnect_0|cmd_demux|src10_valid~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y22_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|arb|grant[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|arb|grant[0]~1_combout  = ( \u0|mm_interconnect_0|router|Equal16~0_combout  & ( \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg [1] & ( (\u0|mm_interconnect_0|cmd_demux|src10_valid~0_combout  & 
// ((!\u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg [0]) # (!\u0|mm_interconnect_0|cmd_demux_001|src10_valid~1_combout ))) ) ) ) # ( \u0|mm_interconnect_0|router|Equal16~0_combout  & ( !\u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg [1] & ( 
// (\u0|mm_interconnect_0|cmd_demux|src10_valid~0_combout  & !\u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg [0]) ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_demux|src10_valid~0_combout ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg [0]),
        .datad(!\u0|mm_interconnect_0|cmd_demux_001|src10_valid~1_combout ),
        .datae(!\u0|mm_interconnect_0|router|Equal16~0_combout ),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_010|arb|grant[0]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|arb|grant[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|arb|grant[0]~1 .lut_mask = 64'h0000303000003330;
defparam \u0|mm_interconnect_0|cmd_mux_010|arb|grant[0]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y22_N20
dffeas \u0|mm_interconnect_0|cmd_mux_010|saved_grant[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_010|arb|grant[0]~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|cmd_mux_010|update_grant~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|saved_grant[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_010|saved_grant[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X22_Y18_N8
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] .power_up = "low";
// synopsys translate_on

// Location: FF_X22_Y18_N47
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][68] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][68]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][68] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][68] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y18_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~2 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~2_combout  = (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68])) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & 
// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][68]~q )))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][68]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~2 .lut_mask = 64'h0C3F0C3F0C3F0C3F;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y17_N26
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][68] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~2_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][68]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][68] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][68] .power_up = "low";
// synopsys translate_on

// Location: FF_X19_Y17_N55
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][69] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][69]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][69] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y17_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~1_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & ( 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][69]~q ) ) ) # ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][69]~q  & 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][69]~q ),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h000F000FFF0FFF0F;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y17_N23
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][69] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][69]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][69] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y17_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_010|src0_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_010|src0_valid~0_combout  = ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][66]~q  & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][68]~q  & 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][69]~q ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][68]~q ),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][69]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][66]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_demux_010|src0_valid~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_010|src0_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_010|src0_valid~0 .lut_mask = 64'h0F000F0000000000;
defparam \u0|mm_interconnect_0|rsp_demux_010|src0_valid~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y17_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_010|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_010|WideOr0~0_combout  = (!\u0|mm_interconnect_0|rsp_demux_010|src0_valid~0_combout  & ((\u0|hps_0|fpga_interfaces|h2f_RREADY [0]))) # (\u0|mm_interconnect_0|rsp_demux_010|src0_valid~0_combout  & 
// (\u0|hps_0|fpga_interfaces|h2f_BREADY [0]))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|rsp_demux_010|src0_valid~0_combout ),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_BREADY [0]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_demux_010|WideOr0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_010|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_010|WideOr0~0 .lut_mask = 64'h03CF03CF03CF03CF;
defparam \u0|mm_interconnect_0|rsp_demux_010|WideOr0~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y17_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0_combout  = (\u0|mm_interconnect_0|rsp_demux_010|WideOr0~0_combout  & \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|comb~0_combout )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_010|WideOr0~0_combout ),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|comb~0_combout ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0 .lut_mask = 64'h0055005500550055;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y17_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used[1]~0_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout  & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|write~0_combout 
//  & ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]))) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|write~0_combout  & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [0])) ) ) # ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout  & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|write~0_combout  & 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0_combout  & ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1])))) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|write~0_combout  & 
// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0_combout  & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [0])) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0_combout  & 
// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]))))) ) )

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|write~0_combout ),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0_combout ),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [0]),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used[1]~0 .lut_mask = 64'h049D049D05AF05AF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used[1]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y17_N47
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X22_Y24_N56
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~13_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][108]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][108] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y24_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_data[108] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_data [108] = ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [3] ) ) # ( !\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [3] & ( 
// (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [3]) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & ( !\u0|hps_0|fpga_interfaces|h2f_ARID [3] & ( (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & 
// \u0|hps_0|fpga_interfaces|h2f_AWID [3]) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & ( !\u0|hps_0|fpga_interfaces|h2f_ARID [3] & ( (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [3]) ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [3]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_010|src_data [108]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[108] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[108] .lut_mask = 64'h050505050505FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[108] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y24_N55
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_010|src_data [108]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y24_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~13 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~13_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][108]~q  & ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108] ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][108]~q  & ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108] & ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] ) ) ) # ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][108]~q  & ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108] & ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][108]~q ),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~13 .lut_mask = 64'h00003333CCCCFFFF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~13 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y24_N56
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][108] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~13_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][108]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][108] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y24_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[108]~17 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[108]~17_combout  = ( \u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout  & ( ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][108]~q  & 
// \u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout )) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][108]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout  & ( 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][108]~q  & \u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][108]~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout ),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][108]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data[108]~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[108]~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[108]~17 .lut_mask = 64'h0505050505FF05FF;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[108]~17 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y26_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[108]~15 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[108]~15_combout  = ( \u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout  & ( ((\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout  & \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][108]~q )) # 
// (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][108]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout  & ( (\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout  & 
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][108]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout ),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][108]~q ),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][108]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data[108]~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[108]~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[108]~15 .lut_mask = 64'h003300330F3F0F3F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[108]~15 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y23_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[108]~18 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[108]~18_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][108]~q  & ( ((\u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout  & 
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][108]~q )) # (\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][108]~q  & ( 
// (\u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout  & \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][108]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout ),
        .datac(!\u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout ),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][108]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][108]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data[108]~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[108]~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[108]~18 .lut_mask = 64'h000F000F333F333F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[108]~18 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y26_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[108]~19 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[108]~19_combout  = ( \u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout  & ( ((\u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout  & \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][108]~q )) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][108]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout  & ( (\u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout  & 
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][108]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][108]~q ),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][108]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data[108]~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[108]~19 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[108]~19 .lut_mask = 64'h005500550F5F0F5F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[108]~19 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y29_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[108]~16 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[108]~16_combout  = ( \u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout  & ( ((\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][108]~q  & \u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout )) # 
// (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][108]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout  & ( (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][108]~q  & 
// \u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][108]~q ),
        .datac(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][108]~q ),
        .datad(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data[108]~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[108]~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[108]~16 .lut_mask = 64'h000F000F333F333F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[108]~16 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y26_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[108] (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data [108] = ( \u0|mm_interconnect_0|rsp_mux|src_data[108]~16_combout  ) # ( !\u0|mm_interconnect_0|rsp_mux|src_data[108]~16_combout  & ( (((\u0|mm_interconnect_0|rsp_mux|src_data[108]~19_combout ) # 
// (\u0|mm_interconnect_0|rsp_mux|src_data[108]~18_combout )) # (\u0|mm_interconnect_0|rsp_mux|src_data[108]~15_combout )) # (\u0|mm_interconnect_0|rsp_mux|src_data[108]~17_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_mux|src_data[108]~17_combout ),
        .datab(!\u0|mm_interconnect_0|rsp_mux|src_data[108]~15_combout ),
        .datac(!\u0|mm_interconnect_0|rsp_mux|src_data[108]~18_combout ),
        .datad(!\u0|mm_interconnect_0|rsp_mux|src_data[108]~19_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_mux|src_data[108]~16_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data [108]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[108] .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[108] .lut_mask = 64'h7FFF7FFFFFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[108] .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y18_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_data[33] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_data [33] = ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] ) # ( !\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_WSTRB [1] & \u0|mm_interconnect_0|cmd_mux_010|saved_grant 
// [0]) ) )

        .dataa(gnd),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [1]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
        .datae(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_010|src_data [33]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[33] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[33] .lut_mask = 64'h0033FFFF0033FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[33] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y18_N50
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_010|src_data [33]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y18_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q  & 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]))) ) ) ) # ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg 
// [0] & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg 
// [3] & !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2])) ) ) )

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0 .lut_mask = 64'h8800800000000000;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y18_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_write (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_write~combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|local_write~0_combout  & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0_combout  & 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0_combout ),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|local_write~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_write~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_write .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_write .lut_mask = 64'h00000000F000F000;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_write .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y14_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter~0_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg~0_combout  & ( 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override~q  & ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_write~combout  $ (\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [0])) # 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [1]))) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg~0_combout  & ( 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override~q  & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_write~combout  & ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [1]) # 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [0])))) ) )

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override~q ),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_write~combout ),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [0]),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter~0 .lut_mask = 64'h0111011141554155;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y14_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter~1_combout  = ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [0] & ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter~0_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [0]),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter~1 .lut_mask = 64'h00000000FFFF0000;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y14_N11
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y18_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0_combout  & ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  ) ) ) # ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0_combout  ) ) # ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0_combout  & ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  ) ) ) # ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0_combout  & ( 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~0_combout  & 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [0] $ (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68])))) ) ) )

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [0]),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~0_combout ),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hFF06FF00FFFFFF00;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y18_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  & ( 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) # 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ))) ) ) # ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  & ( 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .lut_mask = 64'h000C000C030F030F;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y18_N50
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y18_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout 
//  & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout  )

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .lut_mask = 64'hFFFFFFFF50505050;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y18_N35
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y18_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|local_write~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|local_write~0_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] & ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|local_write~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|local_write~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|local_write~0 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|local_write~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y18_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|write~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|write~0_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_read~0_combout  & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~4_combout  & ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] ) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_read~0_combout  & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~4_combout  & ( 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|local_write~0_combout  & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1])) ) ) ) # ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_read~0_combout  & ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~4_combout  & ( 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0_combout  & !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_read~0_combout  & ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~4_combout  & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|local_write~0_combout  & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0_combout  & 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]))) ) ) )

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|local_write~0_combout ),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0_combout ),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),
        .datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_read~0_combout ),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~4_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|write~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|write~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h010033000500FF00;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|write~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y17_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used[0]~1_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout  & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [0]) # 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|write~0_combout ) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout  & ( ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [0] & 
// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0_combout ) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1])))) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|write~0_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|write~0_combout ),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0_combout ),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h55DF55DF55FF55FF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y17_N41
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y17_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|rp_valid (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|rp_valid~combout  = ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg [0] & 
// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [0]) # (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][129]~q ))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [0]),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|rp_valid~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|rp_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|rp_valid .lut_mask = 64'hFC00FC0000000000;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|rp_valid .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y24_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_010|src0_valid~1 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout  = ( \u0|mm_interconnect_0|rsp_demux_010|src0_valid~0_combout  & ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|rp_valid~combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|rp_valid~combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_010|src0_valid~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_010|src0_valid~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_010|src0_valid~1 .lut_mask = 64'h00000000FF00FF00;
defparam \u0|mm_interconnect_0|rsp_demux_010|src0_valid~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y24_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[107]~12 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[107]~12_combout  = ( \u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout  & ( ((\u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout  & 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][107]~q )) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][107]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout  & ( 
// (\u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout  & \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][107]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout ),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][107]~q ),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][107]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data[107]~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[107]~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[107]~12 .lut_mask = 64'h003300330F3F0F3F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[107]~12 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y26_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[107]~10 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[107]~10_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][107]~q  & ( \u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout  & ( 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][107]~q ) # (\u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout ) ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][107]~q  & ( 
// \u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout  & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][107]~q  ) ) ) # ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][107]~q  & ( 
// !\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout  & ( \u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout  ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][107]~q ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][107]~q ),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data[107]~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[107]~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[107]~10 .lut_mask = 64'h000055550F0F5F5F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[107]~10 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y23_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[107]~13 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[107]~13_combout  = ( \u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout  & ( ((\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout  & \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][107]~q 
// )) # (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][107]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout  & ( (\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout  & 
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][107]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout ),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][107]~q ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][107]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data[107]~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[107]~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[107]~13 .lut_mask = 64'h003300330F3F0F3F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[107]~13 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y26_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[107]~14 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[107]~14_combout  = ( \u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout  & ( ((\u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout  & \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][107]~q )) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][107]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout  & ( (\u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout  & 
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][107]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][107]~q ),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][107]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data[107]~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[107]~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[107]~14 .lut_mask = 64'h005500550F5F0F5F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[107]~14 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y28_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[107]~11 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[107]~11_combout  = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][107]~q  & ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][107]~q  & ( 
// (\u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout ) # (\u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout ) ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][107]~q  & ( 
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][107]~q  & ( \u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout  ) ) ) # ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][107]~q  & ( 
// !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][107]~q  & ( \u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout  ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout ),
        .datac(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][107]~q ),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][107]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data[107]~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[107]~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[107]~11 .lut_mask = 64'h00000F0F33333F3F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[107]~11 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y26_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[107] (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data [107] = ( \u0|mm_interconnect_0|rsp_mux|src_data[107]~14_combout  & ( \u0|mm_interconnect_0|rsp_mux|src_data[107]~11_combout  ) ) # ( !\u0|mm_interconnect_0|rsp_mux|src_data[107]~14_combout  & ( 
// \u0|mm_interconnect_0|rsp_mux|src_data[107]~11_combout  ) ) # ( \u0|mm_interconnect_0|rsp_mux|src_data[107]~14_combout  & ( !\u0|mm_interconnect_0|rsp_mux|src_data[107]~11_combout  ) ) # ( !\u0|mm_interconnect_0|rsp_mux|src_data[107]~14_combout  & ( 
// !\u0|mm_interconnect_0|rsp_mux|src_data[107]~11_combout  & ( ((\u0|mm_interconnect_0|rsp_mux|src_data[107]~13_combout ) # (\u0|mm_interconnect_0|rsp_mux|src_data[107]~10_combout )) # (\u0|mm_interconnect_0|rsp_mux|src_data[107]~12_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_mux|src_data[107]~12_combout ),
        .datab(!\u0|mm_interconnect_0|rsp_mux|src_data[107]~10_combout ),
        .datac(!\u0|mm_interconnect_0|rsp_mux|src_data[107]~13_combout ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|rsp_mux|src_data[107]~14_combout ),
        .dataf(!\u0|mm_interconnect_0|rsp_mux|src_data[107]~11_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data [107]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[107] .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[107] .lut_mask = 64'h7F7FFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[107] .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y17_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|always0~0_combout  = ( \u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout  & ( (\u0|mm_interconnect_0|led_pio_test_s1_agent|comb~0_combout  & \u0|hps_0|fpga_interfaces|h2f_BREADY [0]) ) ) # ( 
// !\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout  & ( (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & \u0|mm_interconnect_0|led_pio_test_s1_agent|comb~0_combout ) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent|comb~0_combout ),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_BREADY [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|always0~0 .lut_mask = 64'h05050505000F000F;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y17_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used[1]~0_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout  & ( (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|write~0_combout  & 
// ((\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]))) # (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|write~0_combout  & (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [0])) ) ) # ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout  & ( (!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|always0~0_combout  & ((!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|write~0_combout  & 
// ((\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]))) # (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|write~0_combout  & (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [0])))) # 
// (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|always0~0_combout  & (((\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|write~0_combout  & \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1])))) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|always0~0_combout ),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [0]),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|write~0_combout ),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used[1]~0 .lut_mask = 64'h02A702A703F303F3;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used[1]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y17_N56
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X25_Y24_N23
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~11_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][106]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][106] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y24_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|src_data[106] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|src_data [106] = ( \u0|mm_interconnect_0|cmd_mux|saved_grant [0] & ( \u0|mm_interconnect_0|cmd_mux|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_AWID [1]) # (\u0|hps_0|fpga_interfaces|h2f_ARID [1]) ) ) ) # ( 
// !\u0|mm_interconnect_0|cmd_mux|saved_grant [0] & ( \u0|mm_interconnect_0|cmd_mux|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [1] ) ) ) # ( \u0|mm_interconnect_0|cmd_mux|saved_grant [0] & ( !\u0|mm_interconnect_0|cmd_mux|saved_grant [1] & ( 
// \u0|hps_0|fpga_interfaces|h2f_AWID [1] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [1]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_AWID [1]),
        .datae(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux|src_data [106]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|src_data[106] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|src_data[106] .lut_mask = 64'h000000FF0F0F0FFF;
defparam \u0|mm_interconnect_0|cmd_mux|src_data[106] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y24_N43
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux|src_data [106]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y24_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~11 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~11_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][106]~q  & ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg 
// [106] ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][106]~q  & ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106] & ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] ) ) ) # ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][106]~q  & ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106] & ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] ) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][106]~q ),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~11 .lut_mask = 64'h00005555AAAAFFFF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~11 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y26_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][106]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][106]~feeder_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~11_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~11_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][106]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][106]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][106]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][106]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y26_N47
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][106] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][106]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][106]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][106] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y26_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[106]~5 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[106]~5_combout  = (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][106]~q  & (\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout  & 
// ((\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][106]~q )))) # (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][106]~q  & (((\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout  & 
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][106]~q )) # (\u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout )))

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][106]~q ),
        .datab(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout ),
        .datac(!\u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout ),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][106]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data[106]~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[106]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[106]~5 .lut_mask = 64'h0537053705370537;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[106]~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y29_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[106]~6 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[106]~6_combout  = ( \u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout  & ( ((\u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout  & \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][106]~q )) # 
// (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][106]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout  & ( (\u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout  & 
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][106]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout ),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][106]~q ),
        .datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][106]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data[106]~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[106]~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[106]~6 .lut_mask = 64'h003300330F3F0F3F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[106]~6 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y23_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[106]~8 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[106]~8_combout  = ( \u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout  & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][106]~q  & ( (\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout 
// ) # (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][106]~q ) ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout  & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][106]~q  & ( 
// \u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout  ) ) ) # ( \u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout  & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][106]~q  & ( 
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][106]~q  ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][106]~q ),
        .datac(!\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout ),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][106]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data[106]~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[106]~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[106]~8 .lut_mask = 64'h000033330F0F3F3F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[106]~8 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y24_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[106]~7 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[106]~7_combout  = ( \u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout  & ( ((\u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout  & \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][106]~q 
// )) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][106]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout  & ( (\u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout  & 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][106]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][106]~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout ),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][106]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data[106]~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[106]~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[106]~7 .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[106]~7 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y26_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[106]~9 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[106]~9_combout  = ( \u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout  & ( ((\u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout  & \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][106]~q )) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][106]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout  & ( (\u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout  & 
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][106]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][106]~q ),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][106]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data[106]~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[106]~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[106]~9 .lut_mask = 64'h005500550F5F0F5F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[106]~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y26_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[106] (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data [106] = ( \u0|mm_interconnect_0|rsp_mux|src_data[106]~9_combout  ) # ( !\u0|mm_interconnect_0|rsp_mux|src_data[106]~9_combout  & ( (((\u0|mm_interconnect_0|rsp_mux|src_data[106]~7_combout ) # 
// (\u0|mm_interconnect_0|rsp_mux|src_data[106]~8_combout )) # (\u0|mm_interconnect_0|rsp_mux|src_data[106]~6_combout )) # (\u0|mm_interconnect_0|rsp_mux|src_data[106]~5_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_mux|src_data[106]~5_combout ),
        .datab(!\u0|mm_interconnect_0|rsp_mux|src_data[106]~6_combout ),
        .datac(!\u0|mm_interconnect_0|rsp_mux|src_data[106]~8_combout ),
        .datad(!\u0|mm_interconnect_0|rsp_mux|src_data[106]~7_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_mux|src_data[106]~9_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data [106]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[106] .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[106] .lut_mask = 64'h7FFF7FFFFFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[106] .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y28_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout  = ( \u0|hps_0|fpga_interfaces|h2f_AWADDR [17] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [17] ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_AWADDR [17] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [17] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_AWADDR [17] 
// & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [17] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
        .datad(gnd),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [17]),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [17]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0 .lut_mask = 64'h0000F0F00F0FFFFF;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y25_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|src8_valid~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|src8_valid~1_combout  = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout  & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout  
// & (\u0|mm_interconnect_0|router|Equal14~0_combout  & (\u0|mm_interconnect_0|cmd_demux|src8_valid~0_combout  & \u0|mm_interconnect_0|router|Equal7~1_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout ),
        .datab(!\u0|mm_interconnect_0|router|Equal14~0_combout ),
        .datac(!\u0|mm_interconnect_0|cmd_demux|src8_valid~0_combout ),
        .datad(!\u0|mm_interconnect_0|router|Equal7~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux|src8_valid~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|src8_valid~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|src8_valid~1 .lut_mask = 64'h0002000200000000;
defparam \u0|mm_interconnect_0|cmd_demux|src8_valid~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y25_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg~1_combout  = ( \u0|mm_interconnect_0|cmd_mux_008|update_grant~0_combout  & ( (!\u0|mm_interconnect_0|cmd_demux|src8_valid~1_combout  & (\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg [0] & 
// ((!\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg [1]) # (!\u0|mm_interconnect_0|cmd_demux_001|src8_valid~1_combout )))) # (\u0|mm_interconnect_0|cmd_demux|src8_valid~1_combout  & ((!\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg [1]) # 
// ((!\u0|mm_interconnect_0|cmd_demux_001|src8_valid~1_combout )))) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_008|update_grant~0_combout  & ( \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg [0] ) )

        .dataa(!\u0|mm_interconnect_0|cmd_demux|src8_valid~1_combout ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg [1]),
        .datac(!\u0|mm_interconnect_0|cmd_demux_001|src8_valid~1_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_008|update_grant~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg~1 .lut_mask = 64'h00FF00FF54FC54FC;
defparam \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y25_N29
dffeas \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y25_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg [1] & ( \u0|mm_interconnect_0|cmd_mux_008|update_grant~0_combout  & ( (!\u0|mm_interconnect_0|cmd_demux_001|src8_valid~1_combout ) 
// # ((!\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg [0] & \u0|mm_interconnect_0|cmd_demux|src8_valid~1_combout )) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg [1] & ( \u0|mm_interconnect_0|cmd_mux_008|update_grant~0_combout  & 
// ( (!\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg [0] & \u0|mm_interconnect_0|cmd_demux|src8_valid~1_combout ) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg [1] & ( !\u0|mm_interconnect_0|cmd_mux_008|update_grant~0_combout  ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg [0]),
        .datab(!\u0|mm_interconnect_0|cmd_demux_001|src8_valid~1_combout ),
        .datac(!\u0|mm_interconnect_0|cmd_demux|src8_valid~1_combout ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg [1]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_008|update_grant~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg~0 .lut_mask = 64'h0000FFFF0A0ACECE;
defparam \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y25_N44
dffeas \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y25_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|arb|grant[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|arb|grant[0]~1_combout  = ( \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg [0] & ( \u0|mm_interconnect_0|cmd_demux|src8_valid~1_combout  & ( (\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg [1] & 
// !\u0|mm_interconnect_0|cmd_demux_001|src8_valid~1_combout ) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg [0] & ( \u0|mm_interconnect_0|cmd_demux|src8_valid~1_combout  ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg [1]),
        .datac(!\u0|mm_interconnect_0|cmd_demux_001|src8_valid~1_combout ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg [0]),
        .dataf(!\u0|mm_interconnect_0|cmd_demux|src8_valid~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_008|arb|grant[0]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|arb|grant[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|arb|grant[0]~1 .lut_mask = 64'h00000000FFFF3030;
defparam \u0|mm_interconnect_0|cmd_mux_008|arb|grant[0]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y25_N2
dffeas \u0|mm_interconnect_0|cmd_mux_008|saved_grant[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_008|arb|grant[0]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|cmd_mux_008|update_grant~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|saved_grant[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_008|saved_grant[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y25_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_data[33] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|src_data [33] = ( \u0|hps_0|fpga_interfaces|h2f_WSTRB [1] & ( (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_WSTRB [1] & ( 
// \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_008|src_data [33]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[33] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[33] .lut_mask = 64'h3333333377777777;
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[33] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y25_N35
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_008|src_data [33]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y25_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout  = ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q  & ( 
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & 
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & 
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]))) ) ) ) # ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q  & ( 
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & 
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & 
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]))) ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q  & ( 
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & 
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & 
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]))) ) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .datae(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0 .lut_mask = 64'h8000800080000000;
defparam \u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y25_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg~0_combout  = (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & (!\u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout  & 
// \u0|mm_interconnect_0|auto_start_s1_agent|m0_read~0_combout ))

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout ),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_agent|m0_read~0_combout ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg~0 .lut_mask = 64'h00A000A000A000A0;
defparam \u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X10_Y25_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~0_combout  = ( \u0|mm_interconnect_0|auto_start_s1_agent|m0_write~combout  & ( (\u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~q  & 
// ((\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0]) # (\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [1]))) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent|m0_write~combout  & ( 
// (\u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg~0_combout  & (\u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~q  & ((!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0]) # 
// (\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [1])))) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [1]),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0]),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg~0_combout ),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|m0_write~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~0 .lut_mask = 64'h000D000D00770077;
defparam \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X10_Y25_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~1_combout  = ( !\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0] & ( \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~0_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0]),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~1 .lut_mask = 64'h00000000FFFF0000;
defparam \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y25_N41
dffeas \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y25_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~1_combout  = ( \u0|mm_interconnect_0|auto_start_s1_agent|local_write~0_combout  & ( (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & 
// (((!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0] & \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout )) # (\u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout ))) ) ) # ( 
// !\u0|mm_interconnect_0|auto_start_s1_agent|local_write~0_combout  & ( (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & (((\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0] & 
// \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout )) # (\u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0]),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout ),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|local_write~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~1 .lut_mask = 64'h0A2A0A2A0A8A0A8A;
defparam \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y25_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q  & ( 
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) # ((!\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~1_combout  & 
// ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ))) # (\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~1_combout  & 
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q  & ( 
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ((!\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~1_combout  & 
// ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ))) # (\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~1_combout  & 
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )))) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~1_combout ),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .lut_mask = 64'h010B010BF1FBF1FB;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y25_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout  = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( 
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) # (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ) ) ) # ( 
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout  ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .lut_mask = 64'hFF00FF00FFAAFFAA;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y25_N5
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y25_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|local_write~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent|local_write~0_combout  = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] & ( 
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_agent|local_write~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|local_write~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|local_write~0 .lut_mask = 64'h0000000000FF00FF;
defparam \u0|mm_interconnect_0|auto_start_s1_agent|local_write~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y25_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|write~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|write~0_combout  = ( \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~4_combout  & ( 
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|auto_start_s1_agent|m0_read~0_combout ) 
// # (\u0|mm_interconnect_0|auto_start_s1_agent|local_write~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~4_combout  & ( 
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( (\u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout  & (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & 
// ((\u0|mm_interconnect_0|auto_start_s1_agent|m0_read~0_combout ) # (\u0|mm_interconnect_0|auto_start_s1_agent|local_write~0_combout )))) ) ) ) # ( \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~4_combout  & ( 
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|auto_start_s1_agent|m0_read~0_combout ) 
// ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~4_combout  & ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( 
// (\u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout  & (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|auto_start_s1_agent|m0_read~0_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_agent|local_write~0_combout ),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout ),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_agent|m0_read~0_combout ),
        .datae(!\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~4_combout ),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|write~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|write~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h003000F0103050F0;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|write~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y25_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[1]~0_combout  = ( \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout  & ( (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|write~0_combout  & 
// ((\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]))) # (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|write~0_combout  & (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [0])) ) ) # ( 
// !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout  & ( (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|write~0_combout  & (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout  & 
// ((\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1])))) # (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|write~0_combout  & ((!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout  & 
// (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [0])) # (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout  & ((\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]))))) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|write~0_combout ),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout ),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [0]),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[1]~0 .lut_mask = 64'h049D049D05AF05AF;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[1]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y25_N14
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X18_Y28_N26
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~10_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][105]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][105] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y25_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_data[105] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|src_data [105] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [0] & ( ((\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [0])) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_AWID [0] & ( (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [0]) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
        .datac(gnd),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [0]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_008|src_data [105]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[105] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[105] .lut_mask = 64'h0033003355775577;
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[105] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y25_N13
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_008|src_data [105]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y28_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~10 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~10_combout  = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105] & ( (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used 
// [1]) # (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][105]~q ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105] & ( 
// (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][105]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][105]~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~10 .lut_mask = 64'h03030303CFCFCFCF;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~10 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y28_N17
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][105] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~10_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][105]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][105] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y28_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[105]~1 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[105]~1_combout  = ( \u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout  & ( \u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout  & ( (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][105]~q ) # 
// (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][105]~q ) ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout  & ( \u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout  & ( 
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][105]~q  ) ) ) # ( \u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout  & ( !\u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout  & ( 
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][105]~q  ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][105]~q ),
        .datac(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][105]~q ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout ),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data[105]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[105]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[105]~1 .lut_mask = 64'h000033330F0F3F3F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[105]~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y26_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[105]~0 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[105]~0_combout  = ( \u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout  & ( ((\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout  & \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][105]~q )) # 
// (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][105]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout  & ( (\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout  & 
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][105]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][105]~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout ),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][105]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data[105]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[105]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[105]~0 .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[105]~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y24_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[105]~2 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[105]~2_combout  = ( \u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout  & ( ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][105]~q  & \u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout 
// )) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][105]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout  & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][105]~q  & 
// \u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][105]~q ),
        .datac(!\u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout ),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][105]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data[105]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[105]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[105]~2 .lut_mask = 64'h0303030303FF03FF;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[105]~2 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y26_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[105]~4 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[105]~4_combout  = ( \u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout  & ( ((\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][105]~q  & \u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout )) # 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][105]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout  & ( (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][105]~q  & 
// \u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][105]~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][105]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data[105]~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[105]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[105]~4 .lut_mask = 64'h0505050505FF05FF;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[105]~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y23_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[105]~3 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[105]~3_combout  = ( \u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout  & ( ((\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout  & \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][105]~q 
// )) # (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][105]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout  & ( (\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout  & 
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][105]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout ),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][105]~q ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][105]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data[105]~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[105]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[105]~3 .lut_mask = 64'h003300330F3F0F3F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[105]~3 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y26_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[105] (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data [105] = ( \u0|mm_interconnect_0|rsp_mux|src_data[105]~3_combout  ) # ( !\u0|mm_interconnect_0|rsp_mux|src_data[105]~3_combout  & ( (((\u0|mm_interconnect_0|rsp_mux|src_data[105]~4_combout ) # 
// (\u0|mm_interconnect_0|rsp_mux|src_data[105]~2_combout )) # (\u0|mm_interconnect_0|rsp_mux|src_data[105]~0_combout )) # (\u0|mm_interconnect_0|rsp_mux|src_data[105]~1_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_mux|src_data[105]~1_combout ),
        .datab(!\u0|mm_interconnect_0|rsp_mux|src_data[105]~0_combout ),
        .datac(!\u0|mm_interconnect_0|rsp_mux|src_data[105]~2_combout ),
        .datad(!\u0|mm_interconnect_0|rsp_mux|src_data[105]~4_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_mux|src_data[105]~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_data [105]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[105] .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[105] .lut_mask = 64'h7FFF7FFFFFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[105] .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y29_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector24~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector24~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~0_combout  & ( (!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & (!\u0|hps_0|fpga_interfaces|h2f_AWLEN 
// [3] & ((!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]) # (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~0_combout )))) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~0_combout  & ( (!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & 
// ((!\u0|hps_0|fpga_interfaces|h2f_AWLEN [3]) # ((!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~0_combout )))) # (\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & (!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] & 
// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~0_combout  & !\u0|hps_0|fpga_interfaces|h2f_AWLEN [3]))) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~0_combout ),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector24~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector24~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector24~0 .lut_mask = 64'hEA80EA80A800A800;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector24~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y29_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~1_sumout  = SUM(( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [5])) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [5]))) ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~0_combout  ) + ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~6  ))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [5]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [5]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~0_combout ),
        .datag(gnd),
        .cin(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~6 ),
        .sharein(gnd),
        .combout(),
        .sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~1_sumout ),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~1 .lut_mask = 64'h0000FF0000000C3F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y29_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[5]~4 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[5]~4_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [5] ) 
// ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ( \u0|hps_0|fpga_interfaces|h2f_AWADDR [5] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [5]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [5]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[5]~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[5]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[5]~4 .lut_mask = 64'h00FF00FF0F0F0F0F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[5]~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y29_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector24~1 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector24~1_combout  = ( \u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[5]~4_combout  & ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~5_sumout  ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[5]~4_combout  & ( 
// ((!\u0|hps_0|fpga_interfaces|h2f_AWBURST [1]) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~1_sumout )) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector24~0_combout ) ) ) ) # ( 
// \u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[5]~4_combout  & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~5_sumout  ) ) ) # ( 
// !\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[5]~4_combout  & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector24~0_combout  & 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~1_sumout  & \u0|hps_0|fpga_interfaces|h2f_AWBURST [1])) ) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector24~0_combout ),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~1_sumout ),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [1]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~5_sumout ),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[5]~4_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector24~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector24~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector24~1 .lut_mask = 64'h020200FFF7F700FF;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector24~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y29_N38
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector24~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y29_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|router|Equal6~0 (
// Equation(s):
// \u0|mm_interconnect_0|router|Equal6~0_combout  = ( \u0|hps_0|fpga_interfaces|h2f_AWADDR [4] & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [5] & 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [4])) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_AWADDR [4] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (((!\u0|hps_0|fpga_interfaces|h2f_AWADDR 
// [5])))) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [5] & (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst 
// [4]))) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [5]),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [4]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [5]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router|Equal6~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router|Equal6~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router|Equal6~0 .lut_mask = 64'hEA40EA4040404040;
defparam \u0|mm_interconnect_0|router|Equal6~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y25_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|router|Equal6~6 (
// Equation(s):
// \u0|mm_interconnect_0|router|Equal6~6_combout  = ( \u0|mm_interconnect_0|router|Equal6~2_combout  & ( \u0|mm_interconnect_0|router|Equal6~3_combout  & ( (\u0|mm_interconnect_0|router|Equal6~0_combout  & (\u0|mm_interconnect_0|router|Equal6~5_combout  & 
// (\u0|mm_interconnect_0|router|Equal6~1_combout  & \u0|mm_interconnect_0|router|Equal6~4_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|router|Equal6~0_combout ),
        .datab(!\u0|mm_interconnect_0|router|Equal6~5_combout ),
        .datac(!\u0|mm_interconnect_0|router|Equal6~1_combout ),
        .datad(!\u0|mm_interconnect_0|router|Equal6~4_combout ),
        .datae(!\u0|mm_interconnect_0|router|Equal6~2_combout ),
        .dataf(!\u0|mm_interconnect_0|router|Equal6~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router|Equal6~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router|Equal6~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router|Equal6~6 .lut_mask = 64'h0000000000000001;
defparam \u0|mm_interconnect_0|router|Equal6~6 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y21_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  = ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( 
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & (((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & 
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))))) ) ) # ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  
// & ( ((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// ((\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~1_combout ))))) ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datae(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~1_combout ),
        .datag(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .extended_lut = "on";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .lut_mask = 64'h0A00F0F00A00F3F3;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y23_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|sink_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|sink_ready~0_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & ( (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & 
// (\u0|mm_interconnect_0|router|Equal6~6_combout  & \u0|mm_interconnect_0|router|Equal6~8_combout )) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & ( 
// (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & (\u0|mm_interconnect_0|router|Equal6~6_combout  & (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & 
// \u0|mm_interconnect_0|router|Equal6~8_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|router|Equal6~6_combout ),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datad(!\u0|mm_interconnect_0|router|Equal6~8_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux|sink_ready~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|sink_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|sink_ready~0 .lut_mask = 64'h0001000100110011;
defparam \u0|mm_interconnect_0|cmd_demux|sink_ready~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y24_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|sink_ready~7 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|sink_ready~7_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & ( \u0|mm_interconnect_0|cmd_mux|saved_grant [0] ) ) # ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & ( (\u0|mm_interconnect_0|cmd_mux|saved_grant [0] & 
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux|sink_ready~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|sink_ready~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|sink_ready~7 .lut_mask = 64'h0303030333333333;
defparam \u0|mm_interconnect_0|cmd_demux|sink_ready~7 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y23_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|sink_ready~3 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|sink_ready~3_combout  = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout  & ( \u0|mm_interconnect_0|router|Equal7~1_combout  & ( 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout  & (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & \u0|mm_interconnect_0|router|Equal14~0_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
        .datac(!\u0|mm_interconnect_0|router|Equal14~0_combout ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout ),
        .dataf(!\u0|mm_interconnect_0|router|Equal7~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux|sink_ready~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|sink_ready~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|sink_ready~3 .lut_mask = 64'h0000000001010000;
defparam \u0|mm_interconnect_0|cmd_demux|sink_ready~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y23_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|sink_ready~4 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|sink_ready~4_combout  = ( \u0|mm_interconnect_0|router|Equal7~1_combout  & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout  & (\u0|mm_interconnect_0|cmd_mux_011|saved_grant 
// [0] & (\u0|mm_interconnect_0|router|Equal14~0_combout  & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
        .datac(!\u0|mm_interconnect_0|router|Equal14~0_combout ),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|router|Equal7~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux|sink_ready~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|sink_ready~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|sink_ready~4 .lut_mask = 64'h0000000000010001;
defparam \u0|mm_interconnect_0|cmd_demux|sink_ready~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y23_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|WideOr0~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|WideOr0~1_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & ( \u0|mm_interconnect_0|cmd_demux|sink_ready~4_combout  & ( 
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & (!\u0|mm_interconnect_0|cmd_demux|sink_ready~3_combout  & 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout )) ) ) ) # ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & ( \u0|mm_interconnect_0|cmd_demux|sink_ready~4_combout  & ( 
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & 
// ((!\u0|mm_interconnect_0|cmd_demux|sink_ready~3_combout ) # (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout )))) ) ) ) # ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & ( !\u0|mm_interconnect_0|cmd_demux|sink_ready~4_combout  & ( !\u0|mm_interconnect_0|cmd_demux|sink_ready~3_combout  ) ) ) # 
// ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & ( !\u0|mm_interconnect_0|cmd_demux|sink_ready~4_combout  & ( (!\u0|mm_interconnect_0|cmd_demux|sink_ready~3_combout ) # 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datab(!\u0|mm_interconnect_0|cmd_demux|sink_ready~3_combout ),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .dataf(!\u0|mm_interconnect_0|cmd_demux|sink_ready~4_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux|WideOr0~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|WideOr0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|WideOr0~1 .lut_mask = 64'hFFCCCCCCA0808080;
defparam \u0|mm_interconnect_0|cmd_demux|WideOr0~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y25_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|sink_ready~5 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|sink_ready~5_combout  = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout  & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout  
// & (\u0|mm_interconnect_0|router|Equal14~0_combout  & (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & \u0|mm_interconnect_0|router|Equal7~1_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout ),
        .datab(!\u0|mm_interconnect_0|router|Equal14~0_combout ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
        .datad(!\u0|mm_interconnect_0|router|Equal7~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux|sink_ready~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|sink_ready~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|sink_ready~5 .lut_mask = 64'h0002000200000000;
defparam \u0|mm_interconnect_0|cmd_demux|sink_ready~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y25_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|sink_ready~6 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|sink_ready~6_combout  = ( \u0|mm_interconnect_0|router|Equal7~1_combout  & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout  & ( (\u0|mm_interconnect_0|cmd_mux_009|saved_grant 
// [0] & (\u0|mm_interconnect_0|router|Equal14~0_combout  & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|router|Equal14~0_combout ),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout ),
        .datae(!\u0|mm_interconnect_0|router|Equal7~1_combout ),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux|sink_ready~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|sink_ready~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|sink_ready~6 .lut_mask = 64'h0000000000000500;
defparam \u0|mm_interconnect_0|cmd_demux|sink_ready~6 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y25_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|WideOr0~2 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|WideOr0~2_combout  = ( \u0|mm_interconnect_0|cmd_demux|sink_ready~5_combout  & ( \u0|mm_interconnect_0|cmd_demux|sink_ready~6_combout  & ( 
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & 
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ))) ) ) 
// ) # ( !\u0|mm_interconnect_0|cmd_demux|sink_ready~5_combout  & ( \u0|mm_interconnect_0|cmd_demux|sink_ready~6_combout  & ( (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ) ) ) ) # ( \u0|mm_interconnect_0|cmd_demux|sink_ready~5_combout  & ( !\u0|mm_interconnect_0|cmd_demux|sink_ready~6_combout  & ( 
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ) ) ) ) # 
// ( !\u0|mm_interconnect_0|cmd_demux|sink_ready~5_combout  & ( !\u0|mm_interconnect_0|cmd_demux|sink_ready~6_combout  ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .datae(!\u0|mm_interconnect_0|cmd_demux|sink_ready~5_combout ),
        .dataf(!\u0|mm_interconnect_0|cmd_demux|sink_ready~6_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux|WideOr0~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|WideOr0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|WideOr0~2 .lut_mask = 64'hFFFFAA00C0C08000;
defparam \u0|mm_interconnect_0|cmd_demux|WideOr0~2 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y27_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|sink_ready~9 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|sink_ready~9_combout  = ( \u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & ( (\u0|mm_interconnect_0|router|Equal7~1_combout  & 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~3_combout  & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout  & \u0|mm_interconnect_0|router|Equal6~5_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|router|Equal7~1_combout ),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~3_combout ),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout ),
        .datad(!\u0|mm_interconnect_0|router|Equal6~5_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux|sink_ready~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|sink_ready~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|sink_ready~9 .lut_mask = 64'h0000000000010001;
defparam \u0|mm_interconnect_0|cmd_demux|sink_ready~9 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y27_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|sink_ready~8 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|sink_ready~8_combout  = ( \u0|mm_interconnect_0|router|Equal7~1_combout  & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~3_combout  & (\u0|mm_interconnect_0|cmd_mux_004|saved_grant 
// [0] & \u0|mm_interconnect_0|router|Equal7~2_combout )) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~3_combout ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
        .datad(!\u0|mm_interconnect_0|router|Equal7~2_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|router|Equal7~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux|sink_ready~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|sink_ready~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|sink_ready~8 .lut_mask = 64'h0000000000030003;
defparam \u0|mm_interconnect_0|cmd_demux|sink_ready~8 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y27_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|WideOr0~3 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|WideOr0~3_combout  = ( \u0|mm_interconnect_0|cmd_demux|sink_ready~9_combout  & ( \u0|mm_interconnect_0|cmd_demux|sink_ready~8_combout  & ( 
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout 
// ))) ) ) ) # ( !\u0|mm_interconnect_0|cmd_demux|sink_ready~9_combout  & ( \u0|mm_interconnect_0|cmd_demux|sink_ready~8_combout  & ( 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout 
// ) ) ) ) # ( \u0|mm_interconnect_0|cmd_demux|sink_ready~9_combout  & ( !\u0|mm_interconnect_0|cmd_demux|sink_ready~8_combout  & ( (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & 
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ) ) ) ) # ( !\u0|mm_interconnect_0|cmd_demux|sink_ready~9_combout  & ( !\u0|mm_interconnect_0|cmd_demux|sink_ready~8_combout  ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datae(!\u0|mm_interconnect_0|cmd_demux|sink_ready~9_combout ),
        .dataf(!\u0|mm_interconnect_0|cmd_demux|sink_ready~8_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux|WideOr0~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|WideOr0~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|WideOr0~3 .lut_mask = 64'hFFFF8888F0008000;
defparam \u0|mm_interconnect_0|cmd_demux|WideOr0~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y27_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|WideOr0~4 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|WideOr0~4_combout  = ( \u0|mm_interconnect_0|cmd_demux|WideOr0~2_combout  & ( \u0|mm_interconnect_0|cmd_demux|WideOr0~3_combout  & ( (\u0|mm_interconnect_0|cmd_demux|WideOr0~0_combout  & 
// (\u0|mm_interconnect_0|cmd_demux|WideOr0~1_combout  & ((!\u0|mm_interconnect_0|cmd_demux|sink_ready~7_combout ) # (!\u0|mm_interconnect_0|cmd_demux|src0_valid~1_combout )))) ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_demux|sink_ready~7_combout ),
        .datab(!\u0|mm_interconnect_0|cmd_demux|src0_valid~1_combout ),
        .datac(!\u0|mm_interconnect_0|cmd_demux|WideOr0~0_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_demux|WideOr0~1_combout ),
        .datae(!\u0|mm_interconnect_0|cmd_demux|WideOr0~2_combout ),
        .dataf(!\u0|mm_interconnect_0|cmd_demux|WideOr0~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux|WideOr0~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|WideOr0~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|WideOr0~4 .lut_mask = 64'h000000000000000E;
defparam \u0|mm_interconnect_0|cmd_demux|WideOr0~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y27_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout  = ( \u0|mm_interconnect_0|cmd_demux|sink_ready~0_combout  & ( \u0|mm_interconnect_0|cmd_demux|WideOr0~4_combout  & ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout  ) ) ) # ( \u0|mm_interconnect_0|cmd_demux|sink_ready~0_combout  & ( !\u0|mm_interconnect_0|cmd_demux|WideOr0~4_combout  & ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout  ) ) ) # ( !\u0|mm_interconnect_0|cmd_demux|sink_ready~0_combout  & ( !\u0|mm_interconnect_0|cmd_demux|WideOr0~4_combout  & ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout  ) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_demux|sink_ready~0_combout ),
        .dataf(!\u0|mm_interconnect_0|cmd_demux|WideOr0~4_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1 .lut_mask = 64'h5555555500005555;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y28_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|router|Equal6~8 (
// Equation(s):
// \u0|mm_interconnect_0|router|Equal6~8_combout  = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ( (\u0|hps_0|fpga_interfaces|h2f_AWADDR [13] & 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout  & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [15] & (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~3_combout )))) ) ) # ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ( ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout  & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst 
// [15] & (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~3_combout  & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [13])))) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [13]),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout ),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [15]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~3_combout ),
        .datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [13]),
        .datag(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [15]),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router|Equal6~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router|Equal6~8 .extended_lut = "on";
defparam \u0|mm_interconnect_0|router|Equal6~8 .lut_mask = 64'h0100000001000300;
defparam \u0|mm_interconnect_0|router|Equal6~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y25_N52
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[18] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|router|Equal6~7_combout ),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [18]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[18] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[18] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y23_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|src18_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|src18_valid~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout  & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q ) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [18]) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [18]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux|src18_valid~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|src18_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|src18_valid~0 .lut_mask = 64'h00000000FF0FFF0F;
defparam \u0|mm_interconnect_0|cmd_demux|src18_valid~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y23_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|src_valid~0_combout  = ( \u0|mm_interconnect_0|cmd_demux|src18_valid~0_combout  & ( (\u0|mm_interconnect_0|router|Equal6~8_combout  & (\u0|mm_interconnect_0|router|Equal6~6_combout  & 
// \u0|mm_interconnect_0|cmd_mux_018|saved_grant [0])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|router|Equal6~8_combout ),
        .datac(!\u0|mm_interconnect_0|router|Equal6~6_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_demux|src18_valid~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_018|src_valid~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|src_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|src_valid~0 .lut_mask = 64'h0000000000030003;
defparam \u0|mm_interconnect_0|cmd_mux_018|src_valid~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y23_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout  = ( \u0|mm_interconnect_0|cmd_mux_018|src_valid~1_combout  & ( 
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) # 
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ))) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_018|src_valid~1_combout  & ( (\u0|mm_interconnect_0|cmd_mux_018|src_valid~0_combout  & 
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) # 
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_018|src_valid~0_combout ),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_018|src_valid~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h01050105030F030F;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y20_N50
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y20_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|m0_read~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent|m0_read~0_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & ( 
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]) # (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]) ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_agent|m0_read~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|m0_read~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|m0_read~0 .lut_mask = 64'h0000000055FF55FF;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|m0_read~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y22_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg~0_combout  = ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|clock_sel_s1_agent|m0_read~0_combout  & 
// !\u0|mm_interconnect_0|clock_sel_s1_agent|WideOr0~0_combout ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_agent|m0_read~0_combout ),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_agent|WideOr0~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg~0 .lut_mask = 64'h3030303000000000;
defparam \u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y20_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter~0_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_agent|m0_write~combout  & ( \u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override~q  & ( 
// (\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [1]) # (\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [0]) ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_agent|m0_write~combout  & ( 
// \u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override~q  & ( (\u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg~0_combout  & ((!\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [0]) # 
// (\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [1]))) ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [0]),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg~0_combout ),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [1]),
        .datae(!\u0|mm_interconnect_0|clock_sel_s1_agent|m0_write~combout ),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter~0 .lut_mask = 64'h000000000C0F33FF;
defparam \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y20_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter~1_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter~0_combout  & ( !\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [0] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter~1 .lut_mask = 64'h00000000FF00FF00;
defparam \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y20_N14
dffeas \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y20_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter~2 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter~2_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter~0_combout  & ( !\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [0] $ 
// (!\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [1]) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [0]),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter~2 .lut_mask = 64'h000000000FF00FF0;
defparam \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y20_N41
dffeas \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y20_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~0_combout  = ( !\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [1] & ( \u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override~q  ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override~q ),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~0 .lut_mask = 64'h3333333300000000;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y20_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~4 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~4_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~0_combout  & 
// \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [0]) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~0_combout  & 
// (!\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [0] $ (((!\u0|mm_interconnect_0|clock_sel_s1_agent|local_write~0_combout ) # (\u0|mm_interconnect_0|clock_sel_s1_agent|WideOr0~0_combout ))))) ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent|WideOr0~0_combout ),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~0_combout ),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [0]),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_agent|local_write~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~4 .lut_mask = 64'h0321032103030303;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y22_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg~1_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg~0_combout  & ( \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~4_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~4_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg~1 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y22_N29
dffeas \u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y22_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|comb~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent|comb~0_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [0] ) ) # ( 
// !\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [0] & ((\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][129]~q ) # 
// (\u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg [0]))) ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [0]),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_agent|comb~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|comb~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|comb~0 .lut_mask = 64'h050F050F0F0F0F0F;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|comb~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y22_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|always0~0_combout  = ( \u0|mm_interconnect_0|rsp_demux_018|WideOr0~0_combout  & ( \u0|mm_interconnect_0|clock_sel_s1_agent|comb~0_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_agent|comb~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_018|WideOr0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|always0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|always0~0 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|always0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y22_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used[0]~1_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [0]) # 
// (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|write~0_combout ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ( ((\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [0] & 
// ((!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|always0~0_combout ) # (\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout )))) # (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|write~0_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|always0~0_combout ),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|write~0_combout ),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout ),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h33BF33BF33FF33FF;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y22_N53
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y22_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|rp_valid (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent|rp_valid~combout  = ( !\u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg [0] & ( (!\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [0] & 
// ((!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [0]) # (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][129]~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [0]),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_agent|rp_valid~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|rp_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|rp_valid .lut_mask = 64'hE0E0E0E000000000;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|rp_valid .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y22_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_018|src1_valid (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout  = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][66]~q  & ( !\u0|mm_interconnect_0|clock_sel_s1_agent|rp_valid~combout  ) ) # ( 
// !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][66]~q  & ( (!\u0|mm_interconnect_0|clock_sel_s1_agent|rp_valid~combout  & ((!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][68]~q ) # 
// (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][69]~q ))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_agent|rp_valid~combout ),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][68]~q ),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][69]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][66]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_018|src1_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_018|src1_valid .lut_mask = 64'hC0CCC0CCCCCCCCCC;
defparam \u0|mm_interconnect_0|rsp_demux_018|src1_valid .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y19_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|WideOr1~0 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|WideOr1~0_combout  = ( \u0|mm_interconnect_0|rsp_demux_011|src0_valid~0_combout  & ( \u0|mm_interconnect_0|rsp_demux_015|src0_valid~0_combout  & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|rp_valid~combout ) # 
// (\u0|mm_interconnect_0|rsp_demux_014|src0_valid~0_combout ) ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_011|src0_valid~0_combout  & ( \u0|mm_interconnect_0|rsp_demux_015|src0_valid~0_combout  & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent|rp_valid~combout 
//  & ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent|rp_valid~combout ) # (\u0|mm_interconnect_0|rsp_demux_014|src0_valid~0_combout ))) ) ) ) # ( \u0|mm_interconnect_0|rsp_demux_011|src0_valid~0_combout  & ( 
// !\u0|mm_interconnect_0|rsp_demux_015|src0_valid~0_combout  & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|rp_valid~combout  & ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent|rp_valid~combout ) # 
// (\u0|mm_interconnect_0|rsp_demux_014|src0_valid~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_011|src0_valid~0_combout  & ( !\u0|mm_interconnect_0|rsp_demux_015|src0_valid~0_combout  & ( 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|rp_valid~combout  & (\u0|mm_interconnect_0|write_en_tx_s1_agent|rp_valid~combout  & ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent|rp_valid~combout ) # 
// (\u0|mm_interconnect_0|rsp_demux_014|src0_valid~0_combout )))) ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_014|src0_valid~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|rp_valid~combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|rp_valid~combout ),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent|rp_valid~combout ),
        .datae(!\u0|mm_interconnect_0|rsp_demux_011|src0_valid~0_combout ),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_015|src0_valid~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|WideOr1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|WideOr1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|WideOr1~0 .lut_mask = 64'h00131313005F5F5F;
defparam \u0|mm_interconnect_0|rsp_mux_001|WideOr1~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y24_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|WideOr1~1 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|WideOr1~1_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|rp_valid~combout  & ( \u0|mm_interconnect_0|rsp_demux_009|src0_valid~0_combout  & ( (\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ) # 
// (\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ) ) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|rp_valid~combout  & ( \u0|mm_interconnect_0|rsp_demux_009|src0_valid~0_combout  & ( 
// (\u0|mm_interconnect_0|rsp_demux_010|src0_valid~0_combout  & ((\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ) # (\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ))) ) ) ) # ( 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|rp_valid~combout  & ( !\u0|mm_interconnect_0|rsp_demux_009|src0_valid~0_combout  & ( (\u0|mm_interconnect_0|link_disable_s1_agent|rp_valid~combout  & 
// ((\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ) # (\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|rp_valid~combout  & ( 
// !\u0|mm_interconnect_0|rsp_demux_009|src0_valid~0_combout  & ( (\u0|mm_interconnect_0|rsp_demux_010|src0_valid~0_combout  & (\u0|mm_interconnect_0|link_disable_s1_agent|rp_valid~combout  & ((\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ) # 
// (\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout )))) ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_010|src0_valid~0_combout ),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_agent|rp_valid~combout ),
        .datac(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ),
        .datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|rp_valid~combout ),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_009|src0_valid~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|WideOr1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|WideOr1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|WideOr1~1 .lut_mask = 64'h0111033305550FFF;
defparam \u0|mm_interconnect_0|rsp_mux_001|WideOr1~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y27_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|WideOr1~2 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|WideOr1~2_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout  & ( \u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout  & ( (!\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout  & 
// (\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout  & ((\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout ) # (\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout )))) # (\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout  & 
// (((\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout )) # (\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout  & ( 
// \u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout  & ( (!\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout  & (\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout  & ((\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout ) # 
// (\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout )))) # (\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout  & (((\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout )) # (\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout 
// ))) ) ) ) # ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout  & ( !\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout  & ( (!\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout  & 
// (\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout  & ((\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout ) # (\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout )))) # (\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout  & 
// (((\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout )) # (\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ),
        .datab(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ),
        .datac(!\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ),
        .datad(!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout ),
        .datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|WideOr1~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|WideOr1~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|WideOr1~2 .lut_mask = 64'h0000135F135F135F;
defparam \u0|mm_interconnect_0|rsp_mux_001|WideOr1~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y35_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|rp_valid (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|rp_valid~combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q  & ( (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0] & 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0] & !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0])) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0] & !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|rp_valid~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|rp_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|rp_valid .lut_mask = 64'hAA00AA00A000A000;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|rp_valid .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y27_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|rp_valid (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|rp_valid~combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0] & 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0] & !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q )) ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0] & ( 
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|rp_valid~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|rp_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|rp_valid .lut_mask = 64'h8888888888008800;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|rp_valid .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y27_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|WideOr1~3 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|WideOr1~3_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|rp_valid~combout  & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout  & ( 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout  & (\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout  & (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|rp_valid~combout  & 
// \u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout ),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|rp_valid~combout ),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ),
        .datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|rp_valid~combout ),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|WideOr1~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|WideOr1~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|WideOr1~3 .lut_mask = 64'h0000000000000001;
defparam \u0|mm_interconnect_0|rsp_mux_001|WideOr1~3 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y30_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|WideOr1~4 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|WideOr1~4_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout  & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout  & ( 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout  & (!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout  & (\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout  & 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout ),
        .datab(!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout ),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ),
        .datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|WideOr1~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|WideOr1~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|WideOr1~4 .lut_mask = 64'h0000000000000004;
defparam \u0|mm_interconnect_0|rsp_mux_001|WideOr1~4 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y27_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|WideOr1 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|WideOr1~combout  = ( \u0|mm_interconnect_0|rsp_mux_001|WideOr1~3_combout  & ( \u0|mm_interconnect_0|rsp_mux_001|WideOr1~4_combout  & ( ((!\u0|mm_interconnect_0|rsp_mux_001|WideOr1~0_combout ) # 
// ((!\u0|mm_interconnect_0|rsp_mux_001|WideOr1~1_combout ) # (!\u0|mm_interconnect_0|rsp_mux_001|WideOr1~2_combout ))) # (\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout ) ) ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|WideOr1~3_combout  & ( 
// \u0|mm_interconnect_0|rsp_mux_001|WideOr1~4_combout  ) ) # ( \u0|mm_interconnect_0|rsp_mux_001|WideOr1~3_combout  & ( !\u0|mm_interconnect_0|rsp_mux_001|WideOr1~4_combout  ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|WideOr1~3_combout  & ( 
// !\u0|mm_interconnect_0|rsp_mux_001|WideOr1~4_combout  ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout ),
        .datab(!\u0|mm_interconnect_0|rsp_mux_001|WideOr1~0_combout ),
        .datac(!\u0|mm_interconnect_0|rsp_mux_001|WideOr1~1_combout ),
        .datad(!\u0|mm_interconnect_0|rsp_mux_001|WideOr1~2_combout ),
        .datae(!\u0|mm_interconnect_0|rsp_mux_001|WideOr1~3_combout ),
        .dataf(!\u0|mm_interconnect_0|rsp_mux_001|WideOr1~4_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|WideOr1~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|WideOr1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|WideOr1 .lut_mask = 64'hFFFFFFFFFFFFFFFD;
defparam \u0|mm_interconnect_0|rsp_mux_001|WideOr1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y29_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|src7_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|src7_valid~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [7] & ( (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & \u0|mm_interconnect_0|router_001|Equal13~1_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [7] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q  & (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & \u0|mm_interconnect_0|router_001|Equal13~1_combout 
// )) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
        .datad(!\u0|mm_interconnect_0|router_001|Equal13~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [7]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux_001|src7_valid~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|src7_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|src7_valid~0 .lut_mask = 64'h000C000C000F000F;
defparam \u0|mm_interconnect_0|cmd_demux_001|src7_valid~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y27_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_007|update_grant~0_combout  & ( ((\u0|mm_interconnect_0|router|Equal13~0_combout  & \u0|mm_interconnect_0|cmd_demux|src7_valid~0_combout )) # 
// (\u0|mm_interconnect_0|cmd_demux_001|src7_valid~0_combout ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_demux_001|src7_valid~0_combout ),
        .datac(!\u0|mm_interconnect_0|router|Equal13~0_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_demux|src7_valid~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_007|update_grant~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg~0 .lut_mask = 64'h00000000333F333F;
defparam \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y27_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg~2 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg~2_combout  = ( \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg~0_combout  & ( !\u0|mm_interconnect_0|cmd_mux_007|arb|grant[1]~0_combout  ) ) # ( 
// !\u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg~0_combout  & ( \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg [0] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_007|arb|grant[1]~0_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg~2 .lut_mask = 64'h00FF00FFF0F0F0F0;
defparam \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y27_N50
dffeas \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y27_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|arb|grant[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|arb|grant[1]~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg [1] & ( \u0|mm_interconnect_0|cmd_demux_001|src7_valid~0_combout  ) ) # ( !\u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg [1] & ( 
// (!\u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg [0] & (\u0|mm_interconnect_0|cmd_demux_001|src7_valid~0_combout  & ((!\u0|mm_interconnect_0|cmd_demux|src7_valid~0_combout ) # (!\u0|mm_interconnect_0|router|Equal13~0_combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg [0]),
        .datab(!\u0|mm_interconnect_0|cmd_demux_001|src7_valid~0_combout ),
        .datac(!\u0|mm_interconnect_0|cmd_demux|src7_valid~0_combout ),
        .datad(!\u0|mm_interconnect_0|router|Equal13~0_combout ),
        .datae(!\u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg [1]),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_007|arb|grant[1]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|arb|grant[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|arb|grant[1]~0 .lut_mask = 64'h2220333322203333;
defparam \u0|mm_interconnect_0|cmd_mux_007|arb|grant[1]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y27_N26
dffeas \u0|mm_interconnect_0|cmd_mux_007|saved_grant[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_007|arb|grant[1]~0_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|cmd_mux_007|update_grant~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|saved_grant[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_007|saved_grant[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y27_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|src_data[32] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|src_data [32] = ( \u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & ( (\u0|hps_0|fpga_interfaces|h2f_WSTRB [0]) # (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]) ) ) # ( 
// !\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & ( \u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_007|src_data [32]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[32] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[32] .lut_mask = 64'h0F0F0F0F0FFF0FFF;
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[32] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y27_N8
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_007|src_data [32]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y29_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout  = ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & ( 
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & ( (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & 
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & ((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) # 
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q )))) ) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .datae(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0 .lut_mask = 64'h8880000000000000;
defparam \u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y29_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  = ( \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0_combout  & ( 
// \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0] & ( (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # 
// ((!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & ((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]) # (\u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout )))) 
// ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0_combout  & ( \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0] & ( 
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # ((!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout )) ) ) 
// ) # ( \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0_combout  & ( !\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0] & ( 
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # ((!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & 
// ((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]) # (\u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout )))) ) ) ) # ( 
// !\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0_combout  & ( !\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0] & ( 
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # ((!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout )) ) ) 
// )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),
        .datab(!\u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout ),
        .datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
        .datae(!\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0_combout ),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hF2F2F2FAF2F2FAF2;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y30_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout  = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  
// & (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & 
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h0010001050505050;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y30_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout  = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h0000000044444444;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y30_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout  = ( 
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout  & ( 
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ) # (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout  & ( 
// ((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout  & ((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ) # 
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout )))) # 
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),
        .datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
        .datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ),
        .datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h31FF31FF33FF33FF;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y30_N11
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y30_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & ( (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  
// & ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  $ 
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  
// & ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q  & ( (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .lut_mask = 64'hC0C000003C3CC0C0;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y30_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout  = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  & ( 
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & 
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout  & ( 
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout  & ((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) # 
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),
        .datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .lut_mask = 64'h1155115500440044;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y30_N41
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y29_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q )) # 
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & (((\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~1_combout ) # 
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q )))) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q )) # 
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & (((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q  & 
// !\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~1_combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
        .datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
        .datad(!\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .lut_mask = 64'h2722272227772777;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y30_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout  = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout  & ( 
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ) # ( 
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout  )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .lut_mask = 64'hFFFFFFFF0C0C0C0C;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y30_N17
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y30_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  
// & ( \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~1_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h000000000000FFFF;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y30_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout  = ( 
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & 
// ( (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) # 
// ((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) # (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) ) 
// # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg 
// [3] & ( (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) ) # ( 
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] 
// & ( (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) # 
// ((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) 
// # (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) 
// ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( 
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( 
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// ((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) 
// # (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))))) ) 
// ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datae(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .lut_mask = 64'h5140BFAE1100FFEE;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y30_N14
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y30_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  = ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( 
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & 
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h0C000C0000000000;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y30_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout  = ( 
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  $ 
// (((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))))) # 
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) 
// # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & ( 
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] $ (((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) # 
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .lut_mask = 64'h5A0F5A0F5ACC5ACC;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y30_N53
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y30_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout  = ( 
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  & ( 
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])) # 
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) # 
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg 
// [6] & ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  & ( (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])) # (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & 
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) ) # ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg 
// [6] & ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  & ( (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) # 
// ((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) # 
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg 
// [6] & ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout  & ( (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & 
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout  & !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg 
// [2])) ) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
        .datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datae(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 .lut_mask = 64'h0300FFFC8B887774;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y30_N44
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";
// synopsys translate_on

// Location: FF_X23_Y30_N5
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][78] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~9_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][78]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y30_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~9 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~9_combout  = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6])) # 
// (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][78]~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][78]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
        .datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][78]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~9 .lut_mask = 64'h005500550A5F0A5F;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~9 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y30_N50
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][78] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~9_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][78]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";
// synopsys translate_on

// Location: FF_X22_Y30_N44
dffeas \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_busy (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";
// synopsys translate_on

// Location: FF_X23_Y30_N23
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][76] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~7_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][76]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y30_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~7 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~7_combout  = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4])) # 
// (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][76]~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][76]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
        .datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][76]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h005500550A5F0A5F;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y30_N11
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][76] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~7_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][76]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";
// synopsys translate_on

// Location: FF_X23_Y30_N56
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][75] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][75]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y30_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~6 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~6_combout  = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( 
// (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) # 
// (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][75]~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][75]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),
        .datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][75]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h0055005522772277;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y30_N56
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][75] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~6_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][75]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";
// synopsys translate_on

// Location: FF_X23_Y30_N2
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][77] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][77]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y30_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~8 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~8_combout  = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])) # 
// (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][77]~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][77]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
        .datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][77]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~8 .lut_mask = 64'h005500550A5F0A5F;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y30_N35
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][77] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~8_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][77]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y30_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~0_combout  = ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][75]~q  & ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][77]~q  & ( 
// (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][78]~q  & (!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_busy~q  & (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74]~q  & 
// !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][76]~q ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][78]~q ),
        .datab(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .datac(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datae(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][75]~q ),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][77]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h0800000000000000;
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y30_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout  = ( !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~2_combout  & ( 
// (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74]~q ) # (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) 
// ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datad(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h00AF00AF00000000;
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y30_N32
dffeas \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y30_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~2 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~2_combout  = ( \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_busy~q  & ( \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter 
// [2] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y30_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout  = ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][66]~q  & ( (!\u0|mm_interconnect_0|link_start_s1_agent|comb~0_combout ) # 
// ((!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~0_combout  & ((!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~2_combout ) # 
// (!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~1_combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .datab(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .datac(!\u0|mm_interconnect_0|link_start_s1_agent|comb~0_combout ),
        .datad(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .datae(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][66]~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h0000FAF80000FAF8;
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y29_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|write~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|write~0_combout  = ( \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~4_combout  & ( 
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|link_start_s1_agent|m0_read~0_combout ) 
// # (\u0|mm_interconnect_0|link_start_s1_agent|local_write~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~4_combout  & ( 
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout  & 
// ((\u0|mm_interconnect_0|link_start_s1_agent|m0_read~0_combout ) # (\u0|mm_interconnect_0|link_start_s1_agent|local_write~0_combout )))) ) ) ) # ( \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~4_combout  & ( 
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|link_start_s1_agent|m0_read~0_combout ) 
// ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~4_combout  & ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( 
// (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout  & \u0|mm_interconnect_0|link_start_s1_agent|m0_read~0_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),
        .datab(!\u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout ),
        .datac(!\u0|mm_interconnect_0|link_start_s1_agent|local_write~0_combout ),
        .datad(!\u0|mm_interconnect_0|link_start_s1_agent|m0_read~0_combout ),
        .datae(!\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~4_combout ),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|write~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|write~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h002200AA02220AAA;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|write~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y29_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used[0]~1_combout  = ( \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0_combout  & ( ((\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [0] & 
// ((\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout )))) # (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|write~0_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0_combout  & ( (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [0]) # (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|write~0_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout ),
        .datab(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|write~0_combout ),
        .datac(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h33FF33FF337F337F;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y29_N29
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y29_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used[1]~0_combout  = ( \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0_combout  & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|write~0_combout  & 
// (((\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout  & \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1])))) # (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|write~0_combout  & 
// ((!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout  & ((\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]))) # (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout  & 
// (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [0])))) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0_combout  & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|write~0_combout  & 
// ((\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]))) # (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|write~0_combout  & (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [0])) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [0]),
        .datab(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|write~0_combout ),
        .datac(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout ),
        .datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used[1]~0 .lut_mask = 64'h11DD11DD013D013D;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used[1]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y29_N8
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X23_Y30_N59
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][74] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][74]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y30_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~5 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~5_combout  = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & (((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) # 
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))) # (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & 
// (((\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][74]~q )))) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & ( 
// (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))) # (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & 
// (((\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][74]~q )))) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),
        .datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
        .datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][74]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h085D085D2A7F2A7F;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y30_N23
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~5_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y30_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~0_combout  = ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][77]~q  & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74]~q  & 
// (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][75]~q  & !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][76]~q )) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][77]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~0 .lut_mask = 64'hA000A00000000000;
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y30_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~1_combout  = ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][77]~q  & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][76]~q  & 
// (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][75]~q  & !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74]~q )) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][77]~q  & ( 
// ((\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74]~q ) # (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][75]~q )) # (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][76]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][77]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h5FFF5FFFA000A000;
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y30_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~2 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~2_combout  = ( \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter 
// [5] ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [5] $ 
// (((!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3]))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datac(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datad(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h3FC03FC0FF00FF00;
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y30_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout  = ( \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( 
// (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout  & !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~2_combout ) ) ) # ( 
// !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ( (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout  & !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~1_combout 
// ) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~1_combout ),
        .datad(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~2_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h5050505055005500;
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y30_N41
dffeas \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y30_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~1_combout  = ( !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( (!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter 
// [2] & (!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [5])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datac(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datad(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~1 .lut_mask = 64'hC000C00000000000;
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y30_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout  = ( \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( 
// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~1_combout  & ( (!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout 
//  & (!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~0_combout  $ (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][78]~q )))) ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( 
// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~1_combout  & ( (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~0_combout  $ 
// (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][78]~q )) # (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( 
// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~1_combout  & ( (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout  & 
// ((!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~0_combout  $ (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][78]~q )) # (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # 
// ( !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~1_combout  & ( 
// (!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout  & (!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~0_combout 
//  $ (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][78]~q )))) ) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~0_combout ),
        .datab(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datac(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout ),
        .datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][78]~q ),
        .datae(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h0408070B070B0408;
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y30_N8
dffeas \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y30_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout  = ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][78]~q  & ( \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~1_combout  & ( 
// (!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout  & 
// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout )) ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][78]~q  & ( \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~1_combout  & ( 
// (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout  & ((!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~0_combout 
// )) # (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ((!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6]))))) ) ) ) # ( 
// !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][78]~q  & ( !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~1_combout  & ( (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~0_combout  & 
// (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout  & !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~0_combout ),
        .datab(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .datac(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout ),
        .datad(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datae(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][78]~q ),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h05000000050C000C;
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y30_N2
dffeas \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y30_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  = ( \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( 
// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_busy~q  ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( 
// (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_busy~q  & ((!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~1_combout ) # 
// (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [7]))) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .datad(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_busy~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h00F500F500FF00FF;
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y30_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout  = ( \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout  & ( (!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ((!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74]~q  $ 
// (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][75]~q )))) # (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2])) ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( 
// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout  & ( (!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ((!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74]~q  $ 
// (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][75]~q )))) # (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & 
// (!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2])) ) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datab(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datac(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74]~q ),
        .datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datae(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h00000000E44EB11B;
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y30_N20
dffeas \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y30_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~0_combout  = !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4] $ (((!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter 
// [3] & !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))

        .dataa(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datab(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h66CC66CC66CC66CC;
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y30_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout  = ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74]~q  & ( \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout  & ( 
// (!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ((\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][76]~q ))) # 
// (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~0_combout )) ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74]~q  & ( 
// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout  & ( (!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & ((!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][76]~q  $ 
// (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][75]~q )))) # (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout  & (!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~0_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~0_combout ),
        .datab(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
        .datac(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][76]~q ),
        .datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][75]~q ),
        .datae(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74]~q ),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h00000000E22E2E2E;
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y30_N14
dffeas \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y30_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~1_combout  = ( !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( 
// (!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & 
// !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3])) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
        .datac(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
        .datad(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'hC000C00000000000;
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y30_N59
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][130] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][130]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][130] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y30_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~4 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~4_combout  = ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][130]~q  & ( 
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][130]~q  & ( 
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] ) ) ) # ( 
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][130]~q  & ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used 
// [1] ) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][130]~q ),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~4 .lut_mask = 64'h00005555AAAAFFFF;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y30_N26
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][130] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~4_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][130]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][130] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y30_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_payload~8 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_payload~8_combout  = ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][66]~q  & ( \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~0_combout  & ( 
// (\u0|mm_interconnect_0|link_start_s1_agent|comb~0_combout  & \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][130]~q ) ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][66]~q  & ( 
// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~0_combout  & ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][130]~q  ) ) ) # ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][66]~q  & ( 
// !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~0_combout  & ( (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~1_combout  & 
// (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~2_combout  & (\u0|mm_interconnect_0|link_start_s1_agent|comb~0_combout  & \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][130]~q ))) ) ) ) # ( 
// !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][66]~q  & ( !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~0_combout  & ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][130]~q  ) ) )

        .dataa(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .datab(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .datac(!\u0|mm_interconnect_0|link_start_s1_agent|comb~0_combout ),
        .datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][130]~q ),
        .datae(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][66]~q ),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_payload~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~8 .lut_mask = 64'h00FF000100FF000F;
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~8 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y30_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_004|src1_valid (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_004|src1_valid~combout  = ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout  & ( !\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout  ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_demux_004|src1_valid~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_004|src1_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_004|src1_valid .lut_mask = 64'hCCCCCCCC00000000;
defparam \u0|mm_interconnect_0|rsp_demux_004|src1_valid .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y30_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_007|src1_valid (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_007|src1_valid~combout  = ( !\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout  & ( !\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ),
        .dataf(!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_demux_007|src1_valid~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_007|src1_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_007|src1_valid .lut_mask = 64'hFFFF000000000000;
defparam \u0|mm_interconnect_0|rsp_demux_007|src1_valid .shared_arith = "off";
// synopsys translate_on

// Location: FF_X14_Y29_N5
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][130] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][130]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][130] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X14_Y29_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~4 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~4_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][130]~q  ) ) # ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][130]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~4 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y29_N29
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][130] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~4_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][130]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][130] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y29_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_payload~7 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_payload~7_combout  = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][130]~q  & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~2_combout  & ( 
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][66]~q ) # ((\u0|mm_interconnect_0|data_read_en_rx_s1_agent|comb~0_combout  & ((\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~0_combout ) # 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~1_combout )))) ) ) ) # ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][130]~q  & ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~2_combout  & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][66]~q ) # 
// ((\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~0_combout  & \u0|mm_interconnect_0|data_read_en_rx_s1_agent|comb~0_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][66]~q ),
        .datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|comb~0_combout ),
        .datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][130]~q ),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_payload~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~7 .lut_mask = 64'h0000CCCF0000CCDF;
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~7 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y17_N14
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][130] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~4_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][130]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][130] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y17_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~4 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~4_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( 
// (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][130]~q ) ) ) # ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][130]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][130]~q ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~4 .lut_mask = 64'h05050505AFAFAFAF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y17_N26
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][130] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~4_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][130]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][130] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y17_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_payload~6 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_payload~6_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][66]~q  & ( \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~2_combout  & ( 
// (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][130]~q  & (\u0|mm_interconnect_0|led_pio_test_s1_agent|comb~0_combout  & ((\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~0_combout ) # 
// (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~1_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][66]~q  & ( \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~2_combout 
//  & ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][130]~q  ) ) ) # ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][66]~q  & ( !\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~2_combout  & ( 
// (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][130]~q  & (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~0_combout  & \u0|mm_interconnect_0|led_pio_test_s1_agent|comb~0_combout )) ) ) ) # ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][66]~q  & ( !\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~2_combout  & ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][130]~q  ) ) )

        .dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][130]~q ),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent|comb~0_combout ),
        .datae(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][66]~q ),
        .dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_payload~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~6 .lut_mask = 64'h5555000555550015;
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~6 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y30_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~3 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~3_combout  = ( !\u0|mm_interconnect_0|rsp_mux|src_payload~6_combout  & ( \u0|mm_interconnect_0|rsp_demux|src1_valid~combout  & ( (!\u0|mm_interconnect_0|rsp_mux|src_payload~8_combout  & 
// ((!\u0|mm_interconnect_0|rsp_demux_004|src1_valid~combout ) # ((!\u0|mm_interconnect_0|rsp_mux|src_payload~7_combout )))) # (\u0|mm_interconnect_0|rsp_mux|src_payload~8_combout  & (!\u0|mm_interconnect_0|rsp_demux_007|src1_valid~combout  & 
// ((!\u0|mm_interconnect_0|rsp_demux_004|src1_valid~combout ) # (!\u0|mm_interconnect_0|rsp_mux|src_payload~7_combout )))) ) ) ) # ( \u0|mm_interconnect_0|rsp_mux|src_payload~6_combout  & ( !\u0|mm_interconnect_0|rsp_demux|src1_valid~combout  & ( 
// (!\u0|mm_interconnect_0|rsp_mux|src_payload~8_combout  & ((!\u0|mm_interconnect_0|rsp_demux_004|src1_valid~combout ) # ((!\u0|mm_interconnect_0|rsp_mux|src_payload~7_combout )))) # (\u0|mm_interconnect_0|rsp_mux|src_payload~8_combout  & 
// (!\u0|mm_interconnect_0|rsp_demux_007|src1_valid~combout  & ((!\u0|mm_interconnect_0|rsp_demux_004|src1_valid~combout ) # (!\u0|mm_interconnect_0|rsp_mux|src_payload~7_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|rsp_mux|src_payload~6_combout  & ( 
// !\u0|mm_interconnect_0|rsp_demux|src1_valid~combout  & ( (!\u0|mm_interconnect_0|rsp_mux|src_payload~8_combout  & ((!\u0|mm_interconnect_0|rsp_demux_004|src1_valid~combout ) # ((!\u0|mm_interconnect_0|rsp_mux|src_payload~7_combout )))) # 
// (\u0|mm_interconnect_0|rsp_mux|src_payload~8_combout  & (!\u0|mm_interconnect_0|rsp_demux_007|src1_valid~combout  & ((!\u0|mm_interconnect_0|rsp_demux_004|src1_valid~combout ) # (!\u0|mm_interconnect_0|rsp_mux|src_payload~7_combout )))) ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_mux|src_payload~8_combout ),
        .datab(!\u0|mm_interconnect_0|rsp_demux_004|src1_valid~combout ),
        .datac(!\u0|mm_interconnect_0|rsp_demux_007|src1_valid~combout ),
        .datad(!\u0|mm_interconnect_0|rsp_mux|src_payload~7_combout ),
        .datae(!\u0|mm_interconnect_0|rsp_mux|src_payload~6_combout ),
        .dataf(!\u0|mm_interconnect_0|rsp_demux|src1_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~3 .lut_mask = 64'hFAC8FAC8FAC80000;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y19_N2
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][130] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][130]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][130] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y19_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~4 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~4_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][130]~q ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][130]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][130]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~4 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y18_N20
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][130] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~4_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][130]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][130] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y18_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_payload~1 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_payload~1_combout  = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66]~q  & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|comb~0_combout  & ( 
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][130]~q  & (((\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~1_combout  & 
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~2_combout )) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~0_combout ))) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66]~q  & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|comb~0_combout  & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][130]~q  ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66]~q  & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|comb~0_combout  & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][130]~q  ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][130]~q ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66]~q ),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|comb~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_payload~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~1 .lut_mask = 64'h5555000055550515;
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y18_N35
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][130] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][130]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][130] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y18_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~4 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~4_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][130]~q  & ( 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][130]~q  & ( 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] ) ) ) # ( 
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][130]~q  & ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( 
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),
        .datae(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][130]~q ),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~4 .lut_mask = 64'h000000FFFF00FFFF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y18_N41
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][130] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~4_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][130]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][130] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y18_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_payload~0 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_payload~0_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~2_combout  & ( \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~1_combout  & ( 
// (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][130]~q  & ((!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][66]~q ) # (\u0|mm_interconnect_0|write_en_tx_s1_agent|comb~0_combout ))) ) ) ) # ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~2_combout  & ( \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~1_combout  & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][130]~q  & 
// ((!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][66]~q ) # ((\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~0_combout  & \u0|mm_interconnect_0|write_en_tx_s1_agent|comb~0_combout )))) ) ) ) # ( 
// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~2_combout  & ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~1_combout  & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][130]~q  & 
// ((!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][66]~q ) # ((\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~0_combout  & \u0|mm_interconnect_0|write_en_tx_s1_agent|comb~0_combout )))) ) ) ) # ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~2_combout  & ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~1_combout  & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][130]~q  & 
// ((!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][66]~q ) # ((\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~0_combout  & \u0|mm_interconnect_0|write_en_tx_s1_agent|comb~0_combout )))) ) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][66]~q ),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent|comb~0_combout ),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][130]~q ),
        .datae(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_payload~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~0 .lut_mask = 64'h00AB00AB00AB00AF;
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y19_N5
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][130] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][130]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][130] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y19_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~4 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~4_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][130]~q ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][130]~q ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][130]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~4 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y19_N8
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][130] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~4_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][130]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][130] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y19_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_payload~2 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_payload~2_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][66]~q  & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][130]~q  & ( 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|comb~0_combout  & (((\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~1_combout  & \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~2_combout 
// )) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][66]~q  & ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][130]~q  ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|comb~0_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][66]~q ),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][130]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_payload~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~2 .lut_mask = 64'h00000000FFFF0133;
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y22_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~1_combout  = ( \u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout  & ( \u0|mm_interconnect_0|rsp_mux|src_payload~2_combout  & ( (!\u0|mm_interconnect_0|rsp_mux|src_payload~1_combout  & 
// (!\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout  & ((!\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout ) # (!\u0|mm_interconnect_0|rsp_mux|src_payload~0_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout  & ( 
// \u0|mm_interconnect_0|rsp_mux|src_payload~2_combout  & ( (!\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout  & ((!\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout ) # (!\u0|mm_interconnect_0|rsp_mux|src_payload~0_combout ))) ) ) ) # ( 
// \u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout  & ( !\u0|mm_interconnect_0|rsp_mux|src_payload~2_combout  & ( (!\u0|mm_interconnect_0|rsp_mux|src_payload~1_combout  & ((!\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout ) # 
// (!\u0|mm_interconnect_0|rsp_mux|src_payload~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout  & ( !\u0|mm_interconnect_0|rsp_mux|src_payload~2_combout  & ( (!\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout ) # 
// (!\u0|mm_interconnect_0|rsp_mux|src_payload~0_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_mux|src_payload~1_combout ),
        .datab(!\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout ),
        .datac(!\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout ),
        .datad(!\u0|mm_interconnect_0|rsp_mux|src_payload~0_combout ),
        .datae(!\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout ),
        .dataf(!\u0|mm_interconnect_0|rsp_mux|src_payload~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~1 .lut_mask = 64'hFFCCAA88F0C0A080;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y25_N23
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][130] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][130]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][130] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y25_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~4 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~4_combout  = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][130]~q  ) ) # ( 
// !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][130]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~4 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y25_N17
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][130] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~4_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][130]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][130] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y25_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_payload~3 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_payload~3_combout  = ( \u0|mm_interconnect_0|auto_start_s1_agent|comb~0_combout  & ( \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~2_combout  & ( 
// (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][130]~q  & ((!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66]~q ) # ((\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~1_combout ) # 
// (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~0_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent|comb~0_combout  & ( \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~2_combout  & ( 
// (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66]~q  & \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][130]~q ) ) ) ) # ( \u0|mm_interconnect_0|auto_start_s1_agent|comb~0_combout  & ( 
// !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~2_combout  & ( (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][130]~q  & ((!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66]~q ) # 
// (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent|comb~0_combout  & ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~2_combout  & ( 
// (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66]~q  & \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][130]~q ) ) ) )

        .dataa(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66]~q ),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][130]~q ),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .datad(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .datae(!\u0|mm_interconnect_0|auto_start_s1_agent|comb~0_combout ),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_payload~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~3 .lut_mask = 64'h2222232322222333;
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y17_N23
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][130] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][130]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][130] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y17_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~4 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~4_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( 
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][130]~q ) ) ) # ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][130]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][130]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~4 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y17_N26
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][130] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~4_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][130]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][130] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y17_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_payload~5 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_payload~5_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|comb~0_combout  & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][130]~q  & ( 
// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][66]~q ) # ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~1_combout  & 
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~2_combout ))) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~0_combout ) ) ) ) # ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|comb~0_combout  & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][130]~q  & ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][66]~q  ) ) )

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][66]~q ),
        .datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|comb~0_combout ),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][130]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_payload~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~5 .lut_mask = 64'h00000000F0F0F3F7;
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y22_N59
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][130] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][130]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][130] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y22_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~4 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~4_combout  = ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][130]~q  ) ) # ( 
// !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][130]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~4 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y22_N1
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][130] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~4_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][130]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][130] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y22_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_payload~4 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_payload~4_combout  = ( \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~2_combout  & ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][66]~q  & ( 
// (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][130]~q  & (\u0|mm_interconnect_0|link_disable_s1_agent|comb~0_combout  & ((\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~1_combout ) # 
// (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~0_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~2_combout  & ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][66]~q 
//  & ( (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][130]~q  & (\u0|mm_interconnect_0|link_disable_s1_agent|comb~0_combout  & \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~0_combout )) ) ) ) # ( 
// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~2_combout  & ( !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][66]~q  & ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][130]~q  ) ) ) # ( 
// !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~2_combout  & ( !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][66]~q  & ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][130]~q  ) ) )

        .dataa(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][130]~q ),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_agent|comb~0_combout ),
        .datac(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .datad(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .datae(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][66]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_payload~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~4 .lut_mask = 64'h5555555501010111;
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y24_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~2 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~2_combout  = ( \u0|mm_interconnect_0|rsp_mux|src_payload~5_combout  & ( \u0|mm_interconnect_0|rsp_mux|src_payload~4_combout  & ( (!\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout  & 
// (!\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout  & ((!\u0|mm_interconnect_0|rsp_demux_008|src1_valid~combout ) # (!\u0|mm_interconnect_0|rsp_mux|src_payload~3_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|rsp_mux|src_payload~5_combout  & ( 
// \u0|mm_interconnect_0|rsp_mux|src_payload~4_combout  & ( (!\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout  & ((!\u0|mm_interconnect_0|rsp_demux_008|src1_valid~combout ) # (!\u0|mm_interconnect_0|rsp_mux|src_payload~3_combout ))) ) ) ) # ( 
// \u0|mm_interconnect_0|rsp_mux|src_payload~5_combout  & ( !\u0|mm_interconnect_0|rsp_mux|src_payload~4_combout  & ( (!\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout  & ((!\u0|mm_interconnect_0|rsp_demux_008|src1_valid~combout ) # 
// (!\u0|mm_interconnect_0|rsp_mux|src_payload~3_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|rsp_mux|src_payload~5_combout  & ( !\u0|mm_interconnect_0|rsp_mux|src_payload~4_combout  & ( (!\u0|mm_interconnect_0|rsp_demux_008|src1_valid~combout ) # 
// (!\u0|mm_interconnect_0|rsp_mux|src_payload~3_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout ),
        .datab(!\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ),
        .datac(!\u0|mm_interconnect_0|rsp_demux_008|src1_valid~combout ),
        .datad(!\u0|mm_interconnect_0|rsp_mux|src_payload~3_combout ),
        .datae(!\u0|mm_interconnect_0|rsp_mux|src_payload~5_combout ),
        .dataf(!\u0|mm_interconnect_0|rsp_mux|src_payload~4_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~2 .lut_mask = 64'hFFF0CCC0AAA08880;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y22_N26
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][130] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][130]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][130] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y22_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~4 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~4_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][130]~q  & ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout 
//  ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][130]~q  & ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( 
// !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] ) ) ) # ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][130]~q  & ( 
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][130]~q ),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~4 .lut_mask = 64'h00003333CCCCFFFF;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y22_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][130]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][130]~feeder_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~4_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~4_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][130]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][130]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][130]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][130]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y22_N2
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][130] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][130]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][130]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][130] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y22_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~0 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~0_combout  = ( !\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout  & ( (\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout  & 
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][130]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout ),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][130]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~0 .lut_mask = 64'h0055005500000000;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X6_Y31_N2
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][130] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][130]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][130] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X6_Y31_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~8 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~8_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout  & ( 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][130]~q ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout  & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]) # 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][130]~q ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][130]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~8 .lut_mask = 64'hCCFFCCFF00330033;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X6_Y31_N47
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][130] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~8_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][130]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][130] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X6_Y31_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~8 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~8_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][129]~q  & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][130]~q  & 
// (((\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0]) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0]))) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][129]~q  & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][130]~q  & ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg [0]) # 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0]))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0]),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][130]~q ),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg [0]),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~8 .lut_mask = 64'h1313131313331333;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~8 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X6_Y31_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~9 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~9_combout  = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~1_combout  & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][66]~q  & ( 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|comb~0_combout  & (\u0|mm_interconnect_0|rsp_mux_001|src_payload~8_combout  & ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~0_combout ) # 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~1_combout  & ( 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][66]~q  & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|comb~0_combout  & (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~0_combout  & 
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~8_combout )) ) ) ) # ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~1_combout  & ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][66]~q  & ( 
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~8_combout  ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~1_combout  & ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][66]~q  & ( 
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~8_combout  ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|comb~0_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .datad(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~8_combout ),
        .datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][66]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~9 .lut_mask = 64'h00FF00FF00050015;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~9 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y33_N35
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][130] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][130]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][130] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y33_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~8 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~8_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][130]~q  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][130]~q  & ( (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout  & 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][130]~q ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~8 .lut_mask = 64'hA0A0AFAFA0A0AFAF;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y33_N35
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][130] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~8_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][130]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][130] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y33_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~6 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~6_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][130]~q  & ( (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q  & 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0])) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][130]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~6 .lut_mask = 64'h000000005F7F5F7F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~6 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X13_Y33_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~7 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~7_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][66]~q  & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout  & ( 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|comb~0_combout  & (\u0|mm_interconnect_0|rsp_mux_001|src_payload~6_combout  & ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~1_combout ) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~0_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][66]~q  & ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout  & ( \u0|mm_interconnect_0|rsp_mux_001|src_payload~6_combout  ) ) ) # ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][66]~q  & ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout  & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~0_combout  & 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|comb~0_combout  & \u0|mm_interconnect_0|rsp_mux_001|src_payload~6_combout )) ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][66]~q  & ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout  & ( \u0|mm_interconnect_0|rsp_mux_001|src_payload~6_combout  ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|comb~0_combout ),
        .datad(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~6_combout ),
        .datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][66]~q ),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~7 .lut_mask = 64'h00FF000500FF0007;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~7 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y34_N14
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][130] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][130]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][130] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y34_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~8 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~8_combout  = (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout )) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & 
// ((\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][130]~q )))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][130]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~8 .lut_mask = 64'hC0CFC0CFC0CFC0CF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~8 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y34_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][130]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][130]~feeder_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~8_combout  )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~8_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][130]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][130]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][130]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][130]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y34_N44
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][130] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][130]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][130]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][130] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y34_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~10 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~10_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][130]~q  & 
// (((\u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg [0]) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][129]~q ))) ) ) # ( 
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][130]~q  & ((\u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg [0]) # 
// (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [0]))) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][130]~q ),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [0]),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg [0]),
        .datae(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [0]),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~10 .lut_mask = 64'h0333133303331333;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~10 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y34_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~11 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~11_combout  = ( \u0|mm_interconnect_0|rsp_mux_001|src_payload~10_combout  & ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~2_combout  & ( 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][66]~q ) # ((\u0|mm_interconnect_0|data_flag_rx_s1_agent|comb~0_combout  & ((\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~0_combout ) # 
// (\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~1_combout )))) ) ) ) # ( \u0|mm_interconnect_0|rsp_mux_001|src_payload~10_combout  & ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~2_combout  & ( 
// (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][66]~q ) # ((\u0|mm_interconnect_0|data_flag_rx_s1_agent|comb~0_combout  & \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~0_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .datab(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|comb~0_combout ),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][66]~q ),
        .datae(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~10_combout ),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~11 .lut_mask = 64'h0000FF030000FF13;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~11 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y32_N11
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][130] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][130]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][130] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y32_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~8 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~8_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][130]~q  & ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout  & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] ) ) ) # ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][130]~q  & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout  ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][130]~q  & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout  & ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][130]~q ),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~8 .lut_mask = 64'hF0F0FFFF00000F0F;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X15_Y31_N29
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][130] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~8_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][130]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][130] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X15_Y31_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~4 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~4_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][130]~q  ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][130]~q  & (((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0] & 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][129]~q )) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0]))) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0]),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0]),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][130]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~4 .lut_mask = 64'h001F001F00FF00FF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y30_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~5 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~5_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~0_combout  & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout  & ( 
// (\u0|mm_interconnect_0|rsp_mux_001|src_payload~4_combout  & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][66]~q ) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|comb~0_combout ))) ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~0_combout  & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout  & ( (\u0|mm_interconnect_0|rsp_mux_001|src_payload~4_combout  & 
// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][66]~q ) # ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|comb~0_combout  & \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout )))) ) ) ) # 
// ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~0_combout  & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout  & ( (\u0|mm_interconnect_0|rsp_mux_001|src_payload~4_combout  & 
// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][66]~q ) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|comb~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~0_combout  & 
// ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout  & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][66]~q  & \u0|mm_interconnect_0|rsp_mux_001|src_payload~4_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][66]~q ),
        .datab(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~4_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|comb~0_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~5 .lut_mask = 64'h2222232322232323;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X13_Y23_N35
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][130] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][130]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][130] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X13_Y23_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~2_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][130]~q  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][130]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~2 .lut_mask = 64'hF0F0F0F000FF00FF;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y23_N2
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][130] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~2_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][130]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][130] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y23_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~12 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~12_combout  = ( \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~1_combout  & ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][66]~q  & ( 
// (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][130]~q  & (\u0|mm_interconnect_0|timecode_rx_s1_agent|comb~0_combout  & !\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout )) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~1_combout  & ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][66]~q  & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][130]~q  & 
// (\u0|mm_interconnect_0|timecode_rx_s1_agent|comb~0_combout  & (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~0_combout  & !\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ))) ) ) ) # ( 
// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~1_combout  & ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][66]~q  & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][130]~q  & 
// !\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ) ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~1_combout  & ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][66]~q  & ( 
// (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][130]~q  & !\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][130]~q ),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent|comb~0_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ),
        .datae(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][66]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~12 .lut_mask = 64'h5500550001001100;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~12 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X10_Y27_N8
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][130] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][130]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][130] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X10_Y27_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~8 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~8_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][130]~q  & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] ) ) # ( 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][130]~q  & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout  ) ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][130]~q  & ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout  ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][130]~q ),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~8 .lut_mask = 64'hF0F0F0F00000FFFF;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X11_Y27_N44
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][130] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~8_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][130]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][130] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X11_Y27_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~13 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~13_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][130]~q  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0] & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][130]~q  & (((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q  & 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0])) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][130]~q ),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~13 .lut_mask = 64'h1113111333333333;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X11_Y26_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~14 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~14_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][66]~q  & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|comb~0_combout  & ( 
// (\u0|mm_interconnect_0|rsp_mux_001|src_payload~13_combout  & (((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~2_combout  & \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~1_combout )) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][66]~q  & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|comb~0_combout  & ( 
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~13_combout  ) ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][66]~q  & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|comb~0_combout  & ( 
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~13_combout  ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .datac(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~13_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][66]~q ),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|comb~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~14 .lut_mask = 64'h0F0F00000F0F0507;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~14 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y30_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~15 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~15_combout  = ( !\u0|mm_interconnect_0|rsp_mux_001|src_payload~12_combout  & ( !\u0|mm_interconnect_0|rsp_mux_001|src_payload~14_combout  & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~9_combout  & 
// (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~7_combout  & (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~11_combout  & !\u0|mm_interconnect_0|rsp_mux_001|src_payload~5_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~9_combout ),
        .datab(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~7_combout ),
        .datac(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~11_combout ),
        .datad(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~5_combout ),
        .datae(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~12_combout ),
        .dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~14_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~15 .lut_mask = 64'h8000000000000000;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~15 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X19_Y38_N38
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][130] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][130]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][130] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y38_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~8 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~8_combout  = (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout )) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & 
// ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][130]~q )))

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][130]~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~8 .lut_mask = 64'hC0F3C0F3C0F3C0F3;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y38_N56
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][130] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~8_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][130]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][130] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y38_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~24 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~24_combout  = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][129]~q  & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0] & ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][130]~q  ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][129]~q  & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0] & ( 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][130]~q  & ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0]) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg [0]))) ) ) ) # 
// ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][129]~q  & ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][130]~q  & 
// ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0]) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg [0]))) ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][129]~q  
// & ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][130]~q  & ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0]) # 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg [0]))) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][130]~q ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0]),
        .datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~24_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~24 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~24 .lut_mask = 64'h050F050F050F0F0F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~24 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y38_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~25 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~25_combout  = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~0_combout  & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][66]~q  & ( 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|comb~0_combout  & \u0|mm_interconnect_0|rsp_mux_001|src_payload~24_combout ) ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~0_combout  & ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][66]~q  & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|comb~0_combout  & (\u0|mm_interconnect_0|rsp_mux_001|src_payload~24_combout  & 
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout  & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout ))) ) ) ) # ( 
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~0_combout  & ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][66]~q  & ( \u0|mm_interconnect_0|rsp_mux_001|src_payload~24_combout  ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~0_combout  & ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][66]~q  & ( \u0|mm_interconnect_0|rsp_mux_001|src_payload~24_combout  ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|comb~0_combout ),
        .datab(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~24_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][66]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~25_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~25 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~25 .lut_mask = 64'h3333333300011111;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~25 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y36_N5
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][130] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][130]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][130] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y36_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~8 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~8_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout  & ( 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][130]~q ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout  & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]) # 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][130]~q ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][130]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~8 .lut_mask = 64'hAAFFAAFF00550055;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y35_N58
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][130] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~8_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][130]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][130] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y35_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~26 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~26_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][130]~q  ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg [0] & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][130]~q  & (((\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [0] & 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][129]~q )) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [0]))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][130]~q ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [0]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~26_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~26 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~26 .lut_mask = 64'h0155015555555555;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~26 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y35_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~27 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~27_combout  = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~2_combout  & ( \u0|mm_interconnect_0|rsp_mux_001|src_payload~26_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][66]~q ) # ((\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|comb~0_combout  & ((\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~1_combout ) # 
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~0_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~2_combout  & ( 
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~26_combout  & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][66]~q ) # ((\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|comb~0_combout  & 
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~0_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][66]~q ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|comb~0_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~26_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~27_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~27 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~27 .lut_mask = 64'h00000000ABABABBB;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~27 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y33_N44
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][130] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][130]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][130] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y33_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~8 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~8_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][130]~q  ) ) # ( 
// !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
        .datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][130]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~8 .lut_mask = 64'hF0F0F0F000FF00FF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y33_N11
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][130] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~8_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][130]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][130] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y33_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~22 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~22_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][130]~q  & 
// (((\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][129]~q ) # (\u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [0]))) ) ) # ( 
// !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][130]~q  & ((\u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg [0]) # 
// (\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [0]))) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [0]),
        .datab(!\u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg [0]),
        .datac(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][130]~q ),
        .datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~22_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~22 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~22 .lut_mask = 64'h07070707070F070F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~22 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y32_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~23 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~23_combout  = ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][66]~q  & ( \u0|mm_interconnect_0|rsp_mux_001|src_payload~22_combout  & ( (\u0|mm_interconnect_0|data_info_s1_agent|comb~0_combout  & 
// (((\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~2_combout  & \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~1_combout )) # (\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~0_combout 
// ))) ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][66]~q  & ( \u0|mm_interconnect_0|rsp_mux_001|src_payload~22_combout  ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .datab(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .datac(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .datad(!\u0|mm_interconnect_0|data_info_s1_agent|comb~0_combout ),
        .datae(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][66]~q ),
        .dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~22_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~23_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~23 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~23 .lut_mask = 64'h00000000FFFF0057;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~23 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y35_N47
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][130] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][130]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][130] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y35_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~8 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~8_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][130]~q  ) ) # ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][130]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~8 .lut_mask = 64'hF0F0F0F000FF00FF;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y35_N56
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][130] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~8_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][130]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][130] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y35_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~18 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~18_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][130]~q  ) ) # ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][130]~q  & (((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0] & 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][129]~q )) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0]))) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0]),
        .datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0]),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][130]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~18 .lut_mask = 64'h001F001F00FF00FF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~18 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y35_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~19 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~19_combout  = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout  & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|comb~0_combout  & ( 
// (\u0|mm_interconnect_0|rsp_mux_001|src_payload~18_combout  & (((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][66]~q ) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout )) # 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout  & ( 
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|comb~0_combout  & ( (\u0|mm_interconnect_0|rsp_mux_001|src_payload~18_combout  & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][66]~q ) # 
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~0_combout ))) ) ) ) # ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout  & ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|comb~0_combout  & ( (\u0|mm_interconnect_0|rsp_mux_001|src_payload~18_combout  & !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][66]~q ) ) ) ) # ( 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout  & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|comb~0_combout  & ( (\u0|mm_interconnect_0|rsp_mux_001|src_payload~18_combout  & 
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][66]~q ) ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .datab(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~18_combout ),
        .datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][66]~q ),
        .datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|comb~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~19 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~19 .lut_mask = 64'h3030303031313133;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~19 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y36_N56
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][130] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][130]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][130] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y36_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~8 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~8_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][130]~q  ) ) # ( 
// !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][130]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~8 .lut_mask = 64'hF0F0F0F000FF00FF;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y36_N47
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][130] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~8_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][130]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][130] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y36_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~20 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~20_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][130]~q  & 
// (((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][129]~q ) # (\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0]))) ) ) # ( 
// !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][130]~q  & ((\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0]) # 
// (\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0]))) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0]),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0]),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][130]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~20 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~20 .lut_mask = 64'h00770077007F007F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~20 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y36_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~21 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~21_combout  = ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~1_combout  & ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~0_combout  & ( 
// (\u0|mm_interconnect_0|rsp_mux_001|src_payload~20_combout  & ((!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][66]~q ) # (\u0|mm_interconnect_0|fsm_info_s1_agent|comb~0_combout ))) ) ) ) # ( 
// !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~1_combout  & ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~0_combout  & ( (\u0|mm_interconnect_0|rsp_mux_001|src_payload~20_combout  & 
// ((!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][66]~q ) # (\u0|mm_interconnect_0|fsm_info_s1_agent|comb~0_combout ))) ) ) ) # ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~1_combout  & ( 
// !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~0_combout  & ( (\u0|mm_interconnect_0|rsp_mux_001|src_payload~20_combout  & ((!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][66]~q ) # 
// ((\u0|mm_interconnect_0|fsm_info_s1_agent|comb~0_combout  & \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~2_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~1_combout  & ( 
// !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~0_combout  & ( (\u0|mm_interconnect_0|rsp_mux_001|src_payload~20_combout  & !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][66]~q ) ) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent|comb~0_combout ),
        .datab(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~20_combout ),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][66]~q ),
        .datae(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~21_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~21 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~21 .lut_mask = 64'h3300330133113311;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~21 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y33_N26
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][130] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~8_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][130]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][130] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y33_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~8 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~8_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][130]~q  & ( 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]) ) ) # ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][130]~q  & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][130]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~8 .lut_mask = 64'hF000F000FF0FFF0F;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y33_N35
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][130] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~8_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][130]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][130] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y33_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~16 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~16_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][129]~q  & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][130]~q  & 
// (((\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0]) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0]))) ) ) # ( 
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][129]~q  & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][130]~q  & ((\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0]) # 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0]))) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][130]~q ),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0]),
        .datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0]),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][129]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~16 .lut_mask = 64'h0555055515551555;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~16 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X30_Y33_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~17 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~17_combout  = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout  & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][66]~q  & ( 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|comb~0_combout  & (\u0|mm_interconnect_0|rsp_mux_001|src_payload~16_combout  & ((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout ) # 
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~0_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout  & ( 
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][66]~q  & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|comb~0_combout  & (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~0_combout  & 
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~16_combout )) ) ) ) # ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout  & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][66]~q  & ( 
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~16_combout  ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout  & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][66]~q  & ( 
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~16_combout  ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|comb~0_combout ),
        .datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~0_combout ),
        .datac(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~16_combout ),
        .datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout ),
        .datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout ),
        .dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][66]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~17 .lut_mask = 64'h0F0F0F0F01010105;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~17 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y34_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~28 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~28_combout  = ( !\u0|mm_interconnect_0|rsp_mux_001|src_payload~21_combout  & ( !\u0|mm_interconnect_0|rsp_mux_001|src_payload~17_combout  & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~25_combout  & 
// (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~27_combout  & (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~23_combout  & !\u0|mm_interconnect_0|rsp_mux_001|src_payload~19_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~25_combout ),
        .datab(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~27_combout ),
        .datac(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~23_combout ),
        .datad(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~19_combout ),
        .datae(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~21_combout ),
        .dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~17_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~28_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~28 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~28 .lut_mask = 64'h8000000000000000;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~28 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y30_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload[0] (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload [0] = ( \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~15_combout  & ( \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~28_combout  & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~3_combout ) # 
// ((!\u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~1_combout ) # ((!\u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~2_combout ) # (\u0|mm_interconnect_0|rsp_mux_001|src_payload~0_combout ))) ) ) ) # ( 
// !\u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~15_combout  & ( \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~28_combout  ) ) # ( \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~15_combout  & ( 
// !\u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~28_combout  ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~15_combout  & ( !\u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~28_combout  ) )

        .dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~3_combout ),
        .datab(!\u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~1_combout ),
        .datac(!\u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~2_combout ),
        .datad(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~0_combout ),
        .datae(!\u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~15_combout ),
        .dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~28_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload [0]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload[0] .lut_mask = 64'hFFFFFFFFFFFFFEFF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload[0] .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y28_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [19] & ( (\u0|hps_0|fpga_interfaces|h2f_AWADDR [19]) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [19] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & 
// \u0|hps_0|fpga_interfaces|h2f_AWADDR [19]) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [19]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [19]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2 .lut_mask = 64'h00F000F00FFF0FFF;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y25_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|router|Equal21~0 (
// Equation(s):
// \u0|mm_interconnect_0|router|Equal21~0_combout  = ( \u0|mm_interconnect_0|router|Equal7~1_combout  & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~3_combout  & 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout  & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout  & 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~3_combout ),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout ),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout ),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|router|Equal7~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router|Equal21~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router|Equal21~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router|Equal21~0 .lut_mask = 64'h0000000000010001;
defparam \u0|mm_interconnect_0|router|Equal21~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y25_N43
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[15] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|router|Equal21~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [15]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[15] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[15] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y25_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|src15_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|src15_valid~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [15] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q  & ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout  ) ) ) # ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [15] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q  & ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout  ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [15] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q  & ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout  ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [15]),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux|src15_valid~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|src15_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|src15_valid~0 .lut_mask = 64'h0F0F0F0F00000F0F;
defparam \u0|mm_interconnect_0|cmd_demux|src15_valid~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y25_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|src15_valid~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|src15_valid~1_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout  & ( \u0|mm_interconnect_0|cmd_demux|src15_valid~0_combout  & ( 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout  & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~3_combout  & 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout  & \u0|mm_interconnect_0|router|Equal7~1_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout ),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~3_combout ),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout ),
        .datad(!\u0|mm_interconnect_0|router|Equal7~1_combout ),
        .datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout ),
        .dataf(!\u0|mm_interconnect_0|cmd_demux|src15_valid~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux|src15_valid~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|src15_valid~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|src15_valid~1 .lut_mask = 64'h0000000000000001;
defparam \u0|mm_interconnect_0|cmd_demux|src15_valid~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y24_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|arb|grant[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|arb|grant[0]~1_combout  = ( \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg [1] & ( \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg [0] & ( (\u0|mm_interconnect_0|cmd_demux|src15_valid~1_combout  & 
// !\u0|mm_interconnect_0|cmd_demux_001|src15_valid~0_combout ) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg [1] & ( !\u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg [0] & ( \u0|mm_interconnect_0|cmd_demux|src15_valid~1_combout  ) 
// ) ) # ( !\u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg [1] & ( !\u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg [0] & ( \u0|mm_interconnect_0|cmd_demux|src15_valid~1_combout  ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_demux|src15_valid~1_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_demux_001|src15_valid~0_combout ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg [1]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_015|arb|grant[0]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|arb|grant[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_015|arb|grant[0]~1 .lut_mask = 64'h5555555500005050;
defparam \u0|mm_interconnect_0|cmd_mux_015|arb|grant[0]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y24_N59
dffeas \u0|mm_interconnect_0|cmd_mux_015|saved_grant[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_015|arb|grant[0]~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|cmd_mux_015|update_grant~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|saved_grant[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_015|saved_grant[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X22_Y21_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_data[32] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|src_data [32] = ((\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_WSTRB [0])) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1])

        .dataa(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
        .datab(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_015|src_data [32]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[32] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[32] .lut_mask = 64'h3737373737373737;
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[32] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X22_Y21_N5
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_015|src_data [32]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y21_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|WideOr0~0_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q  & ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg 
// [3] & !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]))) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q  & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & ( 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1])) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|WideOr0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|WideOr0~0 .lut_mask = 64'hA000800000000000;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|WideOr0~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y19_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg~0_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_read~0_combout  & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|WideOr0~0_combout  & 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|WideOr0~0_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_read~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg~0 .lut_mask = 64'h00000000C0C0C0C0;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y21_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter~0_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_write~combout  & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override~q  & 
// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [0]) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [1]))) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_write~combout  & ( 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override~q  & (\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg~0_combout  & 
// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [0]) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [1])))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override~q ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [1]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_write~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter~0 .lut_mask = 64'h0501050111551155;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y21_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter~2_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [0] & ( 
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter~0_combout  & !\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [1]) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [0] & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter~0_combout  & \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [1]) 
// ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter~0_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter~2 .lut_mask = 64'h000F000F0F000F00;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y21_N38
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y21_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~0_combout  = ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [1] & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override~q  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~0 .lut_mask = 64'h00FF00FF00000000;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y21_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~1_combout  = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|WideOr0~0_combout  & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|WideOr0~0_combout  & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~0_combout  & (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [0] $ (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write~0_combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [0]),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|WideOr0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~1 .lut_mask = 64'h04400440CCCCCCCC;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y21_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  = ( 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( 
// (((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q  & 
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) ) ) # ( 
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q 
// ) # ((\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~1_combout  & (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~1_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .datag(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .extended_lut = "on";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .lut_mask = 64'h0F00F1F10000F1F1;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y25_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|sink_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|sink_ready~2_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout  & ( \u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & ( 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout  & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~3_combout  & (\u0|mm_interconnect_0|router|Equal7~1_combout  & 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout ),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~3_combout ),
        .datac(!\u0|mm_interconnect_0|router|Equal7~1_combout ),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout ),
        .datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout ),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux|sink_ready~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|sink_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|sink_ready~2 .lut_mask = 64'h0000000000000001;
defparam \u0|mm_interconnect_0|cmd_demux|sink_ready~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y25_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|sink_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|sink_ready~1_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~3_combout  & ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & ( 
// (\u0|mm_interconnect_0|router|Equal7~1_combout  & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout  & (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout  & 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|router|Equal7~1_combout ),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout ),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout ),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout ),
        .datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~3_combout ),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux|sink_ready~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|sink_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|sink_ready~1 .lut_mask = 64'h0000000000000010;
defparam \u0|mm_interconnect_0|cmd_demux|sink_ready~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y25_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|WideOr0~0_combout  = ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  & ( \u0|mm_interconnect_0|cmd_demux|sink_ready~1_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & ((!\u0|mm_interconnect_0|cmd_demux|sink_ready~2_combout ) # 
// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  & 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )))) ) ) ) # ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  & ( !\u0|mm_interconnect_0|cmd_demux|sink_ready~1_combout  & ( (!\u0|mm_interconnect_0|cmd_demux|sink_ready~2_combout ) # 
// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  & 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  & ( !\u0|mm_interconnect_0|cmd_demux|sink_ready~1_combout  & ( (!\u0|mm_interconnect_0|cmd_demux|sink_ready~2_combout ) # 
// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  & 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_demux|sink_ready~2_combout ),
        .datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
        .dataf(!\u0|mm_interconnect_0|cmd_demux|sink_ready~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux|WideOr0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|WideOr0~0 .lut_mask = 64'hFF88FF88F0800000;
defparam \u0|mm_interconnect_0|cmd_demux|WideOr0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y25_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|sink_ready~10 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|sink_ready~10_combout  = ( !\u0|mm_interconnect_0|cmd_demux|src0_valid~0_combout  & ( \u0|mm_interconnect_0|cmd_demux|sink_ready~7_combout  & ( (!\u0|mm_interconnect_0|router|src_data[103]~0_combout  & 
// (!\u0|mm_interconnect_0|router|Equal20~0_combout  & (!\u0|mm_interconnect_0|router|Equal6~7_combout  & !\u0|mm_interconnect_0|router|Equal14~1_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|router|src_data[103]~0_combout ),
        .datab(!\u0|mm_interconnect_0|router|Equal20~0_combout ),
        .datac(!\u0|mm_interconnect_0|router|Equal6~7_combout ),
        .datad(!\u0|mm_interconnect_0|router|Equal14~1_combout ),
        .datae(!\u0|mm_interconnect_0|cmd_demux|src0_valid~0_combout ),
        .dataf(!\u0|mm_interconnect_0|cmd_demux|sink_ready~7_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux|sink_ready~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|sink_ready~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|sink_ready~10 .lut_mask = 64'h0000000080000000;
defparam \u0|mm_interconnect_0|cmd_demux|sink_ready~10 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y27_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|WideOr0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|WideOr0~combout  = ( \u0|mm_interconnect_0|cmd_demux|WideOr0~1_combout  & ( \u0|mm_interconnect_0|cmd_demux|WideOr0~3_combout  & ( (\u0|mm_interconnect_0|cmd_demux|WideOr0~0_combout  & 
// (!\u0|mm_interconnect_0|cmd_demux|sink_ready~0_combout  & (!\u0|mm_interconnect_0|cmd_demux|sink_ready~10_combout  & \u0|mm_interconnect_0|cmd_demux|WideOr0~2_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_demux|WideOr0~0_combout ),
        .datab(!\u0|mm_interconnect_0|cmd_demux|sink_ready~0_combout ),
        .datac(!\u0|mm_interconnect_0|cmd_demux|sink_ready~10_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_demux|WideOr0~2_combout ),
        .datae(!\u0|mm_interconnect_0|cmd_demux|WideOr0~1_combout ),
        .dataf(!\u0|mm_interconnect_0|cmd_demux|WideOr0~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux|WideOr0~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|WideOr0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|WideOr0 .lut_mask = 64'h0000000000000040;
defparam \u0|mm_interconnect_0|cmd_demux|WideOr0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y22_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_payload~9 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_payload~9_combout  = ( \u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout  & ( !\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout  & ( 
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][130]~q  ) ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][130]~q ),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout ),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_payload~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~9 .lut_mask = 64'h0000555500000000;
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y22_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_payload~10 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_payload~10_combout  = ( \u0|mm_interconnect_0|rsp_mux|src_payload~0_combout  & ( \u0|mm_interconnect_0|rsp_mux|src_payload~1_combout  & ( (!\u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout  & 
// (!\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout  & ((!\u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout ) # (!\u0|mm_interconnect_0|rsp_mux|src_payload~2_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|rsp_mux|src_payload~0_combout  & ( 
// \u0|mm_interconnect_0|rsp_mux|src_payload~1_combout  & ( (!\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout  & ((!\u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout ) # (!\u0|mm_interconnect_0|rsp_mux|src_payload~2_combout ))) ) ) ) # ( 
// \u0|mm_interconnect_0|rsp_mux|src_payload~0_combout  & ( !\u0|mm_interconnect_0|rsp_mux|src_payload~1_combout  & ( (!\u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout  & ((!\u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout ) # 
// (!\u0|mm_interconnect_0|rsp_mux|src_payload~2_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|rsp_mux|src_payload~0_combout  & ( !\u0|mm_interconnect_0|rsp_mux|src_payload~1_combout  & ( (!\u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout ) # 
// (!\u0|mm_interconnect_0|rsp_mux|src_payload~2_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout ),
        .datab(!\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout ),
        .datac(!\u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout ),
        .datad(!\u0|mm_interconnect_0|rsp_mux|src_payload~2_combout ),
        .datae(!\u0|mm_interconnect_0|rsp_mux|src_payload~0_combout ),
        .dataf(!\u0|mm_interconnect_0|rsp_mux|src_payload~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_payload~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~10 .lut_mask = 64'hFFF0AAA0CCC08880;
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~10 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y24_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_payload~12 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_payload~12_combout  = ( \u0|mm_interconnect_0|rsp_mux|src_payload~5_combout  & ( \u0|mm_interconnect_0|rsp_mux|src_payload~4_combout  & ( (!\u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout  & 
// (!\u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout  & ((!\u0|mm_interconnect_0|rsp_mux|src_payload~3_combout ) # (!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|rsp_mux|src_payload~5_combout  & ( 
// \u0|mm_interconnect_0|rsp_mux|src_payload~4_combout  & ( (!\u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout  & ((!\u0|mm_interconnect_0|rsp_mux|src_payload~3_combout ) # (!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout ))) ) ) ) # ( 
// \u0|mm_interconnect_0|rsp_mux|src_payload~5_combout  & ( !\u0|mm_interconnect_0|rsp_mux|src_payload~4_combout  & ( (!\u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout  & ((!\u0|mm_interconnect_0|rsp_mux|src_payload~3_combout ) # 
// (!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|rsp_mux|src_payload~5_combout  & ( !\u0|mm_interconnect_0|rsp_mux|src_payload~4_combout  & ( (!\u0|mm_interconnect_0|rsp_mux|src_payload~3_combout ) # 
// (!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_mux|src_payload~3_combout ),
        .datab(!\u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout ),
        .datac(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout ),
        .datad(!\u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout ),
        .datae(!\u0|mm_interconnect_0|rsp_mux|src_payload~5_combout ),
        .dataf(!\u0|mm_interconnect_0|rsp_mux|src_payload~4_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_payload~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~12 .lut_mask = 64'hFAFAFA00C8C8C800;
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~12 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y30_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_payload~11 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_payload~11_combout  = ( \u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout  & ( \u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout  & ( (!\u0|mm_interconnect_0|rsp_mux|src_payload~7_combout  & 
// (!\u0|mm_interconnect_0|rsp_mux|src_payload~6_combout  & ((!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout ) # (!\u0|mm_interconnect_0|rsp_mux|src_payload~8_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout  & ( 
// \u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout  & ( (!\u0|mm_interconnect_0|rsp_mux|src_payload~6_combout  & ((!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout ) # (!\u0|mm_interconnect_0|rsp_mux|src_payload~8_combout ))) ) ) ) # ( 
// \u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout  & ( !\u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout  & ( (!\u0|mm_interconnect_0|rsp_mux|src_payload~7_combout  & ((!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout ) # 
// (!\u0|mm_interconnect_0|rsp_mux|src_payload~8_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout  & ( !\u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout  & ( (!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout ) # 
// (!\u0|mm_interconnect_0|rsp_mux|src_payload~8_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout ),
        .datab(!\u0|mm_interconnect_0|rsp_mux|src_payload~7_combout ),
        .datac(!\u0|mm_interconnect_0|rsp_mux|src_payload~6_combout ),
        .datad(!\u0|mm_interconnect_0|rsp_mux|src_payload~8_combout ),
        .datae(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout ),
        .dataf(!\u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|src_payload~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~11 .lut_mask = 64'hFFAACC88F0A0C080;
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~11 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y26_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|response_sink_accepted (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|response_sink_accepted~combout  = ( \u0|mm_interconnect_0|rsp_mux|src_payload~12_combout  & ( \u0|mm_interconnect_0|rsp_mux|src_payload~11_combout  & ( (\u0|hps_0|fpga_interfaces|h2f_BREADY [0] & 
// (\u0|mm_interconnect_0|rsp_mux|WideOr1~combout  & ((!\u0|mm_interconnect_0|rsp_mux|src_payload~10_combout ) # (\u0|mm_interconnect_0|rsp_mux|src_payload~9_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|rsp_mux|src_payload~12_combout  & ( 
// \u0|mm_interconnect_0|rsp_mux|src_payload~11_combout  & ( (\u0|hps_0|fpga_interfaces|h2f_BREADY [0] & \u0|mm_interconnect_0|rsp_mux|WideOr1~combout ) ) ) ) # ( \u0|mm_interconnect_0|rsp_mux|src_payload~12_combout  & ( 
// !\u0|mm_interconnect_0|rsp_mux|src_payload~11_combout  & ( (\u0|hps_0|fpga_interfaces|h2f_BREADY [0] & \u0|mm_interconnect_0|rsp_mux|WideOr1~combout ) ) ) ) # ( !\u0|mm_interconnect_0|rsp_mux|src_payload~12_combout  & ( 
// !\u0|mm_interconnect_0|rsp_mux|src_payload~11_combout  & ( (\u0|hps_0|fpga_interfaces|h2f_BREADY [0] & \u0|mm_interconnect_0|rsp_mux|WideOr1~combout ) ) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_BREADY [0]),
        .datab(!\u0|mm_interconnect_0|rsp_mux|src_payload~9_combout ),
        .datac(!\u0|mm_interconnect_0|rsp_mux|src_payload~10_combout ),
        .datad(!\u0|mm_interconnect_0|rsp_mux|WideOr1~combout ),
        .datae(!\u0|mm_interconnect_0|rsp_mux|src_payload~12_combout ),
        .dataf(!\u0|mm_interconnect_0|rsp_mux|src_payload~11_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|response_sink_accepted~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|response_sink_accepted .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|response_sink_accepted .lut_mask = 64'h0055005500550051;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|response_sink_accepted .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y27_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|next_pending_response_count~1 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|next_pending_response_count~1_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count [0] & ( \u0|mm_interconnect_0|cmd_demux|WideOr0~4_combout  & ( 
// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|response_sink_accepted~combout  & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ) # ((!\u0|hps_0|fpga_interfaces|h2f_WLAST [0]) # 
// (!\u0|mm_interconnect_0|cmd_demux|sink_ready~0_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count [0] & ( \u0|mm_interconnect_0|cmd_demux|WideOr0~4_combout  & ( 
// ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout  & (\u0|hps_0|fpga_interfaces|h2f_WLAST [0] & \u0|mm_interconnect_0|cmd_demux|sink_ready~0_combout ))) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|response_sink_accepted~combout ) ) ) ) # ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count [0] & ( !\u0|mm_interconnect_0|cmd_demux|WideOr0~4_combout  & ( 
// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|response_sink_accepted~combout  & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ) # (!\u0|hps_0|fpga_interfaces|h2f_WLAST [0]))) ) ) ) # ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count [0] & ( !\u0|mm_interconnect_0|cmd_demux|WideOr0~4_combout  & ( ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout  & 
// \u0|hps_0|fpga_interfaces|h2f_WLAST [0])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|response_sink_accepted~combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_WLAST [0]),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|response_sink_accepted~combout ),
        .datad(!\u0|mm_interconnect_0|cmd_demux|sink_ready~0_combout ),
        .datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count [0]),
        .dataf(!\u0|mm_interconnect_0|cmd_demux|WideOr0~4_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|next_pending_response_count~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|next_pending_response_count~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|next_pending_response_count~1 .lut_mask = 64'h1F1FE0E00F1FF0E0;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|next_pending_response_count~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y27_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|always1~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|always1~0_combout  = ( \u0|mm_interconnect_0|cmd_demux|WideOr0~4_combout  & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|response_sink_accepted~combout ) # 
// ((!\u0|hps_0|fpga_interfaces|h2f_WLAST [0]) # ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ) # (!\u0|mm_interconnect_0|cmd_demux|sink_ready~0_combout ))) ) ) # ( !\u0|mm_interconnect_0|cmd_demux|WideOr0~4_combout  & ( 
// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|response_sink_accepted~combout ) # ((!\u0|hps_0|fpga_interfaces|h2f_WLAST [0]) # (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|response_sink_accepted~combout ),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_WLAST [0]),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_demux|sink_ready~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_demux|WideOr0~4_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|always1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|always1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|always1~0 .lut_mask = 64'hFEFEFEFEFFFEFFFE;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|always1~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y27_N2
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|next_pending_response_count~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|always1~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y27_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|next_pending_response_count~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|next_pending_response_count~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count [1] & ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout  & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count [0] & 
// (((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|response_sink_accepted~combout )))) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count [0] & ((!\u0|hps_0|fpga_interfaces|h2f_WLAST [0]) # 
// ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|response_sink_accepted~combout ) # (\u0|mm_interconnect_0|cmd_demux|WideOr0~combout )))) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count [1] & ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout  & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count [0] & 
// (((\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|response_sink_accepted~combout )))) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count [0] & (\u0|hps_0|fpga_interfaces|h2f_WLAST [0] & 
// (!\u0|mm_interconnect_0|cmd_demux|WideOr0~combout  & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|response_sink_accepted~combout ))) ) ) ) # ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count [1] & ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout  & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|response_sink_accepted~combout ) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count 
// [0]) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count [1] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout  & ( 
// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count [0] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|response_sink_accepted~combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count [0]),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_WLAST [0]),
        .datac(!\u0|mm_interconnect_0|cmd_demux|WideOr0~combout ),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|response_sink_accepted~combout ),
        .datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count [1]),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|next_pending_response_count~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|next_pending_response_count~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|next_pending_response_count~0 .lut_mask = 64'h00AAFF5510AAEF55;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|next_pending_response_count~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y27_N50
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|next_pending_response_count~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|always1~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y27_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~0_combout  = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count [1] & ( 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|response_sink_accepted~combout  & \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count [0]) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|response_sink_accepted~combout ),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~0 .lut_mask = 64'h0055005500000000;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y27_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~1 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~1_combout  = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count [1] & ( 
// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|response_sink_accepted~combout  & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count [0]) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|response_sink_accepted~combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~1 .lut_mask = 64'hA0A0A0A000000000;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y27_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~2 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~2_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q  & ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~1_combout  & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~0_combout ) # ((!\u0|mm_interconnect_0|cmd_demux|WideOr0~combout  & 
// (\u0|hps_0|fpga_interfaces|h2f_WLAST [0] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q  & ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~1_combout  & ( (!\u0|mm_interconnect_0|cmd_demux|WideOr0~combout  & (\u0|hps_0|fpga_interfaces|h2f_WLAST [0] & 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout )) ) ) ) # ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q  & ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~1_combout  & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~0_combout ) # ((!\u0|mm_interconnect_0|cmd_demux|WideOr0~combout  & 
// (\u0|hps_0|fpga_interfaces|h2f_WLAST [0] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_demux|WideOr0~combout ),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_WLAST [0]),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~0_combout ),
        .datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q ),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~2 .lut_mask = 64'h0000FF020202FF02;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y27_N20
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y25_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|router|src_data[103]~1 (
// Equation(s):
// \u0|mm_interconnect_0|router|src_data[103]~1_combout  = ( !\u0|mm_interconnect_0|router|src_data[103]~0_combout  & ( (!\u0|mm_interconnect_0|router|Equal6~7_combout  & (!\u0|mm_interconnect_0|router|Equal20~0_combout  & 
// (!\u0|mm_interconnect_0|router|Equal21~0_combout  & !\u0|mm_interconnect_0|router|Equal14~1_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|router|Equal6~7_combout ),
        .datab(!\u0|mm_interconnect_0|router|Equal20~0_combout ),
        .datac(!\u0|mm_interconnect_0|router|Equal21~0_combout ),
        .datad(!\u0|mm_interconnect_0|router|Equal14~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|router|src_data[103]~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router|src_data[103]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router|src_data[103]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router|src_data[103]~1 .lut_mask = 64'h8000800000000000;
defparam \u0|mm_interconnect_0|router|src_data[103]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y25_N28
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|router|src_data[103]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y25_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|router|src_data~2 (
// Equation(s):
// \u0|mm_interconnect_0|router|src_data~2_combout  = ( \u0|mm_interconnect_0|router|Equal7~1_combout  & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout  & \u0|mm_interconnect_0|router|Equal14~0_combout ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout ),
        .datad(!\u0|mm_interconnect_0|router|Equal14~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|router|Equal7~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router|src_data~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router|src_data~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router|src_data~2 .lut_mask = 64'h00000000000F000F;
defparam \u0|mm_interconnect_0|router|src_data~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y25_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|router|src_data[101]~5 (
// Equation(s):
// \u0|mm_interconnect_0|router|src_data[101]~5_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout  & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout  & 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout  & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~3_combout  & \u0|mm_interconnect_0|router|Equal7~1_combout ))) ) ) # ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout  & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~3_combout  & (\u0|mm_interconnect_0|router|Equal7~1_combout  & 
// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout  $ (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout ),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout ),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~3_combout ),
        .datad(!\u0|mm_interconnect_0|router|Equal7~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router|src_data[101]~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router|src_data[101]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router|src_data[101]~5 .lut_mask = 64'h0009000900010001;
defparam \u0|mm_interconnect_0|router|src_data[101]~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y25_N47
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|router|src_data[101]~5_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y25_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~1 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~1_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout  & ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout  & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id [1] $ (((!\u0|mm_interconnect_0|router|Equal7~1_combout ) # 
// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~3_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout  & ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout  & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id [1] ) ) ) # ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout  & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout  & ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id [1] ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout  & ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout  & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id [1] $ (((!\u0|mm_interconnect_0|router|Equal7~1_combout ) # 
// ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~3_combout ) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout )))) ) ) )

        .dataa(!\u0|mm_interconnect_0|router|Equal7~1_combout ),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~3_combout ),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id [1]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout ),
        .datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout ),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~1 .lut_mask = 64'h1E0F0F0F0F0F1E1E;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y25_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|router|src_data~4 (
// Equation(s):
// \u0|mm_interconnect_0|router|src_data~4_combout  = ( \u0|mm_interconnect_0|router|src_data~2_combout  ) # ( !\u0|mm_interconnect_0|router|src_data~2_combout  & ( (\u0|mm_interconnect_0|router|Equal20~0_combout ) # 
// (\u0|mm_interconnect_0|router|Equal6~7_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|router|Equal6~7_combout ),
        .datab(!\u0|mm_interconnect_0|router|Equal20~0_combout ),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|router|src_data~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router|src_data~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router|src_data~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router|src_data~4 .lut_mask = 64'h77777777FFFFFFFF;
defparam \u0|mm_interconnect_0|router|src_data~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y25_N25
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|router|src_data~4_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y25_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|router|src_data[104]~6 (
// Equation(s):
// \u0|mm_interconnect_0|router|src_data[104]~6_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout  & ( (\u0|mm_interconnect_0|router|Equal7~1_combout  & 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|router|Equal7~1_combout ),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout ),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router|src_data[104]~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router|src_data[104]~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router|src_data[104]~6 .lut_mask = 64'h0000000011111111;
defparam \u0|mm_interconnect_0|router|src_data[104]~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y25_N19
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|router|src_data[104]~6_combout ),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y25_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~2 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~2_combout  = !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id [4] $ (((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout ) # 
// ((!\u0|mm_interconnect_0|router|Equal7~1_combout ) # (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout ))))

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout ),
        .datab(!\u0|mm_interconnect_0|router|Equal7~1_combout ),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id [4]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~2 .lut_mask = 64'h0F1E0F1E0F1E0F1E;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y25_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~3 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~3_combout  = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~2_combout  & ( \u0|mm_interconnect_0|router|Equal6~7_combout  & ( 
// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~1_combout  & \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id [0]) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~2_combout  & ( 
// !\u0|mm_interconnect_0|router|Equal6~7_combout  & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~1_combout  & (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id [0] $ (((\u0|mm_interconnect_0|router|Equal20~0_combout ) 
// # (\u0|mm_interconnect_0|router|src_data~2_combout ))))) ) ) )

        .dataa(!\u0|mm_interconnect_0|router|src_data~2_combout ),
        .datab(!\u0|mm_interconnect_0|router|Equal20~0_combout ),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~1_combout ),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id [0]),
        .datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~2_combout ),
        .dataf(!\u0|mm_interconnect_0|router|Equal6~7_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~3 .lut_mask = 64'h8070000000F00000;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y25_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|router|src_data[102]~3 (
// Equation(s):
// \u0|mm_interconnect_0|router|src_data[102]~3_combout  = ( !\u0|mm_interconnect_0|router|Equal21~0_combout  & ( (!\u0|mm_interconnect_0|router|Equal6~7_combout  & (!\u0|mm_interconnect_0|router|Equal14~1_combout  & 
// !\u0|mm_interconnect_0|router|Equal20~0_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|router|Equal6~7_combout ),
        .datab(!\u0|mm_interconnect_0|router|Equal14~1_combout ),
        .datac(!\u0|mm_interconnect_0|router|Equal20~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|router|Equal21~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router|src_data[102]~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router|src_data[102]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router|src_data[102]~3 .lut_mask = 64'h8080808000000000;
defparam \u0|mm_interconnect_0|router|src_data[102]~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y25_N11
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|router|src_data[102]~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id[2] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y25_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~0_combout  = ( \u0|mm_interconnect_0|router|Equal21~0_combout  & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id [2] ) ) # ( !\u0|mm_interconnect_0|router|Equal21~0_combout 
//  & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id [2] $ (((!\u0|mm_interconnect_0|router|Equal20~0_combout  & (!\u0|mm_interconnect_0|router|Equal14~1_combout  & !\u0|mm_interconnect_0|router|Equal6~7_combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|router|Equal20~0_combout ),
        .datab(!\u0|mm_interconnect_0|router|Equal14~1_combout ),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id [2]),
        .datad(!\u0|mm_interconnect_0|router|Equal6~7_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|router|Equal21~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~0 .lut_mask = 64'h78F078F0F0F0F0F0;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y25_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~3_combout  & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~0_combout  & ( 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout  & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q ) # (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id [3] $ 
// (\u0|mm_interconnect_0|router|src_data[103]~1_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~3_combout  & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~0_combout  & ( 
// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q  & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout ) ) ) ) # ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~3_combout  & ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~0_combout  & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q  & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout ) ) ) ) # ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~3_combout  & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~0_combout  & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q  & 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q ),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id [3]),
        .datac(!\u0|mm_interconnect_0|router|src_data[103]~1_combout ),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout ),
        .datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~3_combout ),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0 .lut_mask = 64'h00AA00AA00AA00EB;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y27_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ( \u0|mm_interconnect_0|cmd_demux|WideOr0~4_combout  & ( 
// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ) # ((!\u0|mm_interconnect_0|cmd_demux|sink_ready~0_combout ) # (!\u0|hps_0|fpga_interfaces|h2f_WLAST [0])) ) ) ) # ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ( \u0|mm_interconnect_0|cmd_demux|WideOr0~4_combout  & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout  & 
// (\u0|mm_interconnect_0|cmd_demux|sink_ready~0_combout  & !\u0|hps_0|fpga_interfaces|h2f_WLAST [0])) ) ) ) # ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ( !\u0|mm_interconnect_0|cmd_demux|WideOr0~4_combout  & ( 
// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ) # (!\u0|hps_0|fpga_interfaces|h2f_WLAST [0]) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & ( 
// !\u0|mm_interconnect_0|cmd_demux|WideOr0~4_combout  & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout  & !\u0|hps_0|fpga_interfaces|h2f_WLAST [0]) ) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ),
        .datab(!\u0|mm_interconnect_0|cmd_demux|sink_ready~0_combout ),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_WLAST [0]),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
        .dataf(!\u0|mm_interconnect_0|cmd_demux|WideOr0~4_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~0 .lut_mask = 64'h5050FAFA1010FEFE;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y27_N17
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y28_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|router|Equal14~0 (
// Equation(s):
// \u0|mm_interconnect_0|router|Equal14~0_combout  = ( \u0|hps_0|fpga_interfaces|h2f_AWADDR [18] & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [19] 
// & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [18])) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_AWADDR [18] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & 
// (((\u0|hps_0|fpga_interfaces|h2f_AWADDR [19])))) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q  & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [19] & 
// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [18]))) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [19]),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [18]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [19]),
        .datae(gnd),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [18]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router|Equal14~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router|Equal14~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router|Equal14~0 .lut_mask = 64'h10BA10BA10101010;
defparam \u0|mm_interconnect_0|router|Equal14~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y25_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|router|Equal17~0 (
// Equation(s):
// \u0|mm_interconnect_0|router|Equal17~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout  & ( (\u0|mm_interconnect_0|router|Equal14~0_combout  & 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout  & \u0|mm_interconnect_0|router|Equal7~1_combout )) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|router|Equal14~0_combout ),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout ),
        .datad(!\u0|mm_interconnect_0|router|Equal7~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router|Equal17~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router|Equal17~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router|Equal17~0 .lut_mask = 64'h0000000000030003;
defparam \u0|mm_interconnect_0|router|Equal17~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X23_Y25_N41
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[11] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|router|Equal17~0_combout ),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [11]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[11] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[11] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X23_Y25_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|src11_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|src11_valid~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout  & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q ) # 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [11]) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [11]),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux|src11_valid~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|src11_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|src11_valid~0 .lut_mask = 64'h00000000FF0FFF0F;
defparam \u0|mm_interconnect_0|cmd_demux|src11_valid~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y23_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|arb|grant[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|arb|grant[0]~1_combout  = ( \u0|mm_interconnect_0|router|Equal17~0_combout  & ( (\u0|mm_interconnect_0|cmd_demux|src11_valid~0_combout  & ((!\u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg [0]) # 
// ((!\u0|mm_interconnect_0|cmd_demux_001|src11_valid~1_combout  & \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg [1])))) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_demux|src11_valid~0_combout ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg [0]),
        .datac(!\u0|mm_interconnect_0|cmd_demux_001|src11_valid~1_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg [1]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|router|Equal17~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_011|arb|grant[0]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|arb|grant[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|arb|grant[0]~1 .lut_mask = 64'h0000000044544454;
defparam \u0|mm_interconnect_0|cmd_mux_011|arb|grant[0]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y23_N11
dffeas \u0|mm_interconnect_0|cmd_mux_011|saved_grant[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_011|arb|grant[0]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|cmd_mux_011|update_grant~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|saved_grant[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_011|saved_grant[0] .power_up = "low";
// synopsys translate_on

// Location: FF_X22_Y20_N56
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y20_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|local_write~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent|local_write~0_combout  = (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] & 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|local_write~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|local_write~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|local_write~0 .lut_mask = 64'h000F000F000F000F;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|local_write~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y20_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|m0_write (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent|m0_write~combout  = ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent|local_write~0_combout  & 
// !\u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent|local_write~0_combout ),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0_combout ),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|m0_write~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|m0_write .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|m0_write .lut_mask = 64'h4444444400000000;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|m0_write .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y20_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter~0_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [0] & ( (\u0|mm_interconnect_0|write_en_tx_s1_translator|waitrequest_reset_override~q  & 
// (((\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [1] & \u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg~0_combout )) # (\u0|mm_interconnect_0|write_en_tx_s1_agent|m0_write~combout ))) ) ) # ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [0] & ( (\u0|mm_interconnect_0|write_en_tx_s1_translator|waitrequest_reset_override~q  & ((!\u0|mm_interconnect_0|write_en_tx_s1_agent|m0_write~combout  & 
// ((\u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg~0_combout ))) # (\u0|mm_interconnect_0|write_en_tx_s1_agent|m0_write~combout  & (\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [1])))) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [1]),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_translator|waitrequest_reset_override~q ),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent|m0_write~combout ),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter~0 .lut_mask = 64'h0131013103130313;
defparam \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y20_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter~1_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter~0_combout  & ( !\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [0] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter~1 .lut_mask = 64'h00000000FF00FF00;
defparam \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X21_Y20_N53
dffeas \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X21_Y20_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~4 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~4_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [0] & 
// \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~0_combout ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~0_combout  & 
// (!\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [0] $ (((!\u0|mm_interconnect_0|write_en_tx_s1_agent|local_write~0_combout ) # (\u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0_combout ))))) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [0]),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0_combout ),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent|local_write~0_combout ),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~4 .lut_mask = 64'h0059005900550055;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y18_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|write~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|write~0_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_agent|local_write~0_combout  & ( 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & 
// ((\u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0_combout ) # (\u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~4_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|local_write~0_combout  & ( 
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent|m0_read~0_combout  & (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used 
// [1] & ((\u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0_combout ) # (\u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~4_combout )))) ) ) ) # ( \u0|mm_interconnect_0|write_en_tx_s1_agent|local_write~0_combout  & ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent|m0_read~0_combout  & (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used 
// [1] & ((\u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0_combout ) # (\u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~4_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|local_write~0_combout  & ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent|m0_read~0_combout  & (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used 
// [1] & ((\u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0_combout ) # (\u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~4_combout )))) ) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~4_combout ),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0_combout ),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent|m0_read~0_combout ),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),
        .datae(!\u0|mm_interconnect_0|write_en_tx_s1_agent|local_write~0_combout ),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|write~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|write~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h0700070007007700;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|write~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X17_Y18_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used[1]~0_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout  & ( 
// (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|write~0_combout ) # (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [0]) ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & ( 
// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout  & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|write~0_combout  & \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [0]) ) ) ) # ( 
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout  & ( (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|write~0_combout  & 
// (!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|always0~0_combout )) # (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|write~0_combout  & ((\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [0]) # 
// (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|always0~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout  & ( 
// (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|write~0_combout  & (!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|always0~0_combout  & \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [0])) ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|write~0_combout ),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|always0~0_combout ),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [0]),
        .datae(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used[1]~0 .lut_mask = 64'h0030C3F30033CCFF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used[1]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X17_Y18_N20
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on

// Location: FF_X17_Y18_N59
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~3_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][66]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y18_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~3 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~3_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][66]~q  & ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] 
// ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][66]~q  & ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] ) ) ) # ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][66]~q  & ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),
        .datae(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][66]~q ),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h000000FFFF00FFFF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y18_N23
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][66] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~3_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][66]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";
// synopsys translate_on

// Location: FF_X17_Y18_N5
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][69] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][69]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][69] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X17_Y18_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~1_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][69]~q  & ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] 
// ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][69]~q  & ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] ) ) ) # ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][69]~q  & ( 
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] ) ) )

        .dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][69]~q ),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h00005555AAAAFFFF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y18_N2
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][69] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~1_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][69]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][69] .power_up = "low";
// synopsys translate_on

// Location: FF_X19_Y20_N53
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][68] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][68]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][68] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][68] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X19_Y20_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~2 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~2_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] & ( (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used 
// [1]) # (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][68]~q ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] & ( 
// (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][68]~q ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][68]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~2 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X18_Y18_N58
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][68] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~2_combout ),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][68]~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][68] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][68] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X18_Y18_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_011|src0_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_011|src0_valid~0_combout  = ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][68]~q  & ( (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][66]~q  & 
// !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][69]~q ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][66]~q ),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][69]~q ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][68]~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_demux_011|src0_valid~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_011|src0_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_011|src0_valid~0 .lut_mask = 64'h00000000F000F000;
defparam \u0|mm_interconnect_0|rsp_demux_011|src0_valid~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y22_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_011|src0_valid~1 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout  = ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|rp_valid~combout  & ( \u0|mm_interconnect_0|rsp_demux_011|src0_valid~0_combout  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|rsp_demux_011|src0_valid~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent|rp_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_011|src0_valid~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_011|src0_valid~1 .lut_mask = 64'h00FF00FF00000000;
defparam \u0|mm_interconnect_0|rsp_demux_011|src0_valid~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X18_Y24_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|WideOr1~1 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|WideOr1~1_combout  = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|rp_valid~combout  & ( \u0|mm_interconnect_0|rsp_demux_009|src0_valid~0_combout  & ( (\u0|mm_interconnect_0|link_disable_s1_agent|rp_valid~combout  & 
// ((!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ) # (\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ))) ) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|rp_valid~combout  & ( 
// \u0|mm_interconnect_0|rsp_demux_009|src0_valid~0_combout  & ( (\u0|mm_interconnect_0|link_disable_s1_agent|rp_valid~combout  & (!\u0|mm_interconnect_0|rsp_demux_010|src0_valid~0_combout  & ((!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ) # 
// (\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout )))) ) ) ) # ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|rp_valid~combout  & ( !\u0|mm_interconnect_0|rsp_demux_009|src0_valid~0_combout  & ( 
// (!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ) # (\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ) ) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|rp_valid~combout  & ( 
// !\u0|mm_interconnect_0|rsp_demux_009|src0_valid~0_combout  & ( (!\u0|mm_interconnect_0|rsp_demux_010|src0_valid~0_combout  & ((!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ) # (\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ))) ) 
// ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_agent|rp_valid~combout ),
        .datac(!\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ),
        .datad(!\u0|mm_interconnect_0|rsp_demux_010|src0_valid~0_combout ),
        .datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|rp_valid~combout ),
        .dataf(!\u0|mm_interconnect_0|rsp_demux_009|src0_valid~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|WideOr1~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|WideOr1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|WideOr1~1 .lut_mask = 64'hAF00AFAF23002323;
defparam \u0|mm_interconnect_0|rsp_mux|WideOr1~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y26_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|WideOr1~0 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|WideOr1~0_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout  & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout  & ( (!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ) # 
// (\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout ) ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout  & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout  & ( 
// (!\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout  & ((!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ) # (\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout ))) ) ) ) # ( 
// \u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout  & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout  & ( (!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout  & 
// ((!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ) # (\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout ))) ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout  & ( 
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout  & ( (!\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout  & (!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout  & ((!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ) # 
// (\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout )))) ) ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ),
        .datab(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ),
        .datac(!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout ),
        .datad(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ),
        .datae(!\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ),
        .dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|WideOr1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|WideOr1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|WideOr1~0 .lut_mask = 64'h8A00CF008A8ACFCF;
defparam \u0|mm_interconnect_0|rsp_mux|WideOr1~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X21_Y22_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|WideOr1 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|WideOr1~combout  = ( \u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout  & ( \u0|mm_interconnect_0|rsp_mux|WideOr1~0_combout  ) ) # ( !\u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout  & ( 
// \u0|mm_interconnect_0|rsp_mux|WideOr1~0_combout  & ( (((!\u0|mm_interconnect_0|rsp_mux|WideOr1~1_combout ) # (\u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout )) # (\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout )) # 
// (\u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout ) ) ) ) # ( \u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout  & ( !\u0|mm_interconnect_0|rsp_mux|WideOr1~0_combout  ) ) # ( !\u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout  & ( 
// !\u0|mm_interconnect_0|rsp_mux|WideOr1~0_combout  ) )

        .dataa(!\u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout ),
        .datab(!\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout ),
        .datac(!\u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout ),
        .datad(!\u0|mm_interconnect_0|rsp_mux|WideOr1~1_combout ),
        .datae(!\u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout ),
        .dataf(!\u0|mm_interconnect_0|rsp_mux|WideOr1~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|rsp_mux|WideOr1~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|WideOr1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|WideOr1 .lut_mask = 64'hFFFFFFFFFF7FFFFF;
defparam \u0|mm_interconnect_0|rsp_mux|WideOr1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y27_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~0_combout  = ( \u0|mm_interconnect_0|cmd_demux|sink_ready~0_combout  & ( \u0|mm_interconnect_0|cmd_demux|WideOr0~4_combout  & ( (\u0|hps_0|fpga_interfaces|h2f_WLAST [0] & 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ) ) ) ) # ( \u0|mm_interconnect_0|cmd_demux|sink_ready~0_combout  & ( !\u0|mm_interconnect_0|cmd_demux|WideOr0~4_combout  & ( (\u0|hps_0|fpga_interfaces|h2f_WLAST [0] & 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ) ) ) ) # ( !\u0|mm_interconnect_0|cmd_demux|sink_ready~0_combout  & ( !\u0|mm_interconnect_0|cmd_demux|WideOr0~4_combout  & ( (\u0|hps_0|fpga_interfaces|h2f_WLAST [0] & 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ) ) ) )

        .dataa(gnd),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_WLAST [0]),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_demux|sink_ready~0_combout ),
        .dataf(!\u0|mm_interconnect_0|cmd_demux|WideOr0~4_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~0 .lut_mask = 64'h0303030300000303;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y31_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal5~0 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal5~0_combout  = ( \u0|mm_interconnect_0|router_001|Equal1~4_combout  & ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [17] ) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|router_001|Equal1~4_combout ),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router_001|Equal5~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal5~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal5~0 .lut_mask = 64'h0000555500000000;
defparam \u0|mm_interconnect_0|router_001|Equal5~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X14_Y23_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|sink_ready~9 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|sink_ready~9_combout  = ( \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  ) ) # ( 
// \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  & ( 
// ((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & ((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # 
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout )))) # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ) ) ) 
// )

        .dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datae(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
        .dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux_001|sink_ready~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~9 .lut_mask = 64'h00000F7F0000FFFF;
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~9 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X19_Y34_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|sink_ready~10 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|sink_ready~10_combout  = ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( (\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] & 
// (((\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ) # (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )) 
// # (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  
// & ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( (\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] & 
// (((\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ) # (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )) 
// # (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ))) ) ) ) # ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  
// & ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( (\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] & 
// (((\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ) # (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )) 
// # (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  
// & ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( (\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] & 
// ((\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ) # (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ))) 
// ) ) )

        .dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
        .datae(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux_001|sink_ready~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~10 .lut_mask = 64'h1133133313331333;
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~10 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X10_Y31_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|sink_ready~11 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|sink_ready~11_combout  = ( \u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( 
// ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ) # 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )) # 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] & ( 
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( 
// (((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & 
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) # 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout )) # 
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
        .datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
        .dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux_001|sink_ready~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~11 .lut_mask = 64'h00005F7F00007F7F;
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~11 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y31_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|WideOr0~5 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|WideOr0~5_combout  = ( \u0|mm_interconnect_0|cmd_demux_001|sink_ready~10_combout  & ( \u0|mm_interconnect_0|cmd_demux_001|sink_ready~11_combout  & ( (!\u0|mm_interconnect_0|router_001|Equal5~0_combout  & 
// (!\u0|mm_interconnect_0|router_001|Equal9~1_combout  & ((!\u0|mm_interconnect_0|cmd_demux_001|sink_ready~9_combout ) # (!\u0|mm_interconnect_0|router_001|Equal1~5_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|cmd_demux_001|sink_ready~10_combout  & ( 
// \u0|mm_interconnect_0|cmd_demux_001|sink_ready~11_combout  & ( (!\u0|mm_interconnect_0|router_001|Equal9~1_combout  & ((!\u0|mm_interconnect_0|cmd_demux_001|sink_ready~9_combout ) # (!\u0|mm_interconnect_0|router_001|Equal1~5_combout ))) ) ) ) # ( 
// \u0|mm_interconnect_0|cmd_demux_001|sink_ready~10_combout  & ( !\u0|mm_interconnect_0|cmd_demux_001|sink_ready~11_combout  & ( (!\u0|mm_interconnect_0|router_001|Equal5~0_combout  & ((!\u0|mm_interconnect_0|cmd_demux_001|sink_ready~9_combout ) # 
// (!\u0|mm_interconnect_0|router_001|Equal1~5_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|cmd_demux_001|sink_ready~10_combout  & ( !\u0|mm_interconnect_0|cmd_demux_001|sink_ready~11_combout  & ( (!\u0|mm_interconnect_0|cmd_demux_001|sink_ready~9_combout ) 
// # (!\u0|mm_interconnect_0|router_001|Equal1~5_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|router_001|Equal5~0_combout ),
        .datab(!\u0|mm_interconnect_0|cmd_demux_001|sink_ready~9_combout ),
        .datac(!\u0|mm_interconnect_0|router_001|Equal9~1_combout ),
        .datad(!\u0|mm_interconnect_0|router_001|Equal1~5_combout ),
        .datae(!\u0|mm_interconnect_0|cmd_demux_001|sink_ready~10_combout ),
        .dataf(!\u0|mm_interconnect_0|cmd_demux_001|sink_ready~11_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux_001|WideOr0~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|WideOr0~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|WideOr0~5 .lut_mask = 64'hFFCCAA88F0C0A080;
defparam \u0|mm_interconnect_0|cmd_demux_001|WideOr0~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y31_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|sink_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|sink_ready~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & ( \u0|mm_interconnect_0|router_001|Equal7~0_combout  & ( (\u0|mm_interconnect_0|router_001|Equal1~1_combout  & 
// (\u0|mm_interconnect_0|router_001|Equal1~2_combout  & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & \u0|mm_interconnect_0|router_001|Equal1~0_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),
        .datab(!\u0|mm_interconnect_0|router_001|Equal1~2_combout ),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),
        .datad(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),
        .datae(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
        .dataf(!\u0|mm_interconnect_0|router_001|Equal7~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux_001|sink_ready~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~0 .lut_mask = 64'h0000000000000010;
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y31_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|WideOr0~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & ( \u0|mm_interconnect_0|router_001|Equal19~1_combout  & ( 
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ) # ((\u0|mm_interconnect_0|cmd_demux_001|sink_ready~0_combout  & 
// ((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) # 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & ( \u0|mm_interconnect_0|router_001|Equal19~1_combout  & ( 
// (\u0|mm_interconnect_0|cmd_demux_001|sink_ready~0_combout  & ((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) # 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ))) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & ( !\u0|mm_interconnect_0|router_001|Equal19~1_combout  & ( 
// (\u0|mm_interconnect_0|cmd_demux_001|sink_ready~0_combout  & ((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) # 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & ( !\u0|mm_interconnect_0|router_001|Equal19~1_combout  & ( 
// (\u0|mm_interconnect_0|cmd_demux_001|sink_ready~0_combout  & ((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) # 
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
        .datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .datac(!\u0|mm_interconnect_0|cmd_demux_001|sink_ready~0_combout ),
        .datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datae(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
        .dataf(!\u0|mm_interconnect_0|router_001|Equal19~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux_001|WideOr0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|WideOr0~0 .lut_mask = 64'h030F030F030FABAF;
defparam \u0|mm_interconnect_0|cmd_demux_001|WideOr0~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y38_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|sink_ready~8 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|sink_ready~8_combout  = ( \u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( 
// ((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout )) # 
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & ( 
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( (((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & 
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout )) # 
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
        .datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ),
        .datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datae(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
        .dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux_001|sink_ready~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~8 .lut_mask = 64'h00003F7F00003FFF;
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~8 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y31_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|WideOr0~4 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|WideOr0~4_combout  = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & ( \u0|mm_interconnect_0|cmd_demux_001|sink_ready~8_combout  & ( 
// ((\u0|mm_interconnect_0|cmd_demux_001|src0_valid~0_combout  & \u0|mm_interconnect_0|cmd_mux|saved_grant [1])) # (\u0|mm_interconnect_0|router_001|Equal8~0_combout ) ) ) ) # ( 
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & ( \u0|mm_interconnect_0|cmd_demux_001|sink_ready~8_combout  & ( ((\u0|mm_interconnect_0|cmd_demux_001|src0_valid~0_combout  & 
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  & \u0|mm_interconnect_0|cmd_mux|saved_grant [1]))) # (\u0|mm_interconnect_0|router_001|Equal8~0_combout ) ) ) ) # ( 
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & ( !\u0|mm_interconnect_0|cmd_demux_001|sink_ready~8_combout  & ( (\u0|mm_interconnect_0|cmd_demux_001|src0_valid~0_combout  & 
// \u0|mm_interconnect_0|cmd_mux|saved_grant [1]) ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & ( !\u0|mm_interconnect_0|cmd_demux_001|sink_ready~8_combout  & ( 
// (\u0|mm_interconnect_0|cmd_demux_001|src0_valid~0_combout  & (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  & \u0|mm_interconnect_0|cmd_mux|saved_grant [1])) ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_demux_001|src0_valid~0_combout ),
        .datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
        .datac(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
        .datad(!\u0|mm_interconnect_0|router_001|Equal8~0_combout ),
        .datae(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .dataf(!\u0|mm_interconnect_0|cmd_demux_001|sink_ready~8_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux_001|WideOr0~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|WideOr0~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|WideOr0~4 .lut_mask = 64'h0101050501FF05FF;
defparam \u0|mm_interconnect_0|cmd_demux_001|WideOr0~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X10_Y28_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|sink_ready~5 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|sink_ready~5_combout  = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & ( \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & 
// ( (\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & (((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout )) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ))) ) ) ) # ( 
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & 
// ( (\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & ((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ))) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q  & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  
// & ( (\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & ((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ) # 
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
        .datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux_001|sink_ready~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~5 .lut_mask = 64'h005F005F007F00FF;
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y32_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|sink_ready~7 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|sink_ready~7_combout  = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  & ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & ( \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  & ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & ( (\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & 
// (((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) # 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ))) ) ) ) # ( 
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  & ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & ( \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  & ( 
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & ( 
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout  & \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ),
        .datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
        .datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
        .dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux_001|sink_ready~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~7 .lut_mask = 64'h05050F0F070F0F0F;
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~7 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X15_Y35_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|sink_ready~6 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|sink_ready~6_combout  = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & ( \u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & ( (\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & 
// (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ))) ) ) ) # ( 
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & ( (\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & 
// ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ))) ) ) ) # ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( 
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & ( (\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & 
// ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ) # 
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
        .datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux_001|sink_ready~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~6 .lut_mask = 64'h1133113313333333;
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~6 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y31_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|WideOr0~3 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|WideOr0~3_combout  = ( \u0|mm_interconnect_0|cmd_demux_001|sink_ready~6_combout  & ( \u0|mm_interconnect_0|router_001|Equal18~0_combout  & ( (!\u0|mm_interconnect_0|router_001|Equal11~0_combout  & 
// (!\u0|mm_interconnect_0|cmd_demux_001|sink_ready~7_combout  & ((!\u0|mm_interconnect_0|cmd_demux_001|sink_ready~5_combout ) # (!\u0|mm_interconnect_0|router_001|Equal3~1_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|cmd_demux_001|sink_ready~6_combout  & ( 
// \u0|mm_interconnect_0|router_001|Equal18~0_combout  & ( (!\u0|mm_interconnect_0|cmd_demux_001|sink_ready~7_combout  & ((!\u0|mm_interconnect_0|cmd_demux_001|sink_ready~5_combout ) # (!\u0|mm_interconnect_0|router_001|Equal3~1_combout ))) ) ) ) # ( 
// \u0|mm_interconnect_0|cmd_demux_001|sink_ready~6_combout  & ( !\u0|mm_interconnect_0|router_001|Equal18~0_combout  & ( (!\u0|mm_interconnect_0|router_001|Equal11~0_combout  & ((!\u0|mm_interconnect_0|cmd_demux_001|sink_ready~5_combout ) # 
// (!\u0|mm_interconnect_0|router_001|Equal3~1_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|cmd_demux_001|sink_ready~6_combout  & ( !\u0|mm_interconnect_0|router_001|Equal18~0_combout  & ( (!\u0|mm_interconnect_0|cmd_demux_001|sink_ready~5_combout ) # 
// (!\u0|mm_interconnect_0|router_001|Equal3~1_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|router_001|Equal11~0_combout ),
        .datab(!\u0|mm_interconnect_0|cmd_demux_001|sink_ready~5_combout ),
        .datac(!\u0|mm_interconnect_0|router_001|Equal3~1_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_demux_001|sink_ready~7_combout ),
        .datae(!\u0|mm_interconnect_0|cmd_demux_001|sink_ready~6_combout ),
        .dataf(!\u0|mm_interconnect_0|router_001|Equal18~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux_001|WideOr0~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|WideOr0~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|WideOr0~3 .lut_mask = 64'hFCFCA8A8FC00A800;
defparam \u0|mm_interconnect_0|cmd_demux_001|WideOr0~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y31_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal6~0 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal6~0_combout  = ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [17] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router_001|Equal6~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal6~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal6~0 .lut_mask = 64'h00000000FFFF0000;
defparam \u0|mm_interconnect_0|router_001|Equal6~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y31_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|sink_ready~4 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|sink_ready~4_combout  = ( \u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & ( \u0|mm_interconnect_0|router_001|Equal6~0_combout  & ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & 
// (\u0|mm_interconnect_0|router_001|Equal2~0_combout  & (\u0|mm_interconnect_0|router_001|Equal1~0_combout  & \u0|mm_interconnect_0|router_001|Equal1~1_combout ))) ) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),
        .datab(!\u0|mm_interconnect_0|router_001|Equal2~0_combout ),
        .datac(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),
        .datad(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),
        .datae(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
        .dataf(!\u0|mm_interconnect_0|router_001|Equal6~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux_001|sink_ready~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~4 .lut_mask = 64'h0000000000000001;
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y23_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|sink_ready~3 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|sink_ready~3_combout  = ( \u0|mm_interconnect_0|router_001|Equal1~4_combout  & ( \u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & \u0|hps_0|fpga_interfaces|h2f_ARADDR 
// [17]) ) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|router_001|Equal1~4_combout ),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux_001|sink_ready~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~3 .lut_mask = 64'h0000000000001111;
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y23_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|WideOr0~2 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|WideOr0~2_combout  = ( \u0|mm_interconnect_0|cmd_demux_001|sink_ready~4_combout  & ( \u0|mm_interconnect_0|cmd_demux_001|sink_ready~3_combout  & ( 
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & 
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ))) ) ) 
// ) # ( !\u0|mm_interconnect_0|cmd_demux_001|sink_ready~4_combout  & ( \u0|mm_interconnect_0|cmd_demux_001|sink_ready~3_combout  & ( (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  
// & !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) ) ) ) # ( \u0|mm_interconnect_0|cmd_demux_001|sink_ready~4_combout  & ( !\u0|mm_interconnect_0|cmd_demux_001|sink_ready~3_combout 
//  & ( (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) ) ) 
// ) # ( !\u0|mm_interconnect_0|cmd_demux_001|sink_ready~4_combout  & ( !\u0|mm_interconnect_0|cmd_demux_001|sink_ready~3_combout  ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datae(!\u0|mm_interconnect_0|cmd_demux_001|sink_ready~4_combout ),
        .dataf(!\u0|mm_interconnect_0|cmd_demux_001|sink_ready~3_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux_001|WideOr0~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|WideOr0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|WideOr0~2 .lut_mask = 64'hFFFF8888F0008000;
defparam \u0|mm_interconnect_0|cmd_demux_001|WideOr0~2 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y23_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|sink_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|sink_ready~2_combout  = ( \u0|mm_interconnect_0|router_001|Equal21~0_combout  & ( \u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|router_001|Equal21~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux_001|sink_ready~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~2 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y27_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|sink_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|sink_ready~1_combout  = ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & ( \u0|mm_interconnect_0|router_001|Equal3~0_combout  & ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & \u0|hps_0|fpga_interfaces|h2f_ARADDR 
// [18]) ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),
        .datae(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
        .dataf(!\u0|mm_interconnect_0|router_001|Equal3~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux_001|sink_ready~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~1 .lut_mask = 64'h000000000000000F;
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y23_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|WideOr0~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|WideOr0~1_combout  = ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & ( \u0|mm_interconnect_0|cmd_demux_001|sink_ready~1_combout  & ( 
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  & ((!\u0|mm_interconnect_0|cmd_demux_001|sink_ready~2_combout ) # 
// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout )))) ) ) ) # ( 
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & ( !\u0|mm_interconnect_0|cmd_demux_001|sink_ready~1_combout  & ( (!\u0|mm_interconnect_0|cmd_demux_001|sink_ready~2_combout ) 
// # ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout )) ) ) ) # ( 
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & ( !\u0|mm_interconnect_0|cmd_demux_001|sink_ready~1_combout  & ( (!\u0|mm_interconnect_0|cmd_demux_001|sink_ready~2_combout ) 
// # ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & 
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout )) ) ) )

        .dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
        .datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_demux_001|sink_ready~2_combout ),
        .datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .dataf(!\u0|mm_interconnect_0|cmd_demux_001|sink_ready~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux_001|WideOr0~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|WideOr0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|WideOr0~1 .lut_mask = 64'hFFC0FFC0AA800000;
defparam \u0|mm_interconnect_0|cmd_demux_001|WideOr0~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y31_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|WideOr0~6 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|WideOr0~6_combout  = ( \u0|mm_interconnect_0|cmd_demux_001|WideOr0~2_combout  & ( \u0|mm_interconnect_0|cmd_demux_001|WideOr0~1_combout  & ( (\u0|mm_interconnect_0|cmd_demux_001|WideOr0~5_combout  & 
// (!\u0|mm_interconnect_0|cmd_demux_001|WideOr0~0_combout  & (!\u0|mm_interconnect_0|cmd_demux_001|WideOr0~4_combout  & \u0|mm_interconnect_0|cmd_demux_001|WideOr0~3_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_demux_001|WideOr0~5_combout ),
        .datab(!\u0|mm_interconnect_0|cmd_demux_001|WideOr0~0_combout ),
        .datac(!\u0|mm_interconnect_0|cmd_demux_001|WideOr0~4_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_demux_001|WideOr0~3_combout ),
        .datae(!\u0|mm_interconnect_0|cmd_demux_001|WideOr0~2_combout ),
        .dataf(!\u0|mm_interconnect_0|cmd_demux_001|WideOr0~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux_001|WideOr0~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|WideOr0~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|WideOr0~6 .lut_mask = 64'h0000000000000040;
defparam \u0|mm_interconnect_0|cmd_demux_001|WideOr0~6 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y31_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|sink_ready~13 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|sink_ready~13_combout  = ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  & ( (\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & 
// \u0|mm_interconnect_0|router_001|Equal10~0_combout ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
        .datad(!\u0|mm_interconnect_0|router_001|Equal10~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux_001|sink_ready~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~13 .lut_mask = 64'h000F000F00000000;
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y33_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|sink_ready~16 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|sink_ready~16_combout  = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( 
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & ( \u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] ) ) ) # ( 
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & ( 
// (\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] & (((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # 
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout )) # (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ))) ) ) ) 
// # ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & ( 
// (\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] & ((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ) # 
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout  & 
// ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & ( (\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] & 
// ((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ) # (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
        .datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
        .datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
        .datae(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
        .dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux_001|sink_ready~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~16 .lut_mask = 64'h07070707070F0F0F;
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~16 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y29_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|WideOr0~7 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|WideOr0~7_combout  = ( \u0|mm_interconnect_0|router_001|Equal4~0_combout  & ( \u0|mm_interconnect_0|cmd_demux_001|sink_ready~16_combout  ) ) # ( !\u0|mm_interconnect_0|router_001|Equal4~0_combout  & ( 
// \u0|mm_interconnect_0|cmd_demux_001|sink_ready~16_combout  & ( (\u0|mm_interconnect_0|router_001|Equal13~1_combout  & (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & 
// ((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ) # (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )))) ) ) 
// ) # ( \u0|mm_interconnect_0|router_001|Equal4~0_combout  & ( !\u0|mm_interconnect_0|cmd_demux_001|sink_ready~16_combout  & ( (\u0|mm_interconnect_0|router_001|Equal13~1_combout  & (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & 
// ((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ) # (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )))) ) ) 
// ) # ( !\u0|mm_interconnect_0|router_001|Equal4~0_combout  & ( !\u0|mm_interconnect_0|cmd_demux_001|sink_ready~16_combout  & ( (\u0|mm_interconnect_0|router_001|Equal13~1_combout  & (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & 
// ((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ) # (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )))) ) ) 
// )

        .dataa(!\u0|mm_interconnect_0|router_001|Equal13~1_combout ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
        .datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .datae(!\u0|mm_interconnect_0|router_001|Equal4~0_combout ),
        .dataf(!\u0|mm_interconnect_0|cmd_demux_001|sink_ready~16_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux_001|WideOr0~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|WideOr0~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|WideOr0~7 .lut_mask = 64'h011101110111FFFF;
defparam \u0|mm_interconnect_0|cmd_demux_001|WideOr0~7 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X22_Y27_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|sink_ready~15 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|sink_ready~15_combout  = ( \u0|mm_interconnect_0|router_001|Equal1~4_combout  & ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & ( 
// (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & \u0|mm_interconnect_0|cmd_mux_009|saved_grant [1])) ) ) ) # ( \u0|mm_interconnect_0|router_001|Equal1~4_combout  & ( 
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & 
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & \u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]))) ) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),
        .datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
        .datae(!\u0|mm_interconnect_0|router_001|Equal1~4_combout ),
        .dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux_001|sink_ready~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~15 .lut_mask = 64'h000000020000000A;
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~15 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X23_Y31_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|sink_ready~14 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|sink_ready~14_combout  = ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & ( 
// (\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & \u0|mm_interconnect_0|router_001|Equal3~0_combout )) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & ( 
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & ( 
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & 
// \u0|mm_interconnect_0|router_001|Equal3~0_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),
        .datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),
        .datad(!\u0|mm_interconnect_0|router_001|Equal3~0_combout ),
        .datae(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
        .dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux_001|sink_ready~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~14 .lut_mask = 64'h0000001000000030;
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~14 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y31_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|sink_ready~12 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|sink_ready~12_combout  = ( \u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] & ( (\u0|mm_interconnect_0|router_001|Equal2~2_combout  & 
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|router_001|Equal2~2_combout ),
        .datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux_001|sink_ready~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~12 .lut_mask = 64'h000000000F000F00;
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~12 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y31_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|sink_ready~17 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|sink_ready~17_combout  = ( \u0|mm_interconnect_0|router_001|Equal14~0_combout  & ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & ( (\u0|mm_interconnect_0|router_001|Equal1~2_combout  & 
// (\u0|mm_interconnect_0|router_001|Equal1~1_combout  & (\u0|mm_interconnect_0|router_001|Equal1~0_combout  & !\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]))) ) ) )

        .dataa(!\u0|mm_interconnect_0|router_001|Equal1~2_combout ),
        .datab(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),
        .datac(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),
        .datae(!\u0|mm_interconnect_0|router_001|Equal14~0_combout ),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux_001|sink_ready~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~17 .lut_mask = 64'h0000000000000100;
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~17 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y31_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|WideOr0~8 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|WideOr0~8_combout  = ( \u0|mm_interconnect_0|router_001|Equal12~0_combout  & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & ( 
// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  & \u0|mm_interconnect_0|cmd_mux_021|saved_grant [1])) # (\u0|mm_interconnect_0|cmd_demux_001|sink_ready~17_combout ) ) ) ) # ( 
// !\u0|mm_interconnect_0|router_001|Equal12~0_combout  & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & ( \u0|mm_interconnect_0|cmd_demux_001|sink_ready~17_combout  ) ) ) # ( 
// \u0|mm_interconnect_0|router_001|Equal12~0_combout  & ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & ( 
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  & (((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & 
// \u0|mm_interconnect_0|cmd_demux_001|sink_ready~17_combout )) # (\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]))) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout  & 
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & ((\u0|mm_interconnect_0|cmd_demux_001|sink_ready~17_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|router_001|Equal12~0_combout  & ( 
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout  & ( (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  & 
// \u0|mm_interconnect_0|cmd_demux_001|sink_ready~17_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
        .datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datac(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
        .datad(!\u0|mm_interconnect_0|cmd_demux_001|sink_ready~17_combout ),
        .datae(!\u0|mm_interconnect_0|router_001|Equal12~0_combout ),
        .dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux_001|WideOr0~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|WideOr0~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|WideOr0~8 .lut_mask = 64'h00330A3B00FF0AFF;
defparam \u0|mm_interconnect_0|cmd_demux_001|WideOr0~8 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y31_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|WideOr0~9 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|WideOr0~9_combout  = ( !\u0|mm_interconnect_0|cmd_demux_001|sink_ready~12_combout  & ( !\u0|mm_interconnect_0|cmd_demux_001|WideOr0~8_combout  & ( (!\u0|mm_interconnect_0|cmd_demux_001|sink_ready~13_combout  & 
// (!\u0|mm_interconnect_0|cmd_demux_001|WideOr0~7_combout  & (!\u0|mm_interconnect_0|cmd_demux_001|sink_ready~15_combout  & !\u0|mm_interconnect_0|cmd_demux_001|sink_ready~14_combout ))) ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_demux_001|sink_ready~13_combout ),
        .datab(!\u0|mm_interconnect_0|cmd_demux_001|WideOr0~7_combout ),
        .datac(!\u0|mm_interconnect_0|cmd_demux_001|sink_ready~15_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_demux_001|sink_ready~14_combout ),
        .datae(!\u0|mm_interconnect_0|cmd_demux_001|sink_ready~12_combout ),
        .dataf(!\u0|mm_interconnect_0|cmd_demux_001|WideOr0~8_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux_001|WideOr0~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|WideOr0~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|WideOr0~9 .lut_mask = 64'h8000000000000000;
defparam \u0|mm_interconnect_0|cmd_demux_001|WideOr0~9 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y31_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|response_sink_accepted (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|response_sink_accepted~combout  = ( \u0|mm_interconnect_0|rsp_mux_001|src_payload [0] & ( (\u0|mm_interconnect_0|rsp_mux_001|WideOr1~combout  & \u0|hps_0|fpga_interfaces|h2f_RREADY [0]) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|rsp_mux_001|WideOr1~combout ),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_payload [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|response_sink_accepted~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|response_sink_accepted .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|response_sink_accepted .lut_mask = 64'h00000000000F000F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|response_sink_accepted .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y31_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|next_pending_response_count~1 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|next_pending_response_count~1_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|response_sink_accepted~combout  & ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count [0] ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|response_sink_accepted~combout  & ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count [0] $ (((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ) # ((\u0|mm_interconnect_0|cmd_demux_001|WideOr0~9_combout  & 
// \u0|mm_interconnect_0|cmd_demux_001|WideOr0~6_combout )))) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),
        .datab(!\u0|mm_interconnect_0|cmd_demux_001|WideOr0~9_combout ),
        .datac(!\u0|mm_interconnect_0|cmd_demux_001|WideOr0~6_combout ),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|response_sink_accepted~combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|next_pending_response_count~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|next_pending_response_count~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|next_pending_response_count~1 .lut_mask = 64'h54AB54ABFF00FF00;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|next_pending_response_count~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y31_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|always1~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|always1~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout  & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|response_sink_accepted~combout ) # 
// ((\u0|mm_interconnect_0|cmd_demux_001|WideOr0~9_combout  & \u0|mm_interconnect_0|cmd_demux_001|WideOr0~6_combout )) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout  )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|response_sink_accepted~combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_demux_001|WideOr0~9_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_demux_001|WideOr0~6_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|always1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|always1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|always1~0 .lut_mask = 64'hFFFFFFFFAAAFAAAF;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|always1~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y31_N32
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|next_pending_response_count~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|always1~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count[0] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y31_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|next_pending_response_count~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|next_pending_response_count~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count [1] & ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout  & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|response_sink_accepted~combout  & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count 
// [0]) # ((\u0|mm_interconnect_0|cmd_demux_001|WideOr0~9_combout  & \u0|mm_interconnect_0|cmd_demux_001|WideOr0~6_combout )))) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|response_sink_accepted~combout  & 
// (((\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count [0])))) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count [1] & ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout  & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|response_sink_accepted~combout  & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count [0] 
// & ((!\u0|mm_interconnect_0|cmd_demux_001|WideOr0~9_combout ) # (!\u0|mm_interconnect_0|cmd_demux_001|WideOr0~6_combout )))) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|response_sink_accepted~combout  & 
// (((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count [0])))) ) ) ) # ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count [1] & ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout  & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|response_sink_accepted~combout ) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count 
// [0]) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count [1] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout  & ( 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|response_sink_accepted~combout  & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count [0]) ) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|response_sink_accepted~combout ),
        .datab(!\u0|mm_interconnect_0|cmd_demux_001|WideOr0~9_combout ),
        .datac(!\u0|mm_interconnect_0|cmd_demux_001|WideOr0~6_combout ),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count [0]),
        .datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count [1]),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|next_pending_response_count~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|next_pending_response_count~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|next_pending_response_count~0 .lut_mask = 64'h5500AAFF55A8AA57;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|next_pending_response_count~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y31_N8
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|next_pending_response_count~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|always1~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count[1] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X25_Y31_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~0_combout  = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count [1] & ( (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & 
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count [0] & (\u0|mm_interconnect_0|rsp_mux_001|WideOr1~combout  & \u0|mm_interconnect_0|rsp_mux_001|src_payload [0]))) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count [0]),
        .datac(!\u0|mm_interconnect_0|rsp_mux_001|WideOr1~combout ),
        .datad(!\u0|mm_interconnect_0|rsp_mux_001|src_payload [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~0 .lut_mask = 64'h0001000100000000;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y31_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~1 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~1_combout  = ( \u0|mm_interconnect_0|rsp_mux_001|src_payload [0] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count [0] & 
// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count [1] & ((!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]) # (!\u0|mm_interconnect_0|rsp_mux_001|WideOr1~combout )))) ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_payload [0] & ( 
// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count [1]) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count [0]),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count [1]),
        .datad(!\u0|mm_interconnect_0|rsp_mux_001|WideOr1~combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_payload [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~1 .lut_mask = 64'hC0C0C0C0C080C080;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y31_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~2 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~2_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q  & ( 
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~1_combout  & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~0_combout ) # 
// ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout  & ((!\u0|mm_interconnect_0|cmd_demux_001|WideOr0~6_combout ) # (!\u0|mm_interconnect_0|cmd_demux_001|WideOr0~9_combout )))) ) ) ) # ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q  & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~1_combout  & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout  
// & ((!\u0|mm_interconnect_0|cmd_demux_001|WideOr0~6_combout ) # (!\u0|mm_interconnect_0|cmd_demux_001|WideOr0~9_combout ))) ) ) ) # ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q  & ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~1_combout  & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~0_combout ) # 
// ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout  & ((!\u0|mm_interconnect_0|cmd_demux_001|WideOr0~6_combout ) # (!\u0|mm_interconnect_0|cmd_demux_001|WideOr0~9_combout )))) ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_demux_001|WideOr0~6_combout ),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),
        .datac(!\u0|mm_interconnect_0|cmd_demux_001|WideOr0~9_combout ),
        .datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~0_combout ),
        .datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~2 .lut_mask = 64'h0000FF323232FF32;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X25_Y31_N50
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~2_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y30_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~2 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~2_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~1_combout  & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~0_combout  & 
// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id [2] $ (\u0|mm_interconnect_0|router_001|src_data[102]~0_combout ))) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~0_combout ),
        .datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id [2]),
        .datad(!\u0|mm_interconnect_0|router_001|src_data[102]~0_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~2 .lut_mask = 64'h0000000030033003;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~2 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X25_Y31_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|cmd_sink_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|cmd_sink_ready~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~2_combout  & ( (!\u0|mm_interconnect_0|cmd_demux_001|WideOr0~9_combout ) # 
// (!\u0|mm_interconnect_0|cmd_demux_001|WideOr0~6_combout ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~2_combout  & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q  & 
// ((!\u0|mm_interconnect_0|cmd_demux_001|WideOr0~9_combout ) # (!\u0|mm_interconnect_0|cmd_demux_001|WideOr0~6_combout ))) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_demux_001|WideOr0~9_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_demux_001|WideOr0~6_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~2_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|cmd_sink_ready~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|cmd_sink_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|cmd_sink_ready~0 .lut_mask = 64'hAAA0AAA0FFF0FFF0;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|cmd_sink_ready~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y31_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal6~1 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal6~1_combout  = ( \u0|mm_interconnect_0|router_001|Equal1~1_combout  & ( (\u0|mm_interconnect_0|router_001|Equal6~0_combout  & (\u0|mm_interconnect_0|router_001|Equal1~0_combout  & 
// (\u0|mm_interconnect_0|router_001|Equal2~0_combout  & \u0|hps_0|fpga_interfaces|h2f_ARADDR [16]))) ) )

        .dataa(!\u0|mm_interconnect_0|router_001|Equal6~0_combout ),
        .datab(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),
        .datac(!\u0|mm_interconnect_0|router_001|Equal2~0_combout ),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|router_001|Equal6~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal6~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal6~1 .lut_mask = 64'h0000000000010001;
defparam \u0|mm_interconnect_0|router_001|Equal6~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y31_N20
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[18] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(gnd),
        .asdata(\u0|mm_interconnect_0|router_001|Equal6~1_combout ),
        .clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [18]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[18] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[18] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y31_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|src18_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|src18_valid~0_combout  = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [18] & ( \u0|hps_0|fpga_interfaces|h2f_ARVALID [0] ) ) # ( 
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [18] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q  & \u0|hps_0|fpga_interfaces|h2f_ARVALID [0]) ) )

        .dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [18]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux_001|src18_valid~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|src18_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|src18_valid~0 .lut_mask = 64'h00AA00AA00FF00FF;
defparam \u0|mm_interconnect_0|cmd_demux_001|src18_valid~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y31_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|src18_valid~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|src18_valid~1_combout  = ( \u0|mm_interconnect_0|cmd_demux_001|src18_valid~0_combout  & ( \u0|mm_interconnect_0|router_001|Equal6~0_combout  & ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & 
// (\u0|mm_interconnect_0|router_001|Equal2~0_combout  & (\u0|mm_interconnect_0|router_001|Equal1~1_combout  & \u0|mm_interconnect_0|router_001|Equal1~0_combout ))) ) ) )

        .dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),
        .datab(!\u0|mm_interconnect_0|router_001|Equal2~0_combout ),
        .datac(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),
        .datad(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),
        .datae(!\u0|mm_interconnect_0|cmd_demux_001|src18_valid~0_combout ),
        .dataf(!\u0|mm_interconnect_0|router_001|Equal6~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux_001|src18_valid~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|src18_valid~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|src18_valid~1 .lut_mask = 64'h0000000000000001;
defparam \u0|mm_interconnect_0|cmd_demux_001|src18_valid~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y23_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|src18_valid~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|src18_valid~1_combout  = ( \u0|mm_interconnect_0|cmd_demux|src18_valid~0_combout  & ( (\u0|mm_interconnect_0|router|Equal6~6_combout  & \u0|mm_interconnect_0|router|Equal6~8_combout ) ) )

        .dataa(!\u0|mm_interconnect_0|router|Equal6~6_combout ),
        .datab(!\u0|mm_interconnect_0|router|Equal6~8_combout ),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_demux|src18_valid~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_demux|src18_valid~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|src18_valid~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|src18_valid~1 .lut_mask = 64'h0000000011111111;
defparam \u0|mm_interconnect_0|cmd_demux|src18_valid~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y22_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg [1] & ( \u0|mm_interconnect_0|cmd_demux|src18_valid~1_combout  & ( (!\u0|mm_interconnect_0|cmd_demux_001|src18_valid~1_combout ) # 
// ((!\u0|mm_interconnect_0|cmd_mux_018|update_grant~0_combout ) # (!\u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg [0])) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg [1] & ( \u0|mm_interconnect_0|cmd_demux|src18_valid~1_combout  
// & ( (\u0|mm_interconnect_0|cmd_mux_018|update_grant~0_combout  & !\u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg [0]) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg [1] & ( !\u0|mm_interconnect_0|cmd_demux|src18_valid~1_combout  
// & ( (!\u0|mm_interconnect_0|cmd_demux_001|src18_valid~1_combout ) # (!\u0|mm_interconnect_0|cmd_mux_018|update_grant~0_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_demux_001|src18_valid~1_combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_018|update_grant~0_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg [0]),
        .datae(!\u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg [1]),
        .dataf(!\u0|mm_interconnect_0|cmd_demux|src18_valid~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg~0 .lut_mask = 64'h0000FAFA0F00FFFA;
defparam \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y22_N17
dffeas \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y22_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|arb|grant[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|arb|grant[1]~0_combout  = ( \u0|mm_interconnect_0|cmd_demux_001|src18_valid~1_combout  & ( \u0|mm_interconnect_0|cmd_demux|src18_valid~1_combout  & ( \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg [1] ) ) ) # ( 
// \u0|mm_interconnect_0|cmd_demux_001|src18_valid~1_combout  & ( !\u0|mm_interconnect_0|cmd_demux|src18_valid~1_combout  & ( (!\u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg [0]) # (\u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg [1]) ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg [0]),
        .datad(!\u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg [1]),
        .datae(!\u0|mm_interconnect_0|cmd_demux_001|src18_valid~1_combout ),
        .dataf(!\u0|mm_interconnect_0|cmd_demux|src18_valid~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_018|arb|grant[1]~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|arb|grant[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|arb|grant[1]~0 .lut_mask = 64'h0000F0FF000000FF;
defparam \u0|mm_interconnect_0|cmd_mux_018|arb|grant[1]~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y22_N32
dffeas \u0|mm_interconnect_0|cmd_mux_018|saved_grant[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_018|arb|grant[1]~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|cmd_mux_018|update_grant~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|saved_grant[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_018|saved_grant[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y20_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_data[32] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|src_data [32] = ( \u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & ( (\u0|hps_0|fpga_interfaces|h2f_WSTRB [0]) # (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]) ) ) # ( 
// !\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & ( \u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
        .datad(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [0]),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_018|src_data [32]),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[32] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[32] .lut_mask = 64'h0F0F0F0F0FFF0FFF;
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[32] .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y20_N41
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_018|src_data [32]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y20_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent|WideOr0~0_combout  = ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q  & ( 
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & 
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & 
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]))) ) ) ) # ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q  & ( 
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & 
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & 
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]))) ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q  & ( 
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q  & ( (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & 
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & 
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]))) ) ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
        .datae(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_agent|WideOr0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|WideOr0~0 .lut_mask = 64'h8000800080000000;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|WideOr0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y20_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  = ( \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~0_combout  & ( 
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & ( (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ((!\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter 
// [0] $ (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68])) # (\u0|mm_interconnect_0|clock_sel_s1_agent|WideOr0~0_combout ))) ) ) ) # ( 
// !\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~0_combout  & ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  & ( (\u0|mm_interconnect_0|clock_sel_s1_agent|WideOr0~0_combout  & 
// !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # ( \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~0_combout  & ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  ) 
// ) # ( !\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~0_combout  & ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q  ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent|WideOr0~0_combout ),
        .datab(!\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [0]),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
        .datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),
        .datae(!\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~0_combout ),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hFFFFFFFF55007D00;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y21_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( 
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  
// & !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  
// & ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  & ( 
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ) ) # 
// ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q  & ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q  
// & ( (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout  & !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ) 
// )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'h0000505050505050;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X28_Y23_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|packet_in_progress~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|packet_in_progress~0_combout  = !\u0|mm_interconnect_0|cmd_mux_018|update_grant~0_combout 

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(!\u0|mm_interconnect_0|cmd_mux_018|update_grant~0_combout ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_018|packet_in_progress~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|packet_in_progress~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|packet_in_progress~0 .lut_mask = 64'hFF00FF00FF00FF00;
defparam \u0|mm_interconnect_0|cmd_mux_018|packet_in_progress~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X28_Y23_N47
dffeas \u0|mm_interconnect_0|cmd_mux_018|packet_in_progress (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_018|packet_in_progress~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_018|packet_in_progress~q ),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|packet_in_progress .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_018|packet_in_progress .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X28_Y23_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|update_grant~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|update_grant~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_018|src_payload [0] & ( \u0|mm_interconnect_0|cmd_mux_018|src_valid~0_combout  & ( 
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ) # (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) ) ) ) # ( 
// \u0|mm_interconnect_0|cmd_mux_018|src_payload [0] & ( !\u0|mm_interconnect_0|cmd_mux_018|src_valid~0_combout  & ( (!\u0|mm_interconnect_0|cmd_mux_018|src_valid~1_combout  & (((!\u0|mm_interconnect_0|cmd_mux_018|packet_in_progress~q )))) # 
// (\u0|mm_interconnect_0|cmd_mux_018|src_valid~1_combout  & (((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout )) # 
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_018|src_payload [0] & ( !\u0|mm_interconnect_0|cmd_mux_018|src_valid~0_combout  & ( 
// (!\u0|mm_interconnect_0|cmd_mux_018|packet_in_progress~q  & !\u0|mm_interconnect_0|cmd_mux_018|src_valid~1_combout ) ) ) )

        .dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
        .datab(!\u0|mm_interconnect_0|cmd_mux_018|packet_in_progress~q ),
        .datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_018|src_valid~1_combout ),
        .datae(!\u0|mm_interconnect_0|cmd_mux_018|src_payload [0]),
        .dataf(!\u0|mm_interconnect_0|cmd_mux_018|src_valid~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_018|update_grant~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|update_grant~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|update_grant~0 .lut_mask = 64'hCC00CC5F00005F5F;
defparam \u0|mm_interconnect_0|cmd_mux_018|update_grant~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X27_Y22_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg~1_combout  = ( \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg [0] & ( \u0|mm_interconnect_0|cmd_demux|src18_valid~1_combout  & ( (!\u0|mm_interconnect_0|cmd_mux_018|update_grant~0_combout ) # 
// ((!\u0|mm_interconnect_0|cmd_demux_001|src18_valid~1_combout ) # (!\u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg [1])) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg [0] & ( \u0|mm_interconnect_0|cmd_demux|src18_valid~1_combout 
//  & ( (\u0|mm_interconnect_0|cmd_mux_018|update_grant~0_combout  & ((!\u0|mm_interconnect_0|cmd_demux_001|src18_valid~1_combout ) # (!\u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg [1]))) ) ) ) # ( 
// \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg [0] & ( !\u0|mm_interconnect_0|cmd_demux|src18_valid~1_combout  & ( (!\u0|mm_interconnect_0|cmd_mux_018|update_grant~0_combout ) # ((!\u0|mm_interconnect_0|cmd_demux_001|src18_valid~1_combout ) # 
// (!\u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg [1])) ) ) )

        .dataa(gnd),
        .datab(!\u0|mm_interconnect_0|cmd_mux_018|update_grant~0_combout ),
        .datac(!\u0|mm_interconnect_0|cmd_demux_001|src18_valid~1_combout ),
        .datad(!\u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg [1]),
        .datae(!\u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg [0]),
        .dataf(!\u0|mm_interconnect_0|cmd_demux|src18_valid~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg~1 .lut_mask = 64'h0000FFFC3330FFFC;
defparam \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y22_N20
dffeas \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X27_Y22_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|arb|grant[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|arb|grant[0]~1_combout  = ( \u0|mm_interconnect_0|cmd_demux|src18_valid~1_combout  & ( (!\u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg [0]) # ((\u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg [1] & 
// !\u0|mm_interconnect_0|cmd_demux_001|src18_valid~1_combout )) ) )

        .dataa(!\u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg [0]),
        .datab(gnd),
        .datac(!\u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg [1]),
        .datad(!\u0|mm_interconnect_0|cmd_demux_001|src18_valid~1_combout ),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|cmd_demux|src18_valid~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_018|arb|grant[0]~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|arb|grant[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|arb|grant[0]~1 .lut_mask = 64'h00000000AFAAAFAA;
defparam \u0|mm_interconnect_0|cmd_mux_018|arb|grant[0]~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X27_Y22_N53
dffeas \u0|mm_interconnect_0|cmd_mux_018|saved_grant[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_018|arb|grant[0]~1_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|cmd_mux_018|update_grant~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|saved_grant[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_018|saved_grant[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X30_Y17_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_payload~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|src_payload~0_combout  = ( \u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_WDATA [0] ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
        .dataf(!\u0|hps_0|fpga_interfaces|h2f_WDATA [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|mm_interconnect_0|cmd_mux_018|src_payload~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|src_payload~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|src_payload~0 .lut_mask = 64'h000000000000FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_018|src_payload~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X30_Y17_N26
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|cmd_mux_018|src_payload~0_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X59_Y13_N6
cyclonev_lcell_comb \u0|clock_sel|data_out[0]~feeder (
// Equation(s):
// \u0|clock_sel|data_out[0]~feeder_combout  = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [0] )

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\u0|clock_sel|data_out[0]~feeder_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \u0|clock_sel|data_out[0]~feeder .extended_lut = "off";
defparam \u0|clock_sel|data_out[0]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|clock_sel|data_out[0]~feeder .shared_arith = "off";
// synopsys translate_on

// Location: FF_X59_Y13_N8
dffeas \u0|clock_sel|data_out[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|clock_sel|data_out[0]~feeder_combout ),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|clock_sel|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|clock_sel|data_out [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|clock_sel|data_out[0] .is_wysiwyg = "true";
defparam \u0|clock_sel|data_out[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X65_Y4_N0
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add0~41 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Add0~41_sumout  = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter [0] ) + ( VCC ) + ( !VCC ))
// \R_400_to_2_5_10_100_200_300MHZ|Add0~42  = CARRY(( \R_400_to_2_5_10_100_200_300MHZ|counter [0] ) + ( VCC ) + ( !VCC ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [0]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(),
        .sumout(\R_400_to_2_5_10_100_200_300MHZ|Add0~41_sumout ),
        .cout(\R_400_to_2_5_10_100_200_300MHZ|Add0~42 ),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~41 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~41 .lut_mask = 64'h0000000000000F0F;
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~41 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X65_Y4_N3
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add0~33 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Add0~33_sumout  = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter [1] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add0~42  ))
// \R_400_to_2_5_10_100_200_300MHZ|Add0~34  = CARRY(( \R_400_to_2_5_10_100_200_300MHZ|counter [1] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add0~42  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [1]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\R_400_to_2_5_10_100_200_300MHZ|Add0~42 ),
        .sharein(gnd),
        .combout(),
        .sumout(\R_400_to_2_5_10_100_200_300MHZ|Add0~33_sumout ),
        .cout(\R_400_to_2_5_10_100_200_300MHZ|Add0~34 ),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~33 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~33 .lut_mask = 64'h0000FFFF00000F0F;
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~33 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X65_Y4_N6
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add0~37 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Add0~37_sumout  = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter [2] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add0~34  ))
// \R_400_to_2_5_10_100_200_300MHZ|Add0~38  = CARRY(( \R_400_to_2_5_10_100_200_300MHZ|counter [2] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add0~34  ))

        .dataa(gnd),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\R_400_to_2_5_10_100_200_300MHZ|Add0~34 ),
        .sharein(gnd),
        .combout(),
        .sumout(\R_400_to_2_5_10_100_200_300MHZ|Add0~37_sumout ),
        .cout(\R_400_to_2_5_10_100_200_300MHZ|Add0~38 ),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~37 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~37 .lut_mask = 64'h0000FFFF00003333;
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~37 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X65_Y4_N9
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add0~25 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Add0~25_sumout  = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter [3] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add0~38  ))
// \R_400_to_2_5_10_100_200_300MHZ|Add0~26  = CARRY(( \R_400_to_2_5_10_100_200_300MHZ|counter [3] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add0~38  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [3]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\R_400_to_2_5_10_100_200_300MHZ|Add0~38 ),
        .sharein(gnd),
        .combout(),
        .sumout(\R_400_to_2_5_10_100_200_300MHZ|Add0~25_sumout ),
        .cout(\R_400_to_2_5_10_100_200_300MHZ|Add0~26 ),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~25 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~25 .lut_mask = 64'h0000FFFF00000F0F;
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~25 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X65_Y4_N12
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add0~29 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Add0~29_sumout  = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter [4] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add0~26  ))
// \R_400_to_2_5_10_100_200_300MHZ|Add0~30  = CARRY(( \R_400_to_2_5_10_100_200_300MHZ|counter [4] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add0~26  ))

        .dataa(gnd),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter [4]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\R_400_to_2_5_10_100_200_300MHZ|Add0~26 ),
        .sharein(gnd),
        .combout(),
        .sumout(\R_400_to_2_5_10_100_200_300MHZ|Add0~29_sumout ),
        .cout(\R_400_to_2_5_10_100_200_300MHZ|Add0~30 ),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~29 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~29 .lut_mask = 64'h0000FFFF00003333;
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~29 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X61_Y3_N21
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~41 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~41_combout  = ( !\R_400_to_2_5_10_100_200_300MHZ|counter [2] & ( (\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & (\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout  & 
// \R_400_to_2_5_10_100_200_300MHZ|Add0~29_sumout )) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .datac(gnd),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|Add0~29_sumout ),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~41_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~41 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~41 .lut_mask = 64'h0011001100000000;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~41 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X61_Y3_N24
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~44 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~44_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|Add0~29_sumout  & ( \R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout  & ( (\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & 
// (!\R_400_to_2_5_10_100_200_300MHZ|counter [2] & ((!\R_400_to_2_5_10_100_200_300MHZ|counter [1]) # (!\R_400_to_2_5_10_100_200_300MHZ|counter [0])))) ) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter [1]),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter [0]),
        .datae(!\R_400_to_2_5_10_100_200_300MHZ|Add0~29_sumout ),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~44_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~44 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~44 .lut_mask = 64'h0000000000005040;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~44 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X61_Y3_N6
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~42 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~42_combout  = ( !\R_400_to_2_5_10_100_200_300MHZ|counter [1] & ( (\R_400_to_2_5_10_100_200_300MHZ|Add0~29_sumout  & (\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout  & 
// (\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & !\R_400_to_2_5_10_100_200_300MHZ|counter [2]))) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|Add0~29_sumout ),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~42_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~42 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~42 .lut_mask = 64'h0100010000000000;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~42 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X61_Y3_N0
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~88 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~88_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|counter [5] & ( (\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & (!\R_400_to_2_5_10_100_200_300MHZ|counter [3] & (\R_400_to_2_5_10_100_200_300MHZ|Add0~29_sumout  
// & !\R_400_to_2_5_10_100_200_300MHZ|counter [4]))) ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|counter [5] & ( (\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & \R_400_to_2_5_10_100_200_300MHZ|Add0~29_sumout ) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter [3]),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|Add0~29_sumout ),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter [4]),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~88_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~88 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~88 .lut_mask = 64'h0505050504000400;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~88 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X65_Y4_N15
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add0~21 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Add0~21_sumout  = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter [5] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add0~30  ))
// \R_400_to_2_5_10_100_200_300MHZ|Add0~22  = CARRY(( \R_400_to_2_5_10_100_200_300MHZ|counter [5] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add0~30  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [5]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\R_400_to_2_5_10_100_200_300MHZ|Add0~30 ),
        .sharein(gnd),
        .combout(),
        .sumout(\R_400_to_2_5_10_100_200_300MHZ|Add0~21_sumout ),
        .cout(\R_400_to_2_5_10_100_200_300MHZ|Add0~22 ),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~21 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~21 .lut_mask = 64'h0000FFFF00000F0F;
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~21 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X65_Y4_N18
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add0~1 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Add0~1_sumout  = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter [6] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add0~22  ))
// \R_400_to_2_5_10_100_200_300MHZ|Add0~2  = CARRY(( \R_400_to_2_5_10_100_200_300MHZ|counter [6] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add0~22  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [6]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\R_400_to_2_5_10_100_200_300MHZ|Add0~22 ),
        .sharein(gnd),
        .combout(),
        .sumout(\R_400_to_2_5_10_100_200_300MHZ|Add0~1_sumout ),
        .cout(\R_400_to_2_5_10_100_200_300MHZ|Add0~2 ),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~1 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~1 .lut_mask = 64'h0000FFFF00000F0F;
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~1 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X60_Y3_N6
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~13 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~13_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|Add0~1_sumout  & ( (!\R_400_to_2_5_10_100_200_300MHZ|counter [2] & (\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & 
// \R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout )) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add0~1_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~13_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~13 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~13 .lut_mask = 64'h0000000002020202;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X61_Y3_N27
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~16 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~16_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|Add0~1_sumout  & ( \R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout  & ( (\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & 
// (!\R_400_to_2_5_10_100_200_300MHZ|counter [2] & ((!\R_400_to_2_5_10_100_200_300MHZ|counter [1]) # (!\R_400_to_2_5_10_100_200_300MHZ|counter [0])))) ) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter [1]),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [0]),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
        .datae(!\R_400_to_2_5_10_100_200_300MHZ|Add0~1_sumout ),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~16_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~16 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~16 .lut_mask = 64'h0000000000005400;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~16 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X60_Y3_N15
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~14 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~14_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|Add0~1_sumout  & ( (\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout  & (\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & 
// (!\R_400_to_2_5_10_100_200_300MHZ|counter [1] & !\R_400_to_2_5_10_100_200_300MHZ|counter [2]))) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [1]),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add0~1_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~14_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~14 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~14 .lut_mask = 64'h0000000010001000;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~14 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X65_Y4_N21
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add0~5 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Add0~5_sumout  = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter [7] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add0~2  ))
// \R_400_to_2_5_10_100_200_300MHZ|Add0~6  = CARRY(( \R_400_to_2_5_10_100_200_300MHZ|counter [7] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add0~2  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [7]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\R_400_to_2_5_10_100_200_300MHZ|Add0~2 ),
        .sharein(gnd),
        .combout(),
        .sumout(\R_400_to_2_5_10_100_200_300MHZ|Add0~5_sumout ),
        .cout(\R_400_to_2_5_10_100_200_300MHZ|Add0~6 ),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~5 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~5 .lut_mask = 64'h0000FFFF00000F0F;
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X64_Y3_N39
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~18 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~18_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout  & ( (!\R_400_to_2_5_10_100_200_300MHZ|counter [1] & (\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & 
// (\R_400_to_2_5_10_100_200_300MHZ|Add0~5_sumout  & !\R_400_to_2_5_10_100_200_300MHZ|counter [2]))) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter [1]),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|Add0~5_sumout ),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~18_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~18 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~18 .lut_mask = 64'h0000000002000200;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~18 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X64_Y3_N48
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~20 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~20_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|Add0~5_sumout  & ( \R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout  & ( (!\R_400_to_2_5_10_100_200_300MHZ|counter [2] & 
// (\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & ((!\R_400_to_2_5_10_100_200_300MHZ|counter [1]) # (!\R_400_to_2_5_10_100_200_300MHZ|counter [0])))) ) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter [1]),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter [0]),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datae(!\R_400_to_2_5_10_100_200_300MHZ|Add0~5_sumout ),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~20_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~20 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~20 .lut_mask = 64'h00000000000000E0;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~20 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X65_Y3_N48
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~17 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~17_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|Add0~5_sumout  & ( \R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & ( (\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout  & 
// !\R_400_to_2_5_10_100_200_300MHZ|counter [2]) ) ) )

        .dataa(gnd),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
        .datad(gnd),
        .datae(!\R_400_to_2_5_10_100_200_300MHZ|Add0~5_sumout ),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~17_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~17 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~17 .lut_mask = 64'h0000000000003030;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~17 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X65_Y3_N0
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~64 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~64_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|Add0~5_sumout  & ( \R_400_to_2_5_10_100_200_300MHZ|counter [4] & ( (\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & !\R_400_to_2_5_10_100_200_300MHZ|counter [5]) 
// ) ) ) # ( \R_400_to_2_5_10_100_200_300MHZ|Add0~5_sumout  & ( !\R_400_to_2_5_10_100_200_300MHZ|counter [4] & ( (\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & ((!\R_400_to_2_5_10_100_200_300MHZ|counter [3]) # (!\R_400_to_2_5_10_100_200_300MHZ|counter 
// [5]))) ) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter [3]),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datac(gnd),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter [5]),
        .datae(!\R_400_to_2_5_10_100_200_300MHZ|Add0~5_sumout ),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~64_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~64 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~64 .lut_mask = 64'h0000332200003300;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~64 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X63_Y4_N9
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~61 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~61_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|counter [6] & ( (!\R_400_to_2_5_10_100_200_300MHZ|counter [4] & (!\R_400_to_2_5_10_100_200_300MHZ|counter [5] & (\R_400_to_2_5_10_100_200_300MHZ|Add0~5_sumout  & 
// \R_400_to_2_5_10_100_200_300MHZ|counter~12_combout ))) ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|counter [6] & ( (\R_400_to_2_5_10_100_200_300MHZ|Add0~5_sumout  & \R_400_to_2_5_10_100_200_300MHZ|counter~12_combout ) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter [4]),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter [5]),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|Add0~5_sumout ),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter~12_combout ),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter [6]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~61_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~61 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~61 .lut_mask = 64'h000F000F00080008;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~61 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X63_Y3_N24
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~62 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~62_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|Add0~5_sumout  & ( (\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout  & \R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add0~5_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~62_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~62 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~62 .lut_mask = 64'h0000000011111111;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~62 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X65_Y4_N24
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add0~13 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Add0~13_sumout  = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter [8] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add0~6  ))
// \R_400_to_2_5_10_100_200_300MHZ|Add0~14  = CARRY(( \R_400_to_2_5_10_100_200_300MHZ|counter [8] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add0~6  ))

        .dataa(gnd),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter [8]),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\R_400_to_2_5_10_100_200_300MHZ|Add0~6 ),
        .sharein(gnd),
        .combout(),
        .sumout(\R_400_to_2_5_10_100_200_300MHZ|Add0~13_sumout ),
        .cout(\R_400_to_2_5_10_100_200_300MHZ|Add0~14 ),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~13 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~13 .lut_mask = 64'h0000FFFF00003333;
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~13 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X64_Y3_N18
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~26 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~26_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|Add0~13_sumout  & ( \R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & ( (!\R_400_to_2_5_10_100_200_300MHZ|counter [2] & 
// (\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout  & !\R_400_to_2_5_10_100_200_300MHZ|counter [1])) ) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [1]),
        .datad(gnd),
        .datae(!\R_400_to_2_5_10_100_200_300MHZ|Add0~13_sumout ),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~26_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~26 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~26 .lut_mask = 64'h0000000000002020;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~26 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X64_Y3_N51
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~28 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~28_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|Add0~13_sumout  & ( \R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout  & ( (\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & 
// (!\R_400_to_2_5_10_100_200_300MHZ|counter [2] & ((!\R_400_to_2_5_10_100_200_300MHZ|counter [1]) # (!\R_400_to_2_5_10_100_200_300MHZ|counter [0])))) ) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter [1]),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter [0]),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
        .datae(!\R_400_to_2_5_10_100_200_300MHZ|Add0~13_sumout ),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~28_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~28 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~28 .lut_mask = 64'h0000000000000E00;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~28 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X65_Y3_N18
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~25 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~25_combout  = ( !\R_400_to_2_5_10_100_200_300MHZ|counter [2] & ( \R_400_to_2_5_10_100_200_300MHZ|Add0~13_sumout  & ( (\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & 
// \R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ) ) ) )

        .dataa(gnd),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datac(gnd),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .datae(!\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add0~13_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~25_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~25 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~25 .lut_mask = 64'h0000000000330000;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~25 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X63_Y4_N6
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~69 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~69_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|Add0~13_sumout  & ( (\R_400_to_2_5_10_100_200_300MHZ|counter~12_combout  & ((!\R_400_to_2_5_10_100_200_300MHZ|counter [6]) # ((!\R_400_to_2_5_10_100_200_300MHZ|counter 
// [4] & !\R_400_to_2_5_10_100_200_300MHZ|counter [5])))) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter [4]),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter [5]),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [6]),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter~12_combout ),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add0~13_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~69_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~69 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~69 .lut_mask = 64'h0000000000F800F8;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~69 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X63_Y4_N27
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~72 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~72_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|Add0~13_sumout  & ( (\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & ((!\R_400_to_2_5_10_100_200_300MHZ|counter [5]) # ((!\R_400_to_2_5_10_100_200_300MHZ|counter 
// [4] & !\R_400_to_2_5_10_100_200_300MHZ|counter [3])))) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter [4]),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter [5]),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [3]),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add0~13_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~72_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~72 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~72 .lut_mask = 64'h0000000000EC00EC;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~72 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X64_Y4_N24
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~70 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~70_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout  & ( (\R_400_to_2_5_10_100_200_300MHZ|Add0~13_sumout  & \R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ) ) )

        .dataa(gnd),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|Add0~13_sumout ),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~70_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~70 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~70 .lut_mask = 64'h0000000003030303;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~70 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X64_Y4_N27
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~71 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~71_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|counter [7] & ( (\R_400_to_2_5_10_100_200_300MHZ|Add0~13_sumout  & (\R_400_to_2_5_10_100_200_300MHZ|always4~0_combout  & ((!\R_400_to_2_5_10_100_200_300MHZ|counter 
// [6]) # (\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout )))) ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|counter [7] & ( (\R_400_to_2_5_10_100_200_300MHZ|Add0~13_sumout  & \R_400_to_2_5_10_100_200_300MHZ|always4~0_combout ) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|Add0~13_sumout ),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [6]),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|always4~0_combout ),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter [7]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~71_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~71 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~71 .lut_mask = 64'h0033003300310031;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~71 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X64_Y4_N0
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Mux3~4 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Mux3~4_combout  = ( !\u0|clock_sel|data_out [1] & ( (!\u0|clock_sel|data_out [0] & (((\R_400_to_2_5_10_100_200_300MHZ|counter~71_combout  & (!\u0|clock_sel|data_out [2]))))) # (\u0|clock_sel|data_out [0] & 
// ((((\u0|clock_sel|data_out [2]))) # (\R_400_to_2_5_10_100_200_300MHZ|counter~69_combout ))) ) ) # ( \u0|clock_sel|data_out [1] & ( ((!\u0|clock_sel|data_out [0] & (\R_400_to_2_5_10_100_200_300MHZ|counter~72_combout  & (!\u0|clock_sel|data_out [2]))) # 
// (\u0|clock_sel|data_out [0] & (((\R_400_to_2_5_10_100_200_300MHZ|counter~70_combout ) # (\u0|clock_sel|data_out [2]))))) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter~69_combout ),
        .datab(!\u0|clock_sel|data_out [0]),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter~72_combout ),
        .datad(!\u0|clock_sel|data_out [2]),
        .datae(!\u0|clock_sel|data_out [1]),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter~70_combout ),
        .datag(!\R_400_to_2_5_10_100_200_300MHZ|counter~71_combout ),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|Mux3~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux3~4 .extended_lut = "on";
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux3~4 .lut_mask = 64'h1D330C331D333F33;
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux3~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X64_Y3_N57
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~27 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~27_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|Add0~13_sumout  & ( \R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout  & ( (\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & 
// ((!\R_400_to_2_5_10_100_200_300MHZ|counter [2]) # ((!\R_400_to_2_5_10_100_200_300MHZ|counter [1] & !\R_400_to_2_5_10_100_200_300MHZ|counter [0])))) ) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter [1]),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter [0]),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
        .datae(!\R_400_to_2_5_10_100_200_300MHZ|Add0~13_sumout ),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~27_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~27 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~27 .lut_mask = 64'h0000000000000F08;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~27 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X64_Y3_N6
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Mux3~0 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Mux3~0_combout  = ( !\u0|clock_sel|data_out [1] & ( ((!\u0|clock_sel|data_out [2] & (((\R_400_to_2_5_10_100_200_300MHZ|Mux3~4_combout )))) # (\u0|clock_sel|data_out [2] & ((!\R_400_to_2_5_10_100_200_300MHZ|Mux3~4_combout  & 
// (\R_400_to_2_5_10_100_200_300MHZ|counter~27_combout )) # (\R_400_to_2_5_10_100_200_300MHZ|Mux3~4_combout  & ((\R_400_to_2_5_10_100_200_300MHZ|counter~25_combout )))))) ) ) # ( \u0|clock_sel|data_out [1] & ( (!\u0|clock_sel|data_out [2] & 
// ((((\R_400_to_2_5_10_100_200_300MHZ|Mux3~4_combout ))))) # (\u0|clock_sel|data_out [2] & (((!\R_400_to_2_5_10_100_200_300MHZ|Mux3~4_combout  & ((\R_400_to_2_5_10_100_200_300MHZ|counter~28_combout ))) # (\R_400_to_2_5_10_100_200_300MHZ|Mux3~4_combout  & 
// (\R_400_to_2_5_10_100_200_300MHZ|counter~26_combout ))))) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter~26_combout ),
        .datab(!\u0|clock_sel|data_out [2]),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter~28_combout ),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter~25_combout ),
        .datae(!\u0|clock_sel|data_out [1]),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|Mux3~4_combout ),
        .datag(!\R_400_to_2_5_10_100_200_300MHZ|counter~27_combout ),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|Mux3~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux3~0 .extended_lut = "on";
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux3~0 .lut_mask = 64'h03030303CCFFDDDD;
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux3~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X55_Y4_N57
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~4 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~4_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|Mux3~0_combout  & ( \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock  ) )

        .dataa(!\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock ),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\R_400_to_2_5_10_100_200_300MHZ|Mux3~0_combout ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~4 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~4 .lut_mask = 64'h0000555500005555;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~4 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X55_Y4_N59
dffeas \R_400_to_2_5_10_100_200_300MHZ|counter[8] (
        .clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),
        .d(\R_400_to_2_5_10_100_200_300MHZ|counter~4_combout ),
        .asdata(vcc),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\R_400_to_2_5_10_100_200_300MHZ|counter [8]),
        .prn(vcc));
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[8] .is_wysiwyg = "true";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[8] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X65_Y4_N36
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|always4~0 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|always4~0_combout  = ( !\R_400_to_2_5_10_100_200_300MHZ|counter [9] & ( (!\R_400_to_2_5_10_100_200_300MHZ|counter [8] & !\R_400_to_2_5_10_100_200_300MHZ|counter [10]) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [8]),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter [10]),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter [9]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|always4~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|always4~0 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|always4~0 .lut_mask = 64'hF000F00000000000;
defparam \R_400_to_2_5_10_100_200_300MHZ|always4~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X65_Y3_N9
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~63 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~63_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|Add0~5_sumout  & ( \R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout  & ( \R_400_to_2_5_10_100_200_300MHZ|always4~0_combout  ) ) ) # ( 
// \R_400_to_2_5_10_100_200_300MHZ|Add0~5_sumout  & ( !\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout  & ( (\R_400_to_2_5_10_100_200_300MHZ|always4~0_combout  & ((!\R_400_to_2_5_10_100_200_300MHZ|counter [6]) # (!\R_400_to_2_5_10_100_200_300MHZ|counter 
// [7]))) ) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|always4~0_combout ),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter [6]),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [7]),
        .datad(gnd),
        .datae(!\R_400_to_2_5_10_100_200_300MHZ|Add0~5_sumout ),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~63_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~63 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~63 .lut_mask = 64'h0000545400005555;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~63 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X64_Y3_N30
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Mux4~4 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Mux4~4_combout  = ( !\u0|clock_sel|data_out [1] & ( (!\u0|clock_sel|data_out [0] & (!\u0|clock_sel|data_out [2] & (\R_400_to_2_5_10_100_200_300MHZ|counter~63_combout ))) # (\u0|clock_sel|data_out [0] & 
// ((((\R_400_to_2_5_10_100_200_300MHZ|counter~61_combout ))) # (\u0|clock_sel|data_out [2]))) ) ) # ( \u0|clock_sel|data_out [1] & ( (!\u0|clock_sel|data_out [0] & (!\u0|clock_sel|data_out [2] & (\R_400_to_2_5_10_100_200_300MHZ|counter~64_combout ))) # 
// (\u0|clock_sel|data_out [0] & ((((\R_400_to_2_5_10_100_200_300MHZ|counter~62_combout ))) # (\u0|clock_sel|data_out [2]))) ) )

        .dataa(!\u0|clock_sel|data_out [0]),
        .datab(!\u0|clock_sel|data_out [2]),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter~64_combout ),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter~61_combout ),
        .datae(!\u0|clock_sel|data_out [1]),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter~62_combout ),
        .datag(!\R_400_to_2_5_10_100_200_300MHZ|counter~63_combout ),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|Mux4~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux4~4 .extended_lut = "on";
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux4~4 .lut_mask = 64'h195D1919195D5D5D;
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux4~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X64_Y3_N54
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~19 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~19_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|Add0~5_sumout  & ( \R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout  & ( (\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & 
// ((!\R_400_to_2_5_10_100_200_300MHZ|counter [2]) # ((!\R_400_to_2_5_10_100_200_300MHZ|counter [1] & !\R_400_to_2_5_10_100_200_300MHZ|counter [0])))) ) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter [1]),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter [0]),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datae(!\R_400_to_2_5_10_100_200_300MHZ|Add0~5_sumout ),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~19_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~19 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~19 .lut_mask = 64'h00000000000000F8;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~19 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X64_Y3_N24
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Mux4~0 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Mux4~0_combout  = ( !\u0|clock_sel|data_out [1] & ( (!\u0|clock_sel|data_out [2] & ((((\R_400_to_2_5_10_100_200_300MHZ|Mux4~4_combout ))))) # (\u0|clock_sel|data_out [2] & (((!\R_400_to_2_5_10_100_200_300MHZ|Mux4~4_combout  
// & (\R_400_to_2_5_10_100_200_300MHZ|counter~19_combout )) # (\R_400_to_2_5_10_100_200_300MHZ|Mux4~4_combout  & ((\R_400_to_2_5_10_100_200_300MHZ|counter~17_combout )))))) ) ) # ( \u0|clock_sel|data_out [1] & ( (!\u0|clock_sel|data_out [2] & 
// ((((\R_400_to_2_5_10_100_200_300MHZ|Mux4~4_combout ))))) # (\u0|clock_sel|data_out [2] & (((!\R_400_to_2_5_10_100_200_300MHZ|Mux4~4_combout  & ((\R_400_to_2_5_10_100_200_300MHZ|counter~20_combout ))) # (\R_400_to_2_5_10_100_200_300MHZ|Mux4~4_combout  & 
// (\R_400_to_2_5_10_100_200_300MHZ|counter~18_combout ))))) ) )

        .dataa(!\u0|clock_sel|data_out [2]),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter~18_combout ),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter~20_combout ),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter~17_combout ),
        .datae(!\u0|clock_sel|data_out [1]),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|Mux4~4_combout ),
        .datag(!\R_400_to_2_5_10_100_200_300MHZ|counter~19_combout ),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|Mux4~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux4~0 .extended_lut = "on";
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux4~0 .lut_mask = 64'h05050505AAFFBBBB;
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux4~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X60_Y4_N51
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~2 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~2_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|Mux4~0_combout  & ( \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock  ) )

        .dataa(!\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock ),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|Mux4~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~2 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~2 .lut_mask = 64'h0000000055555555;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~2 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X60_Y4_N53
dffeas \R_400_to_2_5_10_100_200_300MHZ|counter[7] (
        .clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),
        .d(\R_400_to_2_5_10_100_200_300MHZ|counter~2_combout ),
        .asdata(vcc),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\R_400_to_2_5_10_100_200_300MHZ|counter [7]),
        .prn(vcc));
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[7] .is_wysiwyg = "true";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[7] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X65_Y4_N45
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~12 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~12_combout  = ( !\R_400_to_2_5_10_100_200_300MHZ|counter [9] & ( (!\R_400_to_2_5_10_100_200_300MHZ|counter [10] & (!\R_400_to_2_5_10_100_200_300MHZ|counter [7] & !\R_400_to_2_5_10_100_200_300MHZ|counter [8])) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter [10]),
        .datab(gnd),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [7]),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter [8]),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter [9]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~12_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~12 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~12 .lut_mask = 64'hA000A00000000000;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~12 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X63_Y4_N36
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~57 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~57_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|counter [5] & ( (!\R_400_to_2_5_10_100_200_300MHZ|counter [6] & (\R_400_to_2_5_10_100_200_300MHZ|counter~12_combout  & \R_400_to_2_5_10_100_200_300MHZ|Add0~1_sumout )) 
// ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|counter [5] & ( (\R_400_to_2_5_10_100_200_300MHZ|counter~12_combout  & (\R_400_to_2_5_10_100_200_300MHZ|Add0~1_sumout  & ((!\R_400_to_2_5_10_100_200_300MHZ|counter [6]) # (!\R_400_to_2_5_10_100_200_300MHZ|counter 
// [4])))) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter [6]),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter~12_combout ),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|Add0~1_sumout ),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter [4]),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~57_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~57 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~57 .lut_mask = 64'h0302030202020202;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~57 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X61_Y3_N3
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~60 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~60_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|counter [5] & ( (\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & (!\R_400_to_2_5_10_100_200_300MHZ|counter [3] & (\R_400_to_2_5_10_100_200_300MHZ|Add0~1_sumout  & 
// !\R_400_to_2_5_10_100_200_300MHZ|counter [4]))) ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|counter [5] & ( (\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & \R_400_to_2_5_10_100_200_300MHZ|Add0~1_sumout ) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter [3]),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|Add0~1_sumout ),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter [4]),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~60_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~60 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~60 .lut_mask = 64'h0505050504000400;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~60 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X60_Y3_N0
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~58 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~58_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout  & ( \R_400_to_2_5_10_100_200_300MHZ|Add0~1_sumout  & ( \R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  ) ) )

        .dataa(gnd),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datac(gnd),
        .datad(gnd),
        .datae(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add0~1_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~58_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~58 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~58 .lut_mask = 64'h0000000000003333;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~58 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X65_Y3_N57
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~59 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~59_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|counter [7] & ( \R_400_to_2_5_10_100_200_300MHZ|counter [6] & ( (\R_400_to_2_5_10_100_200_300MHZ|always4~0_combout  & (\R_400_to_2_5_10_100_200_300MHZ|Add0~1_sumout  & 
// \R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout )) ) ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|counter [7] & ( \R_400_to_2_5_10_100_200_300MHZ|counter [6] & ( (\R_400_to_2_5_10_100_200_300MHZ|always4~0_combout  & 
// \R_400_to_2_5_10_100_200_300MHZ|Add0~1_sumout ) ) ) ) # ( \R_400_to_2_5_10_100_200_300MHZ|counter [7] & ( !\R_400_to_2_5_10_100_200_300MHZ|counter [6] & ( (\R_400_to_2_5_10_100_200_300MHZ|always4~0_combout  & \R_400_to_2_5_10_100_200_300MHZ|Add0~1_sumout 
// ) ) ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|counter [7] & ( !\R_400_to_2_5_10_100_200_300MHZ|counter [6] & ( (\R_400_to_2_5_10_100_200_300MHZ|always4~0_combout  & \R_400_to_2_5_10_100_200_300MHZ|Add0~1_sumout ) ) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|always4~0_combout ),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|Add0~1_sumout ),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .datad(gnd),
        .datae(!\R_400_to_2_5_10_100_200_300MHZ|counter [7]),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter [6]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~59_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~59 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~59 .lut_mask = 64'h1111111111110101;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~59 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X61_Y3_N48
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Mux5~4 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Mux5~4_combout  = ( !\u0|clock_sel|data_out [1] & ( (!\u0|clock_sel|data_out [2] & (((!\u0|clock_sel|data_out [0] & ((\R_400_to_2_5_10_100_200_300MHZ|counter~59_combout ))) # (\u0|clock_sel|data_out [0] & 
// (\R_400_to_2_5_10_100_200_300MHZ|counter~57_combout ))))) # (\u0|clock_sel|data_out [2] & ((((\u0|clock_sel|data_out [0]))))) ) ) # ( \u0|clock_sel|data_out [1] & ( ((!\u0|clock_sel|data_out [2] & ((!\u0|clock_sel|data_out [0] & 
// (\R_400_to_2_5_10_100_200_300MHZ|counter~60_combout )) # (\u0|clock_sel|data_out [0] & ((\R_400_to_2_5_10_100_200_300MHZ|counter~58_combout ))))) # (\u0|clock_sel|data_out [2] & (((\u0|clock_sel|data_out [0]))))) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter~57_combout ),
        .datab(!\u0|clock_sel|data_out [2]),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter~60_combout ),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter~58_combout ),
        .datae(!\u0|clock_sel|data_out [1]),
        .dataf(!\u0|clock_sel|data_out [0]),
        .datag(!\R_400_to_2_5_10_100_200_300MHZ|counter~59_combout ),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|Mux5~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux5~4 .extended_lut = "on";
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux5~4 .lut_mask = 64'h0C0C0C0C777733FF;
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux5~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X61_Y3_N15
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~15 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~15_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|Add0~1_sumout  & ( \R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout  & ( (\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & 
// ((!\R_400_to_2_5_10_100_200_300MHZ|counter [2]) # ((!\R_400_to_2_5_10_100_200_300MHZ|counter [0] & !\R_400_to_2_5_10_100_200_300MHZ|counter [1])))) ) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter [0]),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [1]),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
        .datae(!\R_400_to_2_5_10_100_200_300MHZ|Add0~1_sumout ),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~15_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~15 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~15 .lut_mask = 64'h0000000000005540;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~15 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X61_Y3_N36
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Mux5~0 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Mux5~0_combout  = ( !\u0|clock_sel|data_out [1] & ( (!\u0|clock_sel|data_out [2] & ((((\R_400_to_2_5_10_100_200_300MHZ|Mux5~4_combout ))))) # (\u0|clock_sel|data_out [2] & (((!\R_400_to_2_5_10_100_200_300MHZ|Mux5~4_combout  
// & ((\R_400_to_2_5_10_100_200_300MHZ|counter~15_combout ))) # (\R_400_to_2_5_10_100_200_300MHZ|Mux5~4_combout  & (\R_400_to_2_5_10_100_200_300MHZ|counter~13_combout ))))) ) ) # ( \u0|clock_sel|data_out [1] & ( ((!\u0|clock_sel|data_out [2] & 
// (((\R_400_to_2_5_10_100_200_300MHZ|Mux5~4_combout )))) # (\u0|clock_sel|data_out [2] & ((!\R_400_to_2_5_10_100_200_300MHZ|Mux5~4_combout  & (\R_400_to_2_5_10_100_200_300MHZ|counter~16_combout )) # (\R_400_to_2_5_10_100_200_300MHZ|Mux5~4_combout  & 
// ((\R_400_to_2_5_10_100_200_300MHZ|counter~14_combout )))))) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter~13_combout ),
        .datab(!\u0|clock_sel|data_out [2]),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter~16_combout ),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter~14_combout ),
        .datae(!\u0|clock_sel|data_out [1]),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|Mux5~4_combout ),
        .datag(!\R_400_to_2_5_10_100_200_300MHZ|counter~15_combout ),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|Mux5~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux5~0 .extended_lut = "on";
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux5~0 .lut_mask = 64'h03030303DDDDCCFF;
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux5~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X55_Y4_N51
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~1 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~1_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|Mux5~0_combout  & ( \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock  ) )

        .dataa(!\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock ),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\R_400_to_2_5_10_100_200_300MHZ|Mux5~0_combout ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~1 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~1 .lut_mask = 64'h0000555500005555;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~1 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X55_Y4_N53
dffeas \R_400_to_2_5_10_100_200_300MHZ|counter[6] (
        .clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),
        .d(\R_400_to_2_5_10_100_200_300MHZ|counter~1_combout ),
        .asdata(vcc),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\R_400_to_2_5_10_100_200_300MHZ|counter [6]),
        .prn(vcc));
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[6] .is_wysiwyg = "true";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[6] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X65_Y4_N51
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~85 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~85_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|counter [4] & ( (!\R_400_to_2_5_10_100_200_300MHZ|counter [6] & (\R_400_to_2_5_10_100_200_300MHZ|Add0~29_sumout  & \R_400_to_2_5_10_100_200_300MHZ|counter~12_combout 
// )) ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|counter [4] & ( (\R_400_to_2_5_10_100_200_300MHZ|Add0~29_sumout  & (\R_400_to_2_5_10_100_200_300MHZ|counter~12_combout  & ((!\R_400_to_2_5_10_100_200_300MHZ|counter [6]) # 
// (!\R_400_to_2_5_10_100_200_300MHZ|counter [5])))) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter [6]),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter [5]),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|Add0~29_sumout ),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter~12_combout ),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~85_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~85 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~85 .lut_mask = 64'h000E000E000A000A;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~85 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X61_Y3_N18
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~86 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~86_combout  = (\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & (\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout  & \R_400_to_2_5_10_100_200_300MHZ|Add0~29_sumout ))

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .datac(gnd),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|Add0~29_sumout ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~86_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~86 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~86 .lut_mask = 64'h0011001100110011;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~86 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X61_Y3_N9
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~87 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~87_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|counter [7] & ( (\R_400_to_2_5_10_100_200_300MHZ|Add0~29_sumout  & (\R_400_to_2_5_10_100_200_300MHZ|always4~0_combout  & ((!\R_400_to_2_5_10_100_200_300MHZ|counter 
// [6]) # (\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout )))) ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|counter [7] & ( (\R_400_to_2_5_10_100_200_300MHZ|Add0~29_sumout  & \R_400_to_2_5_10_100_200_300MHZ|always4~0_combout ) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|Add0~29_sumout ),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [6]),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|always4~0_combout ),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter [7]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~87_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~87 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~87 .lut_mask = 64'h0055005500510051;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~87 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X61_Y3_N42
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Mux7~4 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Mux7~4_combout  = ( !\u0|clock_sel|data_out [1] & ( (!\u0|clock_sel|data_out [0] & (!\u0|clock_sel|data_out [2] & (\R_400_to_2_5_10_100_200_300MHZ|counter~87_combout ))) # (\u0|clock_sel|data_out [0] & 
// ((((\R_400_to_2_5_10_100_200_300MHZ|counter~85_combout ))) # (\u0|clock_sel|data_out [2]))) ) ) # ( \u0|clock_sel|data_out [1] & ( (!\u0|clock_sel|data_out [0] & (!\u0|clock_sel|data_out [2] & (\R_400_to_2_5_10_100_200_300MHZ|counter~88_combout ))) # 
// (\u0|clock_sel|data_out [0] & ((((\R_400_to_2_5_10_100_200_300MHZ|counter~86_combout ))) # (\u0|clock_sel|data_out [2]))) ) )

        .dataa(!\u0|clock_sel|data_out [0]),
        .datab(!\u0|clock_sel|data_out [2]),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter~88_combout ),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter~85_combout ),
        .datae(!\u0|clock_sel|data_out [1]),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter~86_combout ),
        .datag(!\R_400_to_2_5_10_100_200_300MHZ|counter~87_combout ),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|Mux7~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux7~4 .extended_lut = "on";
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux7~4 .lut_mask = 64'h195D1919195D5D5D;
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux7~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X61_Y3_N54
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~43 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~43_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & ( \R_400_to_2_5_10_100_200_300MHZ|counter [1] & ( (\R_400_to_2_5_10_100_200_300MHZ|Add0~29_sumout  & (!\R_400_to_2_5_10_100_200_300MHZ|counter [2] 
// & \R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout )) ) ) ) # ( \R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & ( !\R_400_to_2_5_10_100_200_300MHZ|counter [1] & ( (\R_400_to_2_5_10_100_200_300MHZ|Add0~29_sumout  & 
// (\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout  & ((!\R_400_to_2_5_10_100_200_300MHZ|counter [0]) # (!\R_400_to_2_5_10_100_200_300MHZ|counter [2])))) ) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|Add0~29_sumout ),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter [0]),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .datae(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~43_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~43 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~43 .lut_mask = 64'h0000005400000050;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~43 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X61_Y3_N30
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Mux7~0 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Mux7~0_combout  = ( !\u0|clock_sel|data_out [1] & ( (!\u0|clock_sel|data_out [2] & ((((\R_400_to_2_5_10_100_200_300MHZ|Mux7~4_combout ))))) # (\u0|clock_sel|data_out [2] & (((!\R_400_to_2_5_10_100_200_300MHZ|Mux7~4_combout  
// & ((\R_400_to_2_5_10_100_200_300MHZ|counter~43_combout ))) # (\R_400_to_2_5_10_100_200_300MHZ|Mux7~4_combout  & (\R_400_to_2_5_10_100_200_300MHZ|counter~41_combout ))))) ) ) # ( \u0|clock_sel|data_out [1] & ( ((!\u0|clock_sel|data_out [2] & 
// (((\R_400_to_2_5_10_100_200_300MHZ|Mux7~4_combout )))) # (\u0|clock_sel|data_out [2] & ((!\R_400_to_2_5_10_100_200_300MHZ|Mux7~4_combout  & (\R_400_to_2_5_10_100_200_300MHZ|counter~44_combout )) # (\R_400_to_2_5_10_100_200_300MHZ|Mux7~4_combout  & 
// ((\R_400_to_2_5_10_100_200_300MHZ|counter~42_combout )))))) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter~41_combout ),
        .datab(!\u0|clock_sel|data_out [2]),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter~44_combout ),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter~42_combout ),
        .datae(!\u0|clock_sel|data_out [1]),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|Mux7~4_combout ),
        .datag(!\R_400_to_2_5_10_100_200_300MHZ|counter~43_combout ),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|Mux7~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux7~0 .extended_lut = "on";
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux7~0 .lut_mask = 64'h03030303DDDDCCFF;
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux7~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X60_Y4_N6
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~8 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~8_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|Mux7~0_combout  & ( \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock  ) )

        .dataa(!\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock ),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|Mux7~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~8_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~8 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~8 .lut_mask = 64'h0000000055555555;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~8 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X60_Y4_N8
dffeas \R_400_to_2_5_10_100_200_300MHZ|counter[4] (
        .clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),
        .d(\R_400_to_2_5_10_100_200_300MHZ|counter~8_combout ),
        .asdata(vcc),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\R_400_to_2_5_10_100_200_300MHZ|counter [4]),
        .prn(vcc));
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[4] .is_wysiwyg = "true";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[4] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X64_Y3_N3
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~34 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~34_combout  = ( !\R_400_to_2_5_10_100_200_300MHZ|counter [1] & ( (\R_400_to_2_5_10_100_200_300MHZ|Add0~21_sumout  & (\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & 
// (\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout  & !\R_400_to_2_5_10_100_200_300MHZ|counter [2]))) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|Add0~21_sumout ),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~34_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~34 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~34 .lut_mask = 64'h0100010000000000;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~34 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X63_Y4_N24
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~77 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~77_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|Add0~21_sumout  & ( (\R_400_to_2_5_10_100_200_300MHZ|counter~12_combout  & ((!\R_400_to_2_5_10_100_200_300MHZ|counter [6]) # ((!\R_400_to_2_5_10_100_200_300MHZ|counter 
// [4] & !\R_400_to_2_5_10_100_200_300MHZ|counter [5])))) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter [4]),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter [5]),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [6]),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter~12_combout ),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add0~21_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~77_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~77 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~77 .lut_mask = 64'h0000000000F800F8;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~77 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X64_Y3_N0
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~80 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~80_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|counter [4] & ( (\R_400_to_2_5_10_100_200_300MHZ|Add0~21_sumout  & (\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & !\R_400_to_2_5_10_100_200_300MHZ|counter [5])) 
// ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|counter [4] & ( (\R_400_to_2_5_10_100_200_300MHZ|Add0~21_sumout  & (\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & ((!\R_400_to_2_5_10_100_200_300MHZ|counter [3]) # (!\R_400_to_2_5_10_100_200_300MHZ|counter 
// [5])))) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|Add0~21_sumout ),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [3]),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter [5]),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~80_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~80 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~80 .lut_mask = 64'h1110111011001100;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~80 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X63_Y3_N51
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~78 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~78_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|Add0~21_sumout  & ( (\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout  & \R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .datab(gnd),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add0~21_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~78_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~78 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~78 .lut_mask = 64'h0000000005050505;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~78 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X65_Y3_N39
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~79 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~79_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|Add0~21_sumout  & ( \R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout  & ( \R_400_to_2_5_10_100_200_300MHZ|always4~0_combout  ) ) ) # ( 
// \R_400_to_2_5_10_100_200_300MHZ|Add0~21_sumout  & ( !\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout  & ( (\R_400_to_2_5_10_100_200_300MHZ|always4~0_combout  & ((!\R_400_to_2_5_10_100_200_300MHZ|counter [6]) # 
// (!\R_400_to_2_5_10_100_200_300MHZ|counter [7]))) ) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|always4~0_combout ),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter [6]),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [7]),
        .datad(gnd),
        .datae(!\R_400_to_2_5_10_100_200_300MHZ|Add0~21_sumout ),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~79_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~79 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~79 .lut_mask = 64'h0000545400005555;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~79 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X63_Y3_N42
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Mux6~4 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Mux6~4_combout  = ( !\u0|clock_sel|data_out [1] & ( (!\u0|clock_sel|data_out [2] & ((!\u0|clock_sel|data_out [0] & (((\R_400_to_2_5_10_100_200_300MHZ|counter~79_combout )))) # (\u0|clock_sel|data_out [0] & 
// (\R_400_to_2_5_10_100_200_300MHZ|counter~77_combout )))) # (\u0|clock_sel|data_out [2] & ((((\u0|clock_sel|data_out [0]))))) ) ) # ( \u0|clock_sel|data_out [1] & ( (!\u0|clock_sel|data_out [2] & (((!\u0|clock_sel|data_out [0] & 
// (\R_400_to_2_5_10_100_200_300MHZ|counter~80_combout )) # (\u0|clock_sel|data_out [0] & ((\R_400_to_2_5_10_100_200_300MHZ|counter~78_combout )))))) # (\u0|clock_sel|data_out [2] & ((((\u0|clock_sel|data_out [0]))))) ) )

        .dataa(!\u0|clock_sel|data_out [2]),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter~77_combout ),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter~80_combout ),
        .datad(!\u0|clock_sel|data_out [0]),
        .datae(!\u0|clock_sel|data_out [1]),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter~78_combout ),
        .datag(!\R_400_to_2_5_10_100_200_300MHZ|counter~79_combout ),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|Mux6~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux6~4 .extended_lut = "on";
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux6~4 .lut_mask = 64'h0A770A550A770AFF;
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux6~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X63_Y3_N18
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~36 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~36_combout  = ( !\R_400_to_2_5_10_100_200_300MHZ|counter [2] & ( \R_400_to_2_5_10_100_200_300MHZ|counter [0] & ( (!\R_400_to_2_5_10_100_200_300MHZ|counter [1] & (\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & 
// (\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout  & \R_400_to_2_5_10_100_200_300MHZ|Add0~21_sumout ))) ) ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|counter [2] & ( !\R_400_to_2_5_10_100_200_300MHZ|counter [0] & ( 
// (\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & (\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout  & \R_400_to_2_5_10_100_200_300MHZ|Add0~21_sumout )) ) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter [1]),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|Add0~21_sumout ),
        .datae(!\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~36_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~36 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~36 .lut_mask = 64'h0003000000020000;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~36 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X63_Y3_N12
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~33 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~33_combout  = ( !\R_400_to_2_5_10_100_200_300MHZ|counter [2] & ( \R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & ( (\R_400_to_2_5_10_100_200_300MHZ|Add0~21_sumout  & 
// \R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ) ) ) )

        .dataa(gnd),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|Add0~21_sumout ),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .datad(gnd),
        .datae(!\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~33_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~33 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~33 .lut_mask = 64'h0000000003030000;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~33 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X63_Y3_N36
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~35 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~35_combout  = ( !\R_400_to_2_5_10_100_200_300MHZ|counter [2] & ( \R_400_to_2_5_10_100_200_300MHZ|counter [0] & ( (\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & 
// (\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout  & \R_400_to_2_5_10_100_200_300MHZ|Add0~21_sumout )) ) ) ) # ( \R_400_to_2_5_10_100_200_300MHZ|counter [2] & ( !\R_400_to_2_5_10_100_200_300MHZ|counter [0] & ( (!\R_400_to_2_5_10_100_200_300MHZ|counter 
// [1] & (\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & (\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout  & \R_400_to_2_5_10_100_200_300MHZ|Add0~21_sumout ))) ) ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|counter [2] & ( 
// !\R_400_to_2_5_10_100_200_300MHZ|counter [0] & ( (\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & (\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout  & \R_400_to_2_5_10_100_200_300MHZ|Add0~21_sumout )) ) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter [1]),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|Add0~21_sumout ),
        .datae(!\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~35_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~35 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~35 .lut_mask = 64'h0003000200030000;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~35 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X63_Y3_N54
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Mux6~0 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Mux6~0_combout  = ( !\u0|clock_sel|data_out [1] & ( ((!\R_400_to_2_5_10_100_200_300MHZ|Mux6~4_combout  & (\R_400_to_2_5_10_100_200_300MHZ|counter~35_combout  & ((\u0|clock_sel|data_out [2])))) # 
// (\R_400_to_2_5_10_100_200_300MHZ|Mux6~4_combout  & (((!\u0|clock_sel|data_out [2]) # (\R_400_to_2_5_10_100_200_300MHZ|counter~33_combout ))))) ) ) # ( \u0|clock_sel|data_out [1] & ( (!\R_400_to_2_5_10_100_200_300MHZ|Mux6~4_combout  & 
// (((\R_400_to_2_5_10_100_200_300MHZ|counter~36_combout  & ((\u0|clock_sel|data_out [2])))))) # (\R_400_to_2_5_10_100_200_300MHZ|Mux6~4_combout  & ((((!\u0|clock_sel|data_out [2]))) # (\R_400_to_2_5_10_100_200_300MHZ|counter~34_combout ))) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter~34_combout ),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|Mux6~4_combout ),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter~36_combout ),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter~33_combout ),
        .datae(!\u0|clock_sel|data_out [1]),
        .dataf(!\u0|clock_sel|data_out [2]),
        .datag(!\R_400_to_2_5_10_100_200_300MHZ|counter~35_combout ),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|Mux6~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux6~0 .extended_lut = "on";
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux6~0 .lut_mask = 64'h333333330C3F1D1D;
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux6~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X60_Y4_N9
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~6 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~6_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|Mux6~0_combout  & ( \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock  ) )

        .dataa(!\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock ),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|Mux6~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~6 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~6 .lut_mask = 64'h0000000055555555;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~6 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X60_Y4_N11
dffeas \R_400_to_2_5_10_100_200_300MHZ|counter[5] (
        .clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),
        .d(\R_400_to_2_5_10_100_200_300MHZ|counter~6_combout ),
        .asdata(vcc),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\R_400_to_2_5_10_100_200_300MHZ|counter [5]),
        .prn(vcc));
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[5] .is_wysiwyg = "true";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[5] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X64_Y3_N15
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|LessThan11~0 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout  = ( !\R_400_to_2_5_10_100_200_300MHZ|counter [3] & ( (!\R_400_to_2_5_10_100_200_300MHZ|counter [5] & !\R_400_to_2_5_10_100_200_300MHZ|counter [4]) ) )

        .dataa(gnd),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter [5]),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [4]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|LessThan11~0 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|LessThan11~0 .lut_mask = 64'hC0C0C0C000000000;
defparam \R_400_to_2_5_10_100_200_300MHZ|LessThan11~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X61_Y4_N30
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~98 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~98_combout  = (\R_400_to_2_5_10_100_200_300MHZ|Add0~41_sumout  & (\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & \R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ))

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|Add0~41_sumout ),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~98_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~98 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~98 .lut_mask = 64'h0101010101010101;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~98 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X61_Y4_N33
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~100 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~100_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|counter [4] & ( (\R_400_to_2_5_10_100_200_300MHZ|Add0~41_sumout  & (\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & !\R_400_to_2_5_10_100_200_300MHZ|counter 
// [5])) ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|counter [4] & ( (\R_400_to_2_5_10_100_200_300MHZ|Add0~41_sumout  & (\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & ((!\R_400_to_2_5_10_100_200_300MHZ|counter [3]) # 
// (!\R_400_to_2_5_10_100_200_300MHZ|counter [5])))) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|Add0~41_sumout ),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [3]),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter [5]),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~100_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~100 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~100 .lut_mask = 64'h1110111011001100;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~100 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X65_Y4_N48
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~97 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~97_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|counter [4] & ( (!\R_400_to_2_5_10_100_200_300MHZ|counter [6] & (\R_400_to_2_5_10_100_200_300MHZ|Add0~41_sumout  & \R_400_to_2_5_10_100_200_300MHZ|counter~12_combout 
// )) ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|counter [4] & ( (\R_400_to_2_5_10_100_200_300MHZ|Add0~41_sumout  & (\R_400_to_2_5_10_100_200_300MHZ|counter~12_combout  & ((!\R_400_to_2_5_10_100_200_300MHZ|counter [6]) # 
// (!\R_400_to_2_5_10_100_200_300MHZ|counter [5])))) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter [6]),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter [5]),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|Add0~41_sumout ),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter~12_combout ),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~97_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~97 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~97 .lut_mask = 64'h000E000E000A000A;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~97 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X64_Y4_N57
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~99 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~99_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|counter [6] & ( \R_400_to_2_5_10_100_200_300MHZ|counter [7] & ( (\R_400_to_2_5_10_100_200_300MHZ|Add0~41_sumout  & 
// (\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout  & \R_400_to_2_5_10_100_200_300MHZ|always4~0_combout )) ) ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|counter [6] & ( \R_400_to_2_5_10_100_200_300MHZ|counter [7] & ( 
// (\R_400_to_2_5_10_100_200_300MHZ|Add0~41_sumout  & \R_400_to_2_5_10_100_200_300MHZ|always4~0_combout ) ) ) ) # ( \R_400_to_2_5_10_100_200_300MHZ|counter [6] & ( !\R_400_to_2_5_10_100_200_300MHZ|counter [7] & ( 
// (\R_400_to_2_5_10_100_200_300MHZ|Add0~41_sumout  & \R_400_to_2_5_10_100_200_300MHZ|always4~0_combout ) ) ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|counter [6] & ( !\R_400_to_2_5_10_100_200_300MHZ|counter [7] & ( 
// (\R_400_to_2_5_10_100_200_300MHZ|Add0~41_sumout  & \R_400_to_2_5_10_100_200_300MHZ|always4~0_combout ) ) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|Add0~41_sumout ),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|always4~0_combout ),
        .datad(gnd),
        .datae(!\R_400_to_2_5_10_100_200_300MHZ|counter [6]),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter [7]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~99_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~99 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~99 .lut_mask = 64'h0505050505050101;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~99 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X61_Y4_N18
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Mux11~4 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Mux11~4_combout  = ( !\u0|clock_sel|data_out [1] & ( (!\u0|clock_sel|data_out [0] & (((\R_400_to_2_5_10_100_200_300MHZ|counter~99_combout  & ((!\u0|clock_sel|data_out [2])))))) # (\u0|clock_sel|data_out [0] & 
// ((((\u0|clock_sel|data_out [2]) # (\R_400_to_2_5_10_100_200_300MHZ|counter~97_combout ))))) ) ) # ( \u0|clock_sel|data_out [1] & ( (!\u0|clock_sel|data_out [0] & (((\R_400_to_2_5_10_100_200_300MHZ|counter~100_combout  & ((!\u0|clock_sel|data_out [2])))))) 
// # (\u0|clock_sel|data_out [0] & ((((\u0|clock_sel|data_out [2]))) # (\R_400_to_2_5_10_100_200_300MHZ|counter~98_combout ))) ) )

        .dataa(!\u0|clock_sel|data_out [0]),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter~98_combout ),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter~100_combout ),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter~97_combout ),
        .datae(!\u0|clock_sel|data_out [1]),
        .dataf(!\u0|clock_sel|data_out [2]),
        .datag(!\R_400_to_2_5_10_100_200_300MHZ|counter~99_combout ),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|Mux11~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux11~4 .extended_lut = "on";
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux11~4 .lut_mask = 64'h0A5F1B1B55555555;
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux11~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X64_Y3_N36
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~54 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~54_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout  & ( (!\R_400_to_2_5_10_100_200_300MHZ|counter [1] & (\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & 
// (!\R_400_to_2_5_10_100_200_300MHZ|counter [2] & \R_400_to_2_5_10_100_200_300MHZ|Add0~41_sumout ))) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter [1]),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|Add0~41_sumout ),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~54_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~54 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~54 .lut_mask = 64'h0000000000200020;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~54 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X61_Y4_N3
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~56 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~56_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|Add0~41_sumout  & ( \R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout  & ( (\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & 
// (!\R_400_to_2_5_10_100_200_300MHZ|counter [2] & ((!\R_400_to_2_5_10_100_200_300MHZ|counter [0]) # (!\R_400_to_2_5_10_100_200_300MHZ|counter [1])))) ) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter [0]),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [1]),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
        .datae(!\R_400_to_2_5_10_100_200_300MHZ|Add0~41_sumout ),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~56_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~56 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~56 .lut_mask = 64'h0000000000003200;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~56 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X61_Y4_N12
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~53 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~53_combout  = ( !\R_400_to_2_5_10_100_200_300MHZ|counter [2] & ( \R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & ( (\R_400_to_2_5_10_100_200_300MHZ|Add0~41_sumout  & 
// \R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ) ) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|Add0~41_sumout ),
        .datab(gnd),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .datad(gnd),
        .datae(!\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~53_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~53 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~53 .lut_mask = 64'h0000000005050000;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~53 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X61_Y3_N12
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~55 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~55_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout  & ( \R_400_to_2_5_10_100_200_300MHZ|Add0~41_sumout  & ( (\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & 
// ((!\R_400_to_2_5_10_100_200_300MHZ|counter [2]) # ((!\R_400_to_2_5_10_100_200_300MHZ|counter [0] & !\R_400_to_2_5_10_100_200_300MHZ|counter [1])))) ) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter [0]),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter [1]),
        .datae(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add0~41_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~55_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~55 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~55 .lut_mask = 64'h0000000000005450;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~55 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X61_Y4_N54
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Mux11~0 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Mux11~0_combout  = ( !\u0|clock_sel|data_out [1] & ( (!\R_400_to_2_5_10_100_200_300MHZ|Mux11~4_combout  & (((\R_400_to_2_5_10_100_200_300MHZ|counter~55_combout  & ((\u0|clock_sel|data_out [2])))))) # 
// (\R_400_to_2_5_10_100_200_300MHZ|Mux11~4_combout  & ((((!\u0|clock_sel|data_out [2]) # (\R_400_to_2_5_10_100_200_300MHZ|counter~53_combout ))))) ) ) # ( \u0|clock_sel|data_out [1] & ( (!\R_400_to_2_5_10_100_200_300MHZ|Mux11~4_combout  & 
// (((\R_400_to_2_5_10_100_200_300MHZ|counter~56_combout  & ((\u0|clock_sel|data_out [2])))))) # (\R_400_to_2_5_10_100_200_300MHZ|Mux11~4_combout  & ((((!\u0|clock_sel|data_out [2]))) # (\R_400_to_2_5_10_100_200_300MHZ|counter~54_combout ))) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|Mux11~4_combout ),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter~54_combout ),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter~56_combout ),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter~53_combout ),
        .datae(!\u0|clock_sel|data_out [1]),
        .dataf(!\u0|clock_sel|data_out [2]),
        .datag(!\R_400_to_2_5_10_100_200_300MHZ|counter~55_combout ),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|Mux11~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux11~0 .extended_lut = "on";
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux11~0 .lut_mask = 64'h555555550A5F1B1B;
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux11~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X60_Y4_N36
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~11 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~11_combout  = (\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock  & \R_400_to_2_5_10_100_200_300MHZ|Mux11~0_combout )

        .dataa(!\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock ),
        .datab(gnd),
        .datac(gnd),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|Mux11~0_combout ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~11_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~11 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~11 .lut_mask = 64'h0055005500550055;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~11 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X60_Y4_N38
dffeas \R_400_to_2_5_10_100_200_300MHZ|counter[0] (
        .clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),
        .d(\R_400_to_2_5_10_100_200_300MHZ|counter~11_combout ),
        .asdata(vcc),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\R_400_to_2_5_10_100_200_300MHZ|counter [0]),
        .prn(vcc));
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[0] .is_wysiwyg = "true";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[0] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X61_Y4_N48
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~46 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~46_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout  & ( (\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & (\R_400_to_2_5_10_100_200_300MHZ|Add0~33_sumout  & 
// (!\R_400_to_2_5_10_100_200_300MHZ|counter [2] & !\R_400_to_2_5_10_100_200_300MHZ|counter [1]))) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|Add0~33_sumout ),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter [1]),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~46_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~46 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~46 .lut_mask = 64'h0000000010001000;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~46 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X61_Y4_N9
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~90 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~90_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & ( (\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout  & \R_400_to_2_5_10_100_200_300MHZ|Add0~33_sumout ) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .datab(gnd),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|Add0~33_sumout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~90_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~90 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~90 .lut_mask = 64'h0000000005050505;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~90 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X61_Y4_N51
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~92 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~92_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|counter [4] & ( (\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & (\R_400_to_2_5_10_100_200_300MHZ|Add0~33_sumout  & !\R_400_to_2_5_10_100_200_300MHZ|counter [5])) 
// ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|counter [4] & ( (\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & (\R_400_to_2_5_10_100_200_300MHZ|Add0~33_sumout  & ((!\R_400_to_2_5_10_100_200_300MHZ|counter [3]) # (!\R_400_to_2_5_10_100_200_300MHZ|counter 
// [5])))) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|Add0~33_sumout ),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [3]),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter [5]),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~92_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~92 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~92 .lut_mask = 64'h1110111011001100;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~92 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X65_Y4_N54
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~89 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~89_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|counter [4] & ( (!\R_400_to_2_5_10_100_200_300MHZ|counter [6] & (\R_400_to_2_5_10_100_200_300MHZ|Add0~33_sumout  & \R_400_to_2_5_10_100_200_300MHZ|counter~12_combout 
// )) ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|counter [4] & ( (\R_400_to_2_5_10_100_200_300MHZ|Add0~33_sumout  & (\R_400_to_2_5_10_100_200_300MHZ|counter~12_combout  & ((!\R_400_to_2_5_10_100_200_300MHZ|counter [6]) # 
// (!\R_400_to_2_5_10_100_200_300MHZ|counter [5])))) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter [6]),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter [5]),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|Add0~33_sumout ),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter~12_combout ),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~89_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~89 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~89 .lut_mask = 64'h000E000E000A000A;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~89 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X64_Y4_N51
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~91 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~91_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|counter [7] & ( (\R_400_to_2_5_10_100_200_300MHZ|always4~0_combout  & (\R_400_to_2_5_10_100_200_300MHZ|Add0~33_sumout  & ((!\R_400_to_2_5_10_100_200_300MHZ|counter 
// [6]) # (\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout )))) ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|counter [7] & ( (\R_400_to_2_5_10_100_200_300MHZ|always4~0_combout  & \R_400_to_2_5_10_100_200_300MHZ|Add0~33_sumout ) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|always4~0_combout ),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|Add0~33_sumout ),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter [6]),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter [7]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~91_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~91 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~91 .lut_mask = 64'h0505050505010501;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~91 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X61_Y4_N42
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Mux10~4 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Mux10~4_combout  = ( !\u0|clock_sel|data_out [1] & ( (!\u0|clock_sel|data_out [0] & (((\R_400_to_2_5_10_100_200_300MHZ|counter~91_combout  & ((!\u0|clock_sel|data_out [2])))))) # (\u0|clock_sel|data_out [0] & 
// ((((\u0|clock_sel|data_out [2]) # (\R_400_to_2_5_10_100_200_300MHZ|counter~89_combout ))))) ) ) # ( \u0|clock_sel|data_out [1] & ( (!\u0|clock_sel|data_out [0] & (((\R_400_to_2_5_10_100_200_300MHZ|counter~92_combout  & ((!\u0|clock_sel|data_out [2])))))) 
// # (\u0|clock_sel|data_out [0] & ((((\u0|clock_sel|data_out [2]))) # (\R_400_to_2_5_10_100_200_300MHZ|counter~90_combout ))) ) )

        .dataa(!\u0|clock_sel|data_out [0]),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter~90_combout ),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter~92_combout ),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter~89_combout ),
        .datae(!\u0|clock_sel|data_out [1]),
        .dataf(!\u0|clock_sel|data_out [2]),
        .datag(!\R_400_to_2_5_10_100_200_300MHZ|counter~91_combout ),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|Mux10~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux10~4 .extended_lut = "on";
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux10~4 .lut_mask = 64'h0A5F1B1B55555555;
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux10~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X61_Y4_N0
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~48 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~48_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout  & ( \R_400_to_2_5_10_100_200_300MHZ|Add0~33_sumout  & ( (\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & 
// (!\R_400_to_2_5_10_100_200_300MHZ|counter [2] & ((!\R_400_to_2_5_10_100_200_300MHZ|counter [0]) # (!\R_400_to_2_5_10_100_200_300MHZ|counter [1])))) ) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter [0]),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter [1]),
        .datae(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add0~33_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~48_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~48 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~48 .lut_mask = 64'h0000000000003020;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~48 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X61_Y4_N6
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~45 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~45_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|Add0~33_sumout  & ( (\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout  & (\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & 
// !\R_400_to_2_5_10_100_200_300MHZ|counter [2])) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add0~33_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~45_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~45 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~45 .lut_mask = 64'h0000000010101010;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~45 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X60_Y4_N57
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~47 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~47_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout  & ( \R_400_to_2_5_10_100_200_300MHZ|Add0~33_sumout  & ( (\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & 
// ((!\R_400_to_2_5_10_100_200_300MHZ|counter [2]) # ((!\R_400_to_2_5_10_100_200_300MHZ|counter [1] & !\R_400_to_2_5_10_100_200_300MHZ|counter [0])))) ) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter [1]),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter [0]),
        .datae(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add0~33_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~47_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~47 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~47 .lut_mask = 64'h0000000000000E0A;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~47 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X61_Y4_N24
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Mux10~0 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Mux10~0_combout  = ( !\u0|clock_sel|data_out [1] & ( ((!\R_400_to_2_5_10_100_200_300MHZ|Mux10~4_combout  & (\R_400_to_2_5_10_100_200_300MHZ|counter~47_combout  & ((\u0|clock_sel|data_out [2])))) # 
// (\R_400_to_2_5_10_100_200_300MHZ|Mux10~4_combout  & (((!\u0|clock_sel|data_out [2]) # (\R_400_to_2_5_10_100_200_300MHZ|counter~45_combout ))))) ) ) # ( \u0|clock_sel|data_out [1] & ( (!\R_400_to_2_5_10_100_200_300MHZ|Mux10~4_combout  & 
// (((\R_400_to_2_5_10_100_200_300MHZ|counter~48_combout  & ((\u0|clock_sel|data_out [2])))))) # (\R_400_to_2_5_10_100_200_300MHZ|Mux10~4_combout  & ((((!\u0|clock_sel|data_out [2]))) # (\R_400_to_2_5_10_100_200_300MHZ|counter~46_combout ))) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter~46_combout ),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|Mux10~4_combout ),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter~48_combout ),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter~45_combout ),
        .datae(!\u0|clock_sel|data_out [1]),
        .dataf(!\u0|clock_sel|data_out [2]),
        .datag(!\R_400_to_2_5_10_100_200_300MHZ|counter~47_combout ),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|Mux10~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux10~0 .extended_lut = "on";
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux10~0 .lut_mask = 64'h333333330C3F1D1D;
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux10~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X60_Y4_N39
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~9 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~9_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|Mux10~0_combout  & ( \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock  ) )

        .dataa(!\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock ),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|Mux10~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~9_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~9 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~9 .lut_mask = 64'h0000000055555555;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~9 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X60_Y4_N41
dffeas \R_400_to_2_5_10_100_200_300MHZ|counter[1] (
        .clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),
        .d(\R_400_to_2_5_10_100_200_300MHZ|counter~9_combout ),
        .asdata(vcc),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\R_400_to_2_5_10_100_200_300MHZ|counter [1]),
        .prn(vcc));
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[1] .is_wysiwyg = "true";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[1] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X65_Y4_N27
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add0~17 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Add0~17_sumout  = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter [9] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add0~14  ))
// \R_400_to_2_5_10_100_200_300MHZ|Add0~18  = CARRY(( \R_400_to_2_5_10_100_200_300MHZ|counter [9] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add0~14  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [9]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\R_400_to_2_5_10_100_200_300MHZ|Add0~14 ),
        .sharein(gnd),
        .combout(),
        .sumout(\R_400_to_2_5_10_100_200_300MHZ|Add0~17_sumout ),
        .cout(\R_400_to_2_5_10_100_200_300MHZ|Add0~18 ),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~17 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~17 .lut_mask = 64'h0000FFFF00000F0F;
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~17 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X60_Y4_N15
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~30 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~30_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|Add0~17_sumout  & ( (!\R_400_to_2_5_10_100_200_300MHZ|counter [2] & (\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & (!\R_400_to_2_5_10_100_200_300MHZ|counter [1] 
// & \R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ))) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [1]),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add0~17_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~30_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~30 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~30 .lut_mask = 64'h0000000000200020;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~30 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X60_Y4_N0
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~32 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~32_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout  & ( \R_400_to_2_5_10_100_200_300MHZ|Add0~17_sumout  & ( (!\R_400_to_2_5_10_100_200_300MHZ|counter [2] & 
// (\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & ((!\R_400_to_2_5_10_100_200_300MHZ|counter [0]) # (!\R_400_to_2_5_10_100_200_300MHZ|counter [1])))) ) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [0]),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter [1]),
        .datae(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add0~17_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~32_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~32 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~32 .lut_mask = 64'h0000000000002220;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~32 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X60_Y4_N12
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~29 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~29_combout  = (!\R_400_to_2_5_10_100_200_300MHZ|counter [2] & (\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & (\R_400_to_2_5_10_100_200_300MHZ|Add0~17_sumout  & 
// \R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout )))

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|Add0~17_sumout ),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~29_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~29 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~29 .lut_mask = 64'h0002000200020002;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~29 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X65_Y4_N39
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~76 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~76_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|counter [3] & ( (\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & (!\R_400_to_2_5_10_100_200_300MHZ|counter [5] & \R_400_to_2_5_10_100_200_300MHZ|Add0~17_sumout )) 
// ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|counter [3] & ( (\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & (\R_400_to_2_5_10_100_200_300MHZ|Add0~17_sumout  & ((!\R_400_to_2_5_10_100_200_300MHZ|counter [4]) # (!\R_400_to_2_5_10_100_200_300MHZ|counter 
// [5])))) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter [4]),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [5]),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|Add0~17_sumout ),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter [3]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~76_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~76 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~76 .lut_mask = 64'h0054005400500050;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~76 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X63_Y4_N39
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~73 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~73_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|Add0~17_sumout  & ( (\R_400_to_2_5_10_100_200_300MHZ|counter~12_combout  & ((!\R_400_to_2_5_10_100_200_300MHZ|counter [6]) # ((!\R_400_to_2_5_10_100_200_300MHZ|counter 
// [5] & !\R_400_to_2_5_10_100_200_300MHZ|counter [4])))) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter [6]),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter~12_combout ),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [5]),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter [4]),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add0~17_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~73_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~73 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~73 .lut_mask = 64'h0000000032223222;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~73 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X64_Y4_N12
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~74 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~74_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|Add0~17_sumout  & ( \R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout  & ( \R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  ) ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datad(gnd),
        .datae(!\R_400_to_2_5_10_100_200_300MHZ|Add0~17_sumout ),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~74_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~74 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~74 .lut_mask = 64'h0000000000000F0F;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~74 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X64_Y4_N45
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~75 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~75_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|Add0~17_sumout  & ( \R_400_to_2_5_10_100_200_300MHZ|counter [7] & ( (\R_400_to_2_5_10_100_200_300MHZ|always4~0_combout  & ((!\R_400_to_2_5_10_100_200_300MHZ|counter 
// [6]) # (\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ))) ) ) ) # ( \R_400_to_2_5_10_100_200_300MHZ|Add0~17_sumout  & ( !\R_400_to_2_5_10_100_200_300MHZ|counter [7] & ( \R_400_to_2_5_10_100_200_300MHZ|always4~0_combout  ) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|always4~0_combout ),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [6]),
        .datad(gnd),
        .datae(!\R_400_to_2_5_10_100_200_300MHZ|Add0~17_sumout ),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter [7]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~75_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~75 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~75 .lut_mask = 64'h0000555500005151;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~75 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X64_Y4_N6
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Mux2~4 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Mux2~4_combout  = ( !\u0|clock_sel|data_out [1] & ( (!\u0|clock_sel|data_out [2] & ((!\u0|clock_sel|data_out [0] & (\R_400_to_2_5_10_100_200_300MHZ|counter~75_combout )) # (\u0|clock_sel|data_out [0] & 
// (((\R_400_to_2_5_10_100_200_300MHZ|counter~73_combout )))))) # (\u0|clock_sel|data_out [2] & (\u0|clock_sel|data_out [0])) ) ) # ( \u0|clock_sel|data_out [1] & ( (!\u0|clock_sel|data_out [2] & ((!\u0|clock_sel|data_out [0] & 
// (\R_400_to_2_5_10_100_200_300MHZ|counter~76_combout )) # (\u0|clock_sel|data_out [0] & (((\R_400_to_2_5_10_100_200_300MHZ|counter~74_combout )))))) # (\u0|clock_sel|data_out [2] & (\u0|clock_sel|data_out [0])) ) )

        .dataa(!\u0|clock_sel|data_out [2]),
        .datab(!\u0|clock_sel|data_out [0]),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter~76_combout ),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter~73_combout ),
        .datae(!\u0|clock_sel|data_out [1]),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter~74_combout ),
        .datag(!\R_400_to_2_5_10_100_200_300MHZ|counter~75_combout ),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|Mux2~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux2~4 .extended_lut = "on";
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux2~4 .lut_mask = 64'h193B1919193B3B3B;
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux2~4 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X60_Y4_N45
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~31 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~31_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout  & ( \R_400_to_2_5_10_100_200_300MHZ|Add0~17_sumout  & ( (\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & 
// ((!\R_400_to_2_5_10_100_200_300MHZ|counter [2]) # ((!\R_400_to_2_5_10_100_200_300MHZ|counter [1] & !\R_400_to_2_5_10_100_200_300MHZ|counter [0])))) ) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [1]),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter [0]),
        .datae(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add0~17_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~31_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~31 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~31 .lut_mask = 64'h0000000000003222;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~31 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X60_Y4_N18
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Mux2~0 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Mux2~0_combout  = ( !\u0|clock_sel|data_out [1] & ( (!\u0|clock_sel|data_out [2] & ((((\R_400_to_2_5_10_100_200_300MHZ|Mux2~4_combout ))))) # (\u0|clock_sel|data_out [2] & (((!\R_400_to_2_5_10_100_200_300MHZ|Mux2~4_combout  
// & (\R_400_to_2_5_10_100_200_300MHZ|counter~31_combout )) # (\R_400_to_2_5_10_100_200_300MHZ|Mux2~4_combout  & ((\R_400_to_2_5_10_100_200_300MHZ|counter~29_combout )))))) ) ) # ( \u0|clock_sel|data_out [1] & ( (!\u0|clock_sel|data_out [2] & 
// ((((\R_400_to_2_5_10_100_200_300MHZ|Mux2~4_combout ))))) # (\u0|clock_sel|data_out [2] & (((!\R_400_to_2_5_10_100_200_300MHZ|Mux2~4_combout  & ((\R_400_to_2_5_10_100_200_300MHZ|counter~32_combout ))) # (\R_400_to_2_5_10_100_200_300MHZ|Mux2~4_combout  & 
// (\R_400_to_2_5_10_100_200_300MHZ|counter~30_combout ))))) ) )

        .dataa(!\u0|clock_sel|data_out [2]),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter~30_combout ),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter~32_combout ),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter~29_combout ),
        .datae(!\u0|clock_sel|data_out [1]),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|Mux2~4_combout ),
        .datag(!\R_400_to_2_5_10_100_200_300MHZ|counter~31_combout ),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|Mux2~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux2~0 .extended_lut = "on";
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux2~0 .lut_mask = 64'h05050505AAFFBBBB;
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux2~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X55_Y4_N12
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~5 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~5_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|Mux2~0_combout  & ( \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|Mux2~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~5 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~5 .lut_mask = 64'h000000000F0F0F0F;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~5 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X55_Y4_N14
dffeas \R_400_to_2_5_10_100_200_300MHZ|counter[9] (
        .clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),
        .d(\R_400_to_2_5_10_100_200_300MHZ|counter~5_combout ),
        .asdata(vcc),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\R_400_to_2_5_10_100_200_300MHZ|counter [9]),
        .prn(vcc));
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[9] .is_wysiwyg = "true";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[9] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X65_Y4_N30
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add0~9 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Add0~9_sumout  = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter [10] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add0~18  ))

        .dataa(gnd),
        .datab(gnd),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [10]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(\R_400_to_2_5_10_100_200_300MHZ|Add0~18 ),
        .sharein(gnd),
        .combout(),
        .sumout(\R_400_to_2_5_10_100_200_300MHZ|Add0~9_sumout ),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~9 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~9 .lut_mask = 64'h0000FFFF00000F0F;
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~9 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X59_Y4_N9
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Equal2~1 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Equal2~1_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout  & ( \R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|Equal2~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Equal2~1 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|Equal2~1 .lut_mask = 64'h0000555500005555;
defparam \R_400_to_2_5_10_100_200_300MHZ|Equal2~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X59_Y4_N51
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~21 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~21_combout  = (\R_400_to_2_5_10_100_200_300MHZ|Add0~9_sumout  & (\R_400_to_2_5_10_100_200_300MHZ|Equal2~1_combout  & !\R_400_to_2_5_10_100_200_300MHZ|counter [2]))

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|Add0~9_sumout ),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|Equal2~1_combout ),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~21_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~21 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~21 .lut_mask = 64'h1010101010101010;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~21 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X59_Y4_N27
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~24 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~24_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout  & ( \R_400_to_2_5_10_100_200_300MHZ|Add0~9_sumout  & ( (!\R_400_to_2_5_10_100_200_300MHZ|counter [2] & 
// (\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & ((!\R_400_to_2_5_10_100_200_300MHZ|counter [1]) # (!\R_400_to_2_5_10_100_200_300MHZ|counter [0])))) ) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter [1]),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [0]),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datae(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add0~9_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~24_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~24 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~24 .lut_mask = 64'h00000000000000C8;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~24 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X59_Y4_N39
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~22 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~22_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|Add0~9_sumout  & ( (!\R_400_to_2_5_10_100_200_300MHZ|counter [1] & (\R_400_to_2_5_10_100_200_300MHZ|Equal2~1_combout  & !\R_400_to_2_5_10_100_200_300MHZ|counter [2])) 
// ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter [1]),
        .datab(gnd),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|Equal2~1_combout ),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add0~9_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~22_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~22 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~22 .lut_mask = 64'h000000000A000A00;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~22 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X63_Y4_N21
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~68 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~68_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & ( \R_400_to_2_5_10_100_200_300MHZ|Add0~9_sumout  & ( (!\R_400_to_2_5_10_100_200_300MHZ|counter [5]) # ((!\R_400_to_2_5_10_100_200_300MHZ|counter 
// [4] & !\R_400_to_2_5_10_100_200_300MHZ|counter [3])) ) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter [4]),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter [3]),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [5]),
        .datad(gnd),
        .datae(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add0~9_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~68_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~68 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~68 .lut_mask = 64'h000000000000F8F8;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~68 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X63_Y4_N54
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~65 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~65_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|Add0~9_sumout  & ( (\R_400_to_2_5_10_100_200_300MHZ|counter~12_combout  & ((!\R_400_to_2_5_10_100_200_300MHZ|counter [6]) # ((!\R_400_to_2_5_10_100_200_300MHZ|counter 
// [4] & !\R_400_to_2_5_10_100_200_300MHZ|counter [5])))) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter [4]),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter [5]),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [6]),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter~12_combout ),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add0~9_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~65_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~65 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~65 .lut_mask = 64'h0000000000F800F8;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~65 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X59_Y4_N48
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~66 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~66_combout  = (\R_400_to_2_5_10_100_200_300MHZ|Add0~9_sumout  & \R_400_to_2_5_10_100_200_300MHZ|Equal2~1_combout )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|Add0~9_sumout ),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|Equal2~1_combout ),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~66_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~66 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~66 .lut_mask = 64'h1111111111111111;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~66 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X64_Y4_N48
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~67 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~67_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|Add0~9_sumout  & ( (\R_400_to_2_5_10_100_200_300MHZ|always4~0_combout  & (((!\R_400_to_2_5_10_100_200_300MHZ|counter [7]) # (!\R_400_to_2_5_10_100_200_300MHZ|counter 
// [6])) # (\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ))) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|always4~0_combout ),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [7]),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter [6]),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add0~9_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~67_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~67 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~67 .lut_mask = 64'h0000000055515551;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~67 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X59_Y4_N30
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Mux1~4 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Mux1~4_combout  = ( !\u0|clock_sel|data_out [1] & ( (!\u0|clock_sel|data_out [0] & (!\u0|clock_sel|data_out [2] & (\R_400_to_2_5_10_100_200_300MHZ|counter~67_combout ))) # (\u0|clock_sel|data_out [0] & 
// ((((\R_400_to_2_5_10_100_200_300MHZ|counter~65_combout ))) # (\u0|clock_sel|data_out [2]))) ) ) # ( \u0|clock_sel|data_out [1] & ( (!\u0|clock_sel|data_out [0] & (!\u0|clock_sel|data_out [2] & (\R_400_to_2_5_10_100_200_300MHZ|counter~68_combout ))) # 
// (\u0|clock_sel|data_out [0] & ((((\R_400_to_2_5_10_100_200_300MHZ|counter~66_combout ))) # (\u0|clock_sel|data_out [2]))) ) )

        .dataa(!\u0|clock_sel|data_out [0]),
        .datab(!\u0|clock_sel|data_out [2]),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter~68_combout ),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter~65_combout ),
        .datae(!\u0|clock_sel|data_out [1]),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter~66_combout ),
        .datag(!\R_400_to_2_5_10_100_200_300MHZ|counter~67_combout ),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|Mux1~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux1~4 .extended_lut = "on";
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux1~4 .lut_mask = 64'h195D1919195D5D5D;
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux1~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X59_Y4_N36
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~23 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~23_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|Equal2~1_combout  & ( (\R_400_to_2_5_10_100_200_300MHZ|Add0~9_sumout  & ((!\R_400_to_2_5_10_100_200_300MHZ|counter [2]) # ((!\R_400_to_2_5_10_100_200_300MHZ|counter 
// [1] & !\R_400_to_2_5_10_100_200_300MHZ|counter [0])))) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter [1]),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|Add0~9_sumout ),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter [0]),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|Equal2~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~23_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~23 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~23 .lut_mask = 64'h000000000E0C0E0C;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~23 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X59_Y4_N42
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Mux1~0 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Mux1~0_combout  = ( !\u0|clock_sel|data_out [1] & ( (!\u0|clock_sel|data_out [2] & ((((\R_400_to_2_5_10_100_200_300MHZ|Mux1~4_combout ))))) # (\u0|clock_sel|data_out [2] & (((!\R_400_to_2_5_10_100_200_300MHZ|Mux1~4_combout  
// & ((\R_400_to_2_5_10_100_200_300MHZ|counter~23_combout ))) # (\R_400_to_2_5_10_100_200_300MHZ|Mux1~4_combout  & (\R_400_to_2_5_10_100_200_300MHZ|counter~21_combout ))))) ) ) # ( \u0|clock_sel|data_out [1] & ( ((!\u0|clock_sel|data_out [2] & 
// (((\R_400_to_2_5_10_100_200_300MHZ|Mux1~4_combout )))) # (\u0|clock_sel|data_out [2] & ((!\R_400_to_2_5_10_100_200_300MHZ|Mux1~4_combout  & (\R_400_to_2_5_10_100_200_300MHZ|counter~24_combout )) # (\R_400_to_2_5_10_100_200_300MHZ|Mux1~4_combout  & 
// ((\R_400_to_2_5_10_100_200_300MHZ|counter~22_combout )))))) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter~21_combout ),
        .datab(!\u0|clock_sel|data_out [2]),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter~24_combout ),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter~22_combout ),
        .datae(!\u0|clock_sel|data_out [1]),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|Mux1~4_combout ),
        .datag(!\R_400_to_2_5_10_100_200_300MHZ|counter~23_combout ),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|Mux1~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux1~0 .extended_lut = "on";
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux1~0 .lut_mask = 64'h03030303DDDDCCFF;
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux1~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X55_Y4_N27
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~3 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~3_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|Mux1~0_combout  & ( \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock  ) )

        .dataa(!\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock ),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|Mux1~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~3 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~3 .lut_mask = 64'h0000000055555555;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~3 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X55_Y4_N29
dffeas \R_400_to_2_5_10_100_200_300MHZ|counter[10] (
        .clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),
        .d(\R_400_to_2_5_10_100_200_300MHZ|counter~3_combout ),
        .asdata(vcc),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\R_400_to_2_5_10_100_200_300MHZ|counter [10]),
        .prn(vcc));
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[10] .is_wysiwyg = "true";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[10] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X65_Y4_N42
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~0 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  = ( !\R_400_to_2_5_10_100_200_300MHZ|counter [6] & ( (!\R_400_to_2_5_10_100_200_300MHZ|counter [10] & (!\R_400_to_2_5_10_100_200_300MHZ|counter [9] & (!\R_400_to_2_5_10_100_200_300MHZ|counter [7] & 
// !\R_400_to_2_5_10_100_200_300MHZ|counter [8]))) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter [10]),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter [9]),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [7]),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter [8]),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter [6]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~0 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~0 .lut_mask = 64'h8000800000000000;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X61_Y4_N39
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~96 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~96_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|counter [5] & ( \R_400_to_2_5_10_100_200_300MHZ|Add0~37_sumout  & ( (\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & (!\R_400_to_2_5_10_100_200_300MHZ|counter [3] 
// & !\R_400_to_2_5_10_100_200_300MHZ|counter [4])) ) ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|counter [5] & ( \R_400_to_2_5_10_100_200_300MHZ|Add0~37_sumout  & ( \R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  ) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter [3]),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [4]),
        .datad(gnd),
        .datae(!\R_400_to_2_5_10_100_200_300MHZ|counter [5]),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add0~37_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~96_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~96 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~96 .lut_mask = 64'h0000000055554040;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~96 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X59_Y4_N12
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~94 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~94_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|Add0~37_sumout  & ( (\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & \R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datab(gnd),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add0~37_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~94_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~94 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~94 .lut_mask = 64'h0000000005050505;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~94 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X65_Y4_N57
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~93 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~93_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|Add0~37_sumout  & ( (\R_400_to_2_5_10_100_200_300MHZ|counter~12_combout  & ((!\R_400_to_2_5_10_100_200_300MHZ|counter [6]) # ((!\R_400_to_2_5_10_100_200_300MHZ|counter 
// [5] & !\R_400_to_2_5_10_100_200_300MHZ|counter [4])))) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter [6]),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter [5]),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [4]),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter~12_combout ),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add0~37_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~93_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~93 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~93 .lut_mask = 64'h0000000000EA00EA;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~93 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X59_Y4_N21
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~95 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~95_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|counter [7] & ( (\R_400_to_2_5_10_100_200_300MHZ|Add0~37_sumout  & (\R_400_to_2_5_10_100_200_300MHZ|always4~0_combout  & ((!\R_400_to_2_5_10_100_200_300MHZ|counter 
// [6]) # (\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout )))) ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|counter [7] & ( (\R_400_to_2_5_10_100_200_300MHZ|Add0~37_sumout  & \R_400_to_2_5_10_100_200_300MHZ|always4~0_combout ) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|Add0~37_sumout ),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [6]),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|always4~0_combout ),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter [7]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~95_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~95 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~95 .lut_mask = 64'h0033003300310031;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~95 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X59_Y4_N54
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Mux9~4 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Mux9~4_combout  = ( !\u0|clock_sel|data_out [1] & ( (!\u0|clock_sel|data_out [0] & (!\u0|clock_sel|data_out [2] & (\R_400_to_2_5_10_100_200_300MHZ|counter~95_combout ))) # (\u0|clock_sel|data_out [0] & 
// ((((\R_400_to_2_5_10_100_200_300MHZ|counter~93_combout ))) # (\u0|clock_sel|data_out [2]))) ) ) # ( \u0|clock_sel|data_out [1] & ( (!\u0|clock_sel|data_out [0] & (!\u0|clock_sel|data_out [2] & (\R_400_to_2_5_10_100_200_300MHZ|counter~96_combout ))) # 
// (\u0|clock_sel|data_out [0] & ((((\R_400_to_2_5_10_100_200_300MHZ|counter~94_combout ))) # (\u0|clock_sel|data_out [2]))) ) )

        .dataa(!\u0|clock_sel|data_out [0]),
        .datab(!\u0|clock_sel|data_out [2]),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter~96_combout ),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter~94_combout ),
        .datae(!\u0|clock_sel|data_out [1]),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter~93_combout ),
        .datag(!\R_400_to_2_5_10_100_200_300MHZ|counter~95_combout ),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|Mux9~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux9~4 .extended_lut = "on";
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux9~4 .lut_mask = 64'h1919195D5D5D195D;
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux9~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X59_Y4_N24
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~52 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~52_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout  & ( \R_400_to_2_5_10_100_200_300MHZ|Add0~37_sumout  & ( (!\R_400_to_2_5_10_100_200_300MHZ|counter [2] & 
// (\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & ((!\R_400_to_2_5_10_100_200_300MHZ|counter [1]) # (!\R_400_to_2_5_10_100_200_300MHZ|counter [0])))) ) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter [1]),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter [0]),
        .datae(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add0~37_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~52_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~52 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~52 .lut_mask = 64'h0000000000000C08;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~52 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X59_Y4_N15
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~49 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~49_combout  = (\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & (\R_400_to_2_5_10_100_200_300MHZ|Add0~37_sumout  & (!\R_400_to_2_5_10_100_200_300MHZ|counter [2] & 
// \R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout )))

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|Add0~37_sumout ),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~49_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~49 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~49 .lut_mask = 64'h0010001000100010;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~49 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X59_Y4_N18
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~50 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~50_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & ( (\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout  & (\R_400_to_2_5_10_100_200_300MHZ|Add0~37_sumout  & 
// (!\R_400_to_2_5_10_100_200_300MHZ|counter [1] & !\R_400_to_2_5_10_100_200_300MHZ|counter [2]))) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|Add0~37_sumout ),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [1]),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~50_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~50 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~50 .lut_mask = 64'h0000000010001000;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~50 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X60_Y4_N42
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~51 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~51_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout  & ( \R_400_to_2_5_10_100_200_300MHZ|Add0~37_sumout  & ( (\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & 
// ((!\R_400_to_2_5_10_100_200_300MHZ|counter [2]) # ((!\R_400_to_2_5_10_100_200_300MHZ|counter [0] & !\R_400_to_2_5_10_100_200_300MHZ|counter [1])))) ) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [0]),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter [1]),
        .datae(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add0~37_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~51_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~51 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~51 .lut_mask = 64'h0000000000003222;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~51 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X59_Y4_N0
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Mux9~0 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Mux9~0_combout  = ( !\u0|clock_sel|data_out [1] & ( (!\R_400_to_2_5_10_100_200_300MHZ|Mux9~4_combout  & (\u0|clock_sel|data_out [2] & (\R_400_to_2_5_10_100_200_300MHZ|counter~51_combout ))) # 
// (\R_400_to_2_5_10_100_200_300MHZ|Mux9~4_combout  & ((!\u0|clock_sel|data_out [2]) # (((\R_400_to_2_5_10_100_200_300MHZ|counter~49_combout ))))) ) ) # ( \u0|clock_sel|data_out [1] & ( (!\R_400_to_2_5_10_100_200_300MHZ|Mux9~4_combout  & 
// (\u0|clock_sel|data_out [2] & (\R_400_to_2_5_10_100_200_300MHZ|counter~52_combout ))) # (\R_400_to_2_5_10_100_200_300MHZ|Mux9~4_combout  & ((!\u0|clock_sel|data_out [2]) # (((\R_400_to_2_5_10_100_200_300MHZ|counter~50_combout ))))) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|Mux9~4_combout ),
        .datab(!\u0|clock_sel|data_out [2]),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter~52_combout ),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter~49_combout ),
        .datae(!\u0|clock_sel|data_out [1]),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter~50_combout ),
        .datag(!\R_400_to_2_5_10_100_200_300MHZ|counter~51_combout ),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|Mux9~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux9~0 .extended_lut = "on";
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux9~0 .lut_mask = 64'h4657464646575757;
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux9~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X60_Y4_N48
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~10 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~10_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|Mux9~0_combout  & ( \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock  ) )

        .dataa(!\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock ),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|Mux9~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~10_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~10 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~10 .lut_mask = 64'h0000000055555555;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~10 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X60_Y4_N50
dffeas \R_400_to_2_5_10_100_200_300MHZ|counter[2] (
        .clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),
        .d(\R_400_to_2_5_10_100_200_300MHZ|counter~10_combout ),
        .asdata(vcc),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
        .prn(vcc));
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[2] .is_wysiwyg = "true";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[2] .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X60_Y4_N27
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~38 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~38_combout  = ( !\R_400_to_2_5_10_100_200_300MHZ|counter [1] & ( (!\R_400_to_2_5_10_100_200_300MHZ|counter [2] & (\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & (\R_400_to_2_5_10_100_200_300MHZ|Add0~25_sumout  
// & \R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ))) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|Add0~25_sumout ),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~38_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~38 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~38 .lut_mask = 64'h0002000200000000;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~38 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X63_Y4_N0
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~37 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~37_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout  & ( !\R_400_to_2_5_10_100_200_300MHZ|counter [2] & ( (\R_400_to_2_5_10_100_200_300MHZ|Add0~25_sumout  & 
// \R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ) ) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|Add0~25_sumout ),
        .datab(gnd),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datad(gnd),
        .datae(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~37_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~37 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~37 .lut_mask = 64'h0000050500000000;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~37 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X60_Y4_N3
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~40 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~40_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout  & ( \R_400_to_2_5_10_100_200_300MHZ|Add0~25_sumout  & ( (!\R_400_to_2_5_10_100_200_300MHZ|counter [2] & 
// (\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & ((!\R_400_to_2_5_10_100_200_300MHZ|counter [1]) # (!\R_400_to_2_5_10_100_200_300MHZ|counter [0])))) ) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [1]),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter [0]),
        .datae(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add0~25_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~40_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~40 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~40 .lut_mask = 64'h0000000000002220;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~40 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X63_Y4_N30
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~84 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~84_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|counter [5] & ( (!\R_400_to_2_5_10_100_200_300MHZ|counter [4] & (\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & (\R_400_to_2_5_10_100_200_300MHZ|Add0~25_sumout  
// & !\R_400_to_2_5_10_100_200_300MHZ|counter [3]))) ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|counter [5] & ( (\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & \R_400_to_2_5_10_100_200_300MHZ|Add0~25_sumout ) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter [4]),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|Add0~25_sumout ),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter [3]),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~84_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~84 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~84 .lut_mask = 64'h0303030302000200;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~84 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X63_Y4_N57
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~81 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~81_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|counter [6] & ( (!\R_400_to_2_5_10_100_200_300MHZ|counter [4] & (!\R_400_to_2_5_10_100_200_300MHZ|counter [5] & (\R_400_to_2_5_10_100_200_300MHZ|counter~12_combout  & 
// \R_400_to_2_5_10_100_200_300MHZ|Add0~25_sumout ))) ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|counter [6] & ( (\R_400_to_2_5_10_100_200_300MHZ|counter~12_combout  & \R_400_to_2_5_10_100_200_300MHZ|Add0~25_sumout ) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter [4]),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter [5]),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter~12_combout ),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|Add0~25_sumout ),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter [6]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~81_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~81 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~81 .lut_mask = 64'h000F000F00080008;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~81 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X64_Y4_N18
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~82 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~82_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & ( (\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout  & \R_400_to_2_5_10_100_200_300MHZ|Add0~25_sumout ) ) )

        .dataa(gnd),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|Add0~25_sumout ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~82_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~82 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~82 .lut_mask = 64'h0000000003030303;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~82 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X64_Y4_N21
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~83 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~83_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|counter [7] & ( (\R_400_to_2_5_10_100_200_300MHZ|Add0~25_sumout  & (\R_400_to_2_5_10_100_200_300MHZ|always4~0_combout  & ((!\R_400_to_2_5_10_100_200_300MHZ|counter 
// [6]) # (\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout )))) ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|counter [7] & ( (\R_400_to_2_5_10_100_200_300MHZ|Add0~25_sumout  & \R_400_to_2_5_10_100_200_300MHZ|always4~0_combout ) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|Add0~25_sumout ),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [6]),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|always4~0_combout ),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter [7]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~83_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~83 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~83 .lut_mask = 64'h0055005500510051;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~83 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X64_Y4_N30
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Mux8~4 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Mux8~4_combout  = ( !\u0|clock_sel|data_out [1] & ( (!\u0|clock_sel|data_out [2] & ((!\u0|clock_sel|data_out [0] & (\R_400_to_2_5_10_100_200_300MHZ|counter~83_combout )) # (\u0|clock_sel|data_out [0] & 
// (((\R_400_to_2_5_10_100_200_300MHZ|counter~81_combout )))))) # (\u0|clock_sel|data_out [2] & (\u0|clock_sel|data_out [0])) ) ) # ( \u0|clock_sel|data_out [1] & ( (!\u0|clock_sel|data_out [2] & ((!\u0|clock_sel|data_out [0] & 
// (\R_400_to_2_5_10_100_200_300MHZ|counter~84_combout )) # (\u0|clock_sel|data_out [0] & (((\R_400_to_2_5_10_100_200_300MHZ|counter~82_combout )))))) # (\u0|clock_sel|data_out [2] & (\u0|clock_sel|data_out [0])) ) )

        .dataa(!\u0|clock_sel|data_out [2]),
        .datab(!\u0|clock_sel|data_out [0]),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter~84_combout ),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter~81_combout ),
        .datae(!\u0|clock_sel|data_out [1]),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter~82_combout ),
        .datag(!\R_400_to_2_5_10_100_200_300MHZ|counter~83_combout ),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|Mux8~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux8~4 .extended_lut = "on";
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux8~4 .lut_mask = 64'h193B1919193B3B3B;
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux8~4 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X60_Y4_N54
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~39 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~39_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout  & ( \R_400_to_2_5_10_100_200_300MHZ|Add0~25_sumout  & ( (\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & 
// ((!\R_400_to_2_5_10_100_200_300MHZ|counter [2]) # ((!\R_400_to_2_5_10_100_200_300MHZ|counter [1] & !\R_400_to_2_5_10_100_200_300MHZ|counter [0])))) ) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter [1]),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [0]),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datae(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add0~25_sumout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~39_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~39 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~39 .lut_mask = 64'h00000000000000EA;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~39 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X60_Y4_N30
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Mux8~0 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Mux8~0_combout  = ( !\u0|clock_sel|data_out [1] & ( ((!\u0|clock_sel|data_out [2] & (((\R_400_to_2_5_10_100_200_300MHZ|Mux8~4_combout )))) # (\u0|clock_sel|data_out [2] & ((!\R_400_to_2_5_10_100_200_300MHZ|Mux8~4_combout  & 
// ((\R_400_to_2_5_10_100_200_300MHZ|counter~39_combout ))) # (\R_400_to_2_5_10_100_200_300MHZ|Mux8~4_combout  & (\R_400_to_2_5_10_100_200_300MHZ|counter~37_combout ))))) ) ) # ( \u0|clock_sel|data_out [1] & ( ((!\u0|clock_sel|data_out [2] & 
// (((\R_400_to_2_5_10_100_200_300MHZ|Mux8~4_combout )))) # (\u0|clock_sel|data_out [2] & ((!\R_400_to_2_5_10_100_200_300MHZ|Mux8~4_combout  & ((\R_400_to_2_5_10_100_200_300MHZ|counter~40_combout ))) # (\R_400_to_2_5_10_100_200_300MHZ|Mux8~4_combout  & 
// (\R_400_to_2_5_10_100_200_300MHZ|counter~38_combout ))))) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter~38_combout ),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter~37_combout ),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter~40_combout ),
        .datad(!\u0|clock_sel|data_out [2]),
        .datae(!\u0|clock_sel|data_out [1]),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|Mux8~4_combout ),
        .datag(!\R_400_to_2_5_10_100_200_300MHZ|counter~39_combout ),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|Mux8~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux8~0 .extended_lut = "on";
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux8~0 .lut_mask = 64'h000F000FFF33FF55;
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux8~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X60_Y4_N24
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~7 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~7_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|Mux8~0_combout  & ( \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|Mux8~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|counter~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~7 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~7 .lut_mask = 64'h000000000F0F0F0F;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~7 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X60_Y4_N26
dffeas \R_400_to_2_5_10_100_200_300MHZ|counter[3] (
        .clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),
        .d(\R_400_to_2_5_10_100_200_300MHZ|counter~7_combout ),
        .asdata(vcc),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\R_400_to_2_5_10_100_200_300MHZ|counter [3]),
        .prn(vcc));
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[3] .is_wysiwyg = "true";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[3] .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X64_Y3_N45
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~1 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~1_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|counter [2] & ( \R_400_to_2_5_10_100_200_300MHZ|counter [4] ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|counter [2] & ( \R_400_to_2_5_10_100_200_300MHZ|counter [4] ) 
// ) # ( \R_400_to_2_5_10_100_200_300MHZ|counter [2] & ( !\R_400_to_2_5_10_100_200_300MHZ|counter [4] ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|counter [2] & ( !\R_400_to_2_5_10_100_200_300MHZ|counter [4] & ( 
// ((!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ) # ((!\R_400_to_2_5_10_100_200_300MHZ|counter [1]) # (\R_400_to_2_5_10_100_200_300MHZ|counter [5]))) # (\R_400_to_2_5_10_100_200_300MHZ|counter [3]) ) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter [3]),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [5]),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter [1]),
        .datae(!\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter [4]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~1_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~1 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~1 .lut_mask = 64'hFFDFFFFFFFFFFFFF;
defparam \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~1 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X63_Y4_N45
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~4 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~4_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|counter [5] & ( (!\R_400_to_2_5_10_100_200_300MHZ|counter~12_combout ) # (((!\R_400_to_2_5_10_100_200_300MHZ|counter [4] & 
// !\R_400_to_2_5_10_100_200_300MHZ|counter [3])) # (\R_400_to_2_5_10_100_200_300MHZ|counter [6])) ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|counter [5] & ( ((!\R_400_to_2_5_10_100_200_300MHZ|counter~12_combout ) # (!\R_400_to_2_5_10_100_200_300MHZ|counter 
// [6])) # (\R_400_to_2_5_10_100_200_300MHZ|counter [4]) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter [4]),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter~12_combout ),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [3]),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter [6]),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter [5]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~4 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~4 .lut_mask = 64'hFFDDFFDDECFFECFF;
defparam \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X63_Y4_N51
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~7 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~7_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|counter [3] & ( \R_400_to_2_5_10_100_200_300MHZ|counter [2] & ( (!\R_400_to_2_5_10_100_200_300MHZ|counter [4]) # 
// (((!\R_400_to_2_5_10_100_200_300MHZ|counter~12_combout ) # (\R_400_to_2_5_10_100_200_300MHZ|counter [6])) # (\R_400_to_2_5_10_100_200_300MHZ|counter [5])) ) ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|counter [3] & ( \R_400_to_2_5_10_100_200_300MHZ|counter 
// [2] & ( (!\R_400_to_2_5_10_100_200_300MHZ|counter~12_combout ) # ((!\R_400_to_2_5_10_100_200_300MHZ|counter [4] $ (\R_400_to_2_5_10_100_200_300MHZ|counter [5])) # (\R_400_to_2_5_10_100_200_300MHZ|counter [6])) ) ) ) # ( 
// \R_400_to_2_5_10_100_200_300MHZ|counter [3] & ( !\R_400_to_2_5_10_100_200_300MHZ|counter [2] & ( (!\R_400_to_2_5_10_100_200_300MHZ|counter [4]) # (((!\R_400_to_2_5_10_100_200_300MHZ|counter~12_combout ) # (\R_400_to_2_5_10_100_200_300MHZ|counter [6])) # 
// (\R_400_to_2_5_10_100_200_300MHZ|counter [5])) ) ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|counter [3] & ( !\R_400_to_2_5_10_100_200_300MHZ|counter [2] & ( ((!\R_400_to_2_5_10_100_200_300MHZ|counter [5]) # 
// ((!\R_400_to_2_5_10_100_200_300MHZ|counter~12_combout ) # (\R_400_to_2_5_10_100_200_300MHZ|counter [6]))) # (\R_400_to_2_5_10_100_200_300MHZ|counter [4]) ) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter [4]),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter [5]),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter~12_combout ),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter [6]),
        .datae(!\R_400_to_2_5_10_100_200_300MHZ|counter [3]),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~7_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~7 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~7 .lut_mask = 64'hFDFFFBFFF9FFFBFF;
defparam \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~7 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X64_Y3_N12
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~5 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~5_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  & ( (((!\R_400_to_2_5_10_100_200_300MHZ|counter [2]) # (\R_400_to_2_5_10_100_200_300MHZ|counter [3])) # 
// (\R_400_to_2_5_10_100_200_300MHZ|counter [5])) # (\R_400_to_2_5_10_100_200_300MHZ|counter [4]) ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout  )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter [4]),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter [5]),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [3]),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~5_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~5 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~5 .lut_mask = 64'hFFFFFFFFFF7FFF7F;
defparam \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~5 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X63_Y4_N12
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|LessThan0~0 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|LessThan0~0_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|counter [3] & ( \R_400_to_2_5_10_100_200_300MHZ|counter [2] & ( (\R_400_to_2_5_10_100_200_300MHZ|counter [5] & \R_400_to_2_5_10_100_200_300MHZ|counter [6]) ) ) ) # ( 
// !\R_400_to_2_5_10_100_200_300MHZ|counter [3] & ( \R_400_to_2_5_10_100_200_300MHZ|counter [2] & ( (\R_400_to_2_5_10_100_200_300MHZ|counter [5] & \R_400_to_2_5_10_100_200_300MHZ|counter [6]) ) ) ) # ( \R_400_to_2_5_10_100_200_300MHZ|counter [3] & ( 
// !\R_400_to_2_5_10_100_200_300MHZ|counter [2] & ( (\R_400_to_2_5_10_100_200_300MHZ|counter [5] & \R_400_to_2_5_10_100_200_300MHZ|counter [6]) ) ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|counter [3] & ( !\R_400_to_2_5_10_100_200_300MHZ|counter [2] & ( 
// (\R_400_to_2_5_10_100_200_300MHZ|counter [4] & (\R_400_to_2_5_10_100_200_300MHZ|counter [5] & \R_400_to_2_5_10_100_200_300MHZ|counter [6])) ) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter [4]),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter [5]),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [6]),
        .datad(gnd),
        .datae(!\R_400_to_2_5_10_100_200_300MHZ|counter [3]),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|LessThan0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|LessThan0~0 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|LessThan0~0 .lut_mask = 64'h0101030303030303;
defparam \R_400_to_2_5_10_100_200_300MHZ|LessThan0~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X64_Y4_N36
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~6 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~6_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|counter [6] & ( \R_400_to_2_5_10_100_200_300MHZ|counter [7] & ( (!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ) # 
// (!\R_400_to_2_5_10_100_200_300MHZ|always4~0_combout ) ) ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|counter [6] & ( \R_400_to_2_5_10_100_200_300MHZ|counter [7] & ( !\R_400_to_2_5_10_100_200_300MHZ|always4~0_combout  ) ) ) # ( 
// \R_400_to_2_5_10_100_200_300MHZ|counter [6] & ( !\R_400_to_2_5_10_100_200_300MHZ|counter [7] & ( (!\R_400_to_2_5_10_100_200_300MHZ|LessThan0~0_combout ) # (!\R_400_to_2_5_10_100_200_300MHZ|always4~0_combout ) ) ) ) # ( 
// !\R_400_to_2_5_10_100_200_300MHZ|counter [6] & ( !\R_400_to_2_5_10_100_200_300MHZ|counter [7] & ( (!\R_400_to_2_5_10_100_200_300MHZ|LessThan0~0_combout ) # (!\R_400_to_2_5_10_100_200_300MHZ|always4~0_combout ) ) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|LessThan0~0_combout ),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|always4~0_combout ),
        .datad(gnd),
        .datae(!\R_400_to_2_5_10_100_200_300MHZ|counter [6]),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter [7]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~6_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~6 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~6 .lut_mask = 64'hFAFAFAFAF0F0FCFC;
defparam \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~6 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X63_Y3_N6
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Mux0~4 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Mux0~4_combout  = ( !\u0|clock_sel|data_out [1] & ( (!\u0|clock_sel|data_out [0] & (((\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~6_combout  & ((!\u0|clock_sel|data_out [2])))))) # (\u0|clock_sel|data_out [0] & 
// ((((\u0|clock_sel|data_out [2]))) # (\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~4_combout ))) ) ) # ( \u0|clock_sel|data_out [1] & ( ((!\u0|clock_sel|data_out [0] & (\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~7_combout  & ((!\u0|clock_sel|data_out 
// [2])))) # (\u0|clock_sel|data_out [0] & (((\u0|clock_sel|data_out [2]) # (\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~5_combout ))))) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~4_combout ),
        .datab(!\u0|clock_sel|data_out [0]),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~7_combout ),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~5_combout ),
        .datae(!\u0|clock_sel|data_out [1]),
        .dataf(!\u0|clock_sel|data_out [2]),
        .datag(!\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~6_combout ),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|Mux0~4_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux0~4 .extended_lut = "on";
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux0~4 .lut_mask = 64'h1D1D0C3F33333333;
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux0~4 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X63_Y3_N0
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~3 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~3_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|counter [1] & ( (!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ) # ((!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ) # 
// ((\R_400_to_2_5_10_100_200_300MHZ|counter [2]) # (\R_400_to_2_5_10_100_200_300MHZ|counter [0]))) ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|counter [1] )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [0]),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter [1]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~3_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~3 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~3 .lut_mask = 64'hFFFFFFFFEFFFEFFF;
defparam \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~3 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X63_Y3_N27
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Equal2~0 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Equal2~0_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|counter [0] & ( (!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ) # ((!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ) # 
// ((\R_400_to_2_5_10_100_200_300MHZ|counter [1]) # (\R_400_to_2_5_10_100_200_300MHZ|counter [2]))) ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|counter [0] )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter [1]),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|Equal2~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Equal2~0 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|Equal2~0 .lut_mask = 64'hFFFFFFFFEFFFEFFF;
defparam \R_400_to_2_5_10_100_200_300MHZ|Equal2~0 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X63_Y3_N3
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~2 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~2_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|counter [0] & ( (!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ) # ((!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ) # 
// ((!\R_400_to_2_5_10_100_200_300MHZ|counter [1]) # (\R_400_to_2_5_10_100_200_300MHZ|counter [2]))) ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|counter [0] & ( (!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ) # 
// ((!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ) # (!\R_400_to_2_5_10_100_200_300MHZ|counter [1] $ (\R_400_to_2_5_10_100_200_300MHZ|counter [2]))) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [1]),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter [0]),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~2_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~2 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~2 .lut_mask = 64'hFEEFFEEFFEFFFEFF;
defparam \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~2 .shared_arith = "off";
// synopsys translate_on

// Location: LABCELL_X63_Y3_N30
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Mux0~0 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Mux0~0_combout  = ( !\u0|clock_sel|data_out [1] & ( (!\R_400_to_2_5_10_100_200_300MHZ|Mux0~4_combout  & (((\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~2_combout  & ((\u0|clock_sel|data_out [2])))))) # 
// (\R_400_to_2_5_10_100_200_300MHZ|Mux0~4_combout  & ((((!\u0|clock_sel|data_out [2]))) # (\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~1_combout ))) ) ) # ( \u0|clock_sel|data_out [1] & ( ((!\R_400_to_2_5_10_100_200_300MHZ|Mux0~4_combout  & 
// (\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~3_combout  & ((\u0|clock_sel|data_out [2])))) # (\R_400_to_2_5_10_100_200_300MHZ|Mux0~4_combout  & (((!\u0|clock_sel|data_out [2]) # (\R_400_to_2_5_10_100_200_300MHZ|Equal2~0_combout ))))) ) )

        .dataa(!\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~1_combout ),
        .datab(!\R_400_to_2_5_10_100_200_300MHZ|Mux0~4_combout ),
        .datac(!\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~3_combout ),
        .datad(!\R_400_to_2_5_10_100_200_300MHZ|Equal2~0_combout ),
        .datae(!\u0|clock_sel|data_out [1]),
        .dataf(!\u0|clock_sel|data_out [2]),
        .datag(!\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~2_combout ),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|Mux0~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux0~0 .extended_lut = "on";
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux0~0 .lut_mask = 64'h333333331D1D0C3F;
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux0~0 .shared_arith = "off";
// synopsys translate_on

// Location: MLABCELL_X55_Y4_N42
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~0 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~0_combout  = ( \R_400_to_2_5_10_100_200_300MHZ|Mux0~0_combout  & ( \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock  ) )

        .dataa(gnd),
        .datab(gnd),
        .datac(!\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock ),
        .datad(gnd),
        .datae(gnd),
        .dataf(!\R_400_to_2_5_10_100_200_300MHZ|Mux0~0_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~0 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~0 .lut_mask = 64'h000000000F0F0F0F;
defparam \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X55_Y4_N44
dffeas \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i (
        .clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),
        .d(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~0_combout ),
        .asdata(vcc),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .prn(vcc));
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i .is_wysiwyg = "true";
defparam \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i .power_up = "low";
// synopsys translate_on

// Location: FF_X53_Y6_N41
dffeas \A_SPW_TOP|SPW|TX|last_tx_sout (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|tx_sout~0_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|last_tx_sout~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_tx_sout .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|last_tx_sout .power_up = "low";
// synopsys translate_on

// Location: FF_X53_Y6_N37
dffeas \A_SPW_TOP|SPW|TX|last_tx_dout (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|tx_dout~q ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|last_tx_dout~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_tx_dout .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|last_tx_dout .power_up = "low";
// synopsys translate_on

// Location: LABCELL_X53_Y6_N36
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_sout~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_sout~0_combout  = ( \A_SPW_TOP|SPW|TX|last_tx_dout~q  & ( !\A_SPW_TOP|SPW|TX|last_tx_sout~q  $ (!\A_SPW_TOP|SPW|TX|tx_dout~q ) ) ) # ( !\A_SPW_TOP|SPW|TX|last_tx_dout~q  & ( !\A_SPW_TOP|SPW|TX|last_tx_sout~q  $ 
// (\A_SPW_TOP|SPW|TX|tx_dout~q ) ) )

        .dataa(gnd),
        .datab(!\A_SPW_TOP|SPW|TX|last_tx_sout~q ),
        .datac(gnd),
        .datad(!\A_SPW_TOP|SPW|TX|tx_dout~q ),
        .datae(gnd),
        .dataf(!\A_SPW_TOP|SPW|TX|last_tx_dout~q ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\A_SPW_TOP|SPW|TX|tx_sout~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_sout~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_sout~0 .lut_mask = 64'hCC33CC3333CC33CC;
defparam \A_SPW_TOP|SPW|TX|tx_sout~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X53_Y6_N2
dffeas \A_SPW_TOP|SPW|TX|tx_sout_e (
        .clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
        .d(gnd),
        .asdata(\A_SPW_TOP|SPW|TX|tx_sout~0_combout ),
        .clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
        .aload(gnd),
        .sclr(gnd),
        .sload(vcc),
        .ena(\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~q ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\A_SPW_TOP|SPW|TX|tx_sout_e~q ),
        .prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_sout_e .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|tx_sout_e .power_up = "low";
// synopsys translate_on

// Location: MLABCELL_X47_Y1_N6
cyclonev_lcell_comb \db_system_spwulight_b|PB_down~0 (
// Equation(s):
// \db_system_spwulight_b|PB_down~0_combout  = ( \db_system_spwulight_b|PB_down~q  & ( \db_system_spwulight_b|LessThan0~1_combout  & ( !\KEY[1]~input_o  ) ) ) # ( !\db_system_spwulight_b|PB_down~q  & ( \db_system_spwulight_b|LessThan0~1_combout  & ( 
// !\KEY[1]~input_o  ) ) ) # ( \db_system_spwulight_b|PB_down~q  & ( !\db_system_spwulight_b|LessThan0~1_combout  & ( !\KEY[1]~input_o  ) ) ) # ( !\db_system_spwulight_b|PB_down~q  & ( !\db_system_spwulight_b|LessThan0~1_combout  & ( (!\KEY[1]~input_o  & 
// (((!\db_system_spwulight_b|LessThan0~0_combout ) # (\db_system_spwulight_b|counter [14])) # (\db_system_spwulight_b|counter [15]))) ) ) )

        .dataa(!\db_system_spwulight_b|counter [15]),
        .datab(!\db_system_spwulight_b|counter [14]),
        .datac(!\KEY[1]~input_o ),
        .datad(!\db_system_spwulight_b|LessThan0~0_combout ),
        .datae(!\db_system_spwulight_b|PB_down~q ),
        .dataf(!\db_system_spwulight_b|LessThan0~1_combout ),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\db_system_spwulight_b|PB_down~0_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|PB_down~0 .extended_lut = "off";
defparam \db_system_spwulight_b|PB_down~0 .lut_mask = 64'hF070F0F0F0F0F0F0;
defparam \db_system_spwulight_b|PB_down~0 .shared_arith = "off";
// synopsys translate_on

// Location: FF_X47_Y1_N7
dffeas \db_system_spwulight_b|PB_down (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\db_system_spwulight_b|PB_down~0_combout ),
        .asdata(vcc),
        .clrn(vcc),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(vcc),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\db_system_spwulight_b|PB_down~q ),
        .prn(vcc));
// synopsys translate_off
defparam \db_system_spwulight_b|PB_down .is_wysiwyg = "true";
defparam \db_system_spwulight_b|PB_down .power_up = "low";
// synopsys translate_on

// Location: DDIOOUTCELL_X68_Y12_N30
dffeas \u0|led_pio_test|data_out[0] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [0]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|led_pio_test|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|led_pio_test|data_out [0]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|led_pio_test|data_out[0] .is_wysiwyg = "true";
defparam \u0|led_pio_test|data_out[0] .power_up = "low";
// synopsys translate_on

// Location: DDIOOUTCELL_X68_Y13_N47
dffeas \u0|led_pio_test|data_out[1] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [1]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|led_pio_test|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|led_pio_test|data_out [1]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|led_pio_test|data_out[1] .is_wysiwyg = "true";
defparam \u0|led_pio_test|data_out[1] .power_up = "low";
// synopsys translate_on

// Location: DDIOOUTCELL_X68_Y13_N13
dffeas \u0|led_pio_test|data_out[2] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [2]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|led_pio_test|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|led_pio_test|data_out [2]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|led_pio_test|data_out[2] .is_wysiwyg = "true";
defparam \u0|led_pio_test|data_out[2] .power_up = "low";
// synopsys translate_on

// Location: DDIOOUTCELL_X68_Y13_N30
dffeas \u0|led_pio_test|data_out[3] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [3]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|led_pio_test|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|led_pio_test|data_out [3]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|led_pio_test|data_out[3] .is_wysiwyg = "true";
defparam \u0|led_pio_test|data_out[3] .power_up = "low";
// synopsys translate_on

// Location: DDIOOUTCELL_X68_Y10_N87
dffeas \u0|led_pio_test|data_out[4] (
        .clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
        .d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [4]),
        .asdata(vcc),
        .clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
        .aload(gnd),
        .sclr(gnd),
        .sload(gnd),
        .ena(\u0|led_pio_test|always0~0_combout ),
        .devclrn(devclrn),
        .devpor(devpor),
        .q(\u0|led_pio_test|data_out [4]),
        .prn(vcc));
// synopsys translate_off
defparam \u0|led_pio_test|data_out[4] .is_wysiwyg = "true";
defparam \u0|led_pio_test|data_out[4] .power_up = "low";
// synopsys translate_on

// Location: HPSINTERFACEFPGA2HPS_X32_Y23_N111
cyclonev_hps_interface_fpga2hps \u0|hps_0|fpga_interfaces|fpga2hps (
        .arvalid(gnd),
        .awvalid(gnd),
        .bready(gnd),
        .clk(gnd),
        .rready(gnd),
        .wlast(gnd),
        .wvalid(gnd),
        .araddr(32'b00000000000000000000000000000000),
        .arburst(2'b00),
        .arcache(4'b0000),
        .arid(8'b00000000),
        .arlen(4'b0000),
        .arlock(2'b00),
        .arprot(3'b000),
        .arsize(3'b000),
        .aruser(5'b00000),
        .awaddr(32'b00000000000000000000000000000000),
        .awburst(2'b00),
        .awcache(4'b0000),
        .awid(8'b00000000),
        .awlen(4'b0000),
        .awlock(2'b00),
        .awprot(3'b000),
        .awsize(3'b000),
        .awuser(5'b00000),
        .port_size_config({vcc,vcc}),
        .wdata(128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000),
        .wid(8'b00000000),
        .wstrb(16'b0000000000000000),
        .arready(\u0|hps_0|fpga_interfaces|fpga2hps~arready ),
        .awready(),
        .bvalid(),
        .rlast(),
        .rvalid(),
        .wready(),
        .bid(),
        .bresp(),
        .rdata(),
        .rid(),
        .rresp());
// synopsys translate_off
defparam \u0|hps_0|fpga_interfaces|fpga2hps .data_width = 32;
// synopsys translate_on

// Location: HPSINTERFACEFPGA2SDRAM_X32_Y27_N111
cyclonev_hps_interface_fpga2sdram \u0|hps_0|fpga_interfaces|f2sdram (
        .cmd_port_clk_0(gnd),
        .cmd_port_clk_1(gnd),
        .cmd_port_clk_2(gnd),
        .cmd_port_clk_3(gnd),
        .cmd_port_clk_4(gnd),
        .cmd_port_clk_5(gnd),
        .cmd_valid_0(gnd),
        .cmd_valid_1(gnd),
        .cmd_valid_2(gnd),
        .cmd_valid_3(gnd),
        .cmd_valid_4(gnd),
        .cmd_valid_5(gnd),
        .rd_clk_0(gnd),
        .rd_clk_1(gnd),
        .rd_clk_2(gnd),
        .rd_clk_3(gnd),
        .rd_ready_0(gnd),
        .rd_ready_1(gnd),
        .rd_ready_2(gnd),
        .rd_ready_3(gnd),
        .wr_clk_0(gnd),
        .wr_clk_1(gnd),
        .wr_clk_2(gnd),
        .wr_clk_3(gnd),
        .wr_valid_0(gnd),
        .wr_valid_1(gnd),
        .wr_valid_2(gnd),
        .wr_valid_3(gnd),
        .wrack_ready_0(gnd),
        .wrack_ready_1(gnd),
        .wrack_ready_2(gnd),
        .wrack_ready_3(gnd),
        .wrack_ready_4(gnd),
        .wrack_ready_5(gnd),
        .cfg_axi_mm_select({gnd,gnd,gnd,gnd,gnd,gnd}),
        .cfg_cport_rfifo_map({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
        .cfg_cport_type({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
        .cfg_cport_wfifo_map({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
        .cfg_port_width({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
        .cfg_rfifo_cport_map({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
        .cfg_wfifo_cport_map({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
        .cmd_data_0(60'b000000000000000000000000000000000000000000000000000000000000),
        .cmd_data_1(60'b000000000000000000000000000000000000000000000000000000000000),
        .cmd_data_2(60'b000000000000000000000000000000000000000000000000000000000000),
        .cmd_data_3(60'b000000000000000000000000000000000000000000000000000000000000),
        .cmd_data_4(60'b000000000000000000000000000000000000000000000000000000000000),
        .cmd_data_5(60'b000000000000000000000000000000000000000000000000000000000000),
        .wr_data_0(90'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000),
        .wr_data_1(90'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000),
        .wr_data_2(90'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000),
        .wr_data_3(90'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000),
        .cmd_ready_0(),
        .cmd_ready_1(),
        .cmd_ready_2(),
        .cmd_ready_3(),
        .cmd_ready_4(),
        .cmd_ready_5(),
        .rd_valid_0(),
        .rd_valid_1(),
        .rd_valid_2(),
        .rd_valid_3(),
        .wr_ready_0(),
        .wr_ready_1(),
        .wr_ready_2(),
        .wr_ready_3(),
        .wrack_valid_0(),
        .wrack_valid_1(),
        .wrack_valid_2(),
        .wrack_valid_3(),
        .wrack_valid_4(),
        .wrack_valid_5(),
        .bonding_out_1(\u0|hps_0|fpga_interfaces|f2sdram_BONDING_OUT_1_bus ),
        .bonding_out_2(),
        .rd_data_0(),
        .rd_data_1(),
        .rd_data_2(),
        .rd_data_3(),
        .wrack_data_0(),
        .wrack_data_1(),
        .wrack_data_2(),
        .wrack_data_3(),
        .wrack_data_4(),
        .wrack_data_5());

// Location: HPSINTERFACETPIUTRACE_X32_Y18_N111
cyclonev_hps_interface_tpiu_trace \u0|hps_0|fpga_interfaces|tpiu (
        .traceclk_ctl(vcc),
        .traceclkin(gnd),
        .traceclk(),
        .trace_data(\u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus ));

// Location: HPSINTERFACEBOOTFROMFPGA_X32_Y46_N111
cyclonev_hps_interface_boot_from_fpga \u0|hps_0|fpga_interfaces|boot_from_fpga (
        .boot_from_fpga_on_failure(gnd),
        .boot_from_fpga_ready(gnd),
        .bsel_en(gnd),
        .csel_en(gnd),
        .bsel({gnd,gnd,vcc}),
        .csel({gnd,vcc}),
        .fake_dout(\u0|hps_0|fpga_interfaces|boot_from_fpga~fake_dout ));

// Location: HPSINTERFACEDBGAPB_X32_Y53_N111
cyclonev_hps_interface_dbg_apb \u0|hps_0|fpga_interfaces|debug_apb (
        .p_slv_err(gnd),
        .p_ready(gnd),
        .p_clk(gnd),
        .p_clk_en(gnd),
        .dbg_apb_disable(gnd),
        .p_rdata(32'b00000000000000000000000000000000),
        .p_addr_31(\u0|hps_0|fpga_interfaces|debug_apb~O_P_ADDR_31 ),
        .p_write(),
        .p_sel(),
        .p_enable(),
        .p_reset_n(),
        .p_addr(),
        .p_wdata());
// synopsys translate_off
defparam \u0|hps_0|fpga_interfaces|debug_apb .dummy_param = 256;
// synopsys translate_on

// Location: IOIBUF_X46_Y0_N35
cyclonev_io_ibuf \KEY[0]~input (
        .i(KEY[0]),
        .ibar(gnd),
        .dynamicterminationcontrol(gnd),
        .o(\KEY[0]~input_o ));
// synopsys translate_off
defparam \KEY[0]~input .bus_hold = "false";
defparam \KEY[0]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: MLABCELL_X3_Y12_N0
cyclonev_lcell_comb \~QUARTUS_CREATED_GND~I (
// Equation(s):

        .dataa(gnd),
        .datab(gnd),
        .datac(gnd),
        .datad(gnd),
        .datae(gnd),
        .dataf(gnd),
        .datag(gnd),
        .cin(gnd),
        .sharein(gnd),
        .combout(\~QUARTUS_CREATED_GND~I_combout ),
        .sumout(),
        .cout(),
        .shareout());
// synopsys translate_off
defparam \~QUARTUS_CREATED_GND~I .extended_lut = "off";
defparam \~QUARTUS_CREATED_GND~I .lut_mask = 64'h0000000000000000;
defparam \~QUARTUS_CREATED_GND~I .shared_arith = "off";
// synopsys translate_on


altera_pll_reconfig_tasks pll_reconfig_inst_tasks();
// synopsys translate_off
defparam pll_reconfig_inst_tasks .number_of_fplls = 1;
// synopsys translate_on

endmodule

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.